CMSIS-DAP: CMSIS-DAP Debug Unit Information

| CMSIS-DAP Version 1.2.0 (Proposal) Interface Firmware for CoreSight Debug Access Port

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CMSIS-DAP Debug Unit Information
Configure I/O Ports and Debug Unit

Provides definitions about the hardware and configuration of the Debug Unit. More...

## Macros
#define | CPU_CLOCK 100000000U
| Processor Clock of the Cortex-M MCU used in the Debug Unit. This value is used to calculate the SWD/JTAG clock speed. More...
#define | IO_PORT_WRITE_CYCLES 2U
| Number of processor cycles for I/O Port write operations. This value is used to calculate the SWD/JTAG clock speed that is generated with I/O Port write operations in the Debug Unit by a Cortex-M MCU. Most Cortex-M processors require 2 processor cycles for a I/O Port Write operation. If the Debug Unit uses a Cortex-M0+ processor with high-speed peripheral I/O only 1 processor cycle might be required. More...
#define | DAP_SWD 1
| Indicate that Serial Wire Debug (SWD) communication mode is available at the Debug Access Port. This information is returned by the command DAP_Info as part of Capabilities. More...
#define | DAP_JTAG 1
| Indicate that JTAG communication mode is available at the Debug Port. This information is returned by the command DAP_Info as part of Capabilities. More...
#define | DAP_JTAG_DEV_CNT 8U
| Configure maximum number of JTAG devices on the scan chain connected to the Debug Access Port. This setting impacts the RAM requirements of the Debug Unit. Valid range is 1 .. 255. More...
#define | DAP_DEFAULT_PORT 1U
| Default communication mode on the Debug Access Port. Used for the command DAP_Connect when Port Default mode is selected. More...
#define | DAP_DEFAULT_SWJ_CLOCK 1000000U
| Default communication speed on the Debug Access Port for SWD and JTAG mode. Used to initialize the default SWD/JTAG clock frequency. The command DAP_SWJ_Clock can be used to overwrite this default setting. More...
#define | DAP_PACKET_SIZE 64U
| Maximum Package Size for Command and Response data. This configuration settings is used to optimized the communication performance with the debugger and depends on the USB peripheral. Change setting to 1024 for High-Speed USB. More...
#define | DAP_PACKET_COUNT 64U
| Maximum Package Buffers for Command and Response data. This configuration settings is used to optimized the communication performance with the debugger and depends on the USB peripheral. For devices with limited RAM or USB buffer the setting can be reduced (valid range is 1 .. 255). Change setting to 4 for High-Speed USB. More...
#define | SWO_UART 1
| Indicate that UART Serial Wire Output (SWO) trace is available. This information is returned by the command DAP_Info as part of Capabilities. More...
#define | SWO_UART_MAX_BAUDRATE 10000000U
| Maximum SWO UART Baudrate. More...
#define | SWO_MANCHESTER 0
| Indicate that Manchester Serial Wire Output (SWO) trace is available. This information is returned by the command DAP_Info as part of Capabilities. More...
#define | SWO_BUFFER_SIZE 4096U
| SWO Trace Buffer Size. More...
#define | TARGET_DEVICE_FIXED 0
| Debug Unit is connected to fixed Target Device. The Debug Unit may be part of an evaluation board and always connected to a fixed known device. In this case a Device Vendor and Device Name string is stored which may be used by the debugger or IDE to configure device parameters. More...

## Description

Provides definitions about the hardware and configuration of the Debug Unit.

This information includes:

- Definition of Cortex-M processor parameters used in CMSIS-DAP Debug Unit.
- Debug Unit communication packet size.
- Debug Access Port communication mode (JTAG or SWD).
- Optional information about a connected Target Device (for Evaluation Boards).

## Macro Definition Documentation

#define CPU_CLOCK 100000000U

Processor Clock of the Cortex-M MCU used in the Debug Unit. This value is used to calculate the SWD/JTAG clock speed.

Specifies the CPU Clock in Hz

#define DAP_DEFAULT_PORT 1U

Default communication mode on the Debug Access Port. Used for the command DAP_Connect when Port Default mode is selected.

Default JTAG/SWJ Port Mode: 1 = SWD, 2 = JTAG.

#define DAP_DEFAULT_SWJ_CLOCK 1000000U

Default communication speed on the Debug Access Port for SWD and JTAG mode. Used to initialize the default SWD/JTAG clock frequency. The command DAP_SWJ_Clock can be used to overwrite this default setting.

Default SWD/JTAG clock frequency in Hz.

#define DAP_JTAG 1

Indicate that JTAG communication mode is available at the Debug Port. This information is returned by the command DAP_Info as part of Capabilities.

JTAG Mode: 1 = available, 0 = not available.

#define DAP_JTAG_DEV_CNT 8U

Configure maximum number of JTAG devices on the scan chain connected to the Debug Access Port. This setting impacts the RAM requirements of the Debug Unit. Valid range is 1 .. 255.

Maximum number of JTAG devices on scan chain

#define DAP_PACKET_COUNT 64U

Maximum Package Buffers for Command and Response data. This configuration settings is used to optimized the communication performance with the debugger and depends on the USB peripheral. For devices with limited RAM or USB buffer the setting can be reduced (valid range is 1 .. 255). Change setting to 4 for High-Speed USB.

Buffers: 64 = Full-Speed, 4 = High-Speed.

#define DAP_PACKET_SIZE 64U

Maximum Package Size for Command and Response data. This configuration settings is used to optimized the communication performance with the debugger and depends on the USB peripheral. Change setting to 1024 for High-Speed USB.

USB: 64 = Full-Speed, 1024 = High-Speed.

#define DAP_SWD 1

Indicate that Serial Wire Debug (SWD) communication mode is available at the Debug Access Port. This information is returned by the command DAP_Info as part of Capabilities.

SWD Mode: 1 = available, 0 = not available

#define IO_PORT_WRITE_CYCLES 2U

Number of processor cycles for I/O Port write operations. This value is used to calculate the SWD/JTAG clock speed that is generated with I/O Port write operations in the Debug Unit by a Cortex-M MCU. Most Cortex-M processors require 2 processor cycles for a I/O Port Write operation. If the Debug Unit uses a Cortex-M0+ processor with high-speed peripheral I/O only 1 processor cycle might be required.

I/O Cycles: 2=default, 1=Cortex-M0+ fast I/0

#define SWO_BUFFER_SIZE 4096U

SWO Trace Buffer Size.

SWO Trace Buffer Size in bytes (must be 2^n)

#define SWO_MANCHESTER 0

Indicate that Manchester Serial Wire Output (SWO) trace is available. This information is returned by the command DAP_Info as part of Capabilities.

SWO Manchester: 1 = available, 0 = not available

#define SWO_UART 1

Indicate that UART Serial Wire Output (SWO) trace is available. This information is returned by the command DAP_Info as part of Capabilities.

SWO UART: 1 = available, 0 = not available

#define SWO_UART_MAX_BAUDRATE 10000000U

Maximum SWO UART Baudrate.

SWO UART Maximum Baudrate in Hz

#define TARGET_DEVICE_FIXED 0

Debug Unit is connected to fixed Target Device. The Debug Unit may be part of an evaluation board and always connected to a fixed known device. In this case a Device Vendor and Device Name string is stored which may be used by the debugger or IDE to configure device parameters.

Target Device: 1 = known, 0 = unknown;