CMSIS-Driver: SAI Controls

| CMSIS-Driver Version 2.05 Peripheral Interface for Middleware and Application Code

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SAI Controls
SAI Control Codes

Specifies controls. More...

## Macros
#define | ARM_SAI_CONFIGURE_TX (0x01U)
| Configure Transmitter; arg1 and arg2 provide additional configuration. More...
#define | ARM_SAI_CONFIGURE_RX (0x02U)
| Configure Receiver; arg1 and arg2 provide additional configuration. More...
#define | ARM_SAI_CONTROL_TX (0x03U)
| Control Transmitter; arg1.0: 0=disable (default), 1=enable; arg1.1: mute. More...
#define | ARM_SAI_CONTROL_RX (0x04U)
| Control Receiver; arg1.0: 0=disable (default), 1=enable. More...
#define | ARM_SAI_MASK_SLOTS_TX (0x05U)
| Mask Transmitter slots; arg1 = mask (bit: 0=active, 1=inactive); all configured slots are active by default. More...
#define | ARM_SAI_MASK_SLOTS_RX (0x06U)
| Mask Receiver slots; arg1 = mask (bit: 0=active, 1=inactive); all configured slots are active by default. More...
#define | ARM_SAI_ABORT_SEND (0x07U)
| Abort ARM_SAI_Send. More...
#define | ARM_SAI_ABORT_RECEIVE (0x08U)
| Abort ARM_SAI_Receive. More...

## Description

Specifies controls.

## Macro Definition Documentation

#define ARM_SAI_CONFIGURE_TX (0x01U)

Configure Transmitter; arg1 and arg2 provide additional configuration.

See Also
  ARM_SAI_Control

#define ARM_SAI_CONFIGURE_RX (0x02U)

Configure Receiver; arg1 and arg2 provide additional configuration.

See Also
  ARM_SAI_Control

#define ARM_SAI_CONTROL_TX (0x03U)

Control Transmitter; arg1.0: 0=disable (default), 1=enable; arg1.1: mute.

See Also
  ARM_SAI_Control; ARM_SAI_Send

#define ARM_SAI_CONTROL_RX (0x04U)

Control Receiver; arg1.0: 0=disable (default), 1=enable.

See Also
  ARM_SAI_Control; ARM_SAI_Receive

#define ARM_SAI_MASK_SLOTS_TX (0x05U)

Mask Transmitter slots; arg1 = mask (bit: 0=active, 1=inactive); all configured slots are active by default.

See Also
  ARM_SAI_Control; ARM_SAI_Send

#define ARM_SAI_MASK_SLOTS_RX (0x06U)

Mask Receiver slots; arg1 = mask (bit: 0=active, 1=inactive); all configured slots are active by default.

See Also
  ARM_SAI_Control; ARM_SAI_Receive

#define ARM_SAI_ABORT_SEND (0x07U)

Abort ARM_SAI_Send.

See Also
  ARM_SAI_Control; ARM_SAI_Send

#define ARM_SAI_ABORT_RECEIVE (0x08U)

Abort ARM_SAI_Receive.

See Also
  ARM_SAI_Control; ARM_SAI_Receive