| MINI51DE_BSP V3.02.003 The Board Support Package for Mini51DE Series MCU

spi.c
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1/**************************************************************************/
12#include "Mini51Series.h"
39uint32_t SPI_Open(SPI_T *spi,
40 uint32_t u32MasterSlave,
41 uint32_t u32SPIMode,
42 uint32_t u32DataWidth,
43 uint32_t u32BusClock)
44{
45 uint32_t u32Pclk, u32Div;
46
47 if(u32DataWidth == 32)
48 u32DataWidth = 0;
49
50 spi->CNTRL = u32MasterSlave | (u32DataWidth << SPI_CNTRL_TX_BIT_LEN_Pos) | (u32SPIMode);
51
52 u32Pclk = CLK_GetHCLKFreq();
53
54 u32Div = 0xffff;
55 spi->SSR |= SPI_SSR_SS_LTRIG_Msk;
56
57 if(u32BusClock !=0 )
58 {
59 u32Div = (((u32Pclk / u32BusClock) + 1) >> 1) - 1;
60 if(u32Div > 0xFFFF)
61 u32Div = 0xFFFF;
62 spi->DIVIDER = (spi->DIVIDER & ~0xffff) | u32Div;
63 }
64 else
65 spi->DIVIDER = 0;
66
67 return ( u32Pclk / ((u32Div+1)*2) );
68}
69
75 void SPI_Close(SPI_T *spi)
76{
77 /* Reset SPI */
78 SYS->IPRSTC2 |= SYS_IPRSTC2_SPI_RST_Msk;
79 SYS->IPRSTC2 &= ~SYS_IPRSTC2_SPI_RST_Msk;
80}
81
87 void SPI_ClearRxFIFO(SPI_T *spi)
88{
89 spi->FIFO_CTL |= SPI_FIFO_CTL_RX_CLR_Msk;
90}
91
97 void SPI_ClearTxFIFO(SPI_T *spi)
98{
99 spi->FIFO_CTL |= SPI_FIFO_CTL_TX_CLR_Msk;
100}
101
107 void SPI_DisableAutoSS(SPI_T *spi)
108{
109 spi->SSR &= ~SPI_SSR_AUTOSS_Msk;
110}
111
119 void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel)
120{
121 spi->SSR = (spi->SSR & ~(SPI_SSR_SS_LVL_Msk | SPI_SSR_SSR_Msk)) | (u32SSPinMask | u32ActiveLevel) | SPI_SSR_AUTOSS_Msk;
122}
123
130uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock)
131{
132 uint32_t u32ClkSrc = CLK_GetHCLKFreq();
133 uint32_t u32Div;
134
135 if(u32BusClock > u32ClkSrc)
136 u32BusClock = u32ClkSrc;
137
138 if(u32BusClock != 0 )
139 {
140 u32Div = (((u32ClkSrc / u32BusClock) + 1) >> 1) - 1;
141 if(u32Div > SPI_DIVIDER_DIVIDER_Msk)
142 u32Div = SPI_DIVIDER_DIVIDER_Msk;
143 }
144 else
145 return 0;
146
147 spi->DIVIDER = (spi->DIVIDER & ~SPI_DIVIDER_DIVIDER_Msk) | u32Div;
148 return ( u32ClkSrc / ((u32Div+1)*2) );
149}
150
158 void SPI_EnableFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold)
159{
160 spi->FIFO_CTL = (spi->FIFO_CTL & ~(SPI_FIFO_CTL_TX_THRESHOLD_Msk | SPI_FIFO_CTL_RX_THRESHOLD_Msk) |
161 (u32TxThreshold << SPI_FIFO_CTL_TX_THRESHOLD_Pos) |
162 (u32RxThreshold << SPI_FIFO_CTL_RX_THRESHOLD_Pos));
163
164 spi->CNTRL |= SPI_CNTRL_FIFO_Msk;
165}
166
172 void SPI_DisableFIFO(SPI_T *spi)
173{
174 spi->CNTRL &= ~SPI_CNTRL_FIFO_Msk;
175}
176
182uint32_t SPI_GetBusClock(SPI_T *spi)
183{
184 uint32_t u32Div;
185 uint32_t u32ApbClock;
186
187 u32ApbClock = CLK_GetHCLKFreq();
188 u32Div = spi->DIVIDER & 0xff;
189 return ((u32ApbClock >> 1) / (u32Div + 1));
190}
191
202 void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask)
203{
204 if((u32Mask & SPI_IE_MASK) == SPI_IE_MASK)
205 spi->CNTRL |= SPI_CNTRL_IE_Msk;
206
207 if((u32Mask & SPI_SSTA_INTEN_MASK) == SPI_SSTA_INTEN_MASK)
208 spi->CNTRL2 |= SPI_CNTRL2_SSTA_INTEN_Msk;
209
210 if((u32Mask & SPI_FIFO_TX_INTEN_MASK) == SPI_FIFO_TX_INTEN_MASK)
211 spi->FIFO_CTL |= SPI_FIFO_CTL_TX_INTEN_Msk;
212
213 if((u32Mask & SPI_FIFO_RX_INTEN_MASK) == SPI_FIFO_RX_INTEN_MASK)
214 spi->FIFO_CTL |= SPI_FIFO_CTL_RX_INTEN_Msk;
215
216 if((u32Mask & SPI_FIFO_RXOV_INTEN_MASK) == SPI_FIFO_RXOV_INTEN_MASK)
217 spi->FIFO_CTL |= SPI_FIFO_CTL_RXOV_INTEN_Msk;
218
219 if((u32Mask & SPI_FIFO_TIMEOUT_INTEN_MASK) == SPI_FIFO_TIMEOUT_INTEN_MASK)
220 spi->FIFO_CTL |= SPI_FIFO_CTL_TIMEOUT_INTEN_Msk;
221}
222
233 void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask)
234{
235 if((u32Mask & SPI_IE_MASK) == SPI_IE_MASK)
236 spi->CNTRL &= ~SPI_CNTRL_IE_Msk;
237
238 if((u32Mask & SPI_SSTA_INTEN_MASK) == SPI_SSTA_INTEN_MASK)
239 spi->CNTRL2 &= ~SPI_CNTRL2_SSTA_INTEN_Msk;
240
241 if((u32Mask & SPI_FIFO_TX_INTEN_MASK) == SPI_FIFO_TX_INTEN_MASK)
242 spi->FIFO_CTL &= ~SPI_FIFO_CTL_TX_INTEN_Msk;
243
244 if((u32Mask & SPI_FIFO_RX_INTEN_MASK) == SPI_FIFO_RX_INTEN_MASK)
245 spi->FIFO_CTL &= ~SPI_FIFO_CTL_RX_INTEN_Msk;
246
247 if((u32Mask & SPI_FIFO_RXOV_INTEN_MASK) == SPI_FIFO_RXOV_INTEN_MASK)
248 spi->FIFO_CTL &= ~SPI_FIFO_CTL_RXOV_INTEN_Msk;
249
250 if((u32Mask & SPI_FIFO_TIMEOUT_INTEN_MASK) == SPI_FIFO_TIMEOUT_INTEN_MASK)
251 spi->FIFO_CTL &= ~SPI_FIFO_CTL_TIMEOUT_INTEN_Msk;
252}
253 /* end of group MINI51_SPI_EXPORTED_FUNCTIONS */
255 /* end of group MINI51_SPI_Driver */
257 /* end of group MINI51_Device_Driver */
259
260/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
Mini51Series.h
Mini51 series peripheral access layer header file. This file contains all the peripheral register's d...
SPI_FIFO_CTL_RX_THRESHOLD_Pos
#define SPI_FIFO_CTL_RX_THRESHOLD_Pos
Definition: Mini51Series.h:4608
SPI_CNTRL_FIFO_Msk
#define SPI_CNTRL_FIFO_Msk
Definition: Mini51Series.h:4534
SPI_FIFO_CTL_TX_THRESHOLD_Msk
#define SPI_FIFO_CTL_TX_THRESHOLD_Msk
Definition: Mini51Series.h:4612
SPI_FIFO_CTL_RXOV_INTEN_Msk
#define SPI_FIFO_CTL_RXOV_INTEN_Msk
Definition: Mini51Series.h:4603
SPI_FIFO_CTL_TX_THRESHOLD_Pos
#define SPI_FIFO_CTL_TX_THRESHOLD_Pos
Definition: Mini51Series.h:4611
SPI_SSR_SS_LTRIG_Msk
#define SPI_SSR_SS_LTRIG_Msk
Definition: Mini51Series.h:4561
SPI_SSR_SSR_Msk
#define SPI_SSR_SSR_Msk
Definition: Mini51Series.h:4552
SPI_FIFO_CTL_TX_INTEN_Msk
#define SPI_FIFO_CTL_TX_INTEN_Msk
Definition: Mini51Series.h:4600
SPI_SSR_AUTOSS_Msk
#define SPI_SSR_AUTOSS_Msk
Definition: Mini51Series.h:4558
SPI_CNTRL_IE_Msk
#define SPI_CNTRL_IE_Msk
Definition: Mini51Series.h:4525
SPI_FIFO_CTL_TX_CLR_Msk
#define SPI_FIFO_CTL_TX_CLR_Msk
Definition: Mini51Series.h:4594
SPI_CNTRL2_SSTA_INTEN_Msk
#define SPI_CNTRL2_SSTA_INTEN_Msk
Definition: Mini51Series.h:4579
SPI_CNTRL_TX_BIT_LEN_Pos
#define SPI_CNTRL_TX_BIT_LEN_Pos
Definition: Mini51Series.h:4509
SPI_DIVIDER_DIVIDER_Msk
#define SPI_DIVIDER_DIVIDER_Msk
Definition: Mini51Series.h:4549
SYS_IPRSTC2_SPI_RST_Msk
#define SYS_IPRSTC2_SPI_RST_Msk
Definition: Mini51Series.h:1581
SPI_FIFO_CTL_TIMEOUT_INTEN_Msk
#define SPI_FIFO_CTL_TIMEOUT_INTEN_Msk
Definition: Mini51Series.h:4606
SPI_SSR_SS_LVL_Msk
#define SPI_SSR_SS_LVL_Msk
Definition: Mini51Series.h:4555
SPI_FIFO_CTL_RX_INTEN_Msk
#define SPI_FIFO_CTL_RX_INTEN_Msk
Definition: Mini51Series.h:4597
SPI_FIFO_CTL_RX_CLR_Msk
#define SPI_FIFO_CTL_RX_CLR_Msk
Definition: Mini51Series.h:4591
SPI_FIFO_CTL_RX_THRESHOLD_Msk
#define SPI_FIFO_CTL_RX_THRESHOLD_Msk
Definition: Mini51Series.h:4609
CLK_GetHCLKFreq
uint32_t CLK_GetHCLKFreq(void)
This function get HCLK frequency. The frequency unit is Hz.
Definition: clk.c:114
SYS
#define SYS
Pointer to SYS register structure.
Definition: Mini51Series.h:5735
SPI_FIFO_TIMEOUT_INTEN_MASK
#define SPI_FIFO_TIMEOUT_INTEN_MASK
Definition: spi.h:50
SPI_FIFO_RX_INTEN_MASK
#define SPI_FIFO_RX_INTEN_MASK
Definition: spi.h:48
SPI_SSTA_INTEN_MASK
#define SPI_SSTA_INTEN_MASK
Definition: spi.h:46
SPI_FIFO_TX_INTEN_MASK
#define SPI_FIFO_TX_INTEN_MASK
Definition: spi.h:47
SPI_FIFO_RXOV_INTEN_MASK
#define SPI_FIFO_RXOV_INTEN_MASK
Definition: spi.h:49
SPI_IE_MASK
#define SPI_IE_MASK
Definition: spi.h:45
SPI_DisableInt
void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask)
Disable FIFO related interrupts specified by u32Mask parameter.
Definition: spi.c:233
SPI_DisableFIFO
void SPI_DisableFIFO(SPI_T *spi)
Disable FIFO mode.
Definition: spi.c:172
SPI_EnableInt
void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask)
Enable FIFO related interrupts specified by u32Mask parameter.
Definition: spi.c:202
SPI_EnableAutoSS
void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel)
Enable the automatic slave select function. Only available in Master mode.
Definition: spi.c:119
SPI_EnableFIFO
void SPI_EnableFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold)
Enable FIFO mode with user-specified Tx FIFO threshold and Rx FIFO threshold configurations.
Definition: spi.c:158
SPI_DisableAutoSS
void SPI_DisableAutoSS(SPI_T *spi)
Disable the automatic slave select function.
Definition: spi.c:107
SPI_SetBusClock
uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock)
Set the SPI bus clock. Only available in Master mode.
Definition: spi.c:130
SPI_Close
void SPI_Close(SPI_T *spi)
Reset SPI module and disable SPI peripheral clock.
Definition: spi.c:75
SPI_ClearTxFIFO
void SPI_ClearTxFIFO(SPI_T *spi)
Clear Tx FIFO buffer.
Definition: spi.c:97
SPI_Open
uint32_t SPI_Open(SPI_T *spi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock)
This function make SPI module be ready to transfer. By default, the SPI transfer sequence is MSB firs...
Definition: spi.c:39
SPI_GetBusClock
uint32_t SPI_GetBusClock(SPI_T *spi)
Get the actual frequency of SPI bus clock. Only available in Master mode.
Definition: spi.c:182
SPI_ClearRxFIFO
void SPI_ClearRxFIFO(SPI_T *spi)
Clear Rx FIFO buffer.
Definition: spi.c:87
SPI_T::CNTRL
__IO uint32_t CNTRL
Definition: Mini51Series.h:4473
SPI_T::CNTRL2
__IO uint32_t CNTRL2
Definition: Mini51Series.h:4487
SPI_T::FIFO_CTL
__IO uint32_t FIFO_CTL
Definition: Mini51Series.h:4488
SPI_T::SSR
__IO uint32_t SSR
Definition: Mini51Series.h:4475
SPI_T::DIVIDER
__IO uint32_t DIVIDER
Definition: Mini51Series.h:4474
SPI_T
Definition: Mini51Series.h:4204