| MINI55_BSP V3.01.003 The Board Support Package for Mini55 Series MCU

spi.c
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1/**************************************************************************/
12#include "Mini55Series.h"
39uint32_t SPI_Open(SPI_T *spi,
40 uint32_t u32MasterSlave,
41 uint32_t u32SPIMode,
42 uint32_t u32DataWidth,
43 uint32_t u32BusClock)
44{
45 if(u32DataWidth == 32)
46 u32DataWidth = 0;
47
48 spi->CTL = u32MasterSlave | (u32DataWidth << SPI_CTL_DWIDTH_Pos) | (u32SPIMode);
49
50 return ( SPI_SetBusClock(spi, u32BusClock) );
51}
52
58 void SPI_Close(SPI_T *spi)
59{
60 /* Reset SPI */
61 SYS->IPRST1 |= SYS_IPRST1_SPIRST_Msk;
62 SYS->IPRST1 &= ~SYS_IPRST1_SPIRST_Msk;
63}
64
70 void SPI_ClearRxFIFO(SPI_T *spi)
71{
72 spi->FIFOCTL |= SPI_FIFOCTL_RXRST_Msk;
73}
74
80 void SPI_ClearTxFIFO(SPI_T *spi)
81{
82 spi->FIFOCTL |= SPI_FIFOCTL_TXRST_Msk;
83}
84
90 void SPI_DisableAutoSS(SPI_T *spi)
91{
92 spi->SSCTL &= ~SPI_SSCTL_AUTOSS_Msk;
93}
94
102 void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel)
103{
104 spi->SSCTL = (spi->SSCTL & ~(SPI_SSCTL_SSACTPOL_Msk | SPI_SSCTL_SS_Msk)) | (u32SSPinMask | u32ActiveLevel) | SPI_SSCTL_AUTOSS_Msk;
105}
106
113uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock)
114{
115 uint32_t u32ClkSrc;
116 uint32_t u32Div;
117
118 if((CLK->CLKSEL1 & CLK_CLKSEL1_SPISEL_Msk) == CLK_CLKSEL1_SPISEL_HXTorLXT)
119 {
120 if((u32ClkSrc = CLK_GetHXTFreq()) == 0)
121 u32ClkSrc = CLK_GetLXTFreq();
122 }
123 else
124 u32ClkSrc = CLK_GetHCLKFreq();
125
126 if(u32BusClock > u32ClkSrc)
127 u32BusClock = u32ClkSrc;
128
129 if(u32BusClock != 0)
130 {
131 u32Div = (((u32ClkSrc / u32BusClock) + 1) >> 1) - 1;
132 if(u32Div > SPI_CLKDIV_DIVIDER_Msk)
133 u32Div = SPI_CLKDIV_DIVIDER_Msk;
134 }
135 else
136 return 0;
137
138 spi->CLKDIV = (spi->CLKDIV & ~SPI_CLKDIV_DIVIDER_Msk) | u32Div;
139 return ( u32ClkSrc / ((u32Div+1)*2) );
140}
141
149 void SPI_EnableFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold)
150{
151 spi->FIFOCTL = (spi->FIFOCTL & ~(SPI_FIFOCTL_TXTH_Msk | SPI_FIFOCTL_RXTH_Msk) |
152 (u32TxThreshold << SPI_FIFOCTL_TXTH_Pos) |
153 (u32RxThreshold << SPI_FIFOCTL_RXTH_Pos));
154
155 spi->CTL |= SPI_CTL_FIFOEN_Msk;
156}
157
163 void SPI_DisableFIFO(SPI_T *spi)
164{
165 spi->CTL &= ~SPI_CTL_FIFOEN_Msk;
166}
167
173uint32_t SPI_GetBusClock(SPI_T *spi)
174{
175 uint32_t u32ClkSrc;
176 uint32_t u32Div;
177
178 if((CLK->CLKSEL1 & CLK_CLKSEL1_SPISEL_Msk) == CLK_CLKSEL1_SPISEL_HXTorLXT)
179 {
180 if((u32ClkSrc = CLK_GetHXTFreq()) == 0)
181 u32ClkSrc = CLK_GetLXTFreq();
182 }
183 else
184 u32ClkSrc = CLK_GetHCLKFreq();
185
186 u32Div = spi->CLKDIV & SPI_CLKDIV_DIVIDER_Msk;
187 return ((u32ClkSrc >> 1) / (u32Div + 1));
188}
189
200 void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask)
201{
202 if((u32Mask & SPI_IE_MASK) == SPI_IE_MASK)
203 spi->CTL |= SPI_CTL_UNITIEN_Msk;
204
205 if((u32Mask & SPI_SSTA_INTEN_MASK) == SPI_SSTA_INTEN_MASK)
206 spi->SLVCTL |= SPI_SLVCTL_SLVSTIEN_Msk;
207
208 if((u32Mask & SPI_FIFO_TX_INTEN_MASK) == SPI_FIFO_TX_INTEN_MASK)
209 spi->FIFOCTL |= SPI_FIFOCTL_TXTHIEN_Msk;
210
211 if((u32Mask & SPI_FIFO_RX_INTEN_MASK) == SPI_FIFO_RX_INTEN_MASK)
212 spi->FIFOCTL |= SPI_FIFOCTL_RXTHIEN_Msk;
213
214 if((u32Mask & SPI_FIFO_RXOV_INTEN_MASK) == SPI_FIFO_RXOV_INTEN_MASK)
215 spi->FIFOCTL |= SPI_FIFOCTL_RXOVIEN_Msk;
216
217 if((u32Mask & SPI_FIFO_TIMEOUT_INTEN_MASK) == SPI_FIFO_TIMEOUT_INTEN_MASK)
218 spi->FIFOCTL |= SPI_FIFOCTL_RXTOIEN_Msk;
219}
220
231 void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask)
232{
233 if((u32Mask & SPI_IE_MASK) == SPI_IE_MASK)
234 spi->CTL &= ~SPI_CTL_UNITIEN_Msk;
235
236 if((u32Mask & SPI_SSTA_INTEN_MASK) == SPI_SSTA_INTEN_MASK)
237 spi->SLVCTL &= ~SPI_SLVCTL_SLVSTIEN_Msk;
238
239 if((u32Mask & SPI_FIFO_TX_INTEN_MASK) == SPI_FIFO_TX_INTEN_MASK)
240 spi->FIFOCTL &= ~SPI_FIFOCTL_TXTHIEN_Msk;
241
242 if((u32Mask & SPI_FIFO_RX_INTEN_MASK) == SPI_FIFO_RX_INTEN_MASK)
243 spi->FIFOCTL &= ~SPI_FIFOCTL_RXTHIEN_Msk;
244
245 if((u32Mask & SPI_FIFO_RXOV_INTEN_MASK) == SPI_FIFO_RXOV_INTEN_MASK)
246 spi->FIFOCTL &= ~SPI_FIFOCTL_RXOVIEN_Msk;
247
248 if((u32Mask & SPI_FIFO_TIMEOUT_INTEN_MASK) == SPI_FIFO_TIMEOUT_INTEN_MASK)
249 spi->FIFOCTL &= ~SPI_FIFOCTL_RXTOIEN_Msk;
250}
251 /* end of group MINI55_SPI_EXPORTED_FUNCTIONS */
253 /* end of group MINI55_SPI_Driver */
255 /* end of group MINI55_Device_Driver */
257
258/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
Mini55Series.h
Mini55 series peripheral access layer header file. This file contains all the peripheral register's d...
SPI_SSCTL_SSACTPOL_Msk
#define SPI_SSCTL_SSACTPOL_Msk
Definition: Mini55Series.h:4953
SPI_FIFOCTL_RXOVIEN_Msk
#define SPI_FIFOCTL_RXOVIEN_Msk
Definition: Mini55Series.h:5001
SPI_CTL_FIFOEN_Msk
#define SPI_CTL_FIFOEN_Msk
Definition: Mini55Series.h:4932
SPI_SSCTL_SS_Msk
#define SPI_SSCTL_SS_Msk
Definition: Mini55Series.h:4950
SPI_CTL_UNITIEN_Msk
#define SPI_CTL_UNITIEN_Msk
Definition: Mini55Series.h:4923
SPI_FIFOCTL_RXTH_Pos
#define SPI_FIFOCTL_RXTH_Pos
Definition: Mini55Series.h:5006
SPI_FIFOCTL_TXTH_Msk
#define SPI_FIFOCTL_TXTH_Msk
Definition: Mini55Series.h:5010
SPI_CTL_DWIDTH_Pos
#define SPI_CTL_DWIDTH_Pos
Definition: Mini55Series.h:4907
SPI_FIFOCTL_RXRST_Msk
#define SPI_FIFOCTL_RXRST_Msk
Definition: Mini55Series.h:4989
SPI_FIFOCTL_TXRST_Msk
#define SPI_FIFOCTL_TXRST_Msk
Definition: Mini55Series.h:4992
SPI_CLKDIV_DIVIDER_Msk
#define SPI_CLKDIV_DIVIDER_Msk
Definition: Mini55Series.h:4947
SPI_FIFOCTL_TXTH_Pos
#define SPI_FIFOCTL_TXTH_Pos
Definition: Mini55Series.h:5009
SPI_FIFOCTL_RXTOIEN_Msk
#define SPI_FIFOCTL_RXTOIEN_Msk
Definition: Mini55Series.h:5004
SPI_FIFOCTL_RXTHIEN_Msk
#define SPI_FIFOCTL_RXTHIEN_Msk
Definition: Mini55Series.h:4995
SPI_FIFOCTL_RXTH_Msk
#define SPI_FIFOCTL_RXTH_Msk
Definition: Mini55Series.h:5007
SPI_FIFOCTL_TXTHIEN_Msk
#define SPI_FIFOCTL_TXTHIEN_Msk
Definition: Mini55Series.h:4998
SPI_SSCTL_AUTOSS_Msk
#define SPI_SSCTL_AUTOSS_Msk
Definition: Mini55Series.h:4956
SYS_IPRST1_SPIRST_Msk
#define SYS_IPRST1_SPIRST_Msk
Definition: Mini55Series.h:5538
SPI_SLVCTL_SLVSTIEN_Msk
#define SPI_SLVCTL_SLVSTIEN_Msk
Definition: Mini55Series.h:4977
CLK_CLKSEL1_SPISEL_HXTorLXT
#define CLK_CLKSEL1_SPISEL_HXTorLXT
Definition: clk.h:65
CLK_GetHCLKFreq
uint32_t CLK_GetHCLKFreq(void)
This function get HCLK frequency. The frequency unit is Hz.
Definition: clk.c:114
CLK_GetLXTFreq
uint32_t CLK_GetLXTFreq(void)
This function get external low frequency crystal frequency. The frequency unit is Hz.
Definition: clk.c:102
CLK_GetHXTFreq
uint32_t CLK_GetHXTFreq(void)
This function get external high frequency crystal frequency. The frequency unit is Hz.
Definition: clk.c:90
SPI_FIFO_TIMEOUT_INTEN_MASK
#define SPI_FIFO_TIMEOUT_INTEN_MASK
Definition: spi.h:50
SPI_FIFO_RX_INTEN_MASK
#define SPI_FIFO_RX_INTEN_MASK
Definition: spi.h:48
SPI_SSTA_INTEN_MASK
#define SPI_SSTA_INTEN_MASK
Definition: spi.h:46
SPI_FIFO_TX_INTEN_MASK
#define SPI_FIFO_TX_INTEN_MASK
Definition: spi.h:47
SPI_FIFO_RXOV_INTEN_MASK
#define SPI_FIFO_RXOV_INTEN_MASK
Definition: spi.h:49
SPI_IE_MASK
#define SPI_IE_MASK
Definition: spi.h:45
SPI_DisableInt
void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask)
Disable FIFO related interrupts specified by u32Mask parameter.
Definition: spi.c:231
SPI_DisableFIFO
void SPI_DisableFIFO(SPI_T *spi)
Disable FIFO mode.
Definition: spi.c:163
SPI_EnableInt
void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask)
Enable FIFO related interrupts specified by u32Mask parameter.
Definition: spi.c:200
SPI_EnableAutoSS
void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel)
Enable the automatic slave select function. Only available in Master mode.
Definition: spi.c:102
SPI_EnableFIFO
void SPI_EnableFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold)
Enable FIFO mode with user-specified Tx FIFO threshold and Rx FIFO threshold configurations.
Definition: spi.c:149
SPI_DisableAutoSS
void SPI_DisableAutoSS(SPI_T *spi)
Disable the automatic slave select function.
Definition: spi.c:90
SPI_SetBusClock
uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock)
Set the SPI bus clock. Only available in Master mode.
Definition: spi.c:113
SPI_Close
void SPI_Close(SPI_T *spi)
Reset SPI module and disable SPI peripheral clock.
Definition: spi.c:58
SPI_ClearTxFIFO
void SPI_ClearTxFIFO(SPI_T *spi)
Clear Tx FIFO buffer.
Definition: spi.c:80
SPI_Open
uint32_t SPI_Open(SPI_T *spi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock)
This function make SPI module be ready to transfer. By default, the SPI transfer sequence is MSB firs...
Definition: spi.c:39
SPI_GetBusClock
uint32_t SPI_GetBusClock(SPI_T *spi)
Get the actual frequency of SPI bus clock. Only available in Master mode.
Definition: spi.c:173
SPI_ClearRxFIFO
void SPI_ClearRxFIFO(SPI_T *spi)
Clear Rx FIFO buffer.
Definition: spi.c:70
CLK_CLKSEL1_SPISEL_Msk
#define CLK_CLKSEL1_SPISEL_Msk
Definition: Mini55Series.h:1226
CLK
#define CLK
Pointer to CLK register structure.
Definition: Mini55Series.h:7010
SYS
#define SYS
Pointer to SYS register structure.
Definition: Mini55Series.h:7009
SPI_T::CTL
__IO uint32_t CTL
Definition: Mini55Series.h:4658
SPI_T::CLKDIV
__IO uint32_t CLKDIV
Definition: Mini55Series.h:4675
SPI_T::FIFOCTL
__IO uint32_t FIFOCTL
Definition: Mini55Series.h:4829
SPI_T::SSCTL
__IO uint32_t SSCTL
Definition: Mini55Series.h:4711
SPI_T::SLVCTL
__IO uint32_t SLVCTL
Definition: Mini55Series.h:4795
SPI_T
Definition: Mini55Series.h:4570