| MINI58_BSP V3.01.003 The Board Support Package for Mini58 Series MCU

clk.h
Go to the documentation of this file.
1/**************************************************************************/
12#ifndef __CLK_H__
13#define __CLK_H__
14
15#ifdef __cplusplus
16 extern "C"
17{
18#endif
19
20
35#define FREQ_25MHZ 25000000
36#define FREQ_50MHZ 50000000
37#define FREQ_72MHZ 72000000
38#define FREQ_100MHZ 100000000
39#define FREQ_200MHZ 200000000
40#define FREQ_250MHZ 250000000
41#define FREQ_500MHZ 500000000
42
43
44/*---------------------------------------------------------------------------------------------------------*/
45/* PWRCTL constant definitions. */
46/*---------------------------------------------------------------------------------------------------------*/
47#define CLK_PWRCTL_XTL12M 0x01UL
48#define CLK_PWRCTL_XTLEN_HXT 0x01UL
49#define CLK_PWRCTL_XTL32K 0x02UL
50#define CLK_PWRCTL_XTLEN_LXT 0x02UL
52/*---------------------------------------------------------------------------------------------------------*/
53/* CLKSEL0 constant definitions. */
54/*---------------------------------------------------------------------------------------------------------*/
55#define CLK_CLKSEL0_HCLKSEL_XTAL 0x00UL
56#define CLK_CLKSEL0_HCLKSEL_HXT 0x00UL
57#define CLK_CLKSEL0_HCLKSEL_LXT 0x00UL
58#define CLK_CLKSEL0_HCLKSEL_PLL 0x02UL
59#define CLK_CLKSEL0_HCLKSEL_LIRC 0x03UL
60#define CLK_CLKSEL0_HCLKSEL_HIRC 0x07UL
61#define CLK_CLKSEL0_STCLKSEL_XTAL 0x00UL
62#define CLK_CLKSEL0_STCLKSEL_XTAL_DIV2 0x10UL
63#define CLK_CLKSEL0_STCLKSEL_HCLK_DIV2 0x18UL
64#define CLK_CLKSEL0_STCLKSEL_HIRC_DIV2 0x38UL
65#define CLK_CLKSEL0_STCLKSEL_HCLK 0x08UL
67/*---------------------------------------------------------------------------------------------------------*/
68/* CLKSEL1 constant definitions. */
69/*---------------------------------------------------------------------------------------------------------*/
70#define CLK_CLKSEL1_WDTSEL_XTAL 0x00000000UL
71#define CLK_CLKSEL1_WDTSEL_HCLK_DIV2048 0x00000002UL
72#define CLK_CLKSEL1_WDTSEL_IRC10K 0x00000003UL
73#define CLK_CLKSEL1_WDTSEL_LIRC 0x00000003UL
74#define CLK_CLKSEL1_ADCSEL_XTAL 0x00000000UL
75#define CLK_CLKSEL1_ADCSEL_PLL 0x00000004UL
76#define CLK_CLKSEL1_ADCSEL_HCLK 0x00000008UL
77#define CLK_CLKSEL1_ADCSEL_HIRC 0x0000000CUL
78#define CLK_CLKSEL1_SPISEL_XTAL 0x00000000UL
79#define CLK_CLKSEL1_SPISEL_HCLK 0x00000010UL
80#define CLK_CLKSEL1_SPISEL_PLL 0x00000020UL
81#define CLK_CLKSEL1_TMR0SEL_XTAL 0x00000000UL
82#define CLK_CLKSEL1_TMR0SEL_LIRC 0x00000100UL
83#define CLK_CLKSEL1_TMR0SEL_HCLK 0x00000200UL
84#define CLK_CLKSEL1_TMR0SEL_TM0 0x00000300UL
85#define CLK_CLKSEL1_TMR0SEL_HIRC 0x00000700UL
86#define CLK_CLKSEL1_TMR1SEL_XTAL 0x00000000UL
87#define CLK_CLKSEL1_TMR1SEL_LIRC 0x00001000UL
88#define CLK_CLKSEL1_TMR1SEL_HCLK 0x00002000UL
89#define CLK_CLKSEL1_TMR1SEL_TM1 0x00003000UL
90#define CLK_CLKSEL1_TMR1SEL_HIRC 0x00007000UL
91#define CLK_CLKSEL1_UARTSEL_XTAL 0x00000000UL
92#define CLK_CLKSEL1_UARTSEL_PLL 0x01000000UL
93#define CLK_CLKSEL1_UARTSEL_HIRC 0x02000000UL
94#define CLK_CLKSEL1_PWMCH01SEL_HCLK 0x20000000UL
95#define CLK_CLKSEL1_PWMCH23SEL_HCLK 0x80000000UL
98/*---------------------------------------------------------------------------------------------------------*/
99/* CLKSEL2 constant definitions. */
100/*---------------------------------------------------------------------------------------------------------*/
101#define CLK_CLKSEL2_CLKOSEL_XTAL 0x00000000UL
102#define CLK_CLKSEL2_CLKOSEL_HXT 0x00000000UL
103#define CLK_CLKSEL2_CLKOSEL_LXT 0x00000000UL
104#define CLK_CLKSEL2_CLKOSEL_LIRC 0x00000004UL
105#define CLK_CLKSEL2_CLKOSEL_HCLK 0x00000008UL
106#define CLK_CLKSEL2_CLKOSEL_HIRC 0x0000000CUL
107#define CLK_CLKSEL2_PWMCH45SEL_HCLK 0x00000020UL
108#define CLK_CLKSEL2_WWDTSEL_HCLK_DIV2048 0x00020000UL
109#define CLK_CLKSEL2_WWDTSEL_LIRC 0x00030000UL
112/*---------------------------------------------------------------------------------------------------------*/
113/* CLKDIV constant definitions. */
114/*---------------------------------------------------------------------------------------------------------*/
115#define CLK_CLKDIV_ADC(x) (((x)-1) << 16)
116#define CLK_CLKDIV_UART(x) (((x)-1) << 8)
117#define CLK_CLKDIV_HCLK(x) ((x)-1)
119/*---------------------------------------------------------------------------------------------------------*/
120/* PLLCTL constant definitions. PLL = FIN * NF / NR / NO */
121/*---------------------------------------------------------------------------------------------------------*/
122#define CLK_PLLCTL_PLLSRC_HXT 0x00000000UL
123#define CLK_PLLCTL_PLLSRC_HIRC 0x00080000UL
125#define CLK_PLLCTL_NF(x) ((x)-2)
126#define CLK_PLLCTL_NR(x) (((x)-2)<<9)
128#define CLK_PLLCTL_NO_1 0x0000UL
129#define CLK_PLLCTL_NO_2 0x4000UL
130#define CLK_PLLCTL_NO_4 0xC000UL
132#define CLK_PLLCTL_72MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(2) | CLK_PLLCTL_NF( 24) | CLK_PLLCTL_NO_2)
133#define CLK_PLLCTL_96MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(2) | CLK_PLLCTL_NF( 32) | CLK_PLLCTL_NO_2)
134#define CLK_PLLCTL_100MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(3) | CLK_PLLCTL_NF( 50) | CLK_PLLCTL_NO_2)
136#define CLK_PLLCTL_72MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(4) | CLK_PLLCTL_NF( 26) | CLK_PLLCTL_NO_2)
137#define CLK_PLLCTL_96MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(13)| CLK_PLLCTL_NF(113) | CLK_PLLCTL_NO_2)
138#define CLK_PLLCTL_100MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(4) | CLK_PLLCTL_NF( 36) | CLK_PLLCTL_NO_2)
140/*---------------------------------------------------------------------------------------------------------*/
141/* MODULE constant definitions. */
142/*---------------------------------------------------------------------------------------------------------*/
143#define MODULE_APBCLK(x) ((x >>31) & 0x1)
144#define MODULE_CLKSEL(x) ((x >>29) & 0x3)
145#define MODULE_CLKSEL_Msk(x) ((x >>25) & 0xf)
146#define MODULE_CLKSEL_Pos(x) ((x >>20) & 0x1f)
147#define MODULE_CLKDIV(x) ((x >>18) & 0x3)
148#define MODULE_CLKDIV_Msk(x) ((x >>10) & 0xff)
149#define MODULE_CLKDIV_Pos(x) ((x >>5 ) & 0x1f)
150#define MODULE_IP_EN_Pos(x) ((x >>0 ) & 0x1f)
151#define MODULE_NoMsk 0x0
152#define NA MODULE_NoMsk
154#define MODULE_APBCLK_ENC(x) (((x) & 0x01) << 31)
155#define MODULE_CLKSEL_ENC(x) (((x) & 0x03) << 29)
156#define MODULE_CLKSEL_Msk_ENC(x) (((x) & 0x0f) << 25)
157#define MODULE_CLKSEL_Pos_ENC(x) (((x) & 0x1f) << 20)
158#define MODULE_CLKDIV_ENC(x) (((x) & 0x03) << 18)
159#define MODULE_CLKDIV_Msk_ENC(x) (((x) & 0xff) << 10)
160#define MODULE_CLKDIV_Pos_ENC(x) (((x) & 0x1f) << 5)
161#define MODULE_IP_EN_Pos_ENC(x) (((x) & 0x1f) << 0)
162/*-------------------------------------------------------------------------------------------------------------------------------*/
163/* APBCLK(1) | CLKSEL(2) | CLKSEL_Msk(4) | CLKSEL_Pos(5) | CLKDIV(2) | CLKDIV_Msk(8) | CLKDIV_Pos(5) | IP_EN_Pos(5)*/
164/*-------------------------------------------------------------------------------------------------------------------------------*/
165#define ISP_MODULE (( 0UL<<31)|( 0<<29)|( MODULE_NoMsk<<25)|( 0<<20)|( 0<<18)|( MODULE_NoMsk<<10)|( 0<<5)|( 2<<0))
166#define WDT_MODULE (( 1UL<<31)|( 1<<29)|( 3<<25)|( 0<<20)|( 0<<18)|( MODULE_NoMsk<<10)|( 0<<5)|( 0<<0))
167#define TMR0_MODULE (( 1UL<<31)|( 1<<29)|( 7<<25)|( 8<<20)|( 0<<18)|( MODULE_NoMsk<<10)|( 0<<5)|( 2<<0))
168#define TMR1_MODULE (( 1UL<<31)|( 1<<29)|( 7<<25)|(12<<20)|( 0<<18)|( MODULE_NoMsk<<10)|( 0<<5)|( 3<<0))
169#define CLKO_MODULE (( 1UL<<31)|( 3<<29)|( 3<<25)|( 2<<20)|( 0<<18)|( MODULE_NoMsk<<10)|( 0<<5)|( 6<<0))
170#define I2C0_MODULE (( 1UL<<31)|( 0<<29)|( MODULE_NoMsk<<25)|( 0<<20)|( 0<<18)|( MODULE_NoMsk<<10)|( 0<<5)|( 8<<0))
171#define I2C1_MODULE (( 1UL<<31)|( 0<<29)|( MODULE_NoMsk<<25)|( 0<<20)|( 0<<18)|( MODULE_NoMsk<<10)|( 0<<5)|( 9<<0))
172#define SPI0_MODULE (( 1UL<<31)|( 1<<29)|( 3<<25)|( 4<<20)|( 0<<18)|( MODULE_NoMsk<<10)|( 0<<5)|(12<<0))
173#define UART0_MODULE (( 1UL<<31)|( 1<<29)|( 3<<25)|(24<<20)|( 0<<18)|( 0xF<<10)|( 8<<5)|(16<<0))
174#define UART1_MODULE (( 1UL<<31)|( 1<<29)|( 3<<25)|(24<<20)|( 0<<18)|( 0xF<<10)|( 8<<5)|(17<<0))
175#define PWMCH01_MODULE (( 1UL<<31)|( 1<<29)|( 3<<25)|(28<<20)|( 0<<18)|( MODULE_NoMsk<<10)|( 0<<5)|(20<<0))
176#define PWMCH23_MODULE (( 1UL<<31)|( 1<<29)|( 3<<25)|(30<<20)|( 0<<18)|( MODULE_NoMsk<<10)|( 0<<5)|(21<<0))
177#define PWMCH45_MODULE (( 1UL<<31)|( 3<<29)|( 3<<25)|( 4<<20)|( 0<<18)|( MODULE_NoMsk<<10)|( 0<<5)|(22<<0))
178#define ADC_MODULE (( 1UL<<31)|( 1<<29)|( 3<<25)|( 2<<20)|( 0<<18)|( 0xFF<<10)|(16<<5)|(28<<0))
179#define ACMP_MODULE (( 1UL<<31)|( 0<<29)|( MODULE_NoMsk<<25)|( 0<<20)|( 0<<18)|( MODULE_NoMsk<<10)|( 0<<5)|(30<<0))
180#define WWDT_MODULE (( 1UL<<31)|( 3<<29)|( 3<<25)|(16<<20)|( 0<<18)|( MODULE_NoMsk<<10)|( 0<<5)|( 0<<0)) /* end of group Mini58_CLK_EXPORTED_CONSTANTS */
185
186
197__STATIC_INLINE uint32_t CLK_GetPLLClockFreq(void)
198{
199 uint32_t u32PllFreq = 0, u32PllReg;
200 uint32_t u32FIN, u32NF, u32NR, u32NO;
201 uint8_t au8NoTbl[4] = {1, 2, 2, 4};
202
203 u32PllReg = CLK->PLLCTL;
204
205 if(u32PllReg & (CLK_PLLCTL_PD_Msk | CLK_PLLCTL_OE_Msk))
206 return 0; /* PLL is in power down mode or fix low */
207
208 if(u32PllReg & CLK_PLLCTL_PLLSRC_HIRC)
209 u32FIN = __HIRC; /* PLL source clock from HIRC */
210 else
211 u32FIN = __XTAL; /* PLL source clock from HXT */
212
213 if(u32PllReg & CLK_PLLCTL_BP_Msk)
214 return u32FIN; /* PLL is in bypass mode */
215
216 /* PLL is output enabled in normal work mode */
217 u32NO = au8NoTbl[((u32PllReg & CLK_PLLCTL_OUTDIV_Msk) >> CLK_PLLCTL_OUTDIV_Pos)];
218 u32NF = ((u32PllReg & CLK_PLLCTL_FBDIV_Msk) >> CLK_PLLCTL_FBDIV_Pos) + 2;
219 u32NR = ((u32PllReg & CLK_PLLCTL_INDIV_Msk) >> CLK_PLLCTL_INDIV_Pos) + 2;
220
221 /* u32FIN is shifted 2 bits to avoid overflow */
222 u32PllFreq = (((u32FIN >> 2) * u32NF) / (u32NR * u32NO) << 2);
223
224 return u32PllFreq;
225}
226
227 void CLK_DisableCKO(void);
228 void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En);
229 void CLK_PowerDown(void);
230 void CLK_Idle(void);
231uint32_t CLK_GetHXTFreq(void);
232uint32_t CLK_GetLXTFreq(void);
233uint32_t CLK_GetHCLKFreq(void);
234uint32_t CLK_GetCPUFreq(void);
235uint32_t CLK_SetCoreClock(uint32_t u32Hclk);
236 void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv);
237 void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv);
238 void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc);
239 void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count);
240 void CLK_DisableSysTick(void);
241 void CLK_EnableXtalRC(uint32_t u32ClkMask);
242 void CLK_DisableXtalRC(uint32_t u32ClkMask);
243 void CLK_EnableModuleClock(uint32_t u32ModuleIdx);
244 void CLK_DisableModuleClock(uint32_t u32ModuleIdx);
245int32_t CLK_SysTickDelay(uint32_t us);
246uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq);
247 void CLK_DisablePLL(void);
248uint32_t CLK_WaitClockReady(uint32_t u32ClkMask);
249
250
251 /* end of group Mini58_CLK_EXPORTED_FUNCTIONS */
253 /* end of group Mini58_CLK_Driver */
255 /* end of group Mini58_Device_Driver */
257
258#ifdef __cplusplus
259}
260#endif
261
262#endif //__CLK_H__
263
264/*** (C) COPYRIGHT 2022 Nuvoton Technology Corp. ***/
CLK_PLLCTL_PLLSRC_HIRC
#define CLK_PLLCTL_PLLSRC_HIRC
Definition: clk.h:123
CLK_Idle
void CLK_Idle(void)
This function let system enter to Idle mode.
Definition: clk.c:81
CLK_SetSysTickClockSrc
void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc)
This function set SysTick clock source.
Definition: clk.c:288
CLK_GetHCLKFreq
uint32_t CLK_GetHCLKFreq(void)
This function get HCLK frequency. The frequency unit is Hz.
Definition: clk.c:115
CLK_EnablePLL
uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq)
Set PLL frequency.
Definition: clk.c:420
CLK_DisableCKO
void CLK_DisableCKO(void)
This function disable frequency output function.
Definition: clk.c:30
CLK_EnableModuleClock
void CLK_EnableModuleClock(uint32_t u32ModuleIdx)
This function enable module clock.
Definition: clk.c:380
CLK_EnableCKO
void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En)
This function enable frequency divider module clock, enable frequency divider clock function and conf...
Definition: clk.c:54
CLK_DisableModuleClock
void CLK_DisableModuleClock(uint32_t u32ModuleIdx)
This function disable module clock.
Definition: clk.c:405
CLK_WaitClockReady
uint32_t CLK_WaitClockReady(uint32_t u32ClkMask)
This function check selected clock source status.
Definition: clk.c:630
CLK_GetLXTFreq
uint32_t CLK_GetLXTFreq(void)
This function get external low frequency crystal frequency. The frequency unit is Hz.
Definition: clk.c:103
CLK_PowerDown
void CLK_PowerDown(void)
This function let system enter to Power-down mode.
Definition: clk.c:70
CLK_DisablePLL
void CLK_DisablePLL(void)
Disable PLL.
Definition: clk.c:586
CLK_GetCPUFreq
uint32_t CLK_GetCPUFreq(void)
This function get CPU frequency. The frequency unit is Hz.
Definition: clk.c:126
CLK_SysTickDelay
int32_t CLK_SysTickDelay(uint32_t us)
This function execute delay function.
Definition: clk.c:600
CLK_SetHCLK
void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv)
This function set HCLK clock source and HCLK clock divider.
Definition: clk.c:197
CLK_GetPLLClockFreq
__STATIC_INLINE uint32_t CLK_GetPLLClockFreq(void)
Get PLL clock frequency.
Definition: clk.h:197
CLK_DisableXtalRC
void CLK_DisableXtalRC(uint32_t u32ClkMask)
This function disable clock source.
Definition: clk.c:355
CLK_DisableSysTick
void CLK_DisableSysTick(void)
Disable System Tick counter.
Definition: clk.c:326
CLK_SetModuleClock
void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv)
This function set selected module clock source and module clock divider.
Definition: clk.c:258
CLK_EnableXtalRC
void CLK_EnableXtalRC(uint32_t u32ClkMask)
This function enable clock source.
Definition: clk.c:339
CLK_EnableSysTick
void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count)
Enable System Tick counter.
Definition: clk.c:306
CLK_SetCoreClock
uint32_t CLK_SetCoreClock(uint32_t u32Hclk)
Set HCLK frequency.
Definition: clk.c:141
CLK_GetHXTFreq
uint32_t CLK_GetHXTFreq(void)
This function get external high frequency crystal frequency. The frequency unit is Hz.
Definition: clk.c:91
CLK_PLLCTL_INDIV_Pos
#define CLK_PLLCTL_INDIV_Pos
Definition: Mini58Series.h:1310
CLK_PLLCTL_BP_Msk
#define CLK_PLLCTL_BP_Msk
Definition: Mini58Series.h:1320
CLK_PLLCTL_FBDIV_Msk
#define CLK_PLLCTL_FBDIV_Msk
Definition: Mini58Series.h:1308
CLK_PLLCTL_INDIV_Msk
#define CLK_PLLCTL_INDIV_Msk
Definition: Mini58Series.h:1311
CLK_PLLCTL_PD_Msk
#define CLK_PLLCTL_PD_Msk
Definition: Mini58Series.h:1317
CLK_PLLCTL_OUTDIV_Pos
#define CLK_PLLCTL_OUTDIV_Pos
Definition: Mini58Series.h:1313
CLK_PLLCTL_OUTDIV_Msk
#define CLK_PLLCTL_OUTDIV_Msk
Definition: Mini58Series.h:1314
CLK_PLLCTL_OE_Msk
#define CLK_PLLCTL_OE_Msk
Definition: Mini58Series.h:1323
CLK_PLLCTL_FBDIV_Pos
#define CLK_PLLCTL_FBDIV_Pos
Definition: Mini58Series.h:1307
CLK
#define CLK
Pointer to CLK register structure.
Definition: Mini58Series.h:11730
__HIRC
#define __HIRC
Definition: system_Mini58Series.h:33
__XTAL
#define __XTAL
Definition: system_Mini58Series.h:31