| MINI58_BSP V3.01.003 The Board Support Package for Mini58 Series MCU

Modules | Macros
CLK Exported Constants
Mini58 Device Driver » CLK Driver
Collaboration diagram for CLK Exported Constants:

## Modules
| CLK Exported Functions

## Macros
#define | FREQ_25MHZ 25000000
#define | FREQ_50MHZ 50000000
#define | FREQ_72MHZ 72000000
#define | FREQ_100MHZ 100000000
#define | FREQ_200MHZ 200000000
#define | FREQ_250MHZ 250000000
#define | FREQ_500MHZ 500000000
#define | CLK_PWRCTL_XTL12M 0x01UL
#define | CLK_PWRCTL_XTLEN_HXT 0x01UL
#define | CLK_PWRCTL_XTL32K 0x02UL
#define | CLK_PWRCTL_XTLEN_LXT 0x02UL
#define | CLK_CLKSEL0_HCLKSEL_XTAL 0x00UL
#define | CLK_CLKSEL0_HCLKSEL_HXT 0x00UL
#define | CLK_CLKSEL0_HCLKSEL_LXT 0x00UL
#define | CLK_CLKSEL0_HCLKSEL_PLL 0x02UL
#define | CLK_CLKSEL0_HCLKSEL_LIRC 0x03UL
#define | CLK_CLKSEL0_HCLKSEL_HIRC 0x07UL
#define | CLK_CLKSEL0_STCLKSEL_XTAL 0x00UL
#define | CLK_CLKSEL0_STCLKSEL_XTAL_DIV2 0x10UL
#define | CLK_CLKSEL0_STCLKSEL_HCLK_DIV2 0x18UL
#define | CLK_CLKSEL0_STCLKSEL_HIRC_DIV2 0x38UL
#define | CLK_CLKSEL0_STCLKSEL_HCLK 0x08UL
#define | CLK_CLKSEL1_WDTSEL_XTAL 0x00000000UL
#define | CLK_CLKSEL1_WDTSEL_HCLK_DIV2048 0x00000002UL
#define | CLK_CLKSEL1_WDTSEL_IRC10K 0x00000003UL
#define | CLK_CLKSEL1_WDTSEL_LIRC 0x00000003UL
#define | CLK_CLKSEL1_ADCSEL_XTAL 0x00000000UL
#define | CLK_CLKSEL1_ADCSEL_PLL 0x00000004UL
#define | CLK_CLKSEL1_ADCSEL_HCLK 0x00000008UL
#define | CLK_CLKSEL1_ADCSEL_HIRC 0x0000000CUL
#define | CLK_CLKSEL1_SPISEL_XTAL 0x00000000UL
#define | CLK_CLKSEL1_SPISEL_HCLK 0x00000010UL
#define | CLK_CLKSEL1_SPISEL_PLL 0x00000020UL
#define | CLK_CLKSEL1_TMR0SEL_XTAL 0x00000000UL
#define | CLK_CLKSEL1_TMR0SEL_LIRC 0x00000100UL
#define | CLK_CLKSEL1_TMR0SEL_HCLK 0x00000200UL
#define | CLK_CLKSEL1_TMR0SEL_TM0 0x00000300UL
#define | CLK_CLKSEL1_TMR0SEL_HIRC 0x00000700UL
#define | CLK_CLKSEL1_TMR1SEL_XTAL 0x00000000UL
#define | CLK_CLKSEL1_TMR1SEL_LIRC 0x00001000UL
#define | CLK_CLKSEL1_TMR1SEL_HCLK 0x00002000UL
#define | CLK_CLKSEL1_TMR1SEL_TM1 0x00003000UL
#define | CLK_CLKSEL1_TMR1SEL_HIRC 0x00007000UL
#define | CLK_CLKSEL1_UARTSEL_XTAL 0x00000000UL
#define | CLK_CLKSEL1_UARTSEL_PLL 0x01000000UL
#define | CLK_CLKSEL1_UARTSEL_HIRC 0x02000000UL
#define | CLK_CLKSEL1_PWMCH01SEL_HCLK 0x20000000UL
#define | CLK_CLKSEL1_PWMCH23SEL_HCLK 0x80000000UL
#define | CLK_CLKSEL2_CLKOSEL_XTAL 0x00000000UL
#define | CLK_CLKSEL2_CLKOSEL_HXT 0x00000000UL
#define | CLK_CLKSEL2_CLKOSEL_LXT 0x00000000UL
#define | CLK_CLKSEL2_CLKOSEL_LIRC 0x00000004UL
#define | CLK_CLKSEL2_CLKOSEL_HCLK 0x00000008UL
#define | CLK_CLKSEL2_CLKOSEL_HIRC 0x0000000CUL
#define | CLK_CLKSEL2_PWMCH45SEL_HCLK 0x00000020UL
#define | CLK_CLKSEL2_WWDTSEL_HCLK_DIV2048 0x00020000UL
#define | CLK_CLKSEL2_WWDTSEL_LIRC 0x00030000UL
#define | CLK_CLKDIV_ADC(x) (((x)-1) << 16)
#define | CLK_CLKDIV_UART(x) (((x)-1) << 8)
#define | CLK_CLKDIV_HCLK(x) ((x)-1)
#define | CLK_PLLCTL_PLLSRC_HXT 0x00000000UL
#define | CLK_PLLCTL_PLLSRC_HIRC 0x00080000UL
#define | CLK_PLLCTL_NF(x) ((x)-2)
#define | CLK_PLLCTL_NR(x) (((x)-2)<<9)
#define | CLK_PLLCTL_NO_1 0x0000UL
#define | CLK_PLLCTL_NO_2 0x4000UL
#define | CLK_PLLCTL_NO_4 0xC000UL
#define | CLK_PLLCTL_72MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(2) | CLK_PLLCTL_NF( 24) | CLK_PLLCTL_NO_2)
#define | CLK_PLLCTL_96MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(2) | CLK_PLLCTL_NF( 32) | CLK_PLLCTL_NO_2)
#define | CLK_PLLCTL_100MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(3) | CLK_PLLCTL_NF( 50) | CLK_PLLCTL_NO_2)
#define | CLK_PLLCTL_72MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(4) | CLK_PLLCTL_NF( 26) | CLK_PLLCTL_NO_2)
#define | CLK_PLLCTL_96MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(13)| CLK_PLLCTL_NF(113) | CLK_PLLCTL_NO_2)
#define | CLK_PLLCTL_100MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(4) | CLK_PLLCTL_NF( 36) | CLK_PLLCTL_NO_2)
#define | MODULE_APBCLK(x) ((x >>31) & 0x1)
#define | MODULE_CLKSEL(x) ((x >>29) & 0x3)
#define | MODULE_CLKSEL_Msk(x) ((x >>25) & 0xf)
#define | MODULE_CLKSEL_Pos(x) ((x >>20) & 0x1f)
#define | MODULE_CLKDIV(x) ((x >>18) & 0x3)
#define | MODULE_CLKDIV_Msk(x) ((x >>10) & 0xff)
#define | MODULE_CLKDIV_Pos(x) ((x >>5 ) & 0x1f)
#define | MODULE_IP_EN_Pos(x) ((x >>0 ) & 0x1f)
#define | MODULE_NoMsk 0x0
#define | NA MODULE_NoMsk
#define | MODULE_APBCLK_ENC(x) (((x) & 0x01) << 31)
#define | MODULE_CLKSEL_ENC(x) (((x) & 0x03) << 29)
#define | MODULE_CLKSEL_Msk_ENC(x) (((x) & 0x0f) << 25)
#define | MODULE_CLKSEL_Pos_ENC(x) (((x) & 0x1f) << 20)
#define | MODULE_CLKDIV_ENC(x) (((x) & 0x03) << 18)
#define | MODULE_CLKDIV_Msk_ENC(x) (((x) & 0xff) << 10)
#define | MODULE_CLKDIV_Pos_ENC(x) (((x) & 0x1f) << 5)
#define | MODULE_IP_EN_Pos_ENC(x) (((x) & 0x1f) << 0)
#define | ISP_MODULE
#define | WDT_MODULE
#define | TMR0_MODULE
#define | TMR1_MODULE
#define | CLKO_MODULE
#define | I2C0_MODULE
#define | I2C1_MODULE
#define | SPI0_MODULE
#define | UART0_MODULE
#define | UART1_MODULE
#define | PWMCH01_MODULE
#define | PWMCH23_MODULE
#define | PWMCH45_MODULE
#define | ADC_MODULE
#define | ACMP_MODULE
#define | WWDT_MODULE

## Detailed Description

## Macro Definition Documentation

## ◆ ACMP_MODULE

#define ACMP_MODULE

ACMP Module

Definition at line 179 of file clk.h.

## ◆ ADC_MODULE

#define ADC_MODULE

ADC Module

Definition at line 178 of file clk.h.

## ◆ CLK_CLKDIV_ADC

#define CLK_CLKDIV_ADC | ( |  | x | ) | (((x)-1) << 16)

CLKDIV Setting for ADC clock divider. It could be 1~256

Definition at line 115 of file clk.h.

## ◆ CLK_CLKDIV_HCLK

#define CLK_CLKDIV_HCLK | ( |  | x | ) | ((x)-1)

CLKDIV Setting for HCLK clock divider. It could be 1~16

Definition at line 117 of file clk.h.

## ◆ CLK_CLKDIV_UART

#define CLK_CLKDIV_UART | ( |  | x | ) | (((x)-1) << 8)

CLKDIV Setting for UART clock divider. It could be 1~16

Definition at line 116 of file clk.h.

## ◆ CLK_CLKSEL0_HCLKSEL_HIRC

#define CLK_CLKSEL0_HCLKSEL_HIRC 0x07UL

Setting clock source as internal RC clock

Definition at line 60 of file clk.h.

## ◆ CLK_CLKSEL0_HCLKSEL_HXT

#define CLK_CLKSEL0_HCLKSEL_HXT 0x00UL

Setting clock source as external HXT

Definition at line 56 of file clk.h.

## ◆ CLK_CLKSEL0_HCLKSEL_LIRC

#define CLK_CLKSEL0_HCLKSEL_LIRC 0x03UL

Setting clock source as internal 10KHz RC clock

Definition at line 59 of file clk.h.

## ◆ CLK_CLKSEL0_HCLKSEL_LXT

#define CLK_CLKSEL0_HCLKSEL_LXT 0x00UL

Setting clock source as external LXT

Definition at line 57 of file clk.h.

## ◆ CLK_CLKSEL0_HCLKSEL_PLL

#define CLK_CLKSEL0_HCLKSEL_PLL 0x02UL

Setting clock source as PLL

Definition at line 58 of file clk.h.

## ◆ CLK_CLKSEL0_HCLKSEL_XTAL

#define CLK_CLKSEL0_HCLKSEL_XTAL 0x00UL

Setting clock source as external XTAL

Definition at line 55 of file clk.h.

## ◆ CLK_CLKSEL0_STCLKSEL_HCLK

#define CLK_CLKSEL0_STCLKSEL_HCLK 0x08UL

Setting clock source as HCLK

Definition at line 65 of file clk.h.

## ◆ CLK_CLKSEL0_STCLKSEL_HCLK_DIV2

#define CLK_CLKSEL0_STCLKSEL_HCLK_DIV2 0x18UL

Setting clock source as HCLK/2

Definition at line 63 of file clk.h.

## ◆ CLK_CLKSEL0_STCLKSEL_HIRC_DIV2

#define CLK_CLKSEL0_STCLKSEL_HIRC_DIV2 0x38UL

Setting clock source as internal RC clock/2

Definition at line 64 of file clk.h.

## ◆ CLK_CLKSEL0_STCLKSEL_XTAL

#define CLK_CLKSEL0_STCLKSEL_XTAL 0x00UL

Setting clock source as external XTAL

Definition at line 61 of file clk.h.

## ◆ CLK_CLKSEL0_STCLKSEL_XTAL_DIV2

#define CLK_CLKSEL0_STCLKSEL_XTAL_DIV2 0x10UL

Setting clock source as external XTAL/2

Definition at line 62 of file clk.h.

## ◆ CLK_CLKSEL1_ADCSEL_HCLK

#define CLK_CLKSEL1_ADCSEL_HCLK 0x00000008UL

Setting ADC clock source as HCLK

Definition at line 76 of file clk.h.

## ◆ CLK_CLKSEL1_ADCSEL_HIRC

#define CLK_CLKSEL1_ADCSEL_HIRC 0x0000000CUL

Setting ADC clock source as internal RC clock

Definition at line 77 of file clk.h.

## ◆ CLK_CLKSEL1_ADCSEL_PLL

#define CLK_CLKSEL1_ADCSEL_PLL 0x00000004UL

Setting ADC clock source as PLL

Definition at line 75 of file clk.h.

## ◆ CLK_CLKSEL1_ADCSEL_XTAL

#define CLK_CLKSEL1_ADCSEL_XTAL 0x00000000UL

Setting ADC clock source as external XTAL

Definition at line 74 of file clk.h.

## ◆ CLK_CLKSEL1_PWMCH01SEL_HCLK

#define CLK_CLKSEL1_PWMCH01SEL_HCLK 0x20000000UL

Setting PWM01 clock source as external HCLK

Definition at line 94 of file clk.h.

## ◆ CLK_CLKSEL1_PWMCH23SEL_HCLK

#define CLK_CLKSEL1_PWMCH23SEL_HCLK 0x80000000UL

Setting PWM23 clock source as external HCLK

Definition at line 95 of file clk.h.

## ◆ CLK_CLKSEL1_SPISEL_HCLK

#define CLK_CLKSEL1_SPISEL_HCLK 0x00000010UL

Setting SPI clock source as HCLK

Definition at line 79 of file clk.h.

## ◆ CLK_CLKSEL1_SPISEL_PLL

#define CLK_CLKSEL1_SPISEL_PLL 0x00000020UL

Setting SPI clock source as PLL

Definition at line 80 of file clk.h.

## ◆ CLK_CLKSEL1_SPISEL_XTAL

#define CLK_CLKSEL1_SPISEL_XTAL 0x00000000UL

Setting SPI clock source as HXT or LXT

Definition at line 78 of file clk.h.

## ◆ CLK_CLKSEL1_TMR0SEL_HCLK

#define CLK_CLKSEL1_TMR0SEL_HCLK 0x00000200UL

Setting Timer 0 clock source as HCLK

Definition at line 83 of file clk.h.

## ◆ CLK_CLKSEL1_TMR0SEL_HIRC

#define CLK_CLKSEL1_TMR0SEL_HIRC 0x00000700UL

Setting Timer 0 clock source as internal RC clock

Definition at line 85 of file clk.h.

## ◆ CLK_CLKSEL1_TMR0SEL_LIRC

#define CLK_CLKSEL1_TMR0SEL_LIRC 0x00000100UL

Setting Timer 0 clock source as internal 10KHz RC clock

Definition at line 82 of file clk.h.

## ◆ CLK_CLKSEL1_TMR0SEL_TM0

#define CLK_CLKSEL1_TMR0SEL_TM0 0x00000300UL

Setting Timer 0 clock source as external trigger

Definition at line 84 of file clk.h.

## ◆ CLK_CLKSEL1_TMR0SEL_XTAL

#define CLK_CLKSEL1_TMR0SEL_XTAL 0x00000000UL

Setting Timer 0 clock source as external XTAL

Definition at line 81 of file clk.h.

## ◆ CLK_CLKSEL1_TMR1SEL_HCLK

#define CLK_CLKSEL1_TMR1SEL_HCLK 0x00002000UL

Setting Timer 1 clock source as HCLK

Definition at line 88 of file clk.h.

## ◆ CLK_CLKSEL1_TMR1SEL_HIRC

#define CLK_CLKSEL1_TMR1SEL_HIRC 0x00007000UL

Setting Timer 1 clock source as internal RC clock

Definition at line 90 of file clk.h.

## ◆ CLK_CLKSEL1_TMR1SEL_LIRC

#define CLK_CLKSEL1_TMR1SEL_LIRC 0x00001000UL

Setting Timer 1 clock source as internal 10KHz RC clock

Definition at line 87 of file clk.h.

## ◆ CLK_CLKSEL1_TMR1SEL_TM1

#define CLK_CLKSEL1_TMR1SEL_TM1 0x00003000UL

Setting Timer 1 clock source as external trigger

Definition at line 89 of file clk.h.

## ◆ CLK_CLKSEL1_TMR1SEL_XTAL

#define CLK_CLKSEL1_TMR1SEL_XTAL 0x00000000UL

Setting Timer 1 clock source as external XTAL

Definition at line 86 of file clk.h.

## ◆ CLK_CLKSEL1_UARTSEL_HIRC

#define CLK_CLKSEL1_UARTSEL_HIRC 0x02000000UL

Setting UART clock source as external internal RC clock

Definition at line 93 of file clk.h.

## ◆ CLK_CLKSEL1_UARTSEL_PLL

#define CLK_CLKSEL1_UARTSEL_PLL 0x01000000UL

Setting UART clock source as external PLL

Definition at line 92 of file clk.h.

## ◆ CLK_CLKSEL1_UARTSEL_XTAL

#define CLK_CLKSEL1_UARTSEL_XTAL 0x00000000UL

Setting UART clock source as external XTAL

Definition at line 91 of file clk.h.

## ◆ CLK_CLKSEL1_WDTSEL_HCLK_DIV2048

#define CLK_CLKSEL1_WDTSEL_HCLK_DIV2048 0x00000002UL

Setting WDT clock source as HCLK/2048

Definition at line 71 of file clk.h.

## ◆ CLK_CLKSEL1_WDTSEL_IRC10K

#define CLK_CLKSEL1_WDTSEL_IRC10K 0x00000003UL

Setting WDT clock source as internal 10KHz RC clock

Definition at line 72 of file clk.h.

## ◆ CLK_CLKSEL1_WDTSEL_LIRC

#define CLK_CLKSEL1_WDTSEL_LIRC 0x00000003UL

Setting WDT clock source as internal 10KHz RC clock

Definition at line 73 of file clk.h.

## ◆ CLK_CLKSEL1_WDTSEL_XTAL

#define CLK_CLKSEL1_WDTSEL_XTAL 0x00000000UL

Setting WDT clock source as external XTAL

Definition at line 70 of file clk.h.

## ◆ CLK_CLKSEL2_CLKOSEL_HCLK

#define CLK_CLKSEL2_CLKOSEL_HCLK 0x00000008UL

Setting CLKODIV clock source as HCLK

Definition at line 105 of file clk.h.

## ◆ CLK_CLKSEL2_CLKOSEL_HIRC

#define CLK_CLKSEL2_CLKOSEL_HIRC 0x0000000CUL

Setting CLKODIV clock source as internal RC clock

Definition at line 106 of file clk.h.

## ◆ CLK_CLKSEL2_CLKOSEL_HXT

#define CLK_CLKSEL2_CLKOSEL_HXT 0x00000000UL

Setting CLKODIV clock source as external XTAL

Definition at line 102 of file clk.h.

## ◆ CLK_CLKSEL2_CLKOSEL_LIRC

#define CLK_CLKSEL2_CLKOSEL_LIRC 0x00000004UL

Setting CLKODIV clock source as LIRC

Definition at line 104 of file clk.h.

## ◆ CLK_CLKSEL2_CLKOSEL_LXT

#define CLK_CLKSEL2_CLKOSEL_LXT 0x00000000UL

Setting CLKODIV clock source as external XTAL

Definition at line 103 of file clk.h.

## ◆ CLK_CLKSEL2_CLKOSEL_XTAL

#define CLK_CLKSEL2_CLKOSEL_XTAL 0x00000000UL

Setting CLKODIV clock source as external XTAL

Definition at line 101 of file clk.h.

## ◆ CLK_CLKSEL2_PWMCH45SEL_HCLK

#define CLK_CLKSEL2_PWMCH45SEL_HCLK 0x00000020UL

Setting PWMCH45 clock source as HCLK

Definition at line 107 of file clk.h.

## ◆ CLK_CLKSEL2_WWDTSEL_HCLK_DIV2048

#define CLK_CLKSEL2_WWDTSEL_HCLK_DIV2048 0x00020000UL

Setting WWDT clock source as HCLK/2048

Definition at line 108 of file clk.h.

## ◆ CLK_CLKSEL2_WWDTSEL_LIRC

#define CLK_CLKSEL2_WWDTSEL_LIRC 0x00030000UL

Setting WWDT clock source as internal RC clock

Definition at line 109 of file clk.h.

## ◆ CLK_PLLCTL_100MHz_HIRC

#define CLK_PLLCTL_100MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(4) | CLK_PLLCTL_NF( 36) | CLK_PLLCTL_NO_2)

Predefined PLLCTL setting for 99.532800MHz PLL output with HIRC(22.1184MHz X'tal)

Definition at line 138 of file clk.h.

## ◆ CLK_PLLCTL_100MHz_HXT

#define CLK_PLLCTL_100MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(3) | CLK_PLLCTL_NF( 50) | CLK_PLLCTL_NO_2)

Predefined PLLCTL setting for 100MHz PLL output with HXT(12MHz X'tal)

Definition at line 134 of file clk.h.

## ◆ CLK_PLLCTL_72MHz_HIRC

#define CLK_PLLCTL_72MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(4) | CLK_PLLCTL_NF( 26) | CLK_PLLCTL_NO_2)

Predefined PLLCTL setting for 71.884800MHz PLL output with HIRC(22.1184MHz X'tal)

Definition at line 136 of file clk.h.

## ◆ CLK_PLLCTL_72MHz_HXT

#define CLK_PLLCTL_72MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(2) | CLK_PLLCTL_NF( 24) | CLK_PLLCTL_NO_2)

Predefined PLLCTL setting for 72MHz PLL output with HXT(12MHz X'tal)

Definition at line 132 of file clk.h.

## ◆ CLK_PLLCTL_96MHz_HIRC

#define CLK_PLLCTL_96MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(13)| CLK_PLLCTL_NF(113) | CLK_PLLCTL_NO_2)

Predefined PLLCTL setting for 96.129968MHz PLL output with HIRC(22.1184MHz X'tal)

Definition at line 137 of file clk.h.

## ◆ CLK_PLLCTL_96MHz_HXT

#define CLK_PLLCTL_96MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(2) | CLK_PLLCTL_NF( 32) | CLK_PLLCTL_NO_2)

Predefined PLLCTL setting for 96MHz PLL output with HXT(12MHz X'tal)

Definition at line 133 of file clk.h.

## ◆ CLK_PLLCTL_NF

#define CLK_PLLCTL_NF | ( |  | x | ) | ((x)-2)

x must be constant and 2 <= x <= 513. 200MHz < FIN*NF/NR < 500MHz. (FIN*NF/NR > 250MHz is preferred.)

Definition at line 125 of file clk.h.

## ◆ CLK_PLLCTL_NO_1

#define CLK_PLLCTL_NO_1 0x0000UL

For output divider is 1

Definition at line 128 of file clk.h.

## ◆ CLK_PLLCTL_NO_2

#define CLK_PLLCTL_NO_2 0x4000UL

For output divider is 2

Definition at line 129 of file clk.h.

## ◆ CLK_PLLCTL_NO_4

#define CLK_PLLCTL_NO_4 0xC000UL

For output divider is 4

Definition at line 130 of file clk.h.

## ◆ CLK_PLLCTL_NR

#define CLK_PLLCTL_NR | ( |  | x | ) | (((x)-2)<<9)

x must be constant and 2 <= x <= 33. 1.6MHz < FIN/NR < 16MHz

Definition at line 126 of file clk.h.

## ◆ CLK_PLLCTL_PLLSRC_HIRC

#define CLK_PLLCTL_PLLSRC_HIRC 0x00080000UL

For PLL clock source is HIRC. 3.2MHz < FIN < 150MHz

Definition at line 123 of file clk.h.

## ◆ CLK_PLLCTL_PLLSRC_HXT

#define CLK_PLLCTL_PLLSRC_HXT 0x00000000UL

For PLL clock source is HXT. 3.2MHz < FIN < 150MHz

Definition at line 122 of file clk.h.

## ◆ CLK_PWRCTL_XTL12M

#define CLK_PWRCTL_XTL12M 0x01UL

Setting External Crystal Oscillator as 12MHz

Definition at line 47 of file clk.h.

## ◆ CLK_PWRCTL_XTL32K

#define CLK_PWRCTL_XTL32K 0x02UL

Setting External Crystal Oscillator as 32KHz

Definition at line 49 of file clk.h.

## ◆ CLK_PWRCTL_XTLEN_HXT

#define CLK_PWRCTL_XTLEN_HXT 0x01UL

Setting External Crystal Oscillator as 12MHz

Definition at line 48 of file clk.h.

## ◆ CLK_PWRCTL_XTLEN_LXT

#define CLK_PWRCTL_XTLEN_LXT 0x02UL

Setting External Crystal Oscillator as 32KHz

Definition at line 50 of file clk.h.

## ◆ CLKO_MODULE

#define CLKO_MODULE

CLKO Module

Definition at line 169 of file clk.h.

## ◆ FREQ_100MHZ

#define FREQ_100MHZ 100000000

Definition at line 38 of file clk.h.

## ◆ FREQ_200MHZ

#define FREQ_200MHZ 200000000

Definition at line 39 of file clk.h.

## ◆ FREQ_250MHZ

#define FREQ_250MHZ 250000000

Definition at line 40 of file clk.h.

## ◆ FREQ_25MHZ

#define FREQ_25MHZ 25000000

Definition at line 35 of file clk.h.

## ◆ FREQ_500MHZ

#define FREQ_500MHZ 500000000

Definition at line 41 of file clk.h.

## ◆ FREQ_50MHZ

#define FREQ_50MHZ 50000000

Definition at line 36 of file clk.h.

## ◆ FREQ_72MHZ

#define FREQ_72MHZ 72000000

Definition at line 37 of file clk.h.

## ◆ I2C0_MODULE

#define I2C0_MODULE

I2C0 Module

Definition at line 170 of file clk.h.

## ◆ I2C1_MODULE

#define I2C1_MODULE

I2C1 Module

Definition at line 171 of file clk.h.

## ◆ ISP_MODULE

#define ISP_MODULE

ISP Module

Definition at line 165 of file clk.h.

## ◆ MODULE_APBCLK

#define MODULE_APBCLK | ( |  | x | ) | ((x >>31) & 0x1)

Calculate APBCLK offset on MODULE index

Definition at line 143 of file clk.h.

## ◆ MODULE_APBCLK_ENC

#define MODULE_APBCLK_ENC | ( |  | x | ) | (((x) & 0x01) << 31)

MODULE index, 0x0:AHBCLK, 0x1:APBCLK

Definition at line 154 of file clk.h.

## ◆ MODULE_CLKDIV

#define MODULE_CLKDIV | ( |  | x | ) | ((x >>18) & 0x3)

Calculate APBCLK CLKDIV on MODULE index

Definition at line 147 of file clk.h.

## ◆ MODULE_CLKDIV_ENC

#define MODULE_CLKDIV_ENC | ( |  | x | ) | (((x) & 0x03) << 18)

APBCLK CLKDIV on MODULE index, 0x0:CLKDIV

Definition at line 158 of file clk.h.

## ◆ MODULE_CLKDIV_Msk

#define MODULE_CLKDIV_Msk | ( |  | x | ) | ((x >>10) & 0xff)

Calculate CLKDIV mask offset on MODULE index

Definition at line 148 of file clk.h.

## ◆ MODULE_CLKDIV_Msk_ENC

#define MODULE_CLKDIV_Msk_ENC | ( |  | x | ) | (((x) & 0xff) << 10)

CLKDIV mask offset on MODULE index

Definition at line 159 of file clk.h.

## ◆ MODULE_CLKDIV_Pos

#define MODULE_CLKDIV_Pos | ( |  | x | ) | ((x >>5 ) & 0x1f)

Calculate CLKDIV position offset on MODULE index

Definition at line 149 of file clk.h.

## ◆ MODULE_CLKDIV_Pos_ENC

#define MODULE_CLKDIV_Pos_ENC | ( |  | x | ) | (((x) & 0x1f) << 5)

CLKDIV position offset on MODULE index

Definition at line 160 of file clk.h.

## ◆ MODULE_CLKSEL

#define MODULE_CLKSEL | ( |  | x | ) | ((x >>29) & 0x3)

Calculate CLKSEL offset on MODULE index

Definition at line 144 of file clk.h.

## ◆ MODULE_CLKSEL_ENC

#define MODULE_CLKSEL_ENC | ( |  | x | ) | (((x) & 0x03) << 29)

CLKSEL offset on MODULE index, 0x0:CLKSEL0, 0x1:CLKSEL1 0x3 CLKSEL2

Definition at line 155 of file clk.h.

## ◆ MODULE_CLKSEL_Msk

#define MODULE_CLKSEL_Msk | ( |  | x | ) | ((x >>25) & 0xf)

Calculate CLKSEL mask offset on MODULE index

Definition at line 145 of file clk.h.

## ◆ MODULE_CLKSEL_Msk_ENC

#define MODULE_CLKSEL_Msk_ENC | ( |  | x | ) | (((x) & 0x0f) << 25)

CLKSEL mask offset on MODULE index

Definition at line 156 of file clk.h.

## ◆ MODULE_CLKSEL_Pos

#define MODULE_CLKSEL_Pos | ( |  | x | ) | ((x >>20) & 0x1f)

Calculate CLKSEL position offset on MODULE index

Definition at line 146 of file clk.h.

## ◆ MODULE_CLKSEL_Pos_ENC

#define MODULE_CLKSEL_Pos_ENC | ( |  | x | ) | (((x) & 0x1f) << 20)

CLKSEL position offset on MODULE index

Definition at line 157 of file clk.h.

## ◆ MODULE_IP_EN_Pos

#define MODULE_IP_EN_Pos | ( |  | x | ) | ((x >>0 ) & 0x1f)

Calculate APBCLK offset on MODULE index

Definition at line 150 of file clk.h.

## ◆ MODULE_IP_EN_Pos_ENC

#define MODULE_IP_EN_Pos_ENC | ( |  | x | ) | (((x) & 0x1f) << 0)

APBCLK offset on MODULE index

Definition at line 161 of file clk.h.

## ◆ MODULE_NoMsk

#define MODULE_NoMsk 0x0

Not mask on MODULE index

Definition at line 151 of file clk.h.

## ◆ NA

#define NA MODULE_NoMsk

Not Available

Definition at line 152 of file clk.h.

## ◆ PWMCH01_MODULE

#define PWMCH01_MODULE

PWMCH01 Module

Definition at line 175 of file clk.h.

## ◆ PWMCH23_MODULE

#define PWMCH23_MODULE

PWMCH23 Module

Definition at line 176 of file clk.h.

## ◆ PWMCH45_MODULE

#define PWMCH45_MODULE

PWMCH45 Module

Definition at line 177 of file clk.h.

## ◆ SPI0_MODULE

#define SPI0_MODULE

SPI Module

Definition at line 172 of file clk.h.

## ◆ TMR0_MODULE

#define TMR0_MODULE

TMR0 Module

Definition at line 167 of file clk.h.

## ◆ TMR1_MODULE

#define TMR1_MODULE

TMR1 Module

Definition at line 168 of file clk.h.

## ◆ UART0_MODULE

#define UART0_MODULE

UART0 Module

Definition at line 173 of file clk.h.

## ◆ UART1_MODULE

#define UART1_MODULE

UART1 Module

Definition at line 174 of file clk.h.

## ◆ WDT_MODULE

#define WDT_MODULE

WDT Module

Definition at line 166 of file clk.h.

## ◆ WWDT_MODULE

#define WWDT_MODULE

WWDT Module

Definition at line 180 of file clk.h.