| NUC029FAE BSP V3.01.002 The Board Support Package for NUC029FAE

NUC029FAE.h
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1 /**************************************************************************/
55 #ifndef __NUC029FAE_H__
56 #define __NUC029FAE_H__
57
58 #ifdef __cplusplus
59 extern "C" {
60 #endif
61
62 /******************************************************************************/
63 /* Processor and Core Peripherals */
64 /******************************************************************************/
73 typedef enum IRQn
74 {
75 /****** Cortex-M0 Processor Exceptions Numbers *****************************************/
76
77 NonMaskableInt_IRQn = -14,
78 HardFault_IRQn = -13,
79 SVCall_IRQn = -5,
80 PendSV_IRQn = -2,
81 SysTick_IRQn = -1,
83 /****** NUC029FAE specific Interrupt Numbers ***********************************************/
84
85 BOD_IRQn = 0,
86 WDT_IRQn = 1,
87 EINT0_IRQn = 2,
88 EINT1_IRQn = 3,
89 GPIO01_IRQn = 4,
90 GPIO234_IRQn = 5,
91 PWM_IRQn = 6,
92 FB_IRQn = 7,
93 TMR0_IRQn = 8,
94 TMR1_IRQn = 9,
95 UART_IRQn = 12,
96 SPI_IRQn = 14,
97 GPIO5_IRQn = 16,
98 HIRC_IRQn = 17,
99 I2C_IRQn = 18,
100 ACMP_IRQn = 25,
101 PDWU_IRQn = 28,
102 ADC_IRQn = 29
104 } IRQn_Type;
105
106
107 /*
108 * ==========================================================================
109 * ----------- Processor and Core Peripheral Section ------------------------
110 * ==========================================================================
111 */
112
113
114 /* Configuration of the Cortex-M0 Processor and Core Peripherals */
115 #define __CM0_REV 0x0201
116 #define __NVIC_PRIO_BITS 2
117 #define __Vendor_SysTickConfig 0
118 #define __MPU_PRESENT 0
119 #define __FPU_PRESENT 0
121 /* end of group NUC029FAE_CMSIS */
122
123
124 #include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
125 #include "system_NUC029FAE.h" /* NUC029FAE System include file */
126 #include <stdint.h>
127
128 /******************************************************************************/
129 /* Device Specific Peripheral registers structures */
130 /******************************************************************************/
136 #if defined ( __CC_ARM )
137 #pragma anon_unions
138 #endif
139
140
141 /*---------------------- Analog Comparator Controller -------------------------*/
146 typedef struct
147 {
148 __IO uint32_t CMPCR[2];
149 __IO uint32_t CMPSR;
150 __IO uint32_t CMPRVCR;
151 } ACMP_T;
153 /* CMPCR Bit Field Definitions */
154 #define ACMP_CMPCR_CPPSEL_Pos 29
155 #define ACMP_CMPCR_CPPSEL_Msk (3ul << ACMP_CMPCR_CPPSEL_Pos)
157 #define ACMP_CMPCR_FALLING_Pos 9
158 #define ACMP_CMPCR_FALLING_Msk (1ul << ACMP_CMPCR_FALLING_Pos)
160 #define ACMP_CMPCR_RISING_Pos 8
161 #define ACMP_CMPCR_RISING_Msk (1ul << ACMP_CMPCR_RISING_Pos)
163 #define ACMP_CMPCR_NEGSEL_Pos 4
164 #define ACMP_CMPCR_NEGSEL_Msk (1ul << ACMP_CMPCR_NEGSEL_Pos)
166 #define ACMP_CMPCR_HYSEN_Pos 2
167 #define ACMP_CMPCR_HYSEN_Msk (1ul << ACMP_CMPCR_HYSEN_Pos)
169 #define ACMP_CMPCR_ACMPIE_Pos 1
170 #define ACMP_CMPCR_ACMPIE_Msk (1ul << ACMP_CMPCR_ACMPIE_Pos)
172 #define ACMP_CMPCR_ACMPEN_Pos 0
173 #define ACMP_CMPCR_ACMPEN_Msk (1ul << ACMP_CMPCR_ACMPEN_Pos)
175 /* CMPSR Bit Field Definitions */
176 #define ACMP_CMPSR_ACMPCO1_Pos 3
177 #define ACMP_CMPSR_ACMPCO1_Msk (1ul << ACMP_CMPSR_ACMPCO1_Pos)
179 #define ACMP_CMPSR_ACMPCO0_Pos 2
180 #define ACMP_CMPSR_ACMPCO0_Msk (1ul << ACMP_CMPSR_ACMPCO0_Pos)
182 #define ACMP_CMPSR_ACMPF1_Pos 1
183 #define ACMP_CMPSR_ACMPF1_Msk (1ul << ACMP_CMPSR_ACMPF1_Pos)
185 #define ACMP_CMPSR_ACMPF0_Pos 0
186 #define ACMP_CMPSR_ACMPF0_Msk (1ul << ACMP_CMPSR_ACMPF0_Pos)
188 #define ACMP_CMPRVCR_OUT_SEL_Pos 7
189 #define ACMP_CMPRVCR_OUT_SEL_Msk (1ul << ACMP_CMPRVCR_OUT_SEL_Pos)
191 #define ACMP_CMPRVCR_CRVS_Pos 0
192 #define ACMP_CMPRVCR_CRVS_Msk (0xFul << ACMP_CMPRVCR_CRVS_Pos)
193 /* end of group NUC029FAE_ACMP */
195
196
197 /*---------------------------- Clock Controller ------------------------------*/
198
203 typedef struct
204 {
257 __IO uint32_t PWRCON;
258
270 __IO uint32_t AHBCLK;
271
319 __IO uint32_t APBCLK;
320
342 __IO uint32_t CLKSTATUS;
343
373 __IO uint32_t CLKSEL0;
374
417 __IO uint32_t CLKSEL1;
418
433 __IO uint32_t CLKDIV;
434
451 __IO uint32_t CLKSEL2;
455 uint32_t RESERVED0;
456
473 __IO uint32_t FRQDIV;
474 } CLK_T;
476 /* CLK PWRCON Bit Field Definitions */
477 #define CLK_PWRCON_PD_32K_Pos 9
478 #define CLK_PWRCON_PD_32K_Msk (1ul << CLK_PWRCON_PD_32K_Pos)
480 #define CLK_PWRCON_PWR_DOWN_EN_Pos 7
481 #define CLK_PWRCON_PWR_DOWN_EN_Msk (1ul << CLK_PWRCON_PWR_DOWN_EN_Pos)
483 #define CLK_PWRCON_PD_WU_STS_Pos 6
484 #define CLK_PWRCON_PD_WU_STS_Msk (1ul << CLK_PWRCON_PD_WU_STS_Pos)
486 #define CLK_PWRCON_WINT_EN_Pos 5
487 #define CLK_PWRCON_WINT_EN_Msk (1ul << CLK_PWRCON_WINT_EN_Pos)
489 #define CLK_PWRCON_WU_DLY_Pos 4
490 #define CLK_PWRCON_WU_DLY_Msk (1ul << CLK_PWRCON_WU_DLY_Pos)
492 #define CLK_PWRCON_OSC10K_EN_Pos 3
493 #define CLK_PWRCON_OSC10K_EN_Msk (1ul << CLK_PWRCON_OSC10K_EN_Pos)
494 #define CLK_PWRCON_IRC10K_EN_Pos 3
495 #define CLK_PWRCON_IRC10K_EN_Msk (1ul << CLK_PWRCON_OSC10K_EN_Pos)
496 #define CLK_PWRCON_LIRC_EN_Pos 3
497 #define CLK_PWRCON_LIRC_EN_Msk (1ul << CLK_PWRCON_LIRC_EN_Pos)
499 #define CLK_PWRCON_OSC22M_EN_Pos 2
500 #define CLK_PWRCON_OSC22M_EN_Msk (1ul << CLK_PWRCON_OSC22M_EN_Pos)
501 #define CLK_PWRCON_IRC22M_EN_Pos 2
502 #define CLK_PWRCON_IRC22M_EN_Msk (1ul << CLK_PWRCON_OSC22M_EN_Pos)
503 #define CLK_PWRCON_HIRC_EN_Pos 2
504 #define CLK_PWRCON_HIRC_EN_Msk (1ul << CLK_PWRCON_HIRC_EN_Pos)
506 #define CLK_PWRCON_XTLCLK_EN_Pos 0
507 #define CLK_PWRCON_XTLCLK_EN_Msk (3ul << CLK_PWRCON_XTLCLK_EN_Pos)
509 /* CLK AHBCLK Bit Field Definitions */
510 #define CLK_AHBCLK_ISP_EN_Pos 2
511 #define CLK_AHBCLK_ISP_EN_Msk (1ul << CLK_AHBCLK_ISP_EN_Pos)
513 /* CLK APBCLK Bit Field Definitions */
514 #define CLK_APBCLK_CMP_EN_Pos 30
515 #define CLK_APBCLK_CMP_EN_Msk (1ul << CLK_APBCLK_CMP_EN_Pos)
517 #define CLK_APBCLK_ADC_EN_Pos 28
518 #define CLK_APBCLK_ADC_EN_Msk (1ul << CLK_APBCLK_ADC_EN_Pos)
520 #define CLK_APBCLK_PWM45_EN_Pos 22
521 #define CLK_APBCLK_PWM45_EN_Msk (1ul << CLK_APBCLK_PWM45_EN_Pos)
523 #define CLK_APBCLK_PWM23_EN_Pos 21
524 #define CLK_APBCLK_PWM23_EN_Msk (1ul << CLK_APBCLK_PWM23_EN_Pos)
526 #define CLK_APBCLK_PWM01_EN_Pos 20
527 #define CLK_APBCLK_PWM01_EN_Msk (1ul << CLK_APBCLK_PWM01_EN_Pos)
529 #define CLK_APBCLK_UART_EN_Pos 16
530 #define CLK_APBCLK_UART_EN_Msk (1ul << CLK_APBCLK_UART_EN_Pos)
532 #define CLK_APBCLK_SPI_EN_Pos 12
533 #define CLK_APBCLK_SPI_EN_Msk (1ul << CLK_APBCLK_SPI_EN_Pos)
535 #define CLK_APBCLK_I2C_EN_Pos 8
536 #define CLK_APBCLK_I2C_EN_Msk (1ul << CLK_APBCLK_I2C_EN_Pos)
538 #define CLK_APBCLK_FDIV_EN_Pos 6
539 #define CLK_APBCLK_FDIV_EN_Msk (1ul << CLK_APBCLK_FDIV_EN_Pos)
541 #define CLK_APBCLK_TMR1_EN_Pos 3
542 #define CLK_APBCLK_TMR1_EN_Msk (1ul << CLK_APBCLK_TMR1_EN_Pos)
544 #define CLK_APBCLK_TMR0_EN_Pos 2
545 #define CLK_APBCLK_TMR0_EN_Msk (1ul << CLK_APBCLK_TMR0_EN_Pos)
547 #define CLK_APBCLK_WDT_EN_Pos 0
548 #define CLK_APBCLK_WDT_EN_Msk (1ul << CLK_APBCLK_WDT_EN_Pos)
550 /* CLK CLKSTATUS Bit Field Definitions */
551 #define CLK_CLKSTATUS_CLK_SW_FAIL_Pos 7
552 #define CLK_CLKSTATUS_CLK_SW_FAIL_Msk (1ul << CLK_CLKSTATUS_CLK_SW_FAIL_Pos)
554 #define CLK_CLKSTATUS_OSC22M_STB_Pos 4
555 #define CLK_CLKSTATUS_OSC22M_STB_Msk (1ul << CLK_CLKSTATUS_OSC22M_STB_Pos)
556 #define CLK_CLKSTATUS_IRC22M_STB_Pos 4
557 #define CLK_CLKSTATUS_IRC22M_STB_Msk (1ul << CLK_CLKSTATUS_OSC22M_STB_Pos)
558 #define CLK_CLKSTATUS_HIRC_STB_Pos 4
559 #define CLK_CLKSTATUS_HIRC_STB_Msk (1ul << CLK_CLKSTATUS_HIRC_STB_Pos)
561 #define CLK_CLKSTATUS_OSC10K_STB_Pos 3
562 #define CLK_CLKSTATUS_OSC10K_STB_Msk (1ul << CLK_CLKSTATUS_OSC10K_STB_Pos)
563 #define CLK_CLKSTATUS_IRC10K_STB_Pos 3
564 #define CLK_CLKSTATUS_IRC10K_STB_Msk (1ul << CLK_CLKSTATUS_OSC10K_STB_Pos)
565 #define CLK_CLKSTATUS_LIRC_STB_Pos 3
566 #define CLK_CLKSTATUS_LIRC_STB_Msk (1ul << CLK_CLKSTATUS_LIRC_STB_Pos)
568 #define CLK_CLKSTATUS_XTL_STB_Pos 0
569 #define CLK_CLKSTATUS_XTL_STB_Msk (1ul << CLK_CLKSTATUS_XTL_STB_Pos)
570 #define CLK_CLKSTATUS_HXT_STB_Pos 0
571 #define CLK_CLKSTATUS_HXT_STB_Msk (1ul << CLK_CLKSTATUS_HXT_STB_Pos)
572 #define CLK_CLKSTATUS_LXT_STB_Pos 0
573 #define CLK_CLKSTATUS_LXT_STB_Msk (1ul << CLK_CLKSTATUS_LXT_STB_Pos)
575 /* CLK CLKSEL0 Bit Field Definitions */
576 #define CLK_CLKSEL0_STCLK_S_Pos 3
577 #define CLK_CLKSEL0_STCLK_S_Msk (7ul << CLK_CLKSEL0_STCLK_S_Pos)
579 #define CLK_CLKSEL0_HCLK_S_Pos 0
580 #define CLK_CLKSEL0_HCLK_S_Msk (7ul << CLK_CLKSEL0_HCLK_S_Pos)
582 /* CLK CLKSEL1 Bit Field Definitions */
583 #define CLK_CLKSEL1_PWM23_S_Pos 30
584 #define CLK_CLKSEL1_PWM23_S_Msk (3ul << CLK_CLKSEL1_PWM23_S_Pos)
586 #define CLK_CLKSEL1_PWM01_S_Pos 28
587 #define CLK_CLKSEL1_PWM01_S_Msk (3ul << CLK_CLKSEL1_PWM01_S_Pos)
589 #define CLK_CLKSEL1_UART_S_Pos 24
590 #define CLK_CLKSEL1_UART_S_Msk (3ul << CLK_CLKSEL1_UART_S_Pos)
592 #define CLK_CLKSEL1_TMR1_S_Pos 12
593 #define CLK_CLKSEL1_TMR1_S_Msk (7ul << CLK_CLKSEL1_TMR1_S_Pos)
595 #define CLK_CLKSEL1_TMR0_S_Pos 8
596 #define CLK_CLKSEL1_TMR0_S_Msk (7ul << CLK_CLKSEL1_TMR0_S_Pos)
598 #define CLK_CLKSEL1_SPI_S_Pos 4
599 #define CLK_CLKSEL1_SPI_S_Msk (1ul << CLK_CLKSEL1_SPI_S_Pos)
600 #define CLK_CLKSEL1_ADC_S_Pos 2
601 #define CLK_CLKSEL1_ADC_S_Msk (3ul << CLK_CLKSEL1_ADC_S_Pos)
603 #define CLK_CLKSEL1_WDT_S_Pos 0
604 #define CLK_CLKSEL1_WDT_S_Msk (3ul << CLK_CLKSEL1_WDT_S_Pos)
606 /* CLK CLKSEL2 Bit Field Definitions */
607 #define CLK_CLKSEL2_PWM45_S_Pos 4
608 #define CLK_CLKSEL2_PWM45_S_Msk (3ul << CLK_CLKSEL2_PWM45_S_Pos)
610 #define CLK_CLKSEL2_FRQDIV_S_Pos 2
611 #define CLK_CLKSEL2_FRQDIV_S_Msk (3ul << CLK_CLKSEL2_FRQDIV_S_Pos)
613 /* CLK CLKDIV Bit Field Definitions */
614 #define CLK_CLKDIV_ADC_N_Pos 16
615 #define CLK_CLKDIV_ADC_N_Msk (0xFFul << CLK_CLKDIV_ADC_N_Pos)
617 #define CLK_CLKDIV_UART_N_Pos 8
618 #define CLK_CLKDIV_UART_N_Msk (0xFul << CLK_CLKDIV_UART_N_Pos)
620 #define CLK_CLKDIV_HCLK_N_Pos 0
621 #define CLK_CLKDIV_HCLK_N_Msk (0xFul << CLK_CLKDIV_HCLK_N_Pos)
623 /* CLK FRQDIV Bit Field Definitions */
624 #define CLK_FRQDIV_DIVIDER1_Pos 5
625 #define CLK_FRQDIV_DIVIDER1_Msk (1ul << CLK_FRQDIV_DIVIDER_EN_Pos)
627 #define CLK_FRQDIV_DIVIDER_EN_Pos 4
628 #define CLK_FRQDIV_DIVIDER_EN_Msk (1ul << CLK_FRQDIV_DIVIDER_EN_Pos)
630 #define CLK_FRQDIV_FSEL_Pos 0
631 #define CLK_FRQDIV_FSEL_Msk (0xFul << CLK_FRQDIV_FSEL_Pos)
632 /* end of group CLK */
634
635
636 /*---------------------- Analog to Digital Converter -------------------------*/
637
642 typedef struct
643 {
644 __IO uint32_t ADDR;
645 uint32_t RESERVED0[7];
646 __IO uint32_t ADCR;
647 __IO uint32_t ADCHER;
648 __IO uint32_t ADCMPR[2];
649 __IO uint32_t ADSR;
650 __IO uint32_t ADTDCR;
651 __IO uint32_t ADSAMP;
652 } ADC_T;
654 /* ADDR Bit Field Definitions */
655 #define ADC_ADDR_VALID_Pos 17
656 #define ADC_ADDR_VALID_Msk (1ul << ADC_ADDR_VALID_Pos)
658 #define ADC_ADDR_OVERRUN_Pos 16
659 #define ADC_ADDR_OVERRUN_Msk (1ul << ADC_ADDR_OVERRUN_Pos)
661 #define ADC_ADDR_RSLT_Pos 0
662 #define ADC_ADDR_RSLT_Msk (0x3FFul << ADC_ADDR_RSLT_Pos)
664 /* ADCR Bit Field Definitions */
665 #define ADC_ADCR_ADST_Pos 11
666 #define ADC_ADCR_ADST_Msk (1ul << ADC_ADCR_ADST_Pos)
668 #define ADC_ADCR_TRGEN_Pos 8
669 #define ADC_ADCR_TRGEN_Msk (1ul << ADC_ADCR_TRGEN_Pos)
671 #define ADC_ADCR_TRGCOND_Pos 6
672 #define ADC_ADCR_TRGCOND_Msk (1ul << ADC_ADCR_TRGCOND_Pos)
674 #define ADC_ADCR_TRGS_Pos 4
675 #define ADC_ADCR_TRGS_Msk (3ul << ADC_ADCR_TRGS_Pos)
677 #define ADC_ADCR_ADIE_Pos 1
678 #define ADC_ADCR_ADIE_Msk (1ul << ADC_ADCR_ADIE_Pos)
680 #define ADC_ADCR_ADEN_Pos 0
681 #define ADC_ADCR_ADEN_Msk (1ul << ADC_ADCR_ADEN_Pos)
683 /* ADCHER Bit Field Definitions */
684 #define ADC_ADCHER_PRESEL_Pos 8
685 #define ADC_ADCHER_PRESEL_Msk (1ul << ADC_ADCHER_PRESEL_Pos)
687 #define ADC_ADCHER_CHEN_Pos 0
688 #define ADC_ADCHER_CHEN_Msk (0xFFul << ADC_ADCHER_CHEN_Pos)
690 /* ADCMPR Bit Field Definitions */
691 #define ADC_ADCMPR_CMPD_Pos 16
692 #define ADC_ADCMPR_CMPD_Msk (0x3FFul << ADC_ADCMPR_CMPD_Pos)
694 #define ADC_ADCMPR_CMPMATCNT_Pos 8
695 #define ADC_ADCMPR_CMPMATCNT_Msk (0xFul << ADC_ADCMPR_CMPMATCNT_Pos)
697 #define ADC_ADCMPR_CMPCH_Pos 3
698 #define ADC_ADCMPR_CMPCH_Msk (7ul << ADC_ADCMPR_CMPCH_Pos)
700 #define ADC_ADCMPR_CMPCOND_Pos 2
701 #define ADC_ADCMPR_CMPCOND_Msk (1ul << ADC_ADCMPR_CMPCOND_Pos)
703 #define ADC_ADCMPR_CMPIE_Pos 1
704 #define ADC_ADCMPR_CMPIE_Msk (1ul << ADC_ADCMPR_CMPIE_Pos)
706 #define ADC_ADCMPR_CMPEN_Pos 0
707 #define ADC_ADCMPR_CMPEN_Msk (1ul << ADC_ADCMPR_CMPEN_Pos)
709 /* ADSR Bit Field Definitions */
710 #define ADC_ADSR_OVERRUN_Pos 16
711 #define ADC_ADSR_OVERRUN_Msk (0xFFul << ADC_ADSR_OVERRUN_Pos)
713 #define ADC_ADSR_VALID_Pos 8
714 #define ADC_ADSR_VALID_Msk (0xFFul << ADC_ADSR_VALID_Pos)
716 #define ADC_ADSR_CHANNEL_Pos 4
717 #define ADC_ADSR_CHANNEL_Msk (7ul << ADC_ADSR_CHANNEL_Pos)
719 #define ADC_ADSR_BUSY_Pos 3
720 #define ADC_ADSR_BUSY_Msk (1ul << ADC_ADSR_BUSY_Pos)
722 #define ADC_ADSR_CMPF1_Pos 2
723 #define ADC_ADSR_CMPF1_Msk (1ul << ADC_ADSR_CMPF1_Pos)
725 #define ADC_ADSR_CMPF0_Pos 1
726 #define ADC_ADSR_CMPF0_Msk (1ul << ADC_ADSR_CMPF0_Pos)
728 #define ADC_ADSR_ADF_Pos 0
729 #define ADC_ADSR_ADF_Msk (1ul << ADC_ADSR_ADF_Pos)
731 /* ADTDCR Bit Field Definitions */
732 #define ADC_ADTDCR_PTDT_Pos 0
733 #define ADC_ADTDCR_PTDT_Msk (0xFFul << ADC_ADTDCR_PTDT_Pos)
735 /* ADSAMP Bit Field Definitions */
736 #define ADC_ADSAMP_SAMPCNT_Pos 0
737 #define ADC_ADSAMP_SAMPCNT_Msk (0xFul << ADC_ADTDCR_PTDT_Pos)
738 /* end of group ADC */
740
741
742 /*-------------------------- Flash Memory Controller -------------------------*/
743
748 typedef struct
749 {
804 __IO uint32_t ISPCON;
805
817 __IO uint32_t ISPADR;
818
830 __IO uint32_t ISPDAT;
831
849 __IO uint32_t ISPCMD;
850
864 __IO uint32_t ISPTRG;
865
881 __I uint32_t DFBADR;
882
883 } FMC_T;
885
886 /* FMC ISPCON Bit Field Definitions */
887 #define FMC_ISPCON_ISPFF_Pos 6
888 #define FMC_ISPCON_ISPFF_Msk (1ul << FMC_ISPCON_ISPFF_Pos)
890 #define FMC_ISPCON_LDUEN_Pos 5
891 #define FMC_ISPCON_LDUEN_Msk (1ul << FMC_ISPCON_LDUEN_Pos)
893 #define FMC_ISPCON_CFGUEN_Pos 4
894 #define FMC_ISPCON_CFGUEN_Msk (1ul << FMC_ISPCON_CFGUEN_Pos)
896 #define FMC_ISPCON_APUEN_Pos 3
897 #define FMC_ISPCON_APUEN_Msk (1ul << FMC_ISPCON_APUEN_Pos)
899 #define FMC_ISPCON_BS_Pos 1
900 #define FMC_ISPCON_BS_Msk (1ul << FMC_ISPCON_BS_Pos)
902 #define FMC_ISPCON_ISPEN_Pos 0
903 #define FMC_ISPCON_ISPEN_Msk (1ul << FMC_ISPCON_ISPEN_Pos)
905 /* FMC ISPCMD Bit Field Definitions */
906 #define FMC_ISPCMD_FOEN_Pos 5
907 #define FMC_ISPCMD_FOEN_Msk (1ul << FMC_ISPCMD_FOEN_Pos)
909 #define FMC_ISPCMD_FCEN_Pos 4
910 #define FMC_ISPCMD_FCEN_Msk (1ul << FMC_ISPCMD_FCEN_Pos)
912 #define FMC_ISPCMD_FCTRL_Pos 0
913 #define FMC_ISPCMD_FCTRL_Msk (0xFul << FMC_ISPCMD_FCTRL_Pos)
915 /* FMC ISPTRG Bit Field Definitions */
916 #define FMC_ISPTRG_ISPGO_Pos 0
917 #define FMC_ISPTRG_ISPGO_Msk (1ul << FMC_ISPTRG_ISPGO_Pos)
918
920 /* end of group FMC */
921
922 /*---------------------- General Purpose Input/Output Controller -------------------------*/
928 typedef struct
929 {
930 __IO uint32_t PMD;
931 __IO uint32_t OFFD;
932 __IO uint32_t DOUT;
933 __IO uint32_t DMASK;
934 __I uint32_t PIN;
935 __IO uint32_t DBEN;
936 __IO uint32_t IMD;
937 __IO uint32_t IEN;
938 __IO uint32_t ISRC;
939 } GPIO_T;
940
941
942 typedef struct
943 {
944 __IO uint32_t DBNCECON;
945 } GPIO_DBNCECON_T;
947 /* GPIO PMD Bit Field Definitions */
948 #define GPIO_PMD_PMD7_Pos 14
949 #define GPIO_PMD_PMD7_Msk (0x3ul << GPIO_PMD_PMD7_Pos)
951 #define GPIO_PMD_PMD6_Pos 12
952 #define GPIO_PMD_PMD6_Msk (0x3ul << GPIO_PMD_PMD6_Pos)
954 #define GPIO_PMD_PMD5_Pos 10
955 #define GPIO_PMD_PMD5_Msk (0x3ul << GPIO_PMD_PMD5_Pos)
957 #define GPIO_PMD_PMD4_Pos 8
958 #define GPIO_PMD_PMD4_Msk (0x3ul << GPIO_PMD_PMD4_Pos)
960 #define GPIO_PMD_PMD3_Pos 6
961 #define GPIO_PMD_PMD3_Msk (0x3ul << GPIO_PMD_PMD3_Pos)
963 #define GPIO_PMD_PMD2_Pos 4
964 #define GPIO_PMD_PMD2_Msk (0x3ul << GPIO_PMD_PMD2_Pos)
966 #define GPIO_PMD_PMD1_Pos 2
967 #define GPIO_PMD_PMD1_Msk (0x3ul << GPIO_PMD_PMD1_Pos)
969 #define GPIO_PMD_PMD0_Pos 0
970 #define GPIO_PMD_PMD0_Msk (0x3ul << GPIO_PMD_PMD0_Pos)
972 /* GPIO OFFD Bit Field Definitions */
973 #define GPIO_OFFD_OFFD_Pos 16
974 #define GPIO_OFFD_OFFD_Msk (0xFFul << GPIO_OFFD_OFFD_Pos)
976 /* GPIO DOUT Bit Field Definitions */
977 #define GPIO_DOUT_DOUT_Pos 0
978 #define GPIO_DOUT_DOUT_Msk (0xFFul << GPIO_DOUT_DOUT_Pos)
980 /* GPIO DMASK Bit Field Definitions */
981 #define GPIO_DMASK_DMASK_Pos 0
982 #define GPIO_DMASK_DMASK_Msk (0xFFul << GPIO_DMASK_DMASK_Pos)
984 /* GPIO PIN Bit Field Definitions */
985 #define GPIO_PIN_PIN_Pos 0
986 #define GPIO_PIN_PIN_Msk (0xFFul << GPIO_PIN_PIN_Pos)
988 /* GPIO DBEN Bit Field Definitions */
989 #define GPIO_DBEN_DBEN_Pos 0
990 #define GPIO_DBEN_DBEN_Msk (0xFFul << GPIO_DBEN_DBEN_Pos)
992 /* GPIO IMD Bit Field Definitions */
993 #define GPIO_IMD_IMD_Pos 0
994 #define GPIO_IMD_IMD_Msk (0xFFul << GPIO_IMD_IMD_Pos)
996 /* GPIO IEN Bit Field Definitions */
997 #define GPIO_IEN_IR_EN_Pos 16
998 #define GPIO_IEN_IR_EN_Msk (0xFFul << GPIO_IEN_IR_EN_Pos)
1000 #define GPIO_IEN_IF_EN_Pos 0
1001 #define GPIO_IEN_IF_EN_Msk (0xFFul << GPIO_IEN_IF_EN_Pos)
1003 /* GPIO ISRC Bit Field Definitions */
1004 #define GPIO_ISRC_ISRC_Pos 0
1005 #define GPIO_ISRC_ISRC_Msk (0xFFul << GPIO_ISRC_ISRC_Pos)
1007 /* GPIO DBNCECON Bit Field Definitions */
1008 #define GPIO_DBNCECON_ICLK_ON_Pos 5
1009 #define GPIO_DBNCECON_ICLK_ON_Msk (1ul << GPIO_DBNCECON_ICLK_ON_Pos)
1011 #define GPIO_DBNCECON_DBCLKSRC_Pos 4
1012 #define GPIO_DBNCECON_DBCLKSRC_Msk (1ul << GPIO_DBNCECON_DBCLKSRC_Pos)
1014 #define GPIO_DBNCECON_DBCLKSEL_Pos 0
1015 #define GPIO_DBNCECON_DBCLKSEL_Msk (0xFul << GPIO_DBNCECON_DBCLKSEL_Pos)
1016
1018 typedef struct
1019 {
1020 __IO uint32_t GP_BIT0;
1021 __IO uint32_t GP_BIT1;
1022 __IO uint32_t GP_BIT2;
1023 __IO uint32_t GP_BIT3;
1024 __IO uint32_t GP_BIT4;
1025 __IO uint32_t GP_BIT5;
1026 __IO uint32_t GP_BIT6;
1027 __IO uint32_t GP_BIT7;
1028 } GPIOBIT_T;
1029 /* end of group GPIO */
1031
1032
1033 /*---------------------- Inter-IC Bus Controller -------------------------*/
1034
1040 typedef struct
1041 {
1042 __IO uint32_t I2CON;
1043 __IO uint32_t I2CADDR0;
1044 __IO uint32_t I2CDAT;
1045 __IO uint32_t I2CSTATUS;
1046 __IO uint32_t I2CLK;
1047 __IO uint32_t I2CTOC;
1048 __IO uint32_t I2CADDR1;
1049 __IO uint32_t I2CADDR2;
1050 __IO uint32_t I2CADDR3;
1051 __IO uint32_t I2CADM0;
1052 __IO uint32_t I2CADM1;
1053 __IO uint32_t I2CADM2;
1054 __IO uint32_t I2CADM3;
1055 uint32_t RESERVED0;
1056 uint32_t RESERVED1;
1057 __IO uint32_t I2CON2;
1058 __IO uint32_t I2CSTATUS2;
1059 } I2C_T;
1061
1062 /* I2C I2CON Bit Field Definitions */
1063 #define I2C_I2CON_EI_Pos 7
1064 #define I2C_I2CON_EI_Msk (1ul << I2C_I2CON_EI_Pos)
1066 #define I2C_I2CON_ENSI_Pos 6
1067 #define I2C_I2CON_ENSI_Msk (1ul << I2C_I2CON_ENSI_Pos)
1069 #define I2C_I2CON_STA_Pos 5
1070 #define I2C_I2CON_STA_Msk (1ul << I2C_I2CON_STA_Pos)
1072 #define I2C_I2CON_STO_Pos 4
1073 #define I2C_I2CON_STO_Msk (1ul << I2C_I2CON_STO_Pos)
1075 #define I2C_I2CON_SI_Pos 3
1076 #define I2C_I2CON_SI_Msk (1ul << I2C_I2CON_SI_Pos)
1078 #define I2C_I2CON_AA_Pos 2
1079 #define I2C_I2CON_AA_Msk (1ul << I2C_I2CON_AA_Pos)
1081 /* I2C I2CADDR Bit Field Definitions */
1082 #define I2C_I2CADDR_I2CADDR_Pos 1
1083 #define I2C_I2CADDR_I2CADDR_Msk (0x7Ful << I2C_I2CADDR_I2CADDR_Pos)
1085 #define I2C_I2CADDR_GC_Pos 0
1086 #define I2C_I2CADDR_GC_Msk (1ul << I2C_I2CADDR_GC_Pos)
1088 /* I2C I2CDAT Bit Field Definitions */
1089 #define I2C_I2CDAT_I2CDAT_Pos 0
1090 #define I2C_I2CDAT_I2CDAT_Msk (0xFFul << I2C_I2CDAT_I2CDAT_Pos)
1092 /* I2C I2CSTATUS Bit Field Definitions */
1093 #define I2C_I2CSTATUS_I2CSTATUS_Pos 0
1094 #define I2C_I2CSTATUS_I2CSTATUS_Msk (0xFFul << I2C_I2CSTATUS_I2CSTATUS_Pos)
1096 /* I2C I2CLK Bit Field Definitions */
1097 #define I2C_I2CLK_I2CLK_Pos 0
1098 #define I2C_I2CLK_I2CLK_Msk (0xFFul << I2C_I2CLK_I2CLK_Pos)
1100 /* I2C I2CTOC Bit Field Definitions */
1101 #define I2C_I2CTOC_ENTI_Pos 2
1102 #define I2C_I2CTOC_ENTI_Msk (1ul << I2C_I2CTOC_ENTI_Pos)
1104 #define I2C_I2CTOC_DIV4_Pos 1
1105 #define I2C_I2CTOC_DIV4_Msk (1ul << I2C_I2CTOC_DIV4_Pos)
1107 #define I2C_I2CTOC_TIF_Pos 0
1108 #define I2C_I2CTOC_TIF_Msk (1ul << I2C_I2CTOC_TIF_Pos)
1110 /* I2C I2CADM Bit Field Definitions */
1111 #define I2C_I2CADM_I2CADM_Pos 1
1112 #define I2C_I2CADM_I2CADM_Msk (0x7Ful << I2C_I2CADM_I2CADM_Pos)
1114 /* I2C I2CON2 Bit Field Definitions */
1115 #define I2C_I2CON2_WKUPEN_Pos 0
1116 #define I2C_I2CON2_WKUPEN_Msk (1ul << I2C_I2CON2_WKUPEN_Pos)
1118 #define I2C_I2CON2_TWOFF_EN_Pos 1
1119 #define I2C_I2CON2_TWOFF_EN_Msk (1ul << I2C_I2CON2_TWOFF_EN_Pos)
1121 #define I2C_I2CON2_NOSTRETCH_Pos 2
1122 #define I2C_I2CON2_NOSTRETCH_Msk (1ul << I2C_I2CON2_NOSTRETCH_Pos)
1124 #define I2C_I2CON2_OVER_INTEN_Pos 3
1125 #define I2C_I2CON2_OVER_INTEN_Msk (1ul << I2C_I2CON2_OVER_INTEN_Pos)
1127 #define I2C_I2CON2_UNDER_INTEN_Pos 4
1128 #define I2C_I2CON2_UNDER_INTEN_Msk (1ul << I2C_I2CON2_UNDER_INTEN_Pos)
1130 /* I2C I2CSTATUS2 Bit Field Definitions */
1131 #define I2C_I2CSTATUS2_WAKEUP_Pos 0
1132 #define I2C_I2CSTATUS2_WAKEUP_Msk (1ul << I2C_I2CSTATUS2_WAKEUP_Pos)
1134 #define I2C_I2CSTATUS2_FULL_Pos 1
1135 #define I2C_I2CSTATUS2_FULL_Msk (1ul << I2C_I2CSTATUS2_FULL_Pos)
1137 #define I2C_I2CSTATUS2_EMPTY_Pos 2
1138 #define I2C_I2CSTATUS2_EMPTY_Msk (1ul << I2C_I2CSTATUS2_EMPTY_Pos)
1140 #define I2C_I2CSTATUS2_OVERUN_Pos 3
1141 #define I2C_I2CSTATUS2_OVERUN_Msk (1ul << I2C_I2CSTATUS2_OVERUN_Pos)
1143 #define I2C_I2CSTATUS2_UNDERUN_Pos 4
1144 #define I2C_I2CSTATUS2_UNDERUN_Msk (1ul << I2C_I2CSTATUS2_UNDERUN_P
1145 /* end of group I2C */
1147
1148 /*---------------------- Interrupt Source Controller -------------------------*/
1149
1155 typedef struct
1156 {
1157 __I uint32_t IRQSRC[32];
1158 __IO uint32_t NMICNO;
1159 __IO uint32_t MCUIRQ;
1161 } INT_T; /* end of group INT */
1163
1164 /*---------------------- Pulse Width Modulation Controller -------------------------*/
1165
1171 typedef struct
1172 {
1173 __IO uint32_t PPR;
1174 __IO uint32_t CSR;
1175 __IO uint32_t PCR;
1176 __IO uint32_t CNR[6];
1177 __IO uint32_t CMR[6];
1178 uint32_t RESERVED0[6];
1179 __IO uint32_t PIER;
1180 __IO uint32_t PIIR;
1181 __IO uint32_t POE;
1182 __IO uint32_t PFBCON;
1183 __IO uint32_t PDZIR;
1184 __IO uint32_t TRGCON0;
1185 __IO uint32_t TRGCON1;
1186 __IO uint32_t TRGSTS0;
1187 __IO uint32_t TRGSTS1;
1188 __IO uint32_t PHCHG;
1189 __IO uint32_t PHCHGNXT;
1190 __IO uint32_t PHCHGMASK;
1191 __IO uint32_t INTACCUCTL;
1192 } PWM_T;
1194 /* PWM PPR Bit Field Definitions */
1195 #define PWM_PPR_CP45_Pos 16
1196 #define PWM_PPR_CP45_Msk (0xFFul << PWM_PPR_CP45_Pos)
1198 #define PWM_PPR_CP23_Pos 8
1199 #define PWM_PPR_CP23_Msk (0xFFul << PWM_PPR_CP23_Pos)
1201 #define PWM_PPR_CP01_Pos 0
1202 #define PWM_PPR_CP01_Msk (0xFFul << PWM_PPR_CP01_Pos)
1204 /* PWM CSR Bit Field Definitions */
1205 #define PWM_CSR_CSR5_Pos 20
1206 #define PWM_CSR_CSR5_Msk (7ul << PWM_CSR_CSR5_Pos)
1208 #define PWM_CSR_CSR4_Pos 16
1209 #define PWM_CSR_CSR4_Msk (7ul << PWM_CSR_CSR4_Pos)
1211 #define PWM_CSR_CSR3_Pos 12
1212 #define PWM_CSR_CSR3_Msk (7ul << PWM_CSR_CSR3_Pos)
1214 #define PWM_CSR_CSR2_Pos 8
1215 #define PWM_CSR_CSR2_Msk (7ul << PWM_CSR_CSR2_Pos)
1217 #define PWM_CSR_CSR1_Pos 4
1218 #define PWM_CSR_CSR1_Msk (7ul << PWM_CSR_CSR1_Pos)
1220 #define PWM_CSR_CSR0_Pos 0
1221 #define PWM_CSR_CSR0_Msk (7ul << PWM_CSR_CSR0_Pos)
1223 /* PWM PCR Bit Field Definitions */
1224 #define PWM_PCR_PWMTYPE_Pos 31
1225 #define PWM_PCR_PWMTYPE_Msk (1ul << PWM_PCR_PWMTYPE_Pos)
1227 #define PWM_PCR_GRP_Pos 30
1228 #define PWM_PCR_GRP_Msk (1ul << PWM_PCR_GRP_Pos)
1230 #define PWM_PCR_PWMMOD_Pos 28
1231 #define PWM_PCR_PWMMOD_Msk (3ul << PWM_PCR_PWMMOD_Pos)
1233 #define PWM_PCR_CLRPWM_Pos 27
1234 #define PWM_PCR_CLRPWM_Msk (1ul << PWM_PCR_CLRPWM_Pos)
1236 #define PWM_PCR_DZEN45_Pos 26
1237 #define PWM_PCR_DZEN45_Msk (1ul << PWM_PCR_DZEN45_Pos)
1239 #define PWM_PCR_DZEN23_Pos 25
1240 #define PWM_PCR_DZEN23_Msk (1ul << PWM_PCR_DZEN23_Pos)
1242 #define PWM_PCR_DZEN01_Pos 24
1243 #define PWM_PCR_DZEN01_Msk (1ul << PWM_PCR_DZEN01_Pos)
1245 #define PWM_PCR_CH5MOD_Pos 23
1246 #define PWM_PCR_CH5MOD_Msk (1ul << PWM_PCR_CH5MOD_Pos)
1248 #define PWM_PCR_CH5INV_Pos 22
1249 #define PWM_PCR_CH5INV_Msk (1ul << PWM_PCR_CH5INV_Pos)
1251 #define PWM_PCR_CH5EN_Pos 20
1252 #define PWM_PCR_CH5EN_Msk (1ul << PWM_PCR_CH5EN_Pos)
1254 #define PWM_PCR_CH4MOD_Pos 19
1255 #define PWM_PCR_CH4MOD_Msk (1ul << PWM_PCR_CH4MOD_Pos)
1257 #define PWM_PCR_CH4INV_Pos 18
1258 #define PWM_PCR_CH4INV_Msk (1ul << PWM_PCR_CH4INV_Pos)
1260 #define PWM_PCR_CH4EN_Pos 16
1261 #define PWM_PCR_CH4EN_Msk (1ul << PWM_PCR_CH4EN_Pos)
1263 #define PWM_PCR_CH3MOD_Pos 15
1264 #define PWM_PCR_CH3MOD_Msk (1ul << PWM_PCR_CH3MOD_Pos)
1266 #define PWM_PCR_CH3INV_Pos 14
1267 #define PWM_PCR_CH3INV_Msk (1ul << PWM_PCR_CH3INV_Pos)
1269 #define PWM_PCR_CH3EN_Pos 12
1270 #define PWM_PCR_CH3EN_Msk (1ul << PWM_PCR_CH3EN_Pos)
1272 #define PWM_PCR_CH2MOD_Pos 11
1273 #define PWM_PCR_CH2MOD_Msk (1ul << PWM_PCR_CH2MOD_Pos)
1275 #define PWM_PCR_CH2INV_Pos 10
1276 #define PWM_PCR_CH2INV_Msk (1ul << PWM_PCR_CH2INV_Pos)
1278 #define PWM_PCR_CH2EN_Pos 8
1279 #define PWM_PCR_CH2EN_Msk (1ul << PWM_PCR_CH2EN_Pos)
1281 #define PWM_PCR_CH1MOD_Pos 7
1282 #define PWM_PCR_CH1MOD_Msk (1ul << PWM_PCR_CH1MOD_Pos)
1284 #define PWM_PCR_CH1INV_Pos 6
1285 #define PWM_PCR_CH1INV_Msk (1ul << PWM_PCR_CH1INV_Pos)
1287 #define PWM_PCR_CH1EN_Pos 4
1288 #define PWM_PCR_CH1EN_Msk (1ul << PWM_PCR_CH1EN_Pos)
1290 #define PWM_PCR_CH0MOD_Pos 3
1291 #define PWM_PCR_CH0MOD_Msk (1ul << PWM_PCR_CH0MOD_Pos)
1293 #define PWM_PCR_CH0INV_Pos 2
1294 #define PWM_PCR_CH0INV_Msk (1ul << PWM_PCR_CH0INV_Pos)
1296 #define PWM_PCR_DB_MOD_Pos 1
1297 #define PWM_PCR_DB_MOD_Msk (1ul << PWM_PCR_DB_MOD_Pos)
1299 #define PWM_PCR_CH0EN_Pos 0
1300 #define PWM_PCR_CH0EN_Msk (1ul << PWM_PCR_CH0EN_Pos)
1302 /* PWM CNR Bit Field Definitions */
1303 #define PWM_CNR_CNR_Pos 0
1304 #define PWM_CNR_CNR_Msk (0xFFFFul << PWM_CNR_CNR_Pos)
1306 /* PWM CMR Bit Field Definitions */
1307 #define PWM_CMR_CMR_Pos 0
1308 #define PWM_CMR_CMR_Msk (0xFFFFul << PWM_CMR_CMR_Pos)
1311 /* PWM PIER Bit Field Definitions */
1312 #define PWM_PIER_INT_TYPE_Pos 17
1313 #define PWM_PIER_INT_TYPE_Msk (1ul << PWM_PIER_INT_TYPE_Pos)
1315 #define PWM_PIER_BRKIE_Pos 16
1316 #define PWM_PIER_BRKIE_Msk (1ul << PWM_PIER_BRKIE_Pos)
1318 #define PWM_PIER_PWMDIE5_Pos 13
1319 #define PWM_PIER_PWMDIE5_Msk (1ul << PWM_PIER_PWMDIE5_Pos)
1321 #define PWM_PIER_PWMDIE4_Pos 12
1322 #define PWM_PIER_PWMDIE4_Msk (1ul << PWM_PIER_PWMDIE4_Pos)
1324 #define PWM_PIER_PWMDIE3_Pos 11
1325 #define PWM_PIER_PWMDIE3_Msk (1ul << PWM_PIER_PWMDIE3_Pos)
1327 #define PWM_PIER_PWMDIE2_Pos 10
1328 #define PWM_PIER_PWMDIE2_Msk (1ul << PWM_PIER_PWMDIE2_Pos)
1330 #define PWM_PIER_PWMDIE1_Pos 9
1331 #define PWM_PIER_PWMDIE1_Msk (1ul << PWM_PIER_PWMDIE1_Pos)
1333 #define PWM_PIER_PWMDIE0_Pos 8
1334 #define PWM_PIER_PWMDIE0_Msk (1ul << PWM_PIER_PWMDIE0_Pos)
1336 #define PWM_PIER_PWMPIE5_Pos 5
1337 #define PWM_PIER_PWMPIE5_Msk (1ul << PWM_PIER_PWMPIE5_Pos)
1339 #define PWM_PIER_PWMPIE4_Pos 4
1340 #define PWM_PIER_PWMPIE4_Msk (1ul << PWM_PIER_PWMPIE4_Pos)
1342 #define PWM_PIER_PWMPIE3_Pos 3
1343 #define PWM_PIER_PWMPIE3_Msk (1ul << PWM_PIER_PWMPIE3_Pos)
1345 #define PWM_PIER_PWMPIE2_Pos 2
1346 #define PWM_PIER_PWMPIE2_Msk (1ul << PWM_PIER_PWMPIE2_Pos)
1348 #define PWM_PIER_PWMPIE1_Pos 1
1349 #define PWM_PIER_PWMPIE1_Msk (1ul << PWM_PIER_PWMPIE1_Pos)
1351 #define PWM_PIER_PWMPIE0_Pos 0
1352 #define PWM_PIER_PWMPIE0_Msk (1ul << PWM_PIER_PWMPIE0_Pos)
1354 /* PWM PIIR Bit Field Definitions */
1355 #define PWM_PIIR_BKF1_Pos 17
1356 #define PWM_PIIR_BKF1_Msk (1ul << PWM_PIIR_BKF1_Pos)
1358 #define PWM_PIIR_BKF0_Pos 16
1359 #define PWM_PIIR_BKF0_Msk (1ul << PWM_PIIR_BKF0_Pos)
1361 #define PWM_PIIR_PWMDIF5_Pos 13
1362 #define PWM_PIIR_PWMDIF5_Msk (1ul << PWM_PIIR_PWMDIF5_Pos)
1364 #define PWM_PIIR_PWMDIF4_Pos 12
1365 #define PWM_PIIR_PWMDIF4_Msk (1ul << PWM_PIIR_PWMDIF4_Pos)
1367 #define PWM_PIIR_PWMDIF3_Pos 11
1368 #define PWM_PIIR_PWMDIF3_Msk (1ul << PWM_PIIR_PWMDIF3_Pos)
1370 #define PWM_PIIR_PWMDIF2_Pos 10
1371 #define PWM_PIIR_PWMDIF2_Msk (1ul << PWM_PIIR_PWMDIF2_Pos)
1373 #define PWM_PIIR_PWMDIF1_Pos 9
1374 #define PWM_PIIR_PWMDIF1_Msk (1ul << PWM_PIIR_PWMDIF1_Pos)
1376 #define PWM_PIIR_PWMDIF0_Pos 8
1377 #define PWM_PIIR_PWMDIF0_Msk (1ul << PWM_PIIR_PWMDIF0_Pos)
1379 #define PWM_PIIR_PWMPIF5_Pos 5
1380 #define PWM_PIIR_PWMPIF5_Msk (1ul << PWM_PIIR_PWMPIF5_Pos)
1382 #define PWM_PIIR_PWMPIF4_Pos 4
1383 #define PWM_PIIR_PWMPIF4_Msk (1ul << PWM_PIIR_PWMPIF4_Pos)
1385 #define PWM_PIIR_PWMPIF3_Pos 3
1386 #define PWM_PIIR_PWMPIF3_Msk (1ul << PWM_PIIR_PWMPIF3_Pos)
1388 #define PWM_PIIR_PWMPIF2_Pos 2
1389 #define PWM_PIIR_PWMPIF2_Msk (1ul << PWM_PIIR_PWMPIF2_Pos)
1391 #define PWM_PIIR_PWMPIF1_Pos 1
1392 #define PWM_PIIR_PWMPIF1_Msk (1ul << PWM_PIIR_PWMPIF1_Pos)
1394 #define PWM_PIIR_PWMPIF0_Pos 0
1395 #define PWM_PIIR_PWMPIF0_Msk (1ul << PWM_PIIR_PWMPIF0_Pos)
1397 /* PWM POE Bit Field Definitions */
1398 #define PWM_POE_PWM5_Pos 5
1399 #define PWM_POE_PWM5_Msk (1ul << PWM_POE_PWM5_Pos)
1401 #define PWM_POE_PWM4_Pos 4
1402 #define PWM_POE_PWM4_Msk (1ul << PWM_POE_PWM4_Pos)
1404 #define PWM_POE_PWM3_Pos 3
1405 #define PWM_POE_PWM3_Msk (1ul << PWM_POE_PWM3_Pos)
1407 #define PWM_POE_PWM2_Pos 2
1408 #define PWM_POE_PWM2_Msk (1ul << PWM_POE_PWM2_Pos)
1410 #define PWM_POE_PWM1_Pos 1
1411 #define PWM_POE_PWM1_Msk (1ul << PWM_POE_PWM1_Pos)
1413 #define PWM_POE_PWM0_Pos 0
1414 #define PWM_POE_PWM0_Msk (1ul << PWM_POE_PWM0_Pos)
1416 /* PWM PFBCON Bit Field Definitions */
1417 #define PWM_PFBCON_D7BKO7_Pos 31
1418 #define PWM_PFBCON_D7BKO7_Msk (1ul << PWM_PFBCON_D7BKO7_Pos)
1420 #define PWM_PFBCON_D6BKO6_Pos 30
1421 #define PWM_PFBCON_D6BKO6_Msk (1ul << PWM_PFBCON_D6BKO6_Pos)
1423 #define PWM_PFBCON_PWMBKO5_Pos 29
1424 #define PWM_PFBCON_PWMBKO5_Msk (1ul << PWM_PFBCON_PWMBKO5_Pos)
1426 #define PWM_PFBCON_PWMBKO4_Pos 28
1427 #define PWM_PFBCON_PWMBKO4_Msk (1ul << PWM_PFBCON_PWMBKO4_Pos)
1429 #define PWM_PFBCON_PWMBKO3_Pos 27
1430 #define PWM_PFBCON_PWMBKO3_Msk (1ul << PWM_PFBCON_PWMBKO3_Pos)
1432 #define PWM_PFBCON_PWMBKO2_Pos 26
1433 #define PWM_PFBCON_PWMBKO2_Msk (1ul << PWM_PFBCON_PWMBKO2_Pos)
1435 #define PWM_PFBCON_PWMBKO1_Pos 25
1436 #define PWM_PFBCON_PWMBKO1_Msk (1ul << PWM_PFBCON_PWMBKO1_Pos)
1438 #define PWM_PFBCON_PWMBKO0_Pos 24
1439 #define PWM_PFBCON_PWMBKO0_Msk (1ul << PWM_PFBCON_PWMBKO0_Pos)
1441 #define PWM_PFBCON_BKF_Pos 7
1442 #define PWM_PFBCON_BKF_Msk (1ul << PWM_PFBCON_BKF_Pos)
1444 #define PWM_PFBCON_CPO0BKEN_Pos 2
1445 #define PWM_PFBCON_CPO0BKEN_Msk (1ul << PWM_PFBCON_CPO0BKEN_Pos)
1447 #define PWM_PFBCON_BKEN1_Pos 1
1448 #define PWM_PFBCON_BKEN1_Msk (1ul << PWM_PFBCON_BKEN1_Pos)
1450 #define PWM_PFBCON_BKEN0_Pos 0
1451 #define PWM_PFBCON_BKEN0_Msk (1ul << PWM_PFBCON_BKEN0_Pos)
1453 /* PWM DZIR Bit Field Definitions */
1454 #define PWM_DZIR_DZI45_Pos 16
1455 #define PWM_DZIR_DZI45_Msk (0xFFul << PWM_DZIR_DZI45_Pos)
1457 #define PWM_DZIR_DZI23_Pos 8
1458 #define PWM_DZIR_DZI23_Msk (0xFFul << PWM_DZIR_DZI23_Pos)
1460 #define PWM_DZIR_DZI01_Pos 0
1461 #define PWM_DZIR_DZI01_Msk (0xFFul << PWM_DZIR_DZI01_Pos)
1463 /* PWM TRGCON0 Bit Field Definitions */
1464 #define PWM_TRGCON0_P3TRGEN_Pos 27
1465 #define PWM_TRGCON0_P3TRGEN_Msk (1ul << PWM_TRGCON0_P3TRGEN_Pos)
1467 #define PWM_TRGCON0_CM3TRGFEN_Pos 26
1468 #define PWM_TRGCON0_CM3TRGFEN_Msk (1ul << PWM_TRGCON0_CM3TRGFEN_Pos)
1470 #define PWM_TRGCON0_CNT3TRGEN_Pos 25
1471 #define PWM_TRGCON0_CNT3TRGEN_Msk (1ul << PWM_TRGCON0_CNT3TRGEN_Pos)
1473 #define PWM_TRGCON0_CM3TRGREN_Pos 24
1474 #define PWM_TRGCON0_CM3TRGREN_Msk (1ul << PWM_TRGCON0_CM3TRGREN_Pos)
1476 #define PWM_TRGCON0_P2TRGEN_Pos 19
1477 #define PWM_TRGCON0_P2TRGEN_Msk (1ul << PWM_TRGCON0_P2TRGEN_Pos)
1479 #define PWM_TRGCON0_CM2TRGFEN_Pos 18
1480 #define PWM_TRGCON0_CM2TRGFEN_Msk (1ul << PWM_TRGCON0_CM2TRGFEN_Pos)
1482 #define PWM_TRGCON0_CNT2TRGEN_Pos 17
1483 #define PWM_TRGCON0_CNT2TRGEN_Msk (1ul << PWM_TRGCON0_CNT2TRGEN_Pos)
1485 #define PWM_TRGCON0_CM2TRGREN_Pos 16
1486 #define PWM_TRGCON0_CM2TRGREN_Msk (1ul << PWM_TRGCON0_CM2TRGREN_Pos)
1488 #define PWM_TRGCON0_P1TRGEN_Pos 11
1489 #define PWM_TRGCON0_P1TRGEN_Msk (1ul << PWM_TRGCON0_P1TRGEN_Pos)
1491 #define PWM_TRGCON0_CM1TRGFEN_Pos 10
1492 #define PWM_TRGCON0_CM1TRGFEN_Msk (1ul << PWM_TRGCON0_CM1TRGFEN_Pos)
1494 #define PWM_TRGCON0_CNT1TRGEN_Pos 9
1495 #define PWM_TRGCON0_CNT1TRGEN_Msk (1ul << PWM_TRGCON0_CNT1TRGEN_Pos)
1497 #define PWM_TRGCON0_CM1TRGREN_Pos 8
1498 #define PWM_TRGCON0_CM1TRGREN_Msk (1ul << PWM_TRGCON0_CM1TRGREN_Pos)
1500 #define PWM_TRGCON0_P0TRGEN_Pos 3
1501 #define PWM_TRGCON0_P0TRGEN_Msk (1ul << PWM_TRGCON0_P0TRGEN_Pos)
1503 #define PWM_TRGCON0_CM0TRGFEN_Pos 2
1504 #define PWM_TRGCON0_CM0TRGFEN_Msk (1ul << PWM_TRGCON0_CM0TRGFEN_Pos)
1506 #define PWM_TRGCON0_CNT0TRGEN_Pos 1
1507 #define PWM_TRGCON0_CNT0TRGEN_Msk (1ul << PWM_TRGCON0_CNT0TRGEN_Pos)
1509 #define PWM_TRGCON0_CM0TRGREN_Pos 0
1510 #define PWM_TRGCON0_CM0TRGREN_Msk (1ul << PWM_TRGCON0_CM0TRGREN_Pos)
1512 /* PWM TRGCON1 Bit Field Definitions */
1513 #define PWM_TRGCON1_P5TRGEN_Pos 11
1514 #define PWM_TRGCON1_P5TRGEN_Msk (1ul << PWM_TRGCON1_P5TRGEN_Pos)
1516 #define PWM_TRGCON1_CM5TRGFEN_Pos 10
1517 #define PWM_TRGCON1_CM5TRGFEN_Msk (1ul << PWM_TRGCON1_CM5TRGFEN_Pos)
1519 #define PWM_TRGCON1_CNT5TRGEN_Pos 9
1520 #define PWM_TRGCON1_CNT5TRGEN_Msk (1ul << PWM_TRGCON1_CNT5TRGEN_Pos)
1522 #define PWM_TRGCON1_CM5TRGREN_Pos 8
1523 #define PWM_TRGCON1_CM5TRGREN_Msk (1ul << PWM_TRGCON1_CM5TRGREN_Pos)
1525 #define PWM_TRGCON1_P4TRGEN_Pos 3
1526 #define PWM_TRGCON1_P4TRGEN_Msk (1ul << PWM_TRGCON1_P4TRGEN_Pos)
1528 #define PWM_TRGCON1_CM4TRGFEN_Pos 2
1529 #define PWM_TRGCON1_CM4TRGFEN_Msk (1ul << PWM_TRGCON1_CM4TRGFEN_Pos)
1531 #define PWM_TRGCON1_CNT4TRGEN_Pos 1
1532 #define PWM_TRGCON1_CNT4TRGEN_Msk (1ul << PWM_TRGCON1_CNT4TRGEN_Pos)
1534 #define PWM_TRGCON1_CM4TRGREN_Pos 0
1535 #define PWM_TRGCON1_CM4TRGREN_Msk (1ul << PWM_TRGCON1_CM4TRGREN_Pos)
1537 /* PWM TRGSTS0 Bit Field Definitions */
1538 #define PWM_TRGSTS0_PERID3FLAG_Pos 27
1539 #define PWM_TRGSTS0_PERID3FLAG_Msk (1ul << PWM_TRGSTS0_PERID3FLAG_Pos)
1541 #define PWM_TRGSTS0_CMR3FLAG_F_Pos 26
1542 #define PWM_TRGSTS0_CMR3FLAG_F_Msk (1ul << PWM_TRGSTS0_CMR3FLAG_F_Pos)
1544 #define PWM_TRGSTS0_CNT3FLAG_Pos 25
1545 #define PWM_TRGSTS0_CNT3FLAG_Msk (1ul << PWM_TRGSTS0_CNT3FLAG_Pos)
1547 #define PWM_TRGSTS0_CMR3FLAG_R_Pos 24
1548 #define PWM_TRGSTS0_CMR3FLAG_R_Msk (1ul << PWM_TRGSTS0_CMR3FLAG_R_Pos)
1550 #define PWM_TRGSTS0_PERID2FLAG_Pos 19
1551 #define PWM_TRGSTS0_PERID2FLAG_Msk (1ul << PWM_TRGSTS0_PERID2FLAG_Pos)
1553 #define PWM_TRGSTS0_CMR2FLAG_F_Pos 18
1554 #define PWM_TRGSTS0_CMR2FLAG_F_Msk (1ul << PWM_TRGSTS0_CMR2FLAG_F_Pos)
1556 #define PWM_TRGSTS0_CNT2FLAG_Pos 17
1557 #define PWM_TRGSTS0_CNT2FLAG_Msk (1ul << PWM_TRGSTS0_CNT2FLAG_Pos)
1559 #define PWM_TRGSTS0_CMR2FLAG_R_Pos 16
1560 #define PWM_TRGSTS0_CMR2FLAG_R_Msk (1ul << PWM_TRGSTS0_CMR2FLAG_R_Pos)
1562 #define PWM_TRGSTS0_PERID1FLAG_Pos 11
1563 #define PWM_TRGSTS0_PERID1FLAG_Msk (1ul << PWM_TRGSTS0_PERID1FLAG_Pos)
1565 #define PWM_TRGSTS0_CMR1FLAG_F_Pos 10
1566 #define PWM_TRGSTS0_CMR1FLAG_F_Msk (1ul << PWM_TRGSTS0_CMR1FLAG_F_Pos)
1568 #define PWM_TRGSTS0_CNT1FLAG_Pos 9
1569 #define PWM_TRGSTS0_CNT1FLAG_Msk (1ul << PWM_TRGSTS0_CNT1FLAG_Pos)
1571 #define PWM_TRGSTS0_CMR1FLAG_R_Pos 8
1572 #define PWM_TRGSTS0_CMR1FLAG_R_Msk (1ul << PWM_TRGSTS0_CMR1FLAG_R_Pos)
1574 #define PWM_TRGSTS0_PERID0FLAG_Pos 3
1575 #define PWM_TRGSTS0_PERID0FLAG_Msk (1ul << PWM_TRGSTS0_PERID0FLAG_Pos)
1577 #define PWM_TRGSTS0_CMR0FLAG_F_Pos 2
1578 #define PWM_TRGSTS0_CMR0FLAG_F_Msk (1ul << PWM_TRGSTS0_CMR0FLAG_F_Pos)
1580 #define PWM_TRGSTS0_CNT0FLAG_Pos 1
1581 #define PWM_TRGSTS0_CNT0FLAG_Msk (1ul << PWM_TRGSTS0_CNT0FLAG_Pos)
1583 #define PWM_TRGSTS0_CMR0FLAG_R_Pos 0
1584 #define PWM_TRGSTS0_CMR0FLAG_R_Msk (1ul << PWM_TRGSTS0_CMR0FLAG_R_Pos)
1586 /* PWM TRGSTS1 Bit Field Definitions */
1587 #define PWM_TRGSTS1_PERID5FLAG_Pos 11
1588 #define PWM_TRGSTS1_PERID5FLAG_Msk (1ul << PWM_TRGSTS1_PERID5FLAG_Pos)
1590 #define PWM_TRGSTS1_CMR5FLAG_F_Pos 10
1591 #define PWM_TRGSTS1_CMR5FLAG_F_Msk (1ul << PWM_TRGSTS1_CMR5FLAG_F_Pos)
1593 #define PWM_TRGSTS1_CNT5FLAG_Pos 9
1594 #define PWM_TRGSTS1_CNT5FLAG_Msk (1ul << PWM_TRGSTS1_CNT5FLAG_Pos)
1596 #define PWM_TRGSTS1_CMR5FLAG_R_Pos 8
1597 #define PWM_TRGSTS1_CMR5FLAG_R_Msk (1ul << PWM_TRGSTS1_CMR5FLAG_R_Pos)
1599 #define PWM_TRGSTS1_PERID4FLAG_Pos 3
1600 #define PWM_TRGSTS1_PERID4FLAG_Msk (1ul << PWM_TRGSTS1_PERID4FLAG_Pos)
1602 #define PWM_TRGSTS1_CMR4FLAG_F_Pos 2
1603 #define PWM_TRGSTS1_CMR4FLAG_F_Msk (1ul << PWM_TRGSTS1_CMR4FLAG_F_Pos)
1605 #define PWM_TRGSTS1_CNT4FLAG_Pos 1
1606 #define PWM_TRGSTS1_CNT4FLAG_Msk (1ul << PWM_TRGSTS1_CNT4FLAG_Pos)
1608 #define PWM_TRGSTS1_CMR4FLAG_R_Pos 0
1609 #define PWM_TRGSTS1_CMR4FLAG_R_Msk (1ul << PWM_TRGSTS1_CMR4FLAG_R_Pos)
1611 /* PWM PHCHG Bit Field Definitions */
1612 #define PWM_PHCHG_CE0_Pos 31
1613 #define PWM_PHCHG_CE0_Msk (1ul << PWM_PHCHG_CE0_Pos)
1615 #define PWM_PHCHG_T0_Pos 30
1616 #define PWM_PHCHG_T0_Msk (1ul << PWM_PHCHG_T0_Pos)
1618 #define PWM_PHCHG_CMP0SEL_Pos 28
1619 #define PWM_PHCHG_CMP0SEL_Msk (3ul << PWM_PHCHG_CMP0SEL_Pos)
1621 #define PWM_PHCHG_CH31TOFF0_Pos 27
1622 #define PWM_PHCHG_CH31TOFF0_Msk (1ul << PWM_PHCHG_CH31TOFF0_Pos)
1624 #define PWM_PHCHG_CH21TOFF0_Pos 26
1625 #define PWM_PHCHG_CH21TOFF0_Msk (1ul << PWM_PHCHG_CH21TOFF0_Pos)
1627 #define PWM_PHCHG_CH11TOFF0_Pos 25
1628 #define PWM_PHCHG_CH11TOFF0_Msk (1ul << PWM_PHCHG_CH11TOFF0_Pos)
1630 #define PWM_PHCHG_CH01TOFF0_Pos 24
1631 #define PWM_PHCHG_CH01TOFF0_Msk (1ul << PWM_PHCHG_CH01TOFF0_Pos)
1633 #define PWM_PHCHG_CE1_Pos 23
1634 #define PWM_PHCHG_CE1_Msk (1ul << PWM_PHCHG_CE1_Pos)
1636 #define PWM_PHCHG_T1_Pos 22
1637 #define PWM_PHCHG_T1_Msk (1ul << PWM_PHCHG_T1_Pos)
1639 #define PWM_PHCHG_CMP1SEL_Pos 20
1640 #define PWM_PHCHG_CMP1SEL_Msk (3ul << PWM_PHCHG_CMP1SEL_Pos)
1642 #define PWM_PHCHG_CH31TOFF1_Pos 19
1643 #define PWM_PHCHG_CH31TOFF1_Msk (1ul << PWM_PHCHG_CH31TOFF1_Pos)
1645 #define PWM_PHCHG_CH21TOFF1_Pos 18
1646 #define PWM_PHCHG_CH21TOFF1_Msk (1ul << PWM_PHCHG_CH21TOFF1_Pos)
1648 #define PWM_PHCHG_CH11TOFF1_Pos 17
1649 #define PWM_PHCHG_CH11TOFF1_Msk (1ul << PWM_PHCHG_CH11TOFF1_Pos)
1651 #define PWM_PHCHG_CH01TOFF1_Pos 16
1652 #define PWM_PHCHG_CH01TOFF1_Msk (1ul << PWM_PHCHG_CH01TOFF1_Pos)
1654 #define PWM_PHCHG_ACCNT1_Pos 15
1655 #define PWM_PHCHG_ACCNT1_Msk (1ul << PWM_PHCHG_ACCNT1_Pos)
1657 #define PWM_PHCHG_ACCNT0_Pos 14
1658 #define PWM_PHCHG_ACCNT0_Msk (1ul << PWM_PHCHG_ACCNT0_Pos)
1660 #define PWM_PHCHG_PWM5_Pos 13
1661 #define PWM_PHCHG_PWM5_Msk (1ul << PWM_PHCHGPWM5_Pos)
1663 #define PWM_PHCHG_PWM4_Pos 12
1664 #define PWM_PHCHG_PWM4_Msk (1ul << PWM_PHCHG_PWM4_Pos)
1666 #define PWM_PHCHG_PWM3_Pos 11
1667 #define PWM_PHCHG_PWM3_Msk (1ul << PWM_PHCHG_PWM3_Pos)
1669 #define PWM_PHCHG_PWM2_Pos 10
1670 #define PWM_PHCHG_PWM2_Msk (1ul << PWM_PHCHG_PWM2_Pos)
1672 #define PWM_PHCHG_PWM1_Pos 9
1673 #define PWM_PHCHG_PWM1_Msk (1ul << PWM_PHCHG_PWM1_Pos)
1675 #define PWM_PHCHG_PWM0_Pos 8
1676 #define PWM_PHCHG_PWM0_Msk (1ul << PWM_PHCHG_PWM0_Pos)
1678 #define PWM_PHCHG_D7_Pos 7
1679 #define PWM_PHCHG_D7_Msk (1ul << PWM_PHCHG_D7_Pos)
1681 #define PWM_PHCHG_D6_Pos 6
1682 #define PWM_PHCHG_D6_Msk (1ul << PWM_PHCHG_D6_Pos)
1684 #define PWM_PHCHG_D5_Pos 5
1685 #define PWM_PHCHG_D5_Msk (1ul << PWM_PHCHG_D5_Pos)
1687 #define PWM_PHCHG_D4_Pos 4
1688 #define PWM_PHCHG_D4_Msk (1ul << PWM_PHCHG_D4_Pos)
1690 #define PWM_PHCHG_D3_Pos 3
1691 #define PWM_PHCHG_D3_Msk (1ul << PWM_PHCHG_D3_Pos)
1693 #define PWM_PHCHG_D2_Pos 2
1694 #define PWM_PHCHG_D2_Msk (1ul << PWM_PHCHG_D2_Pos)
1696 #define PWM_PHCHG_D1_Pos 1
1697 #define PWM_PHCHG_D1_Msk (1ul << PWM_PHCHG_D1_Pos)
1699 #define PWM_PHCHG_D0_Pos 0
1700 #define PWM_PHCHG_D0_Msk (1ul << PWM_PHCHG_D0_Pos)
1702 /* PWM PHCHGNXT Bit Field Definitions */
1703 #define PWM_PHCHGNXT_CE0_Pos 31
1704 #define PWM_PHCHGNXT_CE0_Msk (1ul << PWM_PHCHGNXT_CE0_Pos)
1706 #define PWM_PHCHGNXT_T0_Pos 30
1707 #define PWM_PHCHGNXT_T0_Msk (1ul << PWM_PHCHGNXT_T0_Pos)
1709 #define PWM_PHCHGNXT_CMP0SEL_Pos 28
1710 #define PWM_PHCHGNXT_CMP0SEL_Msk (3ul << PWM_PHCHGNXT_CMP0SEL_Pos)
1712 #define PWM_PHCHGNXT_CH31TOFF0_Pos 27
1713 #define PWM_PHCHGNXT_CH31TOFF0_Msk (1ul << PWM_PHCHGNXT_CH31TOFF0_Pos)
1715 #define PWM_PHCHGNXT_CH21TOFF0_Pos 26
1716 #define PWM_PHCHGNXT_CH21TOFF0_Msk (1ul << PWM_PHCHGNXT_CH21TOFF0_Pos)
1718 #define PWM_PHCHGNXT_CH11TOFF0_Pos 25
1719 #define PWM_PHCHGNXT_CH11TOFF0_Msk (1ul << PWM_PHCHGNXT_CH11TOFF0_Pos)
1721 #define PWM_PHCHGNXT_CH01TOFF0_Pos 24
1722 #define PWM_PHCHGNXT_CH01TOFF0_Msk (1ul << PWM_PHCHGNXT_CH01TOFF0_Pos)
1724 #define PWM_PHCHGNXT_CE1_Pos 23
1725 #define PWM_PHCHGNXT_CE1_Msk (1ul << PWM_PHCHGNXT_CE1_Pos)
1727 #define PWM_PHCHGNXT_T1_Pos 22
1728 #define PWM_PHCHGNXT_T1_Msk (1ul << PWM_PHCHGNXT_T1_Pos)
1730 #define PWM_PHCHGNXT_CMP1SEL_Pos 20
1731 #define PWM_PHCHGNXT_CMP1SEL_Msk (3ul << PWM_PHCHGNXT_CMP1SEL_Pos)
1733 #define PWM_PHCHGNXT_CH31TOFF1_Pos 19
1734 #define PWM_PHCHGNXT_CH31TOFF1_Msk (1ul << PWM_PHCHGNXT_CH31TOFF1_Pos)
1736 #define PWM_PHCHGNXT_CH21TOFF1_Pos 18
1737 #define PWM_PHCHGNXT_CH21TOFF1_Msk (1ul << PWM_PHCHGNXT_CH21TOFF1_Pos)
1739 #define PWM_PHCHGNXT_CH11TOFF1_Pos 17
1740 #define PWM_PHCHGNXT_CH11TOFF1_Msk (1ul << PWM_PHCHGNXT_CH11TOFF1_Pos)
1742 #define PWM_PHCHGNXT_CH01TOFF1_Pos 16
1743 #define PWM_PHCHGNXT_CH01TOFF1_Msk (1ul << PWM_PHCHGNXT_CH01TOFF1_Pos)
1745 #define PWM_PHCHGNXT_ACCNT1_Pos 15
1746 #define PWM_PHCHGNXT_ACCNT1_Msk (1ul << PWM_PHCHGNXT_ACCNT1_Pos)
1748 #define PWM_PHCHGNXT_ACCNT0_Pos 14
1749 #define PWM_PHCHGNXT_ACCNT0_Msk (1ul << PWM_PHCHGNXT_ACCNT0_Pos)
1751 #define PWM_PHCHGNXT_PWM5_Pos 13
1752 #define PWM_PHCHGNXT_PWM5_Msk (1ul << PWM_PHCHGNXTPWM5_Pos)
1754 #define PWM_PHCHGNXT_PWM4_Pos 12
1755 #define PWM_PHCHGNXT_PWM4_Msk (1ul << PWM_PHCHGNXT_PWM4_Pos)
1757 #define PWM_PHCHGNXT_PWM3_Pos 11
1758 #define PWM_PHCHGNXT_PWM3_Msk (1ul << PWM_PHCHGNXT_PWM3_Pos)
1760 #define PWM_PHCHGNXT_PWM2_Pos 10
1761 #define PWM_PHCHGNXT_PWM2_Msk (1ul << PWM_PHCHGNXT_PWM2_Pos)
1763 #define PWM_PHCHGNXT_PWM1_Pos 9
1764 #define PWM_PHCHGNXT_PWM1_Msk (1ul << PWM_PHCHGNXT_PWM1_Pos)
1766 #define PWM_PHCHGNXT_PWM0_Pos 8
1767 #define PWM_PHCHGNXT_PWM0_Msk (1ul << PWM_PHCHGNXT_PWM0_Pos)
1769 #define PWM_PHCHGNXT_D7_Pos 7
1770 #define PWM_PHCHGNXT_D7_Msk (1ul << PWM_PHCHGNXT_D7_Pos)
1772 #define PWM_PHCHGNXT_D6_Pos 6
1773 #define PWM_PHCHGNXT_D6_Msk (1ul << PWM_PHCHGNXT_D6_Pos)
1775 #define PWM_PHCHGNXT_D5_Pos 5
1776 #define PWM_PHCHGNXT_D5_Msk (1ul << PWM_PHCHGNXT_D5_Pos)
1778 #define PWM_PHCHGNXT_D4_Pos 4
1779 #define PWM_PHCHGNXT_D4_Msk (1ul << PWM_PHCHGNXT_D4_Pos)
1781 #define PWM_PHCHGNXT_D3_Pos 3
1782 #define PWM_PHCHGNXT_D3_Msk (1ul << PWM_PHCHGNXT_D3_Pos)
1784 #define PWM_PHCHGNXT_D2_Pos 2
1785 #define PWM_PHCHGNXT_D2_Msk (1ul << PWM_PHCHGNXT_D2_Pos)
1787 #define PWM_PHCHGNXT_D1_Pos 1
1788 #define PWM_PHCHGNXT_D1_Msk (1ul << PWM_PHCHGNXT_D1_Pos)
1790 #define PWM_PHCHGNXT_D0_Pos 0
1791 #define PWM_PHCHGNXT_D0_Msk (1ul << PWM_PHCHGNXT_D0_Pos)
1793 /* PWM PHCHGMASK Bit Field Definitions */
1794 #define PWM_PHCHGMASK_CMPMASK_Pos 8
1795 #define PWM_PHCHGMASK_CMPMASK_Msk (3ul << PWM_PHCHGMASK_CMPMASK_Pos)
1797 #define PWM_PHCHGMASK_MASK7_Pos 7
1798 #define PWM_PHCHGMASK_MASK7_Msk (1ul << PWM_PHCHGMASK_MASK7_Pos)
1800 #define PWM_PHCHGMASK_MASK6_Pos 6
1801 #define PWM_PHCHGMASK_MASK6_Msk (1ul << PWM_PHCHGMASK_MASK6_Pos)
1803 /* PWM INTACCUCTL Bit Field Definitions */
1804 #define PWM_INTACCUCTL_PERIODCNT_Pos 4
1805 #define PWM_INTACCUCTL_PERIODCNT_Msk (0xFul << PWM_INTACCUCTL_PERIODCNT_Pos)
1807 #define PWM_INTACCUCTL_INTACCUEN0_Pos 0
1808 #define PWM_INTACCUCTL_INTACCUEN0_Msk (1ul << PWM_INTACCUCTL_INTACCUEN0_Pos)
1809
1811 /* end of group PWM */
1812
1813
1814 /*---------------------- Serial Peripheral Interface Controller -------------------------*/
1815
1821 typedef struct
1822 {
1823 __IO uint32_t CNTRL;
1824 __IO uint32_t DIVIDER;
1825 __IO uint32_t SSR;
1826 uint32_t RESERVED0;
1827 __I uint32_t RX;
1828 uint32_t RESERVED1[3];
1829 __O uint32_t TX;
1830 uint32_t RESERVED2[6];
1831 __IO uint32_t CNTRL2;
1832 __IO uint32_t FIFO_CTL;
1833 __IO uint32_t STATUS;
1834 } SPI_T;
1836 /* SPI_CNTRL Bit Field Definitions */
1837 #define SPI_CNTRL_TX_FULL_Pos 27
1838 #define SPI_CNTRL_TX_FULL_Msk (1ul << SPI_CNTRL_TX_FULL_Pos)
1840 #define SPI_CNTRL_TX_EMPTY_Pos 26
1841 #define SPI_CNTRL_TX_EMPTY_Msk (1ul << SPI_CNTRL_TX_EMPTY_Pos)
1843 #define SPI_CNTRL_RX_FULL_Pos 25
1844 #define SPI_CNTRL_RX_FULL_Msk (1ul << SPI_CNTRL_RX_FULL_Pos)
1846 #define SPI_CNTRL_RX_EMPTY_Pos 24
1847 #define SPI_CNTRL_RX_EMPTY_Msk (1ul << SPI_CNTRL_RX_EMPTY_Pos)
1849 #define SPI_CNTRL_FIFO_Pos 21
1850 #define SPI_CNTRL_FIFO_Msk (1ul << SPI_CNTRL_FIFO_Pos)
1852 #define SPI_CNTRL_REORDER_Pos 19
1853 #define SPI_CNTRL_REORDER_Msk (3ul << SPI_CNTRL_REORDER_Pos)
1855 #define SPI_CNTRL_SLAVE_Pos 18
1856 #define SPI_CNTRL_SLAVE_Msk (1ul << SPI_CNTRL_SLAVE_Pos)
1858 #define SPI_CNTRL_IE_Pos 17
1859 #define SPI_CNTRL_IE_Msk (1ul << SPI_CNTRL_IE_Pos)
1861 #define SPI_CNTRL_IF_Pos 16
1862 #define SPI_CNTRL_IF_Msk (1ul << SPI_CNTRL_IF_Pos)
1864 #define SPI_CNTRL_SP_CYCLE_Pos 12
1865 #define SPI_CNTRL_SP_CYCLE_Msk (0xFul << SPI_CNTRL_SP_CYCLE_Pos)
1867 #define SPI_CNTRL_CLKP_Pos 11
1868 #define SPI_CNTRL_CLKP_Msk (1ul << SPI_CNTRL_CLKP_Pos)
1870 #define SPI_CNTRL_LSB_Pos 10
1871 #define SPI_CNTRL_LSB_Msk (1ul << SPI_CNTRL_LSB_Pos)
1873 #define SPI_CNTRL_TX_BIT_LEN_Pos 3
1874 #define SPI_CNTRL_TX_BIT_LEN_Msk (0x1Ful << SPI_CNTRL_TX_BIT_LEN_Pos)
1876 #define SPI_CNTRL_TX_NEG_Pos 2
1877 #define SPI_CNTRL_TX_NEG_Msk (1ul << SPI_CNTRL_TX_NEG_Pos)
1879 #define SPI_CNTRL_RX_NEG_Pos 1
1880 #define SPI_CNTRL_RX_NEG_Msk (1ul << SPI_CNTRL_RX_NEG_Pos)
1882 #define SPI_CNTRL_GO_BUSY_Pos 0
1883 #define SPI_CNTRL_GO_BUSY_Msk (1ul << SPI_CNTRL_GO_BUSY_Pos)
1885 /* SPI_DIVIDER Bit Field Definitions */
1886 #define SPI_DIVIDER_DIVIDER_Pos 0
1887 #define SPI_DIVIDER_DIVIDER_Msk (0xFul << SPI_DIVIDER_DIVIDER_Pos)
1889 /* SPI_SSR Bit Field Definitions */
1890 #define SPI_SSR_LTRIG_FLAG_Pos 5
1891 #define SPI_SSR_LTRIG_FLAG_Msk (1ul << SPI_SSR_LTRIG_FLAG_Pos)
1893 #define SPI_SSR_SS_LTRIG_Pos 4
1894 #define SPI_SSR_SS_LTRIG_Msk (1ul << SPI_SSR_SS_LTRIG_Pos)
1896 #define SPI_SSR_AUTOSS_Pos 3
1897 #define SPI_SSR_AUTOSS_Msk (1ul << SPI_SSR_AUTOSS_Pos)
1899 #define SPI_SSR_SS_LVL_Pos 2
1900 #define SPI_SSR_SS_LVL_Msk (1ul << SPI_SSR_SS_LVL_Pos)
1902 #define SPI_SSR_SSR_Pos 0
1903 #define SPI_SSR_SSR_Msk (1ul << SPI_SSR_SSR_Pos)
1905 /* SPI_CNTRL2 Bit Field Definitions */
1906 #define SPI_CNTRL2_BCn_Pos 31
1907 #define SPI_CNTRL2_BCn_Msk (1ul << SPI_CNTRL2_BCn_Pos)
1909 #define SPI_CNTRL2_SS_INT_OPT_Pos 16
1910 #define SPI_CNTRL2_SS_INT_OPT_Msk (1ul << SPI_CNTRL2_SS_INT_OPT_Pos)
1912 #define SPI_CNTRL2_SLV_START_INTSTS_Pos 11
1913 #define SPI_CNTRL2_SLV_START_INTSTS_Msk (1ul << SPI_CNTRL2_SLV_START_INTSTS_Pos)
1915 #define SPI_CNTRL2_SSTA_INTEN_Pos 10
1916 #define SPI_CNTRL2_SSTA_INTEN_Msk (1ul << SPI_CNTRL2_SSTA_INTEN_Pos)
1918 #define SPI_CNTRL2_SLV_ABORT_Pos 9
1919 #define SPI_CNTRL2_SLV_ABORT_Msk (1ul << SPI_CNTRL2_SLV_ABORT_Pos)
1921 #define SPI_CNTRL2_NOSLVSEL_Pos 8
1922 #define SPI_CNTRL2_NOSLVSEL_Msk (1ul << SPI_CNTRL2_NOSLVSEL_Pos)
1924 /* SPI_FIFO_CTL Bit Field Definitions */
1925 #define SPI_FIFO_CTL_TX_THRESHOLD_Pos 28
1926 #define SPI_FIFO_CTL_TX_THRESHOLD_Msk (3ul << SPI_FIFO_CTL_TX_THRESHOLD_Pos)
1928 #define SPI_FIFO_CTL_RX_THRESHOLD_Pos 24
1929 #define SPI_FIFO_CTL_RX_THRESHOLD_Msk (3ul << SPI_FIFO_CTL_RX_THRESHOLD_Pos)
1931 #define SPI_FIFO_CTL_TIMEOUT_INTEN_Pos 21
1932 #define SPI_FIFO_CTL_TIMEOUT_INTEN_Msk (1ul << SPI_FIFO_CTL_TIMEOUT_INTEN_Pos)
1934 #define SPI_FIFO_CTL_RXOV_INTEN_Pos 6
1935 #define SPI_FIFO_CTL_RXOV_INTEN_Msk (1ul << SPI_FIFO_CTL_RXOV_INTEN_Pos)
1937 #define SPI_FIFO_CTL_TX_INTEN_Pos 3
1938 #define SPI_FIFO_CTL_TX_INTEN_Msk (1ul << SPI_FIFO_CTL_TX_INTEN_Pos)
1940 #define SPI_FIFO_CTL_RX_INTEN_Pos 2
1941 #define SPI_FIFO_CTL_RX_INTEN_Msk (1ul << SPI_FIFO_CTL_RX_INTEN_Pos)
1943 #define SPI_FIFO_CTL_TX_CLR_Pos 1
1944 #define SPI_FIFO_CTL_TX_CLR_Msk (1ul << SPI_FIFO_CTL_TX_CLR_Pos)
1946 #define SPI_FIFO_CTL_RX_CLR_Pos 0
1947 #define SPI_FIFO_CTL_RX_CLR_Msk (1ul << SPI_FIFO_CTL_RX_CLR_Pos)
1949 /* SPI_STATUS Bit Field Definitions */
1950 #define SPI_STATUS_TX_FIFO_COUNT_Pos 28
1951 #define SPI_STATUS_TX_FIFO_COUNT_Msk (0xFul << SPI_STATUS_TX_FIFO_COUNT_Pos)
1953 #define SPI_STATUS_TX_FULL_Pos 27
1954 #define SPI_STATUS_TX_FULL_Msk (1ul << SPI_STATUS_TX_FULL_Pos)
1956 #define SPI_STATUS_TX_EMPTY_Pos 26
1957 #define SPI_STATUS_TX_EMPTY_Msk (1ul << SPI_STATUS_TX_EMPTY_Pos)
1959 #define SPI_STATUS_RX_FULL_Pos 25
1960 #define SPI_STATUS_RX_FULL_Msk (1ul << SPI_STATUS_RX_FULL_Pos)
1962 #define SPI_STATUS_RX_EMPTY_Pos 24
1963 #define SPI_STATUS_RX_EMPTY_Msk (1ul << SPI_STATUS_RX_EMPTY_Pos)
1965 #define SPI_STATUS_TIMEOUT_Pos 20
1966 #define SPI_STATUS_TIMEOUT_Msk (1ul << SPI_STATUS_TIMEOUT_Pos)
1968 #define SPI_STATUS_IF_Pos 16
1969 #define SPI_STATUS_IF_Msk (1ul << SPI_STATUS_IF_Pos)
1971 #define SPI_STATUS_RX_FIFO_COUNT_Pos 12
1972 #define SPI_STATUS_RX_FIFO_COUNT_Msk (0xFul << SPI_STATUS_RX_FIFO_COUNT_Pos)
1974 #define SPI_STATUS_SLV_START_INTSTS_Pos 11
1975 #define SPI_STATUS_SLV_START_INTSTS_Msk (1ul << SPI_STATUS_SLV_START_INTSTS_Pos)
1977 #define SPI_STATUS_TX_INTSTS_Pos 4
1978 #define SPI_STATUS_TX_INTSTS_Msk (1ul << SPI_STATUS_TX_INTSTS_Pos)
1980 #define SPI_STATUS_RX_OVERRUN_Pos 2
1981 #define SPI_STATUS_RX_OVERRUN_Msk (1ul << SPI_STATUS_RX_OVERRUN_Pos)
1983 #define SPI_STATUS_RX_INTSTS_Pos 0
1984 #define SPI_STATUS_RX_INTSTS_Msk (1ul << SPI_STATUS_RX_INTSTS_Pos)
1985 /* end of group SPI */
1987
1988
1989
1990 /*---------------------------- System Controller -----------------------------*/
1991
1996 typedef struct
1997 {
2008 __I uint32_t PDID;
2009
2045 __IO uint32_t RSTSRC;
2046
2073 __IO uint32_t IPRSTC1;
2074
2110 __IO uint32_t IPRSTC2;
2111
2118 uint32_t RESERVED0[2];
2119
2156 __IO uint32_t BODCTL;
2157
2164 uint32_t RESERVED1[5];
2165
2221 __IO uint32_t P0_MFP;
2222
2272 __IO uint32_t P1_MFP;
2273
2323 __IO uint32_t P2_MFP;
2324
2384 __IO uint32_t P3_MFP;
2385
2412 __IO uint32_t P4_MFP;
2413
2464 __IO uint32_t P5_MFP;
2465
2472 uint32_t RESERVED3[14];
2473
2501 __IO uint32_t IRCTRIMCTL;
2502
2525 __IO uint32_t IRCTRIMIER;
2526
2552 __IO uint32_t IRCTRIMISR;
2553
2560 uint32_t RESERVED4[29];
2561
2585 __IO uint32_t RegLockAddr;
2586 } SYS_T;
2588 /* SYS RSTSRC Bit Field Definitions */
2589 #define SYS_RSTSRC_RSTS_CPU_Pos 7
2590 #define SYS_RSTSRC_RSTS_CPU_Msk (1ul << SYS_RSTSRC_RSTS_CPU_Pos)
2592 #define SYS_RSTSRC_RSTS_MCU_Pos 5
2593 #define SYS_RSTSRC_RSTS_MCU_Msk (1ul << SYS_RSTSRC_RSTS_MCU_Pos)
2595 #define SYS_RSTSRC_RSTS_BOD_Pos 4
2596 #define SYS_RSTSRC_RSTS_BOD_Msk (1ul << SYS_RSTSRC_RSTS_BOD_Pos)
2598 #define SYS_RSTSRC_RSTS_WDT_Pos 2
2599 #define SYS_RSTSRC_RSTS_WDT_Msk (1ul << SYS_RSTSRC_RSTS_WDT_Pos)
2601 #define SYS_RSTSRC_RSTS_RESET_Pos 1
2602 #define SYS_RSTSRC_RSTS_RESET_Msk (1ul << SYS_RSTSRC_RSTS_RESET_Pos)
2604 #define SYS_RSTSRC_RSTS_POR_Pos 0
2605 #define SYS_RSTSRC_RSTS_POR_Msk (1ul << SYS_RSTSRC_RSTS_POR_Pos)
2607 /* SYS IPRSTC1 Bit Field Definitions */
2608 #define SYS_IPRSTC1_CPU_RST_Pos 1
2609 #define SYS_IPRSTC1_CPU_RST_Msk (1ul << SYS_IPRSTC1_CPU_RST_Pos)
2611 #define SYS_IPRSTC1_CHIP_RST_Pos 0
2612 #define SYS_IPRSTC1_CHIP_RST_Msk (1ul << SYS_IPRSTC1_CHIP_RST_Pos)
2614 /* SYS IPRSTC2 Bit Field Definitions */
2615 #define SYS_IPRSTC2_ADC_RST_Pos 28
2616 #define SYS_IPRSTC2_ADC_RST_Msk (1ul << SYS_IPRSTC2_ADC_RST_Pos)
2618 #define SYS_IPRSTC2_ACMP_RST_Pos 22
2619 #define SYS_IPRSTC2_ACMP_RST_Msk (1ul << SYS_IPRSTC2_ACMP_RST_Pos)
2621 #define SYS_IPRSTC2_PWM_RST_Pos 20
2622 #define SYS_IPRSTC2_PWM_RST_Msk (1ul << SYS_IPRSTC2_PWM_RST_Pos)
2624 #define SYS_IPRSTC2_UART_RST_Pos 16
2625 #define SYS_IPRSTC2_UART_RST_Msk (1ul << SYS_IPRSTC2_UART_RST_Pos)
2627 #define SYS_IPRSTC2_SPI_RST_Pos 12
2628 #define SYS_IPRSTC2_SPI_RST_Msk (1ul << SYS_IPRSTC2_SPI_RST_Pos)
2630 #define SYS_IPRSTC2_I2C_RST_Pos 8
2631 #define SYS_IPRSTC2_I2C_RST_Msk (1ul << SYS_IPRSTC2_I2C_RST_Pos)
2633 #define SYS_IPRSTC2_TMR1_RST_Pos 3
2634 #define SYS_IPRSTC2_TMR1_RST_Msk (1ul << SYS_IPRSTC2_TMR1_RST_Pos)
2636 #define SYS_IPRSTC2_TMR0_RST_Pos 2
2637 #define SYS_IPRSTC2_TMR0_RST_Msk (1ul << SYS_IPRSTC2_TMR0_RST_Pos)
2639 #define SYS_IPRSTC2_GPIO_RST_Pos 1
2640 #define SYS_IPRSTC2_GPIO_RST_Msk (1ul << SYS_IPRSTC2_GPIO_RST_Pos)
2642 /* SYS BODCR Bit Field Definitions */
2643 #define SYS_BODCR_BOD_OUT_Pos 6
2644 #define SYS_BODCR_BOD_OUT_Msk (1ul << SYS_BODCR_BOD_OUT_Pos)
2646 #define SYS_BODCR_BOD_LPM_Pos 5
2647 #define SYS_BODCR_BOD_LPM_Msk (1ul << SYS_BODCR_BOD_LPM_Pos)
2649 #define SYS_BODCR_BOD_INTF_Pos 4
2650 #define SYS_BODCR_BOD_INTF_Msk (1ul << SYS_BODCR_BOD_INTF_Pos)
2652 #define SYS_BODCR_BOD_RSTEN_Pos 3
2653 #define SYS_BODCR_BOD_RSTEN_Msk (1ul << SYS_BODCR_BOD_RSTEN_Pos)
2655 #define SYS_BODCR_BOD_VL_Pos 1
2656 #define SYS_BODCR_BOD_VL_Msk (3ul << SYS_BODCR_BOD_VL_Pos)
2658 #define SYS_BODCR_BOD_VL_EXT_Pos 0
2659 #define SYS_BODCR_BOD_VL_EXT_Msk (1ul << SYS_BODCR_BOD_VL_EXT_Pos)
2661 /* SYS P0_MFP Bit Field Definitions */
2662 #define SYS_P0_MFP_P0_TYPE_Pos 16
2663 #define SYS_P0_MFP_P0_TYPE_Msk (0xFFul << SYS_P0_MFP_P0_TYPE_Pos)
2665 #define SYS_P0_MFP_P0_ALT_Pos 8
2666 #define SYS_P0_MFP_P0_ALT_Msk (0xFFul << SYS_P0_MFP_P0_ALT_Pos)
2668 #define SYS_P0_MFP_P0_MFP_Pos 0
2669 #define SYS_P0_MFP_P0_MFP_Msk (0xFFul << SYS_P0_MFP_P0_MFP_Pos)
2671 /* SYS P1_MFP Bit Field Definitions */
2672 #define SYS_P1_MFP_P1_TYPE_Pos 16
2673 #define SYS_P1_MFP_P1_TYPE_Msk (0xFFul << SYS_P1_MFP_P1_TYPE_Pos)
2675 #define SYS_P1_MFP_P1_ALT_Pos 8
2676 #define SYS_P1_MFP_P1_ALT_Msk (0xFFul << SYS_P1_MFP_P1_ALT_Pos)
2678 #define SYS_P1_MFP_P1_MFP_Pos 0
2679 #define SYS_P1_MFP_P1_MFP_Msk (0xFFul << SYS_P1_MFP_P1_MFP_Pos)
2681 /* SYS P2_MFP Bit Field Definitions */
2682 #define SYS_P2_MFP_P2_TYPE_Pos 16
2683 #define SYS_P2_MFP_P2_TYPE_Msk (0xFFul << SYS_P2_MFP_P2_TYPE_Pos)
2685 #define SYS_P2_MFP_P2_ALT_Pos 8
2686 #define SYS_P2_MFP_P2_ALT_Msk (0xFFul << SYS_P2_MFP_P2_ALT_Pos)
2688 #define SYS_P2_MFP_P2_MFP_Pos 0
2689 #define SYS_P2_MFP_P2_MFP_Msk (0xFFul << SYS_P2_MFP_P2_MFP_Pos)
2691 /* SYS P3_MFP Bit Field Definitions */
2692 #define SYS_P3_MFP_P3_TYPE_Pos 16
2693 #define SYS_P3_MFP_P3_TYPE_Msk (0xFFul << SYS_P3_MFP_P3_TYPE_Pos)
2695 #define SYS_P3_MFP_P3_ALT_Pos 8
2696 #define SYS_P3_MFP_P3_ALT_Msk (0xFFul << SYS_P3_MFP_P3_ALT_Pos)
2698 #define SYS_P3_MFP_P3_MFP_Pos 0
2699 #define SYS_P3_MFP_P3_MFP_Msk (0xFFul << SYS_P3_MFP_P3_MFP_Pos)
2701 /* SYS P4_MFP Bit Field Definitions */
2702 #define SYS_P4_MFP_P4_TYPE_Pos 16
2703 #define SYS_P4_MFP_P4_TYPE_Msk (0xFFul << SYS_P4_MFP_P4_TYPE_Pos)
2705 #define SYS_P4_MFP_P4_ALT_Pos 8
2706 #define SYS_P4_MFP_P4_ALT_Msk (0xFFul << SYS_P4_MFP_P4_ALT_Pos)
2708 #define SYS_P4_MFP_P4_MFP_Pos 0
2709 #define SYS_P4_MFP_P4_MFP_Msk (0xFFul << SYS_P4_MFP_P4_MFP_Pos)
2711 /* SYS P5_MFP Bit Field Definitions */
2712 #define SYS_P5_MFP_P5_TYPE_Pos 16
2713 #define SYS_P5_MFP_P5_TYPE_Msk (0xFFul << SYS_P5_MFP_P5_TYPE_Pos)
2715 #define SYS_P5_MFP_P5_ALT_Pos 8
2716 #define SYS_P5_MFP_P5_ALT_Msk (0xFFul << SYS_P5_MFP_P5_ALT_Pos)
2718 #define SYS_P5_MFP_P5_MFP_Pos 0
2719 #define SYS_P5_MFP_P5_MFP_Msk (0xFFul << SYS_P5_MFP_P5_MFP_Pos)
2721 /* SYS IRCTRIMCTL Bit Field Definitions */
2722 #define SYS_IRCTRIMCTL_TRIM_LOOP_Pos 3
2723 #define SYS_IRCTRIMCTL_TRIM_LOOP_Msk (0x3ul << SYS_IRCTRIMCTL_TRIM_LOOP_Pos)
2725 #define SYS_IRCTRIMCTL_TRIM_SEL_Pos 0
2726 #define SYS_IRCTRIMCTL_TRIM_SEL_Msk (0x1ul << SYS_IRCTRIMCTL_TRIM_SEL_Pos)
2728 /* SYS IRCTRIMIEN Bit Field Definitions */
2729 #define SYS_IRCTRIMIEN_32K_ERR_IEN_Pos 2
2730 #define SYS_IRCTRIMIEN_32K_ERR_IEN_Msk (0x1ul << SYS_IRCTRIMIEN_32K_ERR_IEN_Pos)
2732 #define SYS_IRCTRIMIEN_TRIM_FAIL_IEN_Pos 1
2733 #define SYS_IRCTRIMIEN_TRIM_FAIL_IEN_Msk (0x1ul << SYS_IRCTRIMIEN_TRIM_FAIL_IEN_Pos)
2735 /* SYS IRCTRIMINT Bit Field Definitions */
2736 #define SYS_IRCTRIMINT_32K_ERR_INT_Pos 2
2737 #define SYS_IRCTRIMINT_32K_ERR_INT_Msk (0x1ul << SYS_IRCTRIMINT_32K_ERR_IEN_Pos)
2739 #define SYS_IRCTRIMINT_TRIM_FAIL_INT_Pos 1
2740 #define SYS_IRCTRIMINT_TRIM_FAIL_INT_Msk (0x1ul << SYS_IRCTRIMINT_TRIM_FAIL_IEN_Pos)
2742 #define SYS_IRCTRIMINT_FREQ_LOCK_Pos 0
2743 #define SYS_IRCTRIMINT_FREQ_LOCK_Msk (0x1ul << SYS_IRCTRIMINT_FREQ_LOCK_Pos)
2745 /* SYS RegLockAddr Bit Field Definitions */
2746 #define SYS_RegLockAddr_RegUnLock_Pos 0
2747 #define SYS_RegLockAddr_RegUnLock_Msk (0x1ul << SYS_RegLockAddr_RegUnLock_Pos)
2748 /* end of group SYS */
2750
2751
2752
2753 /*----------------------------- Timer Controller -----------------------------*/
2759 typedef struct
2760 {
2761 __IO uint32_t TCSR;
2762 __IO uint32_t TCMPR;
2763 __IO uint32_t TISR;
2764 __I uint32_t TDR;
2765 __I uint32_t TCAP;
2766 __IO uint32_t TEXCON;
2767 __IO uint32_t TEXISR;
2768 } TIMER_T;
2770 /* TIMER TCSR Bit Field Definitions */
2771 #define TIMER_TCSR_DBGACK_TMR_Pos 31
2772 #define TIMER_TCSR_DBGACK_TMR_Msk (1ul << TIMER_TCSR_DBGACK_TMR_Pos)
2774 #define TIMER_TCSR_CEN_Pos 30
2775 #define TIMER_TCSR_CEN_Msk (1ul << TIMER_TCSR_CEN_Pos)
2777 #define TIMER_TCSR_IE_Pos 29
2778 #define TIMER_TCSR_IE_Msk (1ul << TIMER_TCSR_IE_Pos)
2780 #define TIMER_TCSR_MODE_Pos 27
2781 #define TIMER_TCSR_MODE_Msk (0x3ul << TIMER_TCSR_MODE_Pos)
2783 #define TIMER_TCSR_CRST_Pos 26
2784 #define TIMER_TCSR_CRST_Msk (1ul << TIMER_TCSR_CRST_Pos)
2786 #define TIMER_TCSR_CACT_Pos 25
2787 #define TIMER_TCSR_CACT_Msk (1ul << TIMER_TCSR_CACT_Pos)
2789 #define TIMER_TCSR_CTB_Pos 24
2790 #define TIMER_TCSR_CTB_Msk (1ul << TIMER_TCSR_CTB_Pos)
2792 #define TIMER_TCSR_WAKE_EN_Pos 23
2793 #define TIMER_TCSR_WAKE_EN_Msk (1ul << TIMER_TCSR_WAKE_EN_Pos)
2795 #define TIMER_TCSR_CAP_SRC_Pos 19
2796 #define TIMER_TCSR_CAP_SRC_Msk (1ul << TIMER_TCSR_CAP_SRC_Pos)
2798 #define TIMER_TCSR_TOGGLE_PIN_Pos 18
2799 #define TIMER_TCSR_TOGGLE_PIN_Msk (1ul << TIMER_TCSR_TOGGLE_PIN_Pos)
2801 #define TIMER_TCSR_PERIODIC_SEL_Pos 17
2802 #define TIMER_TCSR_PERIODIC_SEL_Msk (1ul << TIMER_TCSR_PERIODIC_SEL_Pos)
2804 #define TIMER_TCSR_TDR_EN_Pos 16
2805 #define TIMER_TCSR_TDR_EN_Msk (1ul << TIMER_TCSR_TDR_EN_Pos)
2807 #define TIMER_TCSR_PRESCALE_Pos 0
2808 #define TIMER_TCSR_PRESCALE_Msk (0xFFul << TIMER_TCSR_PRESCALE_Pos)
2810 /* TIMER TCMPR Bit Field Definitions */
2811 #define TIMER_TCMP_TCMP_Pos 0
2812 #define TIMER_TCMP_TCMP_Msk (0xFFFFFFul << TIMER_TCMP_TCMP_Pos)
2814 /* TIMER TISR Bit Field Definitions */
2815 #define TIMER_TISR_TWF_Pos 1
2816 #define TIMER_TISR_TWF_Msk (1ul << TIMER_TISR_TWF_Pos)
2818 #define TIMER_TISR_TIF_Pos 0
2819 #define TIMER_TISR_TIF_Msk (1ul << TIMER_TISR_TIF_Pos)
2821 /* TIMER TDR Bit Field Definitions */
2822 #define TIMER_TDR_TDR_Pos 0
2823 #define TIMER_TDR_TDR_Msk (0xFFFFFFul << TIMER_TDR_TDR_Pos)
2825 /* TIMER TCAP Bit Field Definitions */
2826 #define TIMER_TCAP_TCAP_Pos 0
2827 #define TIMER_TCAP_TCAP_Msk (0xFFFFFFul << TIMER_TCAP_TCAP_Pos)
2829 /* TIMER TEXCON Bit Field Definitions */
2830 #define TIMER_TEXCON_CAP_MODE_Pos 8
2831 #define TIMER_TEXCON_CAP_MODE_Msk (1ul << TIMER_TEXCON_CAP_MODE_Pos)
2833 #define TIMER_TEXCON_TCDB_Pos 7
2834 #define TIMER_TEXCON_TCDB_Msk (1ul << TIMER_TEXCON_TCDB_Pos)
2836 #define TIMER_TEXCON_TEXDB_Pos 6
2837 #define TIMER_TEXCON_TEXDB_Msk (1ul << TIMER_TEXCON_TEXDB_Pos)
2839 #define TIMER_TEXCON_TEXIEN_Pos 5
2840 #define TIMER_TEXCON_TEXIEN_Msk (1ul << TIMER_TEXCON_TEXIEN_Pos)
2842 #define TIMER_TEXCON_RSTCAPSEL_Pos 4
2843 #define TIMER_TEXCON_RSTCAPSEL_Msk (1ul << TIMER_TEXCON_RSTCAPSEL_Pos)
2845 #define TIMER_TEXCON_TEXEN_Pos 3
2846 #define TIMER_TEXCON_TEXEN_Msk (1ul << TIMER_TEXCON_TEXEN_Pos)
2848 #define TIMER_TEXCON_TEX_EDGE_Pos 1
2849 #define TIMER_TEXCON_TEX_EDGE_Msk (0x3ul << TIMER_TEXCON_TEX_EDGE_Pos)
2851 #define TIMER_TEXCON_TX_PHASE_Pos 0
2852 #define TIMER_TEXCON_TX_PHASE_Msk (1ul << TIMER_TEXCON_TX_PHASE_Pos)
2854 /* TIMER TEXISR Bit Field Definitions */
2855 #define TIMER_TEXISR_TEXIF_Pos 0
2856 #define TIMER_TEXISR_TEXIF_Msk (1ul << TIMER_TEXISR_TEXIF_Pos)
2857 /* end of group TIMER */
2859
2860
2861 /*---------------------- Universal Asynchronous Receiver/Transmitter Controller -------------------------*/
2862
2867 typedef struct
2868 {
2869 union
2870 {
2871 __I uint32_t RBR;
2872 __O uint32_t THR;
2873 };
2874 __IO uint32_t IER;
2875 __IO uint32_t FCR;
2876 __IO uint32_t LCR;
2877 __IO uint32_t MCR;
2878 __IO uint32_t MSR;
2879 __IO uint32_t FSR;
2880 __IO uint32_t ISR;
2881 __IO uint32_t TOR;
2882 __IO uint32_t BAUD;
2883 __IO uint32_t IRCR;
2884 __IO uint32_t ALT_CSR;
2885 __IO uint32_t FUN_SEL;
2886 } UART_T;
2888 /* UART THR Bit Field Definitions */
2889 #define UART_THR_THR_Pos 0
2890 #define UART_THR_THR_Msk (0xFul << UART_THR_THR_Pos)
2892 /* UART RBR Bit Field Definitions */
2893 #define UART_RBR_RBR_Pos 0
2894 #define UART_RBR_RBR_Msk (0xFul << UART_RBR_RBR_Pos)
2896 /* UART IER Bit Field Definitions */
2897 #define UART_IER_AUTO_CTS_EN_Pos 13
2898 #define UART_IER_AUTO_CTS_EN_Msk (1ul << UART_IER_AUTO_CTS_EN_Pos)
2900 #define UART_IER_AUTO_RTS_EN_Pos 12
2901 #define UART_IER_AUTO_RTS_EN_Msk (1ul << UART_IER_AUTO_RTS_EN_Pos)
2903 #define UART_IER_TIME_OUT_EN_Pos 11
2904 #define UART_IER_TIME_OUT_EN_Msk (1ul << UART_IER_TIME_OUT_EN_Pos)
2906 #define UART_IER_WAKE_EN_Pos 6
2907 #define UART_IER_WAKE_EN_Msk (1ul << UART_IER_WAKE_EN_Pos)
2909 #define UART_IER_BUF_ERR_IEN_Pos 5
2910 #define UART_IER_BUF_ERR_IEN_Msk (1ul << UART_IER_BUF_ERR_IEN_Pos)
2912 #define UART_IER_RTO_IEN_Pos 4
2913 #define UART_IER_RTO_IEN_Msk (1ul << UART_IER_RTO_IEN_Pos)
2915 #define UART_IER_MODEM_IEN_Pos 3
2916 #define UART_IER_MODEM_IEN_Msk (1ul << UART_IER_MODEM_IEN_Pos)
2918 #define UART_IER_RLS_IEN_Pos 2
2919 #define UART_IER_RLS_IEN_Msk (1ul << UART_IER_RLS_IEN_Pos)
2921 #define UART_IER_THRE_IEN_Pos 1
2922 #define UART_IER_THRE_IEN_Msk (1ul << UART_IER_THRE_IEN_Pos)
2924 #define UART_IER_RDA_IEN_Pos 0
2925 #define UART_IER_RDA_IEN_Msk (1ul << UART_IER_RDA_IEN_Pos)
2927 /* UART FCR Bit Field Definitions */
2928 #define UART_FCR_RTS_TRI_LEV_Pos 16
2929 #define UART_FCR_RTS_TRI_LEV_Msk (0xFul << UART_FCR_RTS_TRI_LEV_Pos)
2931 #define UART_FCR_RX_DIS_Pos 8
2932 #define UART_FCR_RX_DIS_Msk (1ul << UART_FCR_RX_DIS_Pos)
2934 #define UART_FCR_RFITL_Pos 4
2935 #define UART_FCR_RFITL_Msk (0xFul << UART_FCR_RFITL_Pos)
2937 #define UART_FCR_TFR_Pos 2
2938 #define UART_FCR_TFR_Msk (1ul << UART_FCR_TFR_Pos)
2940 #define UART_FCR_RFR_Pos 1
2941 #define UART_FCR_RFR_Msk (1ul << UART_FCR_RFR_Pos)
2943 /* UART LCR Bit Field Definitions */
2944 #define UART_LCR_BCB_Pos 6
2945 #define UART_LCR_BCB_Msk (1ul << UART_LCR_BCB_Pos)
2947 #define UART_LCR_SPE_Pos 5
2948 #define UART_LCR_SPE_Msk (1ul << UART_LCR_SPE_Pos)
2950 #define UART_LCR_EPE_Pos 4
2951 #define UART_LCR_EPE_Msk (1ul << UART_LCR_EPE_Pos)
2953 #define UART_LCR_PBE_Pos 3
2954 #define UART_LCR_PBE_Msk (1ul << UART_LCR_PBE_Pos)
2956 #define UART_LCR_NSB_Pos 2
2957 #define UART_LCR_NSB_Msk (1ul << UART_LCR_NSB_Pos)
2959 #define UART_LCR_WLS_Pos 0
2960 #define UART_LCR_WLS_Msk (0x3ul << UART_LCR_WLS_Pos)
2962 /* UART MCR Bit Field Definitions */
2963 #define UART_MCR_RTS_ST_Pos 13
2964 #define UART_MCR_RTS_ST_Msk (1ul << UART_MCR_RTS_ST_Pos)
2966 #define UART_MCR_LEV_RTS_Pos 9
2967 #define UART_MCR_LEV_RTS_Msk (1ul << UART_MCR_LEV_RTS_Pos)
2969 #define UART_MCR_RTS_Pos 1
2970 #define UART_MCR_RTS_Msk (1ul << UART_MCR_RTS_Pos)
2973 /* UART MSR Bit Field Definitions */
2974 #define UART_MSR_LEV_CTS_Pos 8
2975 #define UART_MSR_LEV_CTS_Msk (1ul << UART_MSR_LEV_CTS_Pos)
2977 #define UART_MSR_CTS_ST_Pos 4
2978 #define UART_MSR_CTS_ST_Msk (1ul << UART_MSR_CTS_ST_Pos)
2980 #define UART_MSR_DCTSF_Pos 0
2981 #define UART_MSR_DCTSF_Msk (1ul << UART_MSR_DCTSF_Pos)
2984 /* UART FSR Bit Field Definitions */
2985 #define UART_FSR_TE_FLAG_Pos 28
2986 #define UART_FSR_TE_FLAG_Msk (1ul << UART_FSR_TE_FLAG_Pos)
2988 #define UART_FSR_TX_OVER_IF_Pos 24
2989 #define UART_FSR_TX_OVER_IF_Msk (1ul << UART_FSR_TX_OVER_IF_Pos)
2991 #define UART_FSR_TX_FULL_Pos 23
2992 #define UART_FSR_TX_FULL_Msk (1ul << UART_FSR_TX_FULL_Pos)
2994 #define UART_FSR_TX_EMPTY_Pos 22
2995 #define UART_FSR_TX_EMPTY_Msk (1ul << UART_FSR_TX_EMPTY_Pos)
2997 #define UART_FSR_TX_POINTER_Pos 16
2998 #define UART_FSR_TX_POINTER_Msk (0x3Ful << UART_FSR_TX_POINTER_Pos)
3000 #define UART_FSR_RX_FULL_Pos 15
3001 #define UART_FSR_RX_FULL_Msk (1ul << UART_FSR_RX_FULL_Pos)
3003 #define UART_FSR_RX_EMPTY_Pos 14
3004 #define UART_FSR_RX_EMPTY_Msk (1ul << UART_FSR_RX_EMPTY_Pos)
3006 #define UART_FSR_RX_POINTER_Pos 8
3007 #define UART_FSR_RX_POINTER_Msk (0x3Ful << UART_FSR_RX_POINTER_Pos)
3009 #define UART_FSR_BIF_Pos 6
3010 #define UART_FSR_BIF_Msk (1ul << UART_FSR_BIF_Pos)
3012 #define UART_FSR_FEF_Pos 5
3013 #define UART_FSR_FEF_Msk (1ul << UART_FSR_FEF_Pos)
3015 #define UART_FSR_PEF_Pos 4
3016 #define UART_FSR_PEF_Msk (1ul << UART_FSR_PEF_Pos)
3018 #define UART_FSR_RS485_ADD_DETF_Pos 3
3019 #define UART_FSR_RS485_ADD_DETF_Msk (1ul << UART_FSR_RS485_ADD_DETF_Pos)
3021 #define UART_FSR_RX_OVER_IF_Pos 0
3022 #define UART_FSR_RX_OVER_IF_Msk (1ul << UART_FSR_RX_OVER_IF_Pos)
3024 /* UART ISR Bit Field Definitions */
3025 #define UART_ISR_BUF_ERR_INT_Pos 13
3026 #define UART_ISR_BUF_ERR_INT_Msk (1ul << UART_ISR_BUF_ERR_INT_Pos)
3028 #define UART_ISR_TOUT_INT_Pos 12
3029 #define UART_ISR_TOUT_INT_Msk (1ul << UART_ISR_TOUT_INT_Pos)
3031 #define UART_ISR_MODEM_INT_Pos 11
3032 #define UART_ISR_MODEM_INT_Msk (1ul << UART_ISR_MODEM_INT_Pos)
3034 #define UART_ISR_RLS_INT_Pos 10
3035 #define UART_ISR_RLS_INT_Msk (1ul << UART_ISR_RLS_INT_Pos)
3037 #define UART_ISR_THRE_INT_Pos 9
3038 #define UART_ISR_THRE_INT_Msk (1ul << UART_ISR_THRE_INT_Pos)
3040 #define UART_ISR_RDA_INT_Pos 8
3041 #define UART_ISR_RDA_INT_Msk (1ul << UART_ISR_RDA_INT_Pos)
3043 #define UART_ISR_BUF_ERR_IF_Pos 5
3044 #define UART_ISR_BUF_ERR_IF_Msk (1ul << UART_ISR_BUF_ERR_IF_Pos)
3046 #define UART_ISR_TOUT_IF_Pos 4
3047 #define UART_ISR_TOUT_IF_Msk (1ul << UART_ISR_TOUT_IF_Pos)
3049 #define UART_ISR_MODEM_IF_Pos 3
3050 #define UART_ISR_MODEM_IF_Msk (1ul << UART_ISR_MODEM_IF_Pos)
3052 #define UART_ISR_RLS_IF_Pos 2
3053 #define UART_ISR_RLS_IF_Msk (1ul << UART_ISR_RLS_IF_Pos)
3055 #define UART_ISR_THRE_IF_Pos 1
3056 #define UART_ISR_THRE_IF_Msk (1ul << UART_ISR_THRE_IF_Pos)
3058 #define UART_ISR_RDA_IF_Pos 0
3059 #define UART_ISR_RDA_IF_Msk (1ul << UART_ISR_RDA_IF_Pos)
3062 /* UART TOR Bit Field Definitions */
3063 #define UART_TOR_DLY_Pos 8
3064 #define UART_TOR_DLY_Msk (0xFFul << UART_TOR_DLY_Pos)
3066 #define UART_TOR_TOIC_Pos 0
3067 #define UART_TOR_TOIC_Msk (0xFFul << UART_TOR_TOIC_Pos)
3069 /* UART BAUD Bit Field Definitions */
3070 #define UART_BAUD_DIV_X_EN_Pos 29
3071 #define UART_BAUD_DIV_X_EN_Msk (1ul << UART_BAUD_DIV_X_EN_Pos)
3073 #define UART_BAUD_DIV_X_ONE_Pos 28
3074 #define UART_BAUD_DIV_X_ONE_Msk (1ul << UART_BAUD_DIV_X_ONE_Pos)
3076 #define UART_BAUD_DIVIDER_X_Pos 24
3077 #define UART_BAUD_DIVIDER_X_Msk (0xFul << UART_BAUD_DIVIDER_X_Pos)
3079 #define UART_BAUD_BRD_Pos 0
3080 #define UART_BAUD_BRD_Msk (0xFFFFul << UART_BAUD_BRD_Pos)
3082 /* UART IRCR Bit Field Definitions */
3083 #define UART_IRCR_INV_RX_Pos 6
3084 #define UART_IRCR_INV_RX_Msk (1ul << UART_IRCR_INV_RX_Pos)
3086 #define UART_IRCR_INV_TX_Pos 5
3087 #define UART_IRCR_INV_TX_Msk (1ul << UART_IRCR_INV_TX_Pos)
3089 #define UART_IRCR_TX_SELECT_Pos 1
3090 #define UART_IRCR_TX_SELECT_Msk (1ul << UART_IRCR_TX_SELECT_Pos)
3092 /* UART ALT_CSR Bit Field Definitions */
3093 #define UART_ALT_CSR_ADDR_MATCH_Pos 24
3094 #define UART_ALT_CSR_ADDR_MATCH_Msk (0xFFul << UART_ALT_CSR_ADDR_MATCH_Pos)
3096 #define UART_ALT_CSR_RS485_ADD_EN_Pos 15
3097 #define UART_ALT_CSR_RS485_ADD_EN_Msk (1ul << UART_ALT_CSR_RS485_ADD_EN_Pos)
3099 #define UART_ALT_CSR_RS485_AUD_Pos 10
3100 #define UART_ALT_CSR_RS485_AUD_Msk (1ul << UART_ALT_CSR_RS485_AUD_Pos)
3102 #define UART_ALT_CSR_RS485_AAD_Pos 9
3103 #define UART_ALT_CSR_RS485_AAD_Msk (1ul << UART_ALT_CSR_RS485_AAD_Pos)
3105 #define UART_ALT_CSR_RS485_NMM_Pos 8
3106 #define UART_ALT_CSR_RS485_NMM_Msk (1ul << UART_ALT_CSR_RS485_NMM_Pos)
3108 /* UART FUN_SEL Bit Field Definitions */
3109 #define UART_FUN_SEL_FUN_SEL_Pos 0
3110 #define UART_FUN_SEL_FUN_SEL_Msk (0x3ul << UART_FUN_SEL_FUN_SEL_Pos)
3112 /* end of group UART */
3114
3115 /*---------------------- Watchdog Timer Controller -------------------------*/
3116
3124 typedef struct
3125 {
3126 __IO uint32_t WTCR;
3127 } WDT_T;
3129 /* WDT WTCR Bit Field Definitions */
3130 #define WDT_WTCR_DBGACK_WDT_Pos 31
3131 #define WDT_WTCR_DBGACK_WDT_Msk (1ul << WDT_WTCR_DBGACK_WDT_Pos)
3133 #define WDT_WTCR_WTIS_Pos 8
3134 #define WDT_WTCR_WTIS_Msk (0x7ul << WDT_WTCR_WTIS_Pos)
3136 #define WDT_WTCR_WTE_Pos 7
3137 #define WDT_WTCR_WTE_Msk (1ul << WDT_WTCR_WTE_Pos)
3139 #define WDT_WTCR_WTIE_Pos 6
3140 #define WDT_WTCR_WTIE_Msk (1ul << WDT_WTCR_WTIE_Pos)
3142 #define WDT_WTCR_WTWKF_Pos 5
3143 #define WDT_WTCR_WTWKF_Msk (1ul << WDT_WTCR_WTWKF_Pos)
3145 #define WDT_WTCR_WTWKE_Pos 4
3146 #define WDT_WTCR_WTWKE_Msk (1ul << WDT_WTCR_WTWKE_Pos)
3148 #define WDT_WTCR_WTIF_Pos 3
3149 #define WDT_WTCR_WTIF_Msk (1ul << WDT_WTCR_WTIF_Pos)
3151 #define WDT_WTCR_WTRF_Pos 2
3152 #define WDT_WTCR_WTRF_Msk (1ul << WDT_WTCR_WTRF_Pos)
3154 #define WDT_WTCR_WTRE_Pos 1
3155 #define WDT_WTCR_WTRE_Msk (1ul << WDT_WTCR_WTRE_Pos)
3157 #define WDT_WTCR_WTR_Pos 0
3158 #define WDT_WTCR_WTR_Msk (1ul << WDT_WTCR_WTR_Pos)
3159 /* end of group WDT */
3161
3162
3163 #if defined ( __CC_ARM )
3164 #pragma no_anon_unions
3165 #endif
3166 /* end of group NUC029FAE_Peripherals */
3168
3173 /* Peripheral and SRAM base address */
3174 #define FLASH_BASE ((uint32_t)0x00000000)
3175 #define SRAM_BASE ((uint32_t)0x20000000)
3176 #define APB1PERIPH_BASE ((uint32_t)0x40000000)
3177 #define APB2PERIPH_BASE ((uint32_t)0x40100000)
3178 #define AHBPERIPH_BASE ((uint32_t)0x50000000)
3179
3180 /* Peripheral memory map */
3181 #define WDT_BASE (APB1PERIPH_BASE + 0x04000)
3182 #define TIMER0_BASE (APB1PERIPH_BASE + 0x10000)
3183 #define TIMER1_BASE (APB1PERIPH_BASE + 0x10020)
3184 #define I2C_BASE (APB1PERIPH_BASE + 0x20000)
3185 #define SPI_BASE (APB1PERIPH_BASE + 0x30000)
3186 #define PWM_BASE (APB1PERIPH_BASE + 0x40000)
3187 #define UART_BASE (APB1PERIPH_BASE + 0x50000)
3188 #define ACMP_BASE (APB1PERIPH_BASE + 0xD0000)
3189 #define ADC_BASE (APB1PERIPH_BASE + 0xE0000)
3190
3191 #define SYS_BASE (AHBPERIPH_BASE + 0x00000)
3192 #define CLK_BASE (AHBPERIPH_BASE + 0x00200)
3193 #define INT_BASE (AHBPERIPH_BASE + 0x00300)
3194 #define P0_BASE (AHBPERIPH_BASE + 0x04000)
3195 #define P1_BASE (AHBPERIPH_BASE + 0x04040)
3196 #define P2_BASE (AHBPERIPH_BASE + 0x04080)
3197 #define P3_BASE (AHBPERIPH_BASE + 0x040C0)
3198 #define P4_BASE (AHBPERIPH_BASE + 0x04100)
3199 #define P5_BASE (AHBPERIPH_BASE + 0x04140)
3200 #define GPIO_DBNCECON_BASE (AHBPERIPH_BASE + 0x04180)
3201 #define GPIO_PIN_DATA_BASE (AHBPERIPH_BASE + 0x04200)
3202 #define GPIOBIT0_BASE (AHBPERIPH_BASE + 0x04200)
3203 #define GPIOBIT1_BASE (AHBPERIPH_BASE + 0x04220)
3204 #define GPIOBIT2_BASE (AHBPERIPH_BASE + 0x04240)
3205 #define GPIOBIT3_BASE (AHBPERIPH_BASE + 0x04260)
3206 #define GPIOBIT4_BASE (AHBPERIPH_BASE + 0x04280)
3207 #define GPIOBIT5_BASE (AHBPERIPH_BASE + 0x042A0)
3208 #define FMC_BASE (AHBPERIPH_BASE + 0x0C000)
3209
3210 /* end of group NUC029FAE_PERIPHERAL_MEM_MAP */
3211
3212
3217 #define WDT ((WDT_T *) WDT_BASE)
3218 #define TIMER0 ((TIMER_T *) TIMER0_BASE)
3219 #define TIMER1 ((TIMER_T *) TIMER1_BASE)
3220 #define I2C ((I2C_T *) I2C_BASE)
3221 #define SPI ((SPI_T *) SPI_BASE)
3222 #define PWM ((PWM_T *) PWM_BASE)
3223 #define UART ((UART_T *) UART_BASE)
3224 #define ADC ((ADC_T *) ADC_BASE)
3225 #define ACMP ((ACMP_T *) ACMP_BASE)
3226
3227 #define SYS ((SYS_T *) SYS_BASE)
3228 #define CLK ((CLK_T *) CLK_BASE)
3229 #define INT ((INT_T *) INT_BASE)
3230 #define P0 ((GPIO_T *) P0_BASE)
3231 #define P1 ((GPIO_T *) P1_BASE)
3232 #define P2 ((GPIO_T *) P2_BASE)
3233 #define P3 ((GPIO_T *) P3_BASE)
3234 #define P4 ((GPIO_T *) P4_BASE)
3235 #define P5 ((GPIO_T *) P5_BASE)
3236 #define GPIO ((GPIO_DBNCECON_T *) GPIO_DBNCECON_BASE)
3237 #define GPIOBIT0 ((GPIOBIT_T *) GPIOBIT0_BASE)
3238 #define GPIOBIT1 ((GPIOBIT_T *) GPIOBIT1_BASE)
3239 #define GPIOBIT2 ((GPIOBIT_T *) GPIOBIT2_BASE)
3240 #define GPIOBIT3 ((GPIOBIT_T *) GPIOBIT3_BASE)
3241 #define GPIOBIT4 ((GPIOBIT_T *) GPIOBIT4_BASE)
3242 #define GPIOBIT5 ((GPIOBIT_T *) GPIOBIT5_BASE)
3243 #define FMC ((FMC_T *) FMC_BASE)
3244
3245 /* end of group NUC029FAE_PERIPHERAL_DECLARATION */
3246
3252 typedef volatile unsigned char vu8;
3253 typedef volatile unsigned short vu16;
3254 typedef volatile unsigned long vu32;
3255
3261 #define M8(addr) (*((vu8 *) (addr)))
3262
3269 #define M16(addr) (*((vu16 *) (addr)))
3270
3277 #define M32(addr) (*((vu32 *) (addr)))
3278
3286 #define outpw(port,value) *((volatile unsigned int *)(port)) = value
3287
3294 #define inpw(port) (*((volatile unsigned int *)(port)))
3295
3303 #define outps(port,value) *((volatile unsigned short *)(port)) = value
3304
3311 #define inps(port) (*((volatile unsigned short *)(port)))
3312
3319 #define outpb(port,value) *((volatile unsigned char *)(port)) = value
3320
3326 #define inpb(port) (*((volatile unsigned char *)(port)))
3327
3335 #define outp32(port,value) *((volatile unsigned int *)(port)) = value
3336
3343 #define inp32(port) (*((volatile unsigned int *)(port)))
3344
3352 #define outp16(port,value) *((volatile unsigned short *)(port)) = value
3353
3360 #define inp16(port) (*((volatile unsigned short *)(port)))
3361
3368 #define outp8(port,value) *((volatile unsigned char *)(port)) = value
3369
3375 #define inp8(port) (*((volatile unsigned char *)(port)))
3376
3377 /* end of group NUC029FAE_IO_ROUTINE */
3379
3380 /******************************************************************************/
3381 /* Legacy Constants */
3382 /******************************************************************************/
3388 #ifndef NULL
3389 #define NULL (0)
3390 #endif
3391
3392 #define TRUE (1)
3393 #define FALSE (0)
3394
3395 #define ENABLE (1)
3396 #define DISABLE (0)
3397
3398 /* Define one bit mask */
3399 #define BIT0 (0x00000001)
3400 #define BIT1 (0x00000002)
3401 #define BIT2 (0x00000004)
3402 #define BIT3 (0x00000008)
3403 #define BIT4 (0x00000010)
3404 #define BIT5 (0x00000020)
3405 #define BIT6 (0x00000040)
3406 #define BIT7 (0x00000080)
3407 #define BIT8 (0x00000100)
3408 #define BIT9 (0x00000200)
3409 #define BIT10 (0x00000400)
3410 #define BIT11 (0x00000800)
3411 #define BIT12 (0x00001000)
3412 #define BIT13 (0x00002000)
3413 #define BIT14 (0x00004000)
3414 #define BIT15 (0x00008000)
3415 #define BIT16 (0x00010000)
3416 #define BIT17 (0x00020000)
3417 #define BIT18 (0x00040000)
3418 #define BIT19 (0x00080000)
3419 #define BIT20 (0x00100000)
3420 #define BIT21 (0x00200000)
3421 #define BIT22 (0x00400000)
3422 #define BIT23 (0x00800000)
3423 #define BIT24 (0x01000000)
3424 #define BIT25 (0x02000000)
3425 #define BIT26 (0x04000000)
3426 #define BIT27 (0x08000000)
3427 #define BIT28 (0x10000000)
3428 #define BIT29 (0x20000000)
3429 #define BIT30 (0x40000000)
3430 #define BIT31 (0x80000000)
3431
3432 /* Byte Mask Definitions */
3433 #define BYTE0_Msk (0x000000FF)
3434 #define BYTE1_Msk (0x0000FF00)
3435 #define BYTE2_Msk (0x00FF0000)
3436 #define BYTE3_Msk (0xFF000000)
3437
3438 #define GET_BYTE0(u32Param) ((u32Param & BYTE0_Msk) )
3439 #define GET_BYTE1(u32Param) ((u32Param & BYTE1_Msk) >> 8)
3440 #define GET_BYTE2(u32Param) ((u32Param & BYTE2_Msk) >> 16)
3441 #define GET_BYTE3(u32Param) ((u32Param & BYTE3_Msk) >> 24)
3443 /* end of group NUC029FAE_legacy_Constants */
3444
3445 #ifdef __cplusplus
3446 }
3447 #endif
3448
3449
3450 /******************************************************************************/
3451 /* Peripheral header files */
3452 /******************************************************************************/
3453 #include "sys.h"
3454 #include "clk.h"
3455 #include "acmp.h"
3456 #include "adc.h"
3457 #include "fmc.h"
3458 #include "gpio.h"
3459 #include "i2c.h"
3460 #include "pwm.h"
3461 #include "spi.h"
3462 #include "timer.h"
3463 #include "uart.h"
3464 #include "wdt.h"
3465
3466 #endif // __NUC029FAE_H__
3467
SVCall_IRQn
Definition: NUC029FAE.h:79
SPI_T::DIVIDER
__IO uint32_t DIVIDER
Definition: NUC029FAE.h:1824
UART_T::LCR
__IO uint32_t LCR
Definition: NUC029FAE.h:2876
UART_T::TOR
__IO uint32_t TOR
Definition: NUC029FAE.h:2881
SYS_T::IRCTRIMCTL
__IO uint32_t IRCTRIMCTL
Definition: NUC029FAE.h:2501
I2C_T::I2CON2
__IO uint32_t I2CON2
Definition: NUC029FAE.h:1057
HIRC_IRQn
Definition: NUC029FAE.h:98
PWM_T::TRGSTS1
__IO uint32_t TRGSTS1
Definition: NUC029FAE.h:1187
I2C_T::RESERVED1
uint32_t RESERVED1
Definition: NUC029FAE.h:1056
uart.h
NUC029FAE UART driver header file.
SPI_T::CNTRL2
__IO uint32_t CNTRL2
Definition: NUC029FAE.h:1831
GPIO_T
Definition: NUC029FAE.h:928
UART_T::FUN_SEL
__IO uint32_t FUN_SEL
Definition: NUC029FAE.h:2885
pwm.h
NUC029FAE PWM driver header file.
CLK_T::CLKSTATUS
__IO uint32_t CLKSTATUS
Definition: NUC029FAE.h:342
TIMER_T::TISR
__IO uint32_t TISR
Definition: NUC029FAE.h:2763
IRQn
IRQn
Definition: NUC029FAE.h:73
CLK_T::CLKSEL2
__IO uint32_t CLKSEL2
Definition: NUC029FAE.h:451
acmp.h
NUC029FAE Analog Comparator(ACMP) driver header file.
TIMER_T::TEXISR
__IO uint32_t TEXISR
Definition: NUC029FAE.h:2767
SYS_T::P2_MFP
__IO uint32_t P2_MFP
Definition: NUC029FAE.h:2323
CLK_T::PWRCON
__IO uint32_t PWRCON
Definition: NUC029FAE.h:257
I2C_T::I2CADDR2
__IO uint32_t I2CADDR2
Definition: NUC029FAE.h:1049
PWM_T::CSR
__IO uint32_t CSR
Definition: NUC029FAE.h:1174
FB_IRQn
Definition: NUC029FAE.h:92
PWM_T::PIIR
__IO uint32_t PIIR
Definition: NUC029FAE.h:1180
FMC_T::ISPCMD
__IO uint32_t ISPCMD
Definition: NUC029FAE.h:849
PWM_T::PHCHGMASK
__IO uint32_t PHCHGMASK
Definition: NUC029FAE.h:1190
UART_T::MSR
__IO uint32_t MSR
Definition: NUC029FAE.h:2878
SPI_T::SSR
__IO uint32_t SSR
Definition: NUC029FAE.h:1825
FMC_T::ISPDAT
__IO uint32_t ISPDAT
Definition: NUC029FAE.h:830
SPI_T::RESERVED0
uint32_t RESERVED0
Definition: NUC029FAE.h:1826
GPIO_T::DMASK
__IO uint32_t DMASK
Definition: NUC029FAE.h:933
FMC_T::DFBADR
__I uint32_t DFBADR
Definition: NUC029FAE.h:881
GPIOBIT_T::GP_BIT5
__IO uint32_t GP_BIT5
Definition: NUC029FAE.h:1025
UART_T::ALT_CSR
__IO uint32_t ALT_CSR
Definition: NUC029FAE.h:2884
GPIOBIT_T
Definition: NUC029FAE.h:1018
WDT_IRQn
Definition: NUC029FAE.h:86
gpio.h
NUC029FAE GPIO driver header file.
I2C_T::I2CLK
__IO uint32_t I2CLK
Definition: NUC029FAE.h:1046
GPIO_T::DBEN
__IO uint32_t DBEN
Definition: NUC029FAE.h:935
CLK_T::APBCLK
__IO uint32_t APBCLK
Definition: NUC029FAE.h:319
system_NUC029FAE.h
NUC029FAE system clock definition file.
I2C_T
Definition: NUC029FAE.h:1040
UART_T::FSR
__IO uint32_t FSR
Definition: NUC029FAE.h:2879
PWM_T::TRGSTS0
__IO uint32_t TRGSTS0
Definition: NUC029FAE.h:1186
INT_T
Definition: NUC029FAE.h:1155
GPIOBIT_T::GP_BIT7
__IO uint32_t GP_BIT7
Definition: NUC029FAE.h:1027
UART_T::IER
__IO uint32_t IER
Definition: NUC029FAE.h:2874
TIMER_T::TEXCON
__IO uint32_t TEXCON
Definition: NUC029FAE.h:2766
sys.h
NUC029FAE SYS driver header file.
INT_T::MCUIRQ
__IO uint32_t MCUIRQ
Definition: NUC029FAE.h:1159
SYS_T::P0_MFP
__IO uint32_t P0_MFP
Definition: NUC029FAE.h:2221
GPIOBIT_T::GP_BIT0
__IO uint32_t GP_BIT0
Definition: NUC029FAE.h:1020
CLK_T
Definition: NUC029FAE.h:203
SPI_T::STATUS
__IO uint32_t STATUS
Definition: NUC029FAE.h:1833
FMC_T::ISPADR
__IO uint32_t ISPADR
Definition: NUC029FAE.h:817
TIMER_T::TDR
__I uint32_t TDR
Definition: NUC029FAE.h:2764
I2C_T::I2CADM3
__IO uint32_t I2CADM3
Definition: NUC029FAE.h:1054
UART_T::RBR
__I uint32_t RBR
Definition: NUC029FAE.h:2871
vu8
volatile unsigned char vu8
Define 8-bit unsigned volatile data type.
Definition: NUC029FAE.h:3252
GPIO_T::OFFD
__IO uint32_t OFFD
Definition: NUC029FAE.h:931
IRQn_Type
enum IRQn IRQn_Type
ADC_T::ADSR
__IO uint32_t ADSR
Definition: NUC029FAE.h:649
UART_T::ISR
__IO uint32_t ISR
Definition: NUC029FAE.h:2880
SYS_T::PDID
__I uint32_t PDID
Definition: NUC029FAE.h:2008
SYS_T::P1_MFP
__IO uint32_t P1_MFP
Definition: NUC029FAE.h:2272
I2C_T::I2CDAT
__IO uint32_t I2CDAT
Definition: NUC029FAE.h:1044
I2C_T::I2CON
__IO uint32_t I2CON
Definition: NUC029FAE.h:1042
ACMP_T::CMPSR
__IO uint32_t CMPSR
Definition: NUC029FAE.h:149
timer.h
NUC029FAE TIMER driver header file.
adc.h
NUC029FAE ADC driver header file.
SPI_T::CNTRL
__IO uint32_t CNTRL
Definition: NUC029FAE.h:1823
PWM_T::INTACCUCTL
__IO uint32_t INTACCUCTL
Definition: NUC029FAE.h:1191
SPI_T
Definition: NUC029FAE.h:1821
wdt.h
NUC029FAE WDT driver header file.
ADC_IRQn
Definition: NUC029FAE.h:102
PWM_T::PHCHG
__IO uint32_t PHCHG
Definition: NUC029FAE.h:1188
GPIO_T::ISRC
__IO uint32_t ISRC
Definition: NUC029FAE.h:938
SYS_T::P4_MFP
__IO uint32_t P4_MFP
Definition: NUC029FAE.h:2412
spi.h
NUC029FAE SPI driver header file.
GPIO234_IRQn
Definition: NUC029FAE.h:90
SYS_T
Definition: NUC029FAE.h:1996
GPIO_DBNCECON_T
Definition: NUC029FAE.h:942
PWM_T::TRGCON1
__IO uint32_t TRGCON1
Definition: NUC029FAE.h:1185
SYS_T::RSTSRC
__IO uint32_t RSTSRC
Definition: NUC029FAE.h:2045
SYS_T::IPRSTC2
__IO uint32_t IPRSTC2
Definition: NUC029FAE.h:2110
I2C_T::I2CADDR1
__IO uint32_t I2CADDR1
Definition: NUC029FAE.h:1048
I2C_T::RESERVED0
uint32_t RESERVED0
Definition: NUC029FAE.h:1055
SYS_T::IRCTRIMISR
__IO uint32_t IRCTRIMISR
Definition: NUC029FAE.h:2552
WDT_T
WDT register map.
Definition: NUC029FAE.h:3124
FMC_T::ISPCON
__IO uint32_t ISPCON
Definition: NUC029FAE.h:804
GPIO_T::IMD
__IO uint32_t IMD
Definition: NUC029FAE.h:936
ADC_T::ADCR
__IO uint32_t ADCR
Definition: NUC029FAE.h:646
ACMP_T
Definition: NUC029FAE.h:146
TIMER_T::TCMPR
__IO uint32_t TCMPR
Definition: NUC029FAE.h:2762
vu16
volatile unsigned short vu16
Define 16-bit unsigned volatile data type.
Definition: NUC029FAE.h:3253
fmc.h
NUC029FAE FMC driver header file.
SYS_T::P5_MFP
__IO uint32_t P5_MFP
Definition: NUC029FAE.h:2464
SPI_IRQn
Definition: NUC029FAE.h:96
FMC_T::ISPTRG
__IO uint32_t ISPTRG
Definition: NUC029FAE.h:864
clk.h
NUC029FAE CLK driver header file.
GPIO_T::PMD
__IO uint32_t PMD
Definition: NUC029FAE.h:930
EINT0_IRQn
Definition: NUC029FAE.h:87
ADC_T::ADCHER
__IO uint32_t ADCHER
Definition: NUC029FAE.h:647
GPIO01_IRQn
Definition: NUC029FAE.h:89
ADC_T::ADSAMP
__IO uint32_t ADSAMP
Definition: NUC029FAE.h:651
ACMP_T::CMPRVCR
__IO uint32_t CMPRVCR
Definition: NUC029FAE.h:150
GPIO_T::DOUT
__IO uint32_t DOUT
Definition: NUC029FAE.h:932
CLK_T::RESERVED0
uint32_t RESERVED0
Definition: NUC029FAE.h:455
PWM_T::PFBCON
__IO uint32_t PFBCON
Definition: NUC029FAE.h:1182
ACMP_IRQn
Definition: NUC029FAE.h:100
PWM_T::PPR
__IO uint32_t PPR
Definition: NUC029FAE.h:1173
vu32
volatile unsigned long vu32
Define 32-bit unsigned volatile data type.
Definition: NUC029FAE.h:3254
SYS_T::BODCTL
__IO uint32_t BODCTL
Definition: NUC029FAE.h:2156
I2C_T::I2CADM0
__IO uint32_t I2CADM0
Definition: NUC029FAE.h:1051
I2C_IRQn
Definition: NUC029FAE.h:99
BOD_IRQn
Definition: NUC029FAE.h:85
ADC_T
Definition: NUC029FAE.h:642
GPIOBIT_T::GP_BIT2
__IO uint32_t GP_BIT2
Definition: NUC029FAE.h:1022
I2C_T::I2CSTATUS
__IO uint32_t I2CSTATUS
Definition: NUC029FAE.h:1045
PWM_T::TRGCON0
__IO uint32_t TRGCON0
Definition: NUC029FAE.h:1184
PendSV_IRQn
Definition: NUC029FAE.h:80
SPI_T::FIFO_CTL
__IO uint32_t FIFO_CTL
Definition: NUC029FAE.h:1832
SysTick_IRQn
Definition: NUC029FAE.h:81
GPIOBIT_T::GP_BIT4
__IO uint32_t GP_BIT4
Definition: NUC029FAE.h:1024
NonMaskableInt_IRQn
Definition: NUC029FAE.h:77
PWM_T::PDZIR
__IO uint32_t PDZIR
Definition: NUC029FAE.h:1183
GPIO_DBNCECON_T::DBNCECON
__IO uint32_t DBNCECON
Definition: NUC029FAE.h:944
ADC_T::ADDR
__IO uint32_t ADDR
Definition: NUC029FAE.h:644
TIMER_T::TCAP
__I uint32_t TCAP
Definition: NUC029FAE.h:2765
GPIOBIT_T::GP_BIT3
__IO uint32_t GP_BIT3
Definition: NUC029FAE.h:1023
FMC_T
Definition: NUC029FAE.h:748
CLK_T::CLKSEL0
__IO uint32_t CLKSEL0
Definition: NUC029FAE.h:373
UART_T::FCR
__IO uint32_t FCR
Definition: NUC029FAE.h:2875
WDT_T::WTCR
__IO uint32_t WTCR
Definition: NUC029FAE.h:3126
GPIO_T::IEN
__IO uint32_t IEN
Definition: NUC029FAE.h:937
TIMER_T
Definition: NUC029FAE.h:2759
SPI_T::RX
__I uint32_t RX
Definition: NUC029FAE.h:1827
SPI_T::TX
__O uint32_t TX
Definition: NUC029FAE.h:1829
ADC_T::ADTDCR
__IO uint32_t ADTDCR
Definition: NUC029FAE.h:650
I2C_T::I2CADDR0
__IO uint32_t I2CADDR0
Definition: NUC029FAE.h:1043
TMR0_IRQn
Definition: NUC029FAE.h:93
I2C_T::I2CSTATUS2
__IO uint32_t I2CSTATUS2
Definition: NUC029FAE.h:1058
SYS_T::P3_MFP
__IO uint32_t P3_MFP
Definition: NUC029FAE.h:2384
CLK_T::CLKSEL1
__IO uint32_t CLKSEL1
Definition: NUC029FAE.h:417
SYS_T::RegLockAddr
__IO uint32_t RegLockAddr
Definition: NUC029FAE.h:2585
SYS_T::IRCTRIMIER
__IO uint32_t IRCTRIMIER
Definition: NUC029FAE.h:2525
PDWU_IRQn
Definition: NUC029FAE.h:101
HardFault_IRQn
Definition: NUC029FAE.h:78
GPIO5_IRQn
Definition: NUC029FAE.h:97
PWM_T::PCR
__IO uint32_t PCR
Definition: NUC029FAE.h:1175
I2C_T::I2CADM1
__IO uint32_t I2CADM1
Definition: NUC029FAE.h:1052
I2C_T::I2CTOC
__IO uint32_t I2CTOC
Definition: NUC029FAE.h:1047
UART_T
Definition: NUC029FAE.h:2867
UART_T::IRCR
__IO uint32_t IRCR
Definition: NUC029FAE.h:2883
TMR1_IRQn
Definition: NUC029FAE.h:94
PWM_T::PIER
__IO uint32_t PIER
Definition: NUC029FAE.h:1179
I2C_T::I2CADDR3
__IO uint32_t I2CADDR3
Definition: NUC029FAE.h:1050
UART_T::MCR
__IO uint32_t MCR
Definition: NUC029FAE.h:2877
CLK_T::AHBCLK
__IO uint32_t AHBCLK
Definition: NUC029FAE.h:270
UART_T::THR
__O uint32_t THR
Definition: NUC029FAE.h:2872
CLK_T::FRQDIV
__IO uint32_t FRQDIV
Definition: NUC029FAE.h:473
INT_T::NMICNO
__IO uint32_t NMICNO
Definition: NUC029FAE.h:1158
GPIOBIT_T::GP_BIT1
__IO uint32_t GP_BIT1
Definition: NUC029FAE.h:1021
UART_IRQn
Definition: NUC029FAE.h:95
GPIOBIT_T::GP_BIT6
__IO uint32_t GP_BIT6
Definition: NUC029FAE.h:1026
SYS_T::IPRSTC1
__IO uint32_t IPRSTC1
Definition: NUC029FAE.h:2073
TIMER_T::TCSR
__IO uint32_t TCSR
Definition: NUC029FAE.h:2761
CLK_T::CLKDIV
__IO uint32_t CLKDIV
Definition: NUC029FAE.h:433
GPIO_T::PIN
__I uint32_t PIN
Definition: NUC029FAE.h:934
PWM_IRQn
Definition: NUC029FAE.h:91
UART_T::BAUD
__IO uint32_t BAUD
Definition: NUC029FAE.h:2882
PWM_T::POE
__IO uint32_t POE
Definition: NUC029FAE.h:1181
I2C_T::I2CADM2
__IO uint32_t I2CADM2
Definition: NUC029FAE.h:1053
EINT1_IRQn
Definition: NUC029FAE.h:88
PWM_T::PHCHGNXT
__IO uint32_t PHCHGNXT
Definition: NUC029FAE.h:1189
i2c.h
NUC029FAE I2C driver header file.
PWM_T
Definition: NUC029FAE.h:1171