| NUC029FAE BSP V3.01.002 The Board Support Package for NUC029FAE

Macros
CLK Exported Constants
NUC029FAE Device Driver » CLK Driver

## Macros
#define | CLK_PWRCON_XTL12M 0x01UL
#define | CLK_PWRCON_HXT 0x01UL
#define | CLK_PWRCON_XTL32K 0x02UL
#define | CLK_PWRCON_LXT 0x02UL
#define | CLK_CLKSEL0_HCLK_S_XTAL 0x00UL
#define | CLK_CLKSEL0_HCLK_S_IRC10K 0x03UL
#define | CLK_CLKSEL0_HCLK_S_LIRC 0x03UL
#define | CLK_CLKSEL0_HCLK_S_IRC22M 0x07UL
#define | CLK_CLKSEL0_HCLK_S_HIRC 0x07UL
#define | CLK_CLKSEL0_STCLK_S_XTAL 0x00UL
#define | CLK_CLKSEL0_STCLK_S_XTAL_DIV2 0x10UL
#define | CLK_CLKSEL0_STCLK_S_HCLK_DIV2 0x18UL
#define | CLK_CLKSEL0_STCLK_S_IRC22M_DIV2 0x38UL
#define | CLK_CLKSEL0_STCLK_S_HIRC_DIV2 0x38UL
#define | CLK_CLKSEL1_WDT_S_XTAL 0x00000000UL
#define | CLK_CLKSEL1_WDT_S_HCLK_DIV2048 0x00000002UL
#define | CLK_CLKSEL1_WDT_S_IRC10K 0x00000003UL
#define | CLK_CLKSEL1_WDT_S_LIRC 0x00000003UL
#define | CLK_CLKSEL1_ADC_S_XTAL 0x00000000UL
#define | CLK_CLKSEL1_ADC_S_HCLK 0x00000008UL
#define | CLK_CLKSEL1_ADC_S_IRC22M 0x0000000CUL
#define | CLK_CLKSEL1_ADC_S_HIRC 0x0000000CUL
#define | CLK_CLKSEL1_SPI_S_HXTorLXT 0x00000000UL
#define | CLK_CLKSEL1_SPI_S_HCLK 0x00000010UL
#define | CLK_CLKSEL1_TMR0_S_XTAL 0x00000000UL
#define | CLK_CLKSEL1_TMR0_S_IRC10K 0x00000100UL
#define | CLK_CLKSEL1_TMR0_S_LIRC 0x00000100UL
#define | CLK_CLKSEL1_TMR0_S_HCLK 0x00000200UL
#define | CLK_CLKSEL1_TMR0_S_IRC22M 0x00000700UL
#define | CLK_CLKSEL1_TMR0_S_HIRC 0x00000700UL
#define | CLK_CLKSEL1_TMR1_S_XTAL 0x00000000UL
#define | CLK_CLKSEL1_TMR1_S_IRC10K 0x00001000UL
#define | CLK_CLKSEL1_TMR1_S_LIRC 0x00001000UL
#define | CLK_CLKSEL1_TMR1_S_HCLK 0x00002000UL
#define | CLK_CLKSEL1_TMR1_S_IRC22M 0x00007000UL
#define | CLK_CLKSEL1_TMR1_S_HIRC 0x00007000UL
#define | CLK_CLKSEL1_UART_S_XTAL 0x00000000UL
#define | CLK_CLKSEL1_UART_S_IRC22M 0x02000000UL
#define | CLK_CLKSEL1_UART_S_HIRC 0x02000000UL
#define | CLK_CLKSEL1_PWM01_S_HCLK 0x20000000UL
#define | CLK_CLKSEL1_PWM23_S_HCLK 0x80000000UL
#define | CLK_CLKSEL2_FRQDIV_XTAL 0x00000000UL
#define | CLK_CLKSEL2_FRQDIV_HXT 0x00000000UL
#define | CLK_CLKSEL2_FRQDIV_LXT 0x00000000UL
#define | CLK_CLKSEL2_FRQDIV_HCLK 0x00000008UL
#define | CLK_CLKSEL2_FRQDIV_IRC22M 0x0000000CUL
#define | CLK_CLKSEL2_FRQDIV_HIRC 0x0000000CUL
#define | CLK_CLKSEL2_PWM45_S_HCLK 0x00000020UL
#define | CLK_CLKDIV_ADC(x) (((x)-1) << 16)
#define | CLK_CLKDIV_UART(x) (((x)-1) << 8)
#define | CLK_CLKDIV_HCLK(x) ((x)-1)
#define | MODULE_APBCLK(x) ((x >>31) & 0x1)
#define | MODULE_CLKSEL(x) ((x >>29) & 0x3)
#define | MODULE_CLKSEL_Msk(x) ((x >>25) & 0xf)
#define | MODULE_CLKSEL_Pos(x) ((x >>20) & 0x1f)
#define | MODULE_CLKDIV(x) ((x >>18) & 0x3)
#define | MODULE_CLKDIV_Msk(x) ((x >>10) & 0xff)
#define | MODULE_CLKDIV_Pos(x) ((x >>5 ) & 0x1f)
#define | MODULE_IP_EN_Pos(x) ((x >>0 ) & 0x1f)
#define | MODULE_NoMsk 0x0
#define | WDT_MODULE ((0x0<<31)|(0x1<<29)|(0x3<<25)|( 0<<20)|(0x3<<18)|(MODULE_NoMsk<<10)|(31<<5)|CLK_APBCLK_WDT_EN_Pos )
#define | TMR0_MODULE ((0x0<<31)|(0x1<<29)|(0x7<<25)|( 8<<20)|(0x3<<18)|(MODULE_NoMsk<<10)|(31<<5)|CLK_APBCLK_TMR0_EN_Pos)
#define | TMR1_MODULE ((0x0<<31)|(0x1<<29)|(0x7<<25)|(12<<20)|(0x3<<18)|(MODULE_NoMsk<<10)|(31<<5)|CLK_APBCLK_TMR1_EN_Pos)
#define | FDIV_MODULE ((0x0<<31)|(0x3<<29)|(0x3<<25)|( 2<<20)|(0x3<<18)|(MODULE_NoMsk<<10)|(31<<5)|CLK_APBCLK_FDIV_EN_Pos)
#define | I2C_MODULE ((0x0<<31)|(0x3<<29)|(MODULE_NoMsk<<25)|(31<<20)|(0x3<<18)|(MODULE_NoMsk<<10)|(31<<5)|CLK_APBCLK_I2C_EN_Pos)
#define | SPI_MODULE ((0x0<<31)|(0x1<<29)|(0x1<<25)|( 4<<20)|(0x3<<18)|(MODULE_NoMsk<<10)|(31<<5)|CLK_APBCLK_SPI_EN_Pos)
#define | UART_MODULE ((0x0<<31)|(0x1<<29)|(0x3<<25)|(24<<20)|(0x0<<18)|(0x0F<<10)|( 8<<5)|CLK_APBCLK_UART_EN_Pos)
#define | PWM01_MODULE ((0x0<<31)|(0x1<<29)|(0x3<<25)|(28<<20)|(0x3<<18)|(MODULE_NoMsk<<10)|(31<<5)|CLK_APBCLK_PWM01_EN_Pos)
#define | PWM23_MODULE ((0x0<<31)|(0x1<<29)|(0x3<<25)|(30<<20)|(0x3<<18)|(MODULE_NoMsk<<10)|(31<<5)|CLK_APBCLK_PWM23_EN_Pos)
#define | PWM45_MODULE ((0x0<<31)|(0x3<<29)|(0x3<<25)|( 4<<20)|(0x3<<18)|(MODULE_NoMsk<<10)|(31<<5)|CLK_APBCLK_PWM45_EN_Pos)
#define | ADC_MODULE ((0x0<<31)|(0x1<<29)|(0x3<<25)|( 2<<20)|(0x0<<18)|(0xFF<<10)|(16<<5)|CLK_APBCLK_ADC_EN_Pos)
#define | ACMP_MODULE ((0x0<<31)|(0x3<<29)|(MODULE_NoMsk<<25)|(31<<20)|(0x3<<18)|(MODULE_NoMsk<<10)|(31<<5)|CLK_APBCLK_ACMP_EN_Pos)

## Detailed Description

## Macro Definition Documentation

## ◆ ACMP_MODULE

#define ACMP_MODULE ((0x0<<31)|(0x3<<29)|(MODULE_NoMsk<<25)|(31<<20)|(0x3<<18)|(MODULE_NoMsk<<10)|(31<<5)|CLK_APBCLK_ACMP_EN_Pos)

ACMP Module

Definition at line 135 of file clk.h.

## ◆ ADC_MODULE

#define ADC_MODULE ((0x0<<31)|(0x1<<29)|(0x3<<25)|( 2<<20)|(0x0<<18)|(0xFF<<10)|(16<<5)|CLK_APBCLK_ADC_EN_Pos)

ADC Module

Definition at line 134 of file clk.h.

## ◆ CLK_CLKDIV_ADC

#define CLK_CLKDIV_ADC | ( |  | x | ) | (((x)-1) << 16)

CLKDIV Setting for ADC clock divider. It could be 1~256

Definition at line 105 of file clk.h.

## ◆ CLK_CLKDIV_HCLK

#define CLK_CLKDIV_HCLK | ( |  | x | ) | ((x)-1)

CLKDIV Setting for HCLK clock divider. It could be 1~16

Definition at line 107 of file clk.h.

## ◆ CLK_CLKDIV_UART

#define CLK_CLKDIV_UART | ( |  | x | ) | (((x)-1) << 8)

CLKDIV Setting for UART clock divider. It could be 1~16

Definition at line 106 of file clk.h.

## ◆ CLK_CLKSEL0_HCLK_S_HIRC

#define CLK_CLKSEL0_HCLK_S_HIRC 0x07UL

Setting clock source as internal 22.1184MHz RC clock

Definition at line 50 of file clk.h.

## ◆ CLK_CLKSEL0_HCLK_S_IRC10K

#define CLK_CLKSEL0_HCLK_S_IRC10K 0x03UL

Setting clock source as internal 10KHz RC clock

Definition at line 47 of file clk.h.

## ◆ CLK_CLKSEL0_HCLK_S_IRC22M

#define CLK_CLKSEL0_HCLK_S_IRC22M 0x07UL

Setting clock source as internal 22.1184MHz RC clock

Definition at line 49 of file clk.h.

## ◆ CLK_CLKSEL0_HCLK_S_LIRC

#define CLK_CLKSEL0_HCLK_S_LIRC 0x03UL

Setting clock source as internal 10KHz RC clock

Definition at line 48 of file clk.h.

## ◆ CLK_CLKSEL0_HCLK_S_XTAL

#define CLK_CLKSEL0_HCLK_S_XTAL 0x00UL

Setting clock source as external XTAL

Definition at line 46 of file clk.h.

## ◆ CLK_CLKSEL0_STCLK_S_HCLK_DIV2

#define CLK_CLKSEL0_STCLK_S_HCLK_DIV2 0x18UL

Setting clock source as HCLK/2

Definition at line 53 of file clk.h.

## ◆ CLK_CLKSEL0_STCLK_S_HIRC_DIV2

#define CLK_CLKSEL0_STCLK_S_HIRC_DIV2 0x38UL

Setting clock source as internal 22.1184MHz RC clock/2

Definition at line 55 of file clk.h.

## ◆ CLK_CLKSEL0_STCLK_S_IRC22M_DIV2

#define CLK_CLKSEL0_STCLK_S_IRC22M_DIV2 0x38UL

Setting clock source as internal 22.1184MHz RC clock/2

Definition at line 54 of file clk.h.

## ◆ CLK_CLKSEL0_STCLK_S_XTAL

#define CLK_CLKSEL0_STCLK_S_XTAL 0x00UL

Setting clock source as external XTAL

Definition at line 51 of file clk.h.

## ◆ CLK_CLKSEL0_STCLK_S_XTAL_DIV2

#define CLK_CLKSEL0_STCLK_S_XTAL_DIV2 0x10UL

Setting clock source as external XTAL/2

Definition at line 52 of file clk.h.

## ◆ CLK_CLKSEL1_ADC_S_HCLK

#define CLK_CLKSEL1_ADC_S_HCLK 0x00000008UL

Setting ADC clock source as HCLK

Definition at line 66 of file clk.h.

## ◆ CLK_CLKSEL1_ADC_S_HIRC

#define CLK_CLKSEL1_ADC_S_HIRC 0x0000000CUL

Setting ADC clock source as internal 22.1184MHz RC clock

Definition at line 68 of file clk.h.

## ◆ CLK_CLKSEL1_ADC_S_IRC22M

#define CLK_CLKSEL1_ADC_S_IRC22M 0x0000000CUL

Setting ADC clock source as internal 22.1184MHz RC clock

Definition at line 67 of file clk.h.

## ◆ CLK_CLKSEL1_ADC_S_XTAL

#define CLK_CLKSEL1_ADC_S_XTAL 0x00000000UL

Setting ADC clock source as external XTAL

Definition at line 65 of file clk.h.

## ◆ CLK_CLKSEL1_PWM01_S_HCLK

#define CLK_CLKSEL1_PWM01_S_HCLK 0x20000000UL

Setting PWM01 clock source as external HCLK

Definition at line 86 of file clk.h.

## ◆ CLK_CLKSEL1_PWM23_S_HCLK

#define CLK_CLKSEL1_PWM23_S_HCLK 0x80000000UL

Setting PWM23 clock source as external HCLK

Definition at line 87 of file clk.h.

## ◆ CLK_CLKSEL1_SPI_S_HCLK

#define CLK_CLKSEL1_SPI_S_HCLK 0x00000010UL

Setting SPI clock source as HCLK

Definition at line 70 of file clk.h.

## ◆ CLK_CLKSEL1_SPI_S_HXTorLXT

#define CLK_CLKSEL1_SPI_S_HXTorLXT 0x00000000UL

Setting SPI clock source as HXT or LXT

Definition at line 69 of file clk.h.

## ◆ CLK_CLKSEL1_TMR0_S_HCLK

#define CLK_CLKSEL1_TMR0_S_HCLK 0x00000200UL

Setting Timer 0 clock source as HCLK

Definition at line 74 of file clk.h.

## ◆ CLK_CLKSEL1_TMR0_S_HIRC

#define CLK_CLKSEL1_TMR0_S_HIRC 0x00000700UL

Setting Timer 0 clock source as internal 22.1184MHz RC clock

Definition at line 76 of file clk.h.

## ◆ CLK_CLKSEL1_TMR0_S_IRC10K

#define CLK_CLKSEL1_TMR0_S_IRC10K 0x00000100UL

Setting Timer 0 clock source as internal 10KHz RC clock

Definition at line 72 of file clk.h.

## ◆ CLK_CLKSEL1_TMR0_S_IRC22M

#define CLK_CLKSEL1_TMR0_S_IRC22M 0x00000700UL

Setting Timer 0 clock source as internal 22.1184MHz RC clock

Definition at line 75 of file clk.h.

## ◆ CLK_CLKSEL1_TMR0_S_LIRC

#define CLK_CLKSEL1_TMR0_S_LIRC 0x00000100UL

Setting Timer 0 clock source as internal 10KHz RC clock

Definition at line 73 of file clk.h.

## ◆ CLK_CLKSEL1_TMR0_S_XTAL

#define CLK_CLKSEL1_TMR0_S_XTAL 0x00000000UL

Setting Timer 0 clock source as external XTAL

Definition at line 71 of file clk.h.

## ◆ CLK_CLKSEL1_TMR1_S_HCLK

#define CLK_CLKSEL1_TMR1_S_HCLK 0x00002000UL

Setting Timer 1 clock source as HCLK

Definition at line 80 of file clk.h.

## ◆ CLK_CLKSEL1_TMR1_S_HIRC

#define CLK_CLKSEL1_TMR1_S_HIRC 0x00007000UL

Setting Timer 1 clock source as internal 22.1184MHz RC clock

Definition at line 82 of file clk.h.

## ◆ CLK_CLKSEL1_TMR1_S_IRC10K

#define CLK_CLKSEL1_TMR1_S_IRC10K 0x00001000UL

Setting Timer 1 clock source as internal 10KHz RC clock

Definition at line 78 of file clk.h.

## ◆ CLK_CLKSEL1_TMR1_S_IRC22M

#define CLK_CLKSEL1_TMR1_S_IRC22M 0x00007000UL

Setting Timer 1 clock source as internal 22.1184MHz RC clock

Definition at line 81 of file clk.h.

## ◆ CLK_CLKSEL1_TMR1_S_LIRC

#define CLK_CLKSEL1_TMR1_S_LIRC 0x00001000UL

Setting Timer 1 clock source as internal 10KHz RC clock

Definition at line 79 of file clk.h.

## ◆ CLK_CLKSEL1_TMR1_S_XTAL

#define CLK_CLKSEL1_TMR1_S_XTAL 0x00000000UL

Setting Timer 1 clock source as external XTAL

Definition at line 77 of file clk.h.

## ◆ CLK_CLKSEL1_UART_S_HIRC

#define CLK_CLKSEL1_UART_S_HIRC 0x02000000UL

Setting UART clock source as external internal 22.1184MHz RC clock

Definition at line 85 of file clk.h.

## ◆ CLK_CLKSEL1_UART_S_IRC22M

#define CLK_CLKSEL1_UART_S_IRC22M 0x02000000UL

Setting UART clock source as external internal 22.1184MHz RC clock

Definition at line 84 of file clk.h.

## ◆ CLK_CLKSEL1_UART_S_XTAL

#define CLK_CLKSEL1_UART_S_XTAL 0x00000000UL

Setting UART clock source as external XTAL

Definition at line 83 of file clk.h.

## ◆ CLK_CLKSEL1_WDT_S_HCLK_DIV2048

#define CLK_CLKSEL1_WDT_S_HCLK_DIV2048 0x00000002UL

Setting WDT clock source as HCLK/2048

Definition at line 62 of file clk.h.

## ◆ CLK_CLKSEL1_WDT_S_IRC10K

#define CLK_CLKSEL1_WDT_S_IRC10K 0x00000003UL

Setting WDT clock source as internal 10KHz RC clock

Definition at line 63 of file clk.h.

## ◆ CLK_CLKSEL1_WDT_S_LIRC

#define CLK_CLKSEL1_WDT_S_LIRC 0x00000003UL

Setting WDT clock source as internal 10KHz RC clock

Definition at line 64 of file clk.h.

## ◆ CLK_CLKSEL1_WDT_S_XTAL

#define CLK_CLKSEL1_WDT_S_XTAL 0x00000000UL

Setting WDT clock source as external XTAL

Definition at line 61 of file clk.h.

## ◆ CLK_CLKSEL2_FRQDIV_HCLK

#define CLK_CLKSEL2_FRQDIV_HCLK 0x00000008UL

Setting FRQDIV clock source as HCLK

Definition at line 96 of file clk.h.

## ◆ CLK_CLKSEL2_FRQDIV_HIRC

#define CLK_CLKSEL2_FRQDIV_HIRC 0x0000000CUL

Setting FRQDIV clock source as internal 22.1184MHz RC clock

Definition at line 98 of file clk.h.

## ◆ CLK_CLKSEL2_FRQDIV_HXT

#define CLK_CLKSEL2_FRQDIV_HXT 0x00000000UL

Setting FRQDIV clock source as external XTAL

Definition at line 94 of file clk.h.

## ◆ CLK_CLKSEL2_FRQDIV_IRC22M

#define CLK_CLKSEL2_FRQDIV_IRC22M 0x0000000CUL

Setting FRQDIV clock source as internal 22.1184MHz RC clock

Definition at line 97 of file clk.h.

## ◆ CLK_CLKSEL2_FRQDIV_LXT

#define CLK_CLKSEL2_FRQDIV_LXT 0x00000000UL

Setting FRQDIV clock source as external XTAL

Definition at line 95 of file clk.h.

## ◆ CLK_CLKSEL2_FRQDIV_XTAL

#define CLK_CLKSEL2_FRQDIV_XTAL 0x00000000UL

Setting FRQDIV clock source as external XTAL

Definition at line 93 of file clk.h.

## ◆ CLK_CLKSEL2_PWM45_S_HCLK

#define CLK_CLKSEL2_PWM45_S_HCLK 0x00000020UL

Setting PWM45 clock source as HCLK

Definition at line 99 of file clk.h.

## ◆ CLK_PWRCON_HXT

#define CLK_PWRCON_HXT 0x01UL

Setting External Crystal Oscillator as 12MHz

Definition at line 39 of file clk.h.

## ◆ CLK_PWRCON_LXT

#define CLK_PWRCON_LXT 0x02UL

Setting External Crystal Oscillator as 32KHz

Definition at line 41 of file clk.h.

## ◆ CLK_PWRCON_XTL12M

#define CLK_PWRCON_XTL12M 0x01UL

Setting External Crystal Oscillator as 12MHz

Definition at line 38 of file clk.h.

## ◆ CLK_PWRCON_XTL32K

#define CLK_PWRCON_XTL32K 0x02UL

Setting External Crystal Oscillator as 32KHz

Definition at line 40 of file clk.h.

## ◆ FDIV_MODULE

#define FDIV_MODULE ((0x0<<31)|(0x3<<29)|(0x3<<25)|( 2<<20)|(0x3<<18)|(MODULE_NoMsk<<10)|(31<<5)|CLK_APBCLK_FDIV_EN_Pos)

Frequency Divider Output Module

Definition at line 127 of file clk.h.

## ◆ I2C_MODULE

#define I2C_MODULE ((0x0<<31)|(0x3<<29)|(MODULE_NoMsk<<25)|(31<<20)|(0x3<<18)|(MODULE_NoMsk<<10)|(31<<5)|CLK_APBCLK_I2C_EN_Pos)

I2C Module

Definition at line 128 of file clk.h.

## ◆ MODULE_APBCLK

#define MODULE_APBCLK | ( |  | x | ) | ((x >>31) & 0x1)

Calculate APBCLK offset on MODULE index

Definition at line 112 of file clk.h.

## ◆ MODULE_CLKDIV

#define MODULE_CLKDIV | ( |  | x | ) | ((x >>18) & 0x3)

Calculate APBCLK CLKDIV on MODULE index

Definition at line 116 of file clk.h.

## ◆ MODULE_CLKDIV_Msk

#define MODULE_CLKDIV_Msk | ( |  | x | ) | ((x >>10) & 0xff)

Calculate CLKDIV mask offset on MODULE index

Definition at line 117 of file clk.h.

## ◆ MODULE_CLKDIV_Pos

#define MODULE_CLKDIV_Pos | ( |  | x | ) | ((x >>5 ) & 0x1f)

Calculate CLKDIV position offset on MODULE index

Definition at line 118 of file clk.h.

## ◆ MODULE_CLKSEL

#define MODULE_CLKSEL | ( |  | x | ) | ((x >>29) & 0x3)

Calculate CLKSEL offset on MODULE index

Definition at line 113 of file clk.h.

## ◆ MODULE_CLKSEL_Msk

#define MODULE_CLKSEL_Msk | ( |  | x | ) | ((x >>25) & 0xf)

Calculate CLKSEL mask offset on MODULE index

Definition at line 114 of file clk.h.

## ◆ MODULE_CLKSEL_Pos

#define MODULE_CLKSEL_Pos | ( |  | x | ) | ((x >>20) & 0x1f)

Calculate CLKSEL position offset on MODULE index

Definition at line 115 of file clk.h.

## ◆ MODULE_IP_EN_Pos

#define MODULE_IP_EN_Pos | ( |  | x | ) | ((x >>0 ) & 0x1f)

Calculate APBCLK offset on MODULE index

Definition at line 119 of file clk.h.

## ◆ MODULE_NoMsk

#define MODULE_NoMsk 0x0

Not mask on MODULE index

Definition at line 120 of file clk.h.

## ◆ PWM01_MODULE

#define PWM01_MODULE ((0x0<<31)|(0x1<<29)|(0x3<<25)|(28<<20)|(0x3<<18)|(MODULE_NoMsk<<10)|(31<<5)|CLK_APBCLK_PWM01_EN_Pos)

PWM Channel0 and Channel1 Module

Definition at line 131 of file clk.h.

## ◆ PWM23_MODULE

#define PWM23_MODULE ((0x0<<31)|(0x1<<29)|(0x3<<25)|(30<<20)|(0x3<<18)|(MODULE_NoMsk<<10)|(31<<5)|CLK_APBCLK_PWM23_EN_Pos)

PWM Channel2 and Channel3 Module

Definition at line 132 of file clk.h.

## ◆ PWM45_MODULE

#define PWM45_MODULE ((0x0<<31)|(0x3<<29)|(0x3<<25)|( 4<<20)|(0x3<<18)|(MODULE_NoMsk<<10)|(31<<5)|CLK_APBCLK_PWM45_EN_Pos)

PWM Channel4 and Channel5 Module

Definition at line 133 of file clk.h.

## ◆ SPI_MODULE

#define SPI_MODULE ((0x0<<31)|(0x1<<29)|(0x1<<25)|( 4<<20)|(0x3<<18)|(MODULE_NoMsk<<10)|(31<<5)|CLK_APBCLK_SPI_EN_Pos)

SPI Module

Definition at line 129 of file clk.h.

## ◆ TMR0_MODULE

#define TMR0_MODULE ((0x0<<31)|(0x1<<29)|(0x7<<25)|( 8<<20)|(0x3<<18)|(MODULE_NoMsk<<10)|(31<<5)|CLK_APBCLK_TMR0_EN_Pos)

Timer0 Module

Definition at line 125 of file clk.h.

## ◆ TMR1_MODULE

#define TMR1_MODULE ((0x0<<31)|(0x1<<29)|(0x7<<25)|(12<<20)|(0x3<<18)|(MODULE_NoMsk<<10)|(31<<5)|CLK_APBCLK_TMR1_EN_Pos)

Timer1 Module

Definition at line 126 of file clk.h.

## ◆ UART_MODULE

#define UART_MODULE ((0x0<<31)|(0x1<<29)|(0x3<<25)|(24<<20)|(0x0<<18)|(0x0F<<10)|( 8<<5)|CLK_APBCLK_UART_EN_Pos)

UART Module

Definition at line 130 of file clk.h.

## ◆ WDT_MODULE

#define WDT_MODULE ((0x0<<31)|(0x1<<29)|(0x3<<25)|( 0<<20)|(0x3<<18)|(MODULE_NoMsk<<10)|(31<<5)|CLK_APBCLK_WDT_EN_Pos )

Watchdog Timer Module

Definition at line 124 of file clk.h.