| NUC029FAE BSP V3.01.002 The Board Support Package for NUC029FAE

spi.c
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1 /**************************************************************************/
12 #include "NUC029FAE.h"
39 uint32_t SPI_Open(SPI_T *spi,
40 uint32_t u32MasterSlave,
41 uint32_t u32SPIMode,
42 uint32_t u32DataWidth,
43 uint32_t u32BusClock)
44 {
45 if(u32DataWidth == 32)
46 u32DataWidth = 0;
47
48 spi->CNTRL = u32MasterSlave | (u32DataWidth << SPI_CNTRL_TX_BIT_LEN_Pos) | (u32SPIMode);
49
50 return ( SPI_SetBusClock(spi, u32BusClock) );
51 }
52
58 void SPI_Close(SPI_T *spi)
59 {
60 /* Reset SPI */
61 SYS->IPRSTC2 |= SYS_IPRSTC2_SPI_RST_Msk;
62 SYS->IPRSTC2 &= ~SYS_IPRSTC2_SPI_RST_Msk;
63
64 /* Disable SPI clock */
65 CLK->APBCLK &= ~CLK_APBCLK_SPI_EN_Msk;
66 }
67
73 void SPI_ClearRxFIFO(SPI_T *spi)
74 {
75 spi->FIFO_CTL |= SPI_FIFO_CTL_RX_CLR_Msk;
76 }
77
83 void SPI_ClearTxFIFO(SPI_T *spi)
84 {
85 spi->FIFO_CTL |= SPI_FIFO_CTL_TX_CLR_Msk;
86 }
87
93 void SPI_DisableAutoSS(SPI_T *spi)
94 {
95 spi->SSR &= ~SPI_SSR_AUTOSS_Msk;
96 }
97
105 void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel)
106 {
107 spi->SSR |= (u32SSPinMask | u32ActiveLevel) | SPI_SSR_AUTOSS_Msk;
108 }
109
116 uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock)
117 {
118 uint32_t u32ClkSrc, u32Div = 0;
119
120 if((CLK->CLKSEL1 & CLK_CLKSEL1_SPI_S_Msk) == CLK_CLKSEL1_SPI_S_HCLK)
121 u32ClkSrc = CLK_GetHCLKFreq();
122 else
123 {
124 if((CLK->PWRCON & CLK_PWRCON_XTLCLK_EN_Msk) == CLK_PWRCON_HXT)
125 u32ClkSrc = CLK_GetHXTFreq();
126 else
127 u32ClkSrc = CLK_GetLXTFreq();
128 }
129
130 if(u32BusClock != 0 )
131 {
132 u32Div = (u32ClkSrc / (2*u32BusClock)) - 1;
133 if(u32Div > SPI_DIVIDER_DIVIDER_Msk)
134 u32Div = SPI_DIVIDER_DIVIDER_Msk;
135 }
136
137 spi->DIVIDER = (spi->DIVIDER & ~SPI_DIVIDER_DIVIDER_Msk) | u32Div;
138
139 return ( u32ClkSrc / ((u32Div + 1) *2) );
140 }
141
149 void SPI_EnableFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold)
150 {
151 spi->FIFO_CTL = (spi->FIFO_CTL & ~(SPI_FIFO_CTL_TX_THRESHOLD_Msk | SPI_FIFO_CTL_RX_THRESHOLD_Msk) |
152 (u32TxThreshold << SPI_FIFO_CTL_TX_THRESHOLD_Pos) |
153 (u32RxThreshold << SPI_FIFO_CTL_RX_THRESHOLD_Pos));
154
155 spi->CNTRL |= SPI_CNTRL_FIFO_Msk;
156 }
157
163 void SPI_DisableFIFO(SPI_T *spi)
164 {
165 spi->CNTRL &= ~SPI_CNTRL_FIFO_Msk;
166 }
167
173 uint32_t SPI_GetBusClock(SPI_T *spi)
174 {
175 uint32_t u32Div = 0;
176 uint32_t u32ClkSrc;
177
178 if((CLK->CLKSEL1 & CLK_CLKSEL1_SPI_S_Msk) == CLK_CLKSEL1_SPI_S_HCLK)
179 u32ClkSrc = CLK_GetHCLKFreq();
180 else
181 {
182 if((CLK->PWRCON & CLK_PWRCON_XTLCLK_EN_Msk) == CLK_PWRCON_HXT)
183 u32ClkSrc = CLK_GetHXTFreq();
184 else
185 u32ClkSrc = CLK_GetLXTFreq();
186 }
187
188 spi->DIVIDER = (spi->DIVIDER & ~SPI_DIVIDER_DIVIDER_Msk) | u32Div;
189
190 return (u32ClkSrc / ((u32Div + 1) *2));
191 }
192
203 void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask)
204 {
205 if((u32Mask & SPI_IE_MASK) == SPI_IE_MASK)
206 spi->CNTRL |= SPI_CNTRL_IE_Msk;
207
208 if((u32Mask & SPI_SSTA_INTEN_MASK) == SPI_SSTA_INTEN_MASK)
209 spi->CNTRL2 |= SPI_CNTRL2_SSTA_INTEN_Msk;
210
211 if((u32Mask & SPI_FIFO_TX_INTEN_MASK) == SPI_FIFO_TX_INTEN_MASK)
212 spi->FIFO_CTL |= SPI_FIFO_CTL_TX_INTEN_Msk;
213
214 if((u32Mask & SPI_FIFO_RX_INTEN_MASK) == SPI_FIFO_RX_INTEN_MASK)
215 spi->FIFO_CTL |= SPI_FIFO_CTL_RX_INTEN_Msk;
216
217 if((u32Mask & SPI_FIFO_RXOV_INTEN_MASK) == SPI_FIFO_RXOV_INTEN_MASK)
218 spi->FIFO_CTL |= SPI_FIFO_CTL_RXOV_INTEN_Msk;
219
220 if((u32Mask & SPI_FIFO_TIMEOUT_INTEN_MASK) == SPI_FIFO_TIMEOUT_INTEN_MASK)
221 spi->FIFO_CTL |= SPI_FIFO_CTL_TIMEOUT_INTEN_Msk;
222 }
223
234 void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask)
235 {
236 if((u32Mask & SPI_IE_MASK) == SPI_IE_MASK)
237 spi->CNTRL &= ~SPI_CNTRL_IE_Msk;
238
239 if((u32Mask & SPI_SSTA_INTEN_MASK) == SPI_SSTA_INTEN_MASK)
240 spi->CNTRL2 &= ~SPI_CNTRL2_SSTA_INTEN_Msk;
241
242 if((u32Mask & SPI_FIFO_TX_INTEN_MASK) == SPI_FIFO_TX_INTEN_MASK)
243 spi->FIFO_CTL &= ~SPI_FIFO_CTL_TX_INTEN_Msk;
244
245 if((u32Mask & SPI_FIFO_RX_INTEN_MASK) == SPI_FIFO_RX_INTEN_MASK)
246 spi->FIFO_CTL &= ~SPI_FIFO_CTL_RX_INTEN_Msk;
247
248 if((u32Mask & SPI_FIFO_RXOV_INTEN_MASK) == SPI_FIFO_RXOV_INTEN_MASK)
249 spi->FIFO_CTL &= ~SPI_FIFO_CTL_RXOV_INTEN_Msk;
250
251 if((u32Mask & SPI_FIFO_TIMEOUT_INTEN_MASK) == SPI_FIFO_TIMEOUT_INTEN_MASK)
252 spi->FIFO_CTL &= ~SPI_FIFO_CTL_TIMEOUT_INTEN_Msk;
253 }
254 /* end of group NUC029FAE_SPI_EXPORTED_FUNCTIONS */
256 /* end of group NUC029FAE_SPI_Driver */
258 /* end of group NUC029FAE_Device_Driver */
260
261 /*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
SPI_EnableInt
void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask)
Enable FIFO related interrupts specified by u32Mask parameter.
Definition: spi.c:203
SPI_T::DIVIDER
__IO uint32_t DIVIDER
Definition: NUC029FAE.h:1824
SPI_T::CNTRL2
__IO uint32_t CNTRL2
Definition: NUC029FAE.h:1831
NUC029FAE.h
NUC029FAE peripheral access layer header file. This file contains all the peripheral register's defin...
SPI_ClearRxFIFO
void SPI_ClearRxFIFO(SPI_T *spi)
Clear Rx FIFO buffer.
Definition: spi.c:73
SPI_IE_MASK
#define SPI_IE_MASK
Definition: spi.h:45
CLK_GetHCLKFreq
uint32_t CLK_GetHCLKFreq(void)
This function get HCLK frequency. The frequency unit is Hz.
Definition: clk.c:114
SPI_T::SSR
__IO uint32_t SSR
Definition: NUC029FAE.h:1825
SPI_DisableInt
void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask)
Disable FIFO related interrupts specified by u32Mask parameter.
Definition: spi.c:234
CLK_GetHXTFreq
uint32_t CLK_GetHXTFreq(void)
This function get external high frequency crystal frequency. The frequency unit is Hz.
Definition: clk.c:90
SPI_T::CNTRL
__IO uint32_t CNTRL
Definition: NUC029FAE.h:1823
SPI_GetBusClock
uint32_t SPI_GetBusClock(SPI_T *spi)
Get the actual frequency of SPI bus clock. Only available in Master mode.
Definition: spi.c:173
SPI_T
Definition: NUC029FAE.h:1821
CLK_GetLXTFreq
uint32_t CLK_GetLXTFreq(void)
This function get external low frequency crystal frequency. The frequency unit is Hz.
Definition: clk.c:102
SYS
#define SYS
Pointer to SYS register structure.
Definition: NUC029FAE.h:3227
SPI_Close
void SPI_Close(SPI_T *spi)
Reset SPI module and disable SPI peripheral clock.
Definition: spi.c:58
SPI_FIFO_TIMEOUT_INTEN_MASK
#define SPI_FIFO_TIMEOUT_INTEN_MASK
Definition: spi.h:50
SPI_SSTA_INTEN_MASK
#define SPI_SSTA_INTEN_MASK
Definition: spi.h:46
CLK
#define CLK
Pointer to CLK register structure.
Definition: NUC029FAE.h:3228
SPI_DisableAutoSS
void SPI_DisableAutoSS(SPI_T *spi)
Disable the automatic slave select function.
Definition: spi.c:93
CLK_PWRCON_HXT
#define CLK_PWRCON_HXT
Definition: clk.h:39
SPI_FIFO_TX_INTEN_MASK
#define SPI_FIFO_TX_INTEN_MASK
Definition: spi.h:47
SPI_T::FIFO_CTL
__IO uint32_t FIFO_CTL
Definition: NUC029FAE.h:1832
SPI_FIFO_RX_INTEN_MASK
#define SPI_FIFO_RX_INTEN_MASK
Definition: spi.h:48
SPI_Open
uint32_t SPI_Open(SPI_T *spi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock)
This function make SPI module be ready to transfer. By default, the SPI transfer sequence is MSB firs...
Definition: spi.c:39
SPI_DisableFIFO
void SPI_DisableFIFO(SPI_T *spi)
Disable FIFO mode.
Definition: spi.c:163
SPI_ClearTxFIFO
void SPI_ClearTxFIFO(SPI_T *spi)
Clear Tx FIFO buffer.
Definition: spi.c:83
SPI_FIFO_RXOV_INTEN_MASK
#define SPI_FIFO_RXOV_INTEN_MASK
Definition: spi.h:49
SPI_EnableAutoSS
void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel)
Enable the automatic slave select function. Only available in Master mode.
Definition: spi.c:105
CLK_CLKSEL1_SPI_S_HCLK
#define CLK_CLKSEL1_SPI_S_HCLK
Definition: clk.h:70
SPI_EnableFIFO
void SPI_EnableFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold)
Enable FIFO mode with user-specified Tx FIFO threshold and Rx FIFO threshold configurations.
Definition: spi.c:149
SPI_SetBusClock
uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock)
Set the SPI bus clock. Only available in Master mode.
Definition: spi.c:116