| NUC029FAE BSP V3.01.002 The Board Support Package for NUC029FAE

Data Fields
PWM_T Struct Reference
NUC029FAE Control Register » Pulse Width Modulation Controller(PWM)

`#include <NUC029FAE.h>`

## Data Fields
__IO uint32_t | PPR
__IO uint32_t | CSR
__IO uint32_t | PCR
__IO uint32_t | CNR [6]
__IO uint32_t | CMR [6]
uint32_t | RESERVED0 [6]
__IO uint32_t | PIER
__IO uint32_t | PIIR
__IO uint32_t | POE
__IO uint32_t | PFBCON
__IO uint32_t | PDZIR
__IO uint32_t | TRGCON0
__IO uint32_t | TRGCON1
__IO uint32_t | TRGSTS0
__IO uint32_t | TRGSTS1
__IO uint32_t | PHCHG
__IO uint32_t | PHCHGNXT
__IO uint32_t | PHCHGMASK
__IO uint32_t | INTACCUCTL

## Detailed Description

Definition at line 1171 of file NUC029FAE.h.

## Field Documentation

## ◆ CMR

__IO uint32_t PWM_T::CMR[6]

Offset: 0x0024 ~ 0x0038 PWM Comparator Register 0 ~ 5

Definition at line 1177 of file NUC029FAE.h.

## ◆ CNR

__IO uint32_t PWM_T::CNR[6]

Offset: 0x000C ~ 0x0020 PWM Counter Register 0 ~ 5

Definition at line 1176 of file NUC029FAE.h.

## ◆ CSR

__IO uint32_t PWM_T::CSR

Offset: 0x0004 PWM Clock Select Register

Definition at line 1174 of file NUC029FAE.h.

## ◆ INTACCUCTL

__IO uint32_t PWM_T::INTACCUCTL

Offset: 0x0084 PWM Period Interrupt Accumulation Control Register

Definition at line 1191 of file NUC029FAE.h.

## ◆ PCR

__IO uint32_t PWM_T::PCR

Offset: 0x0008 PWM Control Register

Definition at line 1175 of file NUC029FAE.h.

## ◆ PDZIR

__IO uint32_t PWM_T::PDZIR

Offset: 0x0064 PWM Dead-zone Interval Register

Definition at line 1183 of file NUC029FAE.h.

## ◆ PFBCON

__IO uint32_t PWM_T::PFBCON

Offset: 0x0060 PWM Fault Brake Control Register

Definition at line 1182 of file NUC029FAE.h.

## ◆ PHCHG

__IO uint32_t PWM_T::PHCHG

Offset: 0x0078 PWM Phase Changed Register

Definition at line 1188 of file NUC029FAE.h.

## ◆ PHCHGMASK

__IO uint32_t PWM_T::PHCHGMASK

Offset: 0x0080 PWM Phase Change MASK Register

Definition at line 1190 of file NUC029FAE.h.

## ◆ PHCHGNXT

__IO uint32_t PWM_T::PHCHGNXT

Offset: 0x007C PWM Next Phase Change Register

Definition at line 1189 of file NUC029FAE.h.

## ◆ PIER

__IO uint32_t PWM_T::PIER

Offset: 0x0054 PWM Interrupt Enable Register

Definition at line 1179 of file NUC029FAE.h.

## ◆ PIIR

__IO uint32_t PWM_T::PIIR

Offset: 0x0058 PWM Interrupt Indication Register

Definition at line 1180 of file NUC029FAE.h.

## ◆ POE

__IO uint32_t PWM_T::POE

Offset: 0x005C PWM Output Enable Register

Definition at line 1181 of file NUC029FAE.h.

## ◆ PPR

__IO uint32_t PWM_T::PPR

Offset: 0x0000 PWM Pre-scale Register

Definition at line 1173 of file NUC029FAE.h.

## ◆ RESERVED0

uint32_t PWM_T::RESERVED0[6]

Offset: 0x003C ~ 0x0050 Reserved

Definition at line 1178 of file NUC029FAE.h.

## ◆ TRGCON0

__IO uint32_t PWM_T::TRGCON0

Offset: 0x0068 PWM Trigger Control Register 0

Definition at line 1184 of file NUC029FAE.h.

## ◆ TRGCON1

__IO uint32_t PWM_T::TRGCON1

Offset: 0x006C PWM Trigger Control Register 1

Definition at line 1185 of file NUC029FAE.h.

## ◆ TRGSTS0

__IO uint32_t PWM_T::TRGSTS0

Offset: 0x0070 PWM Trigger Status Register 0

Definition at line 1186 of file NUC029FAE.h.

## ◆ TRGSTS1

__IO uint32_t PWM_T::TRGSTS1

Offset: 0x0074 PWM Trigger Status Register 1

Definition at line 1187 of file NUC029FAE.h.

The documentation for this struct was generated from the following file:

- C:/Users/yachen/workzone/bsp/nuc029faebsp/Library/Device/Nuvoton/NUC029FAE/Include/NUC029FAE.h