NUC029FAE BSP  V3.01.002
The Board Support Package for NUC029FAE
Data Fields

#include <NUC029FAE.h>

Data Fields

__IO uint32_t PWRCON
 
__IO uint32_t AHBCLK
 
__IO uint32_t APBCLK
 
__IO uint32_t CLKSTATUS
 
__IO uint32_t CLKSEL0
 
__IO uint32_t CLKSEL1
 
__IO uint32_t CLKDIV
 
__IO uint32_t CLKSEL2
 
uint32_t RESERVED0
 
__IO uint32_t FRQDIV
 

Detailed Description

Definition at line 203 of file NUC029FAE.h.

Field Documentation

◆ AHBCLK

__IO uint32_t CLK_T::AHBCLK

AHBCLK

Offset: 0x04 AHB Devices Clock Enable Control Register

Bits Field Descriptions
[2] ISP_EN Flash ISP Controller Clock Enable Control.
1 = To enable the Flash ISP controller clock.
0 = To disable the Flash ISP controller clock.

Definition at line 270 of file NUC029FAE.h.

◆ APBCLK

__IO uint32_t CLK_T::APBCLK

APBCLK

Offset: 0x08 APB Devices Clock Enable Control Register

Bits Field Descriptions
[0] WDT_EN Watch Dog Timer Clock Enable.
This bit is the protected bit, program this need a open lock sequence, write "59h","16h","88h" to
address 0x5000_0100 to un-lock this bit. Reference the register REGWRPROT at address
SYS_BA + 0x100
0 = Disable Watchdog Timer Clock
1 = Enable Watchdog Timer Clock
[2] TMR0_EN Timer0 Clock Enable Control
0 = Disable Timer0 Clock
1 = Enable Timer0 Clock
[3] TMR1_EN Timer1 Clock Enable Control
0 = Disable Timer1 Clock
1 = Enable Timer1 Clock
[6] FDIV_EN Clock Divider Clock Enable Control
0 = Disable FDIV Clock
1 = Enable FDIV Clock
[8] I2C_EN I2C Clock Enable Control.
0 = Disable I2C Clock
1 = Enable I2C Clock
[12] SPI_EN SPI Clock Enable Control.
0 = Disable SPI Clock
1 = Enable SPI Clock
[16] UART_EN UART Clock Enable Control.
1 = Enable UART clock
0 = Disable UART clock
[20] PWM01_EN PWM_01 Clock Enable Control.
1 = Enable PWM01 clock
0 = Disable PWM01 clock
[21] PWM23_EN PWM_23 Clock Enable Control.
1 = Enable PWM23 clock
0 = Disable PWM23 clock
[22] PWM45_EN PWM_45 Clock Enable Control.
1 = Enable PWM45 clock
0 = Disable PWM45 clock
[28] ADC_EN Analog-Digital-Converter (ADC) Clock Enable Control.
1 = Enable ADC clock
0 = Disable ADC clock
[30] CMP_EN Comparator Clock Enable Control.
1 = Enable Analog Comparator clock
0 = Disable Analog Comparator clock

Definition at line 319 of file NUC029FAE.h.

◆ CLKDIV

__IO uint32_t CLK_T::CLKDIV

CLKDIV

Offset: 0x18 Clock Divider Number Register

Bits Field Descriptions
[3:0] HCLK_N HCLK clock divide number from HCLK clock source
The HCLK clock frequency = (HCLK clock source frequency) / (HCLK_N + 1)
[11:8] UART_N UART clock divide number from UART clock source
The UART clock frequency = (UART clock source frequency ) / (UART_N + 1)
[23:16] ADC_N ADC clock divide number from ADC clock source
The ADC clock frequency = (ADC clock source frequency ) / (ADC_N + 1)

Definition at line 433 of file NUC029FAE.h.

◆ CLKSEL0

__IO uint32_t CLK_T::CLKSEL0

CLKSEL0

Offset: 0x10 Clock Source Select Control Register 0

Bits Field Descriptions
[2:0] HCLK_S HCLK clock source select.
Note:
1. Before clock switch the related clock sources (pre-select and new-select) must be turn on
2. These bits are protected bit, program this need an open lock sequence, write
"59h","16h","88h" to address 0x5000_0100 to un-lock this bit. Reference the register
REGWRPROT at address SYS_BA + 0x100
3. To set PWRCON[1:0] to select 12 MHz or 32 KHz crystal clock.
000 = Clock source from external 12 MHz or 32 KHz crystal clock.
011 = clock source from internal 10KHz oscillator clock
111 = clock source from internal 22.1184 MHz oscillator clock
others = Reserved
[5:3] STCLK_S MCU Cortex_M0 SysTick clock source select.
These bits are protected bit, program this need an open lock sequence, write "59h","16h","88h" to
address 0x5000_0100 to un-lock this bit. Reference the register REGWRPROT at address SYS_BA
+ 0x100
000 = Clock source from 12 MHz or 32 KHz crystal clock
010 = Clock source from 12 MHz or 32 KHz crystal clock/2
011 = clock source from HCLK/2
111 = clock source from internal 22.1184 MHz oscillator clock/2
others = Reserved
Note: To set PWRCON[1:0] to select 12 MHz or 32 KHz crystal clock.

Definition at line 373 of file NUC029FAE.h.

◆ CLKSEL1

__IO uint32_t CLK_T::CLKSEL1

CLKSEL1

Offset: 0x14 Clock Source Select Control Register 1

Bits Field Descriptions
[1:0] WDT_S Watchdog Timer clock source select.
These bits are protected bit, program this need a open lock sequence, write "59h","16h","88h" to
address 0x5000_0100 to un-lock this bit. Reference the register REGWRPROT at address
SYS_BA + 0x100
00 = Clock source from external 12 MHz or 32 KHz crystal clock.
10 = clock source from HCLK/2048 clock
11 = clock source from internal 10KHz oscillator clock
[3:2] ADC_S ADC clock source select.
00 = Clock source from external 12 MHz or 32 KHz crystal clock.
10 = clock source from HCLK
11 = clock source from internal 22.1184 MHz oscillator clock
[10:8] TMR0_S TIMER0 clock source select.
000 = Clock source from external 12 MHz or 32 KHz crystal clock
001 = Clock source from internal 10 KHz oscillator clock.
010 = clock source from HCLK
011 = clock source from external trigger
111 = clock source from internal 22.1184 MHz oscillator clock
[14:12] TMR1_S TIMER1 clock source select.
000 = Clock source from external 12 MHz or 32 KHz crystal clock
001 = Clock source from internal 10 KHz oscillator clock.
010 = clock source from HCLK
011 = clock source from external trigger
111 = clock source from internal 22.1184 MHz oscillator clock
[25:24] UART_S UART clock source select.
00 = Clock source from external 12 MHz or 32 KHz crystal clock
10 = clock source from internal 22.1184 MHz oscillator clock
[29:28] PWM01_S PWM0 and PWM1 clock source select.
PWM0 and PWM1 uses the same Engine clock source, both of them with the same pre-scalar
10 = clock source from HCLK
others = Reserved
[31:30] PWM23_S PWM2 and PWM3 clock source select.
PWM2 and PWM3 uses the same Engine clock source, both of them with the same pre-scalar
10 = clock source from HCLK
others = Reserved

Definition at line 417 of file NUC029FAE.h.

◆ CLKSEL2

__IO uint32_t CLK_T::CLKSEL2

CLKSEL2

Offset: 0x1C Clock Source Select Control Register 2

Bits Field Descriptions
[3:2] FRQDIV_S Clock Divider Clock Source Select
00 = Clock source from external 12 MHz or 32 KHz crystal clock
10 = clock source from HCLK
11 = clock source from internal 22.1184 MHz oscillator clock
[5:4] PWM45_S PWM4 and PWM5 clock source select. - PWM4 and PWM5 used the same Engine clock source,
both of them with the same pre-scalar
10 = clock source from HCLK
others = Reserved

Definition at line 451 of file NUC029FAE.h.

◆ CLKSTATUS

__IO uint32_t CLK_T::CLKSTATUS

CLKSTATUS

Offset: 0x0C Clock Status Monitor Register

Bits Field Descriptions
[0] XTL_STB XTL12M or XTL32K clock source stable flag
1 = External Crystal clock is stable
0 = External Crystal clock is not stable or not enable
[3] OSC10K_STB OSC10K clock source stable flag
1 = OSC10K clock is stable
0 = OSC10K clock is not stable or not enable
[4] OSC22M_STB OSC22M clock source stable flag
1 = OSC22M clock is stable
0 = OSC22M clock is not stable or not enable
[7] CLK_SW_FAIL Clock switch fail flag
1 = Clock switch fail
0 = Clock switch success
This bit will be set when target switch clock source is not stable. Write 1 to clear this bit to zero.

Definition at line 342 of file NUC029FAE.h.

◆ FRQDIV

__IO uint32_t CLK_T::FRQDIV

FRQDIV

Offset: 0x24 Frequency Divider Control Register

Bits Field Descriptions
[3:0] FSEL Divider Output Frequency Selection Bits
The formula of output frequency is
Fout = Fin/2^(N+1),
where Fin is the input clock frequency, Fout is the frequency of divider output clock, N is the 4-bit
value of FSEL[3:0].
[4] DIVIDER_EN Frequency Divider Enable Bit
0 = Disable Frequency Divider
1 = Enable Frequency Divider

Definition at line 473 of file NUC029FAE.h.

◆ PWRCON

__IO uint32_t CLK_T::PWRCON

PWRCON

Offset: 0x00 System Power Down Control Register

Bits Field Descriptions
[1:0] XTLCLK_EN External Crystal Oscillator Control
The default clock source is from internal 22.1184 MHz. These two bits are default set to "00"
and the XTAL1 and XTAL2 pins are GPIO.
00 = XTAL1 and XTAL2 are GPIO, disable both XTL32K & XTAL12M
01 = XTAL12M (HXT) Enabled
10 = XTAL32K (LXT) Enabled
11 = XTAL1 is external clock input pin, XTAL2 is GPIO
Note: To enable external XTAL function, P5_ALT[1:0] and P5_MFP[1:0] bits must also be set in P5_MFP.
[2] OSC22M_EN Internal 22.1184 MHz Oscillator Control
1 = 22.1184 MHz Oscillation enable
0 = 22.1184 MHz Oscillation disable
[3] OSC10K_EN Internal 10KHz Oscillator Control
1 = 10KHz Oscillation enable
0 = 10KHz Oscillation disable
[4] PU_DLY Enable the wake up delay counter.
When the chip wakes up from power down mode, the clock control will delay certain clock
cycles to wait system clock stable.
The delayed clock cycle is 4096 clock cycles when chip work at external crystal (4 ~
24MHz), and 256 clock cycles when chip work at 22.1184 MHz oscillator.
1 = Enable the clock cycle delay
0 = Disable the clock cycle delay
[5] WINT_EN Power down mode wake Up Interrupt Enable
0 = Disable
1 = Enable. The interrupt will occur when Power down mode wakeup.
[6] PD_WU_STS Chip power down wake up status flag
Set by "power down wake up", it indicates that resume from power down mode
The flag is set if the GPIO, UART, WDT, ACMP, Timer or BOD wakeup
Write 1 to clear the bit
Note: This bit is working only if PD_WU_INT_EN (PWRCON[5]) set to 1.
[7] PWR_DOWN System Power-down Active or Enable Bit
When chip waked-up from power-down, this bit is automatically cleared, and user needs to set
this bit again for the next power-down.
In Power-down mode, the LDO, external crystal and the 22.1184 MHz OSC will be disabled, and
the 10K enable is not controlled by this bit.
Note: If XTLCLK_EN[1:0] = 10 (enable 32 KHz External Crystal Oscillator) and when PWR_DOWN_EN ="1" (system entering
Power-down mode), the external crystal oscillator cannot be disabled to ensure system wake-up enabled.
When power down, all of the AMBA clocks (HCLKx, CPU clock and the PCLKx) are also disabled, and the clock
source selection is ignored. The IP engine clock is not controlled by this bit if the IP clock source is from
the 10K clock and the WDT from 10K).
1 = Chip entering the Power-down mode instantly or wait CPU Idle command
0 = Chip operated in Normal mode or CPU enters into Idle mode.
[9] PD_32K This bit controls the crystal oscillator active or not in Power-down mode.
1 = If XTLCLK_EN[1:0] = 10, 32.768 KHz crystal oscillator (LXT) is still active in Power-down mode.
0 = No effect to Power-down mode

Definition at line 257 of file NUC029FAE.h.

◆ RESERVED0

uint32_t CLK_T::RESERVED0

Reserved

Definition at line 455 of file NUC029FAE.h.


The documentation for this struct was generated from the following file: