#include <NUC029FAE.h>
Definition at line 748 of file NUC029FAE.h.
◆ DFBADR
| __I uint32_t FMC_T::DFBADR |
DFBADR
Offset: 0x14 Data Flash Base Address Register
| Bits | Field | Descriptions |
| [31:0] | DFBA | Data Flash Base Address |
| | This register indicates data flash start address. It is a read only register. |
| | | | | |It is a read only register. | | | | | |The data flash start address is defined by user. Since on chip flash erase | | |unit is 512 bytes, it is mandatory to keep bit 8-0 as "0".
Definition at line 881 of file NUC029FAE.h.
◆ ISPADR
| __IO uint32_t FMC_T::ISPADR |
ISPADR
Offset: 0x04 ISP Address Register
| Bits | Field | Descriptions |
| [31:0] | ISPADR | ISP Address |
| | NuMicro NUC029FAETM series supports word program only. ISPADR[1:0] must be kept |
| | 00b for ISP operation. |
Definition at line 817 of file NUC029FAE.h.
◆ ISPCMD
| __IO uint32_t FMC_T::ISPCMD |
ISPCMD
Offset: 0x0C ISP Command Register
| Bits | Field | Descriptions |
| [5:0] | FOEN_FCEN_FCTRL | ISP Command |
| | ISP command table is shown below: |
| | Operation Mode, FOEN, FCEN, FCTRL[3:0] |
| | Read , 0, 0, 0000 |
| | Program , 1, 0, 0001 |
| | Page Erase , 1, 0, 0010 |
| | Read CID , 0, 0, 1011 |
| | Read DID , 0, 0, 1100 |
| | Read UID , 0, 0, 0100 |
Definition at line 849 of file NUC029FAE.h.
◆ ISPCON
| __IO uint32_t FMC_T::ISPCON |
ISPCON
Offset: 0x00 ISP Control Register
| Bits | Field | Descriptions |
| [0] | ISPEN | ISP Enable |
| | ISP function enable bit. Set this bit to enable ISP function. |
| | 1 = Enable ISP function |
| | 0 = Disable ISP function |
| [1] | BS | Boot Select |
| | Set/clear this bit to select next booting from LDROM/APROM, respectively. |
| | This bit also functions as MCU booting status flag, which can be used to |
| | check where MCU booted from. This bit is initiated with the inverse value |
| | of CBS in Config0 after power-on reset; It keeps the same value at other reset. |
| | 1 = Boot from LDROM |
| | 0 = Boot from APROM |
| [4] | CFGUEN | Enable Config-bits Update by ISP |
| | 1 = Enable ISP can update config-bits |
| | 0 = Disable ISP can update config-bits. |
| [5] | LDUEN | LDROM Update Enable |
| | LDROM update enable bit. |
| | 1 = LDROM can be updated when the MCU runs in APROM. |
| | 0 = LDROM cannot be updated |
| [6] | ISPFF | ISP Fail Flag |
| | This bit is set by hardware when a triggered ISP meets any of the following conditions: |
| | (1) APROM writes to itself. |
| | (2) LDROM writes to itself. |
| | (3) CONFIG is erased/programmed when the MCU is running in APROM. |
| | (4) Destination address is illegal, such as over an available range. |
| | Write 1 to clear. |
| [7] | SWRST | Software Reset |
| | Writing 1 to this bit to start software reset. |
| | It is cleared by hardware after reset is finished. |
| [10:8] | PT | Flash Program Time |
| | 000 = 40 us |
| | 001 = 45 us |
| | 010 = 50 us |
| | 011 = 55 us |
| | 100 = 20 us |
| | 101 = 25 us |
| | 110 = 30 us |
| | 111 = 35 us |
| [14:12] | ET | Flash Erase Time |
| | 000 = 20 ms (default) |
| | 001 = 25 ms |
| | 010 = 30 ms |
| | 011 = 35 ms |
| | 100 = 3 ms |
| | 101 = 5 ms |
| | 110 = 10 ms |
| | 111 = 15 ms |
Definition at line 804 of file NUC029FAE.h.
◆ ISPDAT
| __IO uint32_t FMC_T::ISPDAT |
ISPDAT
Offset: 0x08 ISP Data Register
| Bits | Field | Descriptions |
| [31:0] | ISPDAT | ISP Data |
| | Write data to this register before ISP program operation |
| | Read data from this register after ISP read operation |
Definition at line 830 of file NUC029FAE.h.
◆ ISPTRG
| __IO uint32_t FMC_T::ISPTRG |
ISPTRG
Offset: 0x10 ISP Trigger Control Register
| Bits | Field | Descriptions |
| [0] | ISPGO | ISP start trigger |
| | Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP |
| | operation is finish. |
| | 1 = ISP is on going |
| | 0 = ISP operation is finished. |
Definition at line 864 of file NUC029FAE.h.
The documentation for this struct was generated from the following file:
- C:/Users/yachen/workzone/bsp/nuc029faebsp/Library/Device/Nuvoton/NUC029FAE/Include/NUC029FAE.h