| NUC029FAE BSP V3.01.002 The Board Support Package for NUC029FAE

spi.h
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1 /**************************************************************************/
12 #ifndef __SPI_H__
13 #define __SPI_H__
14
15 #ifdef __cplusplus
16 extern "C"
17 {
18 #endif
19
20
33 #define SPI_MODE_0 (SPI_CNTRL_TX_NEG_Msk)
34 #define SPI_MODE_1 (SPI_CNTRL_RX_NEG_Msk)
35 #define SPI_MODE_2 (SPI_CNTRL_CLKP_Msk | SPI_CNTRL_RX_NEG_Msk)
36 #define SPI_MODE_3 (SPI_CNTRL_CLKP_Msk | SPI_CNTRL_TX_NEG_Msk)
38 #define SPI_SLAVE (SPI_CNTRL_SLAVE_Msk)
39 #define SPI_MASTER (0x0)
41 #define SPI_SS (SPI_SSR_SSR_Msk)
42 #define SPI_SS_ACTIVE_HIGH (SPI_SSR_SS_LVL_Msk)
43 #define SPI_SS_ACTIVE_LOW (0x0)
45 #define SPI_IE_MASK (0x01)
46 #define SPI_SSTA_INTEN_MASK (0x04)
47 #define SPI_FIFO_TX_INTEN_MASK (0x08)
48 #define SPI_FIFO_RX_INTEN_MASK (0x10)
49 #define SPI_FIFO_RXOV_INTEN_MASK (0x20)
50 #define SPI_FIFO_TIMEOUT_INTEN_MASK (0x40)
53 /* end of group NUC029FAE_SPI_EXPORTED_CONSTANTS */
54
55
65 #define SPI_ABORT_3WIRE_TRANSFER(spi) ( (spi)->CNTRL2 |= SPI_CNTRL2_SLV_ABORT_Msk )
66
72 #define SPI_CLR_3WIRE_START_INT_FLAG(spi) ( (spi)->STATUS = SPI_STATUS_SLV_START_INTSTS_Msk )
73
79 #define SPI_CLR_UNIT_TRANS_INT_FLAG(spi) ( (spi)->STATUS = SPI_STATUS_IF_Msk )
80
86 #define SPI_DISABLE_3WIRE_MODE(spi) ( (spi)->CNTRL2 &= ~SPI_CNTRL2_NOSLVSEL_Msk )
87
93 #define SPI_ENABLE_3WIRE_MODE(spi) ( (spi)->CNTRL2 |= SPI_CNTRL2_NOSLVSEL_Msk )
94
100 #define SPI_GET_RX_FIFO_COUNT(spi) ( (((spi)->STATUS & SPI_STATUS_RX_FIFO_COUNT_Msk) >> SPI_STATUS_RX_FIFO_COUNT_Pos) & 0xf )
101
109 #define SPI_GET_RX_FIFO_EMPTY_FLAG(spi) ( ((spi)->STATUS & SPI_STATUS_RX_EMPTY_Msk) == SPI_STATUS_RX_EMPTY_Msk ? 1:0 )
110
118 #define SPI_GET_TX_FIFO_EMPTY_FLAG(spi) ( ((spi)->STATUS & SPI_STATUS_TX_EMPTY_Msk) == SPI_STATUS_TX_EMPTY_Msk ? 1:0 )
119
125 #define SPI_READ_RX(spi) ( (spi)->RX )
126
133 #define SPI_WRITE_TX(spi, u32TxData) ( (spi)->TX = u32TxData )
134
140 static __INLINE void SPI_SET_SS_HIGH(SPI_T *spi)
141 {
142 spi->SSR &= ~SPI_SSR_AUTOSS_Msk;
143 spi->SSR |= (SPI_SSR_LTRIG_FLAG_Msk | SPI_SSR_SS_LVL_Msk | SPI_SSR_SSR_Msk);
144 }
145
151 static __INLINE void SPI_SET_SS_LOW(SPI_T *spi)
152 {
153 spi->SSR &= ~SPI_SSR_AUTOSS_Msk;
154 spi->SSR |= SPI_SSR_LTRIG_FLAG_Msk;
155 spi->SSR &= ~SPI_SSR_SS_LVL_Msk;
156 spi->SSR |= SPI_SSR_SSR_Msk;
157 }
158
164 #define SPI_ENABLE_BYTE_REORDER(spi) ( (spi)->CNTRL |= SPI_CNTRL_REORDER_Msk )
165
171 #define SPI_DISABLE_BYTE_REORDER(spi) ( (spi)->CNTRL &= ~SPI_CNTRL_REORDER_Msk )
172
179 #define SPI_SET_SUSPEND_CYCLE(spi, u32SuspCycle) ( (spi)->CNTRL = ((spi)->CNTRL & ~SPI_CNTRL_SP_CYCLE_Msk) | (u32SuspCycle << SPI_CNTRL_SP_CYCLE_Pos) )
180
186 #define SPI_SET_LSB_FIRST(spi) ( (spi)->CNTRL |= SPI_CNTRL_LSB_Msk )
187
193 #define SPI_SET_MSB_FIRST(spi) ( (spi)->CNTRL &= ~SPI_CNTRL_LSB_Msk )
194
201 static __INLINE void SPI_SET_DATA_WIDTH(SPI_T *spi, uint32_t u32Width)
202 {
203 if(u32Width == 32)
204 u32Width = 0;
205
206 spi->CNTRL = (spi->CNTRL & ~SPI_CNTRL_TX_BIT_LEN_Msk) | (u32Width << SPI_CNTRL_TX_BIT_LEN_Pos);
207 }
208
216 #define SPI_IS_BUSY(spi) ( ((spi)->CNTRL & SPI_CNTRL_GO_BUSY_Msk) == SPI_CNTRL_GO_BUSY_Msk ? 1:0 )
217
223 #define SPI_TRIGGER(spi) ( (spi)->CNTRL |= SPI_CNTRL_GO_BUSY_Msk )
224
225 uint32_t SPI_Open(SPI_T *spi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock);
226 void SPI_Close(SPI_T *spi);
227 void SPI_ClearRxFIFO(SPI_T *spi);
228 void SPI_ClearTxFIFO(SPI_T *spi);
229 void SPI_DisableAutoSS(SPI_T *spi);
230 void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel);
231 uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock);
232 void SPI_EnableFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold);
233 void SPI_DisableFIFO(SPI_T *spi);
234 uint32_t SPI_GetBusClock(SPI_T *spi);
235 void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask);
236 void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask);
237 /* end of group NUC029FAE_SPI_EXPORTED_FUNCTIONS */
239 /* end of group NUC029FAE_SPI_Driver */
241 /* end of group NUC029FAE_Device_Driver */
243
244 #ifdef __cplusplus
245 }
246 #endif
247
248 #endif //__SPI_H__
249
250 /*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
SPI_EnableInt
void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask)
Enable FIFO related interrupts specified by u32Mask parameter.
Definition: spi.c:203
SPI_ClearRxFIFO
void SPI_ClearRxFIFO(SPI_T *spi)
Clear Rx FIFO buffer.
Definition: spi.c:73
SPI_SET_SS_HIGH
static __INLINE void SPI_SET_SS_HIGH(SPI_T *spi)
Disable automatic slave select function and set SPI_SS pin to high state.
Definition: spi.h:140
SPI_T::SSR
__IO uint32_t SSR
Definition: NUC029FAE.h:1825
SPI_DisableInt
void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask)
Disable FIFO related interrupts specified by u32Mask parameter.
Definition: spi.c:234
SPI_T::CNTRL
__IO uint32_t CNTRL
Definition: NUC029FAE.h:1823
SPI_GetBusClock
uint32_t SPI_GetBusClock(SPI_T *spi)
Get the actual frequency of SPI bus clock. Only available in Master mode.
Definition: spi.c:173
SPI_T
Definition: NUC029FAE.h:1821
SPI_Close
void SPI_Close(SPI_T *spi)
Reset SPI module and disable SPI peripheral clock.
Definition: spi.c:58
SPI_SET_SS_LOW
static __INLINE void SPI_SET_SS_LOW(SPI_T *spi)
Disable automatic slave select function and set SPI_SS pin to low state.
Definition: spi.h:151
SPI_DisableAutoSS
void SPI_DisableAutoSS(SPI_T *spi)
Disable the automatic slave select function.
Definition: spi.c:93
SPI_Open
uint32_t SPI_Open(SPI_T *spi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock)
This function make SPI module be ready to transfer. By default, the SPI transfer sequence is MSB firs...
Definition: spi.c:39
SPI_DisableFIFO
void SPI_DisableFIFO(SPI_T *spi)
Disable FIFO mode.
Definition: spi.c:163
SPI_ClearTxFIFO
void SPI_ClearTxFIFO(SPI_T *spi)
Clear Tx FIFO buffer.
Definition: spi.c:83
SPI_SET_DATA_WIDTH
static __INLINE void SPI_SET_DATA_WIDTH(SPI_T *spi, uint32_t u32Width)
Set the data width of a SPI transaction.
Definition: spi.h:201
SPI_EnableAutoSS
void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel)
Enable the automatic slave select function. Only available in Master mode.
Definition: spi.c:105
SPI_EnableFIFO
void SPI_EnableFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold)
Enable FIFO mode with user-specified Tx FIFO threshold and Rx FIFO threshold configurations.
Definition: spi.c:149
SPI_SetBusClock
uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock)
Set the SPI bus clock. Only available in Master mode.
Definition: spi.c:116