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NUC029FAE BSP
V3.01.002
The Board Support Package for NUC029FAE
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#include <NUC029FAE.h>
Data Fields | |
| __I uint32_t | PDID |
| __IO uint32_t | RSTSRC |
| __IO uint32_t | IPRSTC1 |
| __IO uint32_t | IPRSTC2 |
| uint32_t | RESERVED0 [2] |
| __IO uint32_t | BODCTL |
| uint32_t | RESERVED1 [5] |
| __IO uint32_t | P0_MFP |
| __IO uint32_t | P1_MFP |
| __IO uint32_t | P2_MFP |
| __IO uint32_t | P3_MFP |
| __IO uint32_t | P4_MFP |
| __IO uint32_t | P5_MFP |
| uint32_t | RESERVED3 [14] |
| __IO uint32_t | IRCTRIMCTL |
| __IO uint32_t | IRCTRIMIER |
| __IO uint32_t | IRCTRIMISR |
| uint32_t | RESERVED4 [29] |
| __IO uint32_t | RegLockAddr |
Definition at line 1996 of file NUC029FAE.h.
| __IO uint32_t SYS_T::BODCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [2:1] | BOD_VL | Brown Out Detector Threshold Voltage Selection (initiated & write-protected bit) |
| The default value is set by flash controller user configuration register config0 bit[22:21] | ||
| Brown out voltage | ||
| 11 = Disable 2.7V and 3.8V | ||
| 10 = 3.8V | ||
| 01 = 2.7V | ||
| 00 = Reserved | ||
| [3] | BOD_RSTEN | Brown Out Reset Enable (initiated & write-protected bit) |
| 1= Enable the Brown Out "RESET" function, when the Brown Out Detector function is enable | ||
| and the detected voltage is lower than the threshold then assert a signal to reset the chip | ||
| The default value is set by flash controller user configuration register config0 bit[20] | ||
| 0= Enable the Brown Out "INTERRUPT" function, when the Brown Out Detector function is | ||
| enable and the detected voltage is lower than the threshold then assert a signal to interrupt | ||
| the MCU Cortex-M0 | ||
| When the BOD_EN is enabled and the interrupt is assert, the interrupt will keep till to the | ||
| BOD_EN set to "0". The interrupt for CPU can be blocked by disable the NVIC in CPU for BOD | ||
| interrupt or disable the interrupt source by disable the BOD_EN and then re-enable the BOD_EN | ||
| function if the BOD function is required | ||
| [4] | BOD_INTF | Brown Out Detector Interrupt Flag |
| 1= When Brown Out Detector detects the VDD is dropped through the voltage of BOD_VL setting | ||
| or the VDD is raised up through the voltage of BOD_VL setting, this bit is set to "1" and the | ||
| brown out interrupt is requested if brown out interrupt is enabled. | ||
| 0= Brown Out Detector does not detect any voltage draft at VDD down through or up through the | ||
| voltage of BOD_VL setting. | ||
| [6] | BOD_OUT | The status for Brown Out Detector output state |
| 1= Brown Out Detector status output is 1, the detected voltage is lower than BOD_VL setting. If | ||
| the BOD_EN is "0"(disabled), this bit always response "0" | ||
| 0= Brown Out Detector status output is 0, the detected voltage is higher than BOD_VL setting |
Definition at line 2156 of file NUC029FAE.h.
| __IO uint32_t SYS_T::IPRSTC1 |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | CHIP_RST | CHIP one shot reset. |
| Set this bit will reset the CHIP, including CPU kernel and all peripherals, and this bit will | ||
| automatically return to "0" after the 2 clock cycles. | ||
| The CHIP_RST is same as the POR reset , all the chip module is reset and the chip setting from | ||
| flash are also reload | ||
| This bit is the protected bit, program this need an open lock sequence, write "59h","16h","88h" to | ||
| address 0x5000_0100 to un-lock this bit. Reference the register REGWRPROT at address SYS_BA | ||
| + 0x100 | ||
| 0= Normal | ||
| 1= Reset CHIP | ||
| [1] | CPU_RST | CPU kernel one shot reset. |
| Set this bit will reset the Cortex-M0 CPU kernel and Flash memory controller (FMC). This bit will | ||
| automatically return to "0" after the 2 clock cycles | ||
| This bit is the protected bit, program this need an open lock sequence, write "59h","16h","88h" to | ||
| address 0x5000_0100 to un-lock this bit. Reference the register REGWRPROT at address SYS_BA | ||
| + 0x100 | ||
| 0= Normal | ||
| 1= Reset CPU |
Definition at line 2073 of file NUC029FAE.h.
| __IO uint32_t SYS_T::IPRSTC2 |
| Bits | Field | Descriptions |
|---|---|---|
| [1] | GPIO_RST | GPIO (P0~P4) controller Reset |
| 0= GPIO controller normal operation | ||
| 1= GPIO controller reset | ||
| [2] | TMR0_RST | Timer0 controller Reset |
| 0= Timer0 controller normal operation | ||
| 1= Timer0 controller reset | ||
| [3] | TMR1_RST | Timer1 controller Reset |
| 0= Timer1 controller normal operation | ||
| 1= Timer1 controller reset | ||
| [8] | I2C_RST | I2C controller Reset |
| 0= I2C controller normal operation | ||
| 1= I2C controller reset | ||
| [12] | SPI_RST | SPI controller Reset |
| 0= SPI controller normal operation | ||
| 1= SPI controller reset | ||
| [16] | UART_RST | UART controller Reset |
| 0= UART controller Normal operation | ||
| 1= UART controller reset | ||
| [20] | PWM_RST | PWM controller Reset |
| 0= PWM controller normal operation | ||
| 1= PWM controller reset | ||
| [22] | ACMP_RST | ACMP controller Reset |
| 0= ACMP controller normal operation | ||
| 1= ACMP controller reset | ||
| [28] | ADC_RST | ADC Controller Reset |
| 0= ADC controller normal operation | ||
| 1= ADC controller reset |
Definition at line 2110 of file NUC029FAE.h.
| __IO uint32_t SYS_T::IRCTRIMCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | TRIM_SEL | Trim Frequency Selection |
| This bit is to enable the HIRC auto trim. | ||
| When setting this bit to "1", the HFIRC auto trim function will trim HIRC to 22.1184 MHz | ||
| automatically based on the 32.768 KHz reference clock. | ||
| During auto trim operation, if 32.768 KHz clock error is detected or trim retry limitation | ||
| count reached, this field will be cleared to "0" automatically. | ||
| 0 = HIRC auto trim function Disabled. | ||
| 1 = HIRC auto trim function Enabled and HIRC trimmed to 22.1184 MHz. | ||
| [5:4] | TRIM_LOOP | Trim Calculation Loop |
| This field defines trim value calculation based on the number of 32.768 KHz clock. | ||
| This field also defines how many times the auto trim circuit will try to update the | ||
| HIRC trim value before the frequency of HIRC is locked. | ||
| Once the HIRC is locked, the internal trim value update counter will be reset | ||
| If the trim value update counter reaches this limitation value and frequency of HIRC | ||
| is still not locked, the auto trim operation will be disabled and TRIM_SEL will be cleared to "0". | ||
| 00 = Trim value calculation is based on average difference in 4 32.768 KHz clock and trim retry count limitation is 64. | ||
| 01 = Trim value calculation is based on average difference in 8 32.768 KHz clock and trim retry count limitation is 128. | ||
| 10 = Trim value calculation is based on average difference in 16 32.768 KHz clock and trim retry count limitation is 256. | ||
| 11 = Trim value calculation is based on average difference in 32 32.768 KHz clock and trim retry count limitation is 512. |
Definition at line 2501 of file NUC029FAE.h.
| __IO uint32_t SYS_T::IRCTRIMIER |
| Bits | Field | Descriptions |
|---|---|---|
| [1] | TRIM_FAIL_IEN | Trim Failure Interrupt Enable |
| This bit controls if an interrupt will be triggered while HIRC trim value update limitation | ||
| count is reached and HIRC frequency is still not locked on target frequency set by TRIM_SEL. | ||
| If this bit is high and TRIM_FAIL_INT is set during auto trim operation, an interrupt will be | ||
| triggered to notify that HFIRC trim value update limitation count is reached. | ||
| 0 = TRIM_FAIL_INT status Disabled to trigger an interrupt to CPU. | ||
| 1 = TRIM_FAIL_INT status Enabled to trigger an interrupt to CPU. | ||
| [2] | 32K_ERR_IEN | 32.768 KHz Clock Error Interrupt Enable |
| This bit controls if CPU could get an interrupt while 32.768 KHz clock is inaccurate during | ||
| auto trim operation. | ||
| If this bit is high, and 32K_ERR_INT is set during auto trim operation, an interrupt will be triggered | ||
| to notify the 32.768 KHz clock frequency is inaccurate. | ||
| 0 = 32K_ERR_INT status Disabled to trigger an interrupt to CPU. | ||
| 1 = 32K_ERR_INT status Enabled to trigger an interrupt to CPU. |
Definition at line 2525 of file NUC029FAE.h.
| __IO uint32_t SYS_T::IRCTRIMISR |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | FREQ_LOCK | HIRC Frequency Lock Status |
| 1 = This bit indicates the HIRC frequency lock. | ||
| [1] | TRIM_FAIL_INT | Trim Failure Interrupt Status |
| This bit indicates that HIRC trim value update limitation count reached and HIRC | ||
| clock frequency still doesn't lock. Once this bit is set, the auto trim operation | ||
| stopped and TRIM_SEL will be cleared to "0" by hardware automatically. | ||
| If this bit is set and TRIM_FAIL_IEN is high, an interrupt will be triggered to notify | ||
| that HIRC trim value update limitation count was reached. Write "1" to clear this to zero. | ||
| 0 = Trim value update limitation count is not reached. | ||
| 1 = Trim value update limitation count is reached and HFIRC frequency is still not locked. | ||
| [2] | 32K_ERR_INT | 32.768 KHz Clock Error Interrupt Status |
| This bit indicates that 32.768 KHz clock frequency is inaccuracy. Once this bit is set, the | ||
| auto trim operation stopped and TRIM_SEL will be cleared to "0" by hardware automatically. | ||
| If this bit is set and 32K_ERR_IEN is high, an interrupt will be triggered to notify the | ||
| 32.768 KHz clock frequency is inaccuracy. Write "1" to clear this to zero. | ||
| 0 = 32.768 KHz clock frequency is accuracy. | ||
| 1 = 32.768 KHz clock frequency is inaccuracy. |
Definition at line 2552 of file NUC029FAE.h.
| __IO uint32_t SYS_T::P0_MFP |
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | P0_MFP | P0 multiple function Selection |
| The pin function of P0 is depending on P0_MFP and P0_ALT. | ||
| Refer to P0_ALT descriptions in detail. | ||
| [8] | P0_ALT0 | P0.0 alternate function Selection |
| The pin function of P0.0 is depend on P0_MFP[0] and P0_ALT[0]. | ||
| P0_ALT[0]P0_MFP[0] = P0.0 Function | ||
| 00 = P0.0 | ||
| 10 = CTS(UART) | ||
| 11 = TX(UART) | ||
| [9] | P0_ALT1 | P0.1 alternate function Selection |
| The pin function of P0.1 is depend on P0_MFP[1] and P0_ALT[1]. | ||
| P0_ALT[1] P0_MFP[1] = P0.1 Function | ||
| 00 = P0.1 | ||
| 01 = SPISS (SPI) | ||
| 10 = RTS(UART) | ||
| 11 = RX(UART) | ||
| [12] | P0_ALT4 | P0.4 alternate function Selection |
| The pin function of P0.4 is depend on P0_MFP[4] and P0_ALT[4]. | ||
| P0_ALT[4] P0_MFP[4] = P0.4 Function | ||
| 00 = P0.4 | ||
| 01 = Reserved | ||
| 10 = SPISS(SPI) | ||
| 11 = PWM5(PWM) | ||
| [13] | P0_ALT5 | P0.5 alternate function Selection |
| The pin function of P0.5 is depend on P0_MFP[5] and P0_ALT[5]. | ||
| P0_ALT[5] P0_MFP[5] = P0.5 Function | ||
| 00 = P0.5 | ||
| 01 = Reserved | ||
| 10 = MOSI(SPI) | ||
| 11 = Reserved | ||
| [14] | P0_ALT6 | P0.6 alternate function Selection |
| The pin function of P0.6 is depend on P0_MFP[6] and P0_ALT[6]. | ||
| P0_ALT[6] P0_MFP[6] = P0.6 Function | ||
| 00 = P0.6 | ||
| 01 = Reserved | ||
| 10 = MISO(SPI) | ||
| 11 = Reserved | ||
| [15] | P0_ALT7 | P0.7 alternate function Selection |
| The pin function of P0.7 is depend on P0_MFP[7] and P0_ALT[7]. | ||
| P0_ALT[7] P0_MFP[7] = P0.7 Function | ||
| 00 = P0.7 | ||
| 01 = Reserved | ||
| 10 = SPICLK(SPI) | ||
| 11 = Reserved | ||
| [23:16] | P0_TYPEn | P0[7:0] input Schmitt Trigger function Enable |
| 1= P0[7:0] I/O input Schmitt Trigger function enable | ||
| 0= P0[7:0] I/O input Schmitt Trigger function disable |
Definition at line 2221 of file NUC029FAE.h.
| __IO uint32_t SYS_T::P1_MFP |
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | P1_MFP | P1 multiple function Selection |
| The pin function of P1 is depending on P1_MFP and P1_ALT. | ||
| Refer to P1_ALT descriptions in detail. | ||
| [8] | P1_ALT0 | P1.0 alternate function Selection |
| The pin function of P1.0 is depend on P1_MFP[0] and P1_ALT[0]. | ||
| P1_ALT[0] P1_MFP[0] = P1.0 Function | ||
| 00 = P1.0 | ||
| 01 = AIN1(ADC) | ||
| 10 = Reserved | ||
| 11 = CPP0 (ACMP) | ||
| [10] | P1_ALT2 | P1.2 alternate function Selection |
| The pin function of P1.2 is depend on P1_MFP[2] and P1_ALT[2]. | ||
| P1_ALT[2] P1_MFP[2] = P1.2 Function | ||
| 00 = P1.2 | ||
| 01 = AIN2(ADC) | ||
| 10 = RX(UART) | ||
| 11 = CPP0 (ACMP) | ||
| [11] | P1_ALT3 | P1.3 alternate function Selection |
| The pin function of P1.3 is depend on P1_MFP[3] and P1_ALT[3]. | ||
| P1_ALT[3] P1_MFP[3] = P1.3 Function | ||
| 00 = P1.3 | ||
| 01 = AIN3(ADC) | ||
| 10 = TX(UART) | ||
| 11 = CPP0 (ACMP) | ||
| [12] | P1_ALT4 | P1.4 alternate function Selection |
| The pin function of P1.4 is depend on P1_MFP[4] and P1_ALT[4]. | ||
| P1_ALT[4] P1_MFP[4] = P1.4 Function | ||
| 00 = P1.4 | ||
| 01 = AIN4(ADC) | ||
| 10 = Reserved | ||
| 11 = CPN0 (CMP) | ||
| [13] | P1_ALT5 | P1.5 alternate function Selection |
| The pin function of P1.5 is depend on P1_MFP[5] and P1_ALT[5]. | ||
| P1_ALT[5] P1_MFP[5] = P1.5 Function | ||
| 00 = P1.5 | ||
| 01 = AIN5(ADC) | ||
| 10 = Reserved | ||
| 11 = CPP0 (CMP) | ||
| [23:16] | P1_TYPEn | P1[7:0] input Schmitt Trigger function Enable |
| 1= P1[7:0] I/O input Schmitt Trigger function enable | ||
| 0= P1[7:0] I/O input Schmitt Trigger function disable |
Definition at line 2272 of file NUC029FAE.h.
| __IO uint32_t SYS_T::P2_MFP |
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | P2_MFP | P2 multiple function Selection |
| The pin function of P2 is depending on P2_MFP and P2_ALT. | ||
| Refer to P2_ALT descriptions in detail. | ||
| [10] | P2_ALT2 | P2.2 alternate function Selection |
| The pin function of P2.2 is depend on P2_MFP[2] and P2_ALT[2]. | ||
| P2_ALT[2] P2_MFP[2] = P2.2 Function | ||
| 00 = P2.2 | ||
| 01 = Reserved | ||
| 10 = PWM0(PWM) | ||
| 11 = Reserved | ||
| [11] | P2_ALT3 | P2.3 alternate function Selection |
| The pin function of P2.3 is depend on P2_MFP[3] and P2_ALT[3]. | ||
| P2_ALT[3] P2_MFP[3] = P2.3 Function | ||
| 00 = P2.3 | ||
| 01 = Reserved | ||
| 10 = PWM1(PWM) | ||
| 11 = Reserved | ||
| [12] | P2_ALT4 | P2.4 alternate function Selection |
| The pin function of P2.4 is depend on P2_MFP[4] and P2_ALT[4]. | ||
| P2_ALT[4] P2_MFP[4] = P0.4 Function | ||
| 00 = P2.4 | ||
| 01 = Reserved | ||
| 10 = PWM2(PWM) | ||
| 11 = Reserved | ||
| [13] | P2_ALT5 | P2.5 alternate function Selection |
| The pin function of P2.5 is depend on P2_MFP[5] and P2_ALT[5]. | ||
| P2_ALT[5] P2_MFP[5] = P2.5 Function | ||
| 00 = P2.5 | ||
| 01 = Reserved | ||
| 10 = PWM3(PWM) | ||
| 11 = Reserved | ||
| [14] | P2_ALT6 | P2.6 alternate function Selection |
| The pin function of P2.6 is depend on P2_MFP[6] and P2_ALT[6]. | ||
| P2_ALT[6] P2_MFP[6] = P2.6 Function | ||
| 00 = P2.6 | ||
| 01 = Reserved | ||
| 10 = PWM4(PWM) | ||
| 11 = CPO1 | ||
| [23:16] | P2_TYPEn | P2[7:0] input Schmitt Trigger function Enable |
| 1= P2[7:0] I/O input Schmitt Trigger function enable | ||
| 0= P2[7:0] I/O input Schmitt Trigger function disable |
Definition at line 2323 of file NUC029FAE.h.
| __IO uint32_t SYS_T::P3_MFP |
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | P3_MFP | P3 multiple function Selection |
| The pin function of P3 is depending on P3_MFP and P3_ALT. | ||
| Refer to P3_ALT descriptions in detail. | ||
| [8] | P3_ALT0 | P3.0 alternate function Selection |
| The pin function of P3.0 is depend on P3_MFP[0] and P3_ALT[0]. | ||
| P3_ALT[0] P3_MFP[0] = P3.0 Function | ||
| 00 = P3.0 | ||
| 01 = Reserved | ||
| 10 = CPN1 | ||
| 11 = AIN6(ADC) | ||
| [9] | P3_ALT1 | P3.1 alternate function Selection |
| The pin function of P3.1 is depend on P3_MFP[1] and P3_ALT[1]. | ||
| P3_ALT[1] P3_MFP[1] = P3.1 Function | ||
| 00 = P3.1 | ||
| 01 = Reserved | ||
| 10 = CPP1 | ||
| 11 = AIN7(ADC) | ||
| [10] | P3_ALT2 | P3.2 alternate function Selection |
| The pin function of P3.2 is depend on P3_MFP[2] and P3_ALT[2]. | ||
| P3_ALT[2] P3_MFP[2] = P3.2 Function | ||
| 00 = P3.2 | ||
| 01 = /INT0 | ||
| 10 = T0EX | ||
| 11 = STADC(ADC) | ||
| [12] | P3_ALT4 | P3.4 alternate function Selection |
| The pin function of P3.4 is depend on P3_MFP[4] and P3_ALT[4]. | ||
| P3_ALT[4] P3_MFP[4] = P3.4 Function | ||
| 00 = P3.4 | ||
| 01 = T0(Timer0) | ||
| 10 = SDA(I2C) | ||
| 11 = CPP1(ACMP) | ||
| [13] | P3_ALT5 | P3.5 alternate function Selection |
| The pin function of P3.5 is depend on P3_MFP[5] and P3_ALT[5]. | ||
| P3_ALT[5] P3_MFP[5] = P3.5 Function | ||
| 00 = P3.5 | ||
| 01 = T1(Timer1) | ||
| 10 = SCL(I2C) | ||
| 11 = CPP1(ACMP) | ||
| [14] | P3_ALT6 | P3.6 alternate function Selection |
| The pin function of P3.6 is depend on P3_MFP[6] and P3_ALT[6]. | ||
| P3_ALT[6] P3_MFP[6] = P3.6 Function | ||
| 00 = P3.6 | ||
| 01 = T1EX | ||
| 10 = CKO(Clock Driver output) | ||
| 11 = CPO0(CMP) | ||
| [23:16] | P3_TYPEn | P3[7:0] input Schmitt Trigger function Enable |
| 1= P3[7:0] I/O input Schmitt Trigger function enable | ||
| 0= P3[7:0] I/O input Schmitt Trigger function disable | ||
| [24] | P32CPP1 | P3.2 Alternate Function Selection Extension |
| 0 = P3.2 is set by P3_ALT[2] and P3_MFP[2] | ||
| 1 = P3.2 is set to CPP1 of ACMP1 |
Definition at line 2384 of file NUC029FAE.h.
| __IO uint32_t SYS_T::P4_MFP |
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | P4_MFP | P4 multiple function Selection |
| The pin function of P4 is depending on P4_MFP and P4_ALT. | ||
| Refer to P4_ALT descriptions in detail. | ||
| [14] | P4_ALT6 | P4.6 alternate function Selection |
| The pin function of P4.6 is depend on P4_MFP[6] and P4_ALT[6]. | ||
| P4_ALT[6] P4_MFP[6] = P4.6 Function | ||
| 00 = P4.6 | ||
| 01 = ICE_CLK(ICE) | ||
| 1x = Reserved | ||
| [15] | P4_ALT7 | P4.7 alternate function Selection |
| The pin function of P4.7 is depend on P4_MFP[7] and P4_ALT[7]. | ||
| P4_ALT[7] P4_MFP[7] = P4.7 Function | ||
| 00 = P4.7 | ||
| 01 = ICE_DAT(ICE) | ||
| 1x = Reserved | ||
| [23:16] | P4_TYPEn | P4[7:0] input Schmitt Trigger function Enable |
| 1= P4[7:0] I/O input Schmitt Trigger function enable | ||
| 0= P4[7:0] I/O input Schmitt Trigger function disable |
Definition at line 2412 of file NUC029FAE.h.
| __IO uint32_t SYS_T::P5_MFP |
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | P5_MFP | P5 multiple function Selection |
| The pin function of P5 is depending on P5_MFP and P5_ALT. | ||
| Refer to P5_ALT descriptions in detail. | ||
| [8] | P5_ALT0 | P5.0 alternate function Selection |
| The pin function of P5.0 is depend on P5_MFP[0] and P5_ALT[0]. | ||
| P5_ALT[0] P5_MFP[0] = P5.0 Function | ||
| 00 = P5.0 | ||
| 01 = XTAL1 | ||
| 1x = Reserved | ||
| [9] | P5_ALT1 | P5.1 alternate function Selection |
| The pin function of P5.1 is depend on P5_MFP[1] and P5_ALT[1]. | ||
| P5_ALT[1] P5_MFP[1] = P5.1 Function | ||
| 00 = P5.1 | ||
| 01 = XTAL2 | ||
| 1x = Reserved | ||
| [10] | P5_ALT2 | P5.2 alternate function Selection |
| The pin function of P5.2 is depend on P5_MFP[2] and P5_ALT[2]. | ||
| P5_ALT[2] P5_MFP[2] = P5.2 Function | ||
| 00 = P5.2 | ||
| 01 = /INT1 | ||
| 1x = Reserved | ||
| [11] | P5_ALT3 | P5.3 alternate function Selection |
| The pin function of P5.3 is depend on P5_MFP[3] and P5_ALT[3]. | ||
| P5_ALT[3] P5_MFP[3] = P5.3 Function | ||
| 00 = P5.3 | ||
| 01 = AIN0(ADC) | ||
| 1x = Reserved | ||
| [12] | P5_ALT4 | P5.4 alternate function Selection |
| The pin function of P5.4 is depend on P5_MFP[4] and P5_ALT[4]. | ||
| P5_ALT[4] P5_MFP[4] = P5.4 Function | ||
| 00 = P5.4 | ||
| 01 = Reserved | ||
| 1x = Reserved | ||
| [13] | P5_ALT5 | P5.5 alternate function Selection |
| The pin function of P5.5 is depend on P5_MFP[5] and P5_ALT[5]. | ||
| P5_ALT[5] P5_MFP[5] = P5.5 Function | ||
| 00 = P5.5 | ||
| 01 = Reserved | ||
| 1x = Reserved | ||
| [23:16] | P5_TYPEn | P5[7:0] input Schmitt Trigger function Enable |
| 1= P5[7:0] I/O input Schmitt Trigger function enable | ||
| 0= P5[7:0] I/O input Schmitt Trigger function disable |
Definition at line 2464 of file NUC029FAE.h.
| __I uint32_t SYS_T::PDID |
| Bits | Field | Descriptions |
|---|---|---|
| [31:0] | PDID | This register reflects device part number code. S/W can read this register to identify which device is |
| used. |
Definition at line 2008 of file NUC029FAE.h.
| __IO uint32_t SYS_T::RegLockAddr |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | RegUnLock | Register Write-Protected Disable index (Read only) |
| 1 = Protected registers are Unlock. | ||
| 0 = Protected registers are locked. Any write to the target register is ignored. | ||
| The Protected registers are: | ||
| IPRSTC1 0x5000_0008 None | ||
| BODCR 0x5000_0018 None | ||
| LDOCR 0x5000_001C None | ||
| PORCR 0x5000_0024 None | ||
| PWRCON 0x5000_0200 bit[6] is not protected for power, wake-up interrupt clear | ||
| APBCLK bit[0] 0x5000_0208 bit[0] is watch dog clock enable | ||
| CLKSEL0 0x5000_0210 HCLK and CPU STCLK clock source select | ||
| CLK_SEL1 bit[1:0] 0x5000_0214 Watch dog clock source select | ||
| ISPCON 0x5000_C000 Flash ISP Control register | ||
| WTCR 0x4000_4000 None | ||
| NMI_SEL[8] - address 0x5000_380 (NMI interrupt source enable) |
Definition at line 2585 of file NUC029FAE.h.
| uint32_t SYS_T::RESERVED0[2] |
| uint32_t SYS_T::RESERVED1[5] |
| uint32_t SYS_T::RESERVED3[14] |
| uint32_t SYS_T::RESERVED4[29] |
| __IO uint32_t SYS_T::RSTSRC |
| Bits | Field | Descriptions |
|---|---|---|
| [31:8] | Reserved | Reserved |
| [7] | RSTS_CPU | The RSTS_CPU flag is set by hardware if software writes CPU_RST (IPRSTC1[1]) 1 to reset Cortex-M0 CPU kernel and Flash memory controller (FMC). |
| 1 = The Cortex-M0 CPU kernel and FMC are reset by software setting CPU_RST to 1. | ||
| 0 = No reset from CPU | ||
| Software can write 1 to clear this bit to zero. | ||
| [6] | Reserved | Reserved |
| [5] | RSTS_MCU | The RSTS_MCU flag is set by the "reset signal" from the MCU Cortex_M0 kernel to indicate the previous reset source. |
| 1= The MCU Cortex_M0 had issued the reset signal to reset the system by software writing 1 to bit SYSRESTREQ(AIRCR[2], Application Interrupt and Reset Control Register) in system control registers of Cortex_M0 kernel. | ||
| 0= No reset from MCU | ||
| This bit is cleared by writing 1 to itself. | ||
| [4] | RSTS_BOD | The RSTS_BOD flag is set by the "reset signal" from the Brown-Out Detector to indicate the previous reset source. |
| 1= The Brown-Out Detector module had issued the reset signal to reset the system. | ||
| 0= No reset from BOD | ||
| Software can write 1 to clear this bit to zero. | ||
| [3] | Reserved | Reserved |
| [2] | RSTS_WDT | The RSTS_WDT flag is set by the "reset signal" from the Watchdog timer to indicate the previous reset source. |
| 1= The Watchdog timer had issued the reset signal to reset the system. | ||
| 0= No reset from Watchdog timer | ||
| Software can write 1 to clear this bit to zero. | ||
| [1] | RSTS_RESET | The RSTS_RESET flag is set by the "reset signal" from the /RESET pin to indicate the previous reset source. |
| 1= The Pin /RESET had issued the reset signal to reset the system. | ||
| 0= No reset from Pin /RESET | ||
| Software can write 1 to clear this bit to zero. | ||
| [0] | RSTS_POR | The RSTS_POR flag is set by the "reset signal", which is from the Power-On Reset (POR) module or bit CHIP_RST (IPRSTC1[0]) is set, to indicate the previous reset source. |
| 1= The Power-On-Reset (POR) or CHIP_RST had issued the reset signal to reset the system. | ||
| 0= No reset from POR or CHIP_RST | ||
| Software can write 1 to clear this bit to zero. |
Definition at line 2045 of file NUC029FAE.h.
1.8.15