| Nano100AN Series BSP V3.02.002 The Board Support Package for Nano100AN Series

adc.h
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1 /**************************************************************************/
12 #ifndef __ADC_H__
13 #define __ADC_H__
14
15 #ifdef __cplusplus
16 extern "C"
17 {
18 #endif
19
20
33 #define ADC_CH_0_MASK (1UL << 0)
34 #define ADC_CH_1_MASK (1UL << 1)
35 #define ADC_CH_2_MASK (1UL << 2)
36 #define ADC_CH_3_MASK (1UL << 3)
37 #define ADC_CH_4_MASK (1UL << 4)
38 #define ADC_CH_5_MASK (1UL << 5)
39 #define ADC_CH_6_MASK (1UL << 6)
40 #define ADC_CH_7_MASK (1UL << 7)
41 #define ADC_CH_10_MASK (1UL << 10)
42 #define ADC_CH10_VTEMP (0UL)
43 #define ADC_CH10_AVDD (2 << ADC_CHEN_CH10SEL_Pos)
44 #define ADC_CH10_AVSS (3 << ADC_CHEN_CH10SEL_Pos)
45 #define ADC_CHEN_Msk (0x7FF)
46 #define ADC_PDMADATA_AD_PDMA_Msk (0xFFF)
47 #define ADC_CMP_LESS_THAN (0UL)
48 #define ADC_CMP_GREATER_OR_EQUAL_TO (ADC_CMPR0_CMPCOND_Msk)
49 #define ADC_TRIGGER_BY_EXT_PIN (1UL)
50 #define ADC_LOW_LEVEL_TRIGGER (0UL << ADC_CR_TRGCOND_Pos)
51 #define ADC_HIGH_LEVEL_TRIGGER (1UL << ADC_CR_TRGCOND_Pos)
52 #define ADC_FALLING_EDGE_TRIGGER (2UL << ADC_CR_TRGCOND_Pos)
53 #define ADC_RISING_EDGE_TRIGGER (3UL << ADC_CR_TRGCOND_Pos)
54 #define ADC_ADF_INT (ADC_SR_ADF_Msk)
55 #define ADC_CMP0_INT (ADC_SR_CMPF0_Msk)
56 #define ADC_CMP1_INT (ADC_SR_CMPF1_Msk)
57 #define ADC_OPERATION_MODE_SINGLE (0UL << ADC_CR_ADMD_Pos)
58 #define ADC_OPERATION_MODE_SINGLE_CYCLE (2UL << ADC_CR_ADMD_Pos)
59 #define ADC_OPERATION_MODE_CONTINUOUS (3UL << ADC_CR_ADMD_Pos)
60 #define ADC_REFSEL_POWER (0UL << ADC_CR_REFSEL_Pos)
61 #define ADC_REFSEL_INT_VREF (1UL << ADC_CR_REFSEL_Pos)
62 #define ADC_REFSEL_VREF (2UL << ADC_CR_REFSEL_Pos)
63 #define ADC_REFSEL_CH7 (3UL << ADC_CR_REFSEL_Pos)
65 /* end of group NANO100_ADC_EXPORTED_CONSTANTS */
66
67
79 #define ADC_GET_CONVERSION_DATA(adc, u32ChNum) (ADC->RESULT[u32ChNum] & ADC_RESULT_RSLT_Msk)
80
91 #define ADC_CONFIG_CH10(adc, u32Source) (ADC->CHEN = ((adc)->CHEN & ~ADC_CHEN_CHEN10_Msk) | (u32Source))
92
103 #define ADC_GET_INT_FLAG(adc, u32Mask) (ADC->SR & (u32Mask))
104
115 #define ADC_CLR_INT_FLAG(adc, u32Mask) (ADC->SR = (ADC->SR & ~(ADC_SR_ADF_Msk | \
116 ADC_SR_CMPF0_Msk | \
117 ADC_SR_CMPF1_Msk)) | (u32Mask))
118
127 #define ADC_IS_BUSY(adc) (ADC->SR & ADC_SR_BUSY_Msk ? 1 : 0)
128
138 #define ADC_IS_DATA_OVERRUN(adc, u32ChNum) ((ADC->SR & ((1 << u32ChNum) << ADC_SR_OVERRUN_Pos)) ? 1 : 0)
139
149 #define ADC_IS_DATA_VALID(adc, u32ChNum) ((ADC->SR & ((1 << u32ChNum) << ADC_SR_VALID_Pos)) ? 1 : 0)
150
157 #define ADC_POWER_DOWN(adc) (ADC->CR &= ~ADC_CR_ADEN_Msk)
158
165 #define ADC_POWER_ON(adc) (ADC->CR |= ADC_CR_ADEN_Msk)
166
182 #define ADC_ENABLE_CMP0(adc, \
183 u32ChNum, \
184 u32Condition, \
185 u32Data, \
186 u32MatchCount) (ADC->CMPR0 = ((u32ChNum) << ADC_CMPR0_CMPCH_Pos) | \
187 (u32Condition) | \
188 ((u32Data) << ADC_CMPR0_CMPD_Pos) | \
189 (((u32MatchCount) - 1) << ADC_CMPR0_CMPMATCNT_Pos) |\
190 ADC_CMPR0_CMPEN_Msk)
191
198 #define ADC_DISABLE_CMP0(adc) (ADC->CMPR0 = 0)
199
215 #define ADC_ENABLE_CMP1(adc, \
216 u32ChNum, \
217 u32Condition, \
218 u32Data, \
219 u32MatchCount) (ADC->CMPR1 = ((u32ChNum) << ADC_CMPR1_CMPCH_Pos) | \
220 (u32Condition) | \
221 ((u32Data) << ADC_CMPR1_CMPD_Pos) | \
222 ((u32MatchCount - 1) << ADC_CMPR1_CMPMATCNT_Pos) |\
223 ADC_CMPR1_CMPEN_Msk)
224
231 #define ADC_DISABLE_CMP1(adc) (ADC->CMPR1 = 0)
232
240 #define ADC_SET_INPUT_CHANNEL(adc, u32Mask) (ADC->CHEN = (ADC->CHEN & ~ADC_CHEN_Msk) | (u32Mask))
241
248 #define ADC_START_CONV(adc) (ADC->CR |= ADC_CR_ADST_Msk)
249
256 #define ADC_STOP_CONV(adc) (ADC->CR &= ~ADC_CR_ADST_Msk)
257
258
270 #define ADC_SET_REF_VOLTAGE(adc, u32Ref) (ADC->CR = (ADC->CR & ~ADC_CR_REFSEL_Msk) | u32Ref)
271
278 #define ADC_ENABLE_PDMA(adc) (ADC->CR |= ADC_CR_PTEN_Msk)
279
286 #define ADC_DISABLE_PDMA(adc) (ADC->CR &= ~ADC_CR_PTEN_Msk)
287
294 #define ADC_GET_PDMA_DATA(adc) (ADC->PDMA & ADC_PDMADATA_AD_PDMA_Msk)
295
296 void ADC_Open(ADC_T *adc,
297 uint32_t u32InputMode,
298 uint32_t u32OpMode,
299 uint32_t u32ChMask);
300 void ADC_Close(ADC_T *adc);
301 void ADC_EnableHWTrigger(ADC_T *adc,
302 uint32_t u32Source,
303 uint32_t u32Param);
304 void ADC_DisableHWTrigger(ADC_T *adc);
305 void ADC_EnableTimerTrigger(ADC_T *adc,
306 uint32_t u32Source,
307 uint32_t u32PDMACnt);
308 void ADC_DisableTimerTrigger(ADC_T *adc);
309 void ADC_SetExtraSampleTime(ADC_T *adc,
310 uint32_t u32ChNum,
311 uint32_t u32SampleTime);
312 void ADC_EnableInt(ADC_T *adc, uint32_t u32Mask);
313 void ADC_DisableInt(ADC_T *adc, uint32_t u32Mask);
314
315
316 /* end of group NANO100_ADC_EXPORTED_FUNCTIONS */
318 /* end of group NANO100_ADC_Driver */
320 /* end of group NANO100_Device_Driver */
322
323 #ifdef __cplusplus
324 }
325 #endif
326
327 #endif //__ADC_H__
328
329 /*** (C) COPYRIGHT 2013-2014 Nuvoton Technology Corp. ***/
ADC_EnableTimerTrigger
void ADC_EnableTimerTrigger(ADC_T *adc, uint32_t u32Source, uint32_t u32PDMACnt)
Config and enable timer trigger.
Definition: adc.c:103
ADC_Close
void ADC_Close(ADC_T *adc)
Disable ADC module.
Definition: adc.c:55
ADC_Open
void ADC_Open(ADC_T *adc, uint32_t u32InputMode, uint32_t u32OpMode, uint32_t u32ChMask)
This API configures ADC module to be ready for convert the input from selected channel.
Definition: adc.c:39
ADC_DisableHWTrigger
void ADC_DisableHWTrigger(ADC_T *adc)
Disable hardware trigger ADC function.
Definition: adc.c:90
ADC_DisableTimerTrigger
void ADC_DisableTimerTrigger(ADC_T *adc)
Disable timer trigger ADC function.
Definition: adc.c:120
ADC_T
Definition: Nano100Series.h:159
ADC_EnableInt
void ADC_EnableInt(ADC_T *adc, uint32_t u32Mask)
Enable the interrupt(s) selected by u32Mask parameter.
Definition: adc.c:155
ADC_EnableHWTrigger
void ADC_EnableHWTrigger(ADC_T *adc, uint32_t u32Source, uint32_t u32Param)
Configure the hardware trigger condition and enable hardware trigger.
Definition: adc.c:76
ADC_SetExtraSampleTime
void ADC_SetExtraSampleTime(ADC_T *adc, uint32_t u32ChNum, uint32_t u32SampleTime)
Configure the extend sampling counter.
Definition: adc.c:134
ADC_DisableInt
void ADC_DisableInt(ADC_T *adc, uint32_t u32Mask)
Disable the interrupt(s) selected by u32Mask parameter.
Definition: adc.c:178