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Nano100AN Series BSP
V3.02.002
The Board Support Package for Nano100AN Series
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Nano100 series peripheral access layer header file. This file contains all the peripheral register's definitions, bits definitions and memory mapping for NuMicro Nano100 series MCU. More...
#include "core_cm0.h"#include "system_Nano100Series.h"#include <stdint.h>#include "sys.h"#include "clk.h"#include "adc.h"#include "fmc.h"#include "ebi.h"#include "gpio.h"#include "i2c.h"#include "pdma.h"#include "pwm.h"#include "rtc.h"#include "sc.h"#include "spi.h"#include "timer.h"#include "uart.h"#include "usbd.h"#include "wdt.h"#include "i2s.h"Go to the source code of this file.
Data Structures | |
| struct | ADC_T |
| struct | CLK_T |
| struct | DMA_GCR_T |
| struct | PDMA_T |
| struct | VDMA_T |
| struct | EBI_T |
| struct | FMC_T |
| struct | SYS_T |
| struct | GPIO_T |
| struct | GP_DB_T |
| struct | I2C_T |
| struct | I2S_T |
| struct | PWM_T |
| struct | RTC_T |
| struct | SC_T |
| struct | SPI_T |
| struct | TIMER_T |
| struct | UART_T |
| struct | USBD_EP_T |
| USBD endpoints register. More... | |
| struct | USBD_T |
| struct | WDT_T |
Macros | |
| #define | __CM0_REV 0x0201 |
| #define | __NVIC_PRIO_BITS 2 |
| #define | __Vendor_SysTickConfig 0 |
| #define | __MPU_PRESENT 0 |
| #define | __FPU_PRESENT 0 |
| #define | FLASH_BASE ((uint32_t)0x00000000) |
| Flash base address. More... | |
| #define | SRAM_BASE ((uint32_t)0x20000000) |
| SRAM base address. More... | |
| #define | APB1PERIPH_BASE ((uint32_t)0x40000000) |
| APB1 base address. More... | |
| #define | APB2PERIPH_BASE ((uint32_t)0x40100000) |
| APB2 base address. More... | |
| #define | AHBPERIPH_BASE ((uint32_t)0x50000000) |
| AHB base address. More... | |
| #define | WDT_BASE (APB1PERIPH_BASE + 0x04000) |
| WDT register base address. More... | |
| #define | RTC_BASE (APB1PERIPH_BASE + 0x08000) |
| RTC register base address. More... | |
| #define | TIMER0_BASE (APB1PERIPH_BASE + 0x10000) |
| TIMER0 register base address. More... | |
| #define | TIMER1_BASE (APB1PERIPH_BASE + 0x10100) |
| TIMER1 register base address. More... | |
| #define | I2C0_BASE (APB1PERIPH_BASE + 0x20000) |
| I2C0 register base address. More... | |
| #define | SPI0_BASE (APB1PERIPH_BASE + 0x30000) |
| SPI0 register base address. More... | |
| #define | PWM0_BASE (APB1PERIPH_BASE + 0x40000) |
| PWM0 register base address. More... | |
| #define | UART0_BASE (APB1PERIPH_BASE + 0x50000) |
| UART0 register base address. More... | |
| #define | SPI2_BASE (APB1PERIPH_BASE + 0xD0000) |
| SPI2 register base address. More... | |
| #define | ADC_BASE (APB1PERIPH_BASE + 0xE0000) |
| ADC register base address. More... | |
| #define | TIMER2_BASE (APB2PERIPH_BASE + 0x10000) |
| TIMER2 register base address. More... | |
| #define | TIMER3_BASE (APB2PERIPH_BASE + 0x10100) |
| TIMER3 register base address. More... | |
| #define | I2C1_BASE (APB2PERIPH_BASE + 0x20000) |
| I2C1 register base address. More... | |
| #define | SPI1_BASE (APB2PERIPH_BASE + 0x30000) |
| SPI1 register base address. More... | |
| #define | PWM1_BASE (APB2PERIPH_BASE + 0x40000) |
| PWM1 register base address. More... | |
| #define | UART1_BASE (APB2PERIPH_BASE + 0x50000) |
| UART1 register base address. More... | |
| #define | USBD_BASE (APB1PERIPH_BASE + 0x60000) |
| USBD register base address. More... | |
| #define | SC0_BASE (APB2PERIPH_BASE + 0x90000) |
| SC0 register base address. More... | |
| #define | I2S_BASE (APB2PERIPH_BASE + 0xA0000) |
| I2S register base address. More... | |
| #define | SC1_BASE (APB2PERIPH_BASE + 0xB0000) |
| SC1 register base address. More... | |
| #define | SYS_BASE (AHBPERIPH_BASE + 0x00000) |
| SYS register base address. More... | |
| #define | CLK_BASE (AHBPERIPH_BASE + 0x00200) |
| CLK register base address. More... | |
| #define | GPIOA_BASE (AHBPERIPH_BASE + 0x04000) |
| GPIO port A register base address. More... | |
| #define | GPIOB_BASE (AHBPERIPH_BASE + 0x04040) |
| GPIO port B register base address. More... | |
| #define | GPIOC_BASE (AHBPERIPH_BASE + 0x04080) |
| GPIO port C register base address. More... | |
| #define | GPIOD_BASE (AHBPERIPH_BASE + 0x040C0) |
| GPIO port D register base address. More... | |
| #define | GPIOE_BASE (AHBPERIPH_BASE + 0x04100) |
| GPIO port E register base address. More... | |
| #define | GPIOF_BASE (AHBPERIPH_BASE + 0x04140) |
| GPIO port F register base address. More... | |
| #define | GPIODBNCE_BASE (AHBPERIPH_BASE + 0x04180) |
| GPIO debounce register base address. More... | |
| #define | GPIO_PIN_DATA_BASE (AHBPERIPH_BASE + 0x04200) |
| GPIO bit access register base address. More... | |
| #define | VDMA_BASE (AHBPERIPH_BASE + 0x08000) |
| VDMA register base address. More... | |
| #define | PDMA1_BASE (AHBPERIPH_BASE + 0x08100) |
| PDMA1 register base address. More... | |
| #define | PDMA2_BASE (AHBPERIPH_BASE + 0x08200) |
| PDMA2 register base address. More... | |
| #define | PDMA3_BASE (AHBPERIPH_BASE + 0x08300) |
| PDMA3 register base address. More... | |
| #define | PDMA4_BASE (AHBPERIPH_BASE + 0x08400) |
| PDMA4 register base address. More... | |
| #define | PDMAGCR_BASE (AHBPERIPH_BASE + 0x08F00) |
| PDMA GCR register base address. More... | |
| #define | FMC_BASE (AHBPERIPH_BASE + 0x0C000) |
| FMC register base address. More... | |
| #define | EBI_BASE (AHBPERIPH_BASE + 0x10000) |
| EBI register base address. More... | |
| #define | WDT ((WDT_T *) WDT_BASE) |
| Pointer to WDT register structure. More... | |
| #define | RTC ((RTC_T *) RTC_BASE) |
| Pointer to RTC register structure. More... | |
| #define | TIMER0 ((TIMER_T *) TIMER0_BASE) |
| Pointer to TIMER0 register structure. More... | |
| #define | TIMER1 ((TIMER_T *) TIMER1_BASE) |
| Pointer to TIMER1 register structure. More... | |
| #define | TIMER2 ((TIMER_T *) TIMER2_BASE) |
| Pointer to TIMER2 register structure. More... | |
| #define | TIMER3 ((TIMER_T *) TIMER3_BASE) |
| Pointer to TIMER3 register structure. More... | |
| #define | I2C0 ((I2C_T *) I2C0_BASE) |
| Pointer to I2C0 register structure. More... | |
| #define | I2C1 ((I2C_T *) I2C1_BASE) |
| Pointer to I2C1 register structure. More... | |
| #define | SPI0 ((SPI_T *) SPI0_BASE) |
| Pointer to SPI0 register structure. More... | |
| #define | SPI1 ((SPI_T *) SPI1_BASE) |
| Pointer to SPI1 register structure. More... | |
| #define | SPI2 ((SPI_T *) SPI2_BASE) |
| Pointer to SPI2 register structure. More... | |
| #define | PWM0 ((PWM_T *) PWM0_BASE) |
| Pointer to PWM0 register structure. More... | |
| #define | PWM1 ((PWM_T *) PWM1_BASE) |
| Pointer to PWM1 register structure. More... | |
| #define | UART0 ((UART_T *) UART0_BASE) |
| Pointer to UART0 register structure. More... | |
| #define | UART1 ((UART_T *) UART1_BASE) |
| Pointer to UART1 register structure. More... | |
| #define | ADC ((ADC_T *) ADC_BASE) |
| Pointer to ADC register structure. More... | |
| #define | SC0 ((SC_T *) SC0_BASE) |
| Pointer to SC0 register structure. More... | |
| #define | SC1 ((SC_T *) SC1_BASE) |
| Pointer to SC1 register structure. More... | |
| #define | USBD ((USBD_T *) USBD_BASE) |
| Pointer to USBD register structure. More... | |
| #define | I2S ((I2S_T *) I2S_BASE) |
| Pointer to I2S register structure. More... | |
| #define | SYS ((SYS_T *) SYS_BASE) |
| Pointer to SYS register structure. More... | |
| #define | CLK ((CLK_T *) CLK_BASE) |
| Pointer to CLK register structure. More... | |
| #define | PA ((GPIO_T *) GPIOA_BASE) |
| Pointer to GPIO port A register structure. More... | |
| #define | PB ((GPIO_T *) GPIOB_BASE) |
| Pointer to GPIO port B register structure. More... | |
| #define | PC ((GPIO_T *) GPIOC_BASE) |
| Pointer to GPIO port C register structure. More... | |
| #define | PD ((GPIO_T *) GPIOD_BASE) |
| Pointer to GPIO port D register structure. More... | |
| #define | PE ((GPIO_T *) GPIOE_BASE) |
| Pointer to GPIO port E register structure. More... | |
| #define | PF ((GPIO_T *) GPIOF_BASE) |
| Pointer to GPIO port F register structure. More... | |
| #define | GPIO ((GP_DB_T *) GPIODBNCE_BASE) |
| Pointer to GPIO debounce register structure. More... | |
| #define | VDMA ((VDMA_T *) VDMA_BASE) |
| Pointer to VDMA register structure. More... | |
| #define | PDMA1 ((PDMA_T *) PDMA1_BASE) |
| Pointer to PDMA1 register structure. More... | |
| #define | PDMA2 ((PDMA_T *) PDMA2_BASE) |
| Pointer to PDMA2 register structure. More... | |
| #define | PDMA3 ((PDMA_T *) PDMA3_BASE) |
| Pointer to PDMA3 register structure. More... | |
| #define | PDMA4 ((PDMA_T *) PDMA4_BASE) |
| Pointer to PDMA4 register structure. More... | |
| #define | PDMAGCR ((DMA_GCR_T *) PDMAGCR_BASE) |
| Pointer to PDMA global control register structure. More... | |
| #define | FMC ((FMC_T *) FMC_BASE) |
| Pointer to FMC register structure. More... | |
| #define | EBI ((EBI_T *) EBI_BASE) |
| Pointer to EBI register structure. More... | |
| #define | M8(addr) (*((vu8 *) (addr))) |
| Get a 8-bit unsigned value from specified address. More... | |
| #define | M16(addr) (*((vu16 *) (addr))) |
| Get a 16-bit unsigned value from specified address. More... | |
| #define | M32(addr) (*((vu32 *) (addr))) |
| Get a 32-bit unsigned value from specified address. More... | |
| #define | outpw(port, value) *((volatile unsigned int *)(port)) = value |
| Set a 32-bit unsigned value to specified I/O port. More... | |
| #define | inpw(port) (*((volatile unsigned int *)(port))) |
| Get a 32-bit unsigned value from specified I/O port. More... | |
| #define | outps(port, value) *((volatile unsigned short *)(port)) = value |
| Set a 16-bit unsigned value to specified I/O port. More... | |
| #define | inps(port) (*((volatile unsigned short *)(port))) |
| Get a 16-bit unsigned value from specified I/O port. More... | |
| #define | outpb(port, value) *((volatile unsigned char *)(port)) = value |
| Set a 8-bit unsigned value to specified I/O port. More... | |
| #define | inpb(port) (*((volatile unsigned char *)(port))) |
| Get a 8-bit unsigned value from specified I/O port. More... | |
| #define | outp32(port, value) *((volatile unsigned int *)(port)) = value |
| Set a 32-bit unsigned value to specified I/O port. More... | |
| #define | inp32(port) (*((volatile unsigned int *)(port))) |
| Get a 32-bit unsigned value from specified I/O port. More... | |
| #define | outp16(port, value) *((volatile unsigned short *)(port)) = value |
| Set a 16-bit unsigned value to specified I/O port. More... | |
| #define | inp16(port) (*((volatile unsigned short *)(port))) |
| Get a 16-bit unsigned value from specified I/O port. More... | |
| #define | outp8(port, value) *((volatile unsigned char *)(port)) = value |
| Set a 8-bit unsigned value to specified I/O port. More... | |
| #define | inp8(port) (*((volatile unsigned char *)(port))) |
| Get a 8-bit unsigned value from specified I/O port. More... | |
| #define | NULL (0) |
| NULL pointer. More... | |
| #define | TRUE (1) |
| Boolean true, define to use in API parameters or return value. More... | |
| #define | FALSE (0) |
| Boolean false, define to use in API parameters or return value. More... | |
| #define | ENABLE (1) |
| Enable, define to use in API parameters. More... | |
| #define | DISABLE (0) |
| Disable, define to use in API parameters. More... | |
| #define | BIT0 (0x00000001) |
| Bit 0 mask of an 32 bit integer. More... | |
| #define | BIT1 (0x00000002) |
| Bit 1 mask of an 32 bit integer. More... | |
| #define | BIT2 (0x00000004) |
| Bit 2 mask of an 32 bit integer. More... | |
| #define | BIT3 (0x00000008) |
| Bit 3 mask of an 32 bit integer. More... | |
| #define | BIT4 (0x00000010) |
| Bit 4 mask of an 32 bit integer. More... | |
| #define | BIT5 (0x00000020) |
| Bit 5 mask of an 32 bit integer. More... | |
| #define | BIT6 (0x00000040) |
| Bit 6 mask of an 32 bit integer. More... | |
| #define | BIT7 (0x00000080) |
| Bit 7 mask of an 32 bit integer. More... | |
| #define | BIT8 (0x00000100) |
| Bit 8 mask of an 32 bit integer. More... | |
| #define | BIT9 (0x00000200) |
| Bit 9 mask of an 32 bit integer. More... | |
| #define | BIT10 (0x00000400) |
| Bit 10 mask of an 32 bit integer. More... | |
| #define | BIT11 (0x00000800) |
| Bit 11 mask of an 32 bit integer. More... | |
| #define | BIT12 (0x00001000) |
| Bit 12 mask of an 32 bit integer. More... | |
| #define | BIT13 (0x00002000) |
| Bit 13 mask of an 32 bit integer. More... | |
| #define | BIT14 (0x00004000) |
| Bit 14 mask of an 32 bit integer. More... | |
| #define | BIT15 (0x00008000) |
| Bit 15 mask of an 32 bit integer. More... | |
| #define | BIT16 (0x00010000) |
| Bit 16 mask of an 32 bit integer. More... | |
| #define | BIT17 (0x00020000) |
| Bit 17 mask of an 32 bit integer. More... | |
| #define | BIT18 (0x00040000) |
| Bit 18 mask of an 32 bit integer. More... | |
| #define | BIT19 (0x00080000) |
| Bit 19 mask of an 32 bit integer. More... | |
| #define | BIT20 (0x00100000) |
| Bit 20 mask of an 32 bit integer. More... | |
| #define | BIT21 (0x00200000) |
| Bit 21 mask of an 32 bit integer. More... | |
| #define | BIT22 (0x00400000) |
| Bit 22 mask of an 32 bit integer. More... | |
| #define | BIT23 (0x00800000) |
| Bit 23 mask of an 32 bit integer. More... | |
| #define | BIT24 (0x01000000) |
| Bit 24 mask of an 32 bit integer. More... | |
| #define | BIT25 (0x02000000) |
| Bit 25 mask of an 32 bit integer. More... | |
| #define | BIT26 (0x04000000) |
| Bit 26 mask of an 32 bit integer. More... | |
| #define | BIT27 (0x08000000) |
| Bit 27 mask of an 32 bit integer. More... | |
| #define | BIT28 (0x10000000) |
| Bit 28 mask of an 32 bit integer. More... | |
| #define | BIT29 (0x20000000) |
| Bit 29 mask of an 32 bit integer. More... | |
| #define | BIT30 (0x40000000) |
| Bit 30 mask of an 32 bit integer. More... | |
| #define | BIT31 (0x80000000) |
| Bit 31 mask of an 32 bit integer. More... | |
| #define | BYTE0_Msk (0x000000FF) |
| Mask to get bit0~bit7 from a 32 bit integer. More... | |
| #define | BYTE1_Msk (0x0000FF00) |
| Mask to get bit8~bit15 from a 32 bit integer. More... | |
| #define | BYTE2_Msk (0x00FF0000) |
| Mask to get bit16~bit23 from a 32 bit integer. More... | |
| #define | BYTE3_Msk (0xFF000000) |
| Mask to get bit24~bit31 from a 32 bit integer. More... | |
| #define | GET_BYTE0(u32Param) ((u32Param & BYTE0_Msk) ) |
| #define | GET_BYTE1(u32Param) ((u32Param & BYTE1_Msk) >> 8) |
| #define | GET_BYTE2(u32Param) ((u32Param & BYTE2_Msk) >> 16) |
| #define | GET_BYTE3(u32Param) ((u32Param & BYTE3_Msk) >> 24) |
| #define | ADC_RESULT_RSLT_Pos (0) |
| #define | ADC_RESULT_RSLT_Msk (0xffful << ADC_RESULT_RSLT_Pos) |
| #define | ADC_CR_ADEN_Pos (0) |
| #define | ADC_CR_ADEN_Msk (0x1ul << ADC_CR_ADEN_Pos) |
| #define | ADC_CR_ADIE_Pos (1) |
| #define | ADC_CR_ADIE_Msk (0x1ul << ADC_CR_ADIE_Pos) |
| #define | ADC_CR_ADMD_Pos (2) |
| #define | ADC_CR_ADMD_Msk (0x3ul << ADC_CR_ADMD_Pos) |
| #define | ADC_CR_TRGS_Pos (4) |
| #define | ADC_CR_TRGS_Msk (0x3ul << ADC_CR_TRGS_Pos) |
| #define | ADC_CR_TRGCOND_Pos (6) |
| #define | ADC_CR_TRGCOND_Msk (0x3ul << ADC_CR_TRGCOND_Pos) |
| #define | ADC_CR_TRGE_Pos (8) |
| #define | ADC_CR_TRGE_Msk (0x1ul << ADC_CR_TRGE_Pos) |
| #define | ADC_CR_PTEN_Pos (9) |
| #define | ADC_CR_PTEN_Msk (0x1ul << ADC_CR_PTEN_Pos) |
| #define | ADC_CR_ADST_Pos (11) |
| #define | ADC_CR_ADST_Msk (0x1ul << ADC_CR_ADST_Pos) |
| #define | ADC_CR_TMSEL_Pos (12) |
| #define | ADC_CR_TMSEL_Msk (0x3ul << ADC_CR_TMSEL_Pos) |
| #define | ADC_CR_TMTRGMOD_Pos (15) |
| #define | ADC_CR_TMTRGMOD_Msk (0x1ul << ADC_CR_TMTRGMOD_Pos) |
| #define | ADC_CR_REFSEL_Pos (16) |
| #define | ADC_CR_REFSEL_Msk (0x3ul << ADC_CR_REFSEL_Pos) |
| #define | ADC_CHEN_CHEN0_Pos (0) |
| #define | ADC_CHEN_CHEN0_Msk (0x1ul << ADC_CHEN_CHEN0_Pos) |
| #define | ADC_CHEN_CHEN1_Pos (1) |
| #define | ADC_CHEN_CHEN1_Msk (0x1ul << ADC_CHEN_CHEN1_Pos) |
| #define | ADC_CHEN_CHEN2_Pos (2) |
| #define | ADC_CHEN_CHEN2_Msk (0x1ul << ADC_CHEN_CHEN2_Pos) |
| #define | ADC_CHEN_CHEN3_Pos (3) |
| #define | ADC_CHEN_CHEN3_Msk (0x1ul << ADC_CHEN_CHEN3_Pos) |
| #define | ADC_CHEN_CHEN4_Pos (4) |
| #define | ADC_CHEN_CHEN4_Msk (0x1ul << ADC_CHEN_CHEN4_Pos) |
| #define | ADC_CHEN_CHEN5_Pos (5) |
| #define | ADC_CHEN_CHEN5_Msk (0x1ul << ADC_CHEN_CHEN5_Pos) |
| #define | ADC_CHEN_CHEN6_Pos (6) |
| #define | ADC_CHEN_CHEN6_Msk (0x1ul << ADC_CHEN_CHEN6_Pos) |
| #define | ADC_CHEN_CHEN7_Pos (7) |
| #define | ADC_CHEN_CHEN7_Msk (0x1ul << ADC_CHEN_CHEN7_Pos) |
| #define | ADC_CHEN_CHEN10_Pos (10) |
| #define | ADC_CHEN_CHEN10_Msk (0x1ul << ADC_CHEN_CHEN10_Pos) |
| #define | ADC_CHEN_CH10SEL_Pos (11) |
| #define | ADC_CHEN_CH10SEL_Msk (0x3ul << ADC_CHEN_CH10SEL_Pos) |
| #define | ADC_CMPR0_CMPEN_Pos (0) |
| #define | ADC_CMPR0_CMPEN_Msk (0x1ul << ADC_CMPR0_CMPEN_Pos) |
| #define | ADC_CMPR0_CMPIE_Pos (1) |
| #define | ADC_CMPR0_CMPIE_Msk (0x1ul << ADC_CMPR0_CMPIE_Pos) |
| #define | ADC_CMPR0_CMPCOND_Pos (2) |
| #define | ADC_CMPR0_CMPCOND_Msk (0x1ul << ADC_CMPR0_CMPCOND_Pos) |
| #define | ADC_CMPR0_CMPCH_Pos (3) |
| #define | ADC_CMPR0_CMPCH_Msk (0xful << ADC_CMPR0_CMPCH_Pos) |
| #define | ADC_CMPR0_CMPMATCNT_Pos (8) |
| #define | ADC_CMPR0_CMPMATCNT_Msk (0xful << ADC_CMPR0_CMPMATCNT_Pos) |
| #define | ADC_CMPR0_CMPD_Pos (16) |
| #define | ADC_CMPR0_CMPD_Msk (0xffful << ADC_CMPR0_CMPD_Pos) |
| #define | ADC_CMPR1_CMPEN_Pos (0) |
| #define | ADC_CMPR1_CMPEN_Msk (0x1ul << ADC_CMPR1_CMPEN_Pos) |
| #define | ADC_CMPR1_CMPIE_Pos (1) |
| #define | ADC_CMPR1_CMPIE_Msk (0x1ul << ADC_CMPR1_CMPIE_Pos) |
| #define | ADC_CMPR1_CMPCOND_Pos (2) |
| #define | ADC_CMPR1_CMPCOND_Msk (0x1ul << ADC_CMPR1_CMPCOND_Pos) |
| #define | ADC_CMPR1_CMPCH_Pos (3) |
| #define | ADC_CMPR1_CMPCH_Msk (0xful << ADC_CMPR1_CMPCH_Pos) |
| #define | ADC_CMPR1_CMPMATCNT_Pos (8) |
| #define | ADC_CMPR1_CMPMATCNT_Msk (0xful << ADC_CMPR1_CMPMATCNT_Pos) |
| #define | ADC_CMPR1_CMPD_Pos (16) |
| #define | ADC_CMPR1_CMPD_Msk (0xffful << ADC_CMPR1_CMPD_Pos) |
| #define | ADC_SR_ADF_Pos (0) |
| #define | ADC_SR_ADF_Msk (0x1ul << ADC_SR_ADF_Pos) |
| #define | ADC_SR_CMPF0_Pos (1) |
| #define | ADC_SR_CMPF0_Msk (0x1ul << ADC_SR_CMPF0_Pos) |
| #define | ADC_SR_CMPF1_Pos (2) |
| #define | ADC_SR_CMPF1_Msk (0x1ul << ADC_SR_CMPF1_Pos) |
| #define | ADC_SR_BUSY_Pos (3) |
| #define | ADC_SR_BUSY_Msk (0x1ul << ADC_SR_BUSY_Pos) |
| #define | ADC_SR_CHANNEL_Pos (4) |
| #define | ADC_SR_CHANNEL_Msk (0xful << ADC_SR_CHANNEL_Pos) |
| #define | ADC_SR_VALID_Pos (8) |
| #define | ADC_SR_VALID_Msk (0x4fful << ADC_SR_VALID_Pos) |
| #define | ADC_SR_OVERRUN_Pos (20) |
| #define | ADC_SR_OVERRUN_Msk (0x4fful << ADC_SR_OVERRUN_Pos) |
| #define | ADC_PDMA_AD_PDMA_Pos (0) |
| #define | ADC_PDMA_AD_PDMA_Msk (0xffful << ADC_PDMA_AD_PDMA_Pos) |
| #define | ADC_DELSEL_En2StDelay_Pos (0) |
| #define | ADC_DELSEL_En2StDelay_Msk (0xfful << ADC_DELSEL_En2StDelay_Pos) |
| #define | ADC_DELSEL_TMPDMACNT_Pos (8) |
| #define | ADC_DELSEL_TMPDMACNT_Msk (0xfful << ADC_DELSEL_TMPDMACNT_Pos) |
| #define | ADC_DELSEL_ADCSTHOLDCNT_Pos (16) |
| #define | ADC_DELSEL_ADCSTHOLDCNT_Msk (0xfful << ADC_DELSEL_ADCSTHOLDCNT_Pos) |
| #define | CLK_PWRCTL_HXT_EN_Pos (0) |
| #define | CLK_PWRCTL_HXT_EN_Msk (0x1ul << CLK_PWRCTL_HXT_EN_Pos) |
| #define | CLK_PWRCTL_LXT_EN_Pos (1) |
| #define | CLK_PWRCTL_LXT_EN_Msk (0x1ul << CLK_PWRCTL_LXT_EN_Pos) |
| #define | CLK_PWRCTL_HIRC_EN_Pos (2) |
| #define | CLK_PWRCTL_HIRC_EN_Msk (0x1ul << CLK_PWRCTL_HIRC_EN_Pos) |
| #define | CLK_PWRCTL_LIRC_EN_Pos (3) |
| #define | CLK_PWRCTL_LIRC_EN_Msk (0x1ul << CLK_PWRCTL_LIRC_EN_Pos) |
| #define | CLK_PWRCTL_WK_DLY_Pos (4) |
| #define | CLK_PWRCTL_WK_DLY_Msk (0x1ul << CLK_PWRCTL_WK_DLY_Pos) |
| #define | CLK_PWRCTL_PD_WK_IE_Pos (5) |
| #define | CLK_PWRCTL_PD_WK_IE_Msk (0x1ul << CLK_PWRCTL_PD_WK_IE_Pos) |
| #define | CLK_PWRCTL_PD_EN_Pos (6) |
| #define | CLK_PWRCTL_PD_EN_Msk (0x1ul << CLK_PWRCTL_PD_EN_Pos) |
| #define | CLK_PWRCTL_HXT_SELXT_Pos (8) |
| #define | CLK_PWRCTL_HXT_SELXT_Msk (0x1ul << CLK_PWRCTL_HXT_SELXT_Pos) |
| #define | CLK_PWRCTL_HXT_GAIN_Pos (9) |
| #define | CLK_PWRCTL_HXT_GAIN_Msk (0x1ul << CLK_PWRCTL_HXT_GAIN_Pos) |
| #define | CLK_PWRCTL_LXT_SCNT_Pos (10) |
| #define | CLK_PWRCTL_LXT_SCNT_Msk (0x1ul << CLK_PWRCTL_LXT_SCNT_Pos) |
| #define | CLK_AHBCLK_GPIO_EN_Pos (0) |
| #define | CLK_AHBCLK_GPIO_EN_Msk (0x1ul << CLK_AHBCLK_GPIO_EN_Pos) |
| #define | CLK_AHBCLK_DMA_EN_Pos (1) |
| #define | CLK_AHBCLK_DMA_EN_Msk (0x1ul << CLK_AHBCLK_DMA_EN_Pos) |
| #define | CLK_AHBCLK_ISP_EN_Pos (2) |
| #define | CLK_AHBCLK_ISP_EN_Msk (0x1ul << CLK_AHBCLK_ISP_EN_Pos) |
| #define | CLK_AHBCLK_EBI_EN_Pos (3) |
| #define | CLK_AHBCLK_EBI_EN_Msk (0x1ul << CLK_AHBCLK_EBI_EN_Pos) |
| #define | CLK_AHBCLK_SRAM_EN_Pos (4) |
| #define | CLK_AHBCLK_SRAM_EN_Msk (0x1ul << CLK_AHBCLK_SRAM_EN_Pos) |
| #define | CLK_AHBCLK_TICK_EN_Pos (5) |
| #define | CLK_AHBCLK_TICK_EN_Msk (0x1ul << CLK_AHBCLK_TICK_EN_Pos) |
| #define | CLK_APBCLK_WDT_EN_Pos (0) |
| #define | CLK_APBCLK_WDT_EN_Msk (0x1ul << CLK_APBCLK_WDT_EN_Pos) |
| #define | CLK_APBCLK_RTC_EN_Pos (1) |
| #define | CLK_APBCLK_RTC_EN_Msk (0x1ul << CLK_APBCLK_RTC_EN_Pos) |
| #define | CLK_APBCLK_TMR0_EN_Pos (2) |
| #define | CLK_APBCLK_TMR0_EN_Msk (0x1ul << CLK_APBCLK_TMR0_EN_Pos) |
| #define | CLK_APBCLK_TMR1_EN_Pos (3) |
| #define | CLK_APBCLK_TMR1_EN_Msk (0x1ul << CLK_APBCLK_TMR1_EN_Pos) |
| #define | CLK_APBCLK_TMR2_EN_Pos (4) |
| #define | CLK_APBCLK_TMR2_EN_Msk (0x1ul << CLK_APBCLK_TMR2_EN_Pos) |
| #define | CLK_APBCLK_TMR3_EN_Pos (5) |
| #define | CLK_APBCLK_TMR3_EN_Msk (0x1ul << CLK_APBCLK_TMR3_EN_Pos) |
| #define | CLK_APBCLK_FDIV_EN_Pos (6) |
| #define | CLK_APBCLK_FDIV_EN_Msk (0x1ul << CLK_APBCLK_FDIV_EN_Pos) |
| #define | CLK_APBCLK_I2C0_EN_Pos (8) |
| #define | CLK_APBCLK_I2C0_EN_Msk (0x1ul << CLK_APBCLK_I2C0_EN_Pos) |
| #define | CLK_APBCLK_I2C1_EN_Pos (9) |
| #define | CLK_APBCLK_I2C1_EN_Msk (0x1ul << CLK_APBCLK_I2C1_EN_Pos) |
| #define | CLK_APBCLK_SPI0_EN_Pos (12) |
| #define | CLK_APBCLK_SPI0_EN_Msk (0x1ul << CLK_APBCLK_SPI0_EN_Pos) |
| #define | CLK_APBCLK_SPI1_EN_Pos (13) |
| #define | CLK_APBCLK_SPI1_EN_Msk (0x1ul << CLK_APBCLK_SPI1_EN_Pos) |
| #define | CLK_APBCLK_SPI2_EN_Pos (14) |
| #define | CLK_APBCLK_SPI2_EN_Msk (0x1ul << CLK_APBCLK_SPI2_EN_Pos) |
| #define | CLK_APBCLK_UART0_EN_Pos (16) |
| #define | CLK_APBCLK_UART0_EN_Msk (0x1ul << CLK_APBCLK_UART0_EN_Pos) |
| #define | CLK_APBCLK_UART1_EN_Pos (17) |
| #define | CLK_APBCLK_UART1_EN_Msk (0x1ul << CLK_APBCLK_UART1_EN_Pos) |
| #define | CLK_APBCLK_PWM0_CH01_EN_Pos (20) |
| #define | CLK_APBCLK_PWM0_CH01_EN_Msk (0x1ul << CLK_APBCLK_PWM0_CH01_EN_Pos) |
| #define | CLK_APBCLK_PWM0_CH23_EN_Pos (21) |
| #define | CLK_APBCLK_PWM0_CH23_EN_Msk (0x1ul << CLK_APBCLK_PWM0_CH23_EN_Pos) |
| #define | CLK_APBCLK_PWM1_CH01_EN_Pos (22) |
| #define | CLK_APBCLK_PWM1_CH01_EN_Msk (0x1ul << CLK_APBCLK_PWM1_CH01_EN_Pos) |
| #define | CLK_APBCLK_PWM1_CH23_EN_Pos (23) |
| #define | CLK_APBCLK_PWM1_CH23_EN_Msk (0x1ul << CLK_APBCLK_PWM1_CH23_EN_Pos) |
| #define | CLK_APBCLK_USBD_EN_Pos (27) |
| #define | CLK_APBCLK_USBD_EN_Msk (0x1ul << CLK_APBCLK_USBD_EN_Pos) |
| #define | CLK_APBCLK_ADC_EN_Pos (28) |
| #define | CLK_APBCLK_ADC_EN_Msk (0x1ul << CLK_APBCLK_ADC_EN_Pos) |
| #define | CLK_APBCLK_I2S_EN_Pos (29) |
| #define | CLK_APBCLK_I2S_EN_Msk (0x1ul << CLK_APBCLK_I2S_EN_Pos) |
| #define | CLK_APBCLK_SC0_EN_Pos (30) |
| #define | CLK_APBCLK_SC0_EN_Msk (0x1ul << CLK_APBCLK_SC0_EN_Pos) |
| #define | CLK_APBCLK_SC1_EN_Pos (31) |
| #define | CLK_APBCLK_SC1_EN_Msk (0x1ul << CLK_APBCLK_SC1_EN_Pos) |
| #define | CLK_CLKSTATUS_HXT_STB_Pos (0) |
| #define | CLK_CLKSTATUS_HXT_STB_Msk (0x1ul << CLK_CLKSTATUS_HXT_STB_Pos) |
| #define | CLK_CLKSTATUS_LXT_STB_Pos (1) |
| #define | CLK_CLKSTATUS_LXT_STB_Msk (0x1ul << CLK_CLKSTATUS_LXT_STB_Pos) |
| #define | CLK_CLKSTATUS_PLL_STB_Pos (2) |
| #define | CLK_CLKSTATUS_PLL_STB_Msk (0x1ul << CLK_CLKSTATUS_PLL_STB_Pos) |
| #define | CLK_CLKSTATUS_LIRC_STB_Pos (3) |
| #define | CLK_CLKSTATUS_LIRC_STB_Msk (0x1ul << CLK_CLKSTATUS_LIRC_STB_Pos) |
| #define | CLK_CLKSTATUS_HIRC_STB_Pos (4) |
| #define | CLK_CLKSTATUS_HIRC_STB_Msk (0x1ul << CLK_CLKSTATUS_HIRC_STB_Pos) |
| #define | CLK_CLKSTATUS_CLK_SW_FAIL_Pos (7) |
| #define | CLK_CLKSTATUS_CLK_SW_FAIL_Msk (0x1ul << CLK_CLKSTATUS_CLK_SW_FAIL_Pos) |
| #define | CLK_CLKSEL0_HCLK_S_Pos (0) |
| #define | CLK_CLKSEL0_HCLK_S_Msk (0x7ul << CLK_CLKSEL0_HCLK_S_Pos) |
| #define | CLK_CLKSEL1_UART_S_Pos (0) |
| #define | CLK_CLKSEL1_UART_S_Msk (0x3ul << CLK_CLKSEL1_UART_S_Pos) |
| #define | CLK_CLKSEL1_ADC_S_Pos (2) |
| #define | CLK_CLKSEL1_ADC_S_Msk (0x3ul << CLK_CLKSEL1_ADC_S_Pos) |
| #define | CLK_CLKSEL1_PWM0_CH01_S_Pos (4) |
| #define | CLK_CLKSEL1_PWM0_CH01_S_Msk (0x3ul << CLK_CLKSEL1_PWM0_CH01_S_Pos) |
| #define | CLK_CLKSEL1_PWM0_CH23_S_Pos (6) |
| #define | CLK_CLKSEL1_PWM0_CH23_S_Msk (0x3ul << CLK_CLKSEL1_PWM0_CH23_S_Pos) |
| #define | CLK_CLKSEL1_TMR0_S_Pos (8) |
| #define | CLK_CLKSEL1_TMR0_S_Msk (0x7ul << CLK_CLKSEL1_TMR0_S_Pos) |
| #define | CLK_CLKSEL1_TMR1_S_Pos (12) |
| #define | CLK_CLKSEL1_TMR1_S_Msk (0x7ul << CLK_CLKSEL1_TMR1_S_Pos) |
| #define | CLK_CLKSEL2_FRQDIV_S_Pos (2) |
| #define | CLK_CLKSEL2_FRQDIV_S_Msk (0x3ul << CLK_CLKSEL2_FRQDIV_S_Pos) |
| #define | CLK_CLKSEL2_PWM1_CH01_S_Pos (4) |
| #define | CLK_CLKSEL2_PWM1_CH01_S_Msk (0x3ul << CLK_CLKSEL2_PWM1_CH01_S_Pos) |
| #define | CLK_CLKSEL2_PWM1_CH23_S_Pos (6) |
| #define | CLK_CLKSEL2_PWM1_CH23_S_Msk (0x3ul << CLK_CLKSEL2_PWM1_CH23_S_Pos) |
| #define | CLK_CLKSEL2_TMR2_S_Pos (8) |
| #define | CLK_CLKSEL2_TMR2_S_Msk (0x7ul << CLK_CLKSEL2_TMR2_S_Pos) |
| #define | CLK_CLKSEL2_TMR3_S_Pos (12) |
| #define | CLK_CLKSEL2_TMR3_S_Msk (0x7ul << CLK_CLKSEL2_TMR3_S_Pos) |
| #define | CLK_CLKSEL2_I2S_S_Pos (16) |
| #define | CLK_CLKSEL2_I2S_S_Msk (0x3ul << CLK_CLKSEL2_I2S_S_Pos) |
| #define | CLK_CLKSEL2_SC_S_Pos (18) |
| #define | CLK_CLKSEL2_SC_S_Msk (0x3ul << CLK_CLKSEL2_SC_S_Pos) |
| #define | CLK_CLKDIV0_HCLK_N_Pos (0) |
| #define | CLK_CLKDIV0_HCLK_N_Msk (0xful << CLK_CLKDIV0_HCLK_N_Pos) |
| #define | CLK_CLKDIV0_USB_N_Pos (4) |
| #define | CLK_CLKDIV0_USB_N_Msk (0xful << CLK_CLKDIV0_USB_N_Pos) |
| #define | CLK_CLKDIV0_UART_N_Pos (8) |
| #define | CLK_CLKDIV0_UART_N_Msk (0xful << CLK_CLKDIV0_UART_N_Pos) |
| #define | CLK_CLKDIV0_I2S_N_Pos (12) |
| #define | CLK_CLKDIV0_I2S_N_Msk (0xful << CLK_CLKDIV0_I2S_N_Pos) |
| #define | CLK_CLKDIV0_ADC_N_Pos (16) |
| #define | CLK_CLKDIV0_ADC_N_Msk (0xfful << CLK_CLKDIV0_ADC_N_Pos) |
| #define | CLK_CLKDIV0_SC0_N_Pos (28) |
| #define | CLK_CLKDIV0_SC0_N_Msk (0xful << CLK_CLKDIV0_SC0_N_Pos) |
| #define | CLK_CLKDIV1_SC1_N_Pos (0) |
| #define | CLK_CLKDIV1_SC1_N_Msk (0xful << CLK_CLKDIV1_SC1_N_Pos) |
| #define | CLK_PLLCTL_FB_DV_Pos (0) |
| #define | CLK_PLLCTL_FB_DV_Msk (0x3ful << CLK_PLLCTL_FB_DV_Pos) |
| #define | CLK_PLLCTL_IN_DV_Pos (8) |
| #define | CLK_PLLCTL_IN_DV_Msk (0x3ul << CLK_PLLCTL_IN_DV_Pos) |
| #define | CLK_PLLCTL_OUT_DV_Pos (12) |
| #define | CLK_PLLCTL_OUT_DV_Msk (0x1ul << CLK_PLLCTL_OUT_DV_Pos) |
| #define | CLK_PLLCTL_PD_Pos (16) |
| #define | CLK_PLLCTL_PD_Msk (0x1ul << CLK_PLLCTL_PD_Pos) |
| #define | CLK_PLLCTL_PLL_SRC_Pos (17) |
| #define | CLK_PLLCTL_PLL_SRC_Msk (0x1ul << CLK_PLLCTL_PLL_SRC_Pos) |
| #define | CLK_FRQDIV_FSEL_Pos (0) |
| #define | CLK_FRQDIV_FSEL_Msk (0xful << CLK_FRQDIV_FSEL_Pos) |
| #define | CLK_FRQDIV_FDIV_EN_Pos (4) |
| #define | CLK_FRQDIV_FDIV_EN_Msk (0x1ul << CLK_FRQDIV_FDIV_EN_Pos) |
| #define | CLK_PD_WK_IS_PD_WK_IS_Pos (0) |
| #define | CLK_PD_WK_IS_PD_WK_IS_Msk (0x1ul << CLK_PD_WK_IS_PD_WK_IS_Pos) |
| #define | DMA_GCR_GCRCSR_CLK0_EN_Pos (8) |
| #define | DMA_GCR_GCRCSR_CLK0_EN_Msk (0x1ul << DMA_GCR_GCRCSR_CLK0_EN_Pos) |
| #define | DMA_GCR_GCRCSR_CLK1_EN_Pos (9) |
| #define | DMA_GCR_GCRCSR_CLK1_EN_Msk (0x1ul << DMA_GCR_GCRCSR_CLK1_EN_Pos) |
| #define | DMA_GCR_GCRCSR_CLK2_EN_Pos (10) |
| #define | DMA_GCR_GCRCSR_CLK2_EN_Msk (0x1ul << DMA_GCR_GCRCSR_CLK2_EN_Pos) |
| #define | DMA_GCR_GCRCSR_CLK3_EN_Pos (11) |
| #define | DMA_GCR_GCRCSR_CLK3_EN_Msk (0x1ul << DMA_GCR_GCRCSR_CLK3_EN_Pos) |
| #define | DMA_GCR_GCRCSR_CLK4_EN_Pos (12) |
| #define | DMA_GCR_GCRCSR_CLK4_EN_Msk (0x1ul << DMA_GCR_GCRCSR_CLK4_EN_Pos) |
| #define | DMA_GCR_DSSR0_CH1_SEL_Pos (8) |
| #define | DMA_GCR_DSSR0_CH1_SEL_Msk (0x1ful << DMA_GCR_DSSR0_CH1_SEL_Pos) |
| #define | DMA_GCR_DSSR0_CH2_SEL_Pos (16) |
| #define | DMA_GCR_DSSR0_CH2_SEL_Msk (0x1ful << DMA_GCR_DSSR0_CH2_SEL_Pos) |
| #define | DMA_GCR_DSSR0_CH3_SEL_Pos (24) |
| #define | DMA_GCR_DSSR0_CH3_SEL_Msk (0x1ful << DMA_GCR_DSSR0_CH3_SEL_Pos) |
| #define | DMA_GCR_DSSR1_CH4_SEL_Pos (0) |
| #define | DMA_GCR_DSSR1_CH4_SEL_Msk (0x1ful << DMA_GCR_DSSR1_CH4_SEL_Pos) |
| #define | DMA_GCR_GCRISR_INTR0_Pos (0) |
| #define | DMA_GCR_GCRISR_INTR0_Msk (0x1ul << DMA_GCR_GCRISR_INTR0_Pos) |
| #define | DMA_GCR_GCRISR_INTR1_Pos (1) |
| #define | DMA_GCR_GCRISR_INTR1_Msk (0x1ul << DMA_GCR_GCRISR_INTR1_Pos) |
| #define | DMA_GCR_GCRISR_INTR2_Pos (2) |
| #define | DMA_GCR_GCRISR_INTR2_Msk (0x1ul << DMA_GCR_GCRISR_INTR2_Pos) |
| #define | DMA_GCR_GCRISR_INTR3_Pos (3) |
| #define | DMA_GCR_GCRISR_INTR3_Msk (0x1ul << DMA_GCR_GCRISR_INTR3_Pos) |
| #define | DMA_GCR_GCRISR_INTR4_Pos (4) |
| #define | DMA_GCR_GCRISR_INTR4_Msk (0x1ul << DMA_GCR_GCRISR_INTR4_Pos) |
| #define | PDMA_CSR_PDMACEN_Pos (0) |
| #define | PDMA_CSR_PDMACEN_Msk (0x1ul << PDMA_CSR_PDMACEN_Pos) |
| #define | PDMA_CSR_SW_RST_Pos (1) |
| #define | PDMA_CSR_SW_RST_Msk (0x1ul << PDMA_CSR_SW_RST_Pos) |
| #define | PDMA_CSR_MODE_SEL_Pos (2) |
| #define | PDMA_CSR_MODE_SEL_Msk (0x3ul << PDMA_CSR_MODE_SEL_Pos) |
| #define | PDMA_CSR_SAD_SEL_Pos (4) |
| #define | PDMA_CSR_SAD_SEL_Msk (0x3ul << PDMA_CSR_SAD_SEL_Pos) |
| #define | PDMA_CSR_DAD_SEL_Pos (6) |
| #define | PDMA_CSR_DAD_SEL_Msk (0x3ul << PDMA_CSR_DAD_SEL_Pos) |
| #define | PDMA_CSR_TO_EN_Pos (12) |
| #define | PDMA_CSR_TO_EN_Msk (0x1ul << PDMA_CSR_TO_EN_Pos) |
| #define | PDMA_CSR_APB_TWS_Pos (19) |
| #define | PDMA_CSR_APB_TWS_Msk (0x3ul << PDMA_CSR_APB_TWS_Pos) |
| #define | PDMA_CSR_TRIG_EN_Pos (23) |
| #define | PDMA_CSR_TRIG_EN_Msk (0x1ul << PDMA_CSR_TRIG_EN_Pos) |
| #define | PDMA_SAR_PDMA_SAR_Pos (0) |
| #define | PDMA_SAR_PDMA_SAR_Msk (0xfffffffful << PDMA_SAR_PDMA_SAR_Pos) |
| #define | PDMA_DAR_PDMA_DAR_Pos (0) |
| #define | PDMA_DAR_PDMA_DAR_Msk (0xfffffffful << PDMA_DAR_PDMA_DAR_Pos) |
| #define | PDMA_BCR_PDMA_BCR_Pos (0) |
| #define | PDMA_BCR_PDMA_BCR_Msk (0xfffful << PDMA_BCR_PDMA_BCR_Pos) |
| #define | PDMA_CSAR_PDMA_CSAR_Pos (0) |
| #define | PDMA_CSAR_PDMA_CSAR_Msk (0xfffffffful << PDMA_CSAR_PDMA_CSAR_Pos) |
| #define | PDMA_CDAR_PDMA_CDAR_Pos (0) |
| #define | PDMA_CDAR_PDMA_CDAR_Msk (0xfffffffful << PDMA_CDAR_PDMA_CDAR_Pos) |
| #define | PDMA_CBCR_PDMA_CBCR_Pos (0) |
| #define | PDMA_CBCR_PDMA_CBCR_Msk (0xfffffful << PDMA_CBCR_PDMA_CBCR_Pos) |
| #define | PDMA_IER_TABORT_IE_Pos (0) |
| #define | PDMA_IER_TABORT_IE_Msk (0x1ul << PDMA_IER_TABORT_IE_Pos) |
| #define | PDMA_IER_TD_IE_Pos (1) |
| #define | PDMA_IER_TD_IE_Msk (0x1ul << PDMA_IER_TD_IE_Pos) |
| #define | PDMA_IER_WRA_BCR_IE_Pos (2) |
| #define | PDMA_IER_WRA_BCR_IE_Msk (0xful << PDMA_IER_WRA_BCR_IE_Pos) |
| #define | PDMA_IER_TO_IE_Pos (6) |
| #define | PDMA_IER_TO_IE_Msk (0x1ul << PDMA_IER_TO_IE_Pos) |
| #define | PDMA_ISR_TABORT_IS_Pos (0) |
| #define | PDMA_ISR_TABORT_IS_Msk (0x1ul << PDMA_ISR_TABORT_IS_Pos) |
| #define | PDMA_ISR_TD_IS_Pos (1) |
| #define | PDMA_ISR_TD_IS_Msk (0x1ul << PDMA_ISR_TD_IS_Pos) |
| #define | PDMA_ISR_WRA_BCR_IS_Pos (2) |
| #define | PDMA_ISR_WRA_BCR_IS_Msk (0xful << PDMA_ISR_WRA_BCR_IS_Pos) |
| #define | PDMA_ISR_TO_IS_Pos (6) |
| #define | PDMA_ISR_TO_IS_Msk (0x1ul << PDMA_ISR_TO_IS_Pos) |
| #define | PDMA_TCR_PDMA_TCR_Pos (0) |
| #define | PDMA_TCR_PDMA_TCR_Msk (0xfffful << PDMA_TCR_PDMA_TCR_Pos) |
| #define | PDMA_BUF_PDMA_BUF_Pos (0) |
| #define | PDMA_BUF_PDMA_BUF_Msk (0xfffffffful << PDMA_BUF_PDMA_BUF_Pos) |
| #define | VDMA_CSR_VDMACEN_Pos (0) |
| #define | VDMA_CSR_VDMACEN_Msk (0x1ul << VDMA_CSR_VDMACEN_Pos) |
| #define | VDMA_CSR_SW_RST_Pos (1) |
| #define | VDMA_CSR_SW_RST_Msk (0x1ul << VDMA_CSR_SW_RST_Pos) |
| #define | VDMA_CSR_STRIDE_EN_Pos (10) |
| #define | VDMA_CSR_STRIDE_EN_Msk (0x1ul << VDMA_CSR_STRIDE_EN_Pos) |
| #define | VDMA_CSR_DIR_SEL_Pos (11) |
| #define | VDMA_CSR_DIR_SEL_Msk (0x1ul << VDMA_CSR_DIR_SEL_Pos) |
| #define | VDMA_CSR_TRIG_EN_Pos (23) |
| #define | VDMA_CSR_TRIG_EN_Msk (0x1ul << VDMA_CSR_TRIG_EN_Pos) |
| #define | VDMA_SAR_VDMA_SAR_Pos (0) |
| #define | VDMA_SAR_VDMA_SAR_Msk (0xfffffffful << VDMA_SAR_VDMA_SAR_Pos) |
| #define | VDMA_DAR_VDMA_DAR_Pos (0) |
| #define | VDMA_DAR_VDMA_DAR_Msk (0xfffffffful << VDMA_DAR_VDMA_DAR_Pos) |
| #define | VDMA_BCR_VDMA_BCR_Pos (0) |
| #define | VDMA_BCR_VDMA_BCR_Msk (0xfffful << VDMA_BCR_VDMA_BCR_Pos) |
| #define | VDMA_CSAR_VDMA_CSAR_Pos (0) |
| #define | VDMA_CSAR_VDMA_CSAR_Msk (0xfffffffful << VDMA_CSAR_VDMA_CSAR_Pos) |
| #define | VDMA_CDAR_VDMA_CDAR_Pos (0) |
| #define | VDMA_CDAR_VDMA_CDAR_Msk (0xfffffffful << VDMA_CDAR_VDMA_CDAR_Pos) |
| #define | VDMA_CBCR_VDMA_CBCR_Pos (0) |
| #define | VDMA_CBCR_VDMA_CBCR_Msk (0xfffful << VDMA_CBCR_VDMA_CBCR_Pos) |
| #define | VDMA_IER_TABORT_IE_Pos (0) |
| #define | VDMA_IER_TABORT_IE_Msk (0x1ul << VDMA_IER_TABORT_IE_Pos) |
| #define | VDMA_IER_TD_IE_Pos (1) |
| #define | VDMA_IER_TD_IE_Msk (0x1ul << VDMA_IER_TD_IE_Pos) |
| #define | VDMA_ISR_TABORT_IS_Pos (0) |
| #define | VDMA_ISR_TABORT_IS_Msk (0x1ul << VDMA_ISR_TABORT_IS_Pos) |
| #define | VDMA_ISR_TD_IS_Pos (1) |
| #define | VDMA_ISR_TD_IS_Msk (0x1ul << VDMA_ISR_TD_IS_Pos) |
| #define | VDMA_SASOCR_SASTOBL_Pos (0) |
| #define | VDMA_SASOCR_SASTOBL_Msk (0xfffful << VDMA_SASOCR_SASTOBL_Pos) |
| #define | VDMA_SASOCR_STBC_Pos (16) |
| #define | VDMA_SASOCR_STBC_Msk (0xfffful << VDMA_SASOCR_STBC_Pos) |
| #define | VDMA_DASOCR_DASTOBL_Pos (0) |
| #define | VDMA_DASOCR_DASTOBL_Msk (0xfffful << VDMA_DASOCR_DASTOBL_Pos) |
| #define | VDMA_BUF0_VDMA_BUF0_Pos (0) |
| #define | VDMA_BUF0_VDMA_BUF0_Msk (0xfffffffful << VDMA_BUF0_VDMA_BUF0_Pos) |
| #define | VDMA_BUF1_VDMA_BUF1_Pos (0) |
| #define | VDMA_BUF1_VDMA_BUF1_Msk (0xfffffffful << VDMA_BUF1_VDMA_BUF1_Pos) |
| #define | EBI_EBICON_ExtEN_Pos (0) |
| #define | EBI_EBICON_ExtEN_Msk (0x1ul << EBI_EBICON_ExtEN_Pos) |
| #define | EBI_EBICON_ExtBW16_Pos (1) |
| #define | EBI_EBICON_ExtBW16_Msk (0x1ul << EBI_EBICON_ExtBW16_Pos) |
| #define | EBI_EBICON_MCLKDIV_Pos (8) |
| #define | EBI_EBICON_MCLKDIV_Msk (0x7ul << EBI_EBICON_MCLKDIV_Pos) |
| #define | EBI_EBICON_MCLKEN_Pos (11) |
| #define | EBI_EBICON_MCLKEN_Msk (0x1ul << EBI_EBICON_MCLKEN_Pos) |
| #define | EBI_EBICON_ExttALE_Pos (16) |
| #define | EBI_EBICON_ExttALE_Msk (0x7ul << EBI_EBICON_ExttALE_Pos) |
| #define | EBI_EXTIME_ExttACC_Pos (0) |
| #define | EBI_EXTIME_ExttACC_Msk (0x1ful << EBI_EXTIME_ExttACC_Pos) |
| #define | EBI_EXTIME_ExttAHD_Pos (8) |
| #define | EBI_EXTIME_ExttAHD_Msk (0x7ul << EBI_EXTIME_ExttAHD_Pos) |
| #define | EBI_EXTIME_ExtIW2X_Pos (12) |
| #define | EBI_EXTIME_ExtIW2X_Msk (0xful << EBI_EXTIME_ExtIW2X_Pos) |
| #define | EBI_EXTIME_ExtIR2W_Pos (16) |
| #define | EBI_EXTIME_ExtIR2W_Msk (0xful << EBI_EXTIME_ExtIR2W_Pos) |
| #define | EBI_EXTIME_ExtIR2R_Pos (24) |
| #define | EBI_EXTIME_ExtIR2R_Msk (0xful << EBI_EXTIME_ExtIR2R_Pos) |
| #define | FMC_ISPCON_ISPEN_Pos (0) |
| #define | FMC_ISPCON_ISPEN_Msk (0x1ul << FMC_ISPCON_ISPEN_Pos) |
| #define | FMC_ISPCON_BS_Pos (1) |
| #define | FMC_ISPCON_BS_Msk (0x1ul << FMC_ISPCON_BS_Pos) |
| #define | FMC_ISPCON_APUEN_Pos (3) |
| #define | FMC_ISPCON_APUEN_Msk (0x1ul << FMC_ISPCON_APUEN_Pos) |
| #define | FMC_ISPCON_CFGUEN_Pos (4) |
| #define | FMC_ISPCON_CFGUEN_Msk (0x1ul << FMC_ISPCON_CFGUEN_Pos) |
| #define | FMC_ISPCON_LDUEN_Pos (5) |
| #define | FMC_ISPCON_LDUEN_Msk (0x1ul << FMC_ISPCON_LDUEN_Pos) |
| #define | FMC_ISPCON_ISPFF_Pos (6) |
| #define | FMC_ISPCON_ISPFF_Msk (0x1ul << FMC_ISPCON_ISPFF_Pos) |
| #define | FMC_ISPCON_SWRST_Pos (7) |
| #define | FMC_ISPCON_SWRST_Msk (0x1ul << FMC_ISPCON_SWRST_Pos) |
| #define | FMC_ISPCON_PT_Pos (8) |
| #define | FMC_ISPCON_PT_Msk (0x7ul << FMC_ISPCON_PT_Pos) |
| #define | FMC_ISPCON_ET_Pos (12) |
| #define | FMC_ISPCON_ET_Msk (0x7ul << FMC_ISPCON_ET_Pos) |
| #define | FMC_ISPADR_ISPADR_Pos (0) |
| #define | FMC_ISPADR_ISPADR_Msk (0xfffffffful << FMC_ISPADR_ISPADR_Pos) |
| #define | FMC_ISPDAT_ISPDAT_Pos (0) |
| #define | FMC_ISPDAT_ISPDAT_Msk (0xfffffffful << FMC_ISPDAT_ISPDAT_Pos) |
| #define | FMC_ISPCMD_FCTRL_Pos (0) |
| #define | FMC_ISPCMD_FCTRL_Msk (0xful << FMC_ISPCMD_FCTRL_Pos) |
| #define | FMC_ISPCMD_FCEN_Pos (4) |
| #define | FMC_ISPCMD_FCEN_Msk (0x1ul << FMC_ISPCMD_FCEN_Pos) |
| #define | FMC_ISPCMD_FOEN_Pos (5) |
| #define | FMC_ISPCMD_FOEN_Msk (0x1ul << FMC_ISPCMD_FOEN_Pos) |
| #define | FMC_ISPTRG_ISPGO_Pos (0) |
| #define | FMC_ISPTRG_ISPGO_Msk (0x1ul << FMC_ISPTRG_ISPGO_Pos) |
| #define | FMC_DFBADR_DFBA_Pos (0) |
| #define | FMC_DFBADR_DFBA_Msk (0xfffffffful << FMC_DFBADR_DFBA_Pos) |
| #define | FMC_ISPSTA_ISPBUSY_Pos (0) |
| #define | FMC_ISPSTA_ISPBUSY_Msk (0x1ul << FMC_ISPSTA_ISPBUSY_Pos) |
| #define | FMC_ISPSTA_CBS_Pos (1) |
| #define | FMC_ISPSTA_CBS_Msk (0x3ul << FMC_ISPSTA_CBS_Pos) |
| #define | FMC_ISPSTA_ISPFF_Pos (6) |
| #define | FMC_ISPSTA_ISPFF_Msk (0x1ul << FMC_ISPSTA_ISPFF_Pos) |
| #define | SYS_PDID_PDID_Pos (0) |
| #define | SYS_PDID_PDID_Msk (0xfffffffful << SYS_PDID_PDID_Pos) |
| #define | SYS_RST_SRC_RSTS_POR_Pos (0) |
| #define | SYS_RST_SRC_RSTS_POR_Msk (0x1ul << SYS_RST_SRC_RSTS_POR_Pos) |
| #define | SYS_RST_SRC_RSTS_PAD_Pos (1) |
| #define | SYS_RST_SRC_RSTS_PAD_Msk (0x1ul << SYS_RST_SRC_RSTS_PAD_Pos) |
| #define | SYS_RST_SRC_RSTS_WDT_Pos (2) |
| #define | SYS_RST_SRC_RSTS_WDT_Msk (0x1ul << SYS_RST_SRC_RSTS_WDT_Pos) |
| #define | SYS_RST_SRC_RSTS_BOD_Pos (4) |
| #define | SYS_RST_SRC_RSTS_BOD_Msk (0x1ul << SYS_RST_SRC_RSTS_BOD_Pos) |
| #define | SYS_RST_SRC_RSTS_SYS_Pos (5) |
| #define | SYS_RST_SRC_RSTS_SYS_Msk (0x1ul << SYS_RST_SRC_RSTS_SYS_Pos) |
| #define | SYS_RST_SRC_RSTS_CPU_Pos (7) |
| #define | SYS_RST_SRC_RSTS_CPU_Msk (0x1ul << SYS_RST_SRC_RSTS_CPU_Pos) |
| #define | SYS_IPRST_CTL1_CHIP_RST_Pos (0) |
| #define | SYS_IPRST_CTL1_CHIP_RST_Msk (0x1ul << SYS_IPRST_CTL1_CHIP_RST_Pos) |
| #define | SYS_IPRST_CTL1_CPU_RST_Pos (1) |
| #define | SYS_IPRST_CTL1_CPU_RST_Msk (0x1ul << SYS_IPRST_CTL1_CPU_RST_Pos) |
| #define | SYS_IPRST_CTL1_DMA_RST_Pos (2) |
| #define | SYS_IPRST_CTL1_DMA_RST_Msk (0x1ul << SYS_IPRST_CTL1_DMA_RST_Pos) |
| #define | SYS_IPRST_CTL1_EBI_RST_Pos (3) |
| #define | SYS_IPRST_CTL1_EBI_RST_Msk (0x1ul << SYS_IPRST_CTL1_EBI_RST_Pos) |
| #define | SYS_IPRST_CTL2_GPIO_RST_Pos (1) |
| #define | SYS_IPRST_CTL2_GPIO_RST_Msk (0x1ul << SYS_IPRST_CTL2_GPIO_RST_Pos) |
| #define | SYS_IPRST_CTL2_TMR0_RST_Pos (2) |
| #define | SYS_IPRST_CTL2_TMR0_RST_Msk (0x1ul << SYS_IPRST_CTL2_TMR0_RST_Pos) |
| #define | SYS_IPRST_CTL2_TMR1_RST_Pos (3) |
| #define | SYS_IPRST_CTL2_TMR1_RST_Msk (0x1ul << SYS_IPRST_CTL2_TMR1_RST_Pos) |
| #define | SYS_IPRST_CTL2_TMR2_RST_Pos (4) |
| #define | SYS_IPRST_CTL2_TMR2_RST_Msk (0x1ul << SYS_IPRST_CTL2_TMR2_RST_Pos) |
| #define | SYS_IPRST_CTL2_TMR3_RST_Pos (5) |
| #define | SYS_IPRST_CTL2_TMR3_RST_Msk (0x1ul << SYS_IPRST_CTL2_TMR3_RST_Pos) |
| #define | SYS_IPRST_CTL2_I2C0_RST_Pos (8) |
| #define | SYS_IPRST_CTL2_I2C0_RST_Msk (0x1ul << SYS_IPRST_CTL2_I2C0_RST_Pos) |
| #define | SYS_IPRST_CTL2_I2C1_RST_Pos (9) |
| #define | SYS_IPRST_CTL2_I2C1_RST_Msk (0x1ul << SYS_IPRST_CTL2_I2C1_RST_Pos) |
| #define | SYS_IPRST_CTL2_SPI0_RST_Pos (12) |
| #define | SYS_IPRST_CTL2_SPI0_RST_Msk (0x1ul << SYS_IPRST_CTL2_SPI0_RST_Pos) |
| #define | SYS_IPRST_CTL2_SPI1_RST_Pos (13) |
| #define | SYS_IPRST_CTL2_SPI1_RST_Msk (0x1ul << SYS_IPRST_CTL2_SPI1_RST_Pos) |
| #define | SYS_IPRST_CTL2_SPI2_RST_Pos (14) |
| #define | SYS_IPRST_CTL2_SPI2_RST_Msk (0x1ul << SYS_IPRST_CTL2_SPI2_RST_Pos) |
| #define | SYS_IPRST_CTL2_UART0_RST_Pos (16) |
| #define | SYS_IPRST_CTL2_UART0_RST_Msk (0x1ul << SYS_IPRST_CTL2_UART0_RST_Pos) |
| #define | SYS_IPRST_CTL2_UART1_RST_Pos (17) |
| #define | SYS_IPRST_CTL2_UART1_RST_Msk (0x1ul << SYS_IPRST_CTL2_UART1_RST_Pos) |
| #define | SYS_IPRST_CTL2_PWM0_RST_Pos (20) |
| #define | SYS_IPRST_CTL2_PWM0_RST_Msk (0x1ul << SYS_IPRST_CTL2_PWM0_RST_Pos) |
| #define | SYS_IPRST_CTL2_PWM1_RST_Pos (21) |
| #define | SYS_IPRST_CTL2_PWM1_RST_Msk (0x1ul << SYS_IPRST_CTL2_PWM1_RST_Pos) |
| #define | SYS_IPRST_CTL2_USBD_RST_Pos (27) |
| #define | SYS_IPRST_CTL2_USBD_RST_Msk (0x1ul << SYS_IPRST_CTL2_USBD_RST_Pos) |
| #define | SYS_IPRST_CTL2_ADC_RST_Pos (28) |
| #define | SYS_IPRST_CTL2_ADC_RST_Msk (0x1ul << SYS_IPRST_CTL2_ADC_RST_Pos) |
| #define | SYS_IPRST_CTL2_I2S_RST_Pos (29) |
| #define | SYS_IPRST_CTL2_I2S_RST_Msk (0x1ul << SYS_IPRST_CTL2_I2S_RST_Pos) |
| #define | SYS_IPRST_CTL2_SC0_RST_Pos (30) |
| #define | SYS_IPRST_CTL2_SC0_RST_Msk (0x1ul << SYS_IPRST_CTL2_SC0_RST_Pos) |
| #define | SYS_IPRST_CTL2_SC1_RST_Pos (31) |
| #define | SYS_IPRST_CTL2_SC1_RST_Msk (0x1ul << SYS_IPRST_CTL2_SC1_RST_Pos) |
| #define | SYS_CPR_HPE_Pos (0) |
| #define | SYS_CPR_HPE_Msk (0x1ul << SYS_CPR_HPE_Pos) |
| #define | SYS_TEMPCTL_VTEMP_EN_Pos (0) |
| #define | SYS_TEMPCTL_VTEMP_EN_Msk (0x1ul << SYS_TEMPCTL_VTEMP_EN_Pos) |
| #define | SYS_PA_L_MFP_PA0_MFP_Pos (0) |
| #define | SYS_PA_L_MFP_PA0_MFP_Msk (0x7ul << SYS_PA_L_MFP_PA0_MFP_Pos) |
| #define | SYS_PA_L_MFP_PA1_MFP_Pos (4) |
| #define | SYS_PA_L_MFP_PA1_MFP_Msk (0x7ul << SYS_PA_L_MFP_PA1_MFP_Pos) |
| #define | SYS_PA_L_MFP_PA2_MFP_Pos (8) |
| #define | SYS_PA_L_MFP_PA2_MFP_Msk (0x7ul << SYS_PA_L_MFP_PA2_MFP_Pos) |
| #define | SYS_PA_L_MFP_PA3_MFP_Pos (12) |
| #define | SYS_PA_L_MFP_PA3_MFP_Msk (0x7ul << SYS_PA_L_MFP_PA3_MFP_Pos) |
| #define | SYS_PA_L_MFP_PA4_MFP_Pos (16) |
| #define | SYS_PA_L_MFP_PA4_MFP_Msk (0x7ul << SYS_PA_L_MFP_PA4_MFP_Pos) |
| #define | SYS_PA_L_MFP_PA5_MFP_Pos (20) |
| #define | SYS_PA_L_MFP_PA5_MFP_Msk (0x7ul << SYS_PA_L_MFP_PA5_MFP_Pos) |
| #define | SYS_PA_L_MFP_PA6_MFP_Pos (24) |
| #define | SYS_PA_L_MFP_PA6_MFP_Msk (0x7ul << SYS_PA_L_MFP_PA6_MFP_Pos) |
| #define | SYS_PA_L_MFP_PA7_MFP_Pos (28) |
| #define | SYS_PA_L_MFP_PA7_MFP_Msk (0x7ul << SYS_PA_L_MFP_PA7_MFP_Pos) |
| #define | SYS_PA_H_MFP_PA8_MFP_Pos (0) |
| #define | SYS_PA_H_MFP_PA8_MFP_Msk (0x7ul << SYS_PA_H_MFP_PA8_MFP_Pos) |
| #define | SYS_PA_H_MFP_PA9_MFP_Pos (4) |
| #define | SYS_PA_H_MFP_PA9_MFP_Msk (0x7ul << SYS_PA_H_MFP_PA9_MFP_Pos) |
| #define | SYS_PA_H_MFP_PA10_MFP_Pos (8) |
| #define | SYS_PA_H_MFP_PA10_MFP_Msk (0x7ul << SYS_PA_H_MFP_PA10_MFP_Pos) |
| #define | SYS_PA_H_MFP_PA11_MFP_Pos (12) |
| #define | SYS_PA_H_MFP_PA11_MFP_Msk (0x7ul << SYS_PA_H_MFP_PA11_MFP_Pos) |
| #define | SYS_PA_H_MFP_PA12_MFP_Pos (16) |
| #define | SYS_PA_H_MFP_PA12_MFP_Msk (0x7ul << SYS_PA_H_MFP_PA12_MFP_Pos) |
| #define | SYS_PA_H_MFP_PA13_MFP_Pos (20) |
| #define | SYS_PA_H_MFP_PA13_MFP_Msk (0x7ul << SYS_PA_H_MFP_PA13_MFP_Pos) |
| #define | SYS_PA_H_MFP_PA14_MFP_Pos (24) |
| #define | SYS_PA_H_MFP_PA14_MFP_Msk (0x7ul << SYS_PA_H_MFP_PA14_MFP_Pos) |
| #define | SYS_PA_H_MFP_PA15_MFP_Pos (28) |
| #define | SYS_PA_H_MFP_PA15_MFP_Msk (0x7ul << SYS_PA_H_MFP_PA15_MFP_Pos) |
| #define | SYS_PB_L_MFP_PB0_MFP_Pos (0) |
| #define | SYS_PB_L_MFP_PB0_MFP_Msk (0x7ul << SYS_PB_L_MFP_PB0_MFP_Pos) |
| #define | SYS_PB_L_MFP_PB1_MFP_Pos (4) |
| #define | SYS_PB_L_MFP_PB1_MFP_Msk (0x7ul << SYS_PB_L_MFP_PB1_MFP_Pos) |
| #define | SYS_PB_L_MFP_PB2_MFP_Pos (8) |
| #define | SYS_PB_L_MFP_PB2_MFP_Msk (0x7ul << SYS_PB_L_MFP_PB2_MFP_Pos) |
| #define | SYS_PB_L_MFP_PB3_MFP_Pos (12) |
| #define | SYS_PB_L_MFP_PB3_MFP_Msk (0x7ul << SYS_PB_L_MFP_PB3_MFP_Pos) |
| #define | SYS_PB_L_MFP_PB4_MFP_Pos (16) |
| #define | SYS_PB_L_MFP_PB4_MFP_Msk (0x7ul << SYS_PB_L_MFP_PB4_MFP_Pos) |
| #define | SYS_PB_L_MFP_PB5_MFP_Pos (20) |
| #define | SYS_PB_L_MFP_PB5_MFP_Msk (0x7ul << SYS_PB_L_MFP_PB5_MFP_Pos) |
| #define | SYS_PB_L_MFP_PB6_MFP_Pos (24) |
| #define | SYS_PB_L_MFP_PB6_MFP_Msk (0x7ul << SYS_PB_L_MFP_PB6_MFP_Pos) |
| #define | SYS_PB_L_MFP_PB7_MFP_Pos (28) |
| #define | SYS_PB_L_MFP_PB7_MFP_Msk (0x7ul << SYS_PB_L_MFP_PB7_MFP_Pos) |
| #define | SYS_PB_H_MFP_PB8_MFP_Pos (0) |
| #define | SYS_PB_H_MFP_PB8_MFP_Msk (0x7ul << SYS_PB_H_MFP_PB8_MFP_Pos) |
| #define | SYS_PB_H_MFP_PB9_MFP_Pos (4) |
| #define | SYS_PB_H_MFP_PB9_MFP_Msk (0x7ul << SYS_PB_H_MFP_PB9_MFP_Pos) |
| #define | SYS_PB_H_MFP_PB10_MFP_Pos (8) |
| #define | SYS_PB_H_MFP_PB10_MFP_Msk (0x7ul << SYS_PB_H_MFP_PB10_MFP_Pos) |
| #define | SYS_PB_H_MFP_PB11_MFP_Pos (12) |
| #define | SYS_PB_H_MFP_PB11_MFP_Msk (0x7ul << SYS_PB_H_MFP_PB11_MFP_Pos) |
| #define | SYS_PB_H_MFP_PB12_MFP_Pos (16) |
| #define | SYS_PB_H_MFP_PB12_MFP_Msk (0x7ul << SYS_PB_H_MFP_PB12_MFP_Pos) |
| #define | SYS_PB_H_MFP_PB13_MFP_Pos (20) |
| #define | SYS_PB_H_MFP_PB13_MFP_Msk (0x7ul << SYS_PB_H_MFP_PB13_MFP_Pos) |
| #define | SYS_PB_H_MFP_PB14_MFP_Pos (24) |
| #define | SYS_PB_H_MFP_PB14_MFP_Msk (0x7ul << SYS_PB_H_MFP_PB14_MFP_Pos) |
| #define | SYS_PB_H_MFP_PB15_MFP_Pos (28) |
| #define | SYS_PB_H_MFP_PB15_MFP_Msk (0x7ul << SYS_PB_H_MFP_PB15_MFP_Pos) |
| #define | SYS_PC_L_MFP_PC0_MFP_Pos (0) |
| #define | SYS_PC_L_MFP_PC0_MFP_Msk (0x7ul << SYS_PC_L_MFP_PC0_MFP_Pos) |
| #define | SYS_PC_L_MFP_PC1_MFP_Pos (4) |
| #define | SYS_PC_L_MFP_PC1_MFP_Msk (0x7ul << SYS_PC_L_MFP_PC1_MFP_Pos) |
| #define | SYS_PC_L_MFP_PC2_MFP_Pos (8) |
| #define | SYS_PC_L_MFP_PC2_MFP_Msk (0x7ul << SYS_PC_L_MFP_PC2_MFP_Pos) |
| #define | SYS_PC_L_MFP_PC3_MFP_Pos (12) |
| #define | SYS_PC_L_MFP_PC3_MFP_Msk (0x7ul << SYS_PC_L_MFP_PC3_MFP_Pos) |
| #define | SYS_PC_L_MFP_PC4_MFP_Pos (16) |
| #define | SYS_PC_L_MFP_PC4_MFP_Msk (0x7ul << SYS_PC_L_MFP_PC4_MFP_Pos) |
| #define | SYS_PC_L_MFP_PC5_MFP_Pos (20) |
| #define | SYS_PC_L_MFP_PC5_MFP_Msk (0x7ul << SYS_PC_L_MFP_PC5_MFP_Pos) |
| #define | SYS_PC_L_MFP_PC6_MFP_Pos (24) |
| #define | SYS_PC_L_MFP_PC6_MFP_Msk (0x7ul << SYS_PC_L_MFP_PC6_MFP_Pos) |
| #define | SYS_PC_L_MFP_PC7_MFP_Pos (28) |
| #define | SYS_PC_L_MFP_PC7_MFP_Msk (0x7ul << SYS_PC_L_MFP_PC7_MFP_Pos) |
| #define | SYS_PC_H_MFP_PC8_MFP_Pos (0) |
| #define | SYS_PC_H_MFP_PC8_MFP_Msk (0x7ul << SYS_PC_H_MFP_PC8_MFP_Pos) |
| #define | SYS_PC_H_MFP_PC9_MFP_Pos (4) |
| #define | SYS_PC_H_MFP_PC9_MFP_Msk (0x7ul << SYS_PC_H_MFP_PC9_MFP_Pos) |
| #define | SYS_PC_H_MFP_PC10_MFP_Pos (8) |
| #define | SYS_PC_H_MFP_PC10_MFP_Msk (0x7ul << SYS_PC_H_MFP_PC10_MFP_Pos) |
| #define | SYS_PC_H_MFP_PC11_MFP_Pos (12) |
| #define | SYS_PC_H_MFP_PC11_MFP_Msk (0x7ul << SYS_PC_H_MFP_PC11_MFP_Pos) |
| #define | SYS_PC_H_MFP_PC12_MFP_Pos (16) |
| #define | SYS_PC_H_MFP_PC12_MFP_Msk (0x7ul << SYS_PC_H_MFP_PC12_MFP_Pos) |
| #define | SYS_PC_H_MFP_PC13_MFP_Pos (20) |
| #define | SYS_PC_H_MFP_PC13_MFP_Msk (0x7ul << SYS_PC_H_MFP_PC13_MFP_Pos) |
| #define | SYS_PC_H_MFP_PC14_MFP_Pos (24) |
| #define | SYS_PC_H_MFP_PC14_MFP_Msk (0x7ul << SYS_PC_H_MFP_PC14_MFP_Pos) |
| #define | SYS_PC_H_MFP_PC15_MFP_Pos (28) |
| #define | SYS_PC_H_MFP_PC15_MFP_Msk (0x7ul << SYS_PC_H_MFP_PC15_MFP_Pos) |
| #define | SYS_PD_L_MFP_PD0_MFP_Pos (0) |
| #define | SYS_PD_L_MFP_PD0_MFP_Msk (0x7ul << SYS_PD_L_MFP_PD0_MFP_Pos) |
| #define | SYS_PD_L_MFP_PD1_MFP_Pos (4) |
| #define | SYS_PD_L_MFP_PD1_MFP_Msk (0x7ul << SYS_PD_L_MFP_PD1_MFP_Pos) |
| #define | SYS_PD_L_MFP_PD2_MFP_Pos (8) |
| #define | SYS_PD_L_MFP_PD2_MFP_Msk (0x7ul << SYS_PD_L_MFP_PD2_MFP_Pos) |
| #define | SYS_PD_L_MFP_PD3_MFP_Pos (12) |
| #define | SYS_PD_L_MFP_PD3_MFP_Msk (0x7ul << SYS_PD_L_MFP_PD3_MFP_Pos) |
| #define | SYS_PD_L_MFP_PD4_MFP_Pos (16) |
| #define | SYS_PD_L_MFP_PD4_MFP_Msk (0x7ul << SYS_PD_L_MFP_PD4_MFP_Pos) |
| #define | SYS_PD_L_MFP_PD5_MFP_Pos (20) |
| #define | SYS_PD_L_MFP_PD5_MFP_Msk (0x7ul << SYS_PD_L_MFP_PD5_MFP_Pos) |
| #define | SYS_PD_L_MFP_PD6_MFP_Pos (24) |
| #define | SYS_PD_L_MFP_PD6_MFP_Msk (0x7ul << SYS_PD_L_MFP_PD6_MFP_Pos) |
| #define | SYS_PD_L_MFP_PD7_MFP_Pos (28) |
| #define | SYS_PD_L_MFP_PD7_MFP_Msk (0x7ul << SYS_PD_L_MFP_PD7_MFP_Pos) |
| #define | SYS_PD_H_MFP_PD8_MFP_Pos (0) |
| #define | SYS_PD_H_MFP_PD8_MFP_Msk (0x7ul << SYS_PD_H_MFP_PD8_MFP_Pos) |
| #define | SYS_PD_H_MFP_PD9_MFP_Pos (4) |
| #define | SYS_PD_H_MFP_PD9_MFP_Msk (0x7ul << SYS_PD_H_MFP_PD9_MFP_Pos) |
| #define | SYS_PD_H_MFP_PD10_MFP_Pos (8) |
| #define | SYS_PD_H_MFP_PD10_MFP_Msk (0x7ul << SYS_PD_H_MFP_PD10_MFP_Pos) |
| #define | SYS_PD_H_MFP_PD11_MFP_Pos (12) |
| #define | SYS_PD_H_MFP_PD11_MFP_Msk (0x7ul << SYS_PD_H_MFP_PD11_MFP_Pos) |
| #define | SYS_PD_H_MFP_PD12_MFP_Pos (16) |
| #define | SYS_PD_H_MFP_PD12_MFP_Msk (0x7ul << SYS_PD_H_MFP_PD12_MFP_Pos) |
| #define | SYS_PD_H_MFP_PD13_MFP_Pos (20) |
| #define | SYS_PD_H_MFP_PD13_MFP_Msk (0x7ul << SYS_PD_H_MFP_PD13_MFP_Pos) |
| #define | SYS_PD_H_MFP_PD14_MFP_Pos (24) |
| #define | SYS_PD_H_MFP_PD14_MFP_Msk (0x7ul << SYS_PD_H_MFP_PD14_MFP_Pos) |
| #define | SYS_PD_H_MFP_PD15_MFP_Pos (28) |
| #define | SYS_PD_H_MFP_PD15_MFP_Msk (0x7ul << SYS_PD_H_MFP_PD15_MFP_Pos) |
| #define | SYS_PE_L_MFP_PE0_MFP_Pos (0) |
| #define | SYS_PE_L_MFP_PE0_MFP_Msk (0x7ul << SYS_PE_L_MFP_PE0_MFP_Pos) |
| #define | SYS_PE_L_MFP_PE1_MFP_Pos (4) |
| #define | SYS_PE_L_MFP_PE1_MFP_Msk (0x7ul << SYS_PE_L_MFP_PE1_MFP_Pos) |
| #define | SYS_PE_L_MFP_PE2_MFP_Pos (8) |
| #define | SYS_PE_L_MFP_PE2_MFP_Msk (0x7ul << SYS_PE_L_MFP_PE2_MFP_Pos) |
| #define | SYS_PE_L_MFP_PE3_MFP_Pos (12) |
| #define | SYS_PE_L_MFP_PE3_MFP_Msk (0x7ul << SYS_PE_L_MFP_PE3_MFP_Pos) |
| #define | SYS_PE_L_MFP_PE4_MFP_Pos (16) |
| #define | SYS_PE_L_MFP_PE4_MFP_Msk (0x7ul << SYS_PE_L_MFP_PE4_MFP_Pos) |
| #define | SYS_PE_L_MFP_PE5_MFP_Pos (20) |
| #define | SYS_PE_L_MFP_PE5_MFP_Msk (0x7ul << SYS_PE_L_MFP_PE5_MFP_Pos) |
| #define | SYS_PE_L_MFP_PE6_MFP_Pos (24) |
| #define | SYS_PE_L_MFP_PE6_MFP_Msk (0x7ul << SYS_PE_L_MFP_PE6_MFP_Pos) |
| #define | SYS_PE_L_MFP_PE7_MFP_Pos (28) |
| #define | SYS_PE_L_MFP_PE7_MFP_Msk (0x7ul << SYS_PE_L_MFP_PE7_MFP_Pos) |
| #define | SYS_PE_H_MFP_PE8_MFP_Pos (0) |
| #define | SYS_PE_H_MFP_PE8_MFP_Msk (0x7ul << SYS_PE_H_MFP_PE8_MFP_Pos) |
| #define | SYS_PE_H_MFP_PE9_MFP_Pos (4) |
| #define | SYS_PE_H_MFP_PE9_MFP_Msk (0x7ul << SYS_PE_H_MFP_PE9_MFP_Pos) |
| #define | SYS_PE_H_MFP_PE10_MFP_Pos (8) |
| #define | SYS_PE_H_MFP_PE10_MFP_Msk (0x7ul << SYS_PE_H_MFP_PE10_MFP_Pos) |
| #define | SYS_PE_H_MFP_PE11_MFP_Pos (12) |
| #define | SYS_PE_H_MFP_PE11_MFP_Msk (0x7ul << SYS_PE_H_MFP_PE11_MFP_Pos) |
| #define | SYS_PE_H_MFP_PE12_MFP_Pos (16) |
| #define | SYS_PE_H_MFP_PE12_MFP_Msk (0x7ul << SYS_PE_H_MFP_PE12_MFP_Pos) |
| #define | SYS_PE_H_MFP_PE13_MFP_Pos (20) |
| #define | SYS_PE_H_MFP_PE13_MFP_Msk (0x7ul << SYS_PE_H_MFP_PE13_MFP_Pos) |
| #define | SYS_PE_H_MFP_PE14_MFP_Pos (24) |
| #define | SYS_PE_H_MFP_PE14_MFP_Msk (0x7ul << SYS_PE_H_MFP_PE14_MFP_Pos) |
| #define | SYS_PE_H_MFP_PE15_MFP_Pos (28) |
| #define | SYS_PE_H_MFP_PE15_MFP_Msk (0x7ul << SYS_PE_H_MFP_PE15_MFP_Pos) |
| #define | SYS_PF_L_MFP_PF0_MFP_Pos (0) |
| #define | SYS_PF_L_MFP_PF0_MFP_Msk (0x7ul << SYS_PF_L_MFP_PF0_MFP_Pos) |
| #define | SYS_PF_L_MFP_PF1_MFP_Pos (4) |
| #define | SYS_PF_L_MFP_PF1_MFP_Msk (0x7ul << SYS_PF_L_MFP_PF1_MFP_Pos) |
| #define | SYS_PF_L_MFP_PF2_MFP_Pos (8) |
| #define | SYS_PF_L_MFP_PF2_MFP_Msk (0x7ul << SYS_PF_L_MFP_PF2_MFP_Pos) |
| #define | SYS_PF_L_MFP_PF3_MFP_Pos (12) |
| #define | SYS_PF_L_MFP_PF3_MFP_Msk (0x7ul << SYS_PF_L_MFP_PF3_MFP_Pos) |
| #define | SYS_PF_L_MFP_PF4_MFP_Pos (16) |
| #define | SYS_PF_L_MFP_PF4_MFP_Msk (0x7ul << SYS_PF_L_MFP_PF4_MFP_Pos) |
| #define | SYS_PF_L_MFP_PF5_MFP_Pos (20) |
| #define | SYS_PF_L_MFP_PF5_MFP_Msk (0x7ul << SYS_PF_L_MFP_PF5_MFP_Pos) |
| #define | SYS_PORCTL_POR_DIS_CODE_Pos (0) |
| #define | SYS_PORCTL_POR_DIS_CODE_Msk (0xfffful << SYS_PORCTL_POR_DIS_CODE_Pos) |
| #define | SYS_BODCTL_BOD17_EN_Pos (0) |
| #define | SYS_BODCTL_BOD17_EN_Msk (0x1ul << SYS_BODCTL_BOD17_EN_Pos) |
| #define | SYS_BODCTL_BOD20_EN_Pos (1) |
| #define | SYS_BODCTL_BOD20_EN_Msk (0x1ul << SYS_BODCTL_BOD20_EN_Pos) |
| #define | SYS_BODCTL_BOD25_EN_Pos (2) |
| #define | SYS_BODCTL_BOD25_EN_Msk (0x1ul << SYS_BODCTL_BOD25_EN_Pos) |
| #define | SYS_BODCTL_BOD17_RST_EN_Pos (4) |
| #define | SYS_BODCTL_BOD17_RST_EN_Msk (0x1ul << SYS_BODCTL_BOD17_RST_EN_Pos) |
| #define | SYS_BODCTL_BOD20_RST_EN_Pos (5) |
| #define | SYS_BODCTL_BOD20_RST_EN_Msk (0x1ul << SYS_BODCTL_BOD20_RST_EN_Pos) |
| #define | SYS_BODCTL_BOD25_RST_EN_Pos (6) |
| #define | SYS_BODCTL_BOD25_RST_EN_Msk (0x1ul << SYS_BODCTL_BOD25_RST_EN_Pos) |
| #define | SYS_BODCTL_BOD17_INT_EN_Pos (8) |
| #define | SYS_BODCTL_BOD17_INT_EN_Msk (0x1ul << SYS_BODCTL_BOD17_INT_EN_Pos) |
| #define | SYS_BODCTL_BOD20_INT_EN_Pos (9) |
| #define | SYS_BODCTL_BOD20_INT_EN_Msk (0x1ul << SYS_BODCTL_BOD20_INT_EN_Pos) |
| #define | SYS_BODCTL_BOD25_INT_EN_Pos (10) |
| #define | SYS_BODCTL_BOD25_INT_EN_Msk (0x1ul << SYS_BODCTL_BOD25_INT_EN_Pos) |
| #define | SYS_BODSTS_BOD_INT_Pos (0) |
| #define | SYS_BODSTS_BOD_INT_Msk (0x1ul << SYS_BODSTS_BOD_INT_Pos) |
| #define | SYS_BODSTS_BOD17_OUT_Pos (1) |
| #define | SYS_BODSTS_BOD17_OUT_Msk (0x1ul << SYS_BODSTS_BOD17_OUT_Pos) |
| #define | SYS_BODSTS_BOD20_OUT_Pos (2) |
| #define | SYS_BODSTS_BOD20_OUT_Msk (0x1ul << SYS_BODSTS_BOD20_OUT_Pos) |
| #define | SYS_BODSTS_BOD25_OUT_Pos (3) |
| #define | SYS_BODSTS_BOD25_OUT_Msk (0x1ul << SYS_BODSTS_BOD25_OUT_Pos) |
| #define | SYS_VREFCTL_BGP_EN_Pos (0) |
| #define | SYS_VREFCTL_BGP_EN_Msk (0x1ul << SYS_VREFCTL_BGP_EN_Pos) |
| #define | SYS_VREFCTL_REG_EN_Pos (1) |
| #define | SYS_VREFCTL_REG_EN_Msk (0x1ul << SYS_VREFCTL_REG_EN_Pos) |
| #define | SYS_VREFCTL_SEL25_Pos (2) |
| #define | SYS_VREFCTL_SEL25_Msk (0x1ul << SYS_VREFCTL_SEL25_Pos) |
| #define | SYS_VREFCTL_EXT_MODE_Pos (3) |
| #define | SYS_VREFCTL_EXT_MODE_Msk (0x1ul << SYS_VREFCTL_EXT_MODE_Pos) |
| #define | SYS_IRCTRIMCTL_TRIM_SEL_Pos (0) |
| #define | SYS_IRCTRIMCTL_TRIM_SEL_Msk (0x3ul << SYS_IRCTRIMCTL_TRIM_SEL_Pos) |
| #define | SYS_IRCTRIMCTL_TRIM_LOOP_Pos (4) |
| #define | SYS_IRCTRIMCTL_TRIM_LOOP_Msk (0x3ul << SYS_IRCTRIMCTL_TRIM_LOOP_Pos) |
| #define | SYS_IRCTRIMCTL_TRIM_RETRY_CNT_Pos (6) |
| #define | SYS_IRCTRIMCTL_TRIM_RETRY_CNT_Msk (0x3ul << SYS_IRCTRIMCTL_TRIM_RETRY_CNT_Pos) |
| #define | SYS_IRCTRIMIEN_TRIM_FAIL_IEN_Pos (1) |
| #define | SYS_IRCTRIMIEN_TRIM_FAIL_IEN_Msk (0x1ul << SYS_IRCTRIMIEN_TRIM_FAIL_IEN_Pos) |
| #define | SYS_IRCTRIMIEN_32K_ERR_IEN_Pos (2) |
| #define | SYS_IRCTRIMIEN_32K_ERR_IEN_Msk (0x1ul << SYS_IRCTRIMIEN_32K_ERR_IEN_Pos) |
| #define | SYS_IRCTRIMINT_FREQ_LOCK_Pos (0) |
| #define | SYS_IRCTRIMINT_FREQ_LOCK_Msk (0x1ul << SYS_IRCTRIMINT_FREQ_LOCK_Pos) |
| #define | SYS_IRCTRIMINT_TRIM_FAIL_INT_Pos (1) |
| #define | SYS_IRCTRIMINT_TRIM_FAIL_INT_Msk (0x1ul << SYS_IRCTRIMINT_TRIM_FAIL_INT_Pos) |
| #define | SYS_IRCTRIMINT_32K_ERR_INT_Pos (2) |
| #define | SYS_IRCTRIMINT_32K_ERR_INT_Msk (0x1ul << SYS_IRCTRIMINT_32K_ERR_INT_Pos) |
| #define | SYS_RegLockAddr_RegUnLock_Pos (0) |
| #define | SYS_RegLockAddr_RegUnLock_Msk (0x1ul << SYS_RegLockAddr_RegUnLock_Pos) |
| #define | GP_PMD_PMD0_Pos (0) |
| #define | GP_PMD_PMD0_Msk (0x3ul << GP_PMD_PMD0_Pos) |
| #define | GP_PMD_PMD1_Pos (2) |
| #define | GP_PMD_PMD1_Msk (0x3ul << GP_PMD_PMD1_Pos) |
| #define | GP_PMD_PMD2_Pos (4) |
| #define | GP_PMD_PMD2_Msk (0x3ul << GP_PMD_PMD2_Pos) |
| #define | GP_PMD_PMD3_Pos (6) |
| #define | GP_PMD_PMD3_Msk (0x3ul << GP_PMD_PMD3_Pos) |
| #define | GP_PMD_PMD4_Pos (8) |
| #define | GP_PMD_PMD4_Msk (0x3ul << GP_PMD_PMD4_Pos) |
| #define | GP_PMD_PMD5_Pos (10) |
| #define | GP_PMD_PMD5_Msk (0x3ul << GP_PMD_PMD5_Pos) |
| #define | GP_PMD_PMD6_Pos (12) |
| #define | GP_PMD_PMD6_Msk (0x3ul << GP_PMD_PMD6_Pos) |
| #define | GP_PMD_PMD7_Pos (14) |
| #define | GP_PMD_PMD7_Msk (0x3ul << GP_PMD_PMD7_Pos) |
| #define | GP_PMD_PMD8_Pos (16) |
| #define | GP_PMD_PMD8_Msk (0x3ul << GP_PMD_PMD8_Pos) |
| #define | GP_PMD_PMD9_Pos (18) |
| #define | GP_PMD_PMD9_Msk (0x3ul << GP_PMD_PMD9_Pos) |
| #define | GP_PMD_PMD10_Pos (20) |
| #define | GP_PMD_PMD10_Msk (0x3ul << GP_PMD_PMD10_Pos) |
| #define | GP_PMD_PMD11_Pos (22) |
| #define | GP_PMD_PMD11_Msk (0x3ul << GP_PMD_PMD11_Pos) |
| #define | GP_PMD_PMD12_Pos (24) |
| #define | GP_PMD_PMD12_Msk (0x3ul << GP_PMD_PMD12_Pos) |
| #define | GP_PMD_PMD13_Pos (26) |
| #define | GP_PMD_PMD13_Msk (0x3ul << GP_PMD_PMD13_Pos) |
| #define | GP_PMD_PMD14_Pos (28) |
| #define | GP_PMD_PMD14_Msk (0x3ul << GP_PMD_PMD14_Pos) |
| #define | GP_PMD_PMD15_Pos (30) |
| #define | GP_PMD_PMD15_Msk (0x3ul << GP_PMD_PMD15_Pos) |
| #define | GP_OFFD_OFFD_Pos (16) |
| #define | GP_OFFD_OFFD_Msk (0xfffful << GP_OFFD_OFFD_Pos) |
| #define | GP_DOUT_DOUT_Pos (0) |
| #define | GP_DOUT_DOUT_Msk (0xfffful << GP_DOUT_DOUT_Pos) |
| #define | GP_DMASK_DMASK_Pos (0) |
| #define | GP_DMASK_DMASK_Msk (0xfffful << GP_DMASK_DMASK_Pos) |
| #define | GP_PIN_PIN_Pos (0) |
| #define | GP_PIN_PIN_Msk (0xfffful << GP_PIN_PIN_Pos) |
| #define | GP_DBEN_DBEN_Pos (0) |
| #define | GP_DBEN_DBEN_Msk (0xfffful << GP_DBEN_DBEN_Pos) |
| #define | GP_IMD_IMD_Pos (0) |
| #define | GP_IMD_IMD_Msk (0xfffful << GP_IMD_IMD_Pos) |
| #define | GP_IER_FIER0_Pos (0) |
| #define | GP_IER_FIER0_Msk (0x1ul << GP_IER_FIER0_Pos) |
| #define | GP_IER_FIER1_Pos (1) |
| #define | GP_IER_FIER1_Msk (0x1ul << GP_IER_FIER1_Pos) |
| #define | GP_IER_FIER2_Pos (2) |
| #define | GP_IER_FIER2_Msk (0x1ul << GP_IER_FIER2_Pos) |
| #define | GP_IER_FIER3_Pos (3) |
| #define | GP_IER_FIER3_Msk (0x1ul << GP_IER_FIER3_Pos) |
| #define | GP_IER_FIER4_Pos (4) |
| #define | GP_IER_FIER4_Msk (0x1ul << GP_IER_FIER4_Pos) |
| #define | GP_IER_FIER5_Pos (5) |
| #define | GP_IER_FIER5_Msk (0x1ul << GP_IER_FIER5_Pos) |
| #define | GP_IER_FIER6_Pos (6) |
| #define | GP_IER_FIER6_Msk (0x1ul << GP_IER_FIER6_Pos) |
| #define | GP_IER_FIER7_Pos (7) |
| #define | GP_IER_FIER7_Msk (0x1ul << GP_IER_FIER7_Pos) |
| #define | GP_IER_FIER8_Pos (8) |
| #define | GP_IER_FIER8_Msk (0x1ul << GP_IER_FIER8_Pos) |
| #define | GP_IER_FIER9_Pos (9) |
| #define | GP_IER_FIER9_Msk (0x1ul << GP_IER_FIER9_Pos) |
| #define | GP_IER_FIER10_Pos (10) |
| #define | GP_IER_FIER10_Msk (0x1ul << GP_IER_FIER10_Pos) |
| #define | GP_IER_FIER11_Pos (11) |
| #define | GP_IER_FIER11_Msk (0x1ul << GP_IER_FIER11_Pos) |
| #define | GP_IER_FIER12_Pos (12) |
| #define | GP_IER_FIER12_Msk (0x1ul << GP_IER_FIER12_Pos) |
| #define | GP_IER_FIER13_Pos (13) |
| #define | GP_IER_FIER13_Msk (0x1ul << GP_IER_FIER13_Pos) |
| #define | GP_IER_FIER14_Pos (14) |
| #define | GP_IER_FIER14_Msk (0x1ul << GP_IER_FIER14_Pos) |
| #define | GP_IER_FIER15_Pos (15) |
| #define | GP_IER_FIER15_Msk (0x1ul << GP_IER_FIER15_Pos) |
| #define | GP_IER_RIER0_Pos (16) |
| #define | GP_IER_RIER0_Msk (0x1ul << GP_IER_RIER0_Pos) |
| #define | GP_IER_RIER1_Pos (17) |
| #define | GP_IER_RIER1_Msk (0x1ul << GP_IER_RIER1_Pos) |
| #define | GP_IER_RIER2_Pos (18) |
| #define | GP_IER_RIER2_Msk (0x1ul << GP_IER_RIER2_Pos) |
| #define | GP_IER_RIER3_Pos (19) |
| #define | GP_IER_RIER3_Msk (0x1ul << GP_IER_RIER3_Pos) |
| #define | GP_IER_RIER4_Pos (20) |
| #define | GP_IER_RIER4_Msk (0x1ul << GP_IER_RIER4_Pos) |
| #define | GP_IER_RIER5_Pos (21) |
| #define | GP_IER_RIER5_Msk (0x1ul << GP_IER_RIER5_Pos) |
| #define | GP_IER_RIER6_Pos (22) |
| #define | GP_IER_RIER6_Msk (0x1ul << GP_IER_RIER6_Pos) |
| #define | GP_IER_RIER7_Pos (23) |
| #define | GP_IER_RIER7_Msk (0x1ul << GP_IER_RIER7_Pos) |
| #define | GP_IER_RIER8_Pos (24) |
| #define | GP_IER_RIER8_Msk (0x1ul << GP_IER_RIER8_Pos) |
| #define | GP_IER_RIER9_Pos (25) |
| #define | GP_IER_RIER9_Msk (0x1ul << GP_IER_RIER9_Pos) |
| #define | GP_IER_RIER10_Pos (26) |
| #define | GP_IER_RIER10_Msk (0x1ul << GP_IER_RIER10_Pos) |
| #define | GP_IER_RIER11_Pos (27) |
| #define | GP_IER_RIER11_Msk (0x1ul << GP_IER_RIER11_Pos) |
| #define | GP_IER_RIER12_Pos (28) |
| #define | GP_IER_RIER12_Msk (0x1ul << GP_IER_RIER12_Pos) |
| #define | GP_IER_RIER13_Pos (29) |
| #define | GP_IER_RIER13_Msk (0x1ul << GP_IER_RIER13_Pos) |
| #define | GP_IER_RIER14_Pos (30) |
| #define | GP_IER_RIER14_Msk (0x1ul << GP_IER_RIER14_Pos) |
| #define | GP_IER_RIER15_Pos (31) |
| #define | GP_IER_RIER15_Msk (0x1ul << GP_IER_RIER15_Pos) |
| #define | GP_ISRC_ISRC_Pos (0) |
| #define | GP_ISRC_ISRC_Msk (0xfffful << GP_ISRC_ISRC_Pos) |
| #define | GP_PUEN_PUEN_Pos (0) |
| #define | GP_PUEN_PUEN_Msk (0xfffful << GP_PUEN_PUEN_Pos) |
| #define | GP_DBNCECON_DBCLKSEL_Pos (0) |
| #define | GP_DBNCECON_DBCLKSEL_Msk (0xful << GP_DBNCECON_DBCLKSEL_Pos) |
| #define | GP_DBNCECON_DBCLKSRC_Pos (4) |
| #define | GP_DBNCECON_DBCLKSRC_Msk (0x1ul << GP_DBNCECON_DBCLKSRC_Pos) |
| #define | GP_DBNCECON_DBCLK_ON_Pos (5) |
| #define | GP_DBNCECON_DBCLK_ON_Msk (0x1ul << GP_DBNCECON_DBCLK_ON_Pos) |
| #define | I2C_CON_IPEN_Pos (0) |
| #define | I2C_CON_IPEN_Msk (0x1ul << I2C_CON_IPEN_Pos) |
| #define | I2C_CON_ACK_Pos (1) |
| #define | I2C_CON_ACK_Msk (0x1ul << I2C_CON_ACK_Pos) |
| #define | I2C_CON_STOP_Pos (2) |
| #define | I2C_CON_STOP_Msk (0x1ul << I2C_CON_STOP_Pos) |
| #define | I2C_CON_START_Pos (3) |
| #define | I2C_CON_START_Msk (0x1ul << I2C_CON_START_Pos) |
| #define | I2C_CON_I2C_STS_Pos (4) |
| #define | I2C_CON_I2C_STS_Msk (0x1ul << I2C_CON_I2C_STS_Pos) |
| #define | I2C_CON_INTEN_Pos (7) |
| #define | I2C_CON_INTEN_Msk (0x1ul << I2C_CON_INTEN_Pos) |
| #define | I2C_INTSTS_INTSTS_Pos (0) |
| #define | I2C_INTSTS_INTSTS_Msk (0x1ul << I2C_INTSTS_INTSTS_Pos) |
| #define | I2C_INTSTS_TIF_Pos (1) |
| #define | I2C_INTSTS_TIF_Msk (0x1ul << I2C_INTSTS_TIF_Pos) |
| #define | I2C_STATUS_STATUS_Pos (0) |
| #define | I2C_STATUS_STATUS_Msk (0xfful << I2C_STATUS_STATUS_Pos) |
| #define | I2C_DIV_CLK_DIV_Pos (0) |
| #define | I2C_DIV_CLK_DIV_Msk (0xfful << I2C_DIV_CLK_DIV_Pos) |
| #define | I2C_TOUT_TOUTEN_Pos (0) |
| #define | I2C_TOUT_TOUTEN_Msk (0x1ul << I2C_TOUT_TOUTEN_Pos) |
| #define | I2C_TOUT_DIV4_Pos (1) |
| #define | I2C_TOUT_DIV4_Msk (0x1ul << I2C_TOUT_DIV4_Pos) |
| #define | I2C_DATA_DATA_Pos (0) |
| #define | I2C_DATA_DATA_Msk (0xfful << I2C_DATA_DATA_Pos) |
| #define | I2C_SADDR0_GCALL_Pos (0) |
| #define | I2C_SADDR0_GCALL_Msk (0x1ul << I2C_SADDR0_GCALL_Pos) |
| #define | I2C_SADDR0_SADDR_Pos (1) |
| #define | I2C_SADDR0_SADDR_Msk (0x7ful << I2C_SADDR0_SADDR_Pos) |
| #define | I2C_SADDR1_GCALL_Pos (0) |
| #define | I2C_SADDR1_GCALL_Msk (0x1ul << I2C_SADDR1_GCALL_Pos) |
| #define | I2C_SADDR1_SADDR_Pos (1) |
| #define | I2C_SADDR1_SADDR_Msk (0x7ful << I2C_SADDR1_SADDR_Pos) |
| #define | I2C_SAMASK0_SAMASK_Pos (1) |
| #define | I2C_SAMASK0_SAMASK_Msk (0x7ful << I2C_SAMASK0_SAMASK_Pos) |
| #define | I2C_SAMASK1_SAMASK_Pos (1) |
| #define | I2C_SAMASK1_SAMASK_Msk (0x7ful << I2C_SAMASK1_SAMASK_Pos) |
| #define | I2S_CTRL_I2SEN_Pos (0) |
| #define | I2S_CTRL_I2SEN_Msk (0x1ul << I2S_CTRL_I2SEN_Pos) |
| #define | I2S_CTRL_TXEN_Pos (1) |
| #define | I2S_CTRL_TXEN_Msk (0x1ul << I2S_CTRL_TXEN_Pos) |
| #define | I2S_CTRL_RXEN_Pos (2) |
| #define | I2S_CTRL_RXEN_Msk (0x1ul << I2S_CTRL_RXEN_Pos) |
| #define | I2S_CTRL_MUTE_Pos (3) |
| #define | I2S_CTRL_MUTE_Msk (0x1ul << I2S_CTRL_MUTE_Pos) |
| #define | I2S_CTRL_WORDWIDTH_Pos (4) |
| #define | I2S_CTRL_WORDWIDTH_Msk (0x3ul << I2S_CTRL_WORDWIDTH_Pos) |
| #define | I2S_CTRL_MONO_Pos (6) |
| #define | I2S_CTRL_MONO_Msk (0x1ul << I2S_CTRL_MONO_Pos) |
| #define | I2S_CTRL_FORMAT_Pos (7) |
| #define | I2S_CTRL_FORMAT_Msk (0x1ul << I2S_CTRL_FORMAT_Pos) |
| #define | I2S_CTRL_SLAVE_Pos (8) |
| #define | I2S_CTRL_SLAVE_Msk (0x1ul << I2S_CTRL_SLAVE_Pos) |
| #define | I2S_CTRL_TXTH_Pos (9) |
| #define | I2S_CTRL_TXTH_Msk (0x7ul << I2S_CTRL_TXTH_Pos) |
| #define | I2S_CTRL_RXTH_Pos (12) |
| #define | I2S_CTRL_RXTH_Msk (0x7ul << I2S_CTRL_RXTH_Pos) |
| #define | I2S_CTRL_MCLKEN_Pos (15) |
| #define | I2S_CTRL_MCLKEN_Msk (0x1ul << I2S_CTRL_MCLKEN_Pos) |
| #define | I2S_CTRL_RCHZCEN_Pos (16) |
| #define | I2S_CTRL_RCHZCEN_Msk (0x1ul << I2S_CTRL_RCHZCEN_Pos) |
| #define | I2S_CTRL_LCHZCEN_Pos (17) |
| #define | I2S_CTRL_LCHZCEN_Msk (0x1ul << I2S_CTRL_LCHZCEN_Pos) |
| #define | I2S_CTRL_CLR_TXFIFO_Pos (18) |
| #define | I2S_CTRL_CLR_TXFIFO_Msk (0x1ul << I2S_CTRL_CLR_TXFIFO_Pos) |
| #define | I2S_CTRL_CLR_RXFIFO_Pos (19) |
| #define | I2S_CTRL_CLR_RXFIFO_Msk (0x1ul << I2S_CTRL_CLR_RXFIFO_Pos) |
| #define | I2S_CTRL_TXDMA_Pos (20) |
| #define | I2S_CTRL_TXDMA_Msk (0x1ul << I2S_CTRL_TXDMA_Pos) |
| #define | I2S_CTRL_RXDMA_Pos (21) |
| #define | I2S_CTRL_RXDMA_Msk (0x1ul << I2S_CTRL_RXDMA_Pos) |
| #define | I2S_CLKDIV_MCLK_DIV_Pos (0) |
| #define | I2S_CLKDIV_MCLK_DIV_Msk (0x7ul << I2S_CLKDIV_MCLK_DIV_Pos) |
| #define | I2S_CLKDIV_BCLK_DIV_Pos (8) |
| #define | I2S_CLKDIV_BCLK_DIV_Msk (0xfful << I2S_CLKDIV_BCLK_DIV_Pos) |
| #define | I2S_INTEN_RXUDFIE_Pos (0) |
| #define | I2S_INTEN_RXUDFIE_Msk (0x1ul << I2S_INTEN_RXUDFIE_Pos) |
| #define | I2S_INTEN_RXOVFIE_Pos (1) |
| #define | I2S_INTEN_RXOVFIE_Msk (0x1ul << I2S_INTEN_RXOVFIE_Pos) |
| #define | I2S_INTEN_RXTHIE_Pos (2) |
| #define | I2S_INTEN_RXTHIE_Msk (0x1ul << I2S_INTEN_RXTHIE_Pos) |
| #define | I2S_INTEN_TXUDFIE_Pos (8) |
| #define | I2S_INTEN_TXUDFIE_Msk (0x1ul << I2S_INTEN_TXUDFIE_Pos) |
| #define | I2S_INTEN_TXOVFIE_Pos (9) |
| #define | I2S_INTEN_TXOVFIE_Msk (0x1ul << I2S_INTEN_TXOVFIE_Pos) |
| #define | I2S_INTEN_TXTHIE_Pos (10) |
| #define | I2S_INTEN_TXTHIE_Msk (0x1ul << I2S_INTEN_TXTHIE_Pos) |
| #define | I2S_INTEN_RZCIE_Pos (11) |
| #define | I2S_INTEN_RZCIE_Msk (0x1ul << I2S_INTEN_RZCIE_Pos) |
| #define | I2S_INTEN_LZCIE_Pos (12) |
| #define | I2S_INTEN_LZCIE_Msk (0x1ul << I2S_INTEN_LZCIE_Pos) |
| #define | I2S_STATUS_I2SINT_Pos (0) |
| #define | I2S_STATUS_I2SINT_Msk (0x1ul << I2S_STATUS_I2SINT_Pos) |
| #define | I2S_STATUS_I2SRXINT_Pos (1) |
| #define | I2S_STATUS_I2SRXINT_Msk (0x1ul << I2S_STATUS_I2SRXINT_Pos) |
| #define | I2S_STATUS_I2STXINT_Pos (2) |
| #define | I2S_STATUS_I2STXINT_Msk (0x1ul << I2S_STATUS_I2STXINT_Pos) |
| #define | I2S_STATUS_RIGHT_Pos (3) |
| #define | I2S_STATUS_RIGHT_Msk (0x1ul << I2S_STATUS_RIGHT_Pos) |
| #define | I2S_STATUS_RXUDF_Pos (8) |
| #define | I2S_STATUS_RXUDF_Msk (0x1ul << I2S_STATUS_RXUDF_Pos) |
| #define | I2S_STATUS_RXOVF_Pos (9) |
| #define | I2S_STATUS_RXOVF_Msk (0x1ul << I2S_STATUS_RXOVF_Pos) |
| #define | I2S_STATUS_RXTHF_Pos (10) |
| #define | I2S_STATUS_RXTHF_Msk (0x1ul << I2S_STATUS_RXTHF_Pos) |
| #define | I2S_STATUS_RXFULL_Pos (11) |
| #define | I2S_STATUS_RXFULL_Msk (0x1ul << I2S_STATUS_RXFULL_Pos) |
| #define | I2S_STATUS_RXEMPTY_Pos (12) |
| #define | I2S_STATUS_RXEMPTY_Msk (0x1ul << I2S_STATUS_RXEMPTY_Pos) |
| #define | I2S_STATUS_TXUDF_Pos (16) |
| #define | I2S_STATUS_TXUDF_Msk (0x1ul << I2S_STATUS_TXUDF_Pos) |
| #define | I2S_STATUS_TXOVF_Pos (17) |
| #define | I2S_STATUS_TXOVF_Msk (0x1ul << I2S_STATUS_TXOVF_Pos) |
| #define | I2S_STATUS_TXTHF_Pos (18) |
| #define | I2S_STATUS_TXTHF_Msk (0x1ul << I2S_STATUS_TXTHF_Pos) |
| #define | I2S_STATUS_TXFULL_Pos (19) |
| #define | I2S_STATUS_TXFULL_Msk (0x1ul << I2S_STATUS_TXFULL_Pos) |
| #define | I2S_STATUS_TXEMPTY_Pos (20) |
| #define | I2S_STATUS_TXEMPTY_Msk (0x1ul << I2S_STATUS_TXEMPTY_Pos) |
| #define | I2S_STATUS_TXBUSY_Pos (21) |
| #define | I2S_STATUS_TXBUSY_Msk (0x1ul << I2S_STATUS_TXBUSY_Pos) |
| #define | I2S_STATUS_RZCF_Pos (22) |
| #define | I2S_STATUS_RZCF_Msk (0x1ul << I2S_STATUS_RZCF_Pos) |
| #define | I2S_STATUS_LZCF_Pos (23) |
| #define | I2S_STATUS_LZCF_Msk (0x1ul << I2S_STATUS_LZCF_Pos) |
| #define | I2S_STATUS_RX_LEVEL_Pos (24) |
| #define | I2S_STATUS_RX_LEVEL_Msk (0xful << I2S_STATUS_RX_LEVEL_Pos) |
| #define | I2S_STATUS_TX_LEVEL_Pos (28) |
| #define | I2S_STATUS_TX_LEVEL_Msk (0xful << I2S_STATUS_TX_LEVEL_Pos) |
| #define | I2S_TXFIFO_TXFIFO_Pos (0) |
| #define | I2S_TXFIFO_TXFIFO_Msk (0xfffffffful << I2S_TXFIFO_TXFIFO_Pos) |
| #define | I2S_RXFIFO_RXFIFO_Pos (0) |
| #define | I2S_RXFIFO_RXFIFO_Msk (0xfffffffful << I2S_RXFIFO_RXFIFO_Pos) |
| #define | PWM_PRES_CP01_Pos (0) |
| #define | PWM_PRES_CP01_Msk (0xfful << PWM_PRES_CP01_Pos) |
| #define | PWM_PRES_CP23_Pos (8) |
| #define | PWM_PRES_CP23_Msk (0xfful << PWM_PRES_CP23_Pos) |
| #define | PWM_PRES_DZ01_Pos (16) |
| #define | PWM_PRES_DZ01_Msk (0xfful << PWM_PRES_DZ01_Pos) |
| #define | PWM_PRES_DZ23_Pos (24) |
| #define | PWM_PRES_DZ23_Msk (0xfful << PWM_PRES_DZ23_Pos) |
| #define | PWM_CLKSEL_CLKSEL0_Pos (0) |
| #define | PWM_CLKSEL_CLKSEL0_Msk (0x7ul << PWM_CLKSEL_CLKSEL0_Pos) |
| #define | PWM_CLKSEL_CLKSEL1_Pos (4) |
| #define | PWM_CLKSEL_CLKSEL1_Msk (0x7ul << PWM_CLKSEL_CLKSEL1_Pos) |
| #define | PWM_CLKSEL_CLKSEL2_Pos (8) |
| #define | PWM_CLKSEL_CLKSEL2_Msk (0x7ul << PWM_CLKSEL_CLKSEL2_Pos) |
| #define | PWM_CLKSEL_CLKSEL3_Pos (12) |
| #define | PWM_CLKSEL_CLKSEL3_Msk (0x7ul << PWM_CLKSEL_CLKSEL3_Pos) |
| #define | PWM_CTL_CH0EN_Pos (0) |
| #define | PWM_CTL_CH0EN_Msk (0x1ul << PWM_CTL_CH0EN_Pos) |
| #define | PWM_CTL_CH0INV_Pos (2) |
| #define | PWM_CTL_CH0INV_Msk (0x1ul << PWM_CTL_CH0INV_Pos) |
| #define | PWM_CTL_CH0MOD_Pos (3) |
| #define | PWM_CTL_CH0MOD_Msk (0x1ul << PWM_CTL_CH0MOD_Pos) |
| #define | PWM_CTL_DZEN01_Pos (4) |
| #define | PWM_CTL_DZEN01_Msk (0x1ul << PWM_CTL_DZEN01_Pos) |
| #define | PWM_CTL_DZEN23_Pos (5) |
| #define | PWM_CTL_DZEN23_Msk (0x1ul << PWM_CTL_DZEN23_Pos) |
| #define | PWM_CTL_CH1EN_Pos (8) |
| #define | PWM_CTL_CH1EN_Msk (0x1ul << PWM_CTL_CH1EN_Pos) |
| #define | PWM_CTL_CH1INV_Pos (10) |
| #define | PWM_CTL_CH1INV_Msk (0x1ul << PWM_CTL_CH1INV_Pos) |
| #define | PWM_CTL_CH1MOD_Pos (11) |
| #define | PWM_CTL_CH1MOD_Msk (0x1ul << PWM_CTL_CH1MOD_Pos) |
| #define | PWM_CTL_CH2EN_Pos (16) |
| #define | PWM_CTL_CH2EN_Msk (0x1ul << PWM_CTL_CH2EN_Pos) |
| #define | PWM_CTL_CH2INV_Pos (18) |
| #define | PWM_CTL_CH2INV_Msk (0x1ul << PWM_CTL_CH2INV_Pos) |
| #define | PWM_CTL_CH2MOD_Pos (19) |
| #define | PWM_CTL_CH2MOD_Msk (0x1ul << PWM_CTL_CH2MOD_Pos) |
| #define | PWM_CTL_CH3EN_Pos (24) |
| #define | PWM_CTL_CH3EN_Msk (0x1ul << PWM_CTL_CH3EN_Pos) |
| #define | PWM_CTL_CH3INV_Pos (26) |
| #define | PWM_CTL_CH3INV_Msk (0x1ul << PWM_CTL_CH3INV_Pos) |
| #define | PWM_CTL_CH3MOD_Pos (27) |
| #define | PWM_CTL_CH3MOD_Msk (0x1ul << PWM_CTL_CH3MOD_Pos) |
| #define | PWM_INTEN_TMIE0_Pos (0) |
| #define | PWM_INTEN_TMIE0_Msk (0x1ul << PWM_INTEN_TMIE0_Pos) |
| #define | PWM_INTEN_TMIE1_Pos (1) |
| #define | PWM_INTEN_TMIE1_Msk (0x1ul << PWM_INTEN_TMIE1_Pos) |
| #define | PWM_INTEN_TMIE2_Pos (2) |
| #define | PWM_INTEN_TMIE2_Msk (0x1ul << PWM_INTEN_TMIE2_Pos) |
| #define | PWM_INTEN_TMIE3_Pos (3) |
| #define | PWM_INTEN_TMIE3_Msk (0x1ul << PWM_INTEN_TMIE3_Pos) |
| #define | PWM_INTSTS_TMINT0_Pos (0) |
| #define | PWM_INTSTS_TMINT0_Msk (0x1ul << PWM_INTSTS_TMINT0_Pos) |
| #define | PWM_INTSTS_TMINT1_Pos (1) |
| #define | PWM_INTSTS_TMINT1_Msk (0x1ul << PWM_INTSTS_TMINT1_Pos) |
| #define | PWM_INTSTS_TMINT2_Pos (2) |
| #define | PWM_INTSTS_TMINT2_Msk (0x1ul << PWM_INTSTS_TMINT2_Pos) |
| #define | PWM_INTSTS_TMINT3_Pos (3) |
| #define | PWM_INTSTS_TMINT3_Msk (0x1ul << PWM_INTSTS_TMINT3_Pos) |
| #define | PWM_INTSTS_Duty0Syncflag_Pos (4) |
| #define | PWM_INTSTS_Duty0Syncflag_Msk (0x1ul << PWM_INTSTS_Duty0Syncflag_Pos) |
| #define | PWM_INTSTS_Duty1Syncflag_Pos (5) |
| #define | PWM_INTSTS_Duty1Syncflag_Msk (0x1ul << PWM_INTSTS_Duty1Syncflag_Pos) |
| #define | PWM_INTSTS_Duty2Syncflag_Pos (6) |
| #define | PWM_INTSTS_Duty2Syncflag_Msk (0x1ul << PWM_INTSTS_Duty2Syncflag_Pos) |
| #define | PWM_INTSTS_Duty3Syncflag_Pos (7) |
| #define | PWM_INTSTS_Duty3Syncflag_Msk (0x1ul << PWM_INTSTS_Duty3Syncflag_Pos) |
| #define | PWM_INTSTS_PresSyncFlag_Pos (8) |
| #define | PWM_INTSTS_PresSyncFlag_Msk (0x1ul << PWM_INTSTS_PresSyncFlag_Pos) |
| #define | PWM_OE_CH0_OE_Pos (0) |
| #define | PWM_OE_CH0_OE_Msk (0x1ul << PWM_OE_CH0_OE_Pos) |
| #define | PWM_OE_CH1_OE_Pos (1) |
| #define | PWM_OE_CH1_OE_Msk (0x1ul << PWM_OE_CH1_OE_Pos) |
| #define | PWM_OE_CH2_OE_Pos (2) |
| #define | PWM_OE_CH2_OE_Msk (0x1ul << PWM_OE_CH2_OE_Pos) |
| #define | PWM_OE_CH3_OE_Pos (3) |
| #define | PWM_OE_CH3_OE_Msk (0x1ul << PWM_OE_CH3_OE_Pos) |
| #define | PWM_DUTY0_CN_Pos (0) |
| #define | PWM_DUTY0_CN_Msk (0xfffful << PWM_DUTY0_CN_Pos) |
| #define | PWM_DUTY0_CM_Pos (16) |
| #define | PWM_DUTY0_CM_Msk (0xfffful << PWM_DUTY0_CM_Pos) |
| #define | PWM_DATA0_PWMx_DATAy15_0_Pos (0) |
| #define | PWM_DATA0_PWMx_DATAy15_0_Msk (0xfffful << PWM_DATA0_PWMx_DATAy15_0_Pos) |
| #define | PWM_DATA0_PWMx_DATAy30_16_Pos (16) |
| #define | PWM_DATA0_PWMx_DATAy30_16_Msk (0x7ffful << PWM_DATA0_PWMx_DATAy30_16_Pos) |
| #define | PWM_DATA0_sync_Pos (31) |
| #define | PWM_DATA0_sync_Msk (0x1ul << PWM_DATA0_sync_Pos) |
| #define | PWM_DUTY1_CN_Pos (0) |
| #define | PWM_DUTY1_CN_Msk (0xfffful << PWM_DUTY1_CN_Pos) |
| #define | PWM_DUTY1_CM_Pos (16) |
| #define | PWM_DUTY1_CM_Msk (0xfffful << PWM_DUTY1_CM_Pos) |
| #define | PWM_DATA1_PWMx_DATAy15_0_Pos (0) |
| #define | PWM_DATA1_PWMx_DATAy15_0_Msk (0xfffful << PWM_DATA1_PWMx_DATAy15_0_Pos) |
| #define | PWM_DATA1_PWMx_DATAy30_16_Pos (16) |
| #define | PWM_DATA1_PWMx_DATAy30_16_Msk (0x7ffful << PWM_DATA1_PWMx_DATAy30_16_Pos) |
| #define | PWM_DATA1_sync_Pos (31) |
| #define | PWM_DATA1_sync_Msk (0x1ul << PWM_DATA1_sync_Pos) |
| #define | PWM_DUTY2_CN_Pos (0) |
| #define | PWM_DUTY2_CN_Msk (0xfffful << PWM_DUTY2_CN_Pos) |
| #define | PWM_DUTY2_CM_Pos (16) |
| #define | PWM_DUTY2_CM_Msk (0xfffful << PWM_DUTY2_CM_Pos) |
| #define | PWM_DATA2_PWMx_DATAy15_0_Pos (0) |
| #define | PWM_DATA2_PWMx_DATAy15_0_Msk (0xfffful << PWM_DATA2_PWMx_DATAy15_0_Pos) |
| #define | PWM_DATA2_PWMx_DATAy30_16_Pos (16) |
| #define | PWM_DATA2_PWMx_DATAy30_16_Msk (0x7ffful << PWM_DATA2_PWMx_DATAy30_16_Pos) |
| #define | PWM_DATA2_sync_Pos (31) |
| #define | PWM_DATA2_sync_Msk (0x1ul << PWM_DATA2_sync_Pos) |
| #define | PWM_DUTY3_CN_Pos (0) |
| #define | PWM_DUTY3_CN_Msk (0xfffful << PWM_DUTY3_CN_Pos) |
| #define | PWM_DUTY3_CM_Pos (16) |
| #define | PWM_DUTY3_CM_Msk (0xfffful << PWM_DUTY3_CM_Pos) |
| #define | PWM_DATA3_PWMx_DATAy15_0_Pos (0) |
| #define | PWM_DATA3_PWMx_DATAy15_0_Msk (0xfffful << PWM_DATA3_PWMx_DATAy15_0_Pos) |
| #define | PWM_DATA3_PWMx_DATAy30_16_Pos (16) |
| #define | PWM_DATA3_PWMx_DATAy30_16_Msk (0x7ffful << PWM_DATA3_PWMx_DATAy30_16_Pos) |
| #define | PWM_DATA3_sync_Pos (31) |
| #define | PWM_DATA3_sync_Msk (0x1ul << PWM_DATA3_sync_Pos) |
| #define | PWM_CAPCTL_INV0_Pos (0) |
| #define | PWM_CAPCTL_INV0_Msk (0x1ul << PWM_CAPCTL_INV0_Pos) |
| #define | PWM_CAPCTL_CAPCH0EN_Pos (1) |
| #define | PWM_CAPCTL_CAPCH0EN_Msk (0x1ul << PWM_CAPCTL_CAPCH0EN_Pos) |
| #define | PWM_CAPCTL_CAPCH0PADEN_Pos (2) |
| #define | PWM_CAPCTL_CAPCH0PADEN_Msk (0x1ul << PWM_CAPCTL_CAPCH0PADEN_Pos) |
| #define | PWM_CAPCTL_CH0PDMAEN_Pos (3) |
| #define | PWM_CAPCTL_CH0PDMAEN_Msk (0x1ul << PWM_CAPCTL_CH0PDMAEN_Pos) |
| #define | PWM_CAPCTL_PDMACAPMOD0_Pos (4) |
| #define | PWM_CAPCTL_PDMACAPMOD0_Msk (0x3ul << PWM_CAPCTL_PDMACAPMOD0_Pos) |
| #define | PWM_CAPCTL_CAPRELOADREN0_Pos (6) |
| #define | PWM_CAPCTL_CAPRELOADREN0_Msk (0x1ul << PWM_CAPCTL_CAPRELOADREN0_Pos) |
| #define | PWM_CAPCTL_CAPRELOADFEN0_Pos (7) |
| #define | PWM_CAPCTL_CAPRELOADFEN0_Msk (0x1ul << PWM_CAPCTL_CAPRELOADFEN0_Pos) |
| #define | PWM_CAPCTL_INV1_Pos (8) |
| #define | PWM_CAPCTL_INV1_Msk (0x1ul << PWM_CAPCTL_INV1_Pos) |
| #define | PWM_CAPCTL_CAPCH1EN_Pos (9) |
| #define | PWM_CAPCTL_CAPCH1EN_Msk (0x1ul << PWM_CAPCTL_CAPCH1EN_Pos) |
| #define | PWM_CAPCTL_CAPCH1PADEN_Pos (10) |
| #define | PWM_CAPCTL_CAPCH1PADEN_Msk (0x1ul << PWM_CAPCTL_CAPCH1PADEN_Pos) |
| #define | PWM_CAPCTL_CH0RFORDER_Pos (12) |
| #define | PWM_CAPCTL_CH0RFORDER_Msk (0x1ul << PWM_CAPCTL_CH0RFORDER_Pos) |
| #define | PWM_CAPCTL_CH01CASK_Pos (13) |
| #define | PWM_CAPCTL_CH01CASK_Msk (0x1ul << PWM_CAPCTL_CH01CASK_Pos) |
| #define | PWM_CAPCTL_CAPRELOADREN1_Pos (14) |
| #define | PWM_CAPCTL_CAPRELOADREN1_Msk (0x1ul << PWM_CAPCTL_CAPRELOADREN1_Pos) |
| #define | PWM_CAPCTL_CAPRELOADFEN1_Pos (15) |
| #define | PWM_CAPCTL_CAPRELOADFEN1_Msk (0x1ul << PWM_CAPCTL_CAPRELOADFEN1_Pos) |
| #define | PWM_CAPCTL_INV2_Pos (16) |
| #define | PWM_CAPCTL_INV2_Msk (0x1ul << PWM_CAPCTL_INV2_Pos) |
| #define | PWM_CAPCTL_CAPCH2EN_Pos (17) |
| #define | PWM_CAPCTL_CAPCH2EN_Msk (0x1ul << PWM_CAPCTL_CAPCH2EN_Pos) |
| #define | PWM_CAPCTL_CAPCH2PADEN_Pos (18) |
| #define | PWM_CAPCTL_CAPCH2PADEN_Msk (0x1ul << PWM_CAPCTL_CAPCH2PADEN_Pos) |
| #define | PWM_CAPCTL_CH2PDMAEN_Pos (19) |
| #define | PWM_CAPCTL_CH2PDMAEN_Msk (0x1ul << PWM_CAPCTL_CH2PDMAEN_Pos) |
| #define | PWM_CAPCTL_PDMACAPMOD2_Pos (20) |
| #define | PWM_CAPCTL_PDMACAPMOD2_Msk (0x3ul << PWM_CAPCTL_PDMACAPMOD2_Pos) |
| #define | PWM_CAPCTL_CAPRELOADREN2_Pos (22) |
| #define | PWM_CAPCTL_CAPRELOADREN2_Msk (0x1ul << PWM_CAPCTL_CAPRELOADREN2_Pos) |
| #define | PWM_CAPCTL_CAPRELOADFEN2_Pos (23) |
| #define | PWM_CAPCTL_CAPRELOADFEN2_Msk (0x1ul << PWM_CAPCTL_CAPRELOADFEN2_Pos) |
| #define | PWM_CAPCTL_INV3_Pos (24) |
| #define | PWM_CAPCTL_INV3_Msk (0x1ul << PWM_CAPCTL_INV3_Pos) |
| #define | PWM_CAPCTL_CAPCH3EN_Pos (25) |
| #define | PWM_CAPCTL_CAPCH3EN_Msk (0x1ul << PWM_CAPCTL_CAPCH3EN_Pos) |
| #define | PWM_CAPCTL_CAPCH3PADEN_Pos (26) |
| #define | PWM_CAPCTL_CAPCH3PADEN_Msk (0x1ul << PWM_CAPCTL_CAPCH3PADEN_Pos) |
| #define | PWM_CAPCTL_CH2RFORDER_Pos (28) |
| #define | PWM_CAPCTL_CH2RFORDER_Msk (0x1ul << PWM_CAPCTL_CH2RFORDER_Pos) |
| #define | PWM_CAPCTL_CH23CASK_Pos (29) |
| #define | PWM_CAPCTL_CH23CASK_Msk (0x1ul << PWM_CAPCTL_CH23CASK_Pos) |
| #define | PWM_CAPCTL_CAPRELOADREN3_Pos (30) |
| #define | PWM_CAPCTL_CAPRELOADREN3_Msk (0x1ul << PWM_CAPCTL_CAPRELOADREN3_Pos) |
| #define | PWM_CAPCTL_CAPRELOADFEN3_Pos (31) |
| #define | PWM_CAPCTL_CAPRELOADFEN3_Msk (0x1ul << PWM_CAPCTL_CAPRELOADFEN3_Pos) |
| #define | PWM_CAPINTEN_CRL_IE0_Pos (0) |
| #define | PWM_CAPINTEN_CRL_IE0_Msk (0x1ul << PWM_CAPINTEN_CRL_IE0_Pos) |
| #define | PWM_CAPINTEN_CFL_IE0_Pos (1) |
| #define | PWM_CAPINTEN_CFL_IE0_Msk (0x1ul << PWM_CAPINTEN_CFL_IE0_Pos) |
| #define | PWM_CAPINTEN_CRL_IE1_Pos (8) |
| #define | PWM_CAPINTEN_CRL_IE1_Msk (0x1ul << PWM_CAPINTEN_CRL_IE1_Pos) |
| #define | PWM_CAPINTEN_CFL_IE1_Pos (9) |
| #define | PWM_CAPINTEN_CFL_IE1_Msk (0x1ul << PWM_CAPINTEN_CFL_IE1_Pos) |
| #define | PWM_CAPINTEN_CRL_IE2_Pos (16) |
| #define | PWM_CAPINTEN_CRL_IE2_Msk (0x1ul << PWM_CAPINTEN_CRL_IE2_Pos) |
| #define | PWM_CAPINTEN_CFL_IE2_Pos (17) |
| #define | PWM_CAPINTEN_CFL_IE2_Msk (0x1ul << PWM_CAPINTEN_CFL_IE2_Pos) |
| #define | PWM_CAPINTEN_CRL_IE3_Pos (24) |
| #define | PWM_CAPINTEN_CRL_IE3_Msk (0x1ul << PWM_CAPINTEN_CRL_IE3_Pos) |
| #define | PWM_CAPINTEN_CFL_IE3_Pos (25) |
| #define | PWM_CAPINTEN_CFL_IE3_Msk (0x1ul << PWM_CAPINTEN_CFL_IE3_Pos) |
| #define | PWM_CAPINTSTS_CAPIF0_Pos (0) |
| #define | PWM_CAPINTSTS_CAPIF0_Msk (0x1ul << PWM_CAPINTSTS_CAPIF0_Pos) |
| #define | PWM_CAPINTSTS_CRLI0_Pos (1) |
| #define | PWM_CAPINTSTS_CRLI0_Msk (0x1ul << PWM_CAPINTSTS_CRLI0_Pos) |
| #define | PWM_CAPINTSTS_CFLRI0_Pos (2) |
| #define | PWM_CAPINTSTS_CFLRI0_Msk (0x1ul << PWM_CAPINTSTS_CFLRI0_Pos) |
| #define | PWM_CAPINTSTS_CAPOVR0_Pos (3) |
| #define | PWM_CAPINTSTS_CAPOVR0_Msk (0x1ul << PWM_CAPINTSTS_CAPOVR0_Pos) |
| #define | PWM_CAPINTSTS_CAPOVF0_Pos (4) |
| #define | PWM_CAPINTSTS_CAPOVF0_Msk (0x1ul << PWM_CAPINTSTS_CAPOVF0_Pos) |
| #define | PWM_CAPINTSTS_CAPIF1_Pos (8) |
| #define | PWM_CAPINTSTS_CAPIF1_Msk (0x1ul << PWM_CAPINTSTS_CAPIF1_Pos) |
| #define | PWM_CAPINTSTS_CRLI1_Pos (9) |
| #define | PWM_CAPINTSTS_CRLI1_Msk (0x1ul << PWM_CAPINTSTS_CRLI1_Pos) |
| #define | PWM_CAPINTSTS_CFLI1_Pos (10) |
| #define | PWM_CAPINTSTS_CFLI1_Msk (0x1ul << PWM_CAPINTSTS_CFLI1_Pos) |
| #define | PWM_CAPINTSTS_CAPOVR1_Pos (11) |
| #define | PWM_CAPINTSTS_CAPOVR1_Msk (0x1ul << PWM_CAPINTSTS_CAPOVR1_Pos) |
| #define | PWM_CAPINTSTS_CAPOVF1_Pos (12) |
| #define | PWM_CAPINTSTS_CAPOVF1_Msk (0x1ul << PWM_CAPINTSTS_CAPOVF1_Pos) |
| #define | PWM_CAPINTSTS_CAPIF2_Pos (16) |
| #define | PWM_CAPINTSTS_CAPIF2_Msk (0x1ul << PWM_CAPINTSTS_CAPIF2_Pos) |
| #define | PWM_CAPINTSTS_CRLI2_Pos (17) |
| #define | PWM_CAPINTSTS_CRLI2_Msk (0x1ul << PWM_CAPINTSTS_CRLI2_Pos) |
| #define | PWM_CAPINTSTS_CFLI2_Pos (18) |
| #define | PWM_CAPINTSTS_CFLI2_Msk (0x1ul << PWM_CAPINTSTS_CFLI2_Pos) |
| #define | PWM_CAPINTSTS_CAPOVR2_Pos (19) |
| #define | PWM_CAPINTSTS_CAPOVR2_Msk (0x1ul << PWM_CAPINTSTS_CAPOVR2_Pos) |
| #define | PWM_CAPINTSTS_CAPOVF2_Pos (20) |
| #define | PWM_CAPINTSTS_CAPOVF2_Msk (0x1ul << PWM_CAPINTSTS_CAPOVF2_Pos) |
| #define | PWM_CAPINTSTS_CAPIF3_Pos (24) |
| #define | PWM_CAPINTSTS_CAPIF3_Msk (0x1ul << PWM_CAPINTSTS_CAPIF3_Pos) |
| #define | PWM_CAPINTSTS_CRLI3_Pos (25) |
| #define | PWM_CAPINTSTS_CRLI3_Msk (0x1ul << PWM_CAPINTSTS_CRLI3_Pos) |
| #define | PWM_CAPINTSTS_CFLI3_Pos (26) |
| #define | PWM_CAPINTSTS_CFLI3_Msk (0x1ul << PWM_CAPINTSTS_CFLI3_Pos) |
| #define | PWM_CAPINTSTS_CAPOVR3_Pos (27) |
| #define | PWM_CAPINTSTS_CAPOVR3_Msk (0x1ul << PWM_CAPINTSTS_CAPOVR3_Pos) |
| #define | PWM_CAPINTSTS_CAPOVF3_Pos (28) |
| #define | PWM_CAPINTSTS_CAPOVF3_Msk (0x1ul << PWM_CAPINTSTS_CAPOVF3_Pos) |
| #define | PWM_CRL0_CRL15_0_Pos (0) |
| #define | PWM_CRL0_CRL15_0_Msk (0xfffful << PWM_CRL0_CRL15_0_Pos) |
| #define | PWM_CRL0_CRL31_16_Pos (16) |
| #define | PWM_CRL0_CRL31_16_Msk (0xfffful << PWM_CRL0_CRL31_16_Pos) |
| #define | PWM_CFL0_CFL15_0_Pos (0) |
| #define | PWM_CFL0_CFL15_0_Msk (0xfffful << PWM_CFL0_CFL15_0_Pos) |
| #define | PWM_CFL0_CFL31_16_Pos (16) |
| #define | PWM_CFL0_CFL31_16_Msk (0xfffful << PWM_CFL0_CFL31_16_Pos) |
| #define | PWM_CRL1_CRL15_0_Pos (0) |
| #define | PWM_CRL1_CRL15_0_Msk (0xfffful << PWM_CRL1_CRL15_0_Pos) |
| #define | PWM_CRL1_CRL31_16_Pos (16) |
| #define | PWM_CRL1_CRL31_16_Msk (0xfffful << PWM_CRL1_CRL31_16_Pos) |
| #define | PWM_CFL1_CFL15_0_Pos (0) |
| #define | PWM_CFL1_CFL15_0_Msk (0xfffful << PWM_CFL1_CFL15_0_Pos) |
| #define | PWM_CFL1_CFL31_16_Pos (16) |
| #define | PWM_CFL1_CFL31_16_Msk (0xfffful << PWM_CFL1_CFL31_16_Pos) |
| #define | PWM_CRL2_CRL15_0_Pos (0) |
| #define | PWM_CRL2_CRL15_0_Msk (0xfffful << PWM_CRL2_CRL15_0_Pos) |
| #define | PWM_CRL2_CRL31_16_Pos (16) |
| #define | PWM_CRL2_CRL31_16_Msk (0xfffful << PWM_CRL2_CRL31_16_Pos) |
| #define | PWM_CFL2_CFL15_0_Pos (0) |
| #define | PWM_CFL2_CFL15_0_Msk (0xfffful << PWM_CFL2_CFL15_0_Pos) |
| #define | PWM_CFL2_CFL31_16_Pos (16) |
| #define | PWM_CFL2_CFL31_16_Msk (0xfffful << PWM_CFL2_CFL31_16_Pos) |
| #define | PWM_CRL3_CRL15_0_Pos (0) |
| #define | PWM_CRL3_CRL15_0_Msk (0xfffful << PWM_CRL3_CRL15_0_Pos) |
| #define | PWM_CRL3_CRL31_16_Pos (16) |
| #define | PWM_CRL3_CRL31_16_Msk (0xfffful << PWM_CRL3_CRL31_16_Pos) |
| #define | PWM_CFL3_CFL15_0_Pos (0) |
| #define | PWM_CFL3_CFL15_0_Msk (0xfffful << PWM_CFL3_CFL15_0_Pos) |
| #define | PWM_CFL3_CFL31_16_Pos (16) |
| #define | PWM_CFL3_CFL31_16_Msk (0xfffful << PWM_CFL3_CFL31_16_Pos) |
| #define | PWM_PDMACH0_Captureddata7_0_Pos (0) |
| #define | PWM_PDMACH0_Captureddata7_0_Msk (0xfful << PWM_PDMACH0_Captureddata7_0_Pos) |
| #define | PWM_PDMACH0_Captureddata15_8_Pos (8) |
| #define | PWM_PDMACH0_Captureddata15_8_Msk (0xfful << PWM_PDMACH0_Captureddata15_8_Pos) |
| #define | PWM_PDMACH0_Captureddata23_16_Pos (16) |
| #define | PWM_PDMACH0_Captureddata23_16_Msk (0xfful << PWM_PDMACH0_Captureddata23_16_Pos) |
| #define | PWM_PDMACH0_Captureddata31_24_Pos (24) |
| #define | PWM_PDMACH0_Captureddata31_24_Msk (0xfful << PWM_PDMACH0_Captureddata31_24_Pos) |
| #define | PWM_PDMACH2_Captureddata7_0_Pos (0) |
| #define | PWM_PDMACH2_Captureddata7_0_Msk (0xfful << PWM_PDMACH2_Captureddata7_0_Pos) |
| #define | PWM_PDMACH2_Captureddata15_8_Pos (8) |
| #define | PWM_PDMACH2_Captureddata15_8_Msk (0xfful << PWM_PDMACH2_Captureddata15_8_Pos) |
| #define | PWM_PDMACH2_Captureddata23_16_Pos (16) |
| #define | PWM_PDMACH2_Captureddata23_16_Msk (0xfful << PWM_PDMACH2_Captureddata23_16_Pos) |
| #define | PWM_PDMACH2_Captureddata31_24_Pos (24) |
| #define | PWM_PDMACH2_Captureddata31_24_Msk (0xfful << PWM_PDMACH2_Captureddata31_24_Pos) |
| #define | RTC_INIR_ACTIVE_Pos (0) |
| #define | RTC_INIR_ACTIVE_Msk (0x1ul << RTC_INIR_ACTIVE_Pos) |
| #define | RTC_INIR_INIR_Pos (0) |
| #define | RTC_INIR_INIR_Msk (0xfffffffful << RTC_INIR_INIR_Pos) |
| #define | RTC_AER_AER_Pos (0) |
| #define | RTC_AER_AER_Msk (0xfffful << RTC_AER_AER_Pos) |
| #define | RTC_AER_ENF_Pos (16) |
| #define | RTC_AER_ENF_Msk (0x1ul << RTC_AER_ENF_Pos) |
| #define | RTC_FCR_FRACTION_Pos (0) |
| #define | RTC_FCR_FRACTION_Msk (0x3ful << RTC_FCR_FRACTION_Pos) |
| #define | RTC_FCR_INTEGER_Pos (8) |
| #define | RTC_FCR_INTEGER_Msk (0xful << RTC_FCR_INTEGER_Pos) |
| #define | RTC_TLR_1SEC_Pos (0) |
| #define | RTC_TLR_1SEC_Msk (0xful << RTC_TLR_1SEC_Pos) |
| #define | RTC_TLR_10SEC_Pos (4) |
| #define | RTC_TLR_10SEC_Msk (0x7ul << RTC_TLR_10SEC_Pos) |
| #define | RTC_TLR_1MIN_Pos (8) |
| #define | RTC_TLR_1MIN_Msk (0xful << RTC_TLR_1MIN_Pos) |
| #define | RTC_TLR_10MIN_Pos (12) |
| #define | RTC_TLR_10MIN_Msk (0x7ul << RTC_TLR_10MIN_Pos) |
| #define | RTC_TLR_1HR_Pos (16) |
| #define | RTC_TLR_1HR_Msk (0xful << RTC_TLR_1HR_Pos) |
| #define | RTC_TLR_10HR_Pos (20) |
| #define | RTC_TLR_10HR_Msk (0x3ul << RTC_TLR_10HR_Pos) |
| #define | RTC_CLR_1DAY_Pos (0) |
| #define | RTC_CLR_1DAY_Msk (0xful << RTC_CLR_1DAY_Pos) |
| #define | RTC_CLR_10DAY_Pos (4) |
| #define | RTC_CLR_10DAY_Msk (0x3ul << RTC_CLR_10DAY_Pos) |
| #define | RTC_CLR_1MON_Pos (8) |
| #define | RTC_CLR_1MON_Msk (0xful << RTC_CLR_1MON_Pos) |
| #define | RTC_CLR_10MON_Pos (12) |
| #define | RTC_CLR_10MON_Msk (0x1ul << RTC_CLR_10MON_Pos) |
| #define | RTC_CLR_1YEAR_Pos (16) |
| #define | RTC_CLR_1YEAR_Msk (0xful << RTC_CLR_1YEAR_Pos) |
| #define | RTC_CLR_10YEAR_Pos (20) |
| #define | RTC_CLR_10YEAR_Msk (0xful << RTC_CLR_10YEAR_Pos) |
| #define | RTC_TSSR_24H_12H_Pos (0) |
| #define | RTC_TSSR_24H_12H_Msk (0x1ul << RTC_TSSR_24H_12H_Pos) |
| #define | RTC_DWR_DWR_Pos (0) |
| #define | RTC_DWR_DWR_Msk (0x7ul << RTC_DWR_DWR_Pos) |
| #define | RTC_TAR_1SEC_Pos (0) |
| #define | RTC_TAR_1SEC_Msk (0xful << RTC_TAR_1SEC_Pos) |
| #define | RTC_TAR_10SEC_Pos (4) |
| #define | RTC_TAR_10SEC_Msk (0x7ul << RTC_TAR_10SEC_Pos) |
| #define | RTC_TAR_1MIN_Pos (8) |
| #define | RTC_TAR_1MIN_Msk (0xful << RTC_TAR_1MIN_Pos) |
| #define | RTC_TAR_10MIN_Pos (12) |
| #define | RTC_TAR_10MIN_Msk (0x7ul << RTC_TAR_10MIN_Pos) |
| #define | RTC_TAR_1HR_Pos (16) |
| #define | RTC_TAR_1HR_Msk (0xful << RTC_TAR_1HR_Pos) |
| #define | RTC_TAR_10HR_Pos (20) |
| #define | RTC_TAR_10HR_Msk (0x3ul << RTC_TAR_10HR_Pos) |
| #define | RTC_CAR_1DAY_Pos (0) |
| #define | RTC_CAR_1DAY_Msk (0xful << RTC_CAR_1DAY_Pos) |
| #define | RTC_CAR_10DAY_Pos (4) |
| #define | RTC_CAR_10DAY_Msk (0x3ul << RTC_CAR_10DAY_Pos) |
| #define | RTC_CAR_1MON_Pos (8) |
| #define | RTC_CAR_1MON_Msk (0xful << RTC_CAR_1MON_Pos) |
| #define | RTC_CAR_10MON_Pos (12) |
| #define | RTC_CAR_10MON_Msk (0x1ul << RTC_CAR_10MON_Pos) |
| #define | RTC_CAR_1YEAR_Pos (16) |
| #define | RTC_CAR_1YEAR_Msk (0xful << RTC_CAR_1YEAR_Pos) |
| #define | RTC_CAR_10YEAR_Pos (20) |
| #define | RTC_CAR_10YEAR_Msk (0xful << RTC_CAR_10YEAR_Pos) |
| #define | RTC_LIR_LIR_Pos (0) |
| #define | RTC_LIR_LIR_Msk (0x1ul << RTC_LIR_LIR_Pos) |
| #define | RTC_RIER_AIER_Pos (0) |
| #define | RTC_RIER_AIER_Msk (0x1ul << RTC_RIER_AIER_Pos) |
| #define | RTC_RIER_TIER_Pos (1) |
| #define | RTC_RIER_TIER_Msk (0x1ul << RTC_RIER_TIER_Pos) |
| #define | RTC_RIER_SNOOPIER_Pos (2) |
| #define | RTC_RIER_SNOOPIER_Msk (0x1ul << RTC_RIER_SNOOPIER_Pos) |
| #define | RTC_RIIR_AIF_Pos (0) |
| #define | RTC_RIIR_AIF_Msk (0x1ul << RTC_RIIR_AIF_Pos) |
| #define | RTC_RIIR_TIF_Pos (1) |
| #define | RTC_RIIR_TIF_Msk (0x1ul << RTC_RIIR_TIF_Pos) |
| #define | RTC_RIIR_SNOOPIF_Pos (2) |
| #define | RTC_RIIR_SNOOPIF_Msk (0x1ul << RTC_RIIR_SNOOPIF_Pos) |
| #define | RTC_TTR_TTR_Pos (0) |
| #define | RTC_TTR_TTR_Msk (0x7ul << RTC_TTR_TTR_Pos) |
| #define | RTC_TTR_TWKE_Pos (3) |
| #define | RTC_TTR_TWKE_Msk (0x1ul << RTC_TTR_TWKE_Pos) |
| #define | RTC_SPRCTL_SNOOPEN_Pos (0) |
| #define | RTC_SPRCTL_SNOOPEN_Msk (0x1ul << RTC_SPRCTL_SNOOPEN_Pos) |
| #define | RTC_SPRCTL_SNOOPEDGE_Pos (1) |
| #define | RTC_SPRCTL_SNOOPEDGE_Msk (0x1ul << RTC_SPRCTL_SNOOPEDGE_Pos) |
| #define | RTC_SPRCTL_SPRRDY_Pos (7) |
| #define | RTC_SPRCTL_SPRRDY_Msk (0x1ul << RTC_SPRCTL_SPRRDY_Pos) |
| #define | RTC_SPR0_SPARE_Pos (0) |
| #define | RTC_SPR0_SPARE_Msk (0xfffffffful << RTC_SPR0_SPARE_Pos) |
| #define | RTC_SPR1_SPARE_Pos (0) |
| #define | RTC_SPR1_SPARE_Msk (0xfffffffful << RTC_SPR1_SPARE_Pos) |
| #define | RTC_SPR2_SPARE_Pos (0) |
| #define | RTC_SPR2_SPARE_Msk (0xfffffffful << RTC_SPR2_SPARE_Pos) |
| #define | RTC_SPR3_SPARE_Pos (0) |
| #define | RTC_SPR3_SPARE_Msk (0xfffffffful << RTC_SPR3_SPARE_Pos) |
| #define | RTC_SPR4_SPARE_Pos (0) |
| #define | RTC_SPR4_SPARE_Msk (0xfffffffful << RTC_SPR4_SPARE_Pos) |
| #define | RTC_SPR5_SPARE_Pos (0) |
| #define | RTC_SPR5_SPARE_Msk (0xfffffffful << RTC_SPR5_SPARE_Pos) |
| #define | RTC_SPR6_SPARE_Pos (0) |
| #define | RTC_SPR6_SPARE_Msk (0xfffffffful << RTC_SPR6_SPARE_Pos) |
| #define | RTC_SPR7_SPARE_Pos (0) |
| #define | RTC_SPR7_SPARE_Msk (0xfffffffful << RTC_SPR7_SPARE_Pos) |
| #define | RTC_SPR8_SPARE_Pos (0) |
| #define | RTC_SPR8_SPARE_Msk (0xfffffffful << RTC_SPR8_SPARE_Pos) |
| #define | RTC_SPR9_SPARE_Pos (0) |
| #define | RTC_SPR9_SPARE_Msk (0xfffffffful << RTC_SPR9_SPARE_Pos) |
| #define | RTC_SPR10_SPARE_Pos (0) |
| #define | RTC_SPR10_SPARE_Msk (0xfffffffful << RTC_SPR10_SPARE_Pos) |
| #define | RTC_SPR11_SPARE_Pos (0) |
| #define | RTC_SPR11_SPARE_Msk (0xfffffffful << RTC_SPR11_SPARE_Pos) |
| #define | RTC_SPR12_SPARE_Pos (0) |
| #define | RTC_SPR12_SPARE_Msk (0xfffffffful << RTC_SPR12_SPARE_Pos) |
| #define | RTC_SPR13_SPARE_Pos (0) |
| #define | RTC_SPR13_SPARE_Msk (0xfffffffful << RTC_SPR13_SPARE_Pos) |
| #define | RTC_SPR14_SPARE_Pos (0) |
| #define | RTC_SPR14_SPARE_Msk (0xfffffffful << RTC_SPR14_SPARE_Pos) |
| #define | RTC_SPR15_SPARE_Pos (0) |
| #define | RTC_SPR15_SPARE_Msk (0xfffffffful << RTC_SPR15_SPARE_Pos) |
| #define | RTC_SPR16_SPARE_Pos (0) |
| #define | RTC_SPR16_SPARE_Msk (0xfffffffful << RTC_SPR16_SPARE_Pos) |
| #define | RTC_SPR17_SPARE_Pos (0) |
| #define | RTC_SPR17_SPARE_Msk (0xfffffffful << RTC_SPR17_SPARE_Pos) |
| #define | RTC_SPR18_SPARE_Pos (0) |
| #define | RTC_SPR18_SPARE_Msk (0xfffffffful << RTC_SPR18_SPARE_Pos) |
| #define | RTC_SPR19_SPARE_Pos (0) |
| #define | RTC_SPR19_SPARE_Msk (0xfffffffful << RTC_SPR19_SPARE_Pos) |
| #define | SC_DAT_DAT_Pos (0) |
| #define | SC_DAT_DAT_Msk (0xfful << SC_DAT_DAT_Pos) |
| #define | SC_CTL_SC_CEN_Pos (0) |
| #define | SC_CTL_SC_CEN_Msk (0x1ul << SC_CTL_SC_CEN_Pos) |
| #define | SC_CTL_DIS_RX_Pos (1) |
| #define | SC_CTL_DIS_RX_Msk (0x1ul << SC_CTL_DIS_RX_Pos) |
| #define | SC_CTL_DIS_TX_Pos (2) |
| #define | SC_CTL_DIS_TX_Msk (0x1ul << SC_CTL_DIS_TX_Pos) |
| #define | SC_CTL_AUTO_CON_EN_Pos (3) |
| #define | SC_CTL_AUTO_CON_EN_Msk (0x1ul << SC_CTL_AUTO_CON_EN_Pos) |
| #define | SC_CTL_CON_SEL_Pos (4) |
| #define | SC_CTL_CON_SEL_Msk (0x3ul << SC_CTL_CON_SEL_Pos) |
| #define | SC_CTL_RX_FTRI_LEV_Pos (6) |
| #define | SC_CTL_RX_FTRI_LEV_Msk (0x3ul << SC_CTL_RX_FTRI_LEV_Pos) |
| #define | SC_CTL_BGT_Pos (8) |
| #define | SC_CTL_BGT_Msk (0x1ful << SC_CTL_BGT_Pos) |
| #define | SC_CTL_TMR_SEL_Pos (13) |
| #define | SC_CTL_TMR_SEL_Msk (0x3ul << SC_CTL_TMR_SEL_Pos) |
| #define | SC_CTL_SLEN_Pos (15) |
| #define | SC_CTL_SLEN_Msk (0x1ul << SC_CTL_SLEN_Pos) |
| #define | SC_CTL_RX_ERETRY_Pos (16) |
| #define | SC_CTL_RX_ERETRY_Msk (0x7ul << SC_CTL_RX_ERETRY_Pos) |
| #define | SC_CTL_RX_ERETRY_EN_Pos (19) |
| #define | SC_CTL_RX_ERETRY_EN_Msk (0x1ul << SC_CTL_RX_ERETRY_EN_Pos) |
| #define | SC_CTL_TX_ERETRY_Pos (20) |
| #define | SC_CTL_TX_ERETRY_Msk (0x7ul << SC_CTL_TX_ERETRY_Pos) |
| #define | SC_CTL_TX_ERETRY_EN_Pos (23) |
| #define | SC_CTL_TX_ERETRY_EN_Msk (0x1ul << SC_CTL_TX_ERETRY_EN_Pos) |
| #define | SC_CTL_CD_DEB_SEL_Pos (24) |
| #define | SC_CTL_CD_DEB_SEL_Msk (0x3ul << SC_CTL_CD_DEB_SEL_Pos) |
| #define | SC_ALTCTL_TX_RST_Pos (0) |
| #define | SC_ALTCTL_TX_RST_Msk (0x1ul << SC_ALTCTL_TX_RST_Pos) |
| #define | SC_ALTCTL_RX_RST_Pos (1) |
| #define | SC_ALTCTL_RX_RST_Msk (0x1ul << SC_ALTCTL_RX_RST_Pos) |
| #define | SC_ALTCTL_DACT_EN_Pos (2) |
| #define | SC_ALTCTL_DACT_EN_Msk (0x1ul << SC_ALTCTL_DACT_EN_Pos) |
| #define | SC_ALTCTL_ACT_EN_Pos (3) |
| #define | SC_ALTCTL_ACT_EN_Msk (0x1ul << SC_ALTCTL_ACT_EN_Pos) |
| #define | SC_ALTCTL_WARST_EN_Pos (4) |
| #define | SC_ALTCTL_WARST_EN_Msk (0x1ul << SC_ALTCTL_WARST_EN_Pos) |
| #define | SC_ALTCTL_TMR0_SEN_Pos (5) |
| #define | SC_ALTCTL_TMR0_SEN_Msk (0x1ul << SC_ALTCTL_TMR0_SEN_Pos) |
| #define | SC_ALTCTL_TMR1_SEN_Pos (6) |
| #define | SC_ALTCTL_TMR1_SEN_Msk (0x1ul << SC_ALTCTL_TMR1_SEN_Pos) |
| #define | SC_ALTCTL_TMR2_SEN_Pos (7) |
| #define | SC_ALTCTL_TMR2_SEN_Msk (0x1ul << SC_ALTCTL_TMR2_SEN_Pos) |
| #define | SC_ALTCTL_INIT_SEL_Pos (8) |
| #define | SC_ALTCTL_INIT_SEL_Msk (0x3ul << SC_ALTCTL_INIT_SEL_Pos) |
| #define | SC_ALTCTL_RX_BGT_EN_Pos (12) |
| #define | SC_ALTCTL_RX_BGT_EN_Msk (0x1ul << SC_ALTCTL_RX_BGT_EN_Pos) |
| #define | SC_ALTCTL_TMR0_ATV_Pos (13) |
| #define | SC_ALTCTL_TMR0_ATV_Msk (0x1ul << SC_ALTCTL_TMR0_ATV_Pos) |
| #define | SC_ALTCTL_TMR1_ATV_Pos (14) |
| #define | SC_ALTCTL_TMR1_ATV_Msk (0x1ul << SC_ALTCTL_TMR1_ATV_Pos) |
| #define | SC_ALTCTL_TMR2_ATV_Pos (15) |
| #define | SC_ALTCTL_TMR2_ATV_Msk (0x1ul << SC_ALTCTL_TMR2_ATV_Pos) |
| #define | SC_EGTR_EGT_Pos (0) |
| #define | SC_EGTR_EGT_Msk (0xfful << SC_EGTR_EGT_Pos) |
| #define | SC_RFTMR_RFTM_Pos (0) |
| #define | SC_RFTMR_RFTM_Msk (0x1fful << SC_RFTMR_RFTM_Pos) |
| #define | SC_ETUCR_ETU_RDIV_Pos (0) |
| #define | SC_ETUCR_ETU_RDIV_Msk (0xffful << SC_ETUCR_ETU_RDIV_Pos) |
| #define | SC_ETUCR_COMPEN_EN_Pos (15) |
| #define | SC_ETUCR_COMPEN_EN_Msk (0x1ul << SC_ETUCR_COMPEN_EN_Pos) |
| #define | SC_IER_RDA_IE_Pos (0) |
| #define | SC_IER_RDA_IE_Msk (0x1ul << SC_IER_RDA_IE_Pos) |
| #define | SC_IER_TBE_IE_Pos (1) |
| #define | SC_IER_TBE_IE_Msk (0x1ul << SC_IER_TBE_IE_Pos) |
| #define | SC_IER_TERR_IE_Pos (2) |
| #define | SC_IER_TERR_IE_Msk (0x1ul << SC_IER_TERR_IE_Pos) |
| #define | SC_IER_TMR0_IE_Pos (3) |
| #define | SC_IER_TMR0_IE_Msk (0x1ul << SC_IER_TMR0_IE_Pos) |
| #define | SC_IER_TMR1_IE_Pos (4) |
| #define | SC_IER_TMR1_IE_Msk (0x1ul << SC_IER_TMR1_IE_Pos) |
| #define | SC_IER_TMR2_IE_Pos (5) |
| #define | SC_IER_TMR2_IE_Msk (0x1ul << SC_IER_TMR2_IE_Pos) |
| #define | SC_IER_BGT_IE_Pos (6) |
| #define | SC_IER_BGT_IE_Msk (0x1ul << SC_IER_BGT_IE_Pos) |
| #define | SC_IER_CD_IE_Pos (7) |
| #define | SC_IER_CD_IE_Msk (0x1ul << SC_IER_CD_IE_Pos) |
| #define | SC_IER_INIT_IE_Pos (8) |
| #define | SC_IER_INIT_IE_Msk (0x1ul << SC_IER_INIT_IE_Pos) |
| #define | SC_IER_RTMR_IE_Pos (9) |
| #define | SC_IER_RTMR_IE_Msk (0x1ul << SC_IER_RTMR_IE_Pos) |
| #define | SC_IER_ACON_ERR_IE_Pos (10) |
| #define | SC_IER_ACON_ERR_IE_Msk (0x1ul << SC_IER_ACON_ERR_IE_Pos) |
| #define | SC_IER_COMPEN_EN_Pos (15) |
| #define | SC_IER_COMPEN_EN_Msk (0x1ul << SC_IER_COMPEN_EN_Pos) |
| #define | SC_ISR_RDA_IS_Pos (0) |
| #define | SC_ISR_RDA_IS_Msk (0x1ul << SC_ISR_RDA_IS_Pos) |
| #define | SC_ISR_TBE_IS_Pos (1) |
| #define | SC_ISR_TBE_IS_Msk (0x1ul << SC_ISR_TBE_IS_Pos) |
| #define | SC_ISR_TERR_IS_Pos (2) |
| #define | SC_ISR_TERR_IS_Msk (0x1ul << SC_ISR_TERR_IS_Pos) |
| #define | SC_ISR_TMR0_IS_Pos (3) |
| #define | SC_ISR_TMR0_IS_Msk (0x1ul << SC_ISR_TMR0_IS_Pos) |
| #define | SC_ISR_TMR1_IS_Pos (4) |
| #define | SC_ISR_TMR1_IS_Msk (0x1ul << SC_ISR_TMR1_IS_Pos) |
| #define | SC_ISR_TMR2_IS_Pos (5) |
| #define | SC_ISR_TMR2_IS_Msk (0x1ul << SC_ISR_TMR2_IS_Pos) |
| #define | SC_ISR_BGT_IS_Pos (6) |
| #define | SC_ISR_BGT_IS_Msk (0x1ul << SC_ISR_BGT_IS_Pos) |
| #define | SC_ISR_CD_IS_Pos (7) |
| #define | SC_ISR_CD_IS_Msk (0x1ul << SC_ISR_CD_IS_Pos) |
| #define | SC_ISR_INIT_IS_Pos (8) |
| #define | SC_ISR_INIT_IS_Msk (0x1ul << SC_ISR_INIT_IS_Pos) |
| #define | SC_ISR_RTMR_IS_Pos (9) |
| #define | SC_ISR_RTMR_IS_Msk (0x1ul << SC_ISR_RTMR_IS_Pos) |
| #define | SC_ISR_ACON_ERR_IS_Pos (10) |
| #define | SC_ISR_ACON_ERR_IS_Msk (0x1ul << SC_ISR_ACON_ERR_IS_Pos) |
| #define | SC_TRSR_RX_OVER_F_Pos (0) |
| #define | SC_TRSR_RX_OVER_F_Msk (0x1ul << SC_TRSR_RX_OVER_F_Pos) |
| #define | SC_TRSR_RX_EMPTY_F_Pos (1) |
| #define | SC_TRSR_RX_EMPTY_F_Msk (0x1ul << SC_TRSR_RX_EMPTY_F_Pos) |
| #define | SC_TRSR_RX_FULL_F_Pos (2) |
| #define | SC_TRSR_RX_FULL_F_Msk (0x1ul << SC_TRSR_RX_FULL_F_Pos) |
| #define | SC_TRSR_RX_EPA_F_Pos (4) |
| #define | SC_TRSR_RX_EPA_F_Msk (0x1ul << SC_TRSR_RX_EPA_F_Pos) |
| #define | SC_TRSR_RX_EFR_F_Pos (5) |
| #define | SC_TRSR_RX_EFR_F_Msk (0x1ul << SC_TRSR_RX_EFR_F_Pos) |
| #define | SC_TRSR_RX_EBR_F_Pos (6) |
| #define | SC_TRSR_RX_EBR_F_Msk (0x1ul << SC_TRSR_RX_EBR_F_Pos) |
| #define | SC_TRSR_TX_OVER_F_Pos (8) |
| #define | SC_TRSR_TX_OVER_F_Msk (0x1ul << SC_TRSR_TX_OVER_F_Pos) |
| #define | SC_TRSR_TX_EMPTY_F_Pos (9) |
| #define | SC_TRSR_TX_EMPTY_F_Msk (0x1ul << SC_TRSR_TX_EMPTY_F_Pos) |
| #define | SC_TRSR_TX_FULL_F_Pos (10) |
| #define | SC_TRSR_TX_FULL_F_Msk (0x1ul << SC_TRSR_TX_FULL_F_Pos) |
| #define | SC_TRSR_RX_POINT_F_Pos (16) |
| #define | SC_TRSR_RX_POINT_F_Msk (0x7ul << SC_TRSR_RX_POINT_F_Pos) |
| #define | SC_TRSR_RX_REERR_Pos (21) |
| #define | SC_TRSR_RX_REERR_Msk (0x1ul << SC_TRSR_RX_REERR_Pos) |
| #define | SC_TRSR_RX_OVER_ERETRY_Pos (22) |
| #define | SC_TRSR_RX_OVER_ERETRY_Msk (0x1ul << SC_TRSR_RX_OVER_ERETRY_Pos) |
| #define | SC_TRSR_RX_ATV_Pos (23) |
| #define | SC_TRSR_RX_ATV_Msk (0x1ul << SC_TRSR_RX_ATV_Pos) |
| #define | SC_TRSR_TX_POINT_F_Pos (24) |
| #define | SC_TRSR_TX_POINT_F_Msk (0x7ul << SC_TRSR_TX_POINT_F_Pos) |
| #define | SC_TRSR_TX_REERR_Pos (29) |
| #define | SC_TRSR_TX_REERR_Msk (0x1ul << SC_TRSR_TX_REERR_Pos) |
| #define | SC_TRSR_TX_OVER_ERETRY_Pos (30) |
| #define | SC_TRSR_TX_OVER_ERETRY_Msk (0x1ul << SC_TRSR_TX_OVER_ERETRY_Pos) |
| #define | SC_TRSR_TX_ATV_Pos (31) |
| #define | SC_TRSR_TX_ATV_Msk (0x1ul << SC_TRSR_TX_ATV_Pos) |
| #define | SC_PINCSR_POW_EN_Pos (0) |
| #define | SC_PINCSR_POW_EN_Msk (0x1ul << SC_PINCSR_POW_EN_Pos) |
| #define | SC_PINCSR_SC_RST_Pos (1) |
| #define | SC_PINCSR_SC_RST_Msk (0x1ul << SC_PINCSR_SC_RST_Pos) |
| #define | SC_PINCSR_CD_REM_F_Pos (2) |
| #define | SC_PINCSR_CD_REM_F_Msk (0x1ul << SC_PINCSR_CD_REM_F_Pos) |
| #define | SC_PINCSR_CD_INS_F_Pos (3) |
| #define | SC_PINCSR_CD_INS_F_Msk (0x1ul << SC_PINCSR_CD_INS_F_Pos) |
| #define | SC_PINCSR_CD_PIN_ST_Pos (4) |
| #define | SC_PINCSR_CD_PIN_ST_Msk (0x1ul << SC_PINCSR_CD_PIN_ST_Pos) |
| #define | SC_PINCSR_CLK_KEEP_Pos (6) |
| #define | SC_PINCSR_CLK_KEEP_Msk (0x1ul << SC_PINCSR_CLK_KEEP_Pos) |
| #define | SC_PINCSR_ADAC_CD_EN_Pos (7) |
| #define | SC_PINCSR_ADAC_CD_EN_Msk (0x1ul << SC_PINCSR_ADAC_CD_EN_Pos) |
| #define | SC_PINCSR_SC_OEN_ST_Pos (8) |
| #define | SC_PINCSR_SC_OEN_ST_Msk (0x1ul << SC_PINCSR_SC_OEN_ST_Pos) |
| #define | SC_PINCSR_SC_DATA_O_Pos (9) |
| #define | SC_PINCSR_SC_DATA_O_Msk (0x1ul << SC_PINCSR_SC_DATA_O_Pos) |
| #define | SC_PINCSR_CD_LEV_Pos (10) |
| #define | SC_PINCSR_CD_LEV_Msk (0x1ul << SC_PINCSR_CD_LEV_Pos) |
| #define | SC_PINCSR_SC_DATA_I_ST_Pos (16) |
| #define | SC_PINCSR_SC_DATA_I_ST_Msk (0x1ul << SC_PINCSR_SC_DATA_I_ST_Pos) |
| #define | SC_TMR0_CNT_Pos (0) |
| #define | SC_TMR0_CNT_Msk (0xfffffful << SC_TMR0_CNT_Pos) |
| #define | SC_TMR0_MODE_Pos (24) |
| #define | SC_TMR0_MODE_Msk (0xful << SC_TMR0_MODE_Pos) |
| #define | SC_TMR1_CNT_Pos (0) |
| #define | SC_TMR1_CNT_Msk (0xfful << SC_TMR1_CNT_Pos) |
| #define | SC_TMR1_MODE_Pos (24) |
| #define | SC_TMR1_MODE_Msk (0xful << SC_TMR1_MODE_Pos) |
| #define | SC_TMR2_CNT_Pos (0) |
| #define | SC_TMR2_CNT_Msk (0xfful << SC_TMR2_CNT_Pos) |
| #define | SC_TMR2_MODE_Pos (24) |
| #define | SC_TMR2_MODE_Msk (0xful << SC_TMR2_MODE_Pos) |
| #define | SC_TDRA_TDR0_Pos (0) |
| #define | SC_TDRA_TDR0_Msk (0xfffffful << SC_TDRA_TDR0_Pos) |
| #define | SC_TDRB_TDR1_Pos (0) |
| #define | SC_TDRB_TDR1_Msk (0xfful << SC_TDRB_TDR1_Pos) |
| #define | SC_TDRB_TDR2_Pos (8) |
| #define | SC_TDRB_TDR2_Msk (0xfful << SC_TDRB_TDR2_Pos) |
| #define | SPI_CTL_GO_BUSY_Pos (0) |
| #define | SPI_CTL_GO_BUSY_Msk (0x1ul << SPI_CTL_GO_BUSY_Pos) |
| #define | SPI_CTL_RX_NEG_Pos (1) |
| #define | SPI_CTL_RX_NEG_Msk (0x1ul << SPI_CTL_RX_NEG_Pos) |
| #define | SPI_CTL_TX_NEG_Pos (2) |
| #define | SPI_CTL_TX_NEG_Msk (0x1ul << SPI_CTL_TX_NEG_Pos) |
| #define | SPI_CTL_TX_BIT_LEN_Pos (3) |
| #define | SPI_CTL_TX_BIT_LEN_Msk (0x1ful << SPI_CTL_TX_BIT_LEN_Pos) |
| #define | SPI_CTL_TX_NUM_Pos (8) |
| #define | SPI_CTL_TX_NUM_Msk (0x3ul << SPI_CTL_TX_NUM_Pos) |
| #define | SPI_CTL_LSB_Pos (10) |
| #define | SPI_CTL_LSB_Msk (0x1ul << SPI_CTL_LSB_Pos) |
| #define | SPI_CTL_CLKP_Pos (11) |
| #define | SPI_CTL_CLKP_Msk (0x1ul << SPI_CTL_CLKP_Pos) |
| #define | SPI_CTL_SP_CYCLE_Pos (12) |
| #define | SPI_CTL_SP_CYCLE_Msk (0xful << SPI_CTL_SP_CYCLE_Pos) |
| #define | SPI_CTL_INTEN_Pos (17) |
| #define | SPI_CTL_INTEN_Msk (0x1ul << SPI_CTL_INTEN_Pos) |
| #define | SPI_CTL_SLAVE_Pos (18) |
| #define | SPI_CTL_SLAVE_Msk (0x1ul << SPI_CTL_SLAVE_Pos) |
| #define | SPI_CTL_REORDER_Pos (19) |
| #define | SPI_CTL_REORDER_Msk (0x3ul << SPI_CTL_REORDER_Pos) |
| #define | SPI_CTL_FIFOM_Pos (21) |
| #define | SPI_CTL_FIFOM_Msk (0x1ul << SPI_CTL_FIFOM_Pos) |
| #define | SPI_CTL_TWOB_Pos (22) |
| #define | SPI_CTL_TWOB_Msk (0x1ul << SPI_CTL_TWOB_Pos) |
| #define | SPI_CTL_VARCLK_EN_Pos (23) |
| #define | SPI_CTL_VARCLK_EN_Msk (0x1ul << SPI_CTL_VARCLK_EN_Pos) |
| #define | SPI_CTL_WKEUP_EN_Pos (31) |
| #define | SPI_CTL_WKEUP_EN_Msk (0x1ul << SPI_CTL_WKEUP_EN_Pos) |
| #define | SPI_STATUS_RX_EMPTY_Pos (0) |
| #define | SPI_STATUS_RX_EMPTY_Msk (0x1ul << SPI_STATUS_RX_EMPTY_Pos) |
| #define | SPI_STATUS_RX_FULL_Pos (1) |
| #define | SPI_STATUS_RX_FULL_Msk (0x1ul << SPI_STATUS_RX_FULL_Pos) |
| #define | SPI_STATUS_TX_EMPTY_Pos (2) |
| #define | SPI_STATUS_TX_EMPTY_Msk (0x1ul << SPI_STATUS_TX_EMPTY_Pos) |
| #define | SPI_STATUS_TX_FULL_Pos (3) |
| #define | SPI_STATUS_TX_FULL_Msk (0x1ul << SPI_STATUS_TX_FULL_Pos) |
| #define | SPI_STATUS_LTRIG_FLAG_Pos (4) |
| #define | SPI_STATUS_LTRIG_FLAG_Msk (0x1ul << SPI_STATUS_LTRIG_FLAG_Pos) |
| #define | SPI_STATUS_SLV_START_INTSTS_Pos (6) |
| #define | SPI_STATUS_SLV_START_INTSTS_Msk (0x1ul << SPI_STATUS_SLV_START_INTSTS_Pos) |
| #define | SPI_STATUS_INTSTS_Pos (7) |
| #define | SPI_STATUS_INTSTS_Msk (0x1ul << SPI_STATUS_INTSTS_Pos) |
| #define | SPI_CLKDIV_DIVIDER1_Pos (0) |
| #define | SPI_CLKDIV_DIVIDER1_Msk (0xfffful << SPI_CLKDIV_DIVIDER1_Pos) |
| #define | SPI_CLKDIV_DIVIDER2_Pos (16) |
| #define | SPI_CLKDIV_DIVIDER2_Msk (0xfffful << SPI_CLKDIV_DIVIDER2_Pos) |
| #define | SPI_SSR_SSR_Pos (0) |
| #define | SPI_SSR_SSR_Msk (0x3ul << SPI_SSR_SSR_Pos) |
| #define | SPI_SSR_SS_LVL_Pos (2) |
| #define | SPI_SSR_SS_LVL_Msk (0x1ul << SPI_SSR_SS_LVL_Pos) |
| #define | SPI_SSR_AUTOSS_Pos (3) |
| #define | SPI_SSR_AUTOSS_Msk (0x1ul << SPI_SSR_AUTOSS_Pos) |
| #define | SPI_SSR_SS_LTRIG_Pos (4) |
| #define | SPI_SSR_SS_LTRIG_Msk (0x1ul << SPI_SSR_SS_LTRIG_Pos) |
| #define | SPI_SSR_NOSLVSEL_Pos (5) |
| #define | SPI_SSR_NOSLVSEL_Msk (0x1ul << SPI_SSR_NOSLVSEL_Pos) |
| #define | SPI_SSR_SLV_ABORT_Pos (8) |
| #define | SPI_SSR_SLV_ABORT_Msk (0x1ul << SPI_SSR_SLV_ABORT_Pos) |
| #define | SPI_SSR_SSTA_INTEN_Pos (9) |
| #define | SPI_SSR_SSTA_INTEN_Msk (0x1ul << SPI_SSR_SSTA_INTEN_Pos) |
| #define | SPI_RX0_RDATA_Pos (0) |
| #define | SPI_RX0_RDATA_Msk (0xfffffffful << SPI_RX0_RDATA_Pos) |
| #define | SPI_RX1_RDATA_Pos (0) |
| #define | SPI_RX1_RDATA_Msk (0xfffffffful << SPI_RX1_RDATA_Pos) |
| #define | SPI_TX0_TDATA_Pos (0) |
| #define | SPI_TX0_TDATA_Msk (0xfffffffful << SPI_TX0_TDATA_Pos) |
| #define | SPI_TX1_TDATA_Pos (0) |
| #define | SPI_TX1_TDATA_Msk (0xfffffffful << SPI_TX1_TDATA_Pos) |
| #define | SPI_VARCLK_VARCLK_Pos (0) |
| #define | SPI_VARCLK_VARCLK_Msk (0xfffffffful << SPI_VARCLK_VARCLK_Pos) |
| #define | SPI_PDMA_TX_DMA_EN_Pos (0) |
| #define | SPI_PDMA_TX_DMA_EN_Msk (0x1ul << SPI_PDMA_TX_DMA_EN_Pos) |
| #define | SPI_PDMA_RX_DMA_EN_Pos (1) |
| #define | SPI_PDMA_RX_DMA_EN_Msk (0x1ul << SPI_PDMA_RX_DMA_EN_Pos) |
| #define | SPI_PDMA_PDMA_RST_Pos (2) |
| #define | SPI_PDMA_PDMA_RST_Msk (0x1ul << SPI_PDMA_PDMA_RST_Pos) |
| #define | SPI_FFCLR_RX_CLR_Pos (0) |
| #define | SPI_FFCLR_RX_CLR_Msk (0x1ul << SPI_FFCLR_RX_CLR_Pos) |
| #define | SPI_FFCLR_TX_CLR_Pos (1) |
| #define | SPI_FFCLR_TX_CLR_Msk (0x1ul << SPI_FFCLR_TX_CLR_Pos) |
| #define | TIMER_CTL_TMR_EN_Pos (0) |
| #define | TIMER_CTL_TMR_EN_Msk (0x1ul << TIMER_CTL_TMR_EN_Pos) |
| #define | TIMER_CTL_SW_RST_Pos (1) |
| #define | TIMER_CTL_SW_RST_Msk (0x1ul << TIMER_CTL_SW_RST_Pos) |
| #define | TIMER_CTL_WAKE_EN_Pos (2) |
| #define | TIMER_CTL_WAKE_EN_Msk (0x1ul << TIMER_CTL_WAKE_EN_Pos) |
| #define | TIMER_CTL_DBGACK_EN_Pos (3) |
| #define | TIMER_CTL_DBGACK_EN_Msk (0x1ul << TIMER_CTL_DBGACK_EN_Pos) |
| #define | TIMER_CTL_MODE_SEL_Pos (4) |
| #define | TIMER_CTL_MODE_SEL_Msk (0x3ul << TIMER_CTL_MODE_SEL_Pos) |
| #define | TIMER_CTL_TMR_ACT_Pos (7) |
| #define | TIMER_CTL_TMR_ACT_Msk (0x1ul << TIMER_CTL_TMR_ACT_Pos) |
| #define | TIMER_CTL_ADC_TEEN_Pos (8) |
| #define | TIMER_CTL_ADC_TEEN_Msk (0x1ul << TIMER_CTL_ADC_TEEN_Pos) |
| #define | TIMER_CTL_PDMA_TEEN_Pos (10) |
| #define | TIMER_CTL_PDMA_TEEN_Msk (0x1ul << TIMER_CTL_PDMA_TEEN_Pos) |
| #define | TIMER_CTL_CAP_TRG_EN_Pos (11) |
| #define | TIMER_CTL_CAP_TRG_EN_Msk (0x1ul << TIMER_CTL_CAP_TRG_EN_Pos) |
| #define | TIMER_CTL_EVENT_EN_Pos (12) |
| #define | TIMER_CTL_EVENT_EN_Msk (0x1ul << TIMER_CTL_EVENT_EN_Pos) |
| #define | TIMER_CTL_EVENT_EDGE_Pos (13) |
| #define | TIMER_CTL_EVENT_EDGE_Msk (0x1ul << TIMER_CTL_EVENT_EDGE_Pos) |
| #define | TIMER_CTL_EVNT_DEB_EN_Pos (14) |
| #define | TIMER_CTL_EVNT_DEB_EN_Msk (0x1ul << TIMER_CTL_EVNT_DEB_EN_Pos) |
| #define | TIMER_CTL_TCAP_EN_Pos (16) |
| #define | TIMER_CTL_TCAP_EN_Msk (0x1ul << TIMER_CTL_TCAP_EN_Pos) |
| #define | TIMER_CTL_TCAP_MODE_Pos (17) |
| #define | TIMER_CTL_TCAP_MODE_Msk (0x1ul << TIMER_CTL_TCAP_MODE_Pos) |
| #define | TIMER_CTL_TCAP_EDGE_Pos (18) |
| #define | TIMER_CTL_TCAP_EDGE_Msk (0x3ul << TIMER_CTL_TCAP_EDGE_Pos) |
| #define | TIMER_CTL_TCAP_CNT_MODE_Pos (20) |
| #define | TIMER_CTL_TCAP_CNT_MODE_Msk (0x1ul << TIMER_CTL_TCAP_CNT_MODE_Pos) |
| #define | TIMER_CTL_TCAP_DEB_EN_Pos (22) |
| #define | TIMER_CTL_TCAP_DEB_EN_Msk (0x1ul << TIMER_CTL_TCAP_DEB_EN_Pos) |
| #define | TIMER_CTL_INTR_TRG_EN_Pos (24) |
| #define | TIMER_CTL_INTR_TRG_EN_Msk (0x1ul << TIMER_CTL_INTR_TRG_EN_Pos) |
| #define | TIMER_PRECNT_PRESCALE_CNT_Pos (0) |
| #define | TIMER_PRECNT_PRESCALE_CNT_Msk (0xfful << TIMER_PRECNT_PRESCALE_CNT_Pos) |
| #define | TIMER_CMPR_TMR_CMP_Pos (0) |
| #define | TIMER_CMPR_TMR_CMP_Msk (0xfffffful << TIMER_CMPR_TMR_CMP_Pos) |
| #define | TIMER_IER_TMR_IE_Pos (0) |
| #define | TIMER_IER_TMR_IE_Msk (0x1ul << TIMER_IER_TMR_IE_Pos) |
| #define | TIMER_IER_TCAP_IE_Pos (1) |
| #define | TIMER_IER_TCAP_IE_Msk (0x1ul << TIMER_IER_TCAP_IE_Pos) |
| #define | TIMER_ISR_TMR_IS_Pos (0) |
| #define | TIMER_ISR_TMR_IS_Msk (0x1ul << TIMER_ISR_TMR_IS_Pos) |
| #define | TIMER_ISR_TCAP_IS_Pos (1) |
| #define | TIMER_ISR_TCAP_IS_Msk (0x1ul << TIMER_ISR_TCAP_IS_Pos) |
| #define | TIMER_ISR_TMR_WAKE_STS_Pos (4) |
| #define | TIMER_ISR_TMR_WAKE_STS_Msk (0x1ul << TIMER_ISR_TMR_WAKE_STS_Pos) |
| #define | TIMER_ISR_NCAP_DET_STS_Pos (5) |
| #define | TIMER_ISR_NCAP_DET_STS_Msk (0x1ul << TIMER_ISR_NCAP_DET_STS_Pos) |
| #define | TIMER_DR_TDR_Pos (0) |
| #define | TIMER_DR_TDR_Msk (0xfffffful << TIMER_DR_TDR_Pos) |
| #define | TIMER_TCAP_CAP_Pos (0) |
| #define | TIMER_TCAP_CAP_Msk (0xfffffful << TIMER_TCAP_CAP_Pos) |
| #define | UART_DAT_DAT_Pos (0) |
| #define | UART_DAT_DAT_Msk (0xfful << UART_DAT_DAT_Pos) |
| #define | UART_CTL_RX_RST_Pos (0) |
| #define | UART_CTL_RX_RST_Msk (0x1ul << UART_CTL_RX_RST_Pos) |
| #define | UART_CTL_TX_RST_Pos (1) |
| #define | UART_CTL_TX_RST_Msk (0x1ul << UART_CTL_TX_RST_Pos) |
| #define | UART_CTL_RX_DIS_Pos (2) |
| #define | UART_CTL_RX_DIS_Msk (0x1ul << UART_CTL_RX_DIS_Pos) |
| #define | UART_CTL_TX_DIS_Pos (3) |
| #define | UART_CTL_TX_DIS_Msk (0x1ul << UART_CTL_TX_DIS_Pos) |
| #define | UART_CTL_AUTO_RTS_EN_Pos (4) |
| #define | UART_CTL_AUTO_RTS_EN_Msk (0x1ul << UART_CTL_AUTO_RTS_EN_Pos) |
| #define | UART_CTL_AUTO_CTS_EN_Pos (5) |
| #define | UART_CTL_AUTO_CTS_EN_Msk (0x1ul << UART_CTL_AUTO_CTS_EN_Pos) |
| #define | UART_CTL_DMA_RX_EN_Pos (6) |
| #define | UART_CTL_DMA_RX_EN_Msk (0x1ul << UART_CTL_DMA_RX_EN_Pos) |
| #define | UART_CTL_DMA_TX_EN_Pos (7) |
| #define | UART_CTL_DMA_TX_EN_Msk (0x1ul << UART_CTL_DMA_TX_EN_Pos) |
| #define | UART_CTL_WAKE_CTS_EN_Pos (8) |
| #define | UART_CTL_WAKE_CTS_EN_Msk (0x1ul << UART_CTL_WAKE_CTS_EN_Pos) |
| #define | UART_CTL_WAKE_DATA_EN_Pos (9) |
| #define | UART_CTL_WAKE_DATA_EN_Msk (0x1ul << UART_CTL_WAKE_DATA_EN_Pos) |
| #define | UART_CTL_ABAUD_EN_Pos (12) |
| #define | UART_CTL_ABAUD_EN_Msk (0x1ul << UART_CTL_ABAUD_EN_Pos) |
| #define | UART_TLCTL_DATA_LEN_Pos (0) |
| #define | UART_TLCTL_DATA_LEN_Msk (0x3ul << UART_TLCTL_DATA_LEN_Pos) |
| #define | UART_TLCTL_NSB_Pos (2) |
| #define | UART_TLCTL_NSB_Msk (0x1ul << UART_TLCTL_NSB_Pos) |
| #define | UART_TLCTL_PBE_Pos (3) |
| #define | UART_TLCTL_PBE_Msk (0x1ul << UART_TLCTL_PBE_Pos) |
| #define | UART_TLCTL_EPE_Pos (4) |
| #define | UART_TLCTL_EPE_Msk (0x1ul << UART_TLCTL_EPE_Pos) |
| #define | UART_TLCTL_SPE_Pos (5) |
| #define | UART_TLCTL_SPE_Msk (0x1ul << UART_TLCTL_SPE_Pos) |
| #define | UART_TLCTL_BCB_Pos (6) |
| #define | UART_TLCTL_BCB_Msk (0x1ul << UART_TLCTL_BCB_Pos) |
| #define | UART_TLCTL_RFITL_Pos (8) |
| #define | UART_TLCTL_RFITL_Msk (0x3ul << UART_TLCTL_RFITL_Pos) |
| #define | UART_TLCTL_RTS_TRI_LEV_Pos (12) |
| #define | UART_TLCTL_RTS_TRI_LEV_Msk (0x3ul << UART_TLCTL_RTS_TRI_LEV_Pos) |
| #define | UART_IER_RDA_IE_Pos (0) |
| #define | UART_IER_RDA_IE_Msk (0x1ul << UART_IER_RDA_IE_Pos) |
| #define | UART_IER_THRE_IE_Pos (1) |
| #define | UART_IER_THRE_IE_Msk (0x1ul << UART_IER_THRE_IE_Pos) |
| #define | UART_IER_RLS_IE_Pos (2) |
| #define | UART_IER_RLS_IE_Msk (0x1ul << UART_IER_RLS_IE_Pos) |
| #define | UART_IER_MODEM_IE_Pos (3) |
| #define | UART_IER_MODEM_IE_Msk (0x1ul << UART_IER_MODEM_IE_Pos) |
| #define | UART_IER_RTO_IE_Pos (4) |
| #define | UART_IER_RTO_IE_Msk (0x1ul << UART_IER_RTO_IE_Pos) |
| #define | UART_IER_BUF_ERR_IE_Pos (5) |
| #define | UART_IER_BUF_ERR_IE_Msk (0x1ul << UART_IER_BUF_ERR_IE_Pos) |
| #define | UART_IER_WAKE_IE_Pos (6) |
| #define | UART_IER_WAKE_IE_Msk (0x1ul << UART_IER_WAKE_IE_Pos) |
| #define | UART_IER_ABAUD_IE_Pos (7) |
| #define | UART_IER_ABAUD_IE_Msk (0x1ul << UART_IER_ABAUD_IE_Pos) |
| #define | UART_IER_LIN_IE_Pos (8) |
| #define | UART_IER_LIN_IE_Msk (0x1ul << UART_IER_LIN_IE_Pos) |
| #define | UART_ISR_RDA_IS_Pos (0) |
| #define | UART_ISR_RDA_IS_Msk (0x1ul << UART_ISR_RDA_IS_Pos) |
| #define | UART_ISR_THRE_IS_Pos (1) |
| #define | UART_ISR_THRE_IS_Msk (0x1ul << UART_ISR_THRE_IS_Pos) |
| #define | UART_ISR_RLS_IS_Pos (2) |
| #define | UART_ISR_RLS_IS_Msk (0x1ul << UART_ISR_RLS_IS_Pos) |
| #define | UART_ISR_MODEM_IS_Pos (3) |
| #define | UART_ISR_MODEM_IS_Msk (0x1ul << UART_ISR_MODEM_IS_Pos) |
| #define | UART_ISR_RTO_IS_Pos (4) |
| #define | UART_ISR_RTO_IS_Msk (0x1ul << UART_ISR_RTO_IS_Pos) |
| #define | UART_ISR_BUF_ERR_IS_Pos (5) |
| #define | UART_ISR_BUF_ERR_IS_Msk (0x1ul << UART_ISR_BUF_ERR_IS_Pos) |
| #define | UART_ISR_WAKE_IS_Pos (6) |
| #define | UART_ISR_WAKE_IS_Msk (0x1ul << UART_ISR_WAKE_IS_Pos) |
| #define | UART_ISR_ABAUD_IS_Pos (7) |
| #define | UART_ISR_ABAUD_IS_Msk (0x1ul << UART_ISR_ABAUD_IS_Pos) |
| #define | UART_ISR_LIN_IS_Pos (8) |
| #define | UART_ISR_LIN_IS_Msk (0x1ul << UART_ISR_LIN_IS_Pos) |
| #define | UART_TRSR_RS485_ADDET_F_Pos (0) |
| #define | UART_TRSR_RS485_ADDET_F_Msk (0x1ul << UART_TRSR_RS485_ADDET_F_Pos) |
| #define | UART_TRSR_ABAUD_F_Pos (1) |
| #define | UART_TRSR_ABAUD_F_Msk (0x1ul << UART_TRSR_ABAUD_F_Pos) |
| #define | UART_TRSR_ABAUD_TOUT_F_Pos (2) |
| #define | UART_TRSR_ABAUD_TOUT_F_Msk (0x1ul << UART_TRSR_ABAUD_TOUT_F_Pos) |
| #define | UART_TRSR_LIN_TX_F_Pos (3) |
| #define | UART_TRSR_LIN_TX_F_Msk (0x1ul << UART_TRSR_LIN_TX_F_Pos) |
| #define | UART_TRSR_LIN_RX_F_Pos (4) |
| #define | UART_TRSR_LIN_RX_F_Msk (0x1ul << UART_TRSR_LIN_RX_F_Pos) |
| #define | UART_TRSR_BIT_ERR_F_Pos (5) |
| #define | UART_TRSR_BIT_ERR_F_Msk (0x1ul << UART_TRSR_BIT_ERR_F_Pos) |
| #define | UART_TRSR_LIN_RX_SYNC_ERR_F_Pos (8) |
| #define | UART_TRSR_LIN_RX_SYNC_ERR_F_Msk (0x1ul << UART_TRSR_LIN_RX_SYNC_ERR_F_Pos) |
| #define | UART_FSR_RX_OVER_F_Pos (0) |
| #define | UART_FSR_RX_OVER_F_Msk (0x1ul << UART_FSR_RX_OVER_F_Pos) |
| #define | UART_FSR_RX_EMPTY_F_Pos (1) |
| #define | UART_FSR_RX_EMPTY_F_Msk (0x1ul << UART_FSR_RX_EMPTY_F_Pos) |
| #define | UART_FSR_RX_FULL_F_Pos (2) |
| #define | UART_FSR_RX_FULL_F_Msk (0x1ul << UART_FSR_RX_FULL_F_Pos) |
| #define | UART_FSR_PE_F_Pos (4) |
| #define | UART_FSR_PE_F_Msk (0x1ul << UART_FSR_PE_F_Pos) |
| #define | UART_FSR_FE_F_Pos (5) |
| #define | UART_FSR_FE_F_Msk (0x1ul << UART_FSR_FE_F_Pos) |
| #define | UART_FSR_BI_F_Pos (6) |
| #define | UART_FSR_BI_F_Msk (0x1ul << UART_FSR_BI_F_Pos) |
| #define | UART_FSR_TX_OVER_F_Pos (8) |
| #define | UART_FSR_TX_OVER_F_Msk (0x1ul << UART_FSR_TX_OVER_F_Pos) |
| #define | UART_FSR_TX_EMPTY_F_Pos (9) |
| #define | UART_FSR_TX_EMPTY_F_Msk (0x1ul << UART_FSR_TX_EMPTY_F_Pos) |
| #define | UART_FSR_TX_FULL_F_Pos (10) |
| #define | UART_FSR_TX_FULL_F_Msk (0x1ul << UART_FSR_TX_FULL_F_Pos) |
| #define | UART_FSR_TE_F_Pos (11) |
| #define | UART_FSR_TE_F_Msk (0x1ul << UART_FSR_TE_F_Pos) |
| #define | UART_FSR_RX_POINTER_F_Pos (16) |
| #define | UART_FSR_RX_POINTER_F_Msk (0x1ful << UART_FSR_RX_POINTER_F_Pos) |
| #define | UART_FSR_TX_POINTER_F_Pos (24) |
| #define | UART_FSR_TX_POINTER_F_Msk (0x1ful << UART_FSR_TX_POINTER_F_Pos) |
| #define | UART_MCSR_LEV_RTS_Pos (0) |
| #define | UART_MCSR_LEV_RTS_Msk (0x1ul << UART_MCSR_LEV_RTS_Pos) |
| #define | UART_MCSR_RTS_ST_Pos (1) |
| #define | UART_MCSR_RTS_ST_Msk (0x1ul << UART_MCSR_RTS_ST_Pos) |
| #define | UART_MCSR_LEV_CTS_Pos (16) |
| #define | UART_MCSR_LEV_CTS_Msk (0x1ul << UART_MCSR_LEV_CTS_Pos) |
| #define | UART_MCSR_CTS_ST_Pos (17) |
| #define | UART_MCSR_CTS_ST_Msk (0x1ul << UART_MCSR_CTS_ST_Pos) |
| #define | UART_MCSR_DCT_F_Pos (18) |
| #define | UART_MCSR_DCT_F_Msk (0x1ul << UART_MCSR_DCT_F_Pos) |
| #define | UART_TMCTL_TOIC_Pos (0) |
| #define | UART_TMCTL_TOIC_Msk (0x1fful << UART_TMCTL_TOIC_Pos) |
| #define | UART_TMCTL_DLY_Pos (16) |
| #define | UART_TMCTL_DLY_Msk (0xfful << UART_TMCTL_DLY_Pos) |
| #define | UART_BAUD_BRD_Pos (0) |
| #define | UART_BAUD_BRD_Msk (0xfffful << UART_BAUD_BRD_Pos) |
| #define | UART_BAUD_DIV_16_EN_Pos (31) |
| #define | UART_BAUD_DIV_16_EN_Msk (0x1ul << UART_BAUD_DIV_16_EN_Pos) |
| #define | UART_IRCR_TX_SELECT_Pos (1) |
| #define | UART_IRCR_TX_SELECT_Msk (0x1ul << UART_IRCR_TX_SELECT_Pos) |
| #define | UART_IRCR_INV_TX_Pos (5) |
| #define | UART_IRCR_INV_TX_Msk (0x1ul << UART_IRCR_INV_TX_Pos) |
| #define | UART_IRCR_INV_RX_Pos (6) |
| #define | UART_IRCR_INV_RX_Msk (0x1ul << UART_IRCR_INV_RX_Pos) |
| #define | UART_ALT_CTL_LIN_TX_BCNT_Pos (0) |
| #define | UART_ALT_CTL_LIN_TX_BCNT_Msk (0x7ul << UART_ALT_CTL_LIN_TX_BCNT_Pos) |
| #define | UART_ALT_CTL_LIN_HEAD_SEL_Pos (4) |
| #define | UART_ALT_CTL_LIN_HEAD_SEL_Msk (0x3ul << UART_ALT_CTL_LIN_HEAD_SEL_Pos) |
| #define | UART_ALT_CTL_LIN_RX_EN_Pos (6) |
| #define | UART_ALT_CTL_LIN_RX_EN_Msk (0x1ul << UART_ALT_CTL_LIN_RX_EN_Pos) |
| #define | UART_ALT_CTL_LIN_TX_EN_Pos (7) |
| #define | UART_ALT_CTL_LIN_TX_EN_Msk (0x1ul << UART_ALT_CTL_LIN_TX_EN_Pos) |
| #define | UART_ALT_CTL_Bit_ERR_EN_Pos (8) |
| #define | UART_ALT_CTL_Bit_ERR_EN_Msk (0x1ul << UART_ALT_CTL_Bit_ERR_EN_Pos) |
| #define | UART_ALT_CTL_RS485_NMM_Pos (16) |
| #define | UART_ALT_CTL_RS485_NMM_Msk (0x1ul << UART_ALT_CTL_RS485_NMM_Pos) |
| #define | UART_ALT_CTL_RS485_AAD_Pos (17) |
| #define | UART_ALT_CTL_RS485_AAD_Msk (0x1ul << UART_ALT_CTL_RS485_AAD_Pos) |
| #define | UART_ALT_CTL_RS485_AUD_Pos (18) |
| #define | UART_ALT_CTL_RS485_AUD_Msk (0x1ul << UART_ALT_CTL_RS485_AUD_Pos) |
| #define | UART_ALT_CTL_RS485_ADD_EN_Pos (19) |
| #define | UART_ALT_CTL_RS485_ADD_EN_Msk (0x1ul << UART_ALT_CTL_RS485_ADD_EN_Pos) |
| #define | UART_ALT_CTL_ADDR_PID_MATCH_Pos (24) |
| #define | UART_ALT_CTL_ADDR_PID_MATCH_Msk (0xfful << UART_ALT_CTL_ADDR_PID_MATCH_Pos) |
| #define | UART_FUN_SEL_FUN_SEL_Pos (0) |
| #define | UART_FUN_SEL_FUN_SEL_Msk (0x3ul << UART_FUN_SEL_FUN_SEL_Pos) |
| #define | USBD_CTL_USB_EN_Pos (0) |
| #define | USBD_CTL_USB_EN_Msk (0x1ul << USBD_CTL_USB_EN_Pos) |
| #define | USBD_CTL_PHY_EN_Pos (1) |
| #define | USBD_CTL_PHY_EN_Msk (0x1ul << USBD_CTL_PHY_EN_Pos) |
| #define | USBD_CTL_PWRDB_Pos (2) |
| #define | USBD_CTL_PWRDB_Msk (0x1ul << USBD_CTL_PWRDB_Pos) |
| #define | USBD_CTL_DPPU_EN_Pos (3) |
| #define | USBD_CTL_DPPU_EN_Msk (0x1ul << USBD_CTL_DPPU_EN_Pos) |
| #define | USBD_CTL_DRVSE0_Pos (4) |
| #define | USBD_CTL_DRVSE0_Msk (0x1ul << USBD_CTL_DRVSE0_Pos) |
| #define | USBD_CTL_RWAKEUP_Pos (8) |
| #define | USBD_CTL_RWAKEUP_Msk (0x1ul << USBD_CTL_RWAKEUP_Pos) |
| #define | USBD_CTL_WAKEUP_EN_Pos (9) |
| #define | USBD_CTL_WAKEUP_EN_Msk (0x1ul << USBD_CTL_WAKEUP_EN_Pos) |
| #define | USBD_BUSSTS_USBRST_Pos (0) |
| #define | USBD_BUSSTS_USBRST_Msk (0x1ul << USBD_BUSSTS_USBRST_Pos) |
| #define | USBD_BUSSTS_SUSPEND_Pos (1) |
| #define | USBD_BUSSTS_SUSPEND_Msk (0x1ul << USBD_BUSSTS_SUSPEND_Pos) |
| #define | USBD_BUSSTS_RESUME_Pos (2) |
| #define | USBD_BUSSTS_RESUME_Msk (0x1ul << USBD_BUSSTS_RESUME_Pos) |
| #define | USBD_BUSSTS_TIMEOUT_Pos (3) |
| #define | USBD_BUSSTS_TIMEOUT_Msk (0x1ul << USBD_BUSSTS_TIMEOUT_Pos) |
| #define | USBD_BUSSTS_FLDET_Pos (4) |
| #define | USBD_BUSSTS_FLDET_Msk (0x1ul << USBD_BUSSTS_FLDET_Pos) |
| #define | USBD_INTEN_BUSEVT_IE_Pos (0) |
| #define | USBD_INTEN_BUSEVT_IE_Msk (0x1ul << USBD_INTEN_BUSEVT_IE_Pos) |
| #define | USBD_INTEN_USBEVT_IE_Pos (1) |
| #define | USBD_INTEN_USBEVT_IE_Msk (0x1ul << USBD_INTEN_USBEVT_IE_Pos) |
| #define | USBD_INTEN_FLDET_IE_Pos (2) |
| #define | USBD_INTEN_FLDET_IE_Msk (0x1ul << USBD_INTEN_FLDET_IE_Pos) |
| #define | USBD_INTEN_WAKEUP_IE_Pos (3) |
| #define | USBD_INTEN_WAKEUP_IE_Msk (0x1ul << USBD_INTEN_WAKEUP_IE_Pos) |
| #define | USBD_INTSTS_BUS_STS_Pos (0) |
| #define | USBD_INTSTS_BUS_STS_Msk (0x1ul << USBD_INTSTS_BUS_STS_Pos) |
| #define | USBD_INTSTS_USB_STS_Pos (1) |
| #define | USBD_INTSTS_USB_STS_Msk (0x1ul << USBD_INTSTS_USB_STS_Pos) |
| #define | USBD_INTSTS_FLD_STS_Pos (2) |
| #define | USBD_INTSTS_FLD_STS_Msk (0x1ul << USBD_INTSTS_FLD_STS_Pos) |
| #define | USBD_INTSTS_WKEUP_STS_Pos (3) |
| #define | USBD_INTSTS_WKEUP_STS_Msk (0x1ul << USBD_INTSTS_WKEUP_STS_Pos) |
| #define | USBD_INTSTS_EPEVT0_Pos (16) |
| #define | USBD_INTSTS_EPEVT0_Msk (0x1ul << USBD_INTSTS_EPEVT0_Pos) |
| #define | USBD_INTSTS_EPEVT1_Pos (17) |
| #define | USBD_INTSTS_EPEVT1_Msk (0x1ul << USBD_INTSTS_EPEVT1_Pos) |
| #define | USBD_INTSTS_EPEVT2_Pos (18) |
| #define | USBD_INTSTS_EPEVT2_Msk (0x1ul << USBD_INTSTS_EPEVT2_Pos) |
| #define | USBD_INTSTS_EPEVT3_Pos (19) |
| #define | USBD_INTSTS_EPEVT3_Msk (0x1ul << USBD_INTSTS_EPEVT3_Pos) |
| #define | USBD_INTSTS_EPEVT4_Pos (20) |
| #define | USBD_INTSTS_EPEVT4_Msk (0x1ul << USBD_INTSTS_EPEVT4_Pos) |
| #define | USBD_INTSTS_EPEVT5_Pos (21) |
| #define | USBD_INTSTS_EPEVT5_Msk (0x1ul << USBD_INTSTS_EPEVT5_Pos) |
| #define | USBD_INTSTS_SETUP_Pos (31) |
| #define | USBD_INTSTS_SETUP_Msk (0x1ul << USBD_INTSTS_SETUP_Pos) |
| #define | USBD_FADDR_FADDR_Pos (0) |
| #define | USBD_FADDR_FADDR_Msk (0x7ful << USBD_FADDR_FADDR_Pos) |
| #define | USBD_EPSTS_OVERRUN_Pos (7) |
| #define | USBD_EPSTS_OVERRUN_Msk (0x1ul << USBD_EPSTS_OVERRUN_Pos) |
| #define | USBD_EPSTS_EPSTS0_Pos (8) |
| #define | USBD_EPSTS_EPSTS0_Msk (0xful << USBD_EPSTS_EPSTS0_Pos) |
| #define | USBD_EPSTS_EPSTS1_Pos (12) |
| #define | USBD_EPSTS_EPSTS1_Msk (0xful << USBD_EPSTS_EPSTS1_Pos) |
| #define | USBD_EPSTS_EPSTS2_Pos (16) |
| #define | USBD_EPSTS_EPSTS2_Msk (0xful << USBD_EPSTS_EPSTS2_Pos) |
| #define | USBD_EPSTS_EPSTS3_Pos (20) |
| #define | USBD_EPSTS_EPSTS3_Msk (0xful << USBD_EPSTS_EPSTS3_Pos) |
| #define | USBD_EPSTS_EPSTS4_Pos (24) |
| #define | USBD_EPSTS_EPSTS4_Msk (0xful << USBD_EPSTS_EPSTS4_Pos) |
| #define | USBD_EPSTS_EPSTS5_Pos (28) |
| #define | USBD_EPSTS_EPSTS5_Msk (0xful << USBD_EPSTS_EPSTS5_Pos) |
| #define | USBD_BUFSEG_BUFSEG_Pos (3) |
| #define | USBD_BUFSEG_BUFSEG_Msk (0x3ful << USBD_BUFSEG_BUFSEG_Pos) |
| #define | USBD_MXPLD_MXPLD_Pos (0) |
| #define | USBD_MXPLD_MXPLD_Msk (0x1fful << USBD_MXPLD_MXPLD_Pos) |
| #define | USBD_CFG_EP_NUM_Pos (0) |
| #define | USBD_CFG_EP_NUM_Msk (0xful << USBD_CFG_EP_NUM_Pos) |
| #define | USBD_CFG_ISOCH_Pos (4) |
| #define | USBD_CFG_ISOCH_Msk (0x1ul << USBD_CFG_ISOCH_Pos) |
| #define | USBD_CFG_EPMODE_Pos (5) |
| #define | USBD_CFG_EPMODE_Msk (0x3ul << USBD_CFG_EPMODE_Pos) |
| #define | USBD_CFG_DSQ_SYNC_Pos (7) |
| #define | USBD_CFG_DSQ_SYNC_Msk (0x1ul << USBD_CFG_DSQ_SYNC_Pos) |
| #define | USBD_CFG_CSTALL_Pos (8) |
| #define | USBD_CFG_CSTALL_Msk (0x1ul << USBD_CFG_CSTALL_Pos) |
| #define | USBD_CFG_SSTALL_Pos (9) |
| #define | USBD_CFG_SSTALL_Msk (0x1ul << USBD_CFG_SSTALL_Pos) |
| #define | USBD_CFG_CLRRDY_Pos (15) |
| #define | USBD_CFG_CLRRDY_Msk (0x1ul << USBD_CFG_CLRRDY_Pos) |
| #define | USBD_PDMA_PDMA_RW_Pos (0) |
| #define | USBD_PDMA_PDMA_RW_Msk (0x1ul << USBD_PDMA_PDMA_RW_Pos) |
| #define | USBD_PDMA_PDMA_TRG_Pos (1) |
| #define | USBD_PDMA_PDMA_TRG_Msk (0x1ul << USBD_PDMA_PDMA_TRG_Pos) |
| #define | USBD_PDMA_BYTEM_Pos (2) |
| #define | USBD_PDMA_BYTEM_Msk (0x1ul << USBD_PDMA_BYTEM_Pos) |
| #define | USBD_PDMA_PDMA_RST_Pos (3) |
| #define | USBD_PDMA_PDMA_RST_Msk (0x1ul << USBD_PDMA_PDMA_RST_Pos) |
| #define | WDT_CTL_WTR_Pos (0) |
| #define | WDT_CTL_WTR_Msk (0x1ul << WDT_CTL_WTR_Pos) |
| #define | WDT_CTL_WTRE_Pos (1) |
| #define | WDT_CTL_WTRE_Msk (0x1ul << WDT_CTL_WTRE_Pos) |
| #define | WDT_CTL_WTWKE_Pos (2) |
| #define | WDT_CTL_WTWKE_Msk (0x1ul << WDT_CTL_WTWKE_Pos) |
| #define | WDT_CTL_WTE_Pos (3) |
| #define | WDT_CTL_WTE_Msk (0x1ul << WDT_CTL_WTE_Pos) |
| #define | WDT_CTL_WTIS_Pos (4) |
| #define | WDT_CTL_WTIS_Msk (0x7ul << WDT_CTL_WTIS_Pos) |
| #define | WDT_IER_IE_Pos (0) |
| #define | WDT_IER_IE_Msk (0x1ul << WDT_IER_IE_Pos) |
| #define | WDT_ISR_IS_Pos (0) |
| #define | WDT_ISR_IS_Msk (0x1ul << WDT_ISR_IS_Pos) |
| #define | WDT_ISR_RST_IS_Pos (1) |
| #define | WDT_ISR_RST_IS_Msk (0x1ul << WDT_ISR_RST_IS_Pos) |
| #define | WDT_ISR_WAKE_IS_Pos (2) |
| #define | WDT_ISR_WAKE_IS_Msk (0x1ul << WDT_ISR_WAKE_IS_Pos) |
Typedefs | |
| typedef enum IRQn | IRQn_Type |
| typedef volatile unsigned char | vu8 |
| Define 8-bit unsigned volatile data type. More... | |
| typedef volatile unsigned short | vu16 |
| Define 16-bit unsigned volatile data type. More... | |
| typedef volatile unsigned long | vu32 |
| Define 32-bit unsigned volatile data type. More... | |
Enumerations | |
| enum | IRQn { NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, SVCall_IRQn = -5, PendSV_IRQn = -2, SysTick_IRQn = -1, BOD_IRQn = 0, WDT_IRQn = 1, EINT0_IRQn = 2, EINT1_IRQn = 3, GPABC_IRQn = 4, GPDEF_IRQn = 5, PWM0_IRQn = 6, PWM1_IRQn = 7, TMR0_IRQn = 8, TMR1_IRQn = 9, TMR2_IRQn = 10, TMR3_IRQn = 11, UART0_IRQn = 12, UART1_IRQn = 13, SPI0_IRQn = 14, SPI1_IRQn = 15, SPI2_IRQn = 16, HIRC_IRQn = 17, I2C0_IRQn = 18, I2C1_IRQn = 19, SC0_IRQn = 21, SC1_IRQn = 22, USBD_IRQn = 23, PDMA_IRQn = 26, I2S_IRQn = 27, PDWU_IRQn = 28, ADC_IRQn = 29, RTC_IRQn = 31 } |
Nano100 series peripheral access layer header file. This file contains all the peripheral register's definitions, bits definitions and memory mapping for NuMicro Nano100 series MCU.
Definition in file Nano100Series.h.
| #define DMA_GCR_DSSR0_CH1_SEL_Msk (0x1ful << DMA_GCR_DSSR0_CH1_SEL_Pos) |
DMA_GCR_T::DSSR0: CH1_SEL Mask
Definition at line 1851 of file Nano100Series.h.
| #define DMA_GCR_DSSR0_CH1_SEL_Pos (8) |
DMA_GCR_T::DSSR0: CH1_SEL Position
Definition at line 1850 of file Nano100Series.h.
| #define DMA_GCR_DSSR0_CH2_SEL_Msk (0x1ful << DMA_GCR_DSSR0_CH2_SEL_Pos) |
DMA_GCR_T::DSSR0: CH2_SEL Mask
Definition at line 1854 of file Nano100Series.h.
| #define DMA_GCR_DSSR0_CH2_SEL_Pos (16) |
DMA_GCR_T::DSSR0: CH2_SEL Position
Definition at line 1853 of file Nano100Series.h.
| #define DMA_GCR_DSSR0_CH3_SEL_Msk (0x1ful << DMA_GCR_DSSR0_CH3_SEL_Pos) |
DMA_GCR_T::DSSR0: CH3_SEL Mask
Definition at line 1857 of file Nano100Series.h.
| #define DMA_GCR_DSSR0_CH3_SEL_Pos (24) |
DMA_GCR_T::DSSR0: CH3_SEL Position
Definition at line 1856 of file Nano100Series.h.
| #define DMA_GCR_DSSR1_CH4_SEL_Msk (0x1ful << DMA_GCR_DSSR1_CH4_SEL_Pos) |
DMA_GCR_T::DSSR1: CH4_SEL Mask
Definition at line 1860 of file Nano100Series.h.
| #define DMA_GCR_DSSR1_CH4_SEL_Pos (0) |
DMA_GCR_T::DSSR1: CH4_SEL Position
Definition at line 1859 of file Nano100Series.h.
| #define DMA_GCR_GCRCSR_CLK0_EN_Msk (0x1ul << DMA_GCR_GCRCSR_CLK0_EN_Pos) |
DMA_GCR_T::GCRCSR: CLK0_EN Mask
Definition at line 1836 of file Nano100Series.h.
| #define DMA_GCR_GCRCSR_CLK0_EN_Pos (8) |
@addtogroup DMA_GCR_CONST DMA_GCR Bit Field Definition Constant Definitions for DMA_GCR Controller
DMA_GCR_T::GCRCSR: CLK0_EN Position
Definition at line 1835 of file Nano100Series.h.
| #define DMA_GCR_GCRCSR_CLK1_EN_Msk (0x1ul << DMA_GCR_GCRCSR_CLK1_EN_Pos) |
DMA_GCR_T::GCRCSR: CLK1_EN Mask
Definition at line 1839 of file Nano100Series.h.
| #define DMA_GCR_GCRCSR_CLK1_EN_Pos (9) |
DMA_GCR_T::GCRCSR: CLK1_EN Position
Definition at line 1838 of file Nano100Series.h.
| #define DMA_GCR_GCRCSR_CLK2_EN_Msk (0x1ul << DMA_GCR_GCRCSR_CLK2_EN_Pos) |
DMA_GCR_T::GCRCSR: CLK2_EN Mask
Definition at line 1842 of file Nano100Series.h.
| #define DMA_GCR_GCRCSR_CLK2_EN_Pos (10) |
DMA_GCR_T::GCRCSR: CLK2_EN Position
Definition at line 1841 of file Nano100Series.h.
| #define DMA_GCR_GCRCSR_CLK3_EN_Msk (0x1ul << DMA_GCR_GCRCSR_CLK3_EN_Pos) |
DMA_GCR_T::GCRCSR: CLK3_EN Mask
Definition at line 1845 of file Nano100Series.h.
| #define DMA_GCR_GCRCSR_CLK3_EN_Pos (11) |
DMA_GCR_T::GCRCSR: CLK3_EN Position
Definition at line 1844 of file Nano100Series.h.
| #define DMA_GCR_GCRCSR_CLK4_EN_Msk (0x1ul << DMA_GCR_GCRCSR_CLK4_EN_Pos) |
DMA_GCR_T::GCRCSR: CLK4_EN Mask
Definition at line 1848 of file Nano100Series.h.
| #define DMA_GCR_GCRCSR_CLK4_EN_Pos (12) |
DMA_GCR_T::GCRCSR: CLK4_EN Position
Definition at line 1847 of file Nano100Series.h.
| #define DMA_GCR_GCRISR_INTR0_Msk (0x1ul << DMA_GCR_GCRISR_INTR0_Pos) |
DMA_GCR_T::GCRISR: INTR0 Mask
Definition at line 1863 of file Nano100Series.h.
| #define DMA_GCR_GCRISR_INTR0_Pos (0) |
DMA_GCR_T::GCRISR: INTR0 Position
Definition at line 1862 of file Nano100Series.h.
| #define DMA_GCR_GCRISR_INTR1_Msk (0x1ul << DMA_GCR_GCRISR_INTR1_Pos) |
DMA_GCR_T::GCRISR: INTR1 Mask
Definition at line 1866 of file Nano100Series.h.
| #define DMA_GCR_GCRISR_INTR1_Pos (1) |
DMA_GCR_T::GCRISR: INTR1 Position
Definition at line 1865 of file Nano100Series.h.
| #define DMA_GCR_GCRISR_INTR2_Msk (0x1ul << DMA_GCR_GCRISR_INTR2_Pos) |
DMA_GCR_T::GCRISR: INTR2 Mask
Definition at line 1869 of file Nano100Series.h.
| #define DMA_GCR_GCRISR_INTR2_Pos (2) |
DMA_GCR_T::GCRISR: INTR2 Position
Definition at line 1868 of file Nano100Series.h.
| #define DMA_GCR_GCRISR_INTR3_Msk (0x1ul << DMA_GCR_GCRISR_INTR3_Pos) |
DMA_GCR_T::GCRISR: INTR3 Mask
Definition at line 1872 of file Nano100Series.h.
| #define DMA_GCR_GCRISR_INTR3_Pos (3) |
DMA_GCR_T::GCRISR: INTR3 Position
Definition at line 1871 of file Nano100Series.h.
| #define DMA_GCR_GCRISR_INTR4_Msk (0x1ul << DMA_GCR_GCRISR_INTR4_Pos) |
DMA_GCR_T::GCRISR: INTR4 Mask
Definition at line 1875 of file Nano100Series.h.
| #define DMA_GCR_GCRISR_INTR4_Pos (4) |
DMA_GCR_T::GCRISR: INTR4 Position
Definition at line 1874 of file Nano100Series.h.
| #define EBI_EBICON_ExtBW16_Msk (0x1ul << EBI_EBICON_ExtBW16_Pos) |
EBI_T::EBICON: ExtBW16 Mask
Definition at line 2111 of file Nano100Series.h.
| #define EBI_EBICON_ExtBW16_Pos (1) |
EBI_T::EBICON: ExtBW16 Position
Definition at line 2110 of file Nano100Series.h.
| #define EBI_EBICON_ExtEN_Msk (0x1ul << EBI_EBICON_ExtEN_Pos) |
EBI_T::EBICON: ExtEN Mask
Definition at line 2108 of file Nano100Series.h.
| #define EBI_EBICON_ExtEN_Pos (0) |
@addtogroup EBI_CONST EBI Bit Field Definition Constant Definitions for EBI Controller
EBI_T::EBICON: ExtEN Position
Definition at line 2107 of file Nano100Series.h.
| #define EBI_EBICON_ExttALE_Msk (0x7ul << EBI_EBICON_ExttALE_Pos) |
EBI_T::EBICON: ExttALE Mask
Definition at line 2120 of file Nano100Series.h.
| #define EBI_EBICON_ExttALE_Pos (16) |
EBI_T::EBICON: ExttALE Position
Definition at line 2119 of file Nano100Series.h.
| #define EBI_EBICON_MCLKDIV_Msk (0x7ul << EBI_EBICON_MCLKDIV_Pos) |
EBI_T::EBICON: MCLKDIV Mask
Definition at line 2114 of file Nano100Series.h.
| #define EBI_EBICON_MCLKDIV_Pos (8) |
EBI_T::EBICON: MCLKDIV Position
Definition at line 2113 of file Nano100Series.h.
| #define EBI_EBICON_MCLKEN_Msk (0x1ul << EBI_EBICON_MCLKEN_Pos) |
EBI_T::EBICON: MCLKEN Mask
Definition at line 2117 of file Nano100Series.h.
| #define EBI_EBICON_MCLKEN_Pos (11) |
EBI_T::EBICON: MCLKEN Position
Definition at line 2116 of file Nano100Series.h.
| #define EBI_EXTIME_ExtIR2R_Msk (0xful << EBI_EXTIME_ExtIR2R_Pos) |
EBI_T::EXTIME: ExtIR2R Mask
Definition at line 2135 of file Nano100Series.h.
| #define EBI_EXTIME_ExtIR2R_Pos (24) |
EBI_T::EXTIME: ExtIR2R Position
Definition at line 2134 of file Nano100Series.h.
| #define EBI_EXTIME_ExtIR2W_Msk (0xful << EBI_EXTIME_ExtIR2W_Pos) |
EBI_T::EXTIME: ExtIR2W Mask
Definition at line 2132 of file Nano100Series.h.
| #define EBI_EXTIME_ExtIR2W_Pos (16) |
EBI_T::EXTIME: ExtIR2W Position
Definition at line 2131 of file Nano100Series.h.
| #define EBI_EXTIME_ExtIW2X_Msk (0xful << EBI_EXTIME_ExtIW2X_Pos) |
EBI_T::EXTIME: ExtIW2X Mask
Definition at line 2129 of file Nano100Series.h.
| #define EBI_EXTIME_ExtIW2X_Pos (12) |
EBI_T::EXTIME: ExtIW2X Position
Definition at line 2128 of file Nano100Series.h.
| #define EBI_EXTIME_ExttACC_Msk (0x1ful << EBI_EXTIME_ExttACC_Pos) |
EBI_T::EXTIME: ExttACC Mask
Definition at line 2123 of file Nano100Series.h.
| #define EBI_EXTIME_ExttACC_Pos (0) |
EBI_T::EXTIME: ExttACC Position
Definition at line 2122 of file Nano100Series.h.
| #define EBI_EXTIME_ExttAHD_Msk (0x7ul << EBI_EXTIME_ExttAHD_Pos) |
EBI_T::EXTIME: ExttAHD Mask
Definition at line 2126 of file Nano100Series.h.
| #define EBI_EXTIME_ExttAHD_Pos (8) |
EBI_T::EXTIME: ExttAHD Position
Definition at line 2125 of file Nano100Series.h.
| #define FMC_DFBADR_DFBA_Msk (0xfffffffful << FMC_DFBADR_DFBA_Pos) |
FMC_T::DFBADR: DFBA Mask
Definition at line 2369 of file Nano100Series.h.
| #define FMC_DFBADR_DFBA_Pos (0) |
FMC_T::DFBADR: DFBA Position
Definition at line 2368 of file Nano100Series.h.
| #define FMC_ISPADR_ISPADR_Msk (0xfffffffful << FMC_ISPADR_ISPADR_Pos) |
FMC_T::ISPADR: ISPADR Mask
Definition at line 2351 of file Nano100Series.h.
| #define FMC_ISPADR_ISPADR_Pos (0) |
FMC_T::ISPADR: ISPADR Position
Definition at line 2350 of file Nano100Series.h.
| #define FMC_ISPCMD_FCEN_Msk (0x1ul << FMC_ISPCMD_FCEN_Pos) |
FMC_T::ISPCMD: FCEN Mask
Definition at line 2360 of file Nano100Series.h.
| #define FMC_ISPCMD_FCEN_Pos (4) |
FMC_T::ISPCMD: FCEN Position
Definition at line 2359 of file Nano100Series.h.
| #define FMC_ISPCMD_FCTRL_Msk (0xful << FMC_ISPCMD_FCTRL_Pos) |
FMC_T::ISPCMD: FCTRL Mask
Definition at line 2357 of file Nano100Series.h.
| #define FMC_ISPCMD_FCTRL_Pos (0) |
FMC_T::ISPCMD: FCTRL Position
Definition at line 2356 of file Nano100Series.h.
| #define FMC_ISPCMD_FOEN_Msk (0x1ul << FMC_ISPCMD_FOEN_Pos) |
FMC_T::ISPCMD: FOEN Mask
Definition at line 2363 of file Nano100Series.h.
| #define FMC_ISPCMD_FOEN_Pos (5) |
FMC_T::ISPCMD: FOEN Position
Definition at line 2362 of file Nano100Series.h.
| #define FMC_ISPCON_APUEN_Msk (0x1ul << FMC_ISPCON_APUEN_Pos) |
FMC_T::ISPCON: APUEN Mask
Definition at line 2330 of file Nano100Series.h.
| #define FMC_ISPCON_APUEN_Pos (3) |
FMC_T::ISPCON: APUEN Position
Definition at line 2329 of file Nano100Series.h.
| #define FMC_ISPCON_BS_Msk (0x1ul << FMC_ISPCON_BS_Pos) |
FMC_T::ISPCON: BS Mask
Definition at line 2327 of file Nano100Series.h.
| #define FMC_ISPCON_BS_Pos (1) |
FMC_T::ISPCON: BS Position
Definition at line 2326 of file Nano100Series.h.
| #define FMC_ISPCON_CFGUEN_Msk (0x1ul << FMC_ISPCON_CFGUEN_Pos) |
FMC_T::ISPCON: CFGUEN Mask
Definition at line 2333 of file Nano100Series.h.
| #define FMC_ISPCON_CFGUEN_Pos (4) |
FMC_T::ISPCON: CFGUEN Position
Definition at line 2332 of file Nano100Series.h.
| #define FMC_ISPCON_ET_Msk (0x7ul << FMC_ISPCON_ET_Pos) |
FMC_T::ISPCON: ET Mask
Definition at line 2348 of file Nano100Series.h.
| #define FMC_ISPCON_ET_Pos (12) |
FMC_T::ISPCON: ET Position
Definition at line 2347 of file Nano100Series.h.
| #define FMC_ISPCON_ISPEN_Msk (0x1ul << FMC_ISPCON_ISPEN_Pos) |
FMC_T::ISPCON: ISPEN Mask
Definition at line 2324 of file Nano100Series.h.
| #define FMC_ISPCON_ISPEN_Pos (0) |
@addtogroup FMC_CONST FMC Bit Field Definition Constant Definitions for FMC Controller
FMC_T::ISPCON: ISPEN Position
Definition at line 2323 of file Nano100Series.h.
| #define FMC_ISPCON_ISPFF_Msk (0x1ul << FMC_ISPCON_ISPFF_Pos) |
FMC_T::ISPCON: ISPFF Mask
Definition at line 2339 of file Nano100Series.h.
| #define FMC_ISPCON_ISPFF_Pos (6) |
FMC_T::ISPCON: ISPFF Position
Definition at line 2338 of file Nano100Series.h.
| #define FMC_ISPCON_LDUEN_Msk (0x1ul << FMC_ISPCON_LDUEN_Pos) |
FMC_T::ISPCON: LDUEN Mask
Definition at line 2336 of file Nano100Series.h.
| #define FMC_ISPCON_LDUEN_Pos (5) |
FMC_T::ISPCON: LDUEN Position
Definition at line 2335 of file Nano100Series.h.
| #define FMC_ISPCON_PT_Msk (0x7ul << FMC_ISPCON_PT_Pos) |
FMC_T::ISPCON: PT Mask
Definition at line 2345 of file Nano100Series.h.
| #define FMC_ISPCON_PT_Pos (8) |
FMC_T::ISPCON: PT Position
Definition at line 2344 of file Nano100Series.h.
| #define FMC_ISPCON_SWRST_Msk (0x1ul << FMC_ISPCON_SWRST_Pos) |
FMC_T::ISPCON: SWRST Mask
Definition at line 2342 of file Nano100Series.h.
| #define FMC_ISPCON_SWRST_Pos (7) |
FMC_T::ISPCON: SWRST Position
Definition at line 2341 of file Nano100Series.h.
| #define FMC_ISPDAT_ISPDAT_Msk (0xfffffffful << FMC_ISPDAT_ISPDAT_Pos) |
FMC_T::ISPDAT: ISPDAT Mask
Definition at line 2354 of file Nano100Series.h.
| #define FMC_ISPDAT_ISPDAT_Pos (0) |
FMC_T::ISPDAT: ISPDAT Position
Definition at line 2353 of file Nano100Series.h.
| #define FMC_ISPSTA_CBS_Msk (0x3ul << FMC_ISPSTA_CBS_Pos) |
FMC_T::ISPSTA: CBS Mask
Definition at line 2375 of file Nano100Series.h.
| #define FMC_ISPSTA_CBS_Pos (1) |
FMC_T::ISPSTA: CBS Position
Definition at line 2374 of file Nano100Series.h.
| #define FMC_ISPSTA_ISPBUSY_Msk (0x1ul << FMC_ISPSTA_ISPBUSY_Pos) |
FMC_T::ISPSTA: ISPBUSY Mask
Definition at line 2372 of file Nano100Series.h.
| #define FMC_ISPSTA_ISPBUSY_Pos (0) |
FMC_T::ISPSTA: ISPBUSY Position
Definition at line 2371 of file Nano100Series.h.
| #define FMC_ISPSTA_ISPFF_Msk (0x1ul << FMC_ISPSTA_ISPFF_Pos) |
FMC_T::ISPSTA: ISPFF Mask
Definition at line 2378 of file Nano100Series.h.
| #define FMC_ISPSTA_ISPFF_Pos (6) |
FMC_T::ISPSTA: ISPFF Position
Definition at line 2377 of file Nano100Series.h.
| #define FMC_ISPTRG_ISPGO_Msk (0x1ul << FMC_ISPTRG_ISPGO_Pos) |
FMC_T::ISPTRG: ISPGO Mask
Definition at line 2366 of file Nano100Series.h.
| #define FMC_ISPTRG_ISPGO_Pos (0) |
FMC_T::ISPTRG: ISPGO Position
Definition at line 2365 of file Nano100Series.h.
| #define GP_DBEN_DBEN_Msk (0xfffful << GP_DBEN_DBEN_Pos) |
GPIO_T::DBEN: DBEN Mask
Definition at line 4422 of file Nano100Series.h.
| #define GP_DBEN_DBEN_Pos (0) |
GPIO_T::DBEN: DBEN Position
Definition at line 4421 of file Nano100Series.h.
| #define GP_DBNCECON_DBCLK_ON_Msk (0x1ul << GP_DBNCECON_DBCLK_ON_Pos) |
GP_DB_T::DBNCECON: DBCLK_ON Mask
Definition at line 4541 of file Nano100Series.h.
| #define GP_DBNCECON_DBCLK_ON_Pos (5) |
GP_DB_T::DBNCECON: DBCLK_ON Position
Definition at line 4540 of file Nano100Series.h.
| #define GP_DBNCECON_DBCLKSEL_Msk (0xful << GP_DBNCECON_DBCLKSEL_Pos) |
GP_DB_T::DBNCECON: DBCLKSEL Mask
Definition at line 4535 of file Nano100Series.h.
| #define GP_DBNCECON_DBCLKSEL_Pos (0) |
@addtogroup GP_DB_CONST GP_DB Bit Field Definition Constant Definitions for GP_DB Controller
GP_DB_T::DBNCECON: DBCLKSEL Position
Definition at line 4534 of file Nano100Series.h.
| #define GP_DBNCECON_DBCLKSRC_Msk (0x1ul << GP_DBNCECON_DBCLKSRC_Pos) |
GP_DB_T::DBNCECON: DBCLKSRC Mask
Definition at line 4538 of file Nano100Series.h.
| #define GP_DBNCECON_DBCLKSRC_Pos (4) |
GP_DB_T::DBNCECON: DBCLKSRC Position
Definition at line 4537 of file Nano100Series.h.
| #define GP_DMASK_DMASK_Msk (0xfffful << GP_DMASK_DMASK_Pos) |
GPIO_T::DMASK: DMASK Mask
Definition at line 4416 of file Nano100Series.h.
| #define GP_DMASK_DMASK_Pos (0) |
GPIO_T::DMASK: DMASK Position
Definition at line 4415 of file Nano100Series.h.
| #define GP_DOUT_DOUT_Msk (0xfffful << GP_DOUT_DOUT_Pos) |
GPIO_T::DOUT: DOUT Mask
Definition at line 4413 of file Nano100Series.h.
| #define GP_DOUT_DOUT_Pos (0) |
GPIO_T::DOUT: DOUT Position
Definition at line 4412 of file Nano100Series.h.
| #define GP_IER_FIER0_Msk (0x1ul << GP_IER_FIER0_Pos) |
GPIO_T::IER: FIER0 Mask
Definition at line 4428 of file Nano100Series.h.
| #define GP_IER_FIER0_Pos (0) |
GPIO_T::IER: FIER0 Position
Definition at line 4427 of file Nano100Series.h.
| #define GP_IER_FIER10_Msk (0x1ul << GP_IER_FIER10_Pos) |
GPIO_T::IER: FIER10 Mask
Definition at line 4458 of file Nano100Series.h.
| #define GP_IER_FIER10_Pos (10) |
GPIO_T::IER: FIER10 Position
Definition at line 4457 of file Nano100Series.h.
| #define GP_IER_FIER11_Msk (0x1ul << GP_IER_FIER11_Pos) |
GPIO_T::IER: FIER11 Mask
Definition at line 4461 of file Nano100Series.h.
| #define GP_IER_FIER11_Pos (11) |
GPIO_T::IER: FIER11 Position
Definition at line 4460 of file Nano100Series.h.
| #define GP_IER_FIER12_Msk (0x1ul << GP_IER_FIER12_Pos) |
GPIO_T::IER: FIER12 Mask
Definition at line 4464 of file Nano100Series.h.
| #define GP_IER_FIER12_Pos (12) |
GPIO_T::IER: FIER12 Position
Definition at line 4463 of file Nano100Series.h.
| #define GP_IER_FIER13_Msk (0x1ul << GP_IER_FIER13_Pos) |
GPIO_T::IER: FIER13 Mask
Definition at line 4467 of file Nano100Series.h.
| #define GP_IER_FIER13_Pos (13) |
GPIO_T::IER: FIER13 Position
Definition at line 4466 of file Nano100Series.h.
| #define GP_IER_FIER14_Msk (0x1ul << GP_IER_FIER14_Pos) |
GPIO_T::IER: FIER14 Mask
Definition at line 4470 of file Nano100Series.h.
| #define GP_IER_FIER14_Pos (14) |
GPIO_T::IER: FIER14 Position
Definition at line 4469 of file Nano100Series.h.
| #define GP_IER_FIER15_Msk (0x1ul << GP_IER_FIER15_Pos) |
GPIO_T::IER: FIER15 Mask
Definition at line 4473 of file Nano100Series.h.
| #define GP_IER_FIER15_Pos (15) |
GPIO_T::IER: FIER15 Position
Definition at line 4472 of file Nano100Series.h.
| #define GP_IER_FIER1_Msk (0x1ul << GP_IER_FIER1_Pos) |
GPIO_T::IER: FIER1 Mask
Definition at line 4431 of file Nano100Series.h.
| #define GP_IER_FIER1_Pos (1) |
GPIO_T::IER: FIER1 Position
Definition at line 4430 of file Nano100Series.h.
| #define GP_IER_FIER2_Msk (0x1ul << GP_IER_FIER2_Pos) |
GPIO_T::IER: FIER2 Mask
Definition at line 4434 of file Nano100Series.h.
| #define GP_IER_FIER2_Pos (2) |
GPIO_T::IER: FIER2 Position
Definition at line 4433 of file Nano100Series.h.
| #define GP_IER_FIER3_Msk (0x1ul << GP_IER_FIER3_Pos) |
GPIO_T::IER: FIER3 Mask
Definition at line 4437 of file Nano100Series.h.
| #define GP_IER_FIER3_Pos (3) |
GPIO_T::IER: FIER3 Position
Definition at line 4436 of file Nano100Series.h.
| #define GP_IER_FIER4_Msk (0x1ul << GP_IER_FIER4_Pos) |
GPIO_T::IER: FIER4 Mask
Definition at line 4440 of file Nano100Series.h.
| #define GP_IER_FIER4_Pos (4) |
GPIO_T::IER: FIER4 Position
Definition at line 4439 of file Nano100Series.h.
| #define GP_IER_FIER5_Msk (0x1ul << GP_IER_FIER5_Pos) |
GPIO_T::IER: FIER5 Mask
Definition at line 4443 of file Nano100Series.h.
| #define GP_IER_FIER5_Pos (5) |
GPIO_T::IER: FIER5 Position
Definition at line 4442 of file Nano100Series.h.
| #define GP_IER_FIER6_Msk (0x1ul << GP_IER_FIER6_Pos) |
GPIO_T::IER: FIER6 Mask
Definition at line 4446 of file Nano100Series.h.
| #define GP_IER_FIER6_Pos (6) |
GPIO_T::IER: FIER6 Position
Definition at line 4445 of file Nano100Series.h.
| #define GP_IER_FIER7_Msk (0x1ul << GP_IER_FIER7_Pos) |
GPIO_T::IER: FIER7 Mask
Definition at line 4449 of file Nano100Series.h.
| #define GP_IER_FIER7_Pos (7) |
GPIO_T::IER: FIER7 Position
Definition at line 4448 of file Nano100Series.h.
| #define GP_IER_FIER8_Msk (0x1ul << GP_IER_FIER8_Pos) |
GPIO_T::IER: FIER8 Mask
Definition at line 4452 of file Nano100Series.h.
| #define GP_IER_FIER8_Pos (8) |
GPIO_T::IER: FIER8 Position
Definition at line 4451 of file Nano100Series.h.
| #define GP_IER_FIER9_Msk (0x1ul << GP_IER_FIER9_Pos) |
GPIO_T::IER: FIER9 Mask
Definition at line 4455 of file Nano100Series.h.
| #define GP_IER_FIER9_Pos (9) |
GPIO_T::IER: FIER9 Position
Definition at line 4454 of file Nano100Series.h.
| #define GP_IER_RIER0_Msk (0x1ul << GP_IER_RIER0_Pos) |
GPIO_T::IER: RIER0 Mask
Definition at line 4476 of file Nano100Series.h.
| #define GP_IER_RIER0_Pos (16) |
GPIO_T::IER: RIER0 Position
Definition at line 4475 of file Nano100Series.h.
| #define GP_IER_RIER10_Msk (0x1ul << GP_IER_RIER10_Pos) |
GPIO_T::IER: RIER10 Mask
Definition at line 4506 of file Nano100Series.h.
| #define GP_IER_RIER10_Pos (26) |
GPIO_T::IER: RIER10 Position
Definition at line 4505 of file Nano100Series.h.
| #define GP_IER_RIER11_Msk (0x1ul << GP_IER_RIER11_Pos) |
GPIO_T::IER: RIER11 Mask
Definition at line 4509 of file Nano100Series.h.
| #define GP_IER_RIER11_Pos (27) |
GPIO_T::IER: RIER11 Position
Definition at line 4508 of file Nano100Series.h.
| #define GP_IER_RIER12_Msk (0x1ul << GP_IER_RIER12_Pos) |
GPIO_T::IER: RIER12 Mask
Definition at line 4512 of file Nano100Series.h.
| #define GP_IER_RIER12_Pos (28) |
GPIO_T::IER: RIER12 Position
Definition at line 4511 of file Nano100Series.h.
| #define GP_IER_RIER13_Msk (0x1ul << GP_IER_RIER13_Pos) |
GPIO_T::IER: RIER13 Mask
Definition at line 4515 of file Nano100Series.h.
| #define GP_IER_RIER13_Pos (29) |
GPIO_T::IER: RIER13 Position
Definition at line 4514 of file Nano100Series.h.
| #define GP_IER_RIER14_Msk (0x1ul << GP_IER_RIER14_Pos) |
GPIO_T::IER: RIER14 Mask
Definition at line 4518 of file Nano100Series.h.
| #define GP_IER_RIER14_Pos (30) |
GPIO_T::IER: RIER14 Position
Definition at line 4517 of file Nano100Series.h.
| #define GP_IER_RIER15_Msk (0x1ul << GP_IER_RIER15_Pos) |
GPIO_T::IER: RIER15 Mask
Definition at line 4521 of file Nano100Series.h.
| #define GP_IER_RIER15_Pos (31) |
GPIO_T::IER: RIER15 Position
Definition at line 4520 of file Nano100Series.h.
| #define GP_IER_RIER1_Msk (0x1ul << GP_IER_RIER1_Pos) |
GPIO_T::IER: RIER1 Mask
Definition at line 4479 of file Nano100Series.h.
| #define GP_IER_RIER1_Pos (17) |
GPIO_T::IER: RIER1 Position
Definition at line 4478 of file Nano100Series.h.
| #define GP_IER_RIER2_Msk (0x1ul << GP_IER_RIER2_Pos) |
GPIO_T::IER: RIER2 Mask
Definition at line 4482 of file Nano100Series.h.
| #define GP_IER_RIER2_Pos (18) |
GPIO_T::IER: RIER2 Position
Definition at line 4481 of file Nano100Series.h.
| #define GP_IER_RIER3_Msk (0x1ul << GP_IER_RIER3_Pos) |
GPIO_T::IER: RIER3 Mask
Definition at line 4485 of file Nano100Series.h.
| #define GP_IER_RIER3_Pos (19) |
GPIO_T::IER: RIER3 Position
Definition at line 4484 of file Nano100Series.h.
| #define GP_IER_RIER4_Msk (0x1ul << GP_IER_RIER4_Pos) |
GPIO_T::IER: RIER4 Mask
Definition at line 4488 of file Nano100Series.h.
| #define GP_IER_RIER4_Pos (20) |
GPIO_T::IER: RIER4 Position
Definition at line 4487 of file Nano100Series.h.
| #define GP_IER_RIER5_Msk (0x1ul << GP_IER_RIER5_Pos) |
GPIO_T::IER: RIER5 Mask
Definition at line 4491 of file Nano100Series.h.
| #define GP_IER_RIER5_Pos (21) |
GPIO_T::IER: RIER5 Position
Definition at line 4490 of file Nano100Series.h.
| #define GP_IER_RIER6_Msk (0x1ul << GP_IER_RIER6_Pos) |
GPIO_T::IER: RIER6 Mask
Definition at line 4494 of file Nano100Series.h.
| #define GP_IER_RIER6_Pos (22) |
GPIO_T::IER: RIER6 Position
Definition at line 4493 of file Nano100Series.h.
| #define GP_IER_RIER7_Msk (0x1ul << GP_IER_RIER7_Pos) |
GPIO_T::IER: RIER7 Mask
Definition at line 4497 of file Nano100Series.h.
| #define GP_IER_RIER7_Pos (23) |
GPIO_T::IER: RIER7 Position
Definition at line 4496 of file Nano100Series.h.
| #define GP_IER_RIER8_Msk (0x1ul << GP_IER_RIER8_Pos) |
GPIO_T::IER: RIER8 Mask
Definition at line 4500 of file Nano100Series.h.
| #define GP_IER_RIER8_Pos (24) |
GPIO_T::IER: RIER8 Position
Definition at line 4499 of file Nano100Series.h.
| #define GP_IER_RIER9_Msk (0x1ul << GP_IER_RIER9_Pos) |
GPIO_T::IER: RIER9 Mask
Definition at line 4503 of file Nano100Series.h.
| #define GP_IER_RIER9_Pos (25) |
GPIO_T::IER: RIER9 Position
Definition at line 4502 of file Nano100Series.h.
| #define GP_IMD_IMD_Msk (0xfffful << GP_IMD_IMD_Pos) |
GPIO_T::IMD: IMD Mask
Definition at line 4425 of file Nano100Series.h.
| #define GP_IMD_IMD_Pos (0) |
GPIO_T::IMD: IMD Position
Definition at line 4424 of file Nano100Series.h.
| #define GP_ISRC_ISRC_Msk (0xfffful << GP_ISRC_ISRC_Pos) |
GPIO_T::ISRC: ISRC Mask
Definition at line 4524 of file Nano100Series.h.
| #define GP_ISRC_ISRC_Pos (0) |
GPIO_T::ISRC: ISRC Position
Definition at line 4523 of file Nano100Series.h.
| #define GP_OFFD_OFFD_Msk (0xfffful << GP_OFFD_OFFD_Pos) |
GPIO_T::OFFD: OFFD Mask
Definition at line 4410 of file Nano100Series.h.
| #define GP_OFFD_OFFD_Pos (16) |
GPIO_T::OFFD: OFFD Position
Definition at line 4409 of file Nano100Series.h.
| #define GP_PIN_PIN_Msk (0xfffful << GP_PIN_PIN_Pos) |
GPIO_T::PIN: PIN Mask
Definition at line 4419 of file Nano100Series.h.
| #define GP_PIN_PIN_Pos (0) |
GPIO_T::PIN: PIN Position
Definition at line 4418 of file Nano100Series.h.
| #define GP_PMD_PMD0_Msk (0x3ul << GP_PMD_PMD0_Pos) |
GPIO_T::PMD: PMD0 Mask
Definition at line 4362 of file Nano100Series.h.
| #define GP_PMD_PMD0_Pos (0) |
@addtogroup GPIO_CONST GPIO Bit Field Definition Constant Definitions for GPIO Controller
GPIO_T::PMD: PMD0 Position
Definition at line 4361 of file Nano100Series.h.
| #define GP_PMD_PMD10_Msk (0x3ul << GP_PMD_PMD10_Pos) |
GPIO_T::PMD: PMD10 Mask
Definition at line 4392 of file Nano100Series.h.
| #define GP_PMD_PMD10_Pos (20) |
GPIO_T::PMD: PMD10 Position
Definition at line 4391 of file Nano100Series.h.
| #define GP_PMD_PMD11_Msk (0x3ul << GP_PMD_PMD11_Pos) |
GPIO_T::PMD: PMD11 Mask
Definition at line 4395 of file Nano100Series.h.
| #define GP_PMD_PMD11_Pos (22) |
GPIO_T::PMD: PMD11 Position
Definition at line 4394 of file Nano100Series.h.
| #define GP_PMD_PMD12_Msk (0x3ul << GP_PMD_PMD12_Pos) |
GPIO_T::PMD: PMD12 Mask
Definition at line 4398 of file Nano100Series.h.
| #define GP_PMD_PMD12_Pos (24) |
GPIO_T::PMD: PMD12 Position
Definition at line 4397 of file Nano100Series.h.
| #define GP_PMD_PMD13_Msk (0x3ul << GP_PMD_PMD13_Pos) |
GPIO_T::PMD: PMD13 Mask
Definition at line 4401 of file Nano100Series.h.
| #define GP_PMD_PMD13_Pos (26) |
GPIO_T::PMD: PMD13 Position
Definition at line 4400 of file Nano100Series.h.
| #define GP_PMD_PMD14_Msk (0x3ul << GP_PMD_PMD14_Pos) |
GPIO_T::PMD: PMD14 Mask
Definition at line 4404 of file Nano100Series.h.
| #define GP_PMD_PMD14_Pos (28) |
GPIO_T::PMD: PMD14 Position
Definition at line 4403 of file Nano100Series.h.
| #define GP_PMD_PMD15_Msk (0x3ul << GP_PMD_PMD15_Pos) |
GPIO_T::PMD: PMD15 Mask
Definition at line 4407 of file Nano100Series.h.
| #define GP_PMD_PMD15_Pos (30) |
GPIO_T::PMD: PMD15 Position
Definition at line 4406 of file Nano100Series.h.
| #define GP_PMD_PMD1_Msk (0x3ul << GP_PMD_PMD1_Pos) |
GPIO_T::PMD: PMD1 Mask
Definition at line 4365 of file Nano100Series.h.
| #define GP_PMD_PMD1_Pos (2) |
GPIO_T::PMD: PMD1 Position
Definition at line 4364 of file Nano100Series.h.
| #define GP_PMD_PMD2_Msk (0x3ul << GP_PMD_PMD2_Pos) |
GPIO_T::PMD: PMD2 Mask
Definition at line 4368 of file Nano100Series.h.
| #define GP_PMD_PMD2_Pos (4) |
GPIO_T::PMD: PMD2 Position
Definition at line 4367 of file Nano100Series.h.
| #define GP_PMD_PMD3_Msk (0x3ul << GP_PMD_PMD3_Pos) |
GPIO_T::PMD: PMD3 Mask
Definition at line 4371 of file Nano100Series.h.
| #define GP_PMD_PMD3_Pos (6) |
GPIO_T::PMD: PMD3 Position
Definition at line 4370 of file Nano100Series.h.
| #define GP_PMD_PMD4_Msk (0x3ul << GP_PMD_PMD4_Pos) |
GPIO_T::PMD: PMD4 Mask
Definition at line 4374 of file Nano100Series.h.
| #define GP_PMD_PMD4_Pos (8) |
GPIO_T::PMD: PMD4 Position
Definition at line 4373 of file Nano100Series.h.
| #define GP_PMD_PMD5_Msk (0x3ul << GP_PMD_PMD5_Pos) |
GPIO_T::PMD: PMD5 Mask
Definition at line 4377 of file Nano100Series.h.
| #define GP_PMD_PMD5_Pos (10) |
GPIO_T::PMD: PMD5 Position
Definition at line 4376 of file Nano100Series.h.
| #define GP_PMD_PMD6_Msk (0x3ul << GP_PMD_PMD6_Pos) |
GPIO_T::PMD: PMD6 Mask
Definition at line 4380 of file Nano100Series.h.
| #define GP_PMD_PMD6_Pos (12) |
GPIO_T::PMD: PMD6 Position
Definition at line 4379 of file Nano100Series.h.
| #define GP_PMD_PMD7_Msk (0x3ul << GP_PMD_PMD7_Pos) |
GPIO_T::PMD: PMD7 Mask
Definition at line 4383 of file Nano100Series.h.
| #define GP_PMD_PMD7_Pos (14) |
GPIO_T::PMD: PMD7 Position
Definition at line 4382 of file Nano100Series.h.
| #define GP_PMD_PMD8_Msk (0x3ul << GP_PMD_PMD8_Pos) |
GPIO_T::PMD: PMD8 Mask
Definition at line 4386 of file Nano100Series.h.
| #define GP_PMD_PMD8_Pos (16) |
GPIO_T::PMD: PMD8 Position
Definition at line 4385 of file Nano100Series.h.
| #define GP_PMD_PMD9_Msk (0x3ul << GP_PMD_PMD9_Pos) |
GPIO_T::PMD: PMD9 Mask
Definition at line 4389 of file Nano100Series.h.
| #define GP_PMD_PMD9_Pos (18) |
GPIO_T::PMD: PMD9 Position
Definition at line 4388 of file Nano100Series.h.
| #define GP_PUEN_PUEN_Msk (0xfffful << GP_PUEN_PUEN_Pos) |
GPIO_T::PUEN: PUEN Mask
Definition at line 4527 of file Nano100Series.h.
| #define GP_PUEN_PUEN_Pos (0) |
GPIO_T::PUEN: PUEN Position
Definition at line 4526 of file Nano100Series.h.
| #define I2C_CON_ACK_Msk (0x1ul << I2C_CON_ACK_Pos) |
I2C_T::CON: ACK Mask
Definition at line 4775 of file Nano100Series.h.
| #define I2C_CON_ACK_Pos (1) |
I2C_T::CON: ACK Position
Definition at line 4774 of file Nano100Series.h.
| #define I2C_CON_I2C_STS_Msk (0x1ul << I2C_CON_I2C_STS_Pos) |
I2C_T::CON: I2C_STS Mask
Definition at line 4784 of file Nano100Series.h.
| #define I2C_CON_I2C_STS_Pos (4) |
I2C_T::CON: I2C_STS Position
Definition at line 4783 of file Nano100Series.h.
| #define I2C_CON_INTEN_Msk (0x1ul << I2C_CON_INTEN_Pos) |
I2C_T::CON: INTEN Mask
Definition at line 4787 of file Nano100Series.h.
| #define I2C_CON_INTEN_Pos (7) |
I2C_T::CON: INTEN Position
Definition at line 4786 of file Nano100Series.h.
| #define I2C_CON_IPEN_Msk (0x1ul << I2C_CON_IPEN_Pos) |
I2C_T::CON: IPEN Mask
Definition at line 4772 of file Nano100Series.h.
| #define I2C_CON_IPEN_Pos (0) |
@addtogroup I2C_CONST I2C Bit Field Definition Constant Definitions for I2C Controller
I2C_T::CON: IPEN Position
Definition at line 4771 of file Nano100Series.h.
| #define I2C_CON_START_Msk (0x1ul << I2C_CON_START_Pos) |
I2C_T::CON: START Mask
Definition at line 4781 of file Nano100Series.h.
| #define I2C_CON_START_Pos (3) |
I2C_T::CON: START Position
Definition at line 4780 of file Nano100Series.h.
| #define I2C_CON_STOP_Msk (0x1ul << I2C_CON_STOP_Pos) |
I2C_T::CON: STOP Mask
Definition at line 4778 of file Nano100Series.h.
| #define I2C_CON_STOP_Pos (2) |
I2C_T::CON: STOP Position
Definition at line 4777 of file Nano100Series.h.
| #define I2C_DATA_DATA_Msk (0xfful << I2C_DATA_DATA_Pos) |
I2C_T::DATA: DATA Mask
Definition at line 4808 of file Nano100Series.h.
| #define I2C_DATA_DATA_Pos (0) |
I2C_T::DATA: DATA Position
Definition at line 4807 of file Nano100Series.h.
| #define I2C_DIV_CLK_DIV_Msk (0xfful << I2C_DIV_CLK_DIV_Pos) |
I2C_T::DIV: CLK_DIV Mask
Definition at line 4799 of file Nano100Series.h.
| #define I2C_DIV_CLK_DIV_Pos (0) |
I2C_T::DIV: CLK_DIV Position
Definition at line 4798 of file Nano100Series.h.
| #define I2C_INTSTS_INTSTS_Msk (0x1ul << I2C_INTSTS_INTSTS_Pos) |
I2C_T::INTSTS: INTSTS Mask
Definition at line 4790 of file Nano100Series.h.
| #define I2C_INTSTS_INTSTS_Pos (0) |
I2C_T::INTSTS: INTSTS Position
Definition at line 4789 of file Nano100Series.h.
| #define I2C_INTSTS_TIF_Msk (0x1ul << I2C_INTSTS_TIF_Pos) |
I2C_T::INTSTS: TIF Mask
Definition at line 4793 of file Nano100Series.h.
| #define I2C_INTSTS_TIF_Pos (1) |
I2C_T::INTSTS: TIF Position
Definition at line 4792 of file Nano100Series.h.
| #define I2C_SADDR0_GCALL_Msk (0x1ul << I2C_SADDR0_GCALL_Pos) |
I2C_T::SADDR0: GCALL Mask
Definition at line 4811 of file Nano100Series.h.
| #define I2C_SADDR0_GCALL_Pos (0) |
I2C_T::SADDR0: GCALL Position
Definition at line 4810 of file Nano100Series.h.
| #define I2C_SADDR0_SADDR_Msk (0x7ful << I2C_SADDR0_SADDR_Pos) |
I2C_T::SADDR0: SADDR Mask
Definition at line 4814 of file Nano100Series.h.
| #define I2C_SADDR0_SADDR_Pos (1) |
I2C_T::SADDR0: SADDR Position
Definition at line 4813 of file Nano100Series.h.
| #define I2C_SADDR1_GCALL_Msk (0x1ul << I2C_SADDR1_GCALL_Pos) |
I2C_T::SADDR1: GCALL Mask
Definition at line 4817 of file Nano100Series.h.
| #define I2C_SADDR1_GCALL_Pos (0) |
I2C_T::SADDR1: GCALL Position
Definition at line 4816 of file Nano100Series.h.
| #define I2C_SADDR1_SADDR_Msk (0x7ful << I2C_SADDR1_SADDR_Pos) |
I2C_T::SADDR1: SADDR Mask
Definition at line 4820 of file Nano100Series.h.
| #define I2C_SADDR1_SADDR_Pos (1) |
I2C_T::SADDR1: SADDR Position
Definition at line 4819 of file Nano100Series.h.
| #define I2C_SAMASK0_SAMASK_Msk (0x7ful << I2C_SAMASK0_SAMASK_Pos) |
I2C_T::SAMASK0: SAMASK Mask
Definition at line 4823 of file Nano100Series.h.
| #define I2C_SAMASK0_SAMASK_Pos (1) |
I2C_T::SAMASK0: SAMASK Position
Definition at line 4822 of file Nano100Series.h.
| #define I2C_SAMASK1_SAMASK_Msk (0x7ful << I2C_SAMASK1_SAMASK_Pos) |
I2C_T::SAMASK1: SAMASK Mask
Definition at line 4826 of file Nano100Series.h.
| #define I2C_SAMASK1_SAMASK_Pos (1) |
I2C_T::SAMASK1: SAMASK Position
Definition at line 4825 of file Nano100Series.h.
| #define I2C_STATUS_STATUS_Msk (0xfful << I2C_STATUS_STATUS_Pos) |
I2C_T::STATUS: STATUS Mask
Definition at line 4796 of file Nano100Series.h.
| #define I2C_STATUS_STATUS_Pos (0) |
I2C_T::STATUS: STATUS Position
Definition at line 4795 of file Nano100Series.h.
| #define I2C_TOUT_DIV4_Msk (0x1ul << I2C_TOUT_DIV4_Pos) |
I2C_T::TOUT: DIV4 Mask
Definition at line 4805 of file Nano100Series.h.
| #define I2C_TOUT_DIV4_Pos (1) |
I2C_T::TOUT: DIV4 Position
Definition at line 4804 of file Nano100Series.h.
| #define I2C_TOUT_TOUTEN_Msk (0x1ul << I2C_TOUT_TOUTEN_Pos) |
I2C_T::TOUT: TOUTEN Mask
Definition at line 4802 of file Nano100Series.h.
| #define I2C_TOUT_TOUTEN_Pos (0) |
I2C_T::TOUT: TOUTEN Position
Definition at line 4801 of file Nano100Series.h.
| #define I2S_CLKDIV_BCLK_DIV_Msk (0xfful << I2S_CLKDIV_BCLK_DIV_Pos) |
I2S_T::CLKDIV: BCLK_DIV Mask
Definition at line 5184 of file Nano100Series.h.
| #define I2S_CLKDIV_BCLK_DIV_Pos (8) |
I2S_T::CLKDIV: BCLK_DIV Position
Definition at line 5183 of file Nano100Series.h.
| #define I2S_CLKDIV_MCLK_DIV_Msk (0x7ul << I2S_CLKDIV_MCLK_DIV_Pos) |
I2S_T::CLKDIV: MCLK_DIV Mask
Definition at line 5181 of file Nano100Series.h.
| #define I2S_CLKDIV_MCLK_DIV_Pos (0) |
I2S_T::CLKDIV: MCLK_DIV Position
Definition at line 5180 of file Nano100Series.h.
| #define I2S_CTRL_CLR_RXFIFO_Msk (0x1ul << I2S_CTRL_CLR_RXFIFO_Pos) |
I2S_T::CTRL: CLR_RXFIFO Mask
Definition at line 5172 of file Nano100Series.h.
| #define I2S_CTRL_CLR_RXFIFO_Pos (19) |
I2S_T::CTRL: CLR_RXFIFO Position
Definition at line 5171 of file Nano100Series.h.
| #define I2S_CTRL_CLR_TXFIFO_Msk (0x1ul << I2S_CTRL_CLR_TXFIFO_Pos) |
I2S_T::CTRL: CLR_TXFIFO Mask
Definition at line 5169 of file Nano100Series.h.
| #define I2S_CTRL_CLR_TXFIFO_Pos (18) |
I2S_T::CTRL: CLR_TXFIFO Position
Definition at line 5168 of file Nano100Series.h.
| #define I2S_CTRL_FORMAT_Msk (0x1ul << I2S_CTRL_FORMAT_Pos) |
I2S_T::CTRL: FORMAT Mask
Definition at line 5148 of file Nano100Series.h.
| #define I2S_CTRL_FORMAT_Pos (7) |
I2S_T::CTRL: FORMAT Position
Definition at line 5147 of file Nano100Series.h.
| #define I2S_CTRL_I2SEN_Msk (0x1ul << I2S_CTRL_I2SEN_Pos) |
I2S_T::CTRL: I2SEN Mask
Definition at line 5130 of file Nano100Series.h.
| #define I2S_CTRL_I2SEN_Pos (0) |
@addtogroup I2S_CONST I2S Bit Field Definition Constant Definitions for I2S Controller
I2S_T::CTRL: I2SEN Position
Definition at line 5129 of file Nano100Series.h.
| #define I2S_CTRL_LCHZCEN_Msk (0x1ul << I2S_CTRL_LCHZCEN_Pos) |
I2S_T::CTRL: LCHZCEN Mask
Definition at line 5166 of file Nano100Series.h.
| #define I2S_CTRL_LCHZCEN_Pos (17) |
I2S_T::CTRL: LCHZCEN Position
Definition at line 5165 of file Nano100Series.h.
| #define I2S_CTRL_MCLKEN_Msk (0x1ul << I2S_CTRL_MCLKEN_Pos) |
I2S_T::CTRL: MCLKEN Mask
Definition at line 5160 of file Nano100Series.h.
| #define I2S_CTRL_MCLKEN_Pos (15) |
I2S_T::CTRL: MCLKEN Position
Definition at line 5159 of file Nano100Series.h.
| #define I2S_CTRL_MONO_Msk (0x1ul << I2S_CTRL_MONO_Pos) |
I2S_T::CTRL: MONO Mask
Definition at line 5145 of file Nano100Series.h.
| #define I2S_CTRL_MONO_Pos (6) |
I2S_T::CTRL: MONO Position
Definition at line 5144 of file Nano100Series.h.
| #define I2S_CTRL_MUTE_Msk (0x1ul << I2S_CTRL_MUTE_Pos) |
I2S_T::CTRL: MUTE Mask
Definition at line 5139 of file Nano100Series.h.
| #define I2S_CTRL_MUTE_Pos (3) |
I2S_T::CTRL: MUTE Position
Definition at line 5138 of file Nano100Series.h.
| #define I2S_CTRL_RCHZCEN_Msk (0x1ul << I2S_CTRL_RCHZCEN_Pos) |
I2S_T::CTRL: RCHZCEN Mask
Definition at line 5163 of file Nano100Series.h.
| #define I2S_CTRL_RCHZCEN_Pos (16) |
I2S_T::CTRL: RCHZCEN Position
Definition at line 5162 of file Nano100Series.h.
| #define I2S_CTRL_RXDMA_Msk (0x1ul << I2S_CTRL_RXDMA_Pos) |
I2S_T::CTRL: RXDMA Mask
Definition at line 5178 of file Nano100Series.h.
| #define I2S_CTRL_RXDMA_Pos (21) |
I2S_T::CTRL: RXDMA Position
Definition at line 5177 of file Nano100Series.h.
| #define I2S_CTRL_RXEN_Msk (0x1ul << I2S_CTRL_RXEN_Pos) |
I2S_T::CTRL: RXEN Mask
Definition at line 5136 of file Nano100Series.h.
| #define I2S_CTRL_RXEN_Pos (2) |
I2S_T::CTRL: RXEN Position
Definition at line 5135 of file Nano100Series.h.
| #define I2S_CTRL_RXTH_Msk (0x7ul << I2S_CTRL_RXTH_Pos) |
I2S_T::CTRL: RXTH Mask
Definition at line 5157 of file Nano100Series.h.
| #define I2S_CTRL_RXTH_Pos (12) |
I2S_T::CTRL: RXTH Position
Definition at line 5156 of file Nano100Series.h.
| #define I2S_CTRL_SLAVE_Msk (0x1ul << I2S_CTRL_SLAVE_Pos) |
I2S_T::CTRL: SLAVE Mask
Definition at line 5151 of file Nano100Series.h.
| #define I2S_CTRL_SLAVE_Pos (8) |
I2S_T::CTRL: SLAVE Position
Definition at line 5150 of file Nano100Series.h.
| #define I2S_CTRL_TXDMA_Msk (0x1ul << I2S_CTRL_TXDMA_Pos) |
I2S_T::CTRL: TXDMA Mask
Definition at line 5175 of file Nano100Series.h.
| #define I2S_CTRL_TXDMA_Pos (20) |
I2S_T::CTRL: TXDMA Position
Definition at line 5174 of file Nano100Series.h.
| #define I2S_CTRL_TXEN_Msk (0x1ul << I2S_CTRL_TXEN_Pos) |
I2S_T::CTRL: TXEN Mask
Definition at line 5133 of file Nano100Series.h.
| #define I2S_CTRL_TXEN_Pos (1) |
I2S_T::CTRL: TXEN Position
Definition at line 5132 of file Nano100Series.h.
| #define I2S_CTRL_TXTH_Msk (0x7ul << I2S_CTRL_TXTH_Pos) |
I2S_T::CTRL: TXTH Mask
Definition at line 5154 of file Nano100Series.h.
| #define I2S_CTRL_TXTH_Pos (9) |
I2S_T::CTRL: TXTH Position
Definition at line 5153 of file Nano100Series.h.
| #define I2S_CTRL_WORDWIDTH_Msk (0x3ul << I2S_CTRL_WORDWIDTH_Pos) |
I2S_T::CTRL: WORDWIDTH Mask
Definition at line 5142 of file Nano100Series.h.
| #define I2S_CTRL_WORDWIDTH_Pos (4) |
I2S_T::CTRL: WORDWIDTH Position
Definition at line 5141 of file Nano100Series.h.
| #define I2S_INTEN_LZCIE_Msk (0x1ul << I2S_INTEN_LZCIE_Pos) |
I2S_T::INTEN: LZCIE Mask
Definition at line 5208 of file Nano100Series.h.
| #define I2S_INTEN_LZCIE_Pos (12) |
I2S_T::INTEN: LZCIE Position
Definition at line 5207 of file Nano100Series.h.
| #define I2S_INTEN_RXOVFIE_Msk (0x1ul << I2S_INTEN_RXOVFIE_Pos) |
I2S_T::INTEN: RXOVFIE Mask
Definition at line 5190 of file Nano100Series.h.
| #define I2S_INTEN_RXOVFIE_Pos (1) |
I2S_T::INTEN: RXOVFIE Position
Definition at line 5189 of file Nano100Series.h.
| #define I2S_INTEN_RXTHIE_Msk (0x1ul << I2S_INTEN_RXTHIE_Pos) |
I2S_T::INTEN: RXTHIE Mask
Definition at line 5193 of file Nano100Series.h.
| #define I2S_INTEN_RXTHIE_Pos (2) |
I2S_T::INTEN: RXTHIE Position
Definition at line 5192 of file Nano100Series.h.
| #define I2S_INTEN_RXUDFIE_Msk (0x1ul << I2S_INTEN_RXUDFIE_Pos) |
I2S_T::INTEN: RXUDFIE Mask
Definition at line 5187 of file Nano100Series.h.
| #define I2S_INTEN_RXUDFIE_Pos (0) |
I2S_T::INTEN: RXUDFIE Position
Definition at line 5186 of file Nano100Series.h.
| #define I2S_INTEN_RZCIE_Msk (0x1ul << I2S_INTEN_RZCIE_Pos) |
I2S_T::INTEN: RZCIE Mask
Definition at line 5205 of file Nano100Series.h.
| #define I2S_INTEN_RZCIE_Pos (11) |
I2S_T::INTEN: RZCIE Position
Definition at line 5204 of file Nano100Series.h.
| #define I2S_INTEN_TXOVFIE_Msk (0x1ul << I2S_INTEN_TXOVFIE_Pos) |
I2S_T::INTEN: TXOVFIE Mask
Definition at line 5199 of file Nano100Series.h.
| #define I2S_INTEN_TXOVFIE_Pos (9) |
I2S_T::INTEN: TXOVFIE Position
Definition at line 5198 of file Nano100Series.h.
| #define I2S_INTEN_TXTHIE_Msk (0x1ul << I2S_INTEN_TXTHIE_Pos) |
I2S_T::INTEN: TXTHIE Mask
Definition at line 5202 of file Nano100Series.h.
| #define I2S_INTEN_TXTHIE_Pos (10) |
I2S_T::INTEN: TXTHIE Position
Definition at line 5201 of file Nano100Series.h.
| #define I2S_INTEN_TXUDFIE_Msk (0x1ul << I2S_INTEN_TXUDFIE_Pos) |
I2S_T::INTEN: TXUDFIE Mask
Definition at line 5196 of file Nano100Series.h.
| #define I2S_INTEN_TXUDFIE_Pos (8) |
I2S_T::INTEN: TXUDFIE Position
Definition at line 5195 of file Nano100Series.h.
| #define I2S_RXFIFO_RXFIFO_Msk (0xfffffffful << I2S_RXFIFO_RXFIFO_Pos) |
I2S_T::RXFIFO: RXFIFO Mask
Definition at line 5271 of file Nano100Series.h.
| #define I2S_RXFIFO_RXFIFO_Pos (0) |
I2S_T::RXFIFO: RXFIFO Position
Definition at line 5270 of file Nano100Series.h.
| #define I2S_STATUS_I2SINT_Msk (0x1ul << I2S_STATUS_I2SINT_Pos) |
I2S_T::STATUS: I2SINT Mask
Definition at line 5211 of file Nano100Series.h.
| #define I2S_STATUS_I2SINT_Pos (0) |
I2S_T::STATUS: I2SINT Position
Definition at line 5210 of file Nano100Series.h.
| #define I2S_STATUS_I2SRXINT_Msk (0x1ul << I2S_STATUS_I2SRXINT_Pos) |
I2S_T::STATUS: I2SRXINT Mask
Definition at line 5214 of file Nano100Series.h.
| #define I2S_STATUS_I2SRXINT_Pos (1) |
I2S_T::STATUS: I2SRXINT Position
Definition at line 5213 of file Nano100Series.h.
| #define I2S_STATUS_I2STXINT_Msk (0x1ul << I2S_STATUS_I2STXINT_Pos) |
I2S_T::STATUS: I2STXINT Mask
Definition at line 5217 of file Nano100Series.h.
| #define I2S_STATUS_I2STXINT_Pos (2) |
I2S_T::STATUS: I2STXINT Position
Definition at line 5216 of file Nano100Series.h.
| #define I2S_STATUS_LZCF_Msk (0x1ul << I2S_STATUS_LZCF_Pos) |
I2S_T::STATUS: LZCF Mask
Definition at line 5259 of file Nano100Series.h.
| #define I2S_STATUS_LZCF_Pos (23) |
I2S_T::STATUS: LZCF Position
Definition at line 5258 of file Nano100Series.h.
| #define I2S_STATUS_RIGHT_Msk (0x1ul << I2S_STATUS_RIGHT_Pos) |
I2S_T::STATUS: RIGHT Mask
Definition at line 5220 of file Nano100Series.h.
| #define I2S_STATUS_RIGHT_Pos (3) |
I2S_T::STATUS: RIGHT Position
Definition at line 5219 of file Nano100Series.h.
| #define I2S_STATUS_RX_LEVEL_Msk (0xful << I2S_STATUS_RX_LEVEL_Pos) |
I2S_T::STATUS: RX_LEVEL Mask
Definition at line 5262 of file Nano100Series.h.
| #define I2S_STATUS_RX_LEVEL_Pos (24) |
I2S_T::STATUS: RX_LEVEL Position
Definition at line 5261 of file Nano100Series.h.
| #define I2S_STATUS_RXEMPTY_Msk (0x1ul << I2S_STATUS_RXEMPTY_Pos) |
I2S_T::STATUS: RXEMPTY Mask
Definition at line 5235 of file Nano100Series.h.
| #define I2S_STATUS_RXEMPTY_Pos (12) |
I2S_T::STATUS: RXEMPTY Position
Definition at line 5234 of file Nano100Series.h.
| #define I2S_STATUS_RXFULL_Msk (0x1ul << I2S_STATUS_RXFULL_Pos) |
I2S_T::STATUS: RXFULL Mask
Definition at line 5232 of file Nano100Series.h.
| #define I2S_STATUS_RXFULL_Pos (11) |
I2S_T::STATUS: RXFULL Position
Definition at line 5231 of file Nano100Series.h.
| #define I2S_STATUS_RXOVF_Msk (0x1ul << I2S_STATUS_RXOVF_Pos) |
I2S_T::STATUS: RXOVF Mask
Definition at line 5226 of file Nano100Series.h.
| #define I2S_STATUS_RXOVF_Pos (9) |
I2S_T::STATUS: RXOVF Position
Definition at line 5225 of file Nano100Series.h.
| #define I2S_STATUS_RXTHF_Msk (0x1ul << I2S_STATUS_RXTHF_Pos) |
I2S_T::STATUS: RXTHF Mask
Definition at line 5229 of file Nano100Series.h.
| #define I2S_STATUS_RXTHF_Pos (10) |
I2S_T::STATUS: RXTHF Position
Definition at line 5228 of file Nano100Series.h.
| #define I2S_STATUS_RXUDF_Msk (0x1ul << I2S_STATUS_RXUDF_Pos) |
I2S_T::STATUS: RXUDF Mask
Definition at line 5223 of file Nano100Series.h.
| #define I2S_STATUS_RXUDF_Pos (8) |
I2S_T::STATUS: RXUDF Position
Definition at line 5222 of file Nano100Series.h.
| #define I2S_STATUS_RZCF_Msk (0x1ul << I2S_STATUS_RZCF_Pos) |
I2S_T::STATUS: RZCF Mask
Definition at line 5256 of file Nano100Series.h.
| #define I2S_STATUS_RZCF_Pos (22) |
I2S_T::STATUS: RZCF Position
Definition at line 5255 of file Nano100Series.h.
| #define I2S_STATUS_TX_LEVEL_Msk (0xful << I2S_STATUS_TX_LEVEL_Pos) |
I2S_T::STATUS: TX_LEVEL Mask
Definition at line 5265 of file Nano100Series.h.
| #define I2S_STATUS_TX_LEVEL_Pos (28) |
I2S_T::STATUS: TX_LEVEL Position
Definition at line 5264 of file Nano100Series.h.
| #define I2S_STATUS_TXBUSY_Msk (0x1ul << I2S_STATUS_TXBUSY_Pos) |
I2S_T::STATUS: TXBUSY Mask
Definition at line 5253 of file Nano100Series.h.
| #define I2S_STATUS_TXBUSY_Pos (21) |
I2S_T::STATUS: TXBUSY Position
Definition at line 5252 of file Nano100Series.h.
| #define I2S_STATUS_TXEMPTY_Msk (0x1ul << I2S_STATUS_TXEMPTY_Pos) |
I2S_T::STATUS: TXEMPTY Mask
Definition at line 5250 of file Nano100Series.h.
| #define I2S_STATUS_TXEMPTY_Pos (20) |
I2S_T::STATUS: TXEMPTY Position
Definition at line 5249 of file Nano100Series.h.
| #define I2S_STATUS_TXFULL_Msk (0x1ul << I2S_STATUS_TXFULL_Pos) |
I2S_T::STATUS: TXFULL Mask
Definition at line 5247 of file Nano100Series.h.
| #define I2S_STATUS_TXFULL_Pos (19) |
I2S_T::STATUS: TXFULL Position
Definition at line 5246 of file Nano100Series.h.
| #define I2S_STATUS_TXOVF_Msk (0x1ul << I2S_STATUS_TXOVF_Pos) |
I2S_T::STATUS: TXOVF Mask
Definition at line 5241 of file Nano100Series.h.
| #define I2S_STATUS_TXOVF_Pos (17) |
I2S_T::STATUS: TXOVF Position
Definition at line 5240 of file Nano100Series.h.
| #define I2S_STATUS_TXTHF_Msk (0x1ul << I2S_STATUS_TXTHF_Pos) |
I2S_T::STATUS: TXTHF Mask
Definition at line 5244 of file Nano100Series.h.
| #define I2S_STATUS_TXTHF_Pos (18) |
I2S_T::STATUS: TXTHF Position
Definition at line 5243 of file Nano100Series.h.
| #define I2S_STATUS_TXUDF_Msk (0x1ul << I2S_STATUS_TXUDF_Pos) |
I2S_T::STATUS: TXUDF Mask
Definition at line 5238 of file Nano100Series.h.
| #define I2S_STATUS_TXUDF_Pos (16) |
I2S_T::STATUS: TXUDF Position
Definition at line 5237 of file Nano100Series.h.
| #define I2S_TXFIFO_TXFIFO_Msk (0xfffffffful << I2S_TXFIFO_TXFIFO_Pos) |
I2S_T::TXFIFO: TXFIFO Mask
Definition at line 5268 of file Nano100Series.h.
| #define I2S_TXFIFO_TXFIFO_Pos (0) |
I2S_T::TXFIFO: TXFIFO Position
Definition at line 5267 of file Nano100Series.h.
| #define PDMA_BCR_PDMA_BCR_Msk (0xfffful << PDMA_BCR_PDMA_BCR_Pos) |
PDMA_T::BCR: PDMA_BCR Mask
Definition at line 1915 of file Nano100Series.h.
| #define PDMA_BCR_PDMA_BCR_Pos (0) |
PDMA_T::BCR: PDMA_BCR Position
Definition at line 1914 of file Nano100Series.h.
| #define PDMA_BUF_PDMA_BUF_Msk (0xfffffffful << PDMA_BUF_PDMA_BUF_Pos) |
PDMA_T::BUF: PDMA_BUF Mask
Definition at line 1954 of file Nano100Series.h.
| #define PDMA_BUF_PDMA_BUF_Pos (0) |
PDMA_T::BUF: PDMA_BUF Position
Definition at line 1953 of file Nano100Series.h.
| #define PDMA_CBCR_PDMA_CBCR_Msk (0xfffffful << PDMA_CBCR_PDMA_CBCR_Pos) |
PDMA_T::CBCR: PDMA_CBCR Mask
Definition at line 1924 of file Nano100Series.h.
| #define PDMA_CBCR_PDMA_CBCR_Pos (0) |
PDMA_T::CBCR: PDMA_CBCR Position
Definition at line 1923 of file Nano100Series.h.
| #define PDMA_CDAR_PDMA_CDAR_Msk (0xfffffffful << PDMA_CDAR_PDMA_CDAR_Pos) |
PDMA_T::CDAR: PDMA_CDAR Mask
Definition at line 1921 of file Nano100Series.h.
| #define PDMA_CDAR_PDMA_CDAR_Pos (0) |
PDMA_T::CDAR: PDMA_CDAR Position
Definition at line 1920 of file Nano100Series.h.
| #define PDMA_CSAR_PDMA_CSAR_Msk (0xfffffffful << PDMA_CSAR_PDMA_CSAR_Pos) |
PDMA_T::CSAR: PDMA_CSAR Mask
Definition at line 1918 of file Nano100Series.h.
| #define PDMA_CSAR_PDMA_CSAR_Pos (0) |
PDMA_T::CSAR: PDMA_CSAR Position
Definition at line 1917 of file Nano100Series.h.
| #define PDMA_CSR_APB_TWS_Msk (0x3ul << PDMA_CSR_APB_TWS_Pos) |
PDMA_T::CSR: APB_TWS Mask
Definition at line 1903 of file Nano100Series.h.
| #define PDMA_CSR_APB_TWS_Pos (19) |
PDMA_T::CSR: APB_TWS Position
Definition at line 1902 of file Nano100Series.h.
| #define PDMA_CSR_DAD_SEL_Msk (0x3ul << PDMA_CSR_DAD_SEL_Pos) |
PDMA_T::CSR: DAD_SEL Mask
Definition at line 1897 of file Nano100Series.h.
| #define PDMA_CSR_DAD_SEL_Pos (6) |
PDMA_T::CSR: DAD_SEL Position
Definition at line 1896 of file Nano100Series.h.
| #define PDMA_CSR_MODE_SEL_Msk (0x3ul << PDMA_CSR_MODE_SEL_Pos) |
PDMA_T::CSR: MODE_SEL Mask
Definition at line 1891 of file Nano100Series.h.
| #define PDMA_CSR_MODE_SEL_Pos (2) |
PDMA_T::CSR: MODE_SEL Position
Definition at line 1890 of file Nano100Series.h.
| #define PDMA_CSR_PDMACEN_Msk (0x1ul << PDMA_CSR_PDMACEN_Pos) |
PDMA_T::CSR: PDMACEN Mask
Definition at line 1885 of file Nano100Series.h.
| #define PDMA_CSR_PDMACEN_Pos (0) |
@addtogroup PDMA_CONST PDMA Bit Field Definition Constant Definitions for PDMA Controller
PDMA_T::CSR: PDMACEN Position
Definition at line 1884 of file Nano100Series.h.
| #define PDMA_CSR_SAD_SEL_Msk (0x3ul << PDMA_CSR_SAD_SEL_Pos) |
PDMA_T::CSR: SAD_SEL Mask
Definition at line 1894 of file Nano100Series.h.
| #define PDMA_CSR_SAD_SEL_Pos (4) |
PDMA_T::CSR: SAD_SEL Position
Definition at line 1893 of file Nano100Series.h.
| #define PDMA_CSR_SW_RST_Msk (0x1ul << PDMA_CSR_SW_RST_Pos) |
PDMA_T::CSR: SW_RST Mask
Definition at line 1888 of file Nano100Series.h.
| #define PDMA_CSR_SW_RST_Pos (1) |
PDMA_T::CSR: SW_RST Position
Definition at line 1887 of file Nano100Series.h.
| #define PDMA_CSR_TO_EN_Msk (0x1ul << PDMA_CSR_TO_EN_Pos) |
PDMA_T::CSR: TO_EN Mask
Definition at line 1900 of file Nano100Series.h.
| #define PDMA_CSR_TO_EN_Pos (12) |
PDMA_T::CSR: TO_EN Position
Definition at line 1899 of file Nano100Series.h.
| #define PDMA_CSR_TRIG_EN_Msk (0x1ul << PDMA_CSR_TRIG_EN_Pos) |
PDMA_T::CSR: TRIG_EN Mask
Definition at line 1906 of file Nano100Series.h.
| #define PDMA_CSR_TRIG_EN_Pos (23) |
PDMA_T::CSR: TRIG_EN Position
Definition at line 1905 of file Nano100Series.h.
| #define PDMA_DAR_PDMA_DAR_Msk (0xfffffffful << PDMA_DAR_PDMA_DAR_Pos) |
PDMA_T::DAR: PDMA_DAR Mask
Definition at line 1912 of file Nano100Series.h.
| #define PDMA_DAR_PDMA_DAR_Pos (0) |
PDMA_T::DAR: PDMA_DAR Position
Definition at line 1911 of file Nano100Series.h.
| #define PDMA_IER_TABORT_IE_Msk (0x1ul << PDMA_IER_TABORT_IE_Pos) |
PDMA_T::IER: TABORT_IE Mask
Definition at line 1927 of file Nano100Series.h.
| #define PDMA_IER_TABORT_IE_Pos (0) |
PDMA_T::IER: TABORT_IE Position
Definition at line 1926 of file Nano100Series.h.
| #define PDMA_IER_TD_IE_Msk (0x1ul << PDMA_IER_TD_IE_Pos) |
PDMA_T::IER: TD_IE Mask
Definition at line 1930 of file Nano100Series.h.
| #define PDMA_IER_TD_IE_Pos (1) |
PDMA_T::IER: TD_IE Position
Definition at line 1929 of file Nano100Series.h.
| #define PDMA_IER_TO_IE_Msk (0x1ul << PDMA_IER_TO_IE_Pos) |
PDMA_T::IER: TO_IE Mask
Definition at line 1936 of file Nano100Series.h.
| #define PDMA_IER_TO_IE_Pos (6) |
PDMA_T::IER: TO_IE Position
Definition at line 1935 of file Nano100Series.h.
| #define PDMA_IER_WRA_BCR_IE_Msk (0xful << PDMA_IER_WRA_BCR_IE_Pos) |
PDMA_T::IER: WRA_BCR_IE Mask
Definition at line 1933 of file Nano100Series.h.
| #define PDMA_IER_WRA_BCR_IE_Pos (2) |
PDMA_T::IER: WRA_BCR_IE Position
Definition at line 1932 of file Nano100Series.h.
| #define PDMA_ISR_TABORT_IS_Msk (0x1ul << PDMA_ISR_TABORT_IS_Pos) |
PDMA_T::ISR: TABORT_IS Mask
Definition at line 1939 of file Nano100Series.h.
| #define PDMA_ISR_TABORT_IS_Pos (0) |
PDMA_T::ISR: TABORT_IS Position
Definition at line 1938 of file Nano100Series.h.
| #define PDMA_ISR_TD_IS_Msk (0x1ul << PDMA_ISR_TD_IS_Pos) |
PDMA_T::ISR: TD_IS Mask
Definition at line 1942 of file Nano100Series.h.
| #define PDMA_ISR_TD_IS_Pos (1) |
PDMA_T::ISR: TD_IS Position
Definition at line 1941 of file Nano100Series.h.
| #define PDMA_ISR_TO_IS_Msk (0x1ul << PDMA_ISR_TO_IS_Pos) |
PDMA_T::ISR: TO_IS Mask
Definition at line 1948 of file Nano100Series.h.
| #define PDMA_ISR_TO_IS_Pos (6) |
PDMA_T::ISR: TO_IS Position
Definition at line 1947 of file Nano100Series.h.
| #define PDMA_ISR_WRA_BCR_IS_Msk (0xful << PDMA_ISR_WRA_BCR_IS_Pos) |
PDMA_T::ISR: WRA_BCR_IS Mask
Definition at line 1945 of file Nano100Series.h.
| #define PDMA_ISR_WRA_BCR_IS_Pos (2) |
PDMA_T::ISR: WRA_BCR_IS Position
Definition at line 1944 of file Nano100Series.h.
| #define PDMA_SAR_PDMA_SAR_Msk (0xfffffffful << PDMA_SAR_PDMA_SAR_Pos) |
PDMA_T::SAR: PDMA_SAR Mask
Definition at line 1909 of file Nano100Series.h.
| #define PDMA_SAR_PDMA_SAR_Pos (0) |
PDMA_T::SAR: PDMA_SAR Position
Definition at line 1908 of file Nano100Series.h.
| #define PDMA_TCR_PDMA_TCR_Msk (0xfffful << PDMA_TCR_PDMA_TCR_Pos) |
PDMA_T::TCR: PDMA_TCR Mask
Definition at line 1951 of file Nano100Series.h.
| #define PDMA_TCR_PDMA_TCR_Pos (0) |
PDMA_T::TCR: PDMA_TCR Position
Definition at line 1950 of file Nano100Series.h.
| #define PWM_CAPCTL_CAPCH0EN_Msk (0x1ul << PWM_CAPCTL_CAPCH0EN_Pos) |
PWM_T::CAPCTL: CAPCH0EN Mask
Definition at line 6246 of file Nano100Series.h.
| #define PWM_CAPCTL_CAPCH0EN_Pos (1) |
PWM_T::CAPCTL: CAPCH0EN Position
Definition at line 6245 of file Nano100Series.h.
| #define PWM_CAPCTL_CAPCH0PADEN_Msk (0x1ul << PWM_CAPCTL_CAPCH0PADEN_Pos) |
PWM_T::CAPCTL: CAPCH0PADEN Mask
Definition at line 6249 of file Nano100Series.h.
| #define PWM_CAPCTL_CAPCH0PADEN_Pos (2) |
PWM_T::CAPCTL: CAPCH0PADEN Position
Definition at line 6248 of file Nano100Series.h.
| #define PWM_CAPCTL_CAPCH1EN_Msk (0x1ul << PWM_CAPCTL_CAPCH1EN_Pos) |
PWM_T::CAPCTL: CAPCH1EN Mask
Definition at line 6267 of file Nano100Series.h.
| #define PWM_CAPCTL_CAPCH1EN_Pos (9) |
PWM_T::CAPCTL: CAPCH1EN Position
Definition at line 6266 of file Nano100Series.h.
| #define PWM_CAPCTL_CAPCH1PADEN_Msk (0x1ul << PWM_CAPCTL_CAPCH1PADEN_Pos) |
PWM_T::CAPCTL: CAPCH1PADEN Mask
Definition at line 6270 of file Nano100Series.h.
| #define PWM_CAPCTL_CAPCH1PADEN_Pos (10) |
PWM_T::CAPCTL: CAPCH1PADEN Position
Definition at line 6269 of file Nano100Series.h.
| #define PWM_CAPCTL_CAPCH2EN_Msk (0x1ul << PWM_CAPCTL_CAPCH2EN_Pos) |
PWM_T::CAPCTL: CAPCH2EN Mask
Definition at line 6288 of file Nano100Series.h.
| #define PWM_CAPCTL_CAPCH2EN_Pos (17) |
PWM_T::CAPCTL: CAPCH2EN Position
Definition at line 6287 of file Nano100Series.h.
| #define PWM_CAPCTL_CAPCH2PADEN_Msk (0x1ul << PWM_CAPCTL_CAPCH2PADEN_Pos) |
PWM_T::CAPCTL: CAPCH2PADEN Mask
Definition at line 6291 of file Nano100Series.h.
| #define PWM_CAPCTL_CAPCH2PADEN_Pos (18) |
PWM_T::CAPCTL: CAPCH2PADEN Position
Definition at line 6290 of file Nano100Series.h.
| #define PWM_CAPCTL_CAPCH3EN_Msk (0x1ul << PWM_CAPCTL_CAPCH3EN_Pos) |
PWM_T::CAPCTL: CAPCH3EN Mask
Definition at line 6309 of file Nano100Series.h.
| #define PWM_CAPCTL_CAPCH3EN_Pos (25) |
PWM_T::CAPCTL: CAPCH3EN Position
Definition at line 6308 of file Nano100Series.h.
| #define PWM_CAPCTL_CAPCH3PADEN_Msk (0x1ul << PWM_CAPCTL_CAPCH3PADEN_Pos) |
PWM_T::CAPCTL: CAPCH3PADEN Mask
Definition at line 6312 of file Nano100Series.h.
| #define PWM_CAPCTL_CAPCH3PADEN_Pos (26) |
PWM_T::CAPCTL: CAPCH3PADEN Position
Definition at line 6311 of file Nano100Series.h.
| #define PWM_CAPCTL_CAPRELOADFEN0_Msk (0x1ul << PWM_CAPCTL_CAPRELOADFEN0_Pos) |
PWM_T::CAPCTL: CAPRELOADFEN0 Mask
Definition at line 6261 of file Nano100Series.h.
| #define PWM_CAPCTL_CAPRELOADFEN0_Pos (7) |
PWM_T::CAPCTL: CAPRELOADFEN0 Position
Definition at line 6260 of file Nano100Series.h.
| #define PWM_CAPCTL_CAPRELOADFEN1_Msk (0x1ul << PWM_CAPCTL_CAPRELOADFEN1_Pos) |
PWM_T::CAPCTL: CAPRELOADFEN1 Mask
Definition at line 6282 of file Nano100Series.h.
| #define PWM_CAPCTL_CAPRELOADFEN1_Pos (15) |
PWM_T::CAPCTL: CAPRELOADFEN1 Position
Definition at line 6281 of file Nano100Series.h.
| #define PWM_CAPCTL_CAPRELOADFEN2_Msk (0x1ul << PWM_CAPCTL_CAPRELOADFEN2_Pos) |
PWM_T::CAPCTL: CAPRELOADFEN2 Mask
Definition at line 6303 of file Nano100Series.h.
| #define PWM_CAPCTL_CAPRELOADFEN2_Pos (23) |
PWM_T::CAPCTL: CAPRELOADFEN2 Position
Definition at line 6302 of file Nano100Series.h.
| #define PWM_CAPCTL_CAPRELOADFEN3_Msk (0x1ul << PWM_CAPCTL_CAPRELOADFEN3_Pos) |
PWM_T::CAPCTL: CAPRELOADFEN3 Mask
Definition at line 6324 of file Nano100Series.h.
| #define PWM_CAPCTL_CAPRELOADFEN3_Pos (31) |
PWM_T::CAPCTL: CAPRELOADFEN3 Position
Definition at line 6323 of file Nano100Series.h.
| #define PWM_CAPCTL_CAPRELOADREN0_Msk (0x1ul << PWM_CAPCTL_CAPRELOADREN0_Pos) |
PWM_T::CAPCTL: CAPRELOADREN0 Mask
Definition at line 6258 of file Nano100Series.h.
| #define PWM_CAPCTL_CAPRELOADREN0_Pos (6) |
PWM_T::CAPCTL: CAPRELOADREN0 Position
Definition at line 6257 of file Nano100Series.h.
| #define PWM_CAPCTL_CAPRELOADREN1_Msk (0x1ul << PWM_CAPCTL_CAPRELOADREN1_Pos) |
PWM_T::CAPCTL: CAPRELOADREN1 Mask
Definition at line 6279 of file Nano100Series.h.
| #define PWM_CAPCTL_CAPRELOADREN1_Pos (14) |
PWM_T::CAPCTL: CAPRELOADREN1 Position
Definition at line 6278 of file Nano100Series.h.
| #define PWM_CAPCTL_CAPRELOADREN2_Msk (0x1ul << PWM_CAPCTL_CAPRELOADREN2_Pos) |
PWM_T::CAPCTL: CAPRELOADREN2 Mask
Definition at line 6300 of file Nano100Series.h.
| #define PWM_CAPCTL_CAPRELOADREN2_Pos (22) |
PWM_T::CAPCTL: CAPRELOADREN2 Position
Definition at line 6299 of file Nano100Series.h.
| #define PWM_CAPCTL_CAPRELOADREN3_Msk (0x1ul << PWM_CAPCTL_CAPRELOADREN3_Pos) |
PWM_T::CAPCTL: CAPRELOADREN3 Mask
Definition at line 6321 of file Nano100Series.h.
| #define PWM_CAPCTL_CAPRELOADREN3_Pos (30) |
PWM_T::CAPCTL: CAPRELOADREN3 Position
Definition at line 6320 of file Nano100Series.h.
| #define PWM_CAPCTL_CH01CASK_Msk (0x1ul << PWM_CAPCTL_CH01CASK_Pos) |
PWM_T::CAPCTL: CH01CASK Mask
Definition at line 6276 of file Nano100Series.h.
| #define PWM_CAPCTL_CH01CASK_Pos (13) |
PWM_T::CAPCTL: CH01CASK Position
Definition at line 6275 of file Nano100Series.h.
| #define PWM_CAPCTL_CH0PDMAEN_Msk (0x1ul << PWM_CAPCTL_CH0PDMAEN_Pos) |
PWM_T::CAPCTL: CH0PDMAEN Mask
Definition at line 6252 of file Nano100Series.h.
| #define PWM_CAPCTL_CH0PDMAEN_Pos (3) |
PWM_T::CAPCTL: CH0PDMAEN Position
Definition at line 6251 of file Nano100Series.h.
| #define PWM_CAPCTL_CH0RFORDER_Msk (0x1ul << PWM_CAPCTL_CH0RFORDER_Pos) |
PWM_T::CAPCTL: CH0RFORDER Mask
Definition at line 6273 of file Nano100Series.h.
| #define PWM_CAPCTL_CH0RFORDER_Pos (12) |
PWM_T::CAPCTL: CH0RFORDER Position
Definition at line 6272 of file Nano100Series.h.
| #define PWM_CAPCTL_CH23CASK_Msk (0x1ul << PWM_CAPCTL_CH23CASK_Pos) |
PWM_T::CAPCTL: CH23CASK Mask
Definition at line 6318 of file Nano100Series.h.
| #define PWM_CAPCTL_CH23CASK_Pos (29) |
PWM_T::CAPCTL: CH23CASK Position
Definition at line 6317 of file Nano100Series.h.
| #define PWM_CAPCTL_CH2PDMAEN_Msk (0x1ul << PWM_CAPCTL_CH2PDMAEN_Pos) |
PWM_T::CAPCTL: CH2PDMAEN Mask
Definition at line 6294 of file Nano100Series.h.
| #define PWM_CAPCTL_CH2PDMAEN_Pos (19) |
PWM_T::CAPCTL: CH2PDMAEN Position
Definition at line 6293 of file Nano100Series.h.
| #define PWM_CAPCTL_CH2RFORDER_Msk (0x1ul << PWM_CAPCTL_CH2RFORDER_Pos) |
PWM_T::CAPCTL: CH2RFORDER Mask
Definition at line 6315 of file Nano100Series.h.
| #define PWM_CAPCTL_CH2RFORDER_Pos (28) |
PWM_T::CAPCTL: CH2RFORDER Position
Definition at line 6314 of file Nano100Series.h.
| #define PWM_CAPCTL_INV0_Msk (0x1ul << PWM_CAPCTL_INV0_Pos) |
PWM_T::CAPCTL: INV0 Mask
Definition at line 6243 of file Nano100Series.h.
| #define PWM_CAPCTL_INV0_Pos (0) |
PWM_T::CAPCTL: INV0 Position
Definition at line 6242 of file Nano100Series.h.
| #define PWM_CAPCTL_INV1_Msk (0x1ul << PWM_CAPCTL_INV1_Pos) |
PWM_T::CAPCTL: INV1 Mask
Definition at line 6264 of file Nano100Series.h.
| #define PWM_CAPCTL_INV1_Pos (8) |
PWM_T::CAPCTL: INV1 Position
Definition at line 6263 of file Nano100Series.h.
| #define PWM_CAPCTL_INV2_Msk (0x1ul << PWM_CAPCTL_INV2_Pos) |
PWM_T::CAPCTL: INV2 Mask
Definition at line 6285 of file Nano100Series.h.
| #define PWM_CAPCTL_INV2_Pos (16) |
PWM_T::CAPCTL: INV2 Position
Definition at line 6284 of file Nano100Series.h.
| #define PWM_CAPCTL_INV3_Msk (0x1ul << PWM_CAPCTL_INV3_Pos) |
PWM_T::CAPCTL: INV3 Mask
Definition at line 6306 of file Nano100Series.h.
| #define PWM_CAPCTL_INV3_Pos (24) |
PWM_T::CAPCTL: INV3 Position
Definition at line 6305 of file Nano100Series.h.
| #define PWM_CAPCTL_PDMACAPMOD0_Msk (0x3ul << PWM_CAPCTL_PDMACAPMOD0_Pos) |
PWM_T::CAPCTL: PDMACAPMOD0 Mask
Definition at line 6255 of file Nano100Series.h.
| #define PWM_CAPCTL_PDMACAPMOD0_Pos (4) |
PWM_T::CAPCTL: PDMACAPMOD0 Position
Definition at line 6254 of file Nano100Series.h.
| #define PWM_CAPCTL_PDMACAPMOD2_Msk (0x3ul << PWM_CAPCTL_PDMACAPMOD2_Pos) |
PWM_T::CAPCTL: PDMACAPMOD2 Mask
Definition at line 6297 of file Nano100Series.h.
| #define PWM_CAPCTL_PDMACAPMOD2_Pos (20) |
PWM_T::CAPCTL: PDMACAPMOD2 Position
Definition at line 6296 of file Nano100Series.h.
| #define PWM_CAPINTEN_CFL_IE0_Msk (0x1ul << PWM_CAPINTEN_CFL_IE0_Pos) |
PWM_T::CAPINTEN: CFL_IE0 Mask
Definition at line 6330 of file Nano100Series.h.
| #define PWM_CAPINTEN_CFL_IE0_Pos (1) |
PWM_T::CAPINTEN: CFL_IE0 Position
Definition at line 6329 of file Nano100Series.h.
| #define PWM_CAPINTEN_CFL_IE1_Msk (0x1ul << PWM_CAPINTEN_CFL_IE1_Pos) |
PWM_T::CAPINTEN: CFL_IE1 Mask
Definition at line 6336 of file Nano100Series.h.
| #define PWM_CAPINTEN_CFL_IE1_Pos (9) |
PWM_T::CAPINTEN: CFL_IE1 Position
Definition at line 6335 of file Nano100Series.h.
| #define PWM_CAPINTEN_CFL_IE2_Msk (0x1ul << PWM_CAPINTEN_CFL_IE2_Pos) |
PWM_T::CAPINTEN: CFL_IE2 Mask
Definition at line 6342 of file Nano100Series.h.
| #define PWM_CAPINTEN_CFL_IE2_Pos (17) |
PWM_T::CAPINTEN: CFL_IE2 Position
Definition at line 6341 of file Nano100Series.h.
| #define PWM_CAPINTEN_CFL_IE3_Msk (0x1ul << PWM_CAPINTEN_CFL_IE3_Pos) |
PWM_T::CAPINTEN: CFL_IE3 Mask
Definition at line 6348 of file Nano100Series.h.
| #define PWM_CAPINTEN_CFL_IE3_Pos (25) |
PWM_T::CAPINTEN: CFL_IE3 Position
Definition at line 6347 of file Nano100Series.h.
| #define PWM_CAPINTEN_CRL_IE0_Msk (0x1ul << PWM_CAPINTEN_CRL_IE0_Pos) |
PWM_T::CAPINTEN: CRL_IE0 Mask
Definition at line 6327 of file Nano100Series.h.
| #define PWM_CAPINTEN_CRL_IE0_Pos (0) |
PWM_T::CAPINTEN: CRL_IE0 Position
Definition at line 6326 of file Nano100Series.h.
| #define PWM_CAPINTEN_CRL_IE1_Msk (0x1ul << PWM_CAPINTEN_CRL_IE1_Pos) |
PWM_T::CAPINTEN: CRL_IE1 Mask
Definition at line 6333 of file Nano100Series.h.
| #define PWM_CAPINTEN_CRL_IE1_Pos (8) |
PWM_T::CAPINTEN: CRL_IE1 Position
Definition at line 6332 of file Nano100Series.h.
| #define PWM_CAPINTEN_CRL_IE2_Msk (0x1ul << PWM_CAPINTEN_CRL_IE2_Pos) |
PWM_T::CAPINTEN: CRL_IE2 Mask
Definition at line 6339 of file Nano100Series.h.
| #define PWM_CAPINTEN_CRL_IE2_Pos (16) |
PWM_T::CAPINTEN: CRL_IE2 Position
Definition at line 6338 of file Nano100Series.h.
| #define PWM_CAPINTEN_CRL_IE3_Msk (0x1ul << PWM_CAPINTEN_CRL_IE3_Pos) |
PWM_T::CAPINTEN: CRL_IE3 Mask
Definition at line 6345 of file Nano100Series.h.
| #define PWM_CAPINTEN_CRL_IE3_Pos (24) |
PWM_T::CAPINTEN: CRL_IE3 Position
Definition at line 6344 of file Nano100Series.h.
| #define PWM_CAPINTSTS_CAPIF0_Msk (0x1ul << PWM_CAPINTSTS_CAPIF0_Pos) |
PWM_T::CAPINTSTS: CAPIF0 Mask
Definition at line 6351 of file Nano100Series.h.
| #define PWM_CAPINTSTS_CAPIF0_Pos (0) |
PWM_T::CAPINTSTS: CAPIF0 Position
Definition at line 6350 of file Nano100Series.h.
| #define PWM_CAPINTSTS_CAPIF1_Msk (0x1ul << PWM_CAPINTSTS_CAPIF1_Pos) |
PWM_T::CAPINTSTS: CAPIF1 Mask
Definition at line 6366 of file Nano100Series.h.
| #define PWM_CAPINTSTS_CAPIF1_Pos (8) |
PWM_T::CAPINTSTS: CAPIF1 Position
Definition at line 6365 of file Nano100Series.h.
| #define PWM_CAPINTSTS_CAPIF2_Msk (0x1ul << PWM_CAPINTSTS_CAPIF2_Pos) |
PWM_T::CAPINTSTS: CAPIF2 Mask
Definition at line 6381 of file Nano100Series.h.
| #define PWM_CAPINTSTS_CAPIF2_Pos (16) |
PWM_T::CAPINTSTS: CAPIF2 Position
Definition at line 6380 of file Nano100Series.h.
| #define PWM_CAPINTSTS_CAPIF3_Msk (0x1ul << PWM_CAPINTSTS_CAPIF3_Pos) |
PWM_T::CAPINTSTS: CAPIF3 Mask
Definition at line 6396 of file Nano100Series.h.
| #define PWM_CAPINTSTS_CAPIF3_Pos (24) |
PWM_T::CAPINTSTS: CAPIF3 Position
Definition at line 6395 of file Nano100Series.h.
| #define PWM_CAPINTSTS_CAPOVF0_Msk (0x1ul << PWM_CAPINTSTS_CAPOVF0_Pos) |
PWM_T::CAPINTSTS: CAPOVF0 Mask
Definition at line 6363 of file Nano100Series.h.
| #define PWM_CAPINTSTS_CAPOVF0_Pos (4) |
PWM_T::CAPINTSTS: CAPOVF0 Position
Definition at line 6362 of file Nano100Series.h.
| #define PWM_CAPINTSTS_CAPOVF1_Msk (0x1ul << PWM_CAPINTSTS_CAPOVF1_Pos) |
PWM_T::CAPINTSTS: CAPOVF1 Mask
Definition at line 6378 of file Nano100Series.h.
| #define PWM_CAPINTSTS_CAPOVF1_Pos (12) |
PWM_T::CAPINTSTS: CAPOVF1 Position
Definition at line 6377 of file Nano100Series.h.
| #define PWM_CAPINTSTS_CAPOVF2_Msk (0x1ul << PWM_CAPINTSTS_CAPOVF2_Pos) |
PWM_T::CAPINTSTS: CAPOVF2 Mask
Definition at line 6393 of file Nano100Series.h.
| #define PWM_CAPINTSTS_CAPOVF2_Pos (20) |
PWM_T::CAPINTSTS: CAPOVF2 Position
Definition at line 6392 of file Nano100Series.h.
| #define PWM_CAPINTSTS_CAPOVF3_Msk (0x1ul << PWM_CAPINTSTS_CAPOVF3_Pos) |
PWM_T::CAPINTSTS: CAPOVF3 Mask
Definition at line 6408 of file Nano100Series.h.
| #define PWM_CAPINTSTS_CAPOVF3_Pos (28) |
PWM_T::CAPINTSTS: CAPOVF3 Position
Definition at line 6407 of file Nano100Series.h.
| #define PWM_CAPINTSTS_CAPOVR0_Msk (0x1ul << PWM_CAPINTSTS_CAPOVR0_Pos) |
PWM_T::CAPINTSTS: CAPOVR0 Mask
Definition at line 6360 of file Nano100Series.h.
| #define PWM_CAPINTSTS_CAPOVR0_Pos (3) |
PWM_T::CAPINTSTS: CAPOVR0 Position
Definition at line 6359 of file Nano100Series.h.
| #define PWM_CAPINTSTS_CAPOVR1_Msk (0x1ul << PWM_CAPINTSTS_CAPOVR1_Pos) |
PWM_T::CAPINTSTS: CAPOVR1 Mask
Definition at line 6375 of file Nano100Series.h.
| #define PWM_CAPINTSTS_CAPOVR1_Pos (11) |
PWM_T::CAPINTSTS: CAPOVR1 Position
Definition at line 6374 of file Nano100Series.h.
| #define PWM_CAPINTSTS_CAPOVR2_Msk (0x1ul << PWM_CAPINTSTS_CAPOVR2_Pos) |
PWM_T::CAPINTSTS: CAPOVR2 Mask
Definition at line 6390 of file Nano100Series.h.
| #define PWM_CAPINTSTS_CAPOVR2_Pos (19) |
PWM_T::CAPINTSTS: CAPOVR2 Position
Definition at line 6389 of file Nano100Series.h.
| #define PWM_CAPINTSTS_CAPOVR3_Msk (0x1ul << PWM_CAPINTSTS_CAPOVR3_Pos) |
PWM_T::CAPINTSTS: CAPOVR3 Mask
Definition at line 6405 of file Nano100Series.h.
| #define PWM_CAPINTSTS_CAPOVR3_Pos (27) |
PWM_T::CAPINTSTS: CAPOVR3 Position
Definition at line 6404 of file Nano100Series.h.
| #define PWM_CAPINTSTS_CFLI1_Msk (0x1ul << PWM_CAPINTSTS_CFLI1_Pos) |
PWM_T::CAPINTSTS: CFLI1 Mask
Definition at line 6372 of file Nano100Series.h.
| #define PWM_CAPINTSTS_CFLI1_Pos (10) |
PWM_T::CAPINTSTS: CFLI1 Position
Definition at line 6371 of file Nano100Series.h.
| #define PWM_CAPINTSTS_CFLI2_Msk (0x1ul << PWM_CAPINTSTS_CFLI2_Pos) |
PWM_T::CAPINTSTS: CFLI2 Mask
Definition at line 6387 of file Nano100Series.h.
| #define PWM_CAPINTSTS_CFLI2_Pos (18) |
PWM_T::CAPINTSTS: CFLI2 Position
Definition at line 6386 of file Nano100Series.h.
| #define PWM_CAPINTSTS_CFLI3_Msk (0x1ul << PWM_CAPINTSTS_CFLI3_Pos) |
PWM_T::CAPINTSTS: CFLI3 Mask
Definition at line 6402 of file Nano100Series.h.
| #define PWM_CAPINTSTS_CFLI3_Pos (26) |
PWM_T::CAPINTSTS: CFLI3 Position
Definition at line 6401 of file Nano100Series.h.
| #define PWM_CAPINTSTS_CFLRI0_Msk (0x1ul << PWM_CAPINTSTS_CFLRI0_Pos) |
PWM_T::CAPINTSTS: CFLRI0 Mask
Definition at line 6357 of file Nano100Series.h.
| #define PWM_CAPINTSTS_CFLRI0_Pos (2) |
PWM_T::CAPINTSTS: CFLRI0 Position
Definition at line 6356 of file Nano100Series.h.
| #define PWM_CAPINTSTS_CRLI0_Msk (0x1ul << PWM_CAPINTSTS_CRLI0_Pos) |
PWM_T::CAPINTSTS: CRLI0 Mask
Definition at line 6354 of file Nano100Series.h.
| #define PWM_CAPINTSTS_CRLI0_Pos (1) |
PWM_T::CAPINTSTS: CRLI0 Position
Definition at line 6353 of file Nano100Series.h.
| #define PWM_CAPINTSTS_CRLI1_Msk (0x1ul << PWM_CAPINTSTS_CRLI1_Pos) |
PWM_T::CAPINTSTS: CRLI1 Mask
Definition at line 6369 of file Nano100Series.h.
| #define PWM_CAPINTSTS_CRLI1_Pos (9) |
PWM_T::CAPINTSTS: CRLI1 Position
Definition at line 6368 of file Nano100Series.h.
| #define PWM_CAPINTSTS_CRLI2_Msk (0x1ul << PWM_CAPINTSTS_CRLI2_Pos) |
PWM_T::CAPINTSTS: CRLI2 Mask
Definition at line 6384 of file Nano100Series.h.
| #define PWM_CAPINTSTS_CRLI2_Pos (17) |
PWM_T::CAPINTSTS: CRLI2 Position
Definition at line 6383 of file Nano100Series.h.
| #define PWM_CAPINTSTS_CRLI3_Msk (0x1ul << PWM_CAPINTSTS_CRLI3_Pos) |
PWM_T::CAPINTSTS: CRLI3 Mask
Definition at line 6399 of file Nano100Series.h.
| #define PWM_CAPINTSTS_CRLI3_Pos (25) |
PWM_T::CAPINTSTS: CRLI3 Position
Definition at line 6398 of file Nano100Series.h.
| #define PWM_CFL0_CFL15_0_Msk (0xfffful << PWM_CFL0_CFL15_0_Pos) |
PWM_T::CFL0: CFL15_0 Mask
Definition at line 6417 of file Nano100Series.h.
| #define PWM_CFL0_CFL15_0_Pos (0) |
PWM_T::CFL0: CFL15_0 Position
Definition at line 6416 of file Nano100Series.h.
| #define PWM_CFL0_CFL31_16_Msk (0xfffful << PWM_CFL0_CFL31_16_Pos) |
PWM_T::CFL0: CFL31_16 Mask
Definition at line 6420 of file Nano100Series.h.
| #define PWM_CFL0_CFL31_16_Pos (16) |
PWM_T::CFL0: CFL31_16 Position
Definition at line 6419 of file Nano100Series.h.
| #define PWM_CFL1_CFL15_0_Msk (0xfffful << PWM_CFL1_CFL15_0_Pos) |
PWM_T::CFL1: CFL15_0 Mask
Definition at line 6429 of file Nano100Series.h.
| #define PWM_CFL1_CFL15_0_Pos (0) |
PWM_T::CFL1: CFL15_0 Position
Definition at line 6428 of file Nano100Series.h.
| #define PWM_CFL1_CFL31_16_Msk (0xfffful << PWM_CFL1_CFL31_16_Pos) |
PWM_T::CFL1: CFL31_16 Mask
Definition at line 6432 of file Nano100Series.h.
| #define PWM_CFL1_CFL31_16_Pos (16) |
PWM_T::CFL1: CFL31_16 Position
Definition at line 6431 of file Nano100Series.h.
| #define PWM_CFL2_CFL15_0_Msk (0xfffful << PWM_CFL2_CFL15_0_Pos) |
PWM_T::CFL2: CFL15_0 Mask
Definition at line 6441 of file Nano100Series.h.
| #define PWM_CFL2_CFL15_0_Pos (0) |
PWM_T::CFL2: CFL15_0 Position
Definition at line 6440 of file Nano100Series.h.
| #define PWM_CFL2_CFL31_16_Msk (0xfffful << PWM_CFL2_CFL31_16_Pos) |
PWM_T::CFL2: CFL31_16 Mask
Definition at line 6444 of file Nano100Series.h.
| #define PWM_CFL2_CFL31_16_Pos (16) |
PWM_T::CFL2: CFL31_16 Position
Definition at line 6443 of file Nano100Series.h.
| #define PWM_CFL3_CFL15_0_Msk (0xfffful << PWM_CFL3_CFL15_0_Pos) |
PWM_T::CFL3: CFL15_0 Mask
Definition at line 6453 of file Nano100Series.h.
| #define PWM_CFL3_CFL15_0_Pos (0) |
PWM_T::CFL3: CFL15_0 Position
Definition at line 6452 of file Nano100Series.h.
| #define PWM_CFL3_CFL31_16_Msk (0xfffful << PWM_CFL3_CFL31_16_Pos) |
PWM_T::CFL3: CFL31_16 Mask
Definition at line 6456 of file Nano100Series.h.
| #define PWM_CFL3_CFL31_16_Pos (16) |
PWM_T::CFL3: CFL31_16 Position
Definition at line 6455 of file Nano100Series.h.
| #define PWM_CLKSEL_CLKSEL0_Msk (0x7ul << PWM_CLKSEL_CLKSEL0_Pos) |
PWM_T::CLKSEL: CLKSEL0 Mask
Definition at line 6078 of file Nano100Series.h.
| #define PWM_CLKSEL_CLKSEL0_Pos (0) |
PWM_T::CLKSEL: CLKSEL0 Position
Definition at line 6077 of file Nano100Series.h.
| #define PWM_CLKSEL_CLKSEL1_Msk (0x7ul << PWM_CLKSEL_CLKSEL1_Pos) |
PWM_T::CLKSEL: CLKSEL1 Mask
Definition at line 6081 of file Nano100Series.h.
| #define PWM_CLKSEL_CLKSEL1_Pos (4) |
PWM_T::CLKSEL: CLKSEL1 Position
Definition at line 6080 of file Nano100Series.h.
| #define PWM_CLKSEL_CLKSEL2_Msk (0x7ul << PWM_CLKSEL_CLKSEL2_Pos) |
PWM_T::CLKSEL: CLKSEL2 Mask
Definition at line 6084 of file Nano100Series.h.
| #define PWM_CLKSEL_CLKSEL2_Pos (8) |
PWM_T::CLKSEL: CLKSEL2 Position
Definition at line 6083 of file Nano100Series.h.
| #define PWM_CLKSEL_CLKSEL3_Msk (0x7ul << PWM_CLKSEL_CLKSEL3_Pos) |
PWM_T::CLKSEL: CLKSEL3 Mask
Definition at line 6087 of file Nano100Series.h.
| #define PWM_CLKSEL_CLKSEL3_Pos (12) |
PWM_T::CLKSEL: CLKSEL3 Position
Definition at line 6086 of file Nano100Series.h.
| #define PWM_CRL0_CRL15_0_Msk (0xfffful << PWM_CRL0_CRL15_0_Pos) |
PWM_T::CRL0: CRL15_0 Mask
Definition at line 6411 of file Nano100Series.h.
| #define PWM_CRL0_CRL15_0_Pos (0) |
PWM_T::CRL0: CRL15_0 Position
Definition at line 6410 of file Nano100Series.h.
| #define PWM_CRL0_CRL31_16_Msk (0xfffful << PWM_CRL0_CRL31_16_Pos) |
PWM_T::CRL0: CRL31_16 Mask
Definition at line 6414 of file Nano100Series.h.
| #define PWM_CRL0_CRL31_16_Pos (16) |
PWM_T::CRL0: CRL31_16 Position
Definition at line 6413 of file Nano100Series.h.
| #define PWM_CRL1_CRL15_0_Msk (0xfffful << PWM_CRL1_CRL15_0_Pos) |
PWM_T::CRL1: CRL15_0 Mask
Definition at line 6423 of file Nano100Series.h.
| #define PWM_CRL1_CRL15_0_Pos (0) |
PWM_T::CRL1: CRL15_0 Position
Definition at line 6422 of file Nano100Series.h.
| #define PWM_CRL1_CRL31_16_Msk (0xfffful << PWM_CRL1_CRL31_16_Pos) |
PWM_T::CRL1: CRL31_16 Mask
Definition at line 6426 of file Nano100Series.h.
| #define PWM_CRL1_CRL31_16_Pos (16) |
PWM_T::CRL1: CRL31_16 Position
Definition at line 6425 of file Nano100Series.h.
| #define PWM_CRL2_CRL15_0_Msk (0xfffful << PWM_CRL2_CRL15_0_Pos) |
PWM_T::CRL2: CRL15_0 Mask
Definition at line 6435 of file Nano100Series.h.
| #define PWM_CRL2_CRL15_0_Pos (0) |
PWM_T::CRL2: CRL15_0 Position
Definition at line 6434 of file Nano100Series.h.
| #define PWM_CRL2_CRL31_16_Msk (0xfffful << PWM_CRL2_CRL31_16_Pos) |
PWM_T::CRL2: CRL31_16 Mask
Definition at line 6438 of file Nano100Series.h.
| #define PWM_CRL2_CRL31_16_Pos (16) |
PWM_T::CRL2: CRL31_16 Position
Definition at line 6437 of file Nano100Series.h.
| #define PWM_CRL3_CRL15_0_Msk (0xfffful << PWM_CRL3_CRL15_0_Pos) |
PWM_T::CRL3: CRL15_0 Mask
Definition at line 6447 of file Nano100Series.h.
| #define PWM_CRL3_CRL15_0_Pos (0) |
PWM_T::CRL3: CRL15_0 Position
Definition at line 6446 of file Nano100Series.h.
| #define PWM_CRL3_CRL31_16_Msk (0xfffful << PWM_CRL3_CRL31_16_Pos) |
PWM_T::CRL3: CRL31_16 Mask
Definition at line 6450 of file Nano100Series.h.
| #define PWM_CRL3_CRL31_16_Pos (16) |
PWM_T::CRL3: CRL31_16 Position
Definition at line 6449 of file Nano100Series.h.
| #define PWM_CTL_CH0EN_Msk (0x1ul << PWM_CTL_CH0EN_Pos) |
PWM_T::CTL: CH0EN Mask
Definition at line 6090 of file Nano100Series.h.
| #define PWM_CTL_CH0EN_Pos (0) |
PWM_T::CTL: CH0EN Position
Definition at line 6089 of file Nano100Series.h.
| #define PWM_CTL_CH0INV_Msk (0x1ul << PWM_CTL_CH0INV_Pos) |
PWM_T::CTL: CH0INV Mask
Definition at line 6093 of file Nano100Series.h.
| #define PWM_CTL_CH0INV_Pos (2) |
PWM_T::CTL: CH0INV Position
Definition at line 6092 of file Nano100Series.h.
| #define PWM_CTL_CH0MOD_Msk (0x1ul << PWM_CTL_CH0MOD_Pos) |
PWM_T::CTL: CH0MOD Mask
Definition at line 6096 of file Nano100Series.h.
| #define PWM_CTL_CH0MOD_Pos (3) |
PWM_T::CTL: CH0MOD Position
Definition at line 6095 of file Nano100Series.h.
| #define PWM_CTL_CH1EN_Msk (0x1ul << PWM_CTL_CH1EN_Pos) |
PWM_T::CTL: CH1EN Mask
Definition at line 6105 of file Nano100Series.h.
| #define PWM_CTL_CH1EN_Pos (8) |
PWM_T::CTL: CH1EN Position
Definition at line 6104 of file Nano100Series.h.
| #define PWM_CTL_CH1INV_Msk (0x1ul << PWM_CTL_CH1INV_Pos) |
PWM_T::CTL: CH1INV Mask
Definition at line 6108 of file Nano100Series.h.
| #define PWM_CTL_CH1INV_Pos (10) |
PWM_T::CTL: CH1INV Position
Definition at line 6107 of file Nano100Series.h.
| #define PWM_CTL_CH1MOD_Msk (0x1ul << PWM_CTL_CH1MOD_Pos) |
PWM_T::CTL: CH1MOD Mask
Definition at line 6111 of file Nano100Series.h.
| #define PWM_CTL_CH1MOD_Pos (11) |
PWM_T::CTL: CH1MOD Position
Definition at line 6110 of file Nano100Series.h.
| #define PWM_CTL_CH2EN_Msk (0x1ul << PWM_CTL_CH2EN_Pos) |
PWM_T::CTL: CH2EN Mask
Definition at line 6114 of file Nano100Series.h.
| #define PWM_CTL_CH2EN_Pos (16) |
PWM_T::CTL: CH2EN Position
Definition at line 6113 of file Nano100Series.h.
| #define PWM_CTL_CH2INV_Msk (0x1ul << PWM_CTL_CH2INV_Pos) |
PWM_T::CTL: CH2INV Mask
Definition at line 6117 of file Nano100Series.h.
| #define PWM_CTL_CH2INV_Pos (18) |
PWM_T::CTL: CH2INV Position
Definition at line 6116 of file Nano100Series.h.
| #define PWM_CTL_CH2MOD_Msk (0x1ul << PWM_CTL_CH2MOD_Pos) |
PWM_T::CTL: CH2MOD Mask
Definition at line 6120 of file Nano100Series.h.
| #define PWM_CTL_CH2MOD_Pos (19) |
PWM_T::CTL: CH2MOD Position
Definition at line 6119 of file Nano100Series.h.
| #define PWM_CTL_CH3EN_Msk (0x1ul << PWM_CTL_CH3EN_Pos) |
PWM_T::CTL: CH3EN Mask
Definition at line 6123 of file Nano100Series.h.
| #define PWM_CTL_CH3EN_Pos (24) |
PWM_T::CTL: CH3EN Position
Definition at line 6122 of file Nano100Series.h.
| #define PWM_CTL_CH3INV_Msk (0x1ul << PWM_CTL_CH3INV_Pos) |
PWM_T::CTL: CH3INV Mask
Definition at line 6126 of file Nano100Series.h.
| #define PWM_CTL_CH3INV_Pos (26) |
PWM_T::CTL: CH3INV Position
Definition at line 6125 of file Nano100Series.h.
| #define PWM_CTL_CH3MOD_Msk (0x1ul << PWM_CTL_CH3MOD_Pos) |
PWM_T::CTL: CH3MOD Mask
Definition at line 6129 of file Nano100Series.h.
| #define PWM_CTL_CH3MOD_Pos (27) |
PWM_T::CTL: CH3MOD Position
Definition at line 6128 of file Nano100Series.h.
| #define PWM_CTL_DZEN01_Msk (0x1ul << PWM_CTL_DZEN01_Pos) |
PWM_T::CTL: DZEN01 Mask
Definition at line 6099 of file Nano100Series.h.
| #define PWM_CTL_DZEN01_Pos (4) |
PWM_T::CTL: DZEN01 Position
Definition at line 6098 of file Nano100Series.h.
| #define PWM_CTL_DZEN23_Msk (0x1ul << PWM_CTL_DZEN23_Pos) |
PWM_T::CTL: DZEN23 Mask
Definition at line 6102 of file Nano100Series.h.
| #define PWM_CTL_DZEN23_Pos (5) |
PWM_T::CTL: DZEN23 Position
Definition at line 6101 of file Nano100Series.h.
| #define PWM_DATA0_PWMx_DATAy15_0_Msk (0xfffful << PWM_DATA0_PWMx_DATAy15_0_Pos) |
PWM_T::DATA0: PWMx_DATAy15_0 Mask
Definition at line 6189 of file Nano100Series.h.
| #define PWM_DATA0_PWMx_DATAy15_0_Pos (0) |
PWM_T::DATA0: PWMx_DATAy15_0 Position
Definition at line 6188 of file Nano100Series.h.
| #define PWM_DATA0_PWMx_DATAy30_16_Msk (0x7ffful << PWM_DATA0_PWMx_DATAy30_16_Pos) |
PWM_T::DATA0: PWMx_DATAy30_16 Mask
Definition at line 6192 of file Nano100Series.h.
| #define PWM_DATA0_PWMx_DATAy30_16_Pos (16) |
PWM_T::DATA0: PWMx_DATAy30_16 Position
Definition at line 6191 of file Nano100Series.h.
| #define PWM_DATA0_sync_Msk (0x1ul << PWM_DATA0_sync_Pos) |
PWM_T::DATA0: sync Mask
Definition at line 6195 of file Nano100Series.h.
| #define PWM_DATA0_sync_Pos (31) |
PWM_T::DATA0: sync Position
Definition at line 6194 of file Nano100Series.h.
| #define PWM_DATA1_PWMx_DATAy15_0_Msk (0xfffful << PWM_DATA1_PWMx_DATAy15_0_Pos) |
PWM_T::DATA1: PWMx_DATAy15_0 Mask
Definition at line 6204 of file Nano100Series.h.
| #define PWM_DATA1_PWMx_DATAy15_0_Pos (0) |
PWM_T::DATA1: PWMx_DATAy15_0 Position
Definition at line 6203 of file Nano100Series.h.
| #define PWM_DATA1_PWMx_DATAy30_16_Msk (0x7ffful << PWM_DATA1_PWMx_DATAy30_16_Pos) |
PWM_T::DATA1: PWMx_DATAy30_16 Mask
Definition at line 6207 of file Nano100Series.h.
| #define PWM_DATA1_PWMx_DATAy30_16_Pos (16) |
PWM_T::DATA1: PWMx_DATAy30_16 Position
Definition at line 6206 of file Nano100Series.h.
| #define PWM_DATA1_sync_Msk (0x1ul << PWM_DATA1_sync_Pos) |
PWM_T::DATA1: sync Mask
Definition at line 6210 of file Nano100Series.h.
| #define PWM_DATA1_sync_Pos (31) |
PWM_T::DATA1: sync Position
Definition at line 6209 of file Nano100Series.h.
| #define PWM_DATA2_PWMx_DATAy15_0_Msk (0xfffful << PWM_DATA2_PWMx_DATAy15_0_Pos) |
PWM_T::DATA2: PWMx_DATAy15_0 Mask
Definition at line 6219 of file Nano100Series.h.
| #define PWM_DATA2_PWMx_DATAy15_0_Pos (0) |
PWM_T::DATA2: PWMx_DATAy15_0 Position
Definition at line 6218 of file Nano100Series.h.
| #define PWM_DATA2_PWMx_DATAy30_16_Msk (0x7ffful << PWM_DATA2_PWMx_DATAy30_16_Pos) |
PWM_T::DATA2: PWMx_DATAy30_16 Mask
Definition at line 6222 of file Nano100Series.h.
| #define PWM_DATA2_PWMx_DATAy30_16_Pos (16) |
PWM_T::DATA2: PWMx_DATAy30_16 Position
Definition at line 6221 of file Nano100Series.h.
| #define PWM_DATA2_sync_Msk (0x1ul << PWM_DATA2_sync_Pos) |
PWM_T::DATA2: sync Mask
Definition at line 6225 of file Nano100Series.h.
| #define PWM_DATA2_sync_Pos (31) |
PWM_T::DATA2: sync Position
Definition at line 6224 of file Nano100Series.h.
| #define PWM_DATA3_PWMx_DATAy15_0_Msk (0xfffful << PWM_DATA3_PWMx_DATAy15_0_Pos) |
PWM_T::DATA3: PWMx_DATAy15_0 Mask
Definition at line 6234 of file Nano100Series.h.
| #define PWM_DATA3_PWMx_DATAy15_0_Pos (0) |
PWM_T::DATA3: PWMx_DATAy15_0 Position
Definition at line 6233 of file Nano100Series.h.
| #define PWM_DATA3_PWMx_DATAy30_16_Msk (0x7ffful << PWM_DATA3_PWMx_DATAy30_16_Pos) |
PWM_T::DATA3: PWMx_DATAy30_16 Mask
Definition at line 6237 of file Nano100Series.h.
| #define PWM_DATA3_PWMx_DATAy30_16_Pos (16) |
PWM_T::DATA3: PWMx_DATAy30_16 Position
Definition at line 6236 of file Nano100Series.h.
| #define PWM_DATA3_sync_Msk (0x1ul << PWM_DATA3_sync_Pos) |
PWM_T::DATA3: sync Mask
Definition at line 6240 of file Nano100Series.h.
| #define PWM_DATA3_sync_Pos (31) |
PWM_T::DATA3: sync Position
Definition at line 6239 of file Nano100Series.h.
| #define PWM_DUTY0_CM_Msk (0xfffful << PWM_DUTY0_CM_Pos) |
PWM_T::DUTY0: CM Mask
Definition at line 6186 of file Nano100Series.h.
| #define PWM_DUTY0_CM_Pos (16) |
PWM_T::DUTY0: CM Position
Definition at line 6185 of file Nano100Series.h.
| #define PWM_DUTY0_CN_Msk (0xfffful << PWM_DUTY0_CN_Pos) |
PWM_T::DUTY0: CN Mask
Definition at line 6183 of file Nano100Series.h.
| #define PWM_DUTY0_CN_Pos (0) |
PWM_T::DUTY0: CN Position
Definition at line 6182 of file Nano100Series.h.
| #define PWM_DUTY1_CM_Msk (0xfffful << PWM_DUTY1_CM_Pos) |
PWM_T::DUTY1: CM Mask
Definition at line 6201 of file Nano100Series.h.
| #define PWM_DUTY1_CM_Pos (16) |
PWM_T::DUTY1: CM Position
Definition at line 6200 of file Nano100Series.h.
| #define PWM_DUTY1_CN_Msk (0xfffful << PWM_DUTY1_CN_Pos) |
PWM_T::DUTY1: CN Mask
Definition at line 6198 of file Nano100Series.h.
| #define PWM_DUTY1_CN_Pos (0) |
PWM_T::DUTY1: CN Position
Definition at line 6197 of file Nano100Series.h.
| #define PWM_DUTY2_CM_Msk (0xfffful << PWM_DUTY2_CM_Pos) |
PWM_T::DUTY2: CM Mask
Definition at line 6216 of file Nano100Series.h.
| #define PWM_DUTY2_CM_Pos (16) |
PWM_T::DUTY2: CM Position
Definition at line 6215 of file Nano100Series.h.
| #define PWM_DUTY2_CN_Msk (0xfffful << PWM_DUTY2_CN_Pos) |
PWM_T::DUTY2: CN Mask
Definition at line 6213 of file Nano100Series.h.
| #define PWM_DUTY2_CN_Pos (0) |
PWM_T::DUTY2: CN Position
Definition at line 6212 of file Nano100Series.h.
| #define PWM_DUTY3_CM_Msk (0xfffful << PWM_DUTY3_CM_Pos) |
PWM_T::DUTY3: CM Mask
Definition at line 6231 of file Nano100Series.h.
| #define PWM_DUTY3_CM_Pos (16) |
PWM_T::DUTY3: CM Position
Definition at line 6230 of file Nano100Series.h.
| #define PWM_DUTY3_CN_Msk (0xfffful << PWM_DUTY3_CN_Pos) |
PWM_T::DUTY3: CN Mask
Definition at line 6228 of file Nano100Series.h.
| #define PWM_DUTY3_CN_Pos (0) |
PWM_T::DUTY3: CN Position
Definition at line 6227 of file Nano100Series.h.
| #define PWM_INTEN_TMIE0_Msk (0x1ul << PWM_INTEN_TMIE0_Pos) |
PWM_T::INTEN: TMIE0 Mask
Definition at line 6132 of file Nano100Series.h.
| #define PWM_INTEN_TMIE0_Pos (0) |
PWM_T::INTEN: TMIE0 Position
Definition at line 6131 of file Nano100Series.h.
| #define PWM_INTEN_TMIE1_Msk (0x1ul << PWM_INTEN_TMIE1_Pos) |
PWM_T::INTEN: TMIE1 Mask
Definition at line 6135 of file Nano100Series.h.
| #define PWM_INTEN_TMIE1_Pos (1) |
PWM_T::INTEN: TMIE1 Position
Definition at line 6134 of file Nano100Series.h.
| #define PWM_INTEN_TMIE2_Msk (0x1ul << PWM_INTEN_TMIE2_Pos) |
PWM_T::INTEN: TMIE2 Mask
Definition at line 6138 of file Nano100Series.h.
| #define PWM_INTEN_TMIE2_Pos (2) |
PWM_T::INTEN: TMIE2 Position
Definition at line 6137 of file Nano100Series.h.
| #define PWM_INTEN_TMIE3_Msk (0x1ul << PWM_INTEN_TMIE3_Pos) |
PWM_T::INTEN: TMIE3 Mask
Definition at line 6141 of file Nano100Series.h.
| #define PWM_INTEN_TMIE3_Pos (3) |
PWM_T::INTEN: TMIE3 Position
Definition at line 6140 of file Nano100Series.h.
| #define PWM_INTSTS_Duty0Syncflag_Msk (0x1ul << PWM_INTSTS_Duty0Syncflag_Pos) |
PWM_T::INTSTS: Duty0Syncflag Mask
Definition at line 6156 of file Nano100Series.h.
| #define PWM_INTSTS_Duty0Syncflag_Pos (4) |
PWM_T::INTSTS: Duty0Syncflag Position
Definition at line 6155 of file Nano100Series.h.
| #define PWM_INTSTS_Duty1Syncflag_Msk (0x1ul << PWM_INTSTS_Duty1Syncflag_Pos) |
PWM_T::INTSTS: Duty1Syncflag Mask
Definition at line 6159 of file Nano100Series.h.
| #define PWM_INTSTS_Duty1Syncflag_Pos (5) |
PWM_T::INTSTS: Duty1Syncflag Position
Definition at line 6158 of file Nano100Series.h.
| #define PWM_INTSTS_Duty2Syncflag_Msk (0x1ul << PWM_INTSTS_Duty2Syncflag_Pos) |
PWM_T::INTSTS: Duty2Syncflag Mask
Definition at line 6162 of file Nano100Series.h.
| #define PWM_INTSTS_Duty2Syncflag_Pos (6) |
PWM_T::INTSTS: Duty2Syncflag Position
Definition at line 6161 of file Nano100Series.h.
| #define PWM_INTSTS_Duty3Syncflag_Msk (0x1ul << PWM_INTSTS_Duty3Syncflag_Pos) |
PWM_T::INTSTS: Duty3Syncflag Mask
Definition at line 6165 of file Nano100Series.h.
| #define PWM_INTSTS_Duty3Syncflag_Pos (7) |
PWM_T::INTSTS: Duty3Syncflag Position
Definition at line 6164 of file Nano100Series.h.
| #define PWM_INTSTS_PresSyncFlag_Msk (0x1ul << PWM_INTSTS_PresSyncFlag_Pos) |
PWM_T::INTSTS: PresSyncFlag Mask
Definition at line 6168 of file Nano100Series.h.
| #define PWM_INTSTS_PresSyncFlag_Pos (8) |
PWM_T::INTSTS: PresSyncFlag Position
Definition at line 6167 of file Nano100Series.h.
| #define PWM_INTSTS_TMINT0_Msk (0x1ul << PWM_INTSTS_TMINT0_Pos) |
PWM_T::INTSTS: TMINT0 Mask
Definition at line 6144 of file Nano100Series.h.
| #define PWM_INTSTS_TMINT0_Pos (0) |
PWM_T::INTSTS: TMINT0 Position
Definition at line 6143 of file Nano100Series.h.
| #define PWM_INTSTS_TMINT1_Msk (0x1ul << PWM_INTSTS_TMINT1_Pos) |
PWM_T::INTSTS: TMINT1 Mask
Definition at line 6147 of file Nano100Series.h.
| #define PWM_INTSTS_TMINT1_Pos (1) |
PWM_T::INTSTS: TMINT1 Position
Definition at line 6146 of file Nano100Series.h.
| #define PWM_INTSTS_TMINT2_Msk (0x1ul << PWM_INTSTS_TMINT2_Pos) |
PWM_T::INTSTS: TMINT2 Mask
Definition at line 6150 of file Nano100Series.h.
| #define PWM_INTSTS_TMINT2_Pos (2) |
PWM_T::INTSTS: TMINT2 Position
Definition at line 6149 of file Nano100Series.h.
| #define PWM_INTSTS_TMINT3_Msk (0x1ul << PWM_INTSTS_TMINT3_Pos) |
PWM_T::INTSTS: TMINT3 Mask
Definition at line 6153 of file Nano100Series.h.
| #define PWM_INTSTS_TMINT3_Pos (3) |
PWM_T::INTSTS: TMINT3 Position
Definition at line 6152 of file Nano100Series.h.
| #define PWM_OE_CH0_OE_Msk (0x1ul << PWM_OE_CH0_OE_Pos) |
PWM_T::OE: CH0_OE Mask
Definition at line 6171 of file Nano100Series.h.
| #define PWM_OE_CH0_OE_Pos (0) |
PWM_T::OE: CH0_OE Position
Definition at line 6170 of file Nano100Series.h.
| #define PWM_OE_CH1_OE_Msk (0x1ul << PWM_OE_CH1_OE_Pos) |
PWM_T::OE: CH1_OE Mask
Definition at line 6174 of file Nano100Series.h.
| #define PWM_OE_CH1_OE_Pos (1) |
PWM_T::OE: CH1_OE Position
Definition at line 6173 of file Nano100Series.h.
| #define PWM_OE_CH2_OE_Msk (0x1ul << PWM_OE_CH2_OE_Pos) |
PWM_T::OE: CH2_OE Mask
Definition at line 6177 of file Nano100Series.h.
| #define PWM_OE_CH2_OE_Pos (2) |
PWM_T::OE: CH2_OE Position
Definition at line 6176 of file Nano100Series.h.
| #define PWM_OE_CH3_OE_Msk (0x1ul << PWM_OE_CH3_OE_Pos) |
PWM_T::OE: CH3_OE Mask
Definition at line 6180 of file Nano100Series.h.
| #define PWM_OE_CH3_OE_Pos (3) |
PWM_T::OE: CH3_OE Position
Definition at line 6179 of file Nano100Series.h.
| #define PWM_PDMACH0_Captureddata15_8_Msk (0xfful << PWM_PDMACH0_Captureddata15_8_Pos) |
PWM_T::PDMACH0: Captureddata15_8 Mask
Definition at line 6462 of file Nano100Series.h.
| #define PWM_PDMACH0_Captureddata15_8_Pos (8) |
PWM_T::PDMACH0: Captureddata15_8 Position
Definition at line 6461 of file Nano100Series.h.
| #define PWM_PDMACH0_Captureddata23_16_Msk (0xfful << PWM_PDMACH0_Captureddata23_16_Pos) |
PWM_T::PDMACH0: Captureddata23_16 Mask
Definition at line 6465 of file Nano100Series.h.
| #define PWM_PDMACH0_Captureddata23_16_Pos (16) |
PWM_T::PDMACH0: Captureddata23_16 Position
Definition at line 6464 of file Nano100Series.h.
| #define PWM_PDMACH0_Captureddata31_24_Msk (0xfful << PWM_PDMACH0_Captureddata31_24_Pos) |
PWM_T::PDMACH0: Captureddata31_24 Mask
Definition at line 6468 of file Nano100Series.h.
| #define PWM_PDMACH0_Captureddata31_24_Pos (24) |
PWM_T::PDMACH0: Captureddata31_24 Position
Definition at line 6467 of file Nano100Series.h.
| #define PWM_PDMACH0_Captureddata7_0_Msk (0xfful << PWM_PDMACH0_Captureddata7_0_Pos) |
PWM_T::PDMACH0: Captureddata7_0 Mask
Definition at line 6459 of file Nano100Series.h.
| #define PWM_PDMACH0_Captureddata7_0_Pos (0) |
PWM_T::PDMACH0: Captureddata7_0 Position
Definition at line 6458 of file Nano100Series.h.
| #define PWM_PDMACH2_Captureddata15_8_Msk (0xfful << PWM_PDMACH2_Captureddata15_8_Pos) |
PWM_T::PDMACH2: Captureddata15_8 Mask
Definition at line 6474 of file Nano100Series.h.
| #define PWM_PDMACH2_Captureddata15_8_Pos (8) |
PWM_T::PDMACH2: Captureddata15_8 Position
Definition at line 6473 of file Nano100Series.h.
| #define PWM_PDMACH2_Captureddata23_16_Msk (0xfful << PWM_PDMACH2_Captureddata23_16_Pos) |
PWM_T::PDMACH2: Captureddata23_16 Mask
Definition at line 6477 of file Nano100Series.h.
| #define PWM_PDMACH2_Captureddata23_16_Pos (16) |
PWM_T::PDMACH2: Captureddata23_16 Position
Definition at line 6476 of file Nano100Series.h.
| #define PWM_PDMACH2_Captureddata31_24_Msk (0xfful << PWM_PDMACH2_Captureddata31_24_Pos) |
PWM_T::PDMACH2: Captureddata31_24 Mask
Definition at line 6480 of file Nano100Series.h.
| #define PWM_PDMACH2_Captureddata31_24_Pos (24) |
PWM_T::PDMACH2: Captureddata31_24 Position
Definition at line 6479 of file Nano100Series.h.
| #define PWM_PDMACH2_Captureddata7_0_Msk (0xfful << PWM_PDMACH2_Captureddata7_0_Pos) |
PWM_T::PDMACH2: Captureddata7_0 Mask
Definition at line 6471 of file Nano100Series.h.
| #define PWM_PDMACH2_Captureddata7_0_Pos (0) |
PWM_T::PDMACH2: Captureddata7_0 Position
Definition at line 6470 of file Nano100Series.h.
| #define PWM_PRES_CP01_Msk (0xfful << PWM_PRES_CP01_Pos) |
PWM_T::PRES: CP01 Mask
Definition at line 6066 of file Nano100Series.h.
| #define PWM_PRES_CP01_Pos (0) |
@addtogroup PWM_CONST PWM Bit Field Definition Constant Definitions for PWM Controller
PWM_T::PRES: CP01 Position
Definition at line 6065 of file Nano100Series.h.
| #define PWM_PRES_CP23_Msk (0xfful << PWM_PRES_CP23_Pos) |
PWM_T::PRES: CP23 Mask
Definition at line 6069 of file Nano100Series.h.
| #define PWM_PRES_CP23_Pos (8) |
PWM_T::PRES: CP23 Position
Definition at line 6068 of file Nano100Series.h.
| #define PWM_PRES_DZ01_Msk (0xfful << PWM_PRES_DZ01_Pos) |
PWM_T::PRES: DZ01 Mask
Definition at line 6072 of file Nano100Series.h.
| #define PWM_PRES_DZ01_Pos (16) |
PWM_T::PRES: DZ01 Position
Definition at line 6071 of file Nano100Series.h.
| #define PWM_PRES_DZ23_Msk (0xfful << PWM_PRES_DZ23_Pos) |
PWM_T::PRES: DZ23 Mask
Definition at line 6075 of file Nano100Series.h.
| #define PWM_PRES_DZ23_Pos (24) |
PWM_T::PRES: DZ23 Position
Definition at line 6074 of file Nano100Series.h.
| #define RTC_AER_AER_Msk (0xfffful << RTC_AER_AER_Pos) |
RTC_T::AER: AER Mask
Definition at line 6801 of file Nano100Series.h.
| #define RTC_AER_AER_Pos (0) |
RTC_T::AER: AER Position
Definition at line 6800 of file Nano100Series.h.
| #define RTC_AER_ENF_Msk (0x1ul << RTC_AER_ENF_Pos) |
RTC_T::AER: ENF Mask
Definition at line 6804 of file Nano100Series.h.
| #define RTC_AER_ENF_Pos (16) |
RTC_T::AER: ENF Position
Definition at line 6803 of file Nano100Series.h.
| #define RTC_CAR_10DAY_Msk (0x3ul << RTC_CAR_10DAY_Pos) |
RTC_T::CAR: 10DAY Mask
Definition at line 6876 of file Nano100Series.h.
| #define RTC_CAR_10DAY_Pos (4) |
RTC_T::CAR: 10DAY Position
Definition at line 6875 of file Nano100Series.h.
| #define RTC_CAR_10MON_Msk (0x1ul << RTC_CAR_10MON_Pos) |
RTC_T::CAR: 10MON Mask
Definition at line 6882 of file Nano100Series.h.
| #define RTC_CAR_10MON_Pos (12) |
RTC_T::CAR: 10MON Position
Definition at line 6881 of file Nano100Series.h.
| #define RTC_CAR_10YEAR_Msk (0xful << RTC_CAR_10YEAR_Pos) |
RTC_T::CAR: 10YEAR Mask
Definition at line 6888 of file Nano100Series.h.
| #define RTC_CAR_10YEAR_Pos (20) |
RTC_T::CAR: 10YEAR Position
Definition at line 6887 of file Nano100Series.h.
| #define RTC_CAR_1DAY_Msk (0xful << RTC_CAR_1DAY_Pos) |
RTC_T::CAR: 1DAY Mask
Definition at line 6873 of file Nano100Series.h.
| #define RTC_CAR_1DAY_Pos (0) |
RTC_T::CAR: 1DAY Position
Definition at line 6872 of file Nano100Series.h.
| #define RTC_CAR_1MON_Msk (0xful << RTC_CAR_1MON_Pos) |
RTC_T::CAR: 1MON Mask
Definition at line 6879 of file Nano100Series.h.
| #define RTC_CAR_1MON_Pos (8) |
RTC_T::CAR: 1MON Position
Definition at line 6878 of file Nano100Series.h.
| #define RTC_CAR_1YEAR_Msk (0xful << RTC_CAR_1YEAR_Pos) |
RTC_T::CAR: 1YEAR Mask
Definition at line 6885 of file Nano100Series.h.
| #define RTC_CAR_1YEAR_Pos (16) |
RTC_T::CAR: 1YEAR Position
Definition at line 6884 of file Nano100Series.h.
| #define RTC_CLR_10DAY_Msk (0x3ul << RTC_CLR_10DAY_Pos) |
RTC_T::CLR: 10DAY Mask
Definition at line 6834 of file Nano100Series.h.
| #define RTC_CLR_10DAY_Pos (4) |
RTC_T::CLR: 10DAY Position
Definition at line 6833 of file Nano100Series.h.
| #define RTC_CLR_10MON_Msk (0x1ul << RTC_CLR_10MON_Pos) |
RTC_T::CLR: 10MON Mask
Definition at line 6840 of file Nano100Series.h.
| #define RTC_CLR_10MON_Pos (12) |
RTC_T::CLR: 10MON Position
Definition at line 6839 of file Nano100Series.h.
| #define RTC_CLR_10YEAR_Msk (0xful << RTC_CLR_10YEAR_Pos) |
RTC_T::CLR: 10YEAR Mask
Definition at line 6846 of file Nano100Series.h.
| #define RTC_CLR_10YEAR_Pos (20) |
RTC_T::CLR: 10YEAR Position
Definition at line 6845 of file Nano100Series.h.
| #define RTC_CLR_1DAY_Msk (0xful << RTC_CLR_1DAY_Pos) |
RTC_T::CLR: 1DAY Mask
Definition at line 6831 of file Nano100Series.h.
| #define RTC_CLR_1DAY_Pos (0) |
RTC_T::CLR: 1DAY Position
Definition at line 6830 of file Nano100Series.h.
| #define RTC_CLR_1MON_Msk (0xful << RTC_CLR_1MON_Pos) |
RTC_T::CLR: 1MON Mask
Definition at line 6837 of file Nano100Series.h.
| #define RTC_CLR_1MON_Pos (8) |
RTC_T::CLR: 1MON Position
Definition at line 6836 of file Nano100Series.h.
| #define RTC_CLR_1YEAR_Msk (0xful << RTC_CLR_1YEAR_Pos) |
RTC_T::CLR: 1YEAR Mask
Definition at line 6843 of file Nano100Series.h.
| #define RTC_CLR_1YEAR_Pos (16) |
RTC_T::CLR: 1YEAR Position
Definition at line 6842 of file Nano100Series.h.
| #define RTC_DWR_DWR_Msk (0x7ul << RTC_DWR_DWR_Pos) |
RTC_T::DWR: DWR Mask
Definition at line 6852 of file Nano100Series.h.
| #define RTC_DWR_DWR_Pos (0) |
RTC_T::DWR: DWR Position
Definition at line 6851 of file Nano100Series.h.
| #define RTC_FCR_FRACTION_Msk (0x3ful << RTC_FCR_FRACTION_Pos) |
RTC_T::FCR: FRACTION Mask
Definition at line 6807 of file Nano100Series.h.
| #define RTC_FCR_FRACTION_Pos (0) |
RTC_T::FCR: FRACTION Position
Definition at line 6806 of file Nano100Series.h.
| #define RTC_FCR_INTEGER_Msk (0xful << RTC_FCR_INTEGER_Pos) |
RTC_T::FCR: INTEGER Mask
Definition at line 6810 of file Nano100Series.h.
| #define RTC_FCR_INTEGER_Pos (8) |
RTC_T::FCR: INTEGER Position
Definition at line 6809 of file Nano100Series.h.
| #define RTC_INIR_ACTIVE_Msk (0x1ul << RTC_INIR_ACTIVE_Pos) |
RTC_T::INIR: ACTIVE Mask
Definition at line 6795 of file Nano100Series.h.
| #define RTC_INIR_ACTIVE_Pos (0) |
@addtogroup RTC_CONST RTC Bit Field Definition Constant Definitions for RTC Controller
RTC_T::INIR: ACTIVE Position
Definition at line 6794 of file Nano100Series.h.
| #define RTC_INIR_INIR_Msk (0xfffffffful << RTC_INIR_INIR_Pos) |
RTC_T::INIR: INIR Mask
Definition at line 6798 of file Nano100Series.h.
| #define RTC_INIR_INIR_Pos (0) |
RTC_T::INIR: INIR Position
Definition at line 6797 of file Nano100Series.h.
| #define RTC_LIR_LIR_Msk (0x1ul << RTC_LIR_LIR_Pos) |
RTC_T::LIR: LIR Mask
Definition at line 6891 of file Nano100Series.h.
| #define RTC_LIR_LIR_Pos (0) |
RTC_T::LIR: LIR Position
Definition at line 6890 of file Nano100Series.h.
| #define RTC_RIER_AIER_Msk (0x1ul << RTC_RIER_AIER_Pos) |
RTC_T::RIER: AIER Mask
Definition at line 6894 of file Nano100Series.h.
| #define RTC_RIER_AIER_Pos (0) |
RTC_T::RIER: AIER Position
Definition at line 6893 of file Nano100Series.h.
| #define RTC_RIER_SNOOPIER_Msk (0x1ul << RTC_RIER_SNOOPIER_Pos) |
RTC_T::RIER: SNOOPIER Mask
Definition at line 6900 of file Nano100Series.h.
| #define RTC_RIER_SNOOPIER_Pos (2) |
RTC_T::RIER: SNOOPIER Position
Definition at line 6899 of file Nano100Series.h.
| #define RTC_RIER_TIER_Msk (0x1ul << RTC_RIER_TIER_Pos) |
RTC_T::RIER: TIER Mask
Definition at line 6897 of file Nano100Series.h.
| #define RTC_RIER_TIER_Pos (1) |
RTC_T::RIER: TIER Position
Definition at line 6896 of file Nano100Series.h.
| #define RTC_RIIR_AIF_Msk (0x1ul << RTC_RIIR_AIF_Pos) |
RTC_T::RIIR: AIF Mask
Definition at line 6903 of file Nano100Series.h.
| #define RTC_RIIR_AIF_Pos (0) |
RTC_T::RIIR: AIF Position
Definition at line 6902 of file Nano100Series.h.
| #define RTC_RIIR_SNOOPIF_Msk (0x1ul << RTC_RIIR_SNOOPIF_Pos) |
RTC_T::RIIR: SNOOPIF Mask
Definition at line 6909 of file Nano100Series.h.
| #define RTC_RIIR_SNOOPIF_Pos (2) |
RTC_T::RIIR: SNOOPIF Position
Definition at line 6908 of file Nano100Series.h.
| #define RTC_RIIR_TIF_Msk (0x1ul << RTC_RIIR_TIF_Pos) |
RTC_T::RIIR: TIF Mask
Definition at line 6906 of file Nano100Series.h.
| #define RTC_RIIR_TIF_Pos (1) |
RTC_T::RIIR: TIF Position
Definition at line 6905 of file Nano100Series.h.
| #define RTC_SPR0_SPARE_Msk (0xfffffffful << RTC_SPR0_SPARE_Pos) |
RTC_T::SPR0: SPARE Mask
Definition at line 6927 of file Nano100Series.h.
| #define RTC_SPR0_SPARE_Pos (0) |
RTC_T::SPR0: SPARE Position
Definition at line 6926 of file Nano100Series.h.
| #define RTC_SPR10_SPARE_Msk (0xfffffffful << RTC_SPR10_SPARE_Pos) |
RTC_T::SPR10: SPARE Mask
Definition at line 6957 of file Nano100Series.h.
| #define RTC_SPR10_SPARE_Pos (0) |
RTC_T::SPR10: SPARE Position
Definition at line 6956 of file Nano100Series.h.
| #define RTC_SPR11_SPARE_Msk (0xfffffffful << RTC_SPR11_SPARE_Pos) |
RTC_T::SPR11: SPARE Mask
Definition at line 6960 of file Nano100Series.h.
| #define RTC_SPR11_SPARE_Pos (0) |
RTC_T::SPR11: SPARE Position
Definition at line 6959 of file Nano100Series.h.
| #define RTC_SPR12_SPARE_Msk (0xfffffffful << RTC_SPR12_SPARE_Pos) |
RTC_T::SPR12: SPARE Mask
Definition at line 6963 of file Nano100Series.h.
| #define RTC_SPR12_SPARE_Pos (0) |
RTC_T::SPR12: SPARE Position
Definition at line 6962 of file Nano100Series.h.
| #define RTC_SPR13_SPARE_Msk (0xfffffffful << RTC_SPR13_SPARE_Pos) |
RTC_T::SPR13: SPARE Mask
Definition at line 6966 of file Nano100Series.h.
| #define RTC_SPR13_SPARE_Pos (0) |
RTC_T::SPR13: SPARE Position
Definition at line 6965 of file Nano100Series.h.
| #define RTC_SPR14_SPARE_Msk (0xfffffffful << RTC_SPR14_SPARE_Pos) |
RTC_T::SPR14: SPARE Mask
Definition at line 6969 of file Nano100Series.h.
| #define RTC_SPR14_SPARE_Pos (0) |
RTC_T::SPR14: SPARE Position
Definition at line 6968 of file Nano100Series.h.
| #define RTC_SPR15_SPARE_Msk (0xfffffffful << RTC_SPR15_SPARE_Pos) |
RTC_T::SPR15: SPARE Mask
Definition at line 6972 of file Nano100Series.h.
| #define RTC_SPR15_SPARE_Pos (0) |
RTC_T::SPR15: SPARE Position
Definition at line 6971 of file Nano100Series.h.
| #define RTC_SPR16_SPARE_Msk (0xfffffffful << RTC_SPR16_SPARE_Pos) |
RTC_T::SPR16: SPARE Mask
Definition at line 6975 of file Nano100Series.h.
| #define RTC_SPR16_SPARE_Pos (0) |
RTC_T::SPR16: SPARE Position
Definition at line 6974 of file Nano100Series.h.
| #define RTC_SPR17_SPARE_Msk (0xfffffffful << RTC_SPR17_SPARE_Pos) |
RTC_T::SPR17: SPARE Mask
Definition at line 6978 of file Nano100Series.h.
| #define RTC_SPR17_SPARE_Pos (0) |
RTC_T::SPR17: SPARE Position
Definition at line 6977 of file Nano100Series.h.
| #define RTC_SPR18_SPARE_Msk (0xfffffffful << RTC_SPR18_SPARE_Pos) |
RTC_T::SPR18: SPARE Mask
Definition at line 6981 of file Nano100Series.h.
| #define RTC_SPR18_SPARE_Pos (0) |
RTC_T::SPR18: SPARE Position
Definition at line 6980 of file Nano100Series.h.
| #define RTC_SPR19_SPARE_Msk (0xfffffffful << RTC_SPR19_SPARE_Pos) |
RTC_T::SPR19: SPARE Mask
Definition at line 6984 of file Nano100Series.h.
| #define RTC_SPR19_SPARE_Pos (0) |
RTC_T::SPR19: SPARE Position
Definition at line 6983 of file Nano100Series.h.
| #define RTC_SPR1_SPARE_Msk (0xfffffffful << RTC_SPR1_SPARE_Pos) |
RTC_T::SPR1: SPARE Mask
Definition at line 6930 of file Nano100Series.h.
| #define RTC_SPR1_SPARE_Pos (0) |
RTC_T::SPR1: SPARE Position
Definition at line 6929 of file Nano100Series.h.
| #define RTC_SPR2_SPARE_Msk (0xfffffffful << RTC_SPR2_SPARE_Pos) |
RTC_T::SPR2: SPARE Mask
Definition at line 6933 of file Nano100Series.h.
| #define RTC_SPR2_SPARE_Pos (0) |
RTC_T::SPR2: SPARE Position
Definition at line 6932 of file Nano100Series.h.
| #define RTC_SPR3_SPARE_Msk (0xfffffffful << RTC_SPR3_SPARE_Pos) |
RTC_T::SPR3: SPARE Mask
Definition at line 6936 of file Nano100Series.h.
| #define RTC_SPR3_SPARE_Pos (0) |
RTC_T::SPR3: SPARE Position
Definition at line 6935 of file Nano100Series.h.
| #define RTC_SPR4_SPARE_Msk (0xfffffffful << RTC_SPR4_SPARE_Pos) |
RTC_T::SPR4: SPARE Mask
Definition at line 6939 of file Nano100Series.h.
| #define RTC_SPR4_SPARE_Pos (0) |
RTC_T::SPR4: SPARE Position
Definition at line 6938 of file Nano100Series.h.
| #define RTC_SPR5_SPARE_Msk (0xfffffffful << RTC_SPR5_SPARE_Pos) |
RTC_T::SPR5: SPARE Mask
Definition at line 6942 of file Nano100Series.h.
| #define RTC_SPR5_SPARE_Pos (0) |
RTC_T::SPR5: SPARE Position
Definition at line 6941 of file Nano100Series.h.
| #define RTC_SPR6_SPARE_Msk (0xfffffffful << RTC_SPR6_SPARE_Pos) |
RTC_T::SPR6: SPARE Mask
Definition at line 6945 of file Nano100Series.h.
| #define RTC_SPR6_SPARE_Pos (0) |
RTC_T::SPR6: SPARE Position
Definition at line 6944 of file Nano100Series.h.
| #define RTC_SPR7_SPARE_Msk (0xfffffffful << RTC_SPR7_SPARE_Pos) |
RTC_T::SPR7: SPARE Mask
Definition at line 6948 of file Nano100Series.h.
| #define RTC_SPR7_SPARE_Pos (0) |
RTC_T::SPR7: SPARE Position
Definition at line 6947 of file Nano100Series.h.
| #define RTC_SPR8_SPARE_Msk (0xfffffffful << RTC_SPR8_SPARE_Pos) |
RTC_T::SPR8: SPARE Mask
Definition at line 6951 of file Nano100Series.h.
| #define RTC_SPR8_SPARE_Pos (0) |
RTC_T::SPR8: SPARE Position
Definition at line 6950 of file Nano100Series.h.
| #define RTC_SPR9_SPARE_Msk (0xfffffffful << RTC_SPR9_SPARE_Pos) |
RTC_T::SPR9: SPARE Mask
Definition at line 6954 of file Nano100Series.h.
| #define RTC_SPR9_SPARE_Pos (0) |
RTC_T::SPR9: SPARE Position
Definition at line 6953 of file Nano100Series.h.
| #define RTC_SPRCTL_SNOOPEDGE_Msk (0x1ul << RTC_SPRCTL_SNOOPEDGE_Pos) |
RTC_T::SPRCTL: SNOOPEDGE Mask
Definition at line 6921 of file Nano100Series.h.
| #define RTC_SPRCTL_SNOOPEDGE_Pos (1) |
RTC_T::SPRCTL: SNOOPEDGE Position
Definition at line 6920 of file Nano100Series.h.
| #define RTC_SPRCTL_SNOOPEN_Msk (0x1ul << RTC_SPRCTL_SNOOPEN_Pos) |
RTC_T::SPRCTL: SNOOPEN Mask
Definition at line 6918 of file Nano100Series.h.
| #define RTC_SPRCTL_SNOOPEN_Pos (0) |
RTC_T::SPRCTL: SNOOPEN Position
Definition at line 6917 of file Nano100Series.h.
| #define RTC_SPRCTL_SPRRDY_Msk (0x1ul << RTC_SPRCTL_SPRRDY_Pos) |
RTC_T::SPRCTL: SPRRDY Mask
Definition at line 6924 of file Nano100Series.h.
| #define RTC_SPRCTL_SPRRDY_Pos (7) |
RTC_T::SPRCTL: SPRRDY Position
Definition at line 6923 of file Nano100Series.h.
| #define RTC_TAR_10HR_Msk (0x3ul << RTC_TAR_10HR_Pos) |
RTC_T::TAR: 10HR Mask
Definition at line 6870 of file Nano100Series.h.
| #define RTC_TAR_10HR_Pos (20) |
RTC_T::TAR: 10HR Position
Definition at line 6869 of file Nano100Series.h.
| #define RTC_TAR_10MIN_Msk (0x7ul << RTC_TAR_10MIN_Pos) |
RTC_T::TAR: 10MIN Mask
Definition at line 6864 of file Nano100Series.h.
| #define RTC_TAR_10MIN_Pos (12) |
RTC_T::TAR: 10MIN Position
Definition at line 6863 of file Nano100Series.h.
| #define RTC_TAR_10SEC_Msk (0x7ul << RTC_TAR_10SEC_Pos) |
RTC_T::TAR: 10SEC Mask
Definition at line 6858 of file Nano100Series.h.
| #define RTC_TAR_10SEC_Pos (4) |
RTC_T::TAR: 10SEC Position
Definition at line 6857 of file Nano100Series.h.
| #define RTC_TAR_1HR_Msk (0xful << RTC_TAR_1HR_Pos) |
RTC_T::TAR: 1HR Mask
Definition at line 6867 of file Nano100Series.h.
| #define RTC_TAR_1HR_Pos (16) |
RTC_T::TAR: 1HR Position
Definition at line 6866 of file Nano100Series.h.
| #define RTC_TAR_1MIN_Msk (0xful << RTC_TAR_1MIN_Pos) |
RTC_T::TAR: 1MIN Mask
Definition at line 6861 of file Nano100Series.h.
| #define RTC_TAR_1MIN_Pos (8) |
RTC_T::TAR: 1MIN Position
Definition at line 6860 of file Nano100Series.h.
| #define RTC_TAR_1SEC_Msk (0xful << RTC_TAR_1SEC_Pos) |
RTC_T::TAR: 1SEC Mask
Definition at line 6855 of file Nano100Series.h.
| #define RTC_TAR_1SEC_Pos (0) |
RTC_T::TAR: 1SEC Position
Definition at line 6854 of file Nano100Series.h.
| #define RTC_TLR_10HR_Msk (0x3ul << RTC_TLR_10HR_Pos) |
RTC_T::TLR: 10HR Mask
Definition at line 6828 of file Nano100Series.h.
| #define RTC_TLR_10HR_Pos (20) |
RTC_T::TLR: 10HR Position
Definition at line 6827 of file Nano100Series.h.
| #define RTC_TLR_10MIN_Msk (0x7ul << RTC_TLR_10MIN_Pos) |
RTC_T::TLR: 10MIN Mask
Definition at line 6822 of file Nano100Series.h.
| #define RTC_TLR_10MIN_Pos (12) |
RTC_T::TLR: 10MIN Position
Definition at line 6821 of file Nano100Series.h.
| #define RTC_TLR_10SEC_Msk (0x7ul << RTC_TLR_10SEC_Pos) |
RTC_T::TLR: 10SEC Mask
Definition at line 6816 of file Nano100Series.h.
| #define RTC_TLR_10SEC_Pos (4) |
RTC_T::TLR: 10SEC Position
Definition at line 6815 of file Nano100Series.h.
| #define RTC_TLR_1HR_Msk (0xful << RTC_TLR_1HR_Pos) |
RTC_T::TLR: 1HR Mask
Definition at line 6825 of file Nano100Series.h.
| #define RTC_TLR_1HR_Pos (16) |
RTC_T::TLR: 1HR Position
Definition at line 6824 of file Nano100Series.h.
| #define RTC_TLR_1MIN_Msk (0xful << RTC_TLR_1MIN_Pos) |
RTC_T::TLR: 1MIN Mask
Definition at line 6819 of file Nano100Series.h.
| #define RTC_TLR_1MIN_Pos (8) |
RTC_T::TLR: 1MIN Position
Definition at line 6818 of file Nano100Series.h.
| #define RTC_TLR_1SEC_Msk (0xful << RTC_TLR_1SEC_Pos) |
RTC_T::TLR: 1SEC Mask
Definition at line 6813 of file Nano100Series.h.
| #define RTC_TLR_1SEC_Pos (0) |
RTC_T::TLR: 1SEC Position
Definition at line 6812 of file Nano100Series.h.
| #define RTC_TSSR_24H_12H_Msk (0x1ul << RTC_TSSR_24H_12H_Pos) |
RTC_T::TSSR: 24H_12H Mask
Definition at line 6849 of file Nano100Series.h.
| #define RTC_TSSR_24H_12H_Pos (0) |
RTC_T::TSSR: 24H_12H Position
Definition at line 6848 of file Nano100Series.h.
| #define RTC_TTR_TTR_Msk (0x7ul << RTC_TTR_TTR_Pos) |
RTC_T::TTR: TTR Mask
Definition at line 6912 of file Nano100Series.h.
| #define RTC_TTR_TTR_Pos (0) |
RTC_T::TTR: TTR Position
Definition at line 6911 of file Nano100Series.h.
| #define RTC_TTR_TWKE_Msk (0x1ul << RTC_TTR_TWKE_Pos) |
RTC_T::TTR: TWKE Mask
Definition at line 6915 of file Nano100Series.h.
| #define RTC_TTR_TWKE_Pos (3) |
RTC_T::TTR: TWKE Position
Definition at line 6914 of file Nano100Series.h.
| #define SC_ALTCTL_ACT_EN_Msk (0x1ul << SC_ALTCTL_ACT_EN_Pos) |
SC_T::ALTCTL: ACT_EN Mask
Definition at line 7640 of file Nano100Series.h.
| #define SC_ALTCTL_ACT_EN_Pos (3) |
SC_T::ALTCTL: ACT_EN Position
Definition at line 7639 of file Nano100Series.h.
| #define SC_ALTCTL_DACT_EN_Msk (0x1ul << SC_ALTCTL_DACT_EN_Pos) |
SC_T::ALTCTL: DACT_EN Mask
Definition at line 7637 of file Nano100Series.h.
| #define SC_ALTCTL_DACT_EN_Pos (2) |
SC_T::ALTCTL: DACT_EN Position
Definition at line 7636 of file Nano100Series.h.
| #define SC_ALTCTL_INIT_SEL_Msk (0x3ul << SC_ALTCTL_INIT_SEL_Pos) |
SC_T::ALTCTL: INIT_SEL Mask
Definition at line 7655 of file Nano100Series.h.
| #define SC_ALTCTL_INIT_SEL_Pos (8) |
SC_T::ALTCTL: INIT_SEL Position
Definition at line 7654 of file Nano100Series.h.
| #define SC_ALTCTL_RX_BGT_EN_Msk (0x1ul << SC_ALTCTL_RX_BGT_EN_Pos) |
SC_T::ALTCTL: RX_BGT_EN Mask
Definition at line 7658 of file Nano100Series.h.
| #define SC_ALTCTL_RX_BGT_EN_Pos (12) |
SC_T::ALTCTL: RX_BGT_EN Position
Definition at line 7657 of file Nano100Series.h.
| #define SC_ALTCTL_RX_RST_Msk (0x1ul << SC_ALTCTL_RX_RST_Pos) |
SC_T::ALTCTL: RX_RST Mask
Definition at line 7634 of file Nano100Series.h.
| #define SC_ALTCTL_RX_RST_Pos (1) |
SC_T::ALTCTL: RX_RST Position
Definition at line 7633 of file Nano100Series.h.
| #define SC_ALTCTL_TMR0_ATV_Msk (0x1ul << SC_ALTCTL_TMR0_ATV_Pos) |
SC_T::ALTCTL: TMR0_ATV Mask
Definition at line 7661 of file Nano100Series.h.
| #define SC_ALTCTL_TMR0_ATV_Pos (13) |
SC_T::ALTCTL: TMR0_ATV Position
Definition at line 7660 of file Nano100Series.h.
| #define SC_ALTCTL_TMR0_SEN_Msk (0x1ul << SC_ALTCTL_TMR0_SEN_Pos) |
SC_T::ALTCTL: TMR0_SEN Mask
Definition at line 7646 of file Nano100Series.h.
| #define SC_ALTCTL_TMR0_SEN_Pos (5) |
SC_T::ALTCTL: TMR0_SEN Position
Definition at line 7645 of file Nano100Series.h.
| #define SC_ALTCTL_TMR1_ATV_Msk (0x1ul << SC_ALTCTL_TMR1_ATV_Pos) |
SC_T::ALTCTL: TMR1_ATV Mask
Definition at line 7664 of file Nano100Series.h.
| #define SC_ALTCTL_TMR1_ATV_Pos (14) |
SC_T::ALTCTL: TMR1_ATV Position
Definition at line 7663 of file Nano100Series.h.
| #define SC_ALTCTL_TMR1_SEN_Msk (0x1ul << SC_ALTCTL_TMR1_SEN_Pos) |
SC_T::ALTCTL: TMR1_SEN Mask
Definition at line 7649 of file Nano100Series.h.
| #define SC_ALTCTL_TMR1_SEN_Pos (6) |
SC_T::ALTCTL: TMR1_SEN Position
Definition at line 7648 of file Nano100Series.h.
| #define SC_ALTCTL_TMR2_ATV_Msk (0x1ul << SC_ALTCTL_TMR2_ATV_Pos) |
SC_T::ALTCTL: TMR2_ATV Mask
Definition at line 7667 of file Nano100Series.h.
| #define SC_ALTCTL_TMR2_ATV_Pos (15) |
SC_T::ALTCTL: TMR2_ATV Position
Definition at line 7666 of file Nano100Series.h.
| #define SC_ALTCTL_TMR2_SEN_Msk (0x1ul << SC_ALTCTL_TMR2_SEN_Pos) |
SC_T::ALTCTL: TMR2_SEN Mask
Definition at line 7652 of file Nano100Series.h.
| #define SC_ALTCTL_TMR2_SEN_Pos (7) |
SC_T::ALTCTL: TMR2_SEN Position
Definition at line 7651 of file Nano100Series.h.
| #define SC_ALTCTL_TX_RST_Msk (0x1ul << SC_ALTCTL_TX_RST_Pos) |
SC_T::ALTCTL: TX_RST Mask
Definition at line 7631 of file Nano100Series.h.
| #define SC_ALTCTL_TX_RST_Pos (0) |
SC_T::ALTCTL: TX_RST Position
Definition at line 7630 of file Nano100Series.h.
| #define SC_ALTCTL_WARST_EN_Msk (0x1ul << SC_ALTCTL_WARST_EN_Pos) |
SC_T::ALTCTL: WARST_EN Mask
Definition at line 7643 of file Nano100Series.h.
| #define SC_ALTCTL_WARST_EN_Pos (4) |
SC_T::ALTCTL: WARST_EN Position
Definition at line 7642 of file Nano100Series.h.
| #define SC_CTL_AUTO_CON_EN_Msk (0x1ul << SC_CTL_AUTO_CON_EN_Pos) |
SC_T::CTL: AUTO_CON_EN Mask
Definition at line 7598 of file Nano100Series.h.
| #define SC_CTL_AUTO_CON_EN_Pos (3) |
SC_T::CTL: AUTO_CON_EN Position
Definition at line 7597 of file Nano100Series.h.
| #define SC_CTL_BGT_Msk (0x1ful << SC_CTL_BGT_Pos) |
SC_T::CTL: BGT Mask
Definition at line 7607 of file Nano100Series.h.
| #define SC_CTL_BGT_Pos (8) |
SC_T::CTL: BGT Position
Definition at line 7606 of file Nano100Series.h.
| #define SC_CTL_CD_DEB_SEL_Msk (0x3ul << SC_CTL_CD_DEB_SEL_Pos) |
SC_T::CTL: CD_DEB_SEL Mask
Definition at line 7628 of file Nano100Series.h.
| #define SC_CTL_CD_DEB_SEL_Pos (24) |
SC_T::CTL: CD_DEB_SEL Position
Definition at line 7627 of file Nano100Series.h.
| #define SC_CTL_CON_SEL_Msk (0x3ul << SC_CTL_CON_SEL_Pos) |
SC_T::CTL: CON_SEL Mask
Definition at line 7601 of file Nano100Series.h.
| #define SC_CTL_CON_SEL_Pos (4) |
SC_T::CTL: CON_SEL Position
Definition at line 7600 of file Nano100Series.h.
| #define SC_CTL_DIS_RX_Msk (0x1ul << SC_CTL_DIS_RX_Pos) |
SC_T::CTL: DIS_RX Mask
Definition at line 7592 of file Nano100Series.h.
| #define SC_CTL_DIS_RX_Pos (1) |
SC_T::CTL: DIS_RX Position
Definition at line 7591 of file Nano100Series.h.
| #define SC_CTL_DIS_TX_Msk (0x1ul << SC_CTL_DIS_TX_Pos) |
SC_T::CTL: DIS_TX Mask
Definition at line 7595 of file Nano100Series.h.
| #define SC_CTL_DIS_TX_Pos (2) |
SC_T::CTL: DIS_TX Position
Definition at line 7594 of file Nano100Series.h.
| #define SC_CTL_RX_ERETRY_EN_Msk (0x1ul << SC_CTL_RX_ERETRY_EN_Pos) |
SC_T::CTL: RX_ERETRY_EN Mask
Definition at line 7619 of file Nano100Series.h.
| #define SC_CTL_RX_ERETRY_EN_Pos (19) |
SC_T::CTL: RX_ERETRY_EN Position
Definition at line 7618 of file Nano100Series.h.
| #define SC_CTL_RX_ERETRY_Msk (0x7ul << SC_CTL_RX_ERETRY_Pos) |
SC_T::CTL: RX_ERETRY Mask
Definition at line 7616 of file Nano100Series.h.
| #define SC_CTL_RX_ERETRY_Pos (16) |
SC_T::CTL: RX_ERETRY Position
Definition at line 7615 of file Nano100Series.h.
| #define SC_CTL_RX_FTRI_LEV_Msk (0x3ul << SC_CTL_RX_FTRI_LEV_Pos) |
SC_T::CTL: RX_FTRI_LEV Mask
Definition at line 7604 of file Nano100Series.h.
| #define SC_CTL_RX_FTRI_LEV_Pos (6) |
SC_T::CTL: RX_FTRI_LEV Position
Definition at line 7603 of file Nano100Series.h.
| #define SC_CTL_SC_CEN_Msk (0x1ul << SC_CTL_SC_CEN_Pos) |
SC_T::CTL: SC_CEN Mask
Definition at line 7589 of file Nano100Series.h.
| #define SC_CTL_SC_CEN_Pos (0) |
SC_T::CTL: SC_CEN Position
Definition at line 7588 of file Nano100Series.h.
| #define SC_CTL_SLEN_Msk (0x1ul << SC_CTL_SLEN_Pos) |
SC_T::CTL: SLEN Mask
Definition at line 7613 of file Nano100Series.h.
| #define SC_CTL_SLEN_Pos (15) |
SC_T::CTL: SLEN Position
Definition at line 7612 of file Nano100Series.h.
| #define SC_CTL_TMR_SEL_Msk (0x3ul << SC_CTL_TMR_SEL_Pos) |
SC_T::CTL: TMR_SEL Mask
Definition at line 7610 of file Nano100Series.h.
| #define SC_CTL_TMR_SEL_Pos (13) |
SC_T::CTL: TMR_SEL Position
Definition at line 7609 of file Nano100Series.h.
| #define SC_CTL_TX_ERETRY_EN_Msk (0x1ul << SC_CTL_TX_ERETRY_EN_Pos) |
SC_T::CTL: TX_ERETRY_EN Mask
Definition at line 7625 of file Nano100Series.h.
| #define SC_CTL_TX_ERETRY_EN_Pos (23) |
SC_T::CTL: TX_ERETRY_EN Position
Definition at line 7624 of file Nano100Series.h.
| #define SC_CTL_TX_ERETRY_Msk (0x7ul << SC_CTL_TX_ERETRY_Pos) |
SC_T::CTL: TX_ERETRY Mask
Definition at line 7622 of file Nano100Series.h.
| #define SC_CTL_TX_ERETRY_Pos (20) |
SC_T::CTL: TX_ERETRY Position
Definition at line 7621 of file Nano100Series.h.
| #define SC_DAT_DAT_Msk (0xfful << SC_DAT_DAT_Pos) |
SC_T::DAT: DAT Mask
Definition at line 7586 of file Nano100Series.h.
| #define SC_DAT_DAT_Pos (0) |
@addtogroup SC_CONST SC Bit Field Definition Constant Definitions for SC Controller
SC_T::DAT: DAT Position
Definition at line 7585 of file Nano100Series.h.
| #define SC_EGTR_EGT_Msk (0xfful << SC_EGTR_EGT_Pos) |
SC_T::EGTR: EGT Mask
Definition at line 7670 of file Nano100Series.h.
| #define SC_EGTR_EGT_Pos (0) |
SC_T::EGTR: EGT Position
Definition at line 7669 of file Nano100Series.h.
| #define SC_ETUCR_COMPEN_EN_Msk (0x1ul << SC_ETUCR_COMPEN_EN_Pos) |
SC_T::ETUCR: COMPEN_EN Mask
Definition at line 7679 of file Nano100Series.h.
| #define SC_ETUCR_COMPEN_EN_Pos (15) |
SC_T::ETUCR: COMPEN_EN Position
Definition at line 7678 of file Nano100Series.h.
| #define SC_ETUCR_ETU_RDIV_Msk (0xffful << SC_ETUCR_ETU_RDIV_Pos) |
SC_T::ETUCR: ETU_RDIV Mask
Definition at line 7676 of file Nano100Series.h.
| #define SC_ETUCR_ETU_RDIV_Pos (0) |
SC_T::ETUCR: ETU_RDIV Position
Definition at line 7675 of file Nano100Series.h.
| #define SC_IER_ACON_ERR_IE_Msk (0x1ul << SC_IER_ACON_ERR_IE_Pos) |
SC_T::IER: ACON_ERR_IE Mask
Definition at line 7712 of file Nano100Series.h.
| #define SC_IER_ACON_ERR_IE_Pos (10) |
SC_T::IER: ACON_ERR_IE Position
Definition at line 7711 of file Nano100Series.h.
| #define SC_IER_BGT_IE_Msk (0x1ul << SC_IER_BGT_IE_Pos) |
SC_T::IER: BGT_IE Mask
Definition at line 7700 of file Nano100Series.h.
| #define SC_IER_BGT_IE_Pos (6) |
SC_T::IER: BGT_IE Position
Definition at line 7699 of file Nano100Series.h.
| #define SC_IER_CD_IE_Msk (0x1ul << SC_IER_CD_IE_Pos) |
SC_T::IER: CD_IE Mask
Definition at line 7703 of file Nano100Series.h.
| #define SC_IER_CD_IE_Pos (7) |
SC_T::IER: CD_IE Position
Definition at line 7702 of file Nano100Series.h.
| #define SC_IER_COMPEN_EN_Msk (0x1ul << SC_IER_COMPEN_EN_Pos) |
SC_T::IER: COMPEN_EN Mask
Definition at line 7715 of file Nano100Series.h.
| #define SC_IER_COMPEN_EN_Pos (15) |
SC_T::IER: COMPEN_EN Position
Definition at line 7714 of file Nano100Series.h.
| #define SC_IER_INIT_IE_Msk (0x1ul << SC_IER_INIT_IE_Pos) |
SC_T::IER: INIT_IE Mask
Definition at line 7706 of file Nano100Series.h.
| #define SC_IER_INIT_IE_Pos (8) |
SC_T::IER: INIT_IE Position
Definition at line 7705 of file Nano100Series.h.
| #define SC_IER_RDA_IE_Msk (0x1ul << SC_IER_RDA_IE_Pos) |
SC_T::IER: RDA_IE Mask
Definition at line 7682 of file Nano100Series.h.
| #define SC_IER_RDA_IE_Pos (0) |
SC_T::IER: RDA_IE Position
Definition at line 7681 of file Nano100Series.h.
| #define SC_IER_RTMR_IE_Msk (0x1ul << SC_IER_RTMR_IE_Pos) |
SC_T::IER: RTMR_IE Mask
Definition at line 7709 of file Nano100Series.h.
| #define SC_IER_RTMR_IE_Pos (9) |
SC_T::IER: RTMR_IE Position
Definition at line 7708 of file Nano100Series.h.
| #define SC_IER_TBE_IE_Msk (0x1ul << SC_IER_TBE_IE_Pos) |
SC_T::IER: TBE_IE Mask
Definition at line 7685 of file Nano100Series.h.
| #define SC_IER_TBE_IE_Pos (1) |
SC_T::IER: TBE_IE Position
Definition at line 7684 of file Nano100Series.h.
| #define SC_IER_TERR_IE_Msk (0x1ul << SC_IER_TERR_IE_Pos) |
SC_T::IER: TERR_IE Mask
Definition at line 7688 of file Nano100Series.h.
| #define SC_IER_TERR_IE_Pos (2) |
SC_T::IER: TERR_IE Position
Definition at line 7687 of file Nano100Series.h.
| #define SC_IER_TMR0_IE_Msk (0x1ul << SC_IER_TMR0_IE_Pos) |
SC_T::IER: TMR0_IE Mask
Definition at line 7691 of file Nano100Series.h.
| #define SC_IER_TMR0_IE_Pos (3) |
SC_T::IER: TMR0_IE Position
Definition at line 7690 of file Nano100Series.h.
| #define SC_IER_TMR1_IE_Msk (0x1ul << SC_IER_TMR1_IE_Pos) |
SC_T::IER: TMR1_IE Mask
Definition at line 7694 of file Nano100Series.h.
| #define SC_IER_TMR1_IE_Pos (4) |
SC_T::IER: TMR1_IE Position
Definition at line 7693 of file Nano100Series.h.
| #define SC_IER_TMR2_IE_Msk (0x1ul << SC_IER_TMR2_IE_Pos) |
SC_T::IER: TMR2_IE Mask
Definition at line 7697 of file Nano100Series.h.
| #define SC_IER_TMR2_IE_Pos (5) |
SC_T::IER: TMR2_IE Position
Definition at line 7696 of file Nano100Series.h.
| #define SC_ISR_ACON_ERR_IS_Msk (0x1ul << SC_ISR_ACON_ERR_IS_Pos) |
SC_T::ISR: ACON_ERR_IS Mask
Definition at line 7748 of file Nano100Series.h.
| #define SC_ISR_ACON_ERR_IS_Pos (10) |
SC_T::ISR: ACON_ERR_IS Position
Definition at line 7747 of file Nano100Series.h.
| #define SC_ISR_BGT_IS_Msk (0x1ul << SC_ISR_BGT_IS_Pos) |
SC_T::ISR: BGT_IS Mask
Definition at line 7736 of file Nano100Series.h.
| #define SC_ISR_BGT_IS_Pos (6) |
SC_T::ISR: BGT_IS Position
Definition at line 7735 of file Nano100Series.h.
| #define SC_ISR_CD_IS_Msk (0x1ul << SC_ISR_CD_IS_Pos) |
SC_T::ISR: CD_IS Mask
Definition at line 7739 of file Nano100Series.h.
| #define SC_ISR_CD_IS_Pos (7) |
SC_T::ISR: CD_IS Position
Definition at line 7738 of file Nano100Series.h.
| #define SC_ISR_INIT_IS_Msk (0x1ul << SC_ISR_INIT_IS_Pos) |
SC_T::ISR: INIT_IS Mask
Definition at line 7742 of file Nano100Series.h.
| #define SC_ISR_INIT_IS_Pos (8) |
SC_T::ISR: INIT_IS Position
Definition at line 7741 of file Nano100Series.h.
| #define SC_ISR_RDA_IS_Msk (0x1ul << SC_ISR_RDA_IS_Pos) |
SC_T::ISR: RDA_IS Mask
Definition at line 7718 of file Nano100Series.h.
| #define SC_ISR_RDA_IS_Pos (0) |
SC_T::ISR: RDA_IS Position
Definition at line 7717 of file Nano100Series.h.
| #define SC_ISR_RTMR_IS_Msk (0x1ul << SC_ISR_RTMR_IS_Pos) |
SC_T::ISR: RTMR_IS Mask
Definition at line 7745 of file Nano100Series.h.
| #define SC_ISR_RTMR_IS_Pos (9) |
SC_T::ISR: RTMR_IS Position
Definition at line 7744 of file Nano100Series.h.
| #define SC_ISR_TBE_IS_Msk (0x1ul << SC_ISR_TBE_IS_Pos) |
SC_T::ISR: TBE_IS Mask
Definition at line 7721 of file Nano100Series.h.
| #define SC_ISR_TBE_IS_Pos (1) |
SC_T::ISR: TBE_IS Position
Definition at line 7720 of file Nano100Series.h.
| #define SC_ISR_TERR_IS_Msk (0x1ul << SC_ISR_TERR_IS_Pos) |
SC_T::ISR: TERR_IS Mask
Definition at line 7724 of file Nano100Series.h.
| #define SC_ISR_TERR_IS_Pos (2) |
SC_T::ISR: TERR_IS Position
Definition at line 7723 of file Nano100Series.h.
| #define SC_ISR_TMR0_IS_Msk (0x1ul << SC_ISR_TMR0_IS_Pos) |
SC_T::ISR: TMR0_IS Mask
Definition at line 7727 of file Nano100Series.h.
| #define SC_ISR_TMR0_IS_Pos (3) |
SC_T::ISR: TMR0_IS Position
Definition at line 7726 of file Nano100Series.h.
| #define SC_ISR_TMR1_IS_Msk (0x1ul << SC_ISR_TMR1_IS_Pos) |
SC_T::ISR: TMR1_IS Mask
Definition at line 7730 of file Nano100Series.h.
| #define SC_ISR_TMR1_IS_Pos (4) |
SC_T::ISR: TMR1_IS Position
Definition at line 7729 of file Nano100Series.h.
| #define SC_ISR_TMR2_IS_Msk (0x1ul << SC_ISR_TMR2_IS_Pos) |
SC_T::ISR: TMR2_IS Mask
Definition at line 7733 of file Nano100Series.h.
| #define SC_ISR_TMR2_IS_Pos (5) |
SC_T::ISR: TMR2_IS Position
Definition at line 7732 of file Nano100Series.h.
| #define SC_PINCSR_ADAC_CD_EN_Msk (0x1ul << SC_PINCSR_ADAC_CD_EN_Pos) |
SC_T::PINCSR: ADAC_CD_EN Mask
Definition at line 7820 of file Nano100Series.h.
| #define SC_PINCSR_ADAC_CD_EN_Pos (7) |
SC_T::PINCSR: ADAC_CD_EN Position
Definition at line 7819 of file Nano100Series.h.
| #define SC_PINCSR_CD_INS_F_Msk (0x1ul << SC_PINCSR_CD_INS_F_Pos) |
SC_T::PINCSR: CD_INS_F Mask
Definition at line 7811 of file Nano100Series.h.
| #define SC_PINCSR_CD_INS_F_Pos (3) |
SC_T::PINCSR: CD_INS_F Position
Definition at line 7810 of file Nano100Series.h.
| #define SC_PINCSR_CD_LEV_Msk (0x1ul << SC_PINCSR_CD_LEV_Pos) |
SC_T::PINCSR: CD_LEV Mask
Definition at line 7829 of file Nano100Series.h.
| #define SC_PINCSR_CD_LEV_Pos (10) |
SC_T::PINCSR: CD_LEV Position
Definition at line 7828 of file Nano100Series.h.
| #define SC_PINCSR_CD_PIN_ST_Msk (0x1ul << SC_PINCSR_CD_PIN_ST_Pos) |
SC_T::PINCSR: CD_PIN_ST Mask
Definition at line 7814 of file Nano100Series.h.
| #define SC_PINCSR_CD_PIN_ST_Pos (4) |
SC_T::PINCSR: CD_PIN_ST Position
Definition at line 7813 of file Nano100Series.h.
| #define SC_PINCSR_CD_REM_F_Msk (0x1ul << SC_PINCSR_CD_REM_F_Pos) |
SC_T::PINCSR: CD_REM_F Mask
Definition at line 7808 of file Nano100Series.h.
| #define SC_PINCSR_CD_REM_F_Pos (2) |
SC_T::PINCSR: CD_REM_F Position
Definition at line 7807 of file Nano100Series.h.
| #define SC_PINCSR_CLK_KEEP_Msk (0x1ul << SC_PINCSR_CLK_KEEP_Pos) |
SC_T::PINCSR: CLK_KEEP Mask
Definition at line 7817 of file Nano100Series.h.
| #define SC_PINCSR_CLK_KEEP_Pos (6) |
SC_T::PINCSR: CLK_KEEP Position
Definition at line 7816 of file Nano100Series.h.
| #define SC_PINCSR_POW_EN_Msk (0x1ul << SC_PINCSR_POW_EN_Pos) |
SC_T::PINCSR: POW_EN Mask
Definition at line 7802 of file Nano100Series.h.
| #define SC_PINCSR_POW_EN_Pos (0) |
SC_T::PINCSR: POW_EN Position
Definition at line 7801 of file Nano100Series.h.
| #define SC_PINCSR_SC_DATA_I_ST_Msk (0x1ul << SC_PINCSR_SC_DATA_I_ST_Pos) |
SC_T::PINCSR: SC_DATA_I_ST Mask
Definition at line 7832 of file Nano100Series.h.
| #define SC_PINCSR_SC_DATA_I_ST_Pos (16) |
SC_T::PINCSR: SC_DATA_I_ST Position
Definition at line 7831 of file Nano100Series.h.
| #define SC_PINCSR_SC_DATA_O_Msk (0x1ul << SC_PINCSR_SC_DATA_O_Pos) |
SC_T::PINCSR: SC_DATA_O Mask
Definition at line 7826 of file Nano100Series.h.
| #define SC_PINCSR_SC_DATA_O_Pos (9) |
SC_T::PINCSR: SC_DATA_O Position
Definition at line 7825 of file Nano100Series.h.
| #define SC_PINCSR_SC_OEN_ST_Msk (0x1ul << SC_PINCSR_SC_OEN_ST_Pos) |
SC_T::PINCSR: SC_OEN_ST Mask
Definition at line 7823 of file Nano100Series.h.
| #define SC_PINCSR_SC_OEN_ST_Pos (8) |
SC_T::PINCSR: SC_OEN_ST Position
Definition at line 7822 of file Nano100Series.h.
| #define SC_PINCSR_SC_RST_Msk (0x1ul << SC_PINCSR_SC_RST_Pos) |
SC_T::PINCSR: SC_RST Mask
Definition at line 7805 of file Nano100Series.h.
| #define SC_PINCSR_SC_RST_Pos (1) |
SC_T::PINCSR: SC_RST Position
Definition at line 7804 of file Nano100Series.h.
| #define SC_RFTMR_RFTM_Msk (0x1fful << SC_RFTMR_RFTM_Pos) |
SC_T::RFTMR: RFTM Mask
Definition at line 7673 of file Nano100Series.h.
| #define SC_RFTMR_RFTM_Pos (0) |
SC_T::RFTMR: RFTM Position
Definition at line 7672 of file Nano100Series.h.
| #define SC_TDRA_TDR0_Msk (0xfffffful << SC_TDRA_TDR0_Pos) |
SC_T::TDRA: TDR0 Mask
Definition at line 7853 of file Nano100Series.h.
| #define SC_TDRA_TDR0_Pos (0) |
SC_T::TDRA: TDR0 Position
Definition at line 7852 of file Nano100Series.h.
| #define SC_TDRB_TDR1_Msk (0xfful << SC_TDRB_TDR1_Pos) |
SC_T::TDRB: TDR1 Mask
Definition at line 7856 of file Nano100Series.h.
| #define SC_TDRB_TDR1_Pos (0) |
SC_T::TDRB: TDR1 Position
Definition at line 7855 of file Nano100Series.h.
| #define SC_TDRB_TDR2_Msk (0xfful << SC_TDRB_TDR2_Pos) |
SC_T::TDRB: TDR2 Mask
Definition at line 7859 of file Nano100Series.h.
| #define SC_TDRB_TDR2_Pos (8) |
SC_T::TDRB: TDR2 Position
Definition at line 7858 of file Nano100Series.h.
| #define SC_TMR0_CNT_Msk (0xfffffful << SC_TMR0_CNT_Pos) |
SC_T::TMR0: CNT Mask
Definition at line 7835 of file Nano100Series.h.
| #define SC_TMR0_CNT_Pos (0) |
SC_T::TMR0: CNT Position
Definition at line 7834 of file Nano100Series.h.
| #define SC_TMR0_MODE_Msk (0xful << SC_TMR0_MODE_Pos) |
SC_T::TMR0: MODE Mask
Definition at line 7838 of file Nano100Series.h.
| #define SC_TMR0_MODE_Pos (24) |
SC_T::TMR0: MODE Position
Definition at line 7837 of file Nano100Series.h.
| #define SC_TMR1_CNT_Msk (0xfful << SC_TMR1_CNT_Pos) |
SC_T::TMR1: CNT Mask
Definition at line 7841 of file Nano100Series.h.
| #define SC_TMR1_CNT_Pos (0) |
SC_T::TMR1: CNT Position
Definition at line 7840 of file Nano100Series.h.
| #define SC_TMR1_MODE_Msk (0xful << SC_TMR1_MODE_Pos) |
SC_T::TMR1: MODE Mask
Definition at line 7844 of file Nano100Series.h.
| #define SC_TMR1_MODE_Pos (24) |
SC_T::TMR1: MODE Position
Definition at line 7843 of file Nano100Series.h.
| #define SC_TMR2_CNT_Msk (0xfful << SC_TMR2_CNT_Pos) |
SC_T::TMR2: CNT Mask
Definition at line 7847 of file Nano100Series.h.
| #define SC_TMR2_CNT_Pos (0) |
SC_T::TMR2: CNT Position
Definition at line 7846 of file Nano100Series.h.
| #define SC_TMR2_MODE_Msk (0xful << SC_TMR2_MODE_Pos) |
SC_T::TMR2: MODE Mask
Definition at line 7850 of file Nano100Series.h.
| #define SC_TMR2_MODE_Pos (24) |
SC_T::TMR2: MODE Position
Definition at line 7849 of file Nano100Series.h.
| #define SC_TRSR_RX_ATV_Msk (0x1ul << SC_TRSR_RX_ATV_Pos) |
SC_T::TRSR: RX_ATV Mask
Definition at line 7787 of file Nano100Series.h.
| #define SC_TRSR_RX_ATV_Pos (23) |
SC_T::TRSR: RX_ATV Position
Definition at line 7786 of file Nano100Series.h.
| #define SC_TRSR_RX_EBR_F_Msk (0x1ul << SC_TRSR_RX_EBR_F_Pos) |
SC_T::TRSR: RX_EBR_F Mask
Definition at line 7766 of file Nano100Series.h.
| #define SC_TRSR_RX_EBR_F_Pos (6) |
SC_T::TRSR: RX_EBR_F Position
Definition at line 7765 of file Nano100Series.h.
| #define SC_TRSR_RX_EFR_F_Msk (0x1ul << SC_TRSR_RX_EFR_F_Pos) |
SC_T::TRSR: RX_EFR_F Mask
Definition at line 7763 of file Nano100Series.h.
| #define SC_TRSR_RX_EFR_F_Pos (5) |
SC_T::TRSR: RX_EFR_F Position
Definition at line 7762 of file Nano100Series.h.
| #define SC_TRSR_RX_EMPTY_F_Msk (0x1ul << SC_TRSR_RX_EMPTY_F_Pos) |
SC_T::TRSR: RX_EMPTY_F Mask
Definition at line 7754 of file Nano100Series.h.
| #define SC_TRSR_RX_EMPTY_F_Pos (1) |
SC_T::TRSR: RX_EMPTY_F Position
Definition at line 7753 of file Nano100Series.h.
| #define SC_TRSR_RX_EPA_F_Msk (0x1ul << SC_TRSR_RX_EPA_F_Pos) |
SC_T::TRSR: RX_EPA_F Mask
Definition at line 7760 of file Nano100Series.h.
| #define SC_TRSR_RX_EPA_F_Pos (4) |
SC_T::TRSR: RX_EPA_F Position
Definition at line 7759 of file Nano100Series.h.
| #define SC_TRSR_RX_FULL_F_Msk (0x1ul << SC_TRSR_RX_FULL_F_Pos) |
SC_T::TRSR: RX_FULL_F Mask
Definition at line 7757 of file Nano100Series.h.
| #define SC_TRSR_RX_FULL_F_Pos (2) |
SC_T::TRSR: RX_FULL_F Position
Definition at line 7756 of file Nano100Series.h.
| #define SC_TRSR_RX_OVER_ERETRY_Msk (0x1ul << SC_TRSR_RX_OVER_ERETRY_Pos) |
SC_T::TRSR: RX_OVER_ERETRY Mask
Definition at line 7784 of file Nano100Series.h.
| #define SC_TRSR_RX_OVER_ERETRY_Pos (22) |
SC_T::TRSR: RX_OVER_ERETRY Position
Definition at line 7783 of file Nano100Series.h.
| #define SC_TRSR_RX_OVER_F_Msk (0x1ul << SC_TRSR_RX_OVER_F_Pos) |
SC_T::TRSR: RX_OVER_F Mask
Definition at line 7751 of file Nano100Series.h.
| #define SC_TRSR_RX_OVER_F_Pos (0) |
SC_T::TRSR: RX_OVER_F Position
Definition at line 7750 of file Nano100Series.h.
| #define SC_TRSR_RX_POINT_F_Msk (0x7ul << SC_TRSR_RX_POINT_F_Pos) |
SC_T::TRSR: RX_POINT_F Mask
Definition at line 7778 of file Nano100Series.h.
| #define SC_TRSR_RX_POINT_F_Pos (16) |
SC_T::TRSR: RX_POINT_F Position
Definition at line 7777 of file Nano100Series.h.
| #define SC_TRSR_RX_REERR_Msk (0x1ul << SC_TRSR_RX_REERR_Pos) |
SC_T::TRSR: RX_REERR Mask
Definition at line 7781 of file Nano100Series.h.
| #define SC_TRSR_RX_REERR_Pos (21) |
SC_T::TRSR: RX_REERR Position
Definition at line 7780 of file Nano100Series.h.
| #define SC_TRSR_TX_ATV_Msk (0x1ul << SC_TRSR_TX_ATV_Pos) |
SC_T::TRSR: TX_ATV Mask
Definition at line 7799 of file Nano100Series.h.
| #define SC_TRSR_TX_ATV_Pos (31) |
SC_T::TRSR: TX_ATV Position
Definition at line 7798 of file Nano100Series.h.
| #define SC_TRSR_TX_EMPTY_F_Msk (0x1ul << SC_TRSR_TX_EMPTY_F_Pos) |
SC_T::TRSR: TX_EMPTY_F Mask
Definition at line 7772 of file Nano100Series.h.
| #define SC_TRSR_TX_EMPTY_F_Pos (9) |
SC_T::TRSR: TX_EMPTY_F Position
Definition at line 7771 of file Nano100Series.h.
| #define SC_TRSR_TX_FULL_F_Msk (0x1ul << SC_TRSR_TX_FULL_F_Pos) |
SC_T::TRSR: TX_FULL_F Mask
Definition at line 7775 of file Nano100Series.h.
| #define SC_TRSR_TX_FULL_F_Pos (10) |
SC_T::TRSR: TX_FULL_F Position
Definition at line 7774 of file Nano100Series.h.
| #define SC_TRSR_TX_OVER_ERETRY_Msk (0x1ul << SC_TRSR_TX_OVER_ERETRY_Pos) |
SC_T::TRSR: TX_OVER_ERETRY Mask
Definition at line 7796 of file Nano100Series.h.
| #define SC_TRSR_TX_OVER_ERETRY_Pos (30) |
SC_T::TRSR: TX_OVER_ERETRY Position
Definition at line 7795 of file Nano100Series.h.
| #define SC_TRSR_TX_OVER_F_Msk (0x1ul << SC_TRSR_TX_OVER_F_Pos) |
SC_T::TRSR: TX_OVER_F Mask
Definition at line 7769 of file Nano100Series.h.
| #define SC_TRSR_TX_OVER_F_Pos (8) |
SC_T::TRSR: TX_OVER_F Position
Definition at line 7768 of file Nano100Series.h.
| #define SC_TRSR_TX_POINT_F_Msk (0x7ul << SC_TRSR_TX_POINT_F_Pos) |
SC_T::TRSR: TX_POINT_F Mask
Definition at line 7790 of file Nano100Series.h.
| #define SC_TRSR_TX_POINT_F_Pos (24) |
SC_T::TRSR: TX_POINT_F Position
Definition at line 7789 of file Nano100Series.h.
| #define SC_TRSR_TX_REERR_Msk (0x1ul << SC_TRSR_TX_REERR_Pos) |
SC_T::TRSR: TX_REERR Mask
Definition at line 7793 of file Nano100Series.h.
| #define SC_TRSR_TX_REERR_Pos (29) |
SC_T::TRSR: TX_REERR Position
Definition at line 7792 of file Nano100Series.h.
| #define SPI_CLKDIV_DIVIDER1_Msk (0xfffful << SPI_CLKDIV_DIVIDER1_Pos) |
SPI_T::CLKDIV: DIVIDER1 Mask
Definition at line 8299 of file Nano100Series.h.
| #define SPI_CLKDIV_DIVIDER1_Pos (0) |
SPI_T::CLKDIV: DIVIDER1 Position
Definition at line 8298 of file Nano100Series.h.
| #define SPI_CLKDIV_DIVIDER2_Msk (0xfffful << SPI_CLKDIV_DIVIDER2_Pos) |
SPI_T::CLKDIV: DIVIDER2 Mask
Definition at line 8302 of file Nano100Series.h.
| #define SPI_CLKDIV_DIVIDER2_Pos (16) |
SPI_T::CLKDIV: DIVIDER2 Position
Definition at line 8301 of file Nano100Series.h.
| #define SPI_CTL_CLKP_Msk (0x1ul << SPI_CTL_CLKP_Pos) |
SPI_T::CTL: CLKP Mask
Definition at line 8251 of file Nano100Series.h.
| #define SPI_CTL_CLKP_Pos (11) |
SPI_T::CTL: CLKP Position
Definition at line 8250 of file Nano100Series.h.
| #define SPI_CTL_FIFOM_Msk (0x1ul << SPI_CTL_FIFOM_Pos) |
SPI_T::CTL: FIFOM Mask
Definition at line 8266 of file Nano100Series.h.
| #define SPI_CTL_FIFOM_Pos (21) |
SPI_T::CTL: FIFOM Position
Definition at line 8265 of file Nano100Series.h.
| #define SPI_CTL_GO_BUSY_Msk (0x1ul << SPI_CTL_GO_BUSY_Pos) |
SPI_T::CTL: GO_BUSY Mask
Definition at line 8233 of file Nano100Series.h.
| #define SPI_CTL_GO_BUSY_Pos (0) |
@addtogroup SPI_CONST SPI Bit Field Definition Constant Definitions for SPI Controller
SPI_T::CTL: GO_BUSY Position
Definition at line 8232 of file Nano100Series.h.
| #define SPI_CTL_INTEN_Msk (0x1ul << SPI_CTL_INTEN_Pos) |
SPI_T::CTL: INTEN Mask
Definition at line 8257 of file Nano100Series.h.
| #define SPI_CTL_INTEN_Pos (17) |
SPI_T::CTL: INTEN Position
Definition at line 8256 of file Nano100Series.h.
| #define SPI_CTL_LSB_Msk (0x1ul << SPI_CTL_LSB_Pos) |
SPI_T::CTL: LSB Mask
Definition at line 8248 of file Nano100Series.h.
| #define SPI_CTL_LSB_Pos (10) |
SPI_T::CTL: LSB Position
Definition at line 8247 of file Nano100Series.h.
| #define SPI_CTL_REORDER_Msk (0x3ul << SPI_CTL_REORDER_Pos) |
SPI_T::CTL: REORDER Mask
Definition at line 8263 of file Nano100Series.h.
| #define SPI_CTL_REORDER_Pos (19) |
SPI_T::CTL: REORDER Position
Definition at line 8262 of file Nano100Series.h.
| #define SPI_CTL_RX_NEG_Msk (0x1ul << SPI_CTL_RX_NEG_Pos) |
SPI_T::CTL: RX_NEG Mask
Definition at line 8236 of file Nano100Series.h.
| #define SPI_CTL_RX_NEG_Pos (1) |
SPI_T::CTL: RX_NEG Position
Definition at line 8235 of file Nano100Series.h.
| #define SPI_CTL_SLAVE_Msk (0x1ul << SPI_CTL_SLAVE_Pos) |
SPI_T::CTL: SLAVE Mask
Definition at line 8260 of file Nano100Series.h.
| #define SPI_CTL_SLAVE_Pos (18) |
SPI_T::CTL: SLAVE Position
Definition at line 8259 of file Nano100Series.h.
| #define SPI_CTL_SP_CYCLE_Msk (0xful << SPI_CTL_SP_CYCLE_Pos) |
SPI_T::CTL: SP_CYCLE Mask
Definition at line 8254 of file Nano100Series.h.
| #define SPI_CTL_SP_CYCLE_Pos (12) |
SPI_T::CTL: SP_CYCLE Position
Definition at line 8253 of file Nano100Series.h.
| #define SPI_CTL_TWOB_Msk (0x1ul << SPI_CTL_TWOB_Pos) |
SPI_T::CTL: TWOB Mask
Definition at line 8269 of file Nano100Series.h.
| #define SPI_CTL_TWOB_Pos (22) |
SPI_T::CTL: TWOB Position
Definition at line 8268 of file Nano100Series.h.
| #define SPI_CTL_TX_BIT_LEN_Msk (0x1ful << SPI_CTL_TX_BIT_LEN_Pos) |
SPI_T::CTL: TX_BIT_LEN Mask
Definition at line 8242 of file Nano100Series.h.
| #define SPI_CTL_TX_BIT_LEN_Pos (3) |
SPI_T::CTL: TX_BIT_LEN Position
Definition at line 8241 of file Nano100Series.h.
| #define SPI_CTL_TX_NEG_Msk (0x1ul << SPI_CTL_TX_NEG_Pos) |
SPI_T::CTL: TX_NEG Mask
Definition at line 8239 of file Nano100Series.h.
| #define SPI_CTL_TX_NEG_Pos (2) |
SPI_T::CTL: TX_NEG Position
Definition at line 8238 of file Nano100Series.h.
| #define SPI_CTL_TX_NUM_Msk (0x3ul << SPI_CTL_TX_NUM_Pos) |
SPI_T::CTL: TX_NUM Mask
Definition at line 8245 of file Nano100Series.h.
| #define SPI_CTL_TX_NUM_Pos (8) |
SPI_T::CTL: TX_NUM Position
Definition at line 8244 of file Nano100Series.h.
| #define SPI_CTL_VARCLK_EN_Msk (0x1ul << SPI_CTL_VARCLK_EN_Pos) |
SPI_T::CTL: VARCLK_EN Mask
Definition at line 8272 of file Nano100Series.h.
| #define SPI_CTL_VARCLK_EN_Pos (23) |
SPI_T::CTL: VARCLK_EN Position
Definition at line 8271 of file Nano100Series.h.
| #define SPI_CTL_WKEUP_EN_Msk (0x1ul << SPI_CTL_WKEUP_EN_Pos) |
SPI_T::CTL: WKEUP_EN Mask
Definition at line 8275 of file Nano100Series.h.
| #define SPI_CTL_WKEUP_EN_Pos (31) |
SPI_T::CTL: WKEUP_EN Position
Definition at line 8274 of file Nano100Series.h.
| #define SPI_FFCLR_RX_CLR_Msk (0x1ul << SPI_FFCLR_RX_CLR_Pos) |
SPI_T::FFCLR: RX_CLR Mask
Definition at line 8350 of file Nano100Series.h.
| #define SPI_FFCLR_RX_CLR_Pos (0) |
SPI_T::FFCLR: RX_CLR Position
Definition at line 8349 of file Nano100Series.h.
| #define SPI_FFCLR_TX_CLR_Msk (0x1ul << SPI_FFCLR_TX_CLR_Pos) |
SPI_T::FFCLR: TX_CLR Mask
Definition at line 8353 of file Nano100Series.h.
| #define SPI_FFCLR_TX_CLR_Pos (1) |
SPI_T::FFCLR: TX_CLR Position
Definition at line 8352 of file Nano100Series.h.
| #define SPI_PDMA_PDMA_RST_Msk (0x1ul << SPI_PDMA_PDMA_RST_Pos) |
SPI_T::PDMA: PDMA_RST Mask
Definition at line 8347 of file Nano100Series.h.
| #define SPI_PDMA_PDMA_RST_Pos (2) |
SPI_T::PDMA: PDMA_RST Position
Definition at line 8346 of file Nano100Series.h.
| #define SPI_PDMA_RX_DMA_EN_Msk (0x1ul << SPI_PDMA_RX_DMA_EN_Pos) |
SPI_T::PDMA: RX_DMA_EN Mask
Definition at line 8344 of file Nano100Series.h.
| #define SPI_PDMA_RX_DMA_EN_Pos (1) |
SPI_T::PDMA: RX_DMA_EN Position
Definition at line 8343 of file Nano100Series.h.
| #define SPI_PDMA_TX_DMA_EN_Msk (0x1ul << SPI_PDMA_TX_DMA_EN_Pos) |
SPI_T::PDMA: TX_DMA_EN Mask
Definition at line 8341 of file Nano100Series.h.
| #define SPI_PDMA_TX_DMA_EN_Pos (0) |
SPI_T::PDMA: TX_DMA_EN Position
Definition at line 8340 of file Nano100Series.h.
| #define SPI_RX0_RDATA_Msk (0xfffffffful << SPI_RX0_RDATA_Pos) |
SPI_T::RX0: RDATA Mask
Definition at line 8326 of file Nano100Series.h.
| #define SPI_RX0_RDATA_Pos (0) |
SPI_T::RX0: RDATA Position
Definition at line 8325 of file Nano100Series.h.
| #define SPI_RX1_RDATA_Msk (0xfffffffful << SPI_RX1_RDATA_Pos) |
SPI_T::RX1: RDATA Mask
Definition at line 8329 of file Nano100Series.h.
| #define SPI_RX1_RDATA_Pos (0) |
SPI_T::RX1: RDATA Position
Definition at line 8328 of file Nano100Series.h.
| #define SPI_SSR_AUTOSS_Msk (0x1ul << SPI_SSR_AUTOSS_Pos) |
SPI_T::SSR: AUTOSS Mask
Definition at line 8311 of file Nano100Series.h.
| #define SPI_SSR_AUTOSS_Pos (3) |
SPI_T::SSR: AUTOSS Position
Definition at line 8310 of file Nano100Series.h.
| #define SPI_SSR_NOSLVSEL_Msk (0x1ul << SPI_SSR_NOSLVSEL_Pos) |
SPI_T::SSR: NOSLVSEL Mask
Definition at line 8317 of file Nano100Series.h.
| #define SPI_SSR_NOSLVSEL_Pos (5) |
SPI_T::SSR: NOSLVSEL Position
Definition at line 8316 of file Nano100Series.h.
| #define SPI_SSR_SLV_ABORT_Msk (0x1ul << SPI_SSR_SLV_ABORT_Pos) |
SPI_T::SSR: SLV_ABORT Mask
Definition at line 8320 of file Nano100Series.h.
| #define SPI_SSR_SLV_ABORT_Pos (8) |
SPI_T::SSR: SLV_ABORT Position
Definition at line 8319 of file Nano100Series.h.
| #define SPI_SSR_SS_LTRIG_Msk (0x1ul << SPI_SSR_SS_LTRIG_Pos) |
SPI_T::SSR: SS_LTRIG Mask
Definition at line 8314 of file Nano100Series.h.
| #define SPI_SSR_SS_LTRIG_Pos (4) |
SPI_T::SSR: SS_LTRIG Position
Definition at line 8313 of file Nano100Series.h.
| #define SPI_SSR_SS_LVL_Msk (0x1ul << SPI_SSR_SS_LVL_Pos) |
SPI_T::SSR: SS_LVL Mask
Definition at line 8308 of file Nano100Series.h.
| #define SPI_SSR_SS_LVL_Pos (2) |
SPI_T::SSR: SS_LVL Position
Definition at line 8307 of file Nano100Series.h.
| #define SPI_SSR_SSR_Msk (0x3ul << SPI_SSR_SSR_Pos) |
SPI_T::SSR: SSR Mask
Definition at line 8305 of file Nano100Series.h.
| #define SPI_SSR_SSR_Pos (0) |
SPI_T::SSR: SSR Position
Definition at line 8304 of file Nano100Series.h.
| #define SPI_SSR_SSTA_INTEN_Msk (0x1ul << SPI_SSR_SSTA_INTEN_Pos) |
SPI_T::SSR: SSTA_INTEN Mask
Definition at line 8323 of file Nano100Series.h.
| #define SPI_SSR_SSTA_INTEN_Pos (9) |
SPI_T::SSR: SSTA_INTEN Position
Definition at line 8322 of file Nano100Series.h.
| #define SPI_STATUS_INTSTS_Msk (0x1ul << SPI_STATUS_INTSTS_Pos) |
SPI_T::STATUS: INTSTS Mask
Definition at line 8296 of file Nano100Series.h.
| #define SPI_STATUS_INTSTS_Pos (7) |
SPI_T::STATUS: INTSTS Position
Definition at line 8295 of file Nano100Series.h.
| #define SPI_STATUS_LTRIG_FLAG_Msk (0x1ul << SPI_STATUS_LTRIG_FLAG_Pos) |
SPI_T::STATUS: LTRIG_FLAG Mask
Definition at line 8290 of file Nano100Series.h.
| #define SPI_STATUS_LTRIG_FLAG_Pos (4) |
SPI_T::STATUS: LTRIG_FLAG Position
Definition at line 8289 of file Nano100Series.h.
| #define SPI_STATUS_RX_EMPTY_Msk (0x1ul << SPI_STATUS_RX_EMPTY_Pos) |
SPI_T::STATUS: RX_EMPTY Mask
Definition at line 8278 of file Nano100Series.h.
| #define SPI_STATUS_RX_EMPTY_Pos (0) |
SPI_T::STATUS: RX_EMPTY Position
Definition at line 8277 of file Nano100Series.h.
| #define SPI_STATUS_RX_FULL_Msk (0x1ul << SPI_STATUS_RX_FULL_Pos) |
SPI_T::STATUS: RX_FULL Mask
Definition at line 8281 of file Nano100Series.h.
| #define SPI_STATUS_RX_FULL_Pos (1) |
SPI_T::STATUS: RX_FULL Position
Definition at line 8280 of file Nano100Series.h.
| #define SPI_STATUS_SLV_START_INTSTS_Msk (0x1ul << SPI_STATUS_SLV_START_INTSTS_Pos) |
SPI_T::STATUS: SLV_START_INTSTS Mask
Definition at line 8293 of file Nano100Series.h.
| #define SPI_STATUS_SLV_START_INTSTS_Pos (6) |
SPI_T::STATUS: SLV_START_INTSTS Position
Definition at line 8292 of file Nano100Series.h.
| #define SPI_STATUS_TX_EMPTY_Msk (0x1ul << SPI_STATUS_TX_EMPTY_Pos) |
SPI_T::STATUS: TX_EMPTY Mask
Definition at line 8284 of file Nano100Series.h.
| #define SPI_STATUS_TX_EMPTY_Pos (2) |
SPI_T::STATUS: TX_EMPTY Position
Definition at line 8283 of file Nano100Series.h.
| #define SPI_STATUS_TX_FULL_Msk (0x1ul << SPI_STATUS_TX_FULL_Pos) |
SPI_T::STATUS: TX_FULL Mask
Definition at line 8287 of file Nano100Series.h.
| #define SPI_STATUS_TX_FULL_Pos (3) |
SPI_T::STATUS: TX_FULL Position
Definition at line 8286 of file Nano100Series.h.
| #define SPI_TX0_TDATA_Msk (0xfffffffful << SPI_TX0_TDATA_Pos) |
SPI_T::TX0: TDATA Mask
Definition at line 8332 of file Nano100Series.h.
| #define SPI_TX0_TDATA_Pos (0) |
SPI_T::TX0: TDATA Position
Definition at line 8331 of file Nano100Series.h.
| #define SPI_TX1_TDATA_Msk (0xfffffffful << SPI_TX1_TDATA_Pos) |
SPI_T::TX1: TDATA Mask
Definition at line 8335 of file Nano100Series.h.
| #define SPI_TX1_TDATA_Pos (0) |
SPI_T::TX1: TDATA Position
Definition at line 8334 of file Nano100Series.h.
| #define SPI_VARCLK_VARCLK_Msk (0xfffffffful << SPI_VARCLK_VARCLK_Pos) |
SPI_T::VARCLK: VARCLK Mask
Definition at line 8338 of file Nano100Series.h.
| #define SPI_VARCLK_VARCLK_Pos (0) |
SPI_T::VARCLK: VARCLK Position
Definition at line 8337 of file Nano100Series.h.
| #define SYS_BODCTL_BOD17_EN_Msk (0x1ul << SYS_BODCTL_BOD17_EN_Pos) |
SYS_T::BODCTL: BOD17_EN Mask
Definition at line 3667 of file Nano100Series.h.
| #define SYS_BODCTL_BOD17_EN_Pos (0) |
SYS_T::BODCTL: BOD17_EN Position
Definition at line 3666 of file Nano100Series.h.
| #define SYS_BODCTL_BOD17_INT_EN_Msk (0x1ul << SYS_BODCTL_BOD17_INT_EN_Pos) |
SYS_T::BODCTL: BOD17_INT_EN Mask
Definition at line 3685 of file Nano100Series.h.
| #define SYS_BODCTL_BOD17_INT_EN_Pos (8) |
SYS_T::BODCTL: BOD17_INT_EN Position
Definition at line 3684 of file Nano100Series.h.
| #define SYS_BODCTL_BOD17_RST_EN_Msk (0x1ul << SYS_BODCTL_BOD17_RST_EN_Pos) |
SYS_T::BODCTL: BOD17_RST_EN Mask
Definition at line 3676 of file Nano100Series.h.
| #define SYS_BODCTL_BOD17_RST_EN_Pos (4) |
SYS_T::BODCTL: BOD17_RST_EN Position
Definition at line 3675 of file Nano100Series.h.
| #define SYS_BODCTL_BOD20_EN_Msk (0x1ul << SYS_BODCTL_BOD20_EN_Pos) |
SYS_T::BODCTL: BOD20_EN Mask
Definition at line 3670 of file Nano100Series.h.
| #define SYS_BODCTL_BOD20_EN_Pos (1) |
SYS_T::BODCTL: BOD20_EN Position
Definition at line 3669 of file Nano100Series.h.
| #define SYS_BODCTL_BOD20_INT_EN_Msk (0x1ul << SYS_BODCTL_BOD20_INT_EN_Pos) |
SYS_T::BODCTL: BOD20_INT_EN Mask
Definition at line 3688 of file Nano100Series.h.
| #define SYS_BODCTL_BOD20_INT_EN_Pos (9) |
SYS_T::BODCTL: BOD20_INT_EN Position
Definition at line 3687 of file Nano100Series.h.
| #define SYS_BODCTL_BOD20_RST_EN_Msk (0x1ul << SYS_BODCTL_BOD20_RST_EN_Pos) |
SYS_T::BODCTL: BOD20_RST_EN Mask
Definition at line 3679 of file Nano100Series.h.
| #define SYS_BODCTL_BOD20_RST_EN_Pos (5) |
SYS_T::BODCTL: BOD20_RST_EN Position
Definition at line 3678 of file Nano100Series.h.
| #define SYS_BODCTL_BOD25_EN_Msk (0x1ul << SYS_BODCTL_BOD25_EN_Pos) |
SYS_T::BODCTL: BOD25_EN Mask
Definition at line 3673 of file Nano100Series.h.
| #define SYS_BODCTL_BOD25_EN_Pos (2) |
SYS_T::BODCTL: BOD25_EN Position
Definition at line 3672 of file Nano100Series.h.
| #define SYS_BODCTL_BOD25_INT_EN_Msk (0x1ul << SYS_BODCTL_BOD25_INT_EN_Pos) |
SYS_T::BODCTL: BOD25_INT_EN Mask
Definition at line 3691 of file Nano100Series.h.
| #define SYS_BODCTL_BOD25_INT_EN_Pos (10) |
SYS_T::BODCTL: BOD25_INT_EN Position
Definition at line 3690 of file Nano100Series.h.
| #define SYS_BODCTL_BOD25_RST_EN_Msk (0x1ul << SYS_BODCTL_BOD25_RST_EN_Pos) |
SYS_T::BODCTL: BOD25_RST_EN Mask
Definition at line 3682 of file Nano100Series.h.
| #define SYS_BODCTL_BOD25_RST_EN_Pos (6) |
SYS_T::BODCTL: BOD25_RST_EN Position
Definition at line 3681 of file Nano100Series.h.
| #define SYS_BODSTS_BOD17_OUT_Msk (0x1ul << SYS_BODSTS_BOD17_OUT_Pos) |
SYS_T::BODSTS: BOD17_OUT Mask
Definition at line 3697 of file Nano100Series.h.
| #define SYS_BODSTS_BOD17_OUT_Pos (1) |
SYS_T::BODSTS: BOD17_OUT Position
Definition at line 3696 of file Nano100Series.h.
| #define SYS_BODSTS_BOD20_OUT_Msk (0x1ul << SYS_BODSTS_BOD20_OUT_Pos) |
SYS_T::BODSTS: BOD20_OUT Mask
Definition at line 3700 of file Nano100Series.h.
| #define SYS_BODSTS_BOD20_OUT_Pos (2) |
SYS_T::BODSTS: BOD20_OUT Position
Definition at line 3699 of file Nano100Series.h.
| #define SYS_BODSTS_BOD25_OUT_Msk (0x1ul << SYS_BODSTS_BOD25_OUT_Pos) |
SYS_T::BODSTS: BOD25_OUT Mask
Definition at line 3703 of file Nano100Series.h.
| #define SYS_BODSTS_BOD25_OUT_Pos (3) |
SYS_T::BODSTS: BOD25_OUT Position
Definition at line 3702 of file Nano100Series.h.
| #define SYS_BODSTS_BOD_INT_Msk (0x1ul << SYS_BODSTS_BOD_INT_Pos) |
SYS_T::BODSTS: BOD_INT Mask
Definition at line 3694 of file Nano100Series.h.
| #define SYS_BODSTS_BOD_INT_Pos (0) |
SYS_T::BODSTS: BOD_INT Position
Definition at line 3693 of file Nano100Series.h.
| #define SYS_CPR_HPE_Msk (0x1ul << SYS_CPR_HPE_Pos) |
SYS_T::CPR: HPE Mask
Definition at line 3400 of file Nano100Series.h.
| #define SYS_CPR_HPE_Pos (0) |
SYS_T::CPR: HPE Position
Definition at line 3399 of file Nano100Series.h.
| #define SYS_IPRST_CTL1_CHIP_RST_Msk (0x1ul << SYS_IPRST_CTL1_CHIP_RST_Pos) |
SYS_T::IPRST_CTL1: CHIP_RST Mask
Definition at line 3331 of file Nano100Series.h.
| #define SYS_IPRST_CTL1_CHIP_RST_Pos (0) |
SYS_T::IPRST_CTL1: CHIP_RST Position
Definition at line 3330 of file Nano100Series.h.
| #define SYS_IPRST_CTL1_CPU_RST_Msk (0x1ul << SYS_IPRST_CTL1_CPU_RST_Pos) |
SYS_T::IPRST_CTL1: CPU_RST Mask
Definition at line 3334 of file Nano100Series.h.
| #define SYS_IPRST_CTL1_CPU_RST_Pos (1) |
SYS_T::IPRST_CTL1: CPU_RST Position
Definition at line 3333 of file Nano100Series.h.
| #define SYS_IPRST_CTL1_DMA_RST_Msk (0x1ul << SYS_IPRST_CTL1_DMA_RST_Pos) |
SYS_T::IPRST_CTL1: DMA_RST Mask
Definition at line 3337 of file Nano100Series.h.
| #define SYS_IPRST_CTL1_DMA_RST_Pos (2) |
SYS_T::IPRST_CTL1: DMA_RST Position
Definition at line 3336 of file Nano100Series.h.
| #define SYS_IPRST_CTL1_EBI_RST_Msk (0x1ul << SYS_IPRST_CTL1_EBI_RST_Pos) |
SYS_T::IPRST_CTL1: EBI_RST Mask
Definition at line 3340 of file Nano100Series.h.
| #define SYS_IPRST_CTL1_EBI_RST_Pos (3) |
SYS_T::IPRST_CTL1: EBI_RST Position
Definition at line 3339 of file Nano100Series.h.
| #define SYS_IPRST_CTL2_ADC_RST_Msk (0x1ul << SYS_IPRST_CTL2_ADC_RST_Pos) |
SYS_T::IPRST_CTL2: ADC_RST Mask
Definition at line 3388 of file Nano100Series.h.
| #define SYS_IPRST_CTL2_ADC_RST_Pos (28) |
SYS_T::IPRST_CTL2: ADC_RST Position
Definition at line 3387 of file Nano100Series.h.
| #define SYS_IPRST_CTL2_GPIO_RST_Msk (0x1ul << SYS_IPRST_CTL2_GPIO_RST_Pos) |
SYS_T::IPRST_CTL2: GPIO_RST Mask
Definition at line 3343 of file Nano100Series.h.
| #define SYS_IPRST_CTL2_GPIO_RST_Pos (1) |
SYS_T::IPRST_CTL2: GPIO_RST Position
Definition at line 3342 of file Nano100Series.h.
| #define SYS_IPRST_CTL2_I2C0_RST_Msk (0x1ul << SYS_IPRST_CTL2_I2C0_RST_Pos) |
SYS_T::IPRST_CTL2: I2C0_RST Mask
Definition at line 3358 of file Nano100Series.h.
| #define SYS_IPRST_CTL2_I2C0_RST_Pos (8) |
SYS_T::IPRST_CTL2: I2C0_RST Position
Definition at line 3357 of file Nano100Series.h.
| #define SYS_IPRST_CTL2_I2C1_RST_Msk (0x1ul << SYS_IPRST_CTL2_I2C1_RST_Pos) |
SYS_T::IPRST_CTL2: I2C1_RST Mask
Definition at line 3361 of file Nano100Series.h.
| #define SYS_IPRST_CTL2_I2C1_RST_Pos (9) |
SYS_T::IPRST_CTL2: I2C1_RST Position
Definition at line 3360 of file Nano100Series.h.
| #define SYS_IPRST_CTL2_I2S_RST_Msk (0x1ul << SYS_IPRST_CTL2_I2S_RST_Pos) |
SYS_T::IPRST_CTL2: I2S_RST Mask
Definition at line 3391 of file Nano100Series.h.
| #define SYS_IPRST_CTL2_I2S_RST_Pos (29) |
SYS_T::IPRST_CTL2: I2S_RST Position
Definition at line 3390 of file Nano100Series.h.
| #define SYS_IPRST_CTL2_PWM0_RST_Msk (0x1ul << SYS_IPRST_CTL2_PWM0_RST_Pos) |
SYS_T::IPRST_CTL2: PWM0_RST Mask
Definition at line 3379 of file Nano100Series.h.
| #define SYS_IPRST_CTL2_PWM0_RST_Pos (20) |
SYS_T::IPRST_CTL2: PWM0_RST Position
Definition at line 3378 of file Nano100Series.h.
| #define SYS_IPRST_CTL2_PWM1_RST_Msk (0x1ul << SYS_IPRST_CTL2_PWM1_RST_Pos) |
SYS_T::IPRST_CTL2: PWM1_RST Mask
Definition at line 3382 of file Nano100Series.h.
| #define SYS_IPRST_CTL2_PWM1_RST_Pos (21) |
SYS_T::IPRST_CTL2: PWM1_RST Position
Definition at line 3381 of file Nano100Series.h.
| #define SYS_IPRST_CTL2_SC0_RST_Msk (0x1ul << SYS_IPRST_CTL2_SC0_RST_Pos) |
SYS_T::IPRST_CTL2: SC0_RST Mask
Definition at line 3394 of file Nano100Series.h.
| #define SYS_IPRST_CTL2_SC0_RST_Pos (30) |
SYS_T::IPRST_CTL2: SC0_RST Position
Definition at line 3393 of file Nano100Series.h.
| #define SYS_IPRST_CTL2_SC1_RST_Msk (0x1ul << SYS_IPRST_CTL2_SC1_RST_Pos) |
SYS_T::IPRST_CTL2: SC1_RST Mask
Definition at line 3397 of file Nano100Series.h.
| #define SYS_IPRST_CTL2_SC1_RST_Pos (31) |
SYS_T::IPRST_CTL2: SC1_RST Position
Definition at line 3396 of file Nano100Series.h.
| #define SYS_IPRST_CTL2_SPI0_RST_Msk (0x1ul << SYS_IPRST_CTL2_SPI0_RST_Pos) |
SYS_T::IPRST_CTL2: SPI0_RST Mask
Definition at line 3364 of file Nano100Series.h.
| #define SYS_IPRST_CTL2_SPI0_RST_Pos (12) |
SYS_T::IPRST_CTL2: SPI0_RST Position
Definition at line 3363 of file Nano100Series.h.
| #define SYS_IPRST_CTL2_SPI1_RST_Msk (0x1ul << SYS_IPRST_CTL2_SPI1_RST_Pos) |
SYS_T::IPRST_CTL2: SPI1_RST Mask
Definition at line 3367 of file Nano100Series.h.
| #define SYS_IPRST_CTL2_SPI1_RST_Pos (13) |
SYS_T::IPRST_CTL2: SPI1_RST Position
Definition at line 3366 of file Nano100Series.h.
| #define SYS_IPRST_CTL2_SPI2_RST_Msk (0x1ul << SYS_IPRST_CTL2_SPI2_RST_Pos) |
SYS_T::IPRST_CTL2: SPI2_RST Mask
Definition at line 3370 of file Nano100Series.h.
| #define SYS_IPRST_CTL2_SPI2_RST_Pos (14) |
SYS_T::IPRST_CTL2: SPI2_RST Position
Definition at line 3369 of file Nano100Series.h.
| #define SYS_IPRST_CTL2_TMR0_RST_Msk (0x1ul << SYS_IPRST_CTL2_TMR0_RST_Pos) |
SYS_T::IPRST_CTL2: TMR0_RST Mask
Definition at line 3346 of file Nano100Series.h.
| #define SYS_IPRST_CTL2_TMR0_RST_Pos (2) |
SYS_T::IPRST_CTL2: TMR0_RST Position
Definition at line 3345 of file Nano100Series.h.
| #define SYS_IPRST_CTL2_TMR1_RST_Msk (0x1ul << SYS_IPRST_CTL2_TMR1_RST_Pos) |
SYS_T::IPRST_CTL2: TMR1_RST Mask
Definition at line 3349 of file Nano100Series.h.
| #define SYS_IPRST_CTL2_TMR1_RST_Pos (3) |
SYS_T::IPRST_CTL2: TMR1_RST Position
Definition at line 3348 of file Nano100Series.h.
| #define SYS_IPRST_CTL2_TMR2_RST_Msk (0x1ul << SYS_IPRST_CTL2_TMR2_RST_Pos) |
SYS_T::IPRST_CTL2: TMR2_RST Mask
Definition at line 3352 of file Nano100Series.h.
| #define SYS_IPRST_CTL2_TMR2_RST_Pos (4) |
SYS_T::IPRST_CTL2: TMR2_RST Position
Definition at line 3351 of file Nano100Series.h.
| #define SYS_IPRST_CTL2_TMR3_RST_Msk (0x1ul << SYS_IPRST_CTL2_TMR3_RST_Pos) |
SYS_T::IPRST_CTL2: TMR3_RST Mask
Definition at line 3355 of file Nano100Series.h.
| #define SYS_IPRST_CTL2_TMR3_RST_Pos (5) |
SYS_T::IPRST_CTL2: TMR3_RST Position
Definition at line 3354 of file Nano100Series.h.
| #define SYS_IPRST_CTL2_UART0_RST_Msk (0x1ul << SYS_IPRST_CTL2_UART0_RST_Pos) |
SYS_T::IPRST_CTL2: UART0_RST Mask
Definition at line 3373 of file Nano100Series.h.
| #define SYS_IPRST_CTL2_UART0_RST_Pos (16) |
SYS_T::IPRST_CTL2: UART0_RST Position
Definition at line 3372 of file Nano100Series.h.
| #define SYS_IPRST_CTL2_UART1_RST_Msk (0x1ul << SYS_IPRST_CTL2_UART1_RST_Pos) |
SYS_T::IPRST_CTL2: UART1_RST Mask
Definition at line 3376 of file Nano100Series.h.
| #define SYS_IPRST_CTL2_UART1_RST_Pos (17) |
SYS_T::IPRST_CTL2: UART1_RST Position
Definition at line 3375 of file Nano100Series.h.
| #define SYS_IPRST_CTL2_USBD_RST_Msk (0x1ul << SYS_IPRST_CTL2_USBD_RST_Pos) |
SYS_T::IPRST_CTL2: USBD_RST Mask
Definition at line 3385 of file Nano100Series.h.
| #define SYS_IPRST_CTL2_USBD_RST_Pos (27) |
SYS_T::IPRST_CTL2: USBD_RST Position
Definition at line 3384 of file Nano100Series.h.
| #define SYS_IRCTRIMCTL_TRIM_LOOP_Msk (0x3ul << SYS_IRCTRIMCTL_TRIM_LOOP_Pos) |
SYS_T::IRCTRIMCTL: TRIM_LOOP Mask
Definition at line 3721 of file Nano100Series.h.
| #define SYS_IRCTRIMCTL_TRIM_LOOP_Pos (4) |
SYS_T::IRCTRIMCTL: TRIM_LOOP Position
Definition at line 3720 of file Nano100Series.h.
| #define SYS_IRCTRIMCTL_TRIM_RETRY_CNT_Msk (0x3ul << SYS_IRCTRIMCTL_TRIM_RETRY_CNT_Pos) |
SYS_T::IRCTRIMCTL: TRIM_RETRY_CNT Mask
Definition at line 3724 of file Nano100Series.h.
| #define SYS_IRCTRIMCTL_TRIM_RETRY_CNT_Pos (6) |
SYS_T::IRCTRIMCTL: TRIM_RETRY_CNT Position
Definition at line 3723 of file Nano100Series.h.
| #define SYS_IRCTRIMCTL_TRIM_SEL_Msk (0x3ul << SYS_IRCTRIMCTL_TRIM_SEL_Pos) |
SYS_T::IRCTRIMCTL: TRIM_SEL Mask
Definition at line 3718 of file Nano100Series.h.
| #define SYS_IRCTRIMCTL_TRIM_SEL_Pos (0) |
SYS_T::IRCTRIMCTL: TRIM_SEL Position
Definition at line 3717 of file Nano100Series.h.
| #define SYS_IRCTRIMIEN_32K_ERR_IEN_Msk (0x1ul << SYS_IRCTRIMIEN_32K_ERR_IEN_Pos) |
SYS_T::IRCTRIMIEN: 32K_ERR_IEN Mask
Definition at line 3730 of file Nano100Series.h.
| #define SYS_IRCTRIMIEN_32K_ERR_IEN_Pos (2) |
SYS_T::IRCTRIMIEN: 32K_ERR_IEN Position
Definition at line 3729 of file Nano100Series.h.
| #define SYS_IRCTRIMIEN_TRIM_FAIL_IEN_Msk (0x1ul << SYS_IRCTRIMIEN_TRIM_FAIL_IEN_Pos) |
SYS_T::IRCTRIMIEN: TRIM_FAIL_IEN Mask
Definition at line 3727 of file Nano100Series.h.
| #define SYS_IRCTRIMIEN_TRIM_FAIL_IEN_Pos (1) |
SYS_T::IRCTRIMIEN: TRIM_FAIL_IEN Position
Definition at line 3726 of file Nano100Series.h.
| #define SYS_IRCTRIMINT_32K_ERR_INT_Msk (0x1ul << SYS_IRCTRIMINT_32K_ERR_INT_Pos) |
SYS_T::IRCTRIMINT: 32K_ERR_INT Mask
Definition at line 3739 of file Nano100Series.h.
| #define SYS_IRCTRIMINT_32K_ERR_INT_Pos (2) |
SYS_T::IRCTRIMINT: 32K_ERR_INT Position
Definition at line 3738 of file Nano100Series.h.
| #define SYS_IRCTRIMINT_FREQ_LOCK_Msk (0x1ul << SYS_IRCTRIMINT_FREQ_LOCK_Pos) |
SYS_T::IRCTRIMINT: FREQ_LOCK Mask
Definition at line 3733 of file Nano100Series.h.
| #define SYS_IRCTRIMINT_FREQ_LOCK_Pos (0) |
SYS_T::IRCTRIMINT: FREQ_LOCK Position
Definition at line 3732 of file Nano100Series.h.
| #define SYS_IRCTRIMINT_TRIM_FAIL_INT_Msk (0x1ul << SYS_IRCTRIMINT_TRIM_FAIL_INT_Pos) |
SYS_T::IRCTRIMINT: TRIM_FAIL_INT Mask
Definition at line 3736 of file Nano100Series.h.
| #define SYS_IRCTRIMINT_TRIM_FAIL_INT_Pos (1) |
SYS_T::IRCTRIMINT: TRIM_FAIL_INT Position
Definition at line 3735 of file Nano100Series.h.
| #define SYS_PA_H_MFP_PA10_MFP_Msk (0x7ul << SYS_PA_H_MFP_PA10_MFP_Pos) |
SYS_T::PA_H_MFP: PA10_MFP Mask
Definition at line 3436 of file Nano100Series.h.
| #define SYS_PA_H_MFP_PA10_MFP_Pos (8) |
SYS_T::PA_H_MFP: PA10_MFP Position
Definition at line 3435 of file Nano100Series.h.
| #define SYS_PA_H_MFP_PA11_MFP_Msk (0x7ul << SYS_PA_H_MFP_PA11_MFP_Pos) |
SYS_T::PA_H_MFP: PA11_MFP Mask
Definition at line 3439 of file Nano100Series.h.
| #define SYS_PA_H_MFP_PA11_MFP_Pos (12) |
SYS_T::PA_H_MFP: PA11_MFP Position
Definition at line 3438 of file Nano100Series.h.
| #define SYS_PA_H_MFP_PA12_MFP_Msk (0x7ul << SYS_PA_H_MFP_PA12_MFP_Pos) |
SYS_T::PA_H_MFP: PA12_MFP Mask
Definition at line 3442 of file Nano100Series.h.
| #define SYS_PA_H_MFP_PA12_MFP_Pos (16) |
SYS_T::PA_H_MFP: PA12_MFP Position
Definition at line 3441 of file Nano100Series.h.
| #define SYS_PA_H_MFP_PA13_MFP_Msk (0x7ul << SYS_PA_H_MFP_PA13_MFP_Pos) |
SYS_T::PA_H_MFP: PA13_MFP Mask
Definition at line 3445 of file Nano100Series.h.
| #define SYS_PA_H_MFP_PA13_MFP_Pos (20) |
SYS_T::PA_H_MFP: PA13_MFP Position
Definition at line 3444 of file Nano100Series.h.
| #define SYS_PA_H_MFP_PA14_MFP_Msk (0x7ul << SYS_PA_H_MFP_PA14_MFP_Pos) |
SYS_T::PA_H_MFP: PA14_MFP Mask
Definition at line 3448 of file Nano100Series.h.
| #define SYS_PA_H_MFP_PA14_MFP_Pos (24) |
SYS_T::PA_H_MFP: PA14_MFP Position
Definition at line 3447 of file Nano100Series.h.
| #define SYS_PA_H_MFP_PA15_MFP_Msk (0x7ul << SYS_PA_H_MFP_PA15_MFP_Pos) |
SYS_T::PA_H_MFP: PA15_MFP Mask
Definition at line 3451 of file Nano100Series.h.
| #define SYS_PA_H_MFP_PA15_MFP_Pos (28) |
SYS_T::PA_H_MFP: PA15_MFP Position
Definition at line 3450 of file Nano100Series.h.
| #define SYS_PA_H_MFP_PA8_MFP_Msk (0x7ul << SYS_PA_H_MFP_PA8_MFP_Pos) |
SYS_T::PA_H_MFP: PA8_MFP Mask
Definition at line 3430 of file Nano100Series.h.
| #define SYS_PA_H_MFP_PA8_MFP_Pos (0) |
SYS_T::PA_H_MFP: PA8_MFP Position
Definition at line 3429 of file Nano100Series.h.
| #define SYS_PA_H_MFP_PA9_MFP_Msk (0x7ul << SYS_PA_H_MFP_PA9_MFP_Pos) |
SYS_T::PA_H_MFP: PA9_MFP Mask
Definition at line 3433 of file Nano100Series.h.
| #define SYS_PA_H_MFP_PA9_MFP_Pos (4) |
SYS_T::PA_H_MFP: PA9_MFP Position
Definition at line 3432 of file Nano100Series.h.
| #define SYS_PA_L_MFP_PA0_MFP_Msk (0x7ul << SYS_PA_L_MFP_PA0_MFP_Pos) |
SYS_T::PA_L_MFP: PA0_MFP Mask
Definition at line 3406 of file Nano100Series.h.
| #define SYS_PA_L_MFP_PA0_MFP_Pos (0) |
SYS_T::PA_L_MFP: PA0_MFP Position
Definition at line 3405 of file Nano100Series.h.
| #define SYS_PA_L_MFP_PA1_MFP_Msk (0x7ul << SYS_PA_L_MFP_PA1_MFP_Pos) |
SYS_T::PA_L_MFP: PA1_MFP Mask
Definition at line 3409 of file Nano100Series.h.
| #define SYS_PA_L_MFP_PA1_MFP_Pos (4) |
SYS_T::PA_L_MFP: PA1_MFP Position
Definition at line 3408 of file Nano100Series.h.
| #define SYS_PA_L_MFP_PA2_MFP_Msk (0x7ul << SYS_PA_L_MFP_PA2_MFP_Pos) |
SYS_T::PA_L_MFP: PA2_MFP Mask
Definition at line 3412 of file Nano100Series.h.
| #define SYS_PA_L_MFP_PA2_MFP_Pos (8) |
SYS_T::PA_L_MFP: PA2_MFP Position
Definition at line 3411 of file Nano100Series.h.
| #define SYS_PA_L_MFP_PA3_MFP_Msk (0x7ul << SYS_PA_L_MFP_PA3_MFP_Pos) |
SYS_T::PA_L_MFP: PA3_MFP Mask
Definition at line 3415 of file Nano100Series.h.
| #define SYS_PA_L_MFP_PA3_MFP_Pos (12) |
SYS_T::PA_L_MFP: PA3_MFP Position
Definition at line 3414 of file Nano100Series.h.
| #define SYS_PA_L_MFP_PA4_MFP_Msk (0x7ul << SYS_PA_L_MFP_PA4_MFP_Pos) |
SYS_T::PA_L_MFP: PA4_MFP Mask
Definition at line 3418 of file Nano100Series.h.
| #define SYS_PA_L_MFP_PA4_MFP_Pos (16) |
SYS_T::PA_L_MFP: PA4_MFP Position
Definition at line 3417 of file Nano100Series.h.
| #define SYS_PA_L_MFP_PA5_MFP_Msk (0x7ul << SYS_PA_L_MFP_PA5_MFP_Pos) |
SYS_T::PA_L_MFP: PA5_MFP Mask
Definition at line 3421 of file Nano100Series.h.
| #define SYS_PA_L_MFP_PA5_MFP_Pos (20) |
SYS_T::PA_L_MFP: PA5_MFP Position
Definition at line 3420 of file Nano100Series.h.
| #define SYS_PA_L_MFP_PA6_MFP_Msk (0x7ul << SYS_PA_L_MFP_PA6_MFP_Pos) |
SYS_T::PA_L_MFP: PA6_MFP Mask
Definition at line 3424 of file Nano100Series.h.
| #define SYS_PA_L_MFP_PA6_MFP_Pos (24) |
SYS_T::PA_L_MFP: PA6_MFP Position
Definition at line 3423 of file Nano100Series.h.
| #define SYS_PA_L_MFP_PA7_MFP_Msk (0x7ul << SYS_PA_L_MFP_PA7_MFP_Pos) |
SYS_T::PA_L_MFP: PA7_MFP Mask
Definition at line 3427 of file Nano100Series.h.
| #define SYS_PA_L_MFP_PA7_MFP_Pos (28) |
SYS_T::PA_L_MFP: PA7_MFP Position
Definition at line 3426 of file Nano100Series.h.
| #define SYS_PB_H_MFP_PB10_MFP_Msk (0x7ul << SYS_PB_H_MFP_PB10_MFP_Pos) |
SYS_T::PB_H_MFP: PB10_MFP Mask
Definition at line 3484 of file Nano100Series.h.
| #define SYS_PB_H_MFP_PB10_MFP_Pos (8) |
SYS_T::PB_H_MFP: PB10_MFP Position
Definition at line 3483 of file Nano100Series.h.
| #define SYS_PB_H_MFP_PB11_MFP_Msk (0x7ul << SYS_PB_H_MFP_PB11_MFP_Pos) |
SYS_T::PB_H_MFP: PB11_MFP Mask
Definition at line 3487 of file Nano100Series.h.
| #define SYS_PB_H_MFP_PB11_MFP_Pos (12) |
SYS_T::PB_H_MFP: PB11_MFP Position
Definition at line 3486 of file Nano100Series.h.
| #define SYS_PB_H_MFP_PB12_MFP_Msk (0x7ul << SYS_PB_H_MFP_PB12_MFP_Pos) |
SYS_T::PB_H_MFP: PB12_MFP Mask
Definition at line 3490 of file Nano100Series.h.
| #define SYS_PB_H_MFP_PB12_MFP_Pos (16) |
SYS_T::PB_H_MFP: PB12_MFP Position
Definition at line 3489 of file Nano100Series.h.
| #define SYS_PB_H_MFP_PB13_MFP_Msk (0x7ul << SYS_PB_H_MFP_PB13_MFP_Pos) |
SYS_T::PB_H_MFP: PB13_MFP Mask
Definition at line 3493 of file Nano100Series.h.
| #define SYS_PB_H_MFP_PB13_MFP_Pos (20) |
SYS_T::PB_H_MFP: PB13_MFP Position
Definition at line 3492 of file Nano100Series.h.
| #define SYS_PB_H_MFP_PB14_MFP_Msk (0x7ul << SYS_PB_H_MFP_PB14_MFP_Pos) |
SYS_T::PB_H_MFP: PB14_MFP Mask
Definition at line 3496 of file Nano100Series.h.
| #define SYS_PB_H_MFP_PB14_MFP_Pos (24) |
SYS_T::PB_H_MFP: PB14_MFP Position
Definition at line 3495 of file Nano100Series.h.
| #define SYS_PB_H_MFP_PB15_MFP_Msk (0x7ul << SYS_PB_H_MFP_PB15_MFP_Pos) |
SYS_T::PB_H_MFP: PB15_MFP Mask
Definition at line 3499 of file Nano100Series.h.
| #define SYS_PB_H_MFP_PB15_MFP_Pos (28) |
SYS_T::PB_H_MFP: PB15_MFP Position
Definition at line 3498 of file Nano100Series.h.
| #define SYS_PB_H_MFP_PB8_MFP_Msk (0x7ul << SYS_PB_H_MFP_PB8_MFP_Pos) |
SYS_T::PB_H_MFP: PB8_MFP Mask
Definition at line 3478 of file Nano100Series.h.
| #define SYS_PB_H_MFP_PB8_MFP_Pos (0) |
SYS_T::PB_H_MFP: PB8_MFP Position
Definition at line 3477 of file Nano100Series.h.
| #define SYS_PB_H_MFP_PB9_MFP_Msk (0x7ul << SYS_PB_H_MFP_PB9_MFP_Pos) |
SYS_T::PB_H_MFP: PB9_MFP Mask
Definition at line 3481 of file Nano100Series.h.
| #define SYS_PB_H_MFP_PB9_MFP_Pos (4) |
SYS_T::PB_H_MFP: PB9_MFP Position
Definition at line 3480 of file Nano100Series.h.
| #define SYS_PB_L_MFP_PB0_MFP_Msk (0x7ul << SYS_PB_L_MFP_PB0_MFP_Pos) |
SYS_T::PB_L_MFP: PB0_MFP Mask
Definition at line 3454 of file Nano100Series.h.
| #define SYS_PB_L_MFP_PB0_MFP_Pos (0) |
SYS_T::PB_L_MFP: PB0_MFP Position
Definition at line 3453 of file Nano100Series.h.
| #define SYS_PB_L_MFP_PB1_MFP_Msk (0x7ul << SYS_PB_L_MFP_PB1_MFP_Pos) |
SYS_T::PB_L_MFP: PB1_MFP Mask
Definition at line 3457 of file Nano100Series.h.
| #define SYS_PB_L_MFP_PB1_MFP_Pos (4) |
SYS_T::PB_L_MFP: PB1_MFP Position
Definition at line 3456 of file Nano100Series.h.
| #define SYS_PB_L_MFP_PB2_MFP_Msk (0x7ul << SYS_PB_L_MFP_PB2_MFP_Pos) |
SYS_T::PB_L_MFP: PB2_MFP Mask
Definition at line 3460 of file Nano100Series.h.
| #define SYS_PB_L_MFP_PB2_MFP_Pos (8) |
SYS_T::PB_L_MFP: PB2_MFP Position
Definition at line 3459 of file Nano100Series.h.
| #define SYS_PB_L_MFP_PB3_MFP_Msk (0x7ul << SYS_PB_L_MFP_PB3_MFP_Pos) |
SYS_T::PB_L_MFP: PB3_MFP Mask
Definition at line 3463 of file Nano100Series.h.
| #define SYS_PB_L_MFP_PB3_MFP_Pos (12) |
SYS_T::PB_L_MFP: PB3_MFP Position
Definition at line 3462 of file Nano100Series.h.
| #define SYS_PB_L_MFP_PB4_MFP_Msk (0x7ul << SYS_PB_L_MFP_PB4_MFP_Pos) |
SYS_T::PB_L_MFP: PB4_MFP Mask
Definition at line 3466 of file Nano100Series.h.
| #define SYS_PB_L_MFP_PB4_MFP_Pos (16) |
SYS_T::PB_L_MFP: PB4_MFP Position
Definition at line 3465 of file Nano100Series.h.
| #define SYS_PB_L_MFP_PB5_MFP_Msk (0x7ul << SYS_PB_L_MFP_PB5_MFP_Pos) |
SYS_T::PB_L_MFP: PB5_MFP Mask
Definition at line 3469 of file Nano100Series.h.
| #define SYS_PB_L_MFP_PB5_MFP_Pos (20) |
SYS_T::PB_L_MFP: PB5_MFP Position
Definition at line 3468 of file Nano100Series.h.
| #define SYS_PB_L_MFP_PB6_MFP_Msk (0x7ul << SYS_PB_L_MFP_PB6_MFP_Pos) |
SYS_T::PB_L_MFP: PB6_MFP Mask
Definition at line 3472 of file Nano100Series.h.
| #define SYS_PB_L_MFP_PB6_MFP_Pos (24) |
SYS_T::PB_L_MFP: PB6_MFP Position
Definition at line 3471 of file Nano100Series.h.
| #define SYS_PB_L_MFP_PB7_MFP_Msk (0x7ul << SYS_PB_L_MFP_PB7_MFP_Pos) |
SYS_T::PB_L_MFP: PB7_MFP Mask
Definition at line 3475 of file Nano100Series.h.
| #define SYS_PB_L_MFP_PB7_MFP_Pos (28) |
SYS_T::PB_L_MFP: PB7_MFP Position
Definition at line 3474 of file Nano100Series.h.
| #define SYS_PC_H_MFP_PC10_MFP_Msk (0x7ul << SYS_PC_H_MFP_PC10_MFP_Pos) |
SYS_T::PC_H_MFP: PC10_MFP Mask
Definition at line 3532 of file Nano100Series.h.
| #define SYS_PC_H_MFP_PC10_MFP_Pos (8) |
SYS_T::PC_H_MFP: PC10_MFP Position
Definition at line 3531 of file Nano100Series.h.
| #define SYS_PC_H_MFP_PC11_MFP_Msk (0x7ul << SYS_PC_H_MFP_PC11_MFP_Pos) |
SYS_T::PC_H_MFP: PC11_MFP Mask
Definition at line 3535 of file Nano100Series.h.
| #define SYS_PC_H_MFP_PC11_MFP_Pos (12) |
SYS_T::PC_H_MFP: PC11_MFP Position
Definition at line 3534 of file Nano100Series.h.
| #define SYS_PC_H_MFP_PC12_MFP_Msk (0x7ul << SYS_PC_H_MFP_PC12_MFP_Pos) |
SYS_T::PC_H_MFP: PC12_MFP Mask
Definition at line 3538 of file Nano100Series.h.
| #define SYS_PC_H_MFP_PC12_MFP_Pos (16) |
SYS_T::PC_H_MFP: PC12_MFP Position
Definition at line 3537 of file Nano100Series.h.
| #define SYS_PC_H_MFP_PC13_MFP_Msk (0x7ul << SYS_PC_H_MFP_PC13_MFP_Pos) |
SYS_T::PC_H_MFP: PC13_MFP Mask
Definition at line 3541 of file Nano100Series.h.
| #define SYS_PC_H_MFP_PC13_MFP_Pos (20) |
SYS_T::PC_H_MFP: PC13_MFP Position
Definition at line 3540 of file Nano100Series.h.
| #define SYS_PC_H_MFP_PC14_MFP_Msk (0x7ul << SYS_PC_H_MFP_PC14_MFP_Pos) |
SYS_T::PC_H_MFP: PC14_MFP Mask
Definition at line 3544 of file Nano100Series.h.
| #define SYS_PC_H_MFP_PC14_MFP_Pos (24) |
SYS_T::PC_H_MFP: PC14_MFP Position
Definition at line 3543 of file Nano100Series.h.
| #define SYS_PC_H_MFP_PC15_MFP_Msk (0x7ul << SYS_PC_H_MFP_PC15_MFP_Pos) |
SYS_T::PC_H_MFP: PC15_MFP Mask
Definition at line 3547 of file Nano100Series.h.
| #define SYS_PC_H_MFP_PC15_MFP_Pos (28) |
SYS_T::PC_H_MFP: PC15_MFP Position
Definition at line 3546 of file Nano100Series.h.
| #define SYS_PC_H_MFP_PC8_MFP_Msk (0x7ul << SYS_PC_H_MFP_PC8_MFP_Pos) |
SYS_T::PC_H_MFP: PC8_MFP Mask
Definition at line 3526 of file Nano100Series.h.
| #define SYS_PC_H_MFP_PC8_MFP_Pos (0) |
SYS_T::PC_H_MFP: PC8_MFP Position
Definition at line 3525 of file Nano100Series.h.
| #define SYS_PC_H_MFP_PC9_MFP_Msk (0x7ul << SYS_PC_H_MFP_PC9_MFP_Pos) |
SYS_T::PC_H_MFP: PC9_MFP Mask
Definition at line 3529 of file Nano100Series.h.
| #define SYS_PC_H_MFP_PC9_MFP_Pos (4) |
SYS_T::PC_H_MFP: PC9_MFP Position
Definition at line 3528 of file Nano100Series.h.
| #define SYS_PC_L_MFP_PC0_MFP_Msk (0x7ul << SYS_PC_L_MFP_PC0_MFP_Pos) |
SYS_T::PC_L_MFP: PC0_MFP Mask
Definition at line 3502 of file Nano100Series.h.
| #define SYS_PC_L_MFP_PC0_MFP_Pos (0) |
SYS_T::PC_L_MFP: PC0_MFP Position
Definition at line 3501 of file Nano100Series.h.
| #define SYS_PC_L_MFP_PC1_MFP_Msk (0x7ul << SYS_PC_L_MFP_PC1_MFP_Pos) |
SYS_T::PC_L_MFP: PC1_MFP Mask
Definition at line 3505 of file Nano100Series.h.
| #define SYS_PC_L_MFP_PC1_MFP_Pos (4) |
SYS_T::PC_L_MFP: PC1_MFP Position
Definition at line 3504 of file Nano100Series.h.
| #define SYS_PC_L_MFP_PC2_MFP_Msk (0x7ul << SYS_PC_L_MFP_PC2_MFP_Pos) |
SYS_T::PC_L_MFP: PC2_MFP Mask
Definition at line 3508 of file Nano100Series.h.
| #define SYS_PC_L_MFP_PC2_MFP_Pos (8) |
SYS_T::PC_L_MFP: PC2_MFP Position
Definition at line 3507 of file Nano100Series.h.
| #define SYS_PC_L_MFP_PC3_MFP_Msk (0x7ul << SYS_PC_L_MFP_PC3_MFP_Pos) |
SYS_T::PC_L_MFP: PC3_MFP Mask
Definition at line 3511 of file Nano100Series.h.
| #define SYS_PC_L_MFP_PC3_MFP_Pos (12) |
SYS_T::PC_L_MFP: PC3_MFP Position
Definition at line 3510 of file Nano100Series.h.
| #define SYS_PC_L_MFP_PC4_MFP_Msk (0x7ul << SYS_PC_L_MFP_PC4_MFP_Pos) |
SYS_T::PC_L_MFP: PC4_MFP Mask
Definition at line 3514 of file Nano100Series.h.
| #define SYS_PC_L_MFP_PC4_MFP_Pos (16) |
SYS_T::PC_L_MFP: PC4_MFP Position
Definition at line 3513 of file Nano100Series.h.
| #define SYS_PC_L_MFP_PC5_MFP_Msk (0x7ul << SYS_PC_L_MFP_PC5_MFP_Pos) |
SYS_T::PC_L_MFP: PC5_MFP Mask
Definition at line 3517 of file Nano100Series.h.
| #define SYS_PC_L_MFP_PC5_MFP_Pos (20) |
SYS_T::PC_L_MFP: PC5_MFP Position
Definition at line 3516 of file Nano100Series.h.
| #define SYS_PC_L_MFP_PC6_MFP_Msk (0x7ul << SYS_PC_L_MFP_PC6_MFP_Pos) |
SYS_T::PC_L_MFP: PC6_MFP Mask
Definition at line 3520 of file Nano100Series.h.
| #define SYS_PC_L_MFP_PC6_MFP_Pos (24) |
SYS_T::PC_L_MFP: PC6_MFP Position
Definition at line 3519 of file Nano100Series.h.
| #define SYS_PC_L_MFP_PC7_MFP_Msk (0x7ul << SYS_PC_L_MFP_PC7_MFP_Pos) |
SYS_T::PC_L_MFP: PC7_MFP Mask
Definition at line 3523 of file Nano100Series.h.
| #define SYS_PC_L_MFP_PC7_MFP_Pos (28) |
SYS_T::PC_L_MFP: PC7_MFP Position
Definition at line 3522 of file Nano100Series.h.
| #define SYS_PD_H_MFP_PD10_MFP_Msk (0x7ul << SYS_PD_H_MFP_PD10_MFP_Pos) |
SYS_T::PD_H_MFP: PD10_MFP Mask
Definition at line 3580 of file Nano100Series.h.
| #define SYS_PD_H_MFP_PD10_MFP_Pos (8) |
SYS_T::PD_H_MFP: PD10_MFP Position
Definition at line 3579 of file Nano100Series.h.
| #define SYS_PD_H_MFP_PD11_MFP_Msk (0x7ul << SYS_PD_H_MFP_PD11_MFP_Pos) |
SYS_T::PD_H_MFP: PD11_MFP Mask
Definition at line 3583 of file Nano100Series.h.
| #define SYS_PD_H_MFP_PD11_MFP_Pos (12) |
SYS_T::PD_H_MFP: PD11_MFP Position
Definition at line 3582 of file Nano100Series.h.
| #define SYS_PD_H_MFP_PD12_MFP_Msk (0x7ul << SYS_PD_H_MFP_PD12_MFP_Pos) |
SYS_T::PD_H_MFP: PD12_MFP Mask
Definition at line 3586 of file Nano100Series.h.
| #define SYS_PD_H_MFP_PD12_MFP_Pos (16) |
SYS_T::PD_H_MFP: PD12_MFP Position
Definition at line 3585 of file Nano100Series.h.
| #define SYS_PD_H_MFP_PD13_MFP_Msk (0x7ul << SYS_PD_H_MFP_PD13_MFP_Pos) |
SYS_T::PD_H_MFP: PD13_MFP Mask
Definition at line 3589 of file Nano100Series.h.
| #define SYS_PD_H_MFP_PD13_MFP_Pos (20) |
SYS_T::PD_H_MFP: PD13_MFP Position
Definition at line 3588 of file Nano100Series.h.
| #define SYS_PD_H_MFP_PD14_MFP_Msk (0x7ul << SYS_PD_H_MFP_PD14_MFP_Pos) |
SYS_T::PD_H_MFP: PD14_MFP Mask
Definition at line 3592 of file Nano100Series.h.
| #define SYS_PD_H_MFP_PD14_MFP_Pos (24) |
SYS_T::PD_H_MFP: PD14_MFP Position
Definition at line 3591 of file Nano100Series.h.
| #define SYS_PD_H_MFP_PD15_MFP_Msk (0x7ul << SYS_PD_H_MFP_PD15_MFP_Pos) |
SYS_T::PD_H_MFP: PD15_MFP Mask
Definition at line 3595 of file Nano100Series.h.
| #define SYS_PD_H_MFP_PD15_MFP_Pos (28) |
SYS_T::PD_H_MFP: PD15_MFP Position
Definition at line 3594 of file Nano100Series.h.
| #define SYS_PD_H_MFP_PD8_MFP_Msk (0x7ul << SYS_PD_H_MFP_PD8_MFP_Pos) |
SYS_T::PD_H_MFP: PD8_MFP Mask
Definition at line 3574 of file Nano100Series.h.
| #define SYS_PD_H_MFP_PD8_MFP_Pos (0) |
SYS_T::PD_H_MFP: PD8_MFP Position
Definition at line 3573 of file Nano100Series.h.
| #define SYS_PD_H_MFP_PD9_MFP_Msk (0x7ul << SYS_PD_H_MFP_PD9_MFP_Pos) |
SYS_T::PD_H_MFP: PD9_MFP Mask
Definition at line 3577 of file Nano100Series.h.
| #define SYS_PD_H_MFP_PD9_MFP_Pos (4) |
SYS_T::PD_H_MFP: PD9_MFP Position
Definition at line 3576 of file Nano100Series.h.
| #define SYS_PD_L_MFP_PD0_MFP_Msk (0x7ul << SYS_PD_L_MFP_PD0_MFP_Pos) |
SYS_T::PD_L_MFP: PD0_MFP Mask
Definition at line 3550 of file Nano100Series.h.
| #define SYS_PD_L_MFP_PD0_MFP_Pos (0) |
SYS_T::PD_L_MFP: PD0_MFP Position
Definition at line 3549 of file Nano100Series.h.
| #define SYS_PD_L_MFP_PD1_MFP_Msk (0x7ul << SYS_PD_L_MFP_PD1_MFP_Pos) |
SYS_T::PD_L_MFP: PD1_MFP Mask
Definition at line 3553 of file Nano100Series.h.
| #define SYS_PD_L_MFP_PD1_MFP_Pos (4) |
SYS_T::PD_L_MFP: PD1_MFP Position
Definition at line 3552 of file Nano100Series.h.
| #define SYS_PD_L_MFP_PD2_MFP_Msk (0x7ul << SYS_PD_L_MFP_PD2_MFP_Pos) |
SYS_T::PD_L_MFP: PD2_MFP Mask
Definition at line 3556 of file Nano100Series.h.
| #define SYS_PD_L_MFP_PD2_MFP_Pos (8) |
SYS_T::PD_L_MFP: PD2_MFP Position
Definition at line 3555 of file Nano100Series.h.
| #define SYS_PD_L_MFP_PD3_MFP_Msk (0x7ul << SYS_PD_L_MFP_PD3_MFP_Pos) |
SYS_T::PD_L_MFP: PD3_MFP Mask
Definition at line 3559 of file Nano100Series.h.
| #define SYS_PD_L_MFP_PD3_MFP_Pos (12) |
SYS_T::PD_L_MFP: PD3_MFP Position
Definition at line 3558 of file Nano100Series.h.
| #define SYS_PD_L_MFP_PD4_MFP_Msk (0x7ul << SYS_PD_L_MFP_PD4_MFP_Pos) |
SYS_T::PD_L_MFP: PD4_MFP Mask
Definition at line 3562 of file Nano100Series.h.
| #define SYS_PD_L_MFP_PD4_MFP_Pos (16) |
SYS_T::PD_L_MFP: PD4_MFP Position
Definition at line 3561 of file Nano100Series.h.
| #define SYS_PD_L_MFP_PD5_MFP_Msk (0x7ul << SYS_PD_L_MFP_PD5_MFP_Pos) |
SYS_T::PD_L_MFP: PD5_MFP Mask
Definition at line 3565 of file Nano100Series.h.
| #define SYS_PD_L_MFP_PD5_MFP_Pos (20) |
SYS_T::PD_L_MFP: PD5_MFP Position
Definition at line 3564 of file Nano100Series.h.
| #define SYS_PD_L_MFP_PD6_MFP_Msk (0x7ul << SYS_PD_L_MFP_PD6_MFP_Pos) |
SYS_T::PD_L_MFP: PD6_MFP Mask
Definition at line 3568 of file Nano100Series.h.
| #define SYS_PD_L_MFP_PD6_MFP_Pos (24) |
SYS_T::PD_L_MFP: PD6_MFP Position
Definition at line 3567 of file Nano100Series.h.
| #define SYS_PD_L_MFP_PD7_MFP_Msk (0x7ul << SYS_PD_L_MFP_PD7_MFP_Pos) |
SYS_T::PD_L_MFP: PD7_MFP Mask
Definition at line 3571 of file Nano100Series.h.
| #define SYS_PD_L_MFP_PD7_MFP_Pos (28) |
SYS_T::PD_L_MFP: PD7_MFP Position
Definition at line 3570 of file Nano100Series.h.
| #define SYS_PDID_PDID_Msk (0xfffffffful << SYS_PDID_PDID_Pos) |
SYS_T::PDID: PDID Mask
Definition at line 3310 of file Nano100Series.h.
| #define SYS_PDID_PDID_Pos (0) |
@addtogroup SYS_CONST GCR Bit Field Definition Constant Definitions for GCR Controller
SYS_T::PDID: PDID Position
Definition at line 3309 of file Nano100Series.h.
| #define SYS_PE_H_MFP_PE10_MFP_Msk (0x7ul << SYS_PE_H_MFP_PE10_MFP_Pos) |
SYS_T::PE_H_MFP: PE10_MFP Mask
Definition at line 3628 of file Nano100Series.h.
| #define SYS_PE_H_MFP_PE10_MFP_Pos (8) |
SYS_T::PE_H_MFP: PE10_MFP Position
Definition at line 3627 of file Nano100Series.h.
| #define SYS_PE_H_MFP_PE11_MFP_Msk (0x7ul << SYS_PE_H_MFP_PE11_MFP_Pos) |
SYS_T::PE_H_MFP: PE11_MFP Mask
Definition at line 3631 of file Nano100Series.h.
| #define SYS_PE_H_MFP_PE11_MFP_Pos (12) |
SYS_T::PE_H_MFP: PE11_MFP Position
Definition at line 3630 of file Nano100Series.h.
| #define SYS_PE_H_MFP_PE12_MFP_Msk (0x7ul << SYS_PE_H_MFP_PE12_MFP_Pos) |
SYS_T::PE_H_MFP: PE12_MFP Mask
Definition at line 3634 of file Nano100Series.h.
| #define SYS_PE_H_MFP_PE12_MFP_Pos (16) |
SYS_T::PE_H_MFP: PE12_MFP Position
Definition at line 3633 of file Nano100Series.h.
| #define SYS_PE_H_MFP_PE13_MFP_Msk (0x7ul << SYS_PE_H_MFP_PE13_MFP_Pos) |
SYS_T::PE_H_MFP: PE13_MFP Mask
Definition at line 3637 of file Nano100Series.h.
| #define SYS_PE_H_MFP_PE13_MFP_Pos (20) |
SYS_T::PE_H_MFP: PE13_MFP Position
Definition at line 3636 of file Nano100Series.h.
| #define SYS_PE_H_MFP_PE14_MFP_Msk (0x7ul << SYS_PE_H_MFP_PE14_MFP_Pos) |
SYS_T::PE_H_MFP: PE14_MFP Mask
Definition at line 3640 of file Nano100Series.h.
| #define SYS_PE_H_MFP_PE14_MFP_Pos (24) |
SYS_T::PE_H_MFP: PE14_MFP Position
Definition at line 3639 of file Nano100Series.h.
| #define SYS_PE_H_MFP_PE15_MFP_Msk (0x7ul << SYS_PE_H_MFP_PE15_MFP_Pos) |
SYS_T::PE_H_MFP: PE15_MFP Mask
Definition at line 3643 of file Nano100Series.h.
| #define SYS_PE_H_MFP_PE15_MFP_Pos (28) |
SYS_T::PE_H_MFP: PE15_MFP Position
Definition at line 3642 of file Nano100Series.h.
| #define SYS_PE_H_MFP_PE8_MFP_Msk (0x7ul << SYS_PE_H_MFP_PE8_MFP_Pos) |
SYS_T::PE_H_MFP: PE8_MFP Mask
Definition at line 3622 of file Nano100Series.h.
| #define SYS_PE_H_MFP_PE8_MFP_Pos (0) |
SYS_T::PE_H_MFP: PE8_MFP Position
Definition at line 3621 of file Nano100Series.h.
| #define SYS_PE_H_MFP_PE9_MFP_Msk (0x7ul << SYS_PE_H_MFP_PE9_MFP_Pos) |
SYS_T::PE_H_MFP: PE9_MFP Mask
Definition at line 3625 of file Nano100Series.h.
| #define SYS_PE_H_MFP_PE9_MFP_Pos (4) |
SYS_T::PE_H_MFP: PE9_MFP Position
Definition at line 3624 of file Nano100Series.h.
| #define SYS_PE_L_MFP_PE0_MFP_Msk (0x7ul << SYS_PE_L_MFP_PE0_MFP_Pos) |
SYS_T::PE_L_MFP: PE0_MFP Mask
Definition at line 3598 of file Nano100Series.h.
| #define SYS_PE_L_MFP_PE0_MFP_Pos (0) |
SYS_T::PE_L_MFP: PE0_MFP Position
Definition at line 3597 of file Nano100Series.h.
| #define SYS_PE_L_MFP_PE1_MFP_Msk (0x7ul << SYS_PE_L_MFP_PE1_MFP_Pos) |
SYS_T::PE_L_MFP: PE1_MFP Mask
Definition at line 3601 of file Nano100Series.h.
| #define SYS_PE_L_MFP_PE1_MFP_Pos (4) |
SYS_T::PE_L_MFP: PE1_MFP Position
Definition at line 3600 of file Nano100Series.h.
| #define SYS_PE_L_MFP_PE2_MFP_Msk (0x7ul << SYS_PE_L_MFP_PE2_MFP_Pos) |
SYS_T::PE_L_MFP: PE2_MFP Mask
Definition at line 3604 of file Nano100Series.h.
| #define SYS_PE_L_MFP_PE2_MFP_Pos (8) |
SYS_T::PE_L_MFP: PE2_MFP Position
Definition at line 3603 of file Nano100Series.h.
| #define SYS_PE_L_MFP_PE3_MFP_Msk (0x7ul << SYS_PE_L_MFP_PE3_MFP_Pos) |
SYS_T::PE_L_MFP: PE3_MFP Mask
Definition at line 3607 of file Nano100Series.h.
| #define SYS_PE_L_MFP_PE3_MFP_Pos (12) |
SYS_T::PE_L_MFP: PE3_MFP Position
Definition at line 3606 of file Nano100Series.h.
| #define SYS_PE_L_MFP_PE4_MFP_Msk (0x7ul << SYS_PE_L_MFP_PE4_MFP_Pos) |
SYS_T::PE_L_MFP: PE4_MFP Mask
Definition at line 3610 of file Nano100Series.h.
| #define SYS_PE_L_MFP_PE4_MFP_Pos (16) |
SYS_T::PE_L_MFP: PE4_MFP Position
Definition at line 3609 of file Nano100Series.h.
| #define SYS_PE_L_MFP_PE5_MFP_Msk (0x7ul << SYS_PE_L_MFP_PE5_MFP_Pos) |
SYS_T::PE_L_MFP: PE5_MFP Mask
Definition at line 3613 of file Nano100Series.h.
| #define SYS_PE_L_MFP_PE5_MFP_Pos (20) |
SYS_T::PE_L_MFP: PE5_MFP Position
Definition at line 3612 of file Nano100Series.h.
| #define SYS_PE_L_MFP_PE6_MFP_Msk (0x7ul << SYS_PE_L_MFP_PE6_MFP_Pos) |
SYS_T::PE_L_MFP: PE6_MFP Mask
Definition at line 3616 of file Nano100Series.h.
| #define SYS_PE_L_MFP_PE6_MFP_Pos (24) |
SYS_T::PE_L_MFP: PE6_MFP Position
Definition at line 3615 of file Nano100Series.h.
| #define SYS_PE_L_MFP_PE7_MFP_Msk (0x7ul << SYS_PE_L_MFP_PE7_MFP_Pos) |
SYS_T::PE_L_MFP: PE7_MFP Mask
Definition at line 3619 of file Nano100Series.h.
| #define SYS_PE_L_MFP_PE7_MFP_Pos (28) |
SYS_T::PE_L_MFP: PE7_MFP Position
Definition at line 3618 of file Nano100Series.h.
| #define SYS_PF_L_MFP_PF0_MFP_Msk (0x7ul << SYS_PF_L_MFP_PF0_MFP_Pos) |
SYS_T::PF_L_MFP: PF0_MFP Mask
Definition at line 3646 of file Nano100Series.h.
| #define SYS_PF_L_MFP_PF0_MFP_Pos (0) |
SYS_T::PF_L_MFP: PF0_MFP Position
Definition at line 3645 of file Nano100Series.h.
| #define SYS_PF_L_MFP_PF1_MFP_Msk (0x7ul << SYS_PF_L_MFP_PF1_MFP_Pos) |
SYS_T::PF_L_MFP: PF1_MFP Mask
Definition at line 3649 of file Nano100Series.h.
| #define SYS_PF_L_MFP_PF1_MFP_Pos (4) |
SYS_T::PF_L_MFP: PF1_MFP Position
Definition at line 3648 of file Nano100Series.h.
| #define SYS_PF_L_MFP_PF2_MFP_Msk (0x7ul << SYS_PF_L_MFP_PF2_MFP_Pos) |
SYS_T::PF_L_MFP: PF2_MFP Mask
Definition at line 3652 of file Nano100Series.h.
| #define SYS_PF_L_MFP_PF2_MFP_Pos (8) |
SYS_T::PF_L_MFP: PF2_MFP Position
Definition at line 3651 of file Nano100Series.h.
| #define SYS_PF_L_MFP_PF3_MFP_Msk (0x7ul << SYS_PF_L_MFP_PF3_MFP_Pos) |
SYS_T::PF_L_MFP: PF3_MFP Mask
Definition at line 3655 of file Nano100Series.h.
| #define SYS_PF_L_MFP_PF3_MFP_Pos (12) |
SYS_T::PF_L_MFP: PF3_MFP Position
Definition at line 3654 of file Nano100Series.h.
| #define SYS_PF_L_MFP_PF4_MFP_Msk (0x7ul << SYS_PF_L_MFP_PF4_MFP_Pos) |
SYS_T::PF_L_MFP: PF4_MFP Mask
Definition at line 3658 of file Nano100Series.h.
| #define SYS_PF_L_MFP_PF4_MFP_Pos (16) |
SYS_T::PF_L_MFP: PF4_MFP Position
Definition at line 3657 of file Nano100Series.h.
| #define SYS_PF_L_MFP_PF5_MFP_Msk (0x7ul << SYS_PF_L_MFP_PF5_MFP_Pos) |
SYS_T::PF_L_MFP: PF5_MFP Mask
Definition at line 3661 of file Nano100Series.h.
| #define SYS_PF_L_MFP_PF5_MFP_Pos (20) |
SYS_T::PF_L_MFP: PF5_MFP Position
Definition at line 3660 of file Nano100Series.h.
| #define SYS_PORCTL_POR_DIS_CODE_Msk (0xfffful << SYS_PORCTL_POR_DIS_CODE_Pos) |
SYS_T::PORCTL: POR_DIS_CODE Mask
Definition at line 3664 of file Nano100Series.h.
| #define SYS_PORCTL_POR_DIS_CODE_Pos (0) |
SYS_T::PORCTL: POR_DIS_CODE Position
Definition at line 3663 of file Nano100Series.h.
| #define SYS_RegLockAddr_RegUnLock_Msk (0x1ul << SYS_RegLockAddr_RegUnLock_Pos) |
SYS_T::RegLockAddr: RegUnLock Mask
Definition at line 3742 of file Nano100Series.h.
| #define SYS_RegLockAddr_RegUnLock_Pos (0) |
SYS_T::RegLockAddr: RegUnLock Position
Definition at line 3741 of file Nano100Series.h.
| #define SYS_RST_SRC_RSTS_BOD_Msk (0x1ul << SYS_RST_SRC_RSTS_BOD_Pos) |
SYS_T::RST_SRC: RSTS_BOD Mask
Definition at line 3322 of file Nano100Series.h.
| #define SYS_RST_SRC_RSTS_BOD_Pos (4) |
SYS_T::RST_SRC: RSTS_BOD Position
Definition at line 3321 of file Nano100Series.h.
| #define SYS_RST_SRC_RSTS_CPU_Msk (0x1ul << SYS_RST_SRC_RSTS_CPU_Pos) |
SYS_T::RST_SRC: RSTS_CPU Mask
Definition at line 3328 of file Nano100Series.h.
| #define SYS_RST_SRC_RSTS_CPU_Pos (7) |
SYS_T::RST_SRC: RSTS_CPU Position
Definition at line 3327 of file Nano100Series.h.
| #define SYS_RST_SRC_RSTS_PAD_Msk (0x1ul << SYS_RST_SRC_RSTS_PAD_Pos) |
SYS_T::RST_SRC: RSTS_PAD Mask
Definition at line 3316 of file Nano100Series.h.
| #define SYS_RST_SRC_RSTS_PAD_Pos (1) |
SYS_T::RST_SRC: RSTS_PAD Position
Definition at line 3315 of file Nano100Series.h.
| #define SYS_RST_SRC_RSTS_POR_Msk (0x1ul << SYS_RST_SRC_RSTS_POR_Pos) |
SYS_T::RST_SRC: RSTS_POR Mask
Definition at line 3313 of file Nano100Series.h.
| #define SYS_RST_SRC_RSTS_POR_Pos (0) |
SYS_T::RST_SRC: RSTS_POR Position
Definition at line 3312 of file Nano100Series.h.
| #define SYS_RST_SRC_RSTS_SYS_Msk (0x1ul << SYS_RST_SRC_RSTS_SYS_Pos) |
SYS_T::RST_SRC: RSTS_SYS Mask
Definition at line 3325 of file Nano100Series.h.
| #define SYS_RST_SRC_RSTS_SYS_Pos (5) |
SYS_T::RST_SRC: RSTS_SYS Position
Definition at line 3324 of file Nano100Series.h.
| #define SYS_RST_SRC_RSTS_WDT_Msk (0x1ul << SYS_RST_SRC_RSTS_WDT_Pos) |
SYS_T::RST_SRC: RSTS_WDT Mask
Definition at line 3319 of file Nano100Series.h.
| #define SYS_RST_SRC_RSTS_WDT_Pos (2) |
SYS_T::RST_SRC: RSTS_WDT Position
Definition at line 3318 of file Nano100Series.h.
| #define SYS_TEMPCTL_VTEMP_EN_Msk (0x1ul << SYS_TEMPCTL_VTEMP_EN_Pos) |
SYS_T::TEMPCTL: VTEMP_EN Mask
Definition at line 3403 of file Nano100Series.h.
| #define SYS_TEMPCTL_VTEMP_EN_Pos (0) |
SYS_T::TEMPCTL: VTEMP_EN Position
Definition at line 3402 of file Nano100Series.h.
| #define SYS_VREFCTL_BGP_EN_Msk (0x1ul << SYS_VREFCTL_BGP_EN_Pos) |
SYS_T::VREFCTL: BGP_EN Mask
Definition at line 3706 of file Nano100Series.h.
| #define SYS_VREFCTL_BGP_EN_Pos (0) |
SYS_T::VREFCTL: BGP_EN Position
Definition at line 3705 of file Nano100Series.h.
| #define SYS_VREFCTL_EXT_MODE_Msk (0x1ul << SYS_VREFCTL_EXT_MODE_Pos) |
SYS_T::VREFCTL: EXT_MODE Mask
Definition at line 3715 of file Nano100Series.h.
| #define SYS_VREFCTL_EXT_MODE_Pos (3) |
SYS_T::VREFCTL: EXT_MODE Position
Definition at line 3714 of file Nano100Series.h.
| #define SYS_VREFCTL_REG_EN_Msk (0x1ul << SYS_VREFCTL_REG_EN_Pos) |
SYS_T::VREFCTL: REG_EN Mask
Definition at line 3709 of file Nano100Series.h.
| #define SYS_VREFCTL_REG_EN_Pos (1) |
SYS_T::VREFCTL: REG_EN Position
Definition at line 3708 of file Nano100Series.h.
| #define SYS_VREFCTL_SEL25_Msk (0x1ul << SYS_VREFCTL_SEL25_Pos) |
SYS_T::VREFCTL: SEL25 Mask
Definition at line 3712 of file Nano100Series.h.
| #define SYS_VREFCTL_SEL25_Pos (2) |
SYS_T::VREFCTL: SEL25 Position
Definition at line 3711 of file Nano100Series.h.
| #define TIMER_CMPR_TMR_CMP_Msk (0xfffffful << TIMER_CMPR_TMR_CMP_Pos) |
TIMER_T::CMPR: TMR_CMP Mask
Definition at line 8666 of file Nano100Series.h.
| #define TIMER_CMPR_TMR_CMP_Pos (0) |
TIMER_T::CMPR: TMR_CMP Position
Definition at line 8665 of file Nano100Series.h.
| #define TIMER_CTL_ADC_TEEN_Msk (0x1ul << TIMER_CTL_ADC_TEEN_Pos) |
TIMER_T::CTL: ADC_TEEN Mask
Definition at line 8627 of file Nano100Series.h.
| #define TIMER_CTL_ADC_TEEN_Pos (8) |
TIMER_T::CTL: ADC_TEEN Position
Definition at line 8626 of file Nano100Series.h.
| #define TIMER_CTL_CAP_TRG_EN_Msk (0x1ul << TIMER_CTL_CAP_TRG_EN_Pos) |
TIMER_T::CTL: CAP_TRG_EN Mask
Definition at line 8633 of file Nano100Series.h.
| #define TIMER_CTL_CAP_TRG_EN_Pos (11) |
TIMER_T::CTL: CAP_TRG_EN Position
Definition at line 8632 of file Nano100Series.h.
| #define TIMER_CTL_DBGACK_EN_Msk (0x1ul << TIMER_CTL_DBGACK_EN_Pos) |
TIMER_T::CTL: DBGACK_EN Mask
Definition at line 8618 of file Nano100Series.h.
| #define TIMER_CTL_DBGACK_EN_Pos (3) |
TIMER_T::CTL: DBGACK_EN Position
Definition at line 8617 of file Nano100Series.h.
| #define TIMER_CTL_EVENT_EDGE_Msk (0x1ul << TIMER_CTL_EVENT_EDGE_Pos) |
TIMER_T::CTL: EVENT_EDGE Mask
Definition at line 8639 of file Nano100Series.h.
| #define TIMER_CTL_EVENT_EDGE_Pos (13) |
TIMER_T::CTL: EVENT_EDGE Position
Definition at line 8638 of file Nano100Series.h.
| #define TIMER_CTL_EVENT_EN_Msk (0x1ul << TIMER_CTL_EVENT_EN_Pos) |
TIMER_T::CTL: EVENT_EN Mask
Definition at line 8636 of file Nano100Series.h.
| #define TIMER_CTL_EVENT_EN_Pos (12) |
TIMER_T::CTL: EVENT_EN Position
Definition at line 8635 of file Nano100Series.h.
| #define TIMER_CTL_EVNT_DEB_EN_Msk (0x1ul << TIMER_CTL_EVNT_DEB_EN_Pos) |
TIMER_T::CTL: EVNT_DEB_EN Mask
Definition at line 8642 of file Nano100Series.h.
| #define TIMER_CTL_EVNT_DEB_EN_Pos (14) |
TIMER_T::CTL: EVNT_DEB_EN Position
Definition at line 8641 of file Nano100Series.h.
| #define TIMER_CTL_INTR_TRG_EN_Msk (0x1ul << TIMER_CTL_INTR_TRG_EN_Pos) |
TIMER_T::CTL: INTR_TRG_EN Mask
Definition at line 8660 of file Nano100Series.h.
| #define TIMER_CTL_INTR_TRG_EN_Pos (24) |
TIMER_T::CTL: INTR_TRG_EN Position
Definition at line 8659 of file Nano100Series.h.
| #define TIMER_CTL_MODE_SEL_Msk (0x3ul << TIMER_CTL_MODE_SEL_Pos) |
TIMER_T::CTL: MODE_SEL Mask
Definition at line 8621 of file Nano100Series.h.
| #define TIMER_CTL_MODE_SEL_Pos (4) |
TIMER_T::CTL: MODE_SEL Position
Definition at line 8620 of file Nano100Series.h.
| #define TIMER_CTL_PDMA_TEEN_Msk (0x1ul << TIMER_CTL_PDMA_TEEN_Pos) |
TIMER_T::CTL: PDMA_TEEN Mask
Definition at line 8630 of file Nano100Series.h.
| #define TIMER_CTL_PDMA_TEEN_Pos (10) |
TIMER_T::CTL: PDMA_TEEN Position
Definition at line 8629 of file Nano100Series.h.
| #define TIMER_CTL_SW_RST_Msk (0x1ul << TIMER_CTL_SW_RST_Pos) |
TIMER_T::CTL: SW_RST Mask
Definition at line 8612 of file Nano100Series.h.
| #define TIMER_CTL_SW_RST_Pos (1) |
TIMER_T::CTL: SW_RST Position
Definition at line 8611 of file Nano100Series.h.
| #define TIMER_CTL_TCAP_CNT_MODE_Msk (0x1ul << TIMER_CTL_TCAP_CNT_MODE_Pos) |
TIMER_T::CTL: TCAP_CNT_MODE Mask
Definition at line 8654 of file Nano100Series.h.
| #define TIMER_CTL_TCAP_CNT_MODE_Pos (20) |
TIMER_T::CTL: TCAP_CNT_MODE Position
Definition at line 8653 of file Nano100Series.h.
| #define TIMER_CTL_TCAP_DEB_EN_Msk (0x1ul << TIMER_CTL_TCAP_DEB_EN_Pos) |
TIMER_T::CTL: TCAP_DEB_EN Mask
Definition at line 8657 of file Nano100Series.h.
| #define TIMER_CTL_TCAP_DEB_EN_Pos (22) |
TIMER_T::CTL: TCAP_DEB_EN Position
Definition at line 8656 of file Nano100Series.h.
| #define TIMER_CTL_TCAP_EDGE_Msk (0x3ul << TIMER_CTL_TCAP_EDGE_Pos) |
TIMER_T::CTL: TCAP_EDGE Mask
Definition at line 8651 of file Nano100Series.h.
| #define TIMER_CTL_TCAP_EDGE_Pos (18) |
TIMER_T::CTL: TCAP_EDGE Position
Definition at line 8650 of file Nano100Series.h.
| #define TIMER_CTL_TCAP_EN_Msk (0x1ul << TIMER_CTL_TCAP_EN_Pos) |
TIMER_T::CTL: TCAP_EN Mask
Definition at line 8645 of file Nano100Series.h.
| #define TIMER_CTL_TCAP_EN_Pos (16) |
TIMER_T::CTL: TCAP_EN Position
Definition at line 8644 of file Nano100Series.h.
| #define TIMER_CTL_TCAP_MODE_Msk (0x1ul << TIMER_CTL_TCAP_MODE_Pos) |
TIMER_T::CTL: TCAP_MODE Mask
Definition at line 8648 of file Nano100Series.h.
| #define TIMER_CTL_TCAP_MODE_Pos (17) |
TIMER_T::CTL: TCAP_MODE Position
Definition at line 8647 of file Nano100Series.h.
| #define TIMER_CTL_TMR_ACT_Msk (0x1ul << TIMER_CTL_TMR_ACT_Pos) |
TIMER_T::CTL: TMR_ACT Mask
Definition at line 8624 of file Nano100Series.h.
| #define TIMER_CTL_TMR_ACT_Pos (7) |
TIMER_T::CTL: TMR_ACT Position
Definition at line 8623 of file Nano100Series.h.
| #define TIMER_CTL_TMR_EN_Msk (0x1ul << TIMER_CTL_TMR_EN_Pos) |
TIMER_T::CTL: TMR_EN Mask
Definition at line 8609 of file Nano100Series.h.
| #define TIMER_CTL_TMR_EN_Pos (0) |
@addtogroup TIMER_CONST TIMER Bit Field Definition Constant Definitions for TIMER Controller
TIMER_T::CTL: TMR_EN Position
Definition at line 8608 of file Nano100Series.h.
| #define TIMER_CTL_WAKE_EN_Msk (0x1ul << TIMER_CTL_WAKE_EN_Pos) |
TIMER_T::CTL: WAKE_EN Mask
Definition at line 8615 of file Nano100Series.h.
| #define TIMER_CTL_WAKE_EN_Pos (2) |
TIMER_T::CTL: WAKE_EN Position
Definition at line 8614 of file Nano100Series.h.
| #define TIMER_DR_TDR_Msk (0xfffffful << TIMER_DR_TDR_Pos) |
TIMER_T::DR: TDR Mask
Definition at line 8687 of file Nano100Series.h.
| #define TIMER_DR_TDR_Pos (0) |
TIMER_T::DR: TDR Position
Definition at line 8686 of file Nano100Series.h.
| #define TIMER_IER_TCAP_IE_Msk (0x1ul << TIMER_IER_TCAP_IE_Pos) |
TIMER_T::IER: TCAP_IE Mask
Definition at line 8672 of file Nano100Series.h.
| #define TIMER_IER_TCAP_IE_Pos (1) |
TIMER_T::IER: TCAP_IE Position
Definition at line 8671 of file Nano100Series.h.
| #define TIMER_IER_TMR_IE_Msk (0x1ul << TIMER_IER_TMR_IE_Pos) |
TIMER_T::IER: TMR_IE Mask
Definition at line 8669 of file Nano100Series.h.
| #define TIMER_IER_TMR_IE_Pos (0) |
TIMER_T::IER: TMR_IE Position
Definition at line 8668 of file Nano100Series.h.
| #define TIMER_ISR_NCAP_DET_STS_Msk (0x1ul << TIMER_ISR_NCAP_DET_STS_Pos) |
TIMER_T::ISR: NCAP_DET_STS Mask
Definition at line 8684 of file Nano100Series.h.
| #define TIMER_ISR_NCAP_DET_STS_Pos (5) |
TIMER_T::ISR: NCAP_DET_STS Position
Definition at line 8683 of file Nano100Series.h.
| #define TIMER_ISR_TCAP_IS_Msk (0x1ul << TIMER_ISR_TCAP_IS_Pos) |
TIMER_T::ISR: TCAP_IS Mask
Definition at line 8678 of file Nano100Series.h.
| #define TIMER_ISR_TCAP_IS_Pos (1) |
TIMER_T::ISR: TCAP_IS Position
Definition at line 8677 of file Nano100Series.h.
| #define TIMER_ISR_TMR_IS_Msk (0x1ul << TIMER_ISR_TMR_IS_Pos) |
TIMER_T::ISR: TMR_IS Mask
Definition at line 8675 of file Nano100Series.h.
| #define TIMER_ISR_TMR_IS_Pos (0) |
TIMER_T::ISR: TMR_IS Position
Definition at line 8674 of file Nano100Series.h.
| #define TIMER_ISR_TMR_WAKE_STS_Msk (0x1ul << TIMER_ISR_TMR_WAKE_STS_Pos) |
TIMER_T::ISR: TMR_WAKE_STS Mask
Definition at line 8681 of file Nano100Series.h.
| #define TIMER_ISR_TMR_WAKE_STS_Pos (4) |
TIMER_T::ISR: TMR_WAKE_STS Position
Definition at line 8680 of file Nano100Series.h.
| #define TIMER_PRECNT_PRESCALE_CNT_Msk (0xfful << TIMER_PRECNT_PRESCALE_CNT_Pos) |
TIMER_T::PRECNT: PRESCALE_CNT Mask
Definition at line 8663 of file Nano100Series.h.
| #define TIMER_PRECNT_PRESCALE_CNT_Pos (0) |
TIMER_T::PRECNT: PRESCALE_CNT Position
Definition at line 8662 of file Nano100Series.h.
| #define TIMER_TCAP_CAP_Msk (0xfffffful << TIMER_TCAP_CAP_Pos) |
TIMER_T::TCAP: CAP Mask
Definition at line 8690 of file Nano100Series.h.
| #define TIMER_TCAP_CAP_Pos (0) |
TIMER_T::TCAP: CAP Position
Definition at line 8689 of file Nano100Series.h.
| #define UART_ALT_CTL_ADDR_PID_MATCH_Msk (0xfful << UART_ALT_CTL_ADDR_PID_MATCH_Pos) |
UART_T::ALT_CTL: ADDR_PID_MATCH Mask
Definition at line 9428 of file Nano100Series.h.
| #define UART_ALT_CTL_ADDR_PID_MATCH_Pos (24) |
UART_T::ALT_CTL: ADDR_PID_MATCH Position
Definition at line 9427 of file Nano100Series.h.
| #define UART_ALT_CTL_Bit_ERR_EN_Msk (0x1ul << UART_ALT_CTL_Bit_ERR_EN_Pos) |
UART_T::ALT_CTL: Bit_ERR_EN Mask
Definition at line 9413 of file Nano100Series.h.
| #define UART_ALT_CTL_Bit_ERR_EN_Pos (8) |
UART_T::ALT_CTL: Bit_ERR_EN Position
Definition at line 9412 of file Nano100Series.h.
| #define UART_ALT_CTL_LIN_HEAD_SEL_Msk (0x3ul << UART_ALT_CTL_LIN_HEAD_SEL_Pos) |
UART_T::ALT_CTL: LIN_HEAD_SEL Mask
Definition at line 9404 of file Nano100Series.h.
| #define UART_ALT_CTL_LIN_HEAD_SEL_Pos (4) |
UART_T::ALT_CTL: LIN_HEAD_SEL Position
Definition at line 9403 of file Nano100Series.h.
| #define UART_ALT_CTL_LIN_RX_EN_Msk (0x1ul << UART_ALT_CTL_LIN_RX_EN_Pos) |
UART_T::ALT_CTL: LIN_RX_EN Mask
Definition at line 9407 of file Nano100Series.h.
| #define UART_ALT_CTL_LIN_RX_EN_Pos (6) |
UART_T::ALT_CTL: LIN_RX_EN Position
Definition at line 9406 of file Nano100Series.h.
| #define UART_ALT_CTL_LIN_TX_BCNT_Msk (0x7ul << UART_ALT_CTL_LIN_TX_BCNT_Pos) |
UART_T::ALT_CTL: LIN_TX_BCNT Mask
Definition at line 9401 of file Nano100Series.h.
| #define UART_ALT_CTL_LIN_TX_BCNT_Pos (0) |
UART_T::ALT_CTL: LIN_TX_BCNT Position
Definition at line 9400 of file Nano100Series.h.
| #define UART_ALT_CTL_LIN_TX_EN_Msk (0x1ul << UART_ALT_CTL_LIN_TX_EN_Pos) |
UART_T::ALT_CTL: LIN_TX_EN Mask
Definition at line 9410 of file Nano100Series.h.
| #define UART_ALT_CTL_LIN_TX_EN_Pos (7) |
UART_T::ALT_CTL: LIN_TX_EN Position
Definition at line 9409 of file Nano100Series.h.
| #define UART_ALT_CTL_RS485_AAD_Msk (0x1ul << UART_ALT_CTL_RS485_AAD_Pos) |
UART_T::ALT_CTL: RS485_AAD Mask
Definition at line 9419 of file Nano100Series.h.
| #define UART_ALT_CTL_RS485_AAD_Pos (17) |
UART_T::ALT_CTL: RS485_AAD Position
Definition at line 9418 of file Nano100Series.h.
| #define UART_ALT_CTL_RS485_ADD_EN_Msk (0x1ul << UART_ALT_CTL_RS485_ADD_EN_Pos) |
UART_T::ALT_CTL: RS485_ADD_EN Mask
Definition at line 9425 of file Nano100Series.h.
| #define UART_ALT_CTL_RS485_ADD_EN_Pos (19) |
UART_T::ALT_CTL: RS485_ADD_EN Position
Definition at line 9424 of file Nano100Series.h.
| #define UART_ALT_CTL_RS485_AUD_Msk (0x1ul << UART_ALT_CTL_RS485_AUD_Pos) |
UART_T::ALT_CTL: RS485_AUD Mask
Definition at line 9422 of file Nano100Series.h.
| #define UART_ALT_CTL_RS485_AUD_Pos (18) |
UART_T::ALT_CTL: RS485_AUD Position
Definition at line 9421 of file Nano100Series.h.
| #define UART_ALT_CTL_RS485_NMM_Msk (0x1ul << UART_ALT_CTL_RS485_NMM_Pos) |
UART_T::ALT_CTL: RS485_NMM Mask
Definition at line 9416 of file Nano100Series.h.
| #define UART_ALT_CTL_RS485_NMM_Pos (16) |
UART_T::ALT_CTL: RS485_NMM Position
Definition at line 9415 of file Nano100Series.h.
| #define UART_BAUD_BRD_Msk (0xfffful << UART_BAUD_BRD_Pos) |
UART_T::BAUD: BRD Mask
Definition at line 9386 of file Nano100Series.h.
| #define UART_BAUD_BRD_Pos (0) |
UART_T::BAUD: BRD Position
Definition at line 9385 of file Nano100Series.h.
| #define UART_BAUD_DIV_16_EN_Msk (0x1ul << UART_BAUD_DIV_16_EN_Pos) |
UART_T::BAUD: DIV_16_EN Mask
Definition at line 9389 of file Nano100Series.h.
| #define UART_BAUD_DIV_16_EN_Pos (31) |
UART_T::BAUD: DIV_16_EN Position
Definition at line 9388 of file Nano100Series.h.
| #define UART_CTL_ABAUD_EN_Msk (0x1ul << UART_CTL_ABAUD_EN_Pos) |
UART_T::CTL: ABAUD_EN Mask
Definition at line 9227 of file Nano100Series.h.
| #define UART_CTL_ABAUD_EN_Pos (12) |
UART_T::CTL: ABAUD_EN Position
Definition at line 9226 of file Nano100Series.h.
| #define UART_CTL_AUTO_CTS_EN_Msk (0x1ul << UART_CTL_AUTO_CTS_EN_Pos) |
UART_T::CTL: AUTO_CTS_EN Mask
Definition at line 9212 of file Nano100Series.h.
| #define UART_CTL_AUTO_CTS_EN_Pos (5) |
UART_T::CTL: AUTO_CTS_EN Position
Definition at line 9211 of file Nano100Series.h.
| #define UART_CTL_AUTO_RTS_EN_Msk (0x1ul << UART_CTL_AUTO_RTS_EN_Pos) |
UART_T::CTL: AUTO_RTS_EN Mask
Definition at line 9209 of file Nano100Series.h.
| #define UART_CTL_AUTO_RTS_EN_Pos (4) |
UART_T::CTL: AUTO_RTS_EN Position
Definition at line 9208 of file Nano100Series.h.
| #define UART_CTL_DMA_RX_EN_Msk (0x1ul << UART_CTL_DMA_RX_EN_Pos) |
UART_T::CTL: DMA_RX_EN Mask
Definition at line 9215 of file Nano100Series.h.
| #define UART_CTL_DMA_RX_EN_Pos (6) |
UART_T::CTL: DMA_RX_EN Position
Definition at line 9214 of file Nano100Series.h.
| #define UART_CTL_DMA_TX_EN_Msk (0x1ul << UART_CTL_DMA_TX_EN_Pos) |
UART_T::CTL: DMA_TX_EN Mask
Definition at line 9218 of file Nano100Series.h.
| #define UART_CTL_DMA_TX_EN_Pos (7) |
UART_T::CTL: DMA_TX_EN Position
Definition at line 9217 of file Nano100Series.h.
| #define UART_CTL_RX_DIS_Msk (0x1ul << UART_CTL_RX_DIS_Pos) |
UART_T::CTL: RX_DIS Mask
Definition at line 9203 of file Nano100Series.h.
| #define UART_CTL_RX_DIS_Pos (2) |
UART_T::CTL: RX_DIS Position
Definition at line 9202 of file Nano100Series.h.
| #define UART_CTL_RX_RST_Msk (0x1ul << UART_CTL_RX_RST_Pos) |
UART_T::CTL: RX_RST Mask
Definition at line 9197 of file Nano100Series.h.
| #define UART_CTL_RX_RST_Pos (0) |
UART_T::CTL: RX_RST Position
Definition at line 9196 of file Nano100Series.h.
| #define UART_CTL_TX_DIS_Msk (0x1ul << UART_CTL_TX_DIS_Pos) |
UART_T::CTL: TX_DIS Mask
Definition at line 9206 of file Nano100Series.h.
| #define UART_CTL_TX_DIS_Pos (3) |
UART_T::CTL: TX_DIS Position
Definition at line 9205 of file Nano100Series.h.
| #define UART_CTL_TX_RST_Msk (0x1ul << UART_CTL_TX_RST_Pos) |
UART_T::CTL: TX_RST Mask
Definition at line 9200 of file Nano100Series.h.
| #define UART_CTL_TX_RST_Pos (1) |
UART_T::CTL: TX_RST Position
Definition at line 9199 of file Nano100Series.h.
| #define UART_CTL_WAKE_CTS_EN_Msk (0x1ul << UART_CTL_WAKE_CTS_EN_Pos) |
UART_T::CTL: WAKE_CTS_EN Mask
Definition at line 9221 of file Nano100Series.h.
| #define UART_CTL_WAKE_CTS_EN_Pos (8) |
UART_T::CTL: WAKE_CTS_EN Position
Definition at line 9220 of file Nano100Series.h.
| #define UART_CTL_WAKE_DATA_EN_Msk (0x1ul << UART_CTL_WAKE_DATA_EN_Pos) |
UART_T::CTL: WAKE_DATA_EN Mask
Definition at line 9224 of file Nano100Series.h.
| #define UART_CTL_WAKE_DATA_EN_Pos (9) |
UART_T::CTL: WAKE_DATA_EN Position
Definition at line 9223 of file Nano100Series.h.
| #define UART_DAT_DAT_Msk (0xfful << UART_DAT_DAT_Pos) |
UART_T::DAT: DAT Mask
Definition at line 9194 of file Nano100Series.h.
| #define UART_DAT_DAT_Pos (0) |
@addtogroup UART_CONST UART Bit Field Definition Constant Definitions for UART Controller
UART_T::DAT: DAT Position
Definition at line 9193 of file Nano100Series.h.
| #define UART_FSR_BI_F_Msk (0x1ul << UART_FSR_BI_F_Pos) |
UART_T::FSR: BI_F Mask
Definition at line 9344 of file Nano100Series.h.
| #define UART_FSR_BI_F_Pos (6) |
UART_T::FSR: BI_F Position
Definition at line 9343 of file Nano100Series.h.
| #define UART_FSR_FE_F_Msk (0x1ul << UART_FSR_FE_F_Pos) |
UART_T::FSR: FE_F Mask
Definition at line 9341 of file Nano100Series.h.
| #define UART_FSR_FE_F_Pos (5) |
UART_T::FSR: FE_F Position
Definition at line 9340 of file Nano100Series.h.
| #define UART_FSR_PE_F_Msk (0x1ul << UART_FSR_PE_F_Pos) |
UART_T::FSR: PE_F Mask
Definition at line 9338 of file Nano100Series.h.
| #define UART_FSR_PE_F_Pos (4) |
UART_T::FSR: PE_F Position
Definition at line 9337 of file Nano100Series.h.
| #define UART_FSR_RX_EMPTY_F_Msk (0x1ul << UART_FSR_RX_EMPTY_F_Pos) |
UART_T::FSR: RX_EMPTY_F Mask
Definition at line 9332 of file Nano100Series.h.
| #define UART_FSR_RX_EMPTY_F_Pos (1) |
UART_T::FSR: RX_EMPTY_F Position
Definition at line 9331 of file Nano100Series.h.
| #define UART_FSR_RX_FULL_F_Msk (0x1ul << UART_FSR_RX_FULL_F_Pos) |
UART_T::FSR: RX_FULL_F Mask
Definition at line 9335 of file Nano100Series.h.
| #define UART_FSR_RX_FULL_F_Pos (2) |
UART_T::FSR: RX_FULL_F Position
Definition at line 9334 of file Nano100Series.h.
| #define UART_FSR_RX_OVER_F_Msk (0x1ul << UART_FSR_RX_OVER_F_Pos) |
UART_T::FSR: RX_OVER_F Mask
Definition at line 9329 of file Nano100Series.h.
| #define UART_FSR_RX_OVER_F_Pos (0) |
UART_T::FSR: RX_OVER_F Position
Definition at line 9328 of file Nano100Series.h.
| #define UART_FSR_RX_POINTER_F_Msk (0x1ful << UART_FSR_RX_POINTER_F_Pos) |
UART_T::FSR: RX_POINTER_F Mask
Definition at line 9359 of file Nano100Series.h.
| #define UART_FSR_RX_POINTER_F_Pos (16) |
UART_T::FSR: RX_POINTER_F Position
Definition at line 9358 of file Nano100Series.h.
| #define UART_FSR_TE_F_Msk (0x1ul << UART_FSR_TE_F_Pos) |
UART_T::FSR: TE_F Mask
Definition at line 9356 of file Nano100Series.h.
| #define UART_FSR_TE_F_Pos (11) |
UART_T::FSR: TE_F Position
Definition at line 9355 of file Nano100Series.h.
| #define UART_FSR_TX_EMPTY_F_Msk (0x1ul << UART_FSR_TX_EMPTY_F_Pos) |
UART_T::FSR: TX_EMPTY_F Mask
Definition at line 9350 of file Nano100Series.h.
| #define UART_FSR_TX_EMPTY_F_Pos (9) |
UART_T::FSR: TX_EMPTY_F Position
Definition at line 9349 of file Nano100Series.h.
| #define UART_FSR_TX_FULL_F_Msk (0x1ul << UART_FSR_TX_FULL_F_Pos) |
UART_T::FSR: TX_FULL_F Mask
Definition at line 9353 of file Nano100Series.h.
| #define UART_FSR_TX_FULL_F_Pos (10) |
UART_T::FSR: TX_FULL_F Position
Definition at line 9352 of file Nano100Series.h.
| #define UART_FSR_TX_OVER_F_Msk (0x1ul << UART_FSR_TX_OVER_F_Pos) |
UART_T::FSR: TX_OVER_F Mask
Definition at line 9347 of file Nano100Series.h.
| #define UART_FSR_TX_OVER_F_Pos (8) |
UART_T::FSR: TX_OVER_F Position
Definition at line 9346 of file Nano100Series.h.
| #define UART_FSR_TX_POINTER_F_Msk (0x1ful << UART_FSR_TX_POINTER_F_Pos) |
UART_T::FSR: TX_POINTER_F Mask
Definition at line 9362 of file Nano100Series.h.
| #define UART_FSR_TX_POINTER_F_Pos (24) |
UART_T::FSR: TX_POINTER_F Position
Definition at line 9361 of file Nano100Series.h.
| #define UART_FUN_SEL_FUN_SEL_Msk (0x3ul << UART_FUN_SEL_FUN_SEL_Pos) |
UART_T::FUN_SEL: FUN_SEL Mask
Definition at line 9431 of file Nano100Series.h.
| #define UART_FUN_SEL_FUN_SEL_Pos (0) |
UART_T::FUN_SEL: FUN_SEL Position
Definition at line 9430 of file Nano100Series.h.
| #define UART_IER_ABAUD_IE_Msk (0x1ul << UART_IER_ABAUD_IE_Pos) |
UART_T::IER: ABAUD_IE Mask
Definition at line 9275 of file Nano100Series.h.
| #define UART_IER_ABAUD_IE_Pos (7) |
UART_T::IER: ABAUD_IE Position
Definition at line 9274 of file Nano100Series.h.
| #define UART_IER_BUF_ERR_IE_Msk (0x1ul << UART_IER_BUF_ERR_IE_Pos) |
UART_T::IER: BUF_ERR_IE Mask
Definition at line 9269 of file Nano100Series.h.
| #define UART_IER_BUF_ERR_IE_Pos (5) |
UART_T::IER: BUF_ERR_IE Position
Definition at line 9268 of file Nano100Series.h.
| #define UART_IER_LIN_IE_Msk (0x1ul << UART_IER_LIN_IE_Pos) |
UART_T::IER: LIN_IE Mask
Definition at line 9278 of file Nano100Series.h.
| #define UART_IER_LIN_IE_Pos (8) |
UART_T::IER: LIN_IE Position
Definition at line 9277 of file Nano100Series.h.
| #define UART_IER_MODEM_IE_Msk (0x1ul << UART_IER_MODEM_IE_Pos) |
UART_T::IER: MODEM_IE Mask
Definition at line 9263 of file Nano100Series.h.
| #define UART_IER_MODEM_IE_Pos (3) |
UART_T::IER: MODEM_IE Position
Definition at line 9262 of file Nano100Series.h.
| #define UART_IER_RDA_IE_Msk (0x1ul << UART_IER_RDA_IE_Pos) |
UART_T::IER: RDA_IE Mask
Definition at line 9254 of file Nano100Series.h.
| #define UART_IER_RDA_IE_Pos (0) |
UART_T::IER: RDA_IE Position
Definition at line 9253 of file Nano100Series.h.
| #define UART_IER_RLS_IE_Msk (0x1ul << UART_IER_RLS_IE_Pos) |
UART_T::IER: RLS_IE Mask
Definition at line 9260 of file Nano100Series.h.
| #define UART_IER_RLS_IE_Pos (2) |
UART_T::IER: RLS_IE Position
Definition at line 9259 of file Nano100Series.h.
| #define UART_IER_RTO_IE_Msk (0x1ul << UART_IER_RTO_IE_Pos) |
UART_T::IER: RTO_IE Mask
Definition at line 9266 of file Nano100Series.h.
| #define UART_IER_RTO_IE_Pos (4) |
UART_T::IER: RTO_IE Position
Definition at line 9265 of file Nano100Series.h.
| #define UART_IER_THRE_IE_Msk (0x1ul << UART_IER_THRE_IE_Pos) |
UART_T::IER: THRE_IE Mask
Definition at line 9257 of file Nano100Series.h.
| #define UART_IER_THRE_IE_Pos (1) |
UART_T::IER: THRE_IE Position
Definition at line 9256 of file Nano100Series.h.
| #define UART_IER_WAKE_IE_Msk (0x1ul << UART_IER_WAKE_IE_Pos) |
UART_T::IER: WAKE_IE Mask
Definition at line 9272 of file Nano100Series.h.
| #define UART_IER_WAKE_IE_Pos (6) |
UART_T::IER: WAKE_IE Position
Definition at line 9271 of file Nano100Series.h.
| #define UART_IRCR_INV_RX_Msk (0x1ul << UART_IRCR_INV_RX_Pos) |
UART_T::IRCR: INV_RX Mask
Definition at line 9398 of file Nano100Series.h.
| #define UART_IRCR_INV_RX_Pos (6) |
UART_T::IRCR: INV_RX Position
Definition at line 9397 of file Nano100Series.h.
| #define UART_IRCR_INV_TX_Msk (0x1ul << UART_IRCR_INV_TX_Pos) |
UART_T::IRCR: INV_TX Mask
Definition at line 9395 of file Nano100Series.h.
| #define UART_IRCR_INV_TX_Pos (5) |
UART_T::IRCR: INV_TX Position
Definition at line 9394 of file Nano100Series.h.
| #define UART_IRCR_TX_SELECT_Msk (0x1ul << UART_IRCR_TX_SELECT_Pos) |
UART_T::IRCR: TX_SELECT Mask
Definition at line 9392 of file Nano100Series.h.
| #define UART_IRCR_TX_SELECT_Pos (1) |
UART_T::IRCR: TX_SELECT Position
Definition at line 9391 of file Nano100Series.h.
| #define UART_ISR_ABAUD_IS_Msk (0x1ul << UART_ISR_ABAUD_IS_Pos) |
UART_T::ISR: ABAUD_IS Mask
Definition at line 9302 of file Nano100Series.h.
| #define UART_ISR_ABAUD_IS_Pos (7) |
UART_T::ISR: ABAUD_IS Position
Definition at line 9301 of file Nano100Series.h.
| #define UART_ISR_BUF_ERR_IS_Msk (0x1ul << UART_ISR_BUF_ERR_IS_Pos) |
UART_T::ISR: BUF_ERR_IS Mask
Definition at line 9296 of file Nano100Series.h.
| #define UART_ISR_BUF_ERR_IS_Pos (5) |
UART_T::ISR: BUF_ERR_IS Position
Definition at line 9295 of file Nano100Series.h.
| #define UART_ISR_LIN_IS_Msk (0x1ul << UART_ISR_LIN_IS_Pos) |
UART_T::ISR: LIN_IS Mask
Definition at line 9305 of file Nano100Series.h.
| #define UART_ISR_LIN_IS_Pos (8) |
UART_T::ISR: LIN_IS Position
Definition at line 9304 of file Nano100Series.h.
| #define UART_ISR_MODEM_IS_Msk (0x1ul << UART_ISR_MODEM_IS_Pos) |
UART_T::ISR: MODEM_IS Mask
Definition at line 9290 of file Nano100Series.h.
| #define UART_ISR_MODEM_IS_Pos (3) |
UART_T::ISR: MODEM_IS Position
Definition at line 9289 of file Nano100Series.h.
| #define UART_ISR_RDA_IS_Msk (0x1ul << UART_ISR_RDA_IS_Pos) |
UART_T::ISR: RDA_IS Mask
Definition at line 9281 of file Nano100Series.h.
| #define UART_ISR_RDA_IS_Pos (0) |
UART_T::ISR: RDA_IS Position
Definition at line 9280 of file Nano100Series.h.
| #define UART_ISR_RLS_IS_Msk (0x1ul << UART_ISR_RLS_IS_Pos) |
UART_T::ISR: RLS_IS Mask
Definition at line 9287 of file Nano100Series.h.
| #define UART_ISR_RLS_IS_Pos (2) |
UART_T::ISR: RLS_IS Position
Definition at line 9286 of file Nano100Series.h.
| #define UART_ISR_RTO_IS_Msk (0x1ul << UART_ISR_RTO_IS_Pos) |
UART_T::ISR: RTO_IS Mask
Definition at line 9293 of file Nano100Series.h.
| #define UART_ISR_RTO_IS_Pos (4) |
UART_T::ISR: RTO_IS Position
Definition at line 9292 of file Nano100Series.h.
| #define UART_ISR_THRE_IS_Msk (0x1ul << UART_ISR_THRE_IS_Pos) |
UART_T::ISR: THRE_IS Mask
Definition at line 9284 of file Nano100Series.h.
| #define UART_ISR_THRE_IS_Pos (1) |
UART_T::ISR: THRE_IS Position
Definition at line 9283 of file Nano100Series.h.
| #define UART_ISR_WAKE_IS_Msk (0x1ul << UART_ISR_WAKE_IS_Pos) |
UART_T::ISR: WAKE_IS Mask
Definition at line 9299 of file Nano100Series.h.
| #define UART_ISR_WAKE_IS_Pos (6) |
UART_T::ISR: WAKE_IS Position
Definition at line 9298 of file Nano100Series.h.
| #define UART_MCSR_CTS_ST_Msk (0x1ul << UART_MCSR_CTS_ST_Pos) |
UART_T::MCSR: CTS_ST Mask
Definition at line 9374 of file Nano100Series.h.
| #define UART_MCSR_CTS_ST_Pos (17) |
UART_T::MCSR: CTS_ST Position
Definition at line 9373 of file Nano100Series.h.
| #define UART_MCSR_DCT_F_Msk (0x1ul << UART_MCSR_DCT_F_Pos) |
UART_T::MCSR: DCT_F Mask
Definition at line 9377 of file Nano100Series.h.
| #define UART_MCSR_DCT_F_Pos (18) |
UART_T::MCSR: DCT_F Position
Definition at line 9376 of file Nano100Series.h.
| #define UART_MCSR_LEV_CTS_Msk (0x1ul << UART_MCSR_LEV_CTS_Pos) |
UART_T::MCSR: LEV_CTS Mask
Definition at line 9371 of file Nano100Series.h.
| #define UART_MCSR_LEV_CTS_Pos (16) |
UART_T::MCSR: LEV_CTS Position
Definition at line 9370 of file Nano100Series.h.
| #define UART_MCSR_LEV_RTS_Msk (0x1ul << UART_MCSR_LEV_RTS_Pos) |
UART_T::MCSR: LEV_RTS Mask
Definition at line 9365 of file Nano100Series.h.
| #define UART_MCSR_LEV_RTS_Pos (0) |
UART_T::MCSR: LEV_RTS Position
Definition at line 9364 of file Nano100Series.h.
| #define UART_MCSR_RTS_ST_Msk (0x1ul << UART_MCSR_RTS_ST_Pos) |
UART_T::MCSR: RTS_ST Mask
Definition at line 9368 of file Nano100Series.h.
| #define UART_MCSR_RTS_ST_Pos (1) |
UART_T::MCSR: RTS_ST Position
Definition at line 9367 of file Nano100Series.h.
| #define UART_TLCTL_BCB_Msk (0x1ul << UART_TLCTL_BCB_Pos) |
UART_T::TLCTL: BCB Mask
Definition at line 9245 of file Nano100Series.h.
| #define UART_TLCTL_BCB_Pos (6) |
UART_T::TLCTL: BCB Position
Definition at line 9244 of file Nano100Series.h.
| #define UART_TLCTL_DATA_LEN_Msk (0x3ul << UART_TLCTL_DATA_LEN_Pos) |
UART_T::TLCTL: DATA_LEN Mask
Definition at line 9230 of file Nano100Series.h.
| #define UART_TLCTL_DATA_LEN_Pos (0) |
UART_T::TLCTL: DATA_LEN Position
Definition at line 9229 of file Nano100Series.h.
| #define UART_TLCTL_EPE_Msk (0x1ul << UART_TLCTL_EPE_Pos) |
UART_T::TLCTL: EPE Mask
Definition at line 9239 of file Nano100Series.h.
| #define UART_TLCTL_EPE_Pos (4) |
UART_T::TLCTL: EPE Position
Definition at line 9238 of file Nano100Series.h.
| #define UART_TLCTL_NSB_Msk (0x1ul << UART_TLCTL_NSB_Pos) |
UART_T::TLCTL: NSB Mask
Definition at line 9233 of file Nano100Series.h.
| #define UART_TLCTL_NSB_Pos (2) |
UART_T::TLCTL: NSB Position
Definition at line 9232 of file Nano100Series.h.
| #define UART_TLCTL_PBE_Msk (0x1ul << UART_TLCTL_PBE_Pos) |
UART_T::TLCTL: PBE Mask
Definition at line 9236 of file Nano100Series.h.
| #define UART_TLCTL_PBE_Pos (3) |
UART_T::TLCTL: PBE Position
Definition at line 9235 of file Nano100Series.h.
| #define UART_TLCTL_RFITL_Msk (0x3ul << UART_TLCTL_RFITL_Pos) |
UART_T::TLCTL: RFITL Mask
Definition at line 9248 of file Nano100Series.h.
| #define UART_TLCTL_RFITL_Pos (8) |
UART_T::TLCTL: RFITL Position
Definition at line 9247 of file Nano100Series.h.
| #define UART_TLCTL_RTS_TRI_LEV_Msk (0x3ul << UART_TLCTL_RTS_TRI_LEV_Pos) |
UART_T::TLCTL: RTS_TRI_LEV Mask
Definition at line 9251 of file Nano100Series.h.
| #define UART_TLCTL_RTS_TRI_LEV_Pos (12) |
UART_T::TLCTL: RTS_TRI_LEV Position
Definition at line 9250 of file Nano100Series.h.
| #define UART_TLCTL_SPE_Msk (0x1ul << UART_TLCTL_SPE_Pos) |
UART_T::TLCTL: SPE Mask
Definition at line 9242 of file Nano100Series.h.
| #define UART_TLCTL_SPE_Pos (5) |
UART_T::TLCTL: SPE Position
Definition at line 9241 of file Nano100Series.h.
| #define UART_TMCTL_DLY_Msk (0xfful << UART_TMCTL_DLY_Pos) |
UART_T::TMCTL: DLY Mask
Definition at line 9383 of file Nano100Series.h.
| #define UART_TMCTL_DLY_Pos (16) |
UART_T::TMCTL: DLY Position
Definition at line 9382 of file Nano100Series.h.
| #define UART_TMCTL_TOIC_Msk (0x1fful << UART_TMCTL_TOIC_Pos) |
UART_T::TMCTL: TOIC Mask
Definition at line 9380 of file Nano100Series.h.
| #define UART_TMCTL_TOIC_Pos (0) |
UART_T::TMCTL: TOIC Position
Definition at line 9379 of file Nano100Series.h.
| #define UART_TRSR_ABAUD_F_Msk (0x1ul << UART_TRSR_ABAUD_F_Pos) |
UART_T::TRSR: ABAUD_F Mask
Definition at line 9311 of file Nano100Series.h.
| #define UART_TRSR_ABAUD_F_Pos (1) |
UART_T::TRSR: ABAUD_F Position
Definition at line 9310 of file Nano100Series.h.
| #define UART_TRSR_ABAUD_TOUT_F_Msk (0x1ul << UART_TRSR_ABAUD_TOUT_F_Pos) |
UART_T::TRSR: ABAUD_TOUT_F Mask
Definition at line 9314 of file Nano100Series.h.
| #define UART_TRSR_ABAUD_TOUT_F_Pos (2) |
UART_T::TRSR: ABAUD_TOUT_F Position
Definition at line 9313 of file Nano100Series.h.
| #define UART_TRSR_BIT_ERR_F_Msk (0x1ul << UART_TRSR_BIT_ERR_F_Pos) |
UART_T::TRSR: BIT_ERR_F Mask
Definition at line 9323 of file Nano100Series.h.
| #define UART_TRSR_BIT_ERR_F_Pos (5) |
UART_T::TRSR: BIT_ERR_F Position
Definition at line 9322 of file Nano100Series.h.
| #define UART_TRSR_LIN_RX_F_Msk (0x1ul << UART_TRSR_LIN_RX_F_Pos) |
UART_T::TRSR: LIN_RX_F Mask
Definition at line 9320 of file Nano100Series.h.
| #define UART_TRSR_LIN_RX_F_Pos (4) |
UART_T::TRSR: LIN_RX_F Position
Definition at line 9319 of file Nano100Series.h.
| #define UART_TRSR_LIN_RX_SYNC_ERR_F_Msk (0x1ul << UART_TRSR_LIN_RX_SYNC_ERR_F_Pos) |
UART_T::TRSR: LIN_RX_SYNC_ERR_F Mask
Definition at line 9326 of file Nano100Series.h.
| #define UART_TRSR_LIN_RX_SYNC_ERR_F_Pos (8) |
UART_T::TRSR: LIN_RX_SYNC_ERR_F Position
Definition at line 9325 of file Nano100Series.h.
| #define UART_TRSR_LIN_TX_F_Msk (0x1ul << UART_TRSR_LIN_TX_F_Pos) |
UART_T::TRSR: LIN_TX_F Mask
Definition at line 9317 of file Nano100Series.h.
| #define UART_TRSR_LIN_TX_F_Pos (3) |
UART_T::TRSR: LIN_TX_F Position
Definition at line 9316 of file Nano100Series.h.
| #define UART_TRSR_RS485_ADDET_F_Msk (0x1ul << UART_TRSR_RS485_ADDET_F_Pos) |
UART_T::TRSR: RS485_ADDET_F Mask
Definition at line 9308 of file Nano100Series.h.
| #define UART_TRSR_RS485_ADDET_F_Pos (0) |
UART_T::TRSR: RS485_ADDET_F Position
Definition at line 9307 of file Nano100Series.h.
| #define USBD_BUFSEG_BUFSEG_Msk (0x3ful << USBD_BUFSEG_BUFSEG_Pos) |
USBD_EP_T::BUFSEG: BUFSEG Mask
Definition at line 9866 of file Nano100Series.h.
| #define USBD_BUFSEG_BUFSEG_Pos (3) |
USBD_EP_T::BUFSEG: BUFSEG Position
Definition at line 9865 of file Nano100Series.h.
| #define USBD_BUSSTS_FLDET_Msk (0x1ul << USBD_BUSSTS_FLDET_Pos) |
USBD_T::BUSSTS: FLDET Mask
Definition at line 9794 of file Nano100Series.h.
| #define USBD_BUSSTS_FLDET_Pos (4) |
USBD_T::BUSSTS: FLDET Position
Definition at line 9793 of file Nano100Series.h.
| #define USBD_BUSSTS_RESUME_Msk (0x1ul << USBD_BUSSTS_RESUME_Pos) |
USBD_T::BUSSTS: RESUME Mask
Definition at line 9788 of file Nano100Series.h.
| #define USBD_BUSSTS_RESUME_Pos (2) |
USBD_T::BUSSTS: RESUME Position
Definition at line 9787 of file Nano100Series.h.
| #define USBD_BUSSTS_SUSPEND_Msk (0x1ul << USBD_BUSSTS_SUSPEND_Pos) |
USBD_T::BUSSTS: SUSPEND Mask
Definition at line 9785 of file Nano100Series.h.
| #define USBD_BUSSTS_SUSPEND_Pos (1) |
USBD_T::BUSSTS: SUSPEND Position
Definition at line 9784 of file Nano100Series.h.
| #define USBD_BUSSTS_TIMEOUT_Msk (0x1ul << USBD_BUSSTS_TIMEOUT_Pos) |
USBD_T::BUSSTS: TIMEOUT Mask
Definition at line 9791 of file Nano100Series.h.
| #define USBD_BUSSTS_TIMEOUT_Pos (3) |
USBD_T::BUSSTS: TIMEOUT Position
Definition at line 9790 of file Nano100Series.h.
| #define USBD_BUSSTS_USBRST_Msk (0x1ul << USBD_BUSSTS_USBRST_Pos) |
USBD_T::BUSSTS: USBRST Mask
Definition at line 9782 of file Nano100Series.h.
| #define USBD_BUSSTS_USBRST_Pos (0) |
USBD_T::BUSSTS: USBRST Position
Definition at line 9781 of file Nano100Series.h.
| #define USBD_CFG_CLRRDY_Msk (0x1ul << USBD_CFG_CLRRDY_Pos) |
USBD_EP_T::CFG: CLRRDY Mask
Definition at line 9890 of file Nano100Series.h.
| #define USBD_CFG_CLRRDY_Pos (15) |
USBD_EP_T::CFG: CLRRDY Position
Definition at line 9889 of file Nano100Series.h.
| #define USBD_CFG_CSTALL_Msk (0x1ul << USBD_CFG_CSTALL_Pos) |
USBD_EP_T::CFG: CSTALL Mask
Definition at line 9884 of file Nano100Series.h.
| #define USBD_CFG_CSTALL_Pos (8) |
USBD_EP_T::CFG: CSTALL Position
Definition at line 9883 of file Nano100Series.h.
| #define USBD_CFG_DSQ_SYNC_Msk (0x1ul << USBD_CFG_DSQ_SYNC_Pos) |
USBD_EP_T::CFG: DSQ_SYNC Mask
Definition at line 9881 of file Nano100Series.h.
| #define USBD_CFG_DSQ_SYNC_Pos (7) |
USBD_EP_T::CFG: DSQ_SYNC Position
Definition at line 9880 of file Nano100Series.h.
| #define USBD_CFG_EP_NUM_Msk (0xful << USBD_CFG_EP_NUM_Pos) |
USBD_EP_T::CFG: EP_NUM Mask
Definition at line 9872 of file Nano100Series.h.
| #define USBD_CFG_EP_NUM_Pos (0) |
USBD_EP_T::CFG: EP_NUM Position
Definition at line 9871 of file Nano100Series.h.
| #define USBD_CFG_EPMODE_Msk (0x3ul << USBD_CFG_EPMODE_Pos) |
USBD_EP_T::CFG: EPMODE Mask
Definition at line 9878 of file Nano100Series.h.
| #define USBD_CFG_EPMODE_Pos (5) |
USBD_EP_T::CFG: EPMODE Position
Definition at line 9877 of file Nano100Series.h.
| #define USBD_CFG_ISOCH_Msk (0x1ul << USBD_CFG_ISOCH_Pos) |
USBD_EP_T::CFG: ISOCH Mask
Definition at line 9875 of file Nano100Series.h.
| #define USBD_CFG_ISOCH_Pos (4) |
USBD_EP_T::CFG: ISOCH Position
Definition at line 9874 of file Nano100Series.h.
| #define USBD_CFG_SSTALL_Msk (0x1ul << USBD_CFG_SSTALL_Pos) |
USBD_EP_T::CFG: SSTALL Mask
Definition at line 9887 of file Nano100Series.h.
| #define USBD_CFG_SSTALL_Pos (9) |
USBD_EP_T::CFG: SSTALL Position
Definition at line 9886 of file Nano100Series.h.
| #define USBD_CTL_DPPU_EN_Msk (0x1ul << USBD_CTL_DPPU_EN_Pos) |
USBD_T::CTL: DPPU_EN Mask
Definition at line 9770 of file Nano100Series.h.
| #define USBD_CTL_DPPU_EN_Pos (3) |
USBD_T::CTL: DPPU_EN Position
Definition at line 9769 of file Nano100Series.h.
| #define USBD_CTL_DRVSE0_Msk (0x1ul << USBD_CTL_DRVSE0_Pos) |
USBD_T::CTL: DRVSE0 Mask
Definition at line 9773 of file Nano100Series.h.
| #define USBD_CTL_DRVSE0_Pos (4) |
USBD_T::CTL: DRVSE0 Position
Definition at line 9772 of file Nano100Series.h.
| #define USBD_CTL_PHY_EN_Msk (0x1ul << USBD_CTL_PHY_EN_Pos) |
USBD_T::CTL: PHY_EN Mask
Definition at line 9764 of file Nano100Series.h.
| #define USBD_CTL_PHY_EN_Pos (1) |
USBD_T::CTL: PHY_EN Position
Definition at line 9763 of file Nano100Series.h.
| #define USBD_CTL_PWRDB_Msk (0x1ul << USBD_CTL_PWRDB_Pos) |
USBD_T::CTL: PWRDB Mask
Definition at line 9767 of file Nano100Series.h.
| #define USBD_CTL_PWRDB_Pos (2) |
USBD_T::CTL: PWRDB Position
Definition at line 9766 of file Nano100Series.h.
| #define USBD_CTL_RWAKEUP_Msk (0x1ul << USBD_CTL_RWAKEUP_Pos) |
USBD_T::CTL: RWAKEUP Mask
Definition at line 9776 of file Nano100Series.h.
| #define USBD_CTL_RWAKEUP_Pos (8) |
USBD_T::CTL: RWAKEUP Position
Definition at line 9775 of file Nano100Series.h.
| #define USBD_CTL_USB_EN_Msk (0x1ul << USBD_CTL_USB_EN_Pos) |
USBD_T::CTL: USB_EN Mask
Definition at line 9761 of file Nano100Series.h.
| #define USBD_CTL_USB_EN_Pos (0) |
@addtogroup USBD_CONST USBD Bit Field Definition Constant Definitions for USBD Controller
USBD_T::CTL: USB_EN Position
Definition at line 9760 of file Nano100Series.h.
| #define USBD_CTL_WAKEUP_EN_Msk (0x1ul << USBD_CTL_WAKEUP_EN_Pos) |
USBD_T::CTL: WAKEUP_EN Mask
Definition at line 9779 of file Nano100Series.h.
| #define USBD_CTL_WAKEUP_EN_Pos (9) |
USBD_T::CTL: WAKEUP_EN Position
Definition at line 9778 of file Nano100Series.h.
| #define USBD_EPSTS_EPSTS0_Msk (0xful << USBD_EPSTS_EPSTS0_Pos) |
USBD_T::EPSTS: EPSTS0 Mask
Definition at line 9848 of file Nano100Series.h.
| #define USBD_EPSTS_EPSTS0_Pos (8) |
USBD_T::EPSTS: EPSTS0 Position
Definition at line 9847 of file Nano100Series.h.
| #define USBD_EPSTS_EPSTS1_Msk (0xful << USBD_EPSTS_EPSTS1_Pos) |
USBD_T::EPSTS: EPSTS1 Mask
Definition at line 9851 of file Nano100Series.h.
| #define USBD_EPSTS_EPSTS1_Pos (12) |
USBD_T::EPSTS: EPSTS1 Position
Definition at line 9850 of file Nano100Series.h.
| #define USBD_EPSTS_EPSTS2_Msk (0xful << USBD_EPSTS_EPSTS2_Pos) |
USBD_T::EPSTS: EPSTS2 Mask
Definition at line 9854 of file Nano100Series.h.
| #define USBD_EPSTS_EPSTS2_Pos (16) |
USBD_T::EPSTS: EPSTS2 Position
Definition at line 9853 of file Nano100Series.h.
| #define USBD_EPSTS_EPSTS3_Msk (0xful << USBD_EPSTS_EPSTS3_Pos) |
USBD_T::EPSTS: EPSTS3 Mask
Definition at line 9857 of file Nano100Series.h.
| #define USBD_EPSTS_EPSTS3_Pos (20) |
USBD_T::EPSTS: EPSTS3 Position
Definition at line 9856 of file Nano100Series.h.
| #define USBD_EPSTS_EPSTS4_Msk (0xful << USBD_EPSTS_EPSTS4_Pos) |
USBD_T::EPSTS: EPSTS4 Mask
Definition at line 9860 of file Nano100Series.h.
| #define USBD_EPSTS_EPSTS4_Pos (24) |
USBD_T::EPSTS: EPSTS4 Position
Definition at line 9859 of file Nano100Series.h.
| #define USBD_EPSTS_EPSTS5_Msk (0xful << USBD_EPSTS_EPSTS5_Pos) |
USBD_T::EPSTS: EPSTS5 Mask
Definition at line 9863 of file Nano100Series.h.
| #define USBD_EPSTS_EPSTS5_Pos (28) |
USBD_T::EPSTS: EPSTS5 Position
Definition at line 9862 of file Nano100Series.h.
| #define USBD_EPSTS_OVERRUN_Msk (0x1ul << USBD_EPSTS_OVERRUN_Pos) |
USBD_T::EPSTS: OVERRUN Mask
Definition at line 9845 of file Nano100Series.h.
| #define USBD_EPSTS_OVERRUN_Pos (7) |
USBD_T::EPSTS: OVERRUN Position
Definition at line 9844 of file Nano100Series.h.
| #define USBD_FADDR_FADDR_Msk (0x7ful << USBD_FADDR_FADDR_Pos) |
USBD_T::FADDR: FADDR Mask
Definition at line 9842 of file Nano100Series.h.
| #define USBD_FADDR_FADDR_Pos (0) |
USBD_T::FADDR: FADDR Position
Definition at line 9841 of file Nano100Series.h.
| #define USBD_INTEN_BUSEVT_IE_Msk (0x1ul << USBD_INTEN_BUSEVT_IE_Pos) |
USBD_T::INTEN: BUSEVT_IE Mask
Definition at line 9797 of file Nano100Series.h.
| #define USBD_INTEN_BUSEVT_IE_Pos (0) |
USBD_T::INTEN: BUSEVT_IE Position
Definition at line 9796 of file Nano100Series.h.
| #define USBD_INTEN_FLDET_IE_Msk (0x1ul << USBD_INTEN_FLDET_IE_Pos) |
USBD_T::INTEN: FLDET_IE Mask
Definition at line 9803 of file Nano100Series.h.
| #define USBD_INTEN_FLDET_IE_Pos (2) |
USBD_T::INTEN: FLDET_IE Position
Definition at line 9802 of file Nano100Series.h.
| #define USBD_INTEN_USBEVT_IE_Msk (0x1ul << USBD_INTEN_USBEVT_IE_Pos) |
USBD_T::INTEN: USBEVT_IE Mask
Definition at line 9800 of file Nano100Series.h.
| #define USBD_INTEN_USBEVT_IE_Pos (1) |
USBD_T::INTEN: USBEVT_IE Position
Definition at line 9799 of file Nano100Series.h.
| #define USBD_INTEN_WAKEUP_IE_Msk (0x1ul << USBD_INTEN_WAKEUP_IE_Pos) |
USBD_T::INTEN: WAKEUP_IE Mask
Definition at line 9806 of file Nano100Series.h.
| #define USBD_INTEN_WAKEUP_IE_Pos (3) |
USBD_T::INTEN: WAKEUP_IE Position
Definition at line 9805 of file Nano100Series.h.
| #define USBD_INTSTS_BUS_STS_Msk (0x1ul << USBD_INTSTS_BUS_STS_Pos) |
USBD_T::INTSTS: BUS_STS Mask
Definition at line 9809 of file Nano100Series.h.
| #define USBD_INTSTS_BUS_STS_Pos (0) |
USBD_T::INTSTS: BUS_STS Position
Definition at line 9808 of file Nano100Series.h.
| #define USBD_INTSTS_EPEVT0_Msk (0x1ul << USBD_INTSTS_EPEVT0_Pos) |
USBD_T::INTSTS: EPEVT0 Mask
Definition at line 9821 of file Nano100Series.h.
| #define USBD_INTSTS_EPEVT0_Pos (16) |
USBD_T::INTSTS: EPEVT0 Position
Definition at line 9820 of file Nano100Series.h.
| #define USBD_INTSTS_EPEVT1_Msk (0x1ul << USBD_INTSTS_EPEVT1_Pos) |
USBD_T::INTSTS: EPEVT1 Mask
Definition at line 9824 of file Nano100Series.h.
| #define USBD_INTSTS_EPEVT1_Pos (17) |
USBD_T::INTSTS: EPEVT1 Position
Definition at line 9823 of file Nano100Series.h.
| #define USBD_INTSTS_EPEVT2_Msk (0x1ul << USBD_INTSTS_EPEVT2_Pos) |
USBD_T::INTSTS: EPEVT2 Mask
Definition at line 9827 of file Nano100Series.h.
| #define USBD_INTSTS_EPEVT2_Pos (18) |
USBD_T::INTSTS: EPEVT2 Position
Definition at line 9826 of file Nano100Series.h.
| #define USBD_INTSTS_EPEVT3_Msk (0x1ul << USBD_INTSTS_EPEVT3_Pos) |
USBD_T::INTSTS: EPEVT3 Mask
Definition at line 9830 of file Nano100Series.h.
| #define USBD_INTSTS_EPEVT3_Pos (19) |
USBD_T::INTSTS: EPEVT3 Position
Definition at line 9829 of file Nano100Series.h.
| #define USBD_INTSTS_EPEVT4_Msk (0x1ul << USBD_INTSTS_EPEVT4_Pos) |
USBD_T::INTSTS: EPEVT4 Mask
Definition at line 9833 of file Nano100Series.h.
| #define USBD_INTSTS_EPEVT4_Pos (20) |
USBD_T::INTSTS: EPEVT4 Position
Definition at line 9832 of file Nano100Series.h.
| #define USBD_INTSTS_EPEVT5_Msk (0x1ul << USBD_INTSTS_EPEVT5_Pos) |
USBD_T::INTSTS: EPEVT5 Mask
Definition at line 9836 of file Nano100Series.h.
| #define USBD_INTSTS_EPEVT5_Pos (21) |
USBD_T::INTSTS: EPEVT5 Position
Definition at line 9835 of file Nano100Series.h.
| #define USBD_INTSTS_FLD_STS_Msk (0x1ul << USBD_INTSTS_FLD_STS_Pos) |
USBD_T::INTSTS: FLD_STS Mask
Definition at line 9815 of file Nano100Series.h.
| #define USBD_INTSTS_FLD_STS_Pos (2) |
USBD_T::INTSTS: FLD_STS Position
Definition at line 9814 of file Nano100Series.h.
| #define USBD_INTSTS_SETUP_Msk (0x1ul << USBD_INTSTS_SETUP_Pos) |
USBD_T::INTSTS: SETUP Mask
Definition at line 9839 of file Nano100Series.h.
| #define USBD_INTSTS_SETUP_Pos (31) |
USBD_T::INTSTS: SETUP Position
Definition at line 9838 of file Nano100Series.h.
| #define USBD_INTSTS_USB_STS_Msk (0x1ul << USBD_INTSTS_USB_STS_Pos) |
USBD_T::INTSTS: USB_STS Mask
Definition at line 9812 of file Nano100Series.h.
| #define USBD_INTSTS_USB_STS_Pos (1) |
USBD_T::INTSTS: USB_STS Position
Definition at line 9811 of file Nano100Series.h.
| #define USBD_INTSTS_WKEUP_STS_Msk (0x1ul << USBD_INTSTS_WKEUP_STS_Pos) |
USBD_T::INTSTS: WKEUP_STS Mask
Definition at line 9818 of file Nano100Series.h.
| #define USBD_INTSTS_WKEUP_STS_Pos (3) |
USBD_T::INTSTS: WKEUP_STS Position
Definition at line 9817 of file Nano100Series.h.
| #define USBD_MXPLD_MXPLD_Msk (0x1fful << USBD_MXPLD_MXPLD_Pos) |
USBD_EP_T::MXPLD: MXPLD Mask
Definition at line 9869 of file Nano100Series.h.
| #define USBD_MXPLD_MXPLD_Pos (0) |
USBD_EP_T::MXPLD: MXPLD Position
Definition at line 9868 of file Nano100Series.h.
| #define USBD_PDMA_BYTEM_Msk (0x1ul << USBD_PDMA_BYTEM_Pos) |
USBD_T::PDMA: BYTEM Mask
Definition at line 9899 of file Nano100Series.h.
| #define USBD_PDMA_BYTEM_Pos (2) |
USBD_T::PDMA: BYTEM Position
Definition at line 9898 of file Nano100Series.h.
| #define USBD_PDMA_PDMA_RST_Msk (0x1ul << USBD_PDMA_PDMA_RST_Pos) |
USBD_T::PDMA: PDMA_RST Mask
Definition at line 9902 of file Nano100Series.h.
| #define USBD_PDMA_PDMA_RST_Pos (3) |
USBD_T::PDMA: PDMA_RST Position
Definition at line 9901 of file Nano100Series.h.
| #define USBD_PDMA_PDMA_RW_Msk (0x1ul << USBD_PDMA_PDMA_RW_Pos) |
USBD_T::PDMA: PDMA_RW Mask
Definition at line 9893 of file Nano100Series.h.
| #define USBD_PDMA_PDMA_RW_Pos (0) |
USBD_T::PDMA: PDMA_RW Position
Definition at line 9892 of file Nano100Series.h.
| #define USBD_PDMA_PDMA_TRG_Msk (0x1ul << USBD_PDMA_PDMA_TRG_Pos) |
USBD_T::PDMA: PDMA_TRG Mask
Definition at line 9896 of file Nano100Series.h.
| #define USBD_PDMA_PDMA_TRG_Pos (1) |
USBD_T::PDMA: PDMA_TRG Position
Definition at line 9895 of file Nano100Series.h.
| #define VDMA_BCR_VDMA_BCR_Msk (0xfffful << VDMA_BCR_VDMA_BCR_Pos) |
VDMA_T::BCR: VDMA_BCR Mask
Definition at line 1985 of file Nano100Series.h.
| #define VDMA_BCR_VDMA_BCR_Pos (0) |
VDMA_T::BCR: VDMA_BCR Position
Definition at line 1984 of file Nano100Series.h.
| #define VDMA_BUF0_VDMA_BUF0_Msk (0xfffffffful << VDMA_BUF0_VDMA_BUF0_Pos) |
VDMA_T::BUF0: VDMA_BUF0 Mask
Definition at line 2018 of file Nano100Series.h.
| #define VDMA_BUF0_VDMA_BUF0_Pos (0) |
VDMA_T::BUF0: VDMA_BUF0 Position
Definition at line 2017 of file Nano100Series.h.
| #define VDMA_BUF1_VDMA_BUF1_Msk (0xfffffffful << VDMA_BUF1_VDMA_BUF1_Pos) |
VDMA_T::BUF1: VDMA_BUF1 Mask
Definition at line 2021 of file Nano100Series.h.
| #define VDMA_BUF1_VDMA_BUF1_Pos (0) |
VDMA_T::BUF1: VDMA_BUF1 Position
Definition at line 2020 of file Nano100Series.h.
| #define VDMA_CBCR_VDMA_CBCR_Msk (0xfffful << VDMA_CBCR_VDMA_CBCR_Pos) |
VDMA_T::CBCR: VDMA_CBCR Mask
Definition at line 1994 of file Nano100Series.h.
| #define VDMA_CBCR_VDMA_CBCR_Pos (0) |
VDMA_T::CBCR: VDMA_CBCR Position
Definition at line 1993 of file Nano100Series.h.
| #define VDMA_CDAR_VDMA_CDAR_Msk (0xfffffffful << VDMA_CDAR_VDMA_CDAR_Pos) |
VDMA_T::CDAR: VDMA_CDAR Mask
Definition at line 1991 of file Nano100Series.h.
| #define VDMA_CDAR_VDMA_CDAR_Pos (0) |
VDMA_T::CDAR: VDMA_CDAR Position
Definition at line 1990 of file Nano100Series.h.
| #define VDMA_CSAR_VDMA_CSAR_Msk (0xfffffffful << VDMA_CSAR_VDMA_CSAR_Pos) |
VDMA_T::CSAR: VDMA_CSAR Mask
Definition at line 1988 of file Nano100Series.h.
| #define VDMA_CSAR_VDMA_CSAR_Pos (0) |
VDMA_T::CSAR: VDMA_CSAR Position
Definition at line 1987 of file Nano100Series.h.
| #define VDMA_CSR_DIR_SEL_Msk (0x1ul << VDMA_CSR_DIR_SEL_Pos) |
VDMA_T::CSR: DIR_SEL Mask
Definition at line 1973 of file Nano100Series.h.
| #define VDMA_CSR_DIR_SEL_Pos (11) |
VDMA_T::CSR: DIR_SEL Position
Definition at line 1972 of file Nano100Series.h.
| #define VDMA_CSR_STRIDE_EN_Msk (0x1ul << VDMA_CSR_STRIDE_EN_Pos) |
VDMA_T::CSR: STRIDE_EN Mask
Definition at line 1970 of file Nano100Series.h.
| #define VDMA_CSR_STRIDE_EN_Pos (10) |
VDMA_T::CSR: STRIDE_EN Position
Definition at line 1969 of file Nano100Series.h.
| #define VDMA_CSR_SW_RST_Msk (0x1ul << VDMA_CSR_SW_RST_Pos) |
VDMA_T::CSR: SW_RST Mask
Definition at line 1967 of file Nano100Series.h.
| #define VDMA_CSR_SW_RST_Pos (1) |
VDMA_T::CSR: SW_RST Position
Definition at line 1966 of file Nano100Series.h.
| #define VDMA_CSR_TRIG_EN_Msk (0x1ul << VDMA_CSR_TRIG_EN_Pos) |
VDMA_T::CSR: TRIG_EN Mask
Definition at line 1976 of file Nano100Series.h.
| #define VDMA_CSR_TRIG_EN_Pos (23) |
VDMA_T::CSR: TRIG_EN Position
Definition at line 1975 of file Nano100Series.h.
| #define VDMA_CSR_VDMACEN_Msk (0x1ul << VDMA_CSR_VDMACEN_Pos) |
VDMA_T::CSR: VDMACEN Mask
Definition at line 1964 of file Nano100Series.h.
| #define VDMA_CSR_VDMACEN_Pos (0) |
@addtogroup VDMA_CONST VDMA Bit Field Definition Constant Definitions for VDMA Controller
VDMA_T::CSR: VDMACEN Position
Definition at line 1963 of file Nano100Series.h.
| #define VDMA_DAR_VDMA_DAR_Msk (0xfffffffful << VDMA_DAR_VDMA_DAR_Pos) |
VDMA_T::DAR: VDMA_DAR Mask
Definition at line 1982 of file Nano100Series.h.
| #define VDMA_DAR_VDMA_DAR_Pos (0) |
VDMA_T::DAR: VDMA_DAR Position
Definition at line 1981 of file Nano100Series.h.
| #define VDMA_DASOCR_DASTOBL_Msk (0xfffful << VDMA_DASOCR_DASTOBL_Pos) |
VDMA_T::DASOCR: DASTOBL Mask
Definition at line 2015 of file Nano100Series.h.
| #define VDMA_DASOCR_DASTOBL_Pos (0) |
VDMA_T::DASOCR: DASTOBL Position
Definition at line 2014 of file Nano100Series.h.
| #define VDMA_IER_TABORT_IE_Msk (0x1ul << VDMA_IER_TABORT_IE_Pos) |
VDMA_T::IER: TABORT_IE Mask
Definition at line 1997 of file Nano100Series.h.
| #define VDMA_IER_TABORT_IE_Pos (0) |
VDMA_T::IER: TABORT_IE Position
Definition at line 1996 of file Nano100Series.h.
| #define VDMA_IER_TD_IE_Msk (0x1ul << VDMA_IER_TD_IE_Pos) |
VDMA_T::IER: TD_IE Mask
Definition at line 2000 of file Nano100Series.h.
| #define VDMA_IER_TD_IE_Pos (1) |
VDMA_T::IER: TD_IE Position
Definition at line 1999 of file Nano100Series.h.
| #define VDMA_ISR_TABORT_IS_Msk (0x1ul << VDMA_ISR_TABORT_IS_Pos) |
VDMA_T::ISR: TABORT_IS Mask
Definition at line 2003 of file Nano100Series.h.
| #define VDMA_ISR_TABORT_IS_Pos (0) |
VDMA_T::ISR: TABORT_IS Position
Definition at line 2002 of file Nano100Series.h.
| #define VDMA_ISR_TD_IS_Msk (0x1ul << VDMA_ISR_TD_IS_Pos) |
VDMA_T::ISR: TD_IS Mask
Definition at line 2006 of file Nano100Series.h.
| #define VDMA_ISR_TD_IS_Pos (1) |
VDMA_T::ISR: TD_IS Position
Definition at line 2005 of file Nano100Series.h.
| #define VDMA_SAR_VDMA_SAR_Msk (0xfffffffful << VDMA_SAR_VDMA_SAR_Pos) |
VDMA_T::SAR: VDMA_SAR Mask
Definition at line 1979 of file Nano100Series.h.
| #define VDMA_SAR_VDMA_SAR_Pos (0) |
VDMA_T::SAR: VDMA_SAR Position
Definition at line 1978 of file Nano100Series.h.
| #define VDMA_SASOCR_SASTOBL_Msk (0xfffful << VDMA_SASOCR_SASTOBL_Pos) |
VDMA_T::SASOCR: SASTOBL Mask
Definition at line 2009 of file Nano100Series.h.
| #define VDMA_SASOCR_SASTOBL_Pos (0) |
VDMA_T::SASOCR: SASTOBL Position
Definition at line 2008 of file Nano100Series.h.
| #define VDMA_SASOCR_STBC_Msk (0xfffful << VDMA_SASOCR_STBC_Pos) |
VDMA_T::SASOCR: STBC Mask
Definition at line 2012 of file Nano100Series.h.
| #define VDMA_SASOCR_STBC_Pos (16) |
VDMA_T::SASOCR: STBC Position
Definition at line 2011 of file Nano100Series.h.
| #define WDT_CTL_WTE_Msk (0x1ul << WDT_CTL_WTE_Pos) |
WDT_T::CTL: WTE Mask
Definition at line 10013 of file Nano100Series.h.
| #define WDT_CTL_WTE_Pos (3) |
WDT_T::CTL: WTE Position
Definition at line 10012 of file Nano100Series.h.
| #define WDT_CTL_WTIS_Msk (0x7ul << WDT_CTL_WTIS_Pos) |
WDT_T::CTL: WTIS Mask
Definition at line 10016 of file Nano100Series.h.
| #define WDT_CTL_WTIS_Pos (4) |
WDT_T::CTL: WTIS Position
Definition at line 10015 of file Nano100Series.h.
| #define WDT_CTL_WTR_Msk (0x1ul << WDT_CTL_WTR_Pos) |
WDT_T::CTL: WTR Mask
Definition at line 10004 of file Nano100Series.h.
| #define WDT_CTL_WTR_Pos (0) |
@addtogroup WDT_CONST WDT Bit Field Definition Constant Definitions for WDT Controller
WDT_T::CTL: WTR Position
Definition at line 10003 of file Nano100Series.h.
| #define WDT_CTL_WTRE_Msk (0x1ul << WDT_CTL_WTRE_Pos) |
WDT_T::CTL: WTRE Mask
Definition at line 10007 of file Nano100Series.h.
| #define WDT_CTL_WTRE_Pos (1) |
WDT_T::CTL: WTRE Position
Definition at line 10006 of file Nano100Series.h.
| #define WDT_CTL_WTWKE_Msk (0x1ul << WDT_CTL_WTWKE_Pos) |
WDT_T::CTL: WTWKE Mask
Definition at line 10010 of file Nano100Series.h.
| #define WDT_CTL_WTWKE_Pos (2) |
WDT_T::CTL: WTWKE Position
Definition at line 10009 of file Nano100Series.h.
| #define WDT_IER_IE_Msk (0x1ul << WDT_IER_IE_Pos) |
WDT_T::IER: IE Mask
Definition at line 10019 of file Nano100Series.h.
| #define WDT_IER_IE_Pos (0) |
WDT_T::IER: IE Position
Definition at line 10018 of file Nano100Series.h.
| #define WDT_ISR_IS_Msk (0x1ul << WDT_ISR_IS_Pos) |
WDT_T::ISR: IS Mask
Definition at line 10022 of file Nano100Series.h.
| #define WDT_ISR_IS_Pos (0) |
WDT_T::ISR: IS Position
Definition at line 10021 of file Nano100Series.h.
| #define WDT_ISR_RST_IS_Msk (0x1ul << WDT_ISR_RST_IS_Pos) |
WDT_T::ISR: RST_IS Mask
Definition at line 10025 of file Nano100Series.h.
| #define WDT_ISR_RST_IS_Pos (1) |
WDT_T::ISR: RST_IS Position
Definition at line 10024 of file Nano100Series.h.
| #define WDT_ISR_WAKE_IS_Msk (0x1ul << WDT_ISR_WAKE_IS_Pos) |
WDT_T::ISR: WAKE_IS Mask
Definition at line 10028 of file Nano100Series.h.
| #define WDT_ISR_WAKE_IS_Pos (2) |
WDT_T::ISR: WAKE_IS Position
Definition at line 10027 of file Nano100Series.h.
1.8.15