42 uint32_t u32MasterSlave,
44 uint32_t u32DataWidth,
47 if(u32DataWidth == 32)
130 uint32_t u32ClkSrc, u32Div = 0;
134 if(u32BusClock > u32ClkSrc)
135 u32BusClock = u32ClkSrc;
137 if(u32BusClock != 0 )
139 u32Div = (u32ClkSrc / u32BusClock) - 1;
148 return ( u32ClkSrc / (u32Div+1) );
184 return (u32ClkSrc / (u32Div + 1));
#define SPI_CTL_INTEN_Msk
#define SPI_SSTA_INTEN_MASK
void SPI_DisableAutoSS(SPI_T *spi)
Disable the automatic slave select function.
void SPI_EnableFIFO(SPI_T *spi)
Enable FIFO mode with user-specified Tx FIFO threshold and Rx FIFO threshold configurations.
#define SPI_CTL_TX_BIT_LEN_Pos
#define SPI_FFCLR_RX_CLR_Msk
uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock)
Set the SPI bus clock. Only available in Master mode.
#define SPI_CTL_FIFOM_Msk
#define SPI_SSR_SS_LVL_Msk
#define SPI0
Pointer to SPI0 register structure.
uint32_t CLK_GetHCLKFreq(void)
This function get HCLK frequency. The frequency unit is Hz.
#define SPI1
Pointer to SPI1 register structure.
void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask)
Enable FIFO related interrupts specified by u32Mask parameter.
Nano100 series peripheral access layer header file. This file contains all the peripheral register's ...
void SPI_ClearRxFIFO(SPI_T *spi)
Clear Rx FIFO buffer.
#define SYS_IPRST_CTL2_SPI0_RST_Msk
void SPI_Close(SPI_T *spi)
Reset SPI module.
#define SPI_CLKDIV_DIVIDER1_Msk
void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask)
Disable FIFO related interrupts specified by u32Mask parameter.
uint32_t SPI_GetBusClock(SPI_T *spi)
Get the actual frequency of SPI bus clock. Only available in Master mode.
#define SYS_IPRST_CTL2_SPI1_RST_Msk
void SPI_DisableFIFO(SPI_T *spi)
Disable FIFO mode.
void SPI_ClearTxFIFO(SPI_T *spi)
Clear Tx FIFO buffer.
void SPI_DisableWakeup(SPI_T *spi)
Disable wake-up function.
#define SPI_FFCLR_TX_CLR_Msk
void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel)
Enable the automatic slave select function. Only available in Master mode.
uint32_t SPI_Open(SPI_T *spi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock)
This function make SPI module be ready to transfer. By default, the SPI transfer sequence is MSB firs...
#define SPI_SSR_AUTOSS_Msk
#define SPI_SSR_SSTA_INTEN_Msk
void SPI_EnableWakeup(SPI_T *spi)
Enable wake-up function.
#define SYS_IPRST_CTL2_SPI2_RST_Msk
#define SPI_CTL_WKEUP_EN_Msk
#define SYS
Pointer to SYS register structure.