| Nano100AN Series BSP V3.02.002 The Board Support Package for Nano100AN Series

Data Fields
SC_T Struct Reference

`#include <Nano100Series.h>`

## Data Fields
union {
__I uint32_t RBR
__O uint32_t THR
}; |
__IO uint32_t | CTL
__IO uint32_t | ALTCTL
__IO uint32_t | EGTR
__IO uint32_t | RFTMR
__IO uint32_t | ETUCR
__IO uint32_t | IER
__IO uint32_t | ISR
__IO uint32_t | TRSR
__IO uint32_t | PINCSR
__IO uint32_t | TMR0
__IO uint32_t | TMR1
__IO uint32_t | TMR2
__I uint32_t | TDRA
__I uint32_t | TDRB

## Detailed Description

    @addtogroup SC Smart Card Host Interface Controller(SC)
    Memory Mapped Structure for SC Controller

Definition at line 6996 of file Nano100Series.h.

## Field Documentation

## ◆ @1

union { ... }

## ◆ ALTCTL

__IO uint32_t SC_T::ALTCTL

# ALTCTL

## Offset: 0x08 SC Alternate Control Register.

Bits | Field | Descriptions
--- | --- | ---
[0] | TX_RST | TX Software Reset
|  | When TX_RST is set, all the bytes in the transmit buffer and TX internal state machine will be cleared.
|  | 0 = No effect.
|  | 1 = Reset the TX internal state machine and pointers.
|  | Note: This bit will be auto cleared and needs at least 3 SC engine clock cycles.
[1] | RX_RST | RX Software Reset
|  | When RX_RST is set, all the bytes in the receiver buffer and RX internal state machine will be cleared.
|  | 0 = No effect.
|  | 1 = Reset the RX internal state machine and pointers.
|  | Note: This bit will be auto cleared and needs at least 3 SC engine clock cycles.
[2] | DACT_EN | Deactivation Sequence Generator Enable
|  | This bit enables SC controller to initiate the card by deactivation sequence
|  | 0 = No effect.
|  | 1 = Deactivation sequence generator Enabled.
|  | Note1: When the deactivation sequence completed, this bit will be cleared automatically and the SC_ISR [INIT_IS] will be set to "1".
|  | Note2: This field will be cleared by TX_RST and RX_RST.
|  | So don't fill this bit, TX_RST, and RX_RST at the same time.
|  | Note3: If SC_CTL [SC_CEN] is not enabled, this filed can not be programmed.
[3] | ACT_EN | Activation Sequence Generator Enable
|  | This bit enables SC controller to initiate the card by activation sequence
|  | 0 = No effect.
|  | 1 = Activation sequence generator Enabled.
|  | Note1: When the activation sequence completed, this bit will be cleared automatically and the SC_IS [INIT_IS] will be set to "1".
|  | Note2: This field will be cleared by TX_RST and RX_RST, so don't fill this bit, TX_RST, and RX_RST at the same time.
|  | Note3: If SC_CTL [SC_CEN] is not enabled, this filed can not be programmed.
[4] | WARST_EN | Warm Reset Sequence Generator Enable
|  | This bit enables SC controller to initiate the card by warm reset sequence
|  | 0 = No effect.
|  | 1 = Warm reset sequence generator Enabled.
|  | Note1: When the warm reset sequence completed, this bit will be cleared automatically and the SC_ISR [INIT_IS] will be set to "1".
|  | Note2: This field will be cleared by TX_RST and RX_RST, so don't fill this bit, TX_RST, and RX_RST at the same time.
|  | Note3: If SC_CTL [SC_CEN] is not enabled, this filed can not be programmed.
[5] | TMR0_SEN | Internal Timer0 Start Enable
|  | This bit enables Timer0 to start counting.
|  | Software can fill "0" to stop it and set "1" to reload and count.
|  | 0 = Stops counting.
|  | 1 = Starts counting.
|  | Note1: This field is used for internal 24 bit timer when SC_CTL [TMR_SEL] = 01.
|  | Note2: If the operation mode is not in auto-reload mode (SC_TMR0 [26] = "0"), this bit will be auto-cleared by hardware.
|  | Note3: This field will be cleared by TX_RST and RX_RST.
|  | So don't fill this bit, TX_RST and RX_RST at the same time.
|  | Note4: If SC_CTL [SC_CEN] is not enabled, this filed can not be programmed.
[6] | TMR1_SEN | Internal Timer1 Start Enable
|  | This bit enables Timer "1" to start counting.
|  | Software can fill 0 to stop it and set "1" to reload and count.
|  | 0 = Stops counting.
|  | 1 = Starts counting.
|  | Note1: This field is used for internal 8 bit timer when SC_CTL [TMR_SEL] = 01 or 10.
|  | Don't filled TMR1_SEN when SC_CTL [TMR_SEL] = 00 or 11.
|  | Note2: If the operation mode is not in auto-reload mode (SC_TMR1 [26] = "0"), this bit will be auto-cleared by hardware.
|  | Note3: This field will be cleared by TX_RST and RX_RST, so don't fill this bit, TX_RST, and RX_RST at the same time.
|  | Note4: If SC_CTL [SC_CEN] is not enabled, this filed can not be programmed.
[7] | TMR2_SEN | Internal Timer2 Start Enable
|  | This bit enables Timer2 to start counting.
|  | Software can fill "0" to stop it and set "1" to reload and count.
|  | 0 = Stops counting.
|  | 1 = Starts counting.
|  | Note1: This field is used for internal 8 bit timer when SC_CTL [TMR_SEL] == 11.
|  | Don't filled TMR2_SEN when SC_CTL [TMR_SEL] == 00 or 01 or 10.
|  | Note2: If the operation mode is not in auto-reload mode (SC_TMR2 [26] = "0"), this bit will be auto-cleared by hardware.
|  | Note3: This field will be cleared by TX_RST and RX_RST.
|  | So don't fill this bit, TX_RST, and RX_RST at the same time.
|  | Note4: If SC_CTL [SC_CEN] is not enabled, this filed can not be programmed.
[9:8] | INIT_SEL | Initial Timing Selection
|  | This field indicates the timing of hardware initial state (activation or warm-reset or deactivation).
[12] | RX_BGT_EN | Receiver Block Guard Time Function Enable
|  | 0 = Receiver block guard time function Disabled.
|  | 1 = Receiver block guard time function Enabled.
[13] | TMR0_ATV | Internal Timer0 Active State (Read Only)
|  | This bit indicates the timer counter status of timer0.
|  | 0 = Timer0 is not active.
|  | 1 = Timer0 is active.
[14] | TMR1_ATV | Internal Timer1 Active State (Read Only)
|  | This bit indicates the timer counter status of timer1.
|  | 0 = Timer1 is not active.
|  | 1 = Timer1 is active.
[15] | TMR2_ATV | Internal Timer2 Active State (Read Only)
|  | This bit indicates the timer counter status of timer2.
|  | 0 = Timer2 is not active.
|  | 1 = Timer2 is active.

Definition at line 7200 of file Nano100Series.h.

## ◆ CTL

__IO uint32_t SC_T::CTL

# CTL

## Offset: 0x04 SC Control Register.

Bits | Field | Descriptions
--- | --- | ---
[0] | SC_CEN | SC Engine Enable
|  | Setting this bit to "1" to enable SC operation.
|  | If this bit is cleared, SC will force all transition to IDLE state.
[1] | DIS_RX | RX Transition Disable
|  | 0 = Receiver Enabled.
|  | 1 = Receiver Disabled.
[2] | DIS_TX | TX Transition Disable
|  | 0 = Transceiver Enabled.
|  | 1 = Transceiver Disabled.
[3] | AUTO_CON_EN | Auto Convention Enable
|  | 0 = Auto-convention Disabled.
|  | 1 = Auto-convention Enabled.
|  | When hardware receives TS in answer to reset state and the TS is direct convention, CON_SEL will be set to 00 automatically, otherwise if the TS is inverse convention, CON_SEL will be set to 11.
|  | If software enables auto convention function, the setting step must be done before Answer to Request state and the first data must be 0x3B or 0x3F.
|  | After hardware received first data and stored it at buffer, hardware will decided the convention and change the SC_CTL[CON_SEL] register automatically.
|  | If the first data is not 0x3B or 0x3F, hardware will generate an interrupt INT_ACON_ERR(if SC_IER [ACON_ERR_IE = "1"] to CPU.
[5:4] | CON_SEL | Convention Selection
|  | 00 = Direct convention.
|  | 01 = Reserved.
|  | 10 = Reserved.
|  | 11 = Inverse convention.
|  | Note: If AUTO_CON_EN is enabled, this field must be ignored.
[7:6] | RX_FTRI_LEV | RX Buffer Trigger Level
|  | When the number of bytes in the receiving buffer equals the RX_FTRI_LEV, the RDA_IF will be set (if IER [RDA_IEN] is enabled, an interrupt will be generated).
|  | 00 = INTR_RDA Trigger Level 1 byte.
|  | 01 = INTR_RDA Trigger Level 2 bytes.
|  | 10 = INTR_RDA Trigger Level 3 bytes.
|  | 11 = Reserved.
[12:8] | BGT | Block Guard Time (BGT)
|  | This field indicates the counter for block guard time.
|  | According to ISO7816-3, in T=0 mode, software must fill 15 (real block guard time = 16) to this field and in T=1 mode software must fill 21 (real block guard time = 22) to it.
|  | In TX mode, hardware will auto hold off first character until BGT has elapsed regardless of the TX data.
|  | In RX mode, software can enable SC_ALTCTL [RX_BGT_EN] to detect the first coming character timing.
|  | If the incoming data timing less than BGT, an interrupt will be generated.
|  | Note: The real block guard time is BGT + 1.
[14:13] | TMR_SEL | Timer Selection
|  | 00 = Disable all internal timer function.
|  | 01 = Enable internal 24 bit timer.
|  | Software can configure it by setting SC_TMR0 [23:0].
|  | SC_TMR1 and SC_TMR2 will be ignored in this mode.
|  | 10 = Enable internal 24 bit timer and 8 bit internal timer.
|  | Software can configure the 24 bit timer by setting SC_TMR0 [23:0] and configure the 8 bit timer by setting SC_TMR1 [7:0].
|  | SC_TMR2 will be ignored in this mode.
|  | 11 = Enable internal 24 bit timer and two 8 bit timers.
|  | Software can configure them by setting SC_TMR0 [23:0], SC_TMR1 [7:0] and SC_TMR2 [7:0].
[15] | SLEN | Stop Bit Length
|  | This field indicates the length of stop bit.
|  | 0 = The stop bit length is 2 ETU.
|  | 1= The stop bit length is 1 ETU.
|  | Note: The default stop bit length is 2.
[18:16] | RX_ERETRY | RX Error Retry Register
|  | This field indicates the maximum number of receiver retries that are allowed when parity error has occurred.
|  | Note1: The real maximum retry number is RX_ERETRY + 1, so 8 is the maximum retry number.
|  | Note2: This field can not be changed when RX_ERETRY_EN enabled.
|  | The change flow is to disable RX_ETRTRY_EN first and then fill new retry value.
[19] | RX_ERETRY_EN | RX Error Retry Enable Register
|  | This bit enables receiver retry function when parity error has occurred.
|  | 0 = RX error retry function Disabled.
|  | 1 = RX error retry function Enabled.
|  | Note: User must fill RX_ERETRY value before enabling this bit.
[22:20] | TX_ERETRY | TX Error Retry Register
|  | This field indicates the maximum number of transmitter retries that are allowed when parity error has occurred.
|  | Note1: The real retry number is TX_ERETRY + 1, so 8 is the maximum retry number.
|  | Note2: This field can not be changed when TX_ERETRY_EN enabled.
|  | The change flow is to disable TX_ETRTRY_EN first and then fill new retry value.
[23] | TX_ERETRY_EN | TX Error Retry Enable Register
|  | This bit enables transmitter retry function when parity error has occurred.
|  | 0 = TX error retry function Disabled.
|  | 1 = TX error retry function Enabled.
|  | Note: User must fill TX_ERETRY value before enabling this bit.
[25:24] | CD_DEB_SEL | Card Detect De-Bounce Select Register
|  | This field indicates the card detect de-bounce selection.
|  | 00 = De-bounce sample card insert once per 384 (128 * 3) engine clocks and de-bounce sample card removal once per 128 engine clocks.
|  | 01 = De-bounce sample card insert once per 192 (64 * 3) engine clocks and de-bounce sample card removal once per 64 engine clocks.
|  | 10 = De-bounce sample card insert once per 96 (32 * 3) engine clocks and de-bounce sample card removal once per 32 engine clocks.
|  | 11 = De-bounce sample card insert once per 48 (16 * 3) engine clocks and de-bounce sample card removal once per 16 engine clocks.

Definition at line 7110 of file Nano100Series.h.

## ◆ EGTR

__IO uint32_t SC_T::EGTR

# EGTR

## Offset: 0x0C SC Extend Guard Time Register.

Bits | Field | Descriptions
--- | --- | ---
[7:0] | EGT | Extended Guard Time
|  | This field indicates the extended guard timer value.
|  | Note: The counter is ETU based and the real extended guard time is EGT.

Definition at line 7213 of file Nano100Series.h.

## ◆ ETUCR

__IO uint32_t SC_T::ETUCR

# ETUCR

## Offset: 0x14 SC ETU Control Register.

Bits | Field | Descriptions
--- | --- | ---
[11:0] | ETU_RDIV | ETU Rate Divider
|  | The field indicates the clock rate divider.
|  | The real ETU is ETU_RDIV + 1.
|  | Note1: Software can configure this field, but this field must be greater than 0x04.
|  | Note2: Software can configure this field, but if the error rate is equal to 2%, this field must be greater than 0x040.
[15] | COMPEN_EN | Compensation Mode Enable
|  | This bit enables clock compensation function.
|  | When this bit enabled, hardware will alternate between n clock cycles and (n-1) clock cycles, where n is the value to be written into the ETU_RDIV register.
|  | 0 = Compensation function Disabled.
|  | 1 = Compensation function Enabled.

Definition at line 7248 of file Nano100Series.h.

## ◆ IER

__IO uint32_t SC_T::IER

# IER

## Offset: 0x18 SC Interrupt Enable Register.

Bits | Field | Descriptions
--- | --- | ---
[0] | RDA_IE | Receive Data Reach Interrupt Enable
|  | This field is used for received data reaching trigger level (SC_CTL [RX_FTRI_LEV]) interrupt enable.
|  | 0 = INT_RDR Disabled.
|  | 1 = INT_RDR Enabled.
[1] | TBE_IE | Transmit Buffer Empty Interrupt Enable
|  | This field is used for transmit buffer empty interrupt enable.
|  | 0 = INT_THRE Disabled.
|  | 1 = INT_THRE Enabled.
[2] | TERR_IE | Transfer Error Interrupt Enable
|  | This field is used for transfer error interrupt enable.
|  | The transfer error states is at SC_TRSR register which includes receiver break error (RX_EBR_F), frame error (RX_EFR_F), parity error (RX_EPA_F), receiver buffer overflow error (RX_OVER_F), transmit buffer overflow error (TX_OVER_F), receiver retry over limit error (RX_OVER_ERETRY) and transmitter retry over limit error (TX_OVER_ERETRY).
|  | 0 = INT_TERR Disabled.
|  | 1 = INT_TERR Enabled.
[3] | TMR0_IE | Timer0 Interrupt Enable
|  | This field is used for TMR0 interrupt enable.
|  | 0 = INT_TMR0 Disabled.
|  | 1 = INT_TMR0 Enabled.
[4] | TMR1_IE | Timer1 Interrupt Enable
|  | This field is used for TMR1 interrupt enable.
|  | 0 = INT_TMR1 Disabled.
|  | 1 = INT_TMR1 Enabled.
[5] | TMR2_IE | Timer2 Interrupt Enable
|  | This field is used for TMR2 interrupt enable.
|  | 0 = INT_TMR2 Disabled.
|  | 1 = INT_TMR2 Enabled.
[6] | BGT_IE | Block Guard Time Interrupt Enable
|  | This field is used for block guard time interrupt enable.
|  | 0 = INT_BGT Disabled.
|  | 1 = INT_BGT Enabled.
[7] | CD_IE | Card Detect Interrupt Enable
|  | This field is used for card detect interrupt enable.
|  | The card detect status register is SC_PINCSR [CD_CH] and SC_PINCSR[CD_CL].
|  | 0 = INT_CD Disabled.
|  | 1 = INT_CD Enabled.
[8] | INIT_IE | Initial End Interrupt Enable
|  | This field is used for activation (SC_ALTCTL [ACT_EN]), deactivation (SC_ALTCTL [DACT_EN]) and warm reset (SC_ALTCTL [WARST_EN]) sequence interrupt enable.
|  | 0 = INT_INIT Disabled.
|  | 1 = INT_INIT Enabled.
[9] | RTMR_IE | Receiver Buffer Time-Out Interrupt Enable
|  | This field is used for receiver buffer time-out interrupt enable.
|  | 0 = INT_RTMR Disabled.
|  | 1 = INT_RTMR Enabled.
[10] | ACON_ERR_IE | Auto Convention Error Interrupt Enable
|  | This field is used for auto convention error interrupt enable.
|  | 0 = INT_ACON_ERR Disabled.
|  | 1 = INT_ACON_ERR Enabled.
[15] | COMPEN_EN | Compensation Mode Enable
|  | This bit enables clock compensation function.
|  | When this bit enabled, hardware will alternate between n clock cycles and (n-1) clock cycles, where n is the value to be written into the ETU_RDIV register.
|  | 0 = Compensation function Disabled.
|  | 1 = Compensation function Enabled.

Definition at line 7309 of file Nano100Series.h.

## ◆ ISR

__IO uint32_t SC_T::ISR

# ISR

## Offset: 0x1C SC Interrupt Status Register.

Bits | Field | Descriptions
--- | --- | ---
[0] | RDA_IS | Receive Data Reach Interrupt Status Flag (Read Only)
|  | This field is used for received data reaching trigger level (SC_CTL [RX_FTRI_LEV]) interrupt status flag.
|  | Note: This field is the status flag of received data reaching SC_CTL [RX_FTRI_LEV].
|  | If software reads data from SC_RBR and receiver pointer is less than SC_CTL [RX_FTRI_LEV], this bit will be cleared automatically.
[1] | TBE_IS | Transmit Buffer Empty Interrupt Status Flag (Read Only)
|  | This field is used for transmit buffer empty interrupt status flag.
|  | This bit is different with SC_TRSR [TX_EMPTY_F] flag and SC_TRSR [TX_ATV] flag; The TX_EMPTY_F will be set when the last byte data be read to shift register and TX_ATV flag indicates the transmitter is in active or not (the last data has been transmitted or not), but the TBE_IS may be set when the last byte data be read to shift register or the last data has been transmitted.
|  | When this bit assert, software can write 1~4 byte data to SC_THR register.
|  | Note: If software wants to clear this bit, software must write data to SC_THR register and then this bit will be cleared automatically.
[2] | TERR_IS | Transfer Error Interrupt Status Flag (Read Only)
|  | This field is used for transfer error interrupt status flag.
|  | The transfer error states is at SC_TRSR register which includes receiver break error (RX_EBR_F), frame error (RX_EFR_F), parity error (RX_EPA_F) and receiver buffer overflow error (RX_OVER_F), transmit buffer overflow error (TX_OVER_F), receiver retry over limit error (RX_OVER_ERETRY) and transmitter retry over limit error (TX_OVER_ERETRY).
|  | Note: This field is the status flag of SC_TRSR [RX_EBR_F], SC_TRSR [RX_EFR_F], SC_TRSR [RX_EPA_F], SC_TRSR [RX_OVER_F], SC_TRSR [TX_OVER_F], SC_TRSR [RX_OVER_ERETRY] or SC_TRSR [TX_OVER_ERETRY].
|  | So if software wants to clear this bit, software must write "1" to each field.
[3] | TMR0_IS | Timer0 Interrupt Status Flag (Read Only)
|  | This field is used for TMR0 interrupt status flag.
|  | Note: This bit is read only, but it can be cleared by writing "1" to it.
[4] | TMR1_IS | Timer1 Interrupt Status Flag (Read Only)
|  | This field is used for TMR1 interrupt status flag.
|  | Note: This bit is read only, but it can be cleared by writing "1" to it.
[5] | TMR2_IS | Timer2 Interrupt Status Flag (Read Only)
|  | This field is used for TMR2 interrupt status flag.
|  | Note: This bit is read only, but it can be cleared by writing "1" to it.
[6] | BGT_IS | Block Guard Time Interrupt Status Flag (Read Only)
|  | This field is used for block guard time interrupt status flag.
|  | Note: This bit is read only, but it can be cleared by writing "1" to it.
[7] | CD_IS | Card Detect Interrupt Status Flag (Read Only)
|  | This field is used for card detect interrupt status flag.
|  | The card detect status register is SC_PINCSR [CD_INS_F] and SC_PINCSR [CD_REM_F].
|  | Note: This field is the status flag of SC_PINCSR [CD_INS_F] or SC_PINCSR [CD_REM_F].
|  | So if software wants to clear this bit, software must write "1" to this field.
[8] | INIT_IS | Initial End Interrupt Status Flag (Read Only)
|  | This field is used for activation (SC_ALTCTL [ACT_EN]), deactivation (SC_ALTCTL [DACT_EN]) and warm reset (SC_ALTCTL [WARST_EN]) sequence interrupt status flag.
|  | Note: This bit is read only, but it can be cleared by writing "1" to it.
[9] | RTMR_IS | Receiver Buffer Time-Out Interrupt Status Flag (Read Only)
|  | This field is used for receiver buffer time-out interrupt status flag.
|  | Note: This field is the status flag of receiver buffer time-out state.
|  | If software wants to clear this bit, software must read the receiver buffer remaining data by reading SC_RBR register,.
[10] | ACON_ERR_IS | Auto Convention Error Interrupt Status Flag (Read Only)
|  | This field indicates auto convention sequence error.
|  | If the received TS at ATR state is not 0x3B or 0x3F, this bit will be set.
|  | Note: This bit is read only, but can be cleared by writing "1" to it.

Definition at line 7361 of file Nano100Series.h.

## ◆ PINCSR

__IO uint32_t SC_T::PINCSR

# PINCSR

## Offset: 0x24 SC Pin Control State Register.

Bits | Field | Descriptions
--- | --- | ---
[0] | POW_EN | SC_POW_EN Pin Signal
|  | This bit is the pin status of SC_POW_EN but user can drive SC_POW_EN pin to high or low by setting this bit.
|  | 0 = Drive SC_POW_EN pin to low.
|  | 1 = Drive SC_POW_EN pin to high.
|  | Note: When operation at activation, warm reset or deactivation mode, this bit will be changed automatically.
|  | So don't fill this field when operation in these modes.
[1] | SC_RST | SC_RST Pin Signal
|  | This bit is the pin status of SC_RST but user can drive SC_RST pin to high or low by setting this bit.
|  | 0 = Drive SC_RST pin to low.
|  | 1 = Drive SC_RST pin to high.
|  | Note: When operation at activation, warm reset or deactivation mode, this bit will be changed automatically.
|  | So don't fill this field when operation in these modes.
[2] | CD_REM_F | Card Detect Removal Status Of SC_CD Pin (Read Only)
|  | This bit is set whenever card has been removal.
|  | 0 = No effect.
|  | 1 = Card Removal.
|  | Note1: This bit is read only, but it can be cleared by writing "1" to it.
|  | Note2: Card detect engine will start after SC_CTL [SC_CEN] set.
[3] | CD_INS_F | Card Detect Insert Status Of SC_CD Pin (Read Only)
|  | This bit is set whenever card has been inserted.
|  | 0 = No effect.
|  | 1 = Card insert.
|  | Note1: This bit is read only, but it can be cleared by writing "1" to it.
|  | Note2: Card detect engine will start after SC_CTL [SC_CEN] set.
[4] | CD_PIN_ST | Card Detect Status Of SC_CD Pin Status (Read Only)
|  | This bit is the pin status flag of SC_CD
|  | 0 = SC_CD pin state at low.
|  | 1 = SC_CD pin state at high.
[6] | CLK_KEEP | SC Clock Enable
|  | 0 = SC clock generation Disabled.
|  | 1 = SC clock always keeps free running.
|  | Note: When operation at activation, warm reset or deactivation mode, this bit will be changed automatically.
|  | So don't fill this field when operation in these modes.
[7] | ADAC_CD_EN | Auto Deactivation When Card Removal
|  | 0 = Auto deactivation Disabled when hardware detected the card is removal.
|  | 1 = Auto deactivation Enabled when hardware detected the card is removal.
|  | Note1: When the card is removal, hardware will stop any process and then do deactivation sequence (if this bit be setting).
|  | If this process completes.
|  | Hardware will generate an interrupt INT_INIT to CPU.
[8] | SC_OEN_ST | SC Data Output Enable Pin Status (Read Only)
|  | This bit is the pin status of SC_DATA_OEN
|  | 0 = The SC_DATA_OEN pin state at low.
|  | 1 = The SC_DATA_OEN pin state at high.
[9] | SC_DATA_O | SC Data Output Pin
|  | This bit is the pin status of SC_DATA_O but user can drive SC_DATA_O pin to high or low by setting this bit.
|  | 0 = Drive SC_DATA_O pin to low.
|  | 1 = Drive SC_DATA_O pin to high.
|  | Note: When SC is at activation, warm reset or deactivation mode, this bit will be changed automatically.
|  | So don't fill this field when SC is in these modes.
[10] | CD_LEV | Card Detect Level
|  | 0 = When hardware detects the card detect pin from high to low, it indicates a card is detected.
|  | 1 = When hardware detects the card detect pin from low to high, it indicates a card is detected.
|  | Note: Software must select card detect level before Smart Card engine enable
[16] | SC_DATA_I_ST | SC Data Input Pin Status (Read Only)
|  | This bit is the pin status of SC_DATA_I
|  | 0 = The SC_DATA_I pin is low.
|  | 1 = The SC_DATA_I pin is high.

Definition at line 7503 of file Nano100Series.h.

## ◆ RBR

__I uint32_t SC_T::RBR

# RBR

## Offset: 0x00 SC Receive Buffer Register

Bits | Field | Descriptions
--- | --- | ---
[7:0] | RBR | Receiving Buffer
|  | By reading this register, the SC Controller will return an 8-bit data received from RX pin (LSB first).

Definition at line 7012 of file Nano100Series.h.

## ◆ RFTMR

__IO uint32_t SC_T::RFTMR

# RFTMR

## Offset: 0x10 SC Receive Buffer Time-Out Register.

Bits | Field | Descriptions
--- | --- | ---
[8:0] | RFTM | SC Receiver Buffer Time-Out Register (ETU Based)
|  | The time-out counter resets and starts counting whenever the RX buffer received a new data word.
|  | Once the counter decrease to "1" and no new data is received or CPU does not read data by reading SC_RBR register, a receiver time-out interrupt INT_RTMR will be generated(if SC_IER[RTMR_IE] is high).
|  | Note1: The counter is ETU based and the real count value is RFTM + 1
|  | Note2: Fill all "0" to this field to disable this function.

Definition at line 7228 of file Nano100Series.h.

## ◆ TDRA

__I uint32_t SC_T::TDRA

# TDRA

## Offset: 0x38 SC Timer Current Data Register A.

Bits | Field | Descriptions
--- | --- | ---
[23:0] | TDR0 | Timer0 Current Data Register (Read Only)
|  | This field indicates the current count values of timer0.

Definition at line 7562 of file Nano100Series.h.

## ◆ TDRB

__I uint32_t SC_T::TDRB

# TDRB

## Offset: 0x3C SC Timer Current Data Register B.

Bits | Field | Descriptions
--- | --- | ---
[7:0] | TDR1 | Timer1 Current Data Register (Read Only)
|  | This field indicates the current count values of timer1.
[15:8] | TDR2 | Timer2 Current Data Register (Read Only)
|  | This field indicates the current count values of timer2.

Definition at line 7576 of file Nano100Series.h.

## ◆ THR

__O uint32_t SC_T::THR

# THR

## Offset: 0x00 SC Transmit Buffer Register

Bits | Field | Descriptions
--- | --- | ---
[7:0] | THR | Transmit Buffer
|  | By writing to this register, the SC sends out an 8-bit data through the TX pin (LSB first).

Definition at line 7023 of file Nano100Series.h.

## ◆ TMR0

__IO uint32_t SC_T::TMR0

# TMR0

## Offset: 0x28 SC Internal Timer Control Register 0.

Bits | Field | Descriptions
--- | --- | ---
[23:0] | CNT | Timer 0 Counter Value Register (ETU Base)
|  | This field indicates the internal timer operation values.
[27:24] | MODE | Timer 0 Operation Mode Selection
|  | This field indicates the internal 24 bit timer operation selection.

Definition at line 7517 of file Nano100Series.h.

## ◆ TMR1

__IO uint32_t SC_T::TMR1

# TMR1

## Offset: 0x2C SC Internal Timer Control Register 1.

Bits | Field | Descriptions
--- | --- | ---
[7:0] | CNT | Timer 1 Counter Value Register (ETU Base)
|  | This field indicates the internal timer operation values.
[27:24] | MODE | Timer 1 Operation Mode Selection
|  | This field indicates the internal 8 bit timer operation selection.

Definition at line 7531 of file Nano100Series.h.

## ◆ TMR2

__IO uint32_t SC_T::TMR2

# TMR2

## Offset: 0x30 SC Internal Timer Control Register 2.

Bits | Field | Descriptions
--- | --- | ---
[7:0] | CNT | Timer 2 Counter Value Register (ETU Base)
|  | This field indicates the internal timer operation values.
[27:24] | MODE | Timer 2 Operation Mode Selection
|  | This field indicates the internal 8 bit timer operation selection.

Definition at line 7545 of file Nano100Series.h.

## ◆ TRSR

__IO uint32_t SC_T::TRSR

# TRSR

## Offset: 0x20 SC Transfer Status Register.

Bits | Field | Descriptions
--- | --- | ---
[0] | RX_OVER_F | RX Overflow Error Status Flag (Read Only)
|  | This bit is set when RX buffer overflow.
|  | If the number of received bytes is greater than RX Buffer (SC_RBR) size, 4 bytes of SC, this bit will be set.
|  | Note1: This bit is read only, but it can be cleared by writing "1" to it.
|  | Note2: The overwrite data will be ignored.
[1] | RX_EMPTY_F | Receiver Buffer Empty Status Flag(Read Only)
|  | This bit indicates RX buffer empty or not.
|  | When the last byte of RX buffer has been read by CPU, hardware sets this bit high.
|  | It will be cleared when SC receives any new data.
[2] | RX_FULL_F | Receiver Buffer Full Status Flag (Read Only)
|  | This bit indicates RX buffer full or not.
|  | This bit is set when RX pointer is equal to 4, otherwise it is cleared by hardware.
[4] | RX_EPA_F | Receiver Parity Error Status Flag (Read Only)
|  | This bit is set to logic "1" whenever the received character does not have a valid "parity bit".
|  | Note1: This bit is read only, but it can be cleared by writing "1" to it.
|  | Note2: If CPU sets receiver retries function by setting SC_CTL [RX_ERETRY_EN] register, hardware will not set this flag.
[5] | RX_EFR_F | Receiver Frame Error Status Flag (Read Only)
|  | This bit is set to logic "1" whenever the received character does not have a valid "stop bit" (that is, the stop bit following the last data bit or parity bit is detected as a logic "0").
|  | Note1: This bit is read only, but can be cleared by writing "1" to it.
|  | Note2: If CPI sets receiver retries function by setting SC_CTL [RX_ERETRY_EN] register, hardware will not set this flag.
[6] | RX_EBR_F | Receiver Break Error Status Flag (Read Only)
|  | This bit is set to a logic "1" whenever the received data input (RX) held in the "spacing state" (logic "0") is longer than a full word transmission time (that is, the total time of "start bit" + data bits + parity + stop bits).
|  | Note1: This bit is read only, but it can be cleared by writing "1" to it.
|  | Note2: If CPU sets receiver retries function by setting SC_CTL [RX_ERETRY_EN] register, hardware will not set this flag.
[8] | TX_OVER_F | TX Overflow Error Interrupt Status Flag (Read Only)
|  | If TX buffer is full (TX_FULL_F = "1"), an additional write data to SC_THR will cause this bit to logic "1".
|  | Note1: This bit is read only, but it can be cleared by writing "1" to it.
|  | Note2: The additional write data will be ignored.
[9] | TX_EMPTY_F | Transmit Buffer Empty Status Flag (Read Only)
|  | This bit indicates TX buffer empty or not.
|  | When the last byte of TX buffer has been transferred to Transmitter Shift Register, hardware sets this bit high.
|  | It will be cleared when writing data into SC_THR (TX buffer not empty).
[10] | TX_FULL_F | Transmit Buffer Full Status Flag (Read Only)
|  | This bit indicates TX buffer full or not.
|  | This bit is set when TX pointer is equal to 4, otherwise is cleared by hardware.
[18:16] | RX_POINT_F | Receiver Buffer Pointer Status Flag (Read Only)
|  | This field indicates the RX buffer pointer status flag.
|  | When SC receives one byte from external device, RX_POINT_F increases one.
|  | When one byte of RX buffer is read by CPU, RX_POINT_F decreases one.
[21] | RX_REERR | Receiver Retry Error (Read Only)
|  | This bit is set by hardware when RX has any error and retries transfer.
|  | Note1: This bit is read only, but it can be cleared by writing "1" to it.
|  | Note2 This bit is a flag and can not generate any interrupt to CPU.
|  | Note3: If CPU enables receiver retry function by setting SC_CTL [RX_ERETRY_EN] register, the RX_EPA_F flag will be ignored (hardware will not set RX_EPA_F).
[22] | RX_OVER_ERETRY | Receiver Over Retry Error (Read Only)
|  | This bit is set by hardware when RX transfer error retry over retry number limit.
|  | Note1: This bit is read only, but it can be cleared by writing "1" to it.
|  | Note2: If CPU enables receiver retries function by setting SC_CTL [RX_ERETRY_EN] register, the RX_EPA_F flag will be ignored (hardware will not set RX_EPA_F).
[23] | RX_ATV | Receiver In Active Status Flag (Read Only)
|  | This bit is set by hardware when RX transfer is in active.
|  | This bit is cleared automatically when RX transfer is finished.
[26:24] | TX_POINT_F | Transmit Buffer Pointer Status Flag (Read Only)
|  | This field indicates the TX buffer pointer status flag.
|  | When CPU writes data into SC_THR, TX_POINT_F increases one.
|  | When one byte of TX Buffer is transferred to transmitter shift register, TX_POINT_F decreases one.
[29] | TX_REERR | Transmitter Retry Error (Read Only)
|  | This bit is set by hardware when transmitter re-transmits.
|  | Note1: This bit is read only, but it can be cleared by writing "1" to it.
|  | Note2 This bit is a flag and can not generate any interrupt to CPU.
[30] | TX_OVER_ERETRY | Transmitter Over Retry Error (Read Only)
|  | This bit is set by hardware when transmitter re-transmits over retry number limitation.
|  | Note: This bit is read only, but it can be cleared by writing "1" to it.
[31] | TX_ATV | Transmit In Active Status Flag (Read Only)
|  | This bit is set by hardware when TX transfer is in active or the last byte transmission has not completed.
|  | This bit is cleared automatically when TX transfer is finished and the STOP bit (include guard time) has been transmitted.

Definition at line 7436 of file Nano100Series.h.

The documentation for this struct was generated from the following file:

- C:/Users/yachen/workzone/bsp/nano100absp/Library/Device/Nuvoton/Nano100Series/Include/Nano100Series.h