34 #define SPI_MODE_0 (SPI_CTL_TX_NEG_Msk) 35 #define SPI_MODE_1 (SPI_CTL_RX_NEG_Msk) 36 #define SPI_MODE_2 (SPI_CTL_CLKP_Msk | SPI_CTL_RX_NEG_Msk) 37 #define SPI_MODE_3 (SPI_CTL_CLKP_Msk | SPI_CTL_TX_NEG_Msk) 39 #define SPI_SLAVE (SPI_CTL_SLAVE_Msk) 40 #define SPI_MASTER (0x0) 43 #define SPI_SS0_ACTIVE_HIGH (SPI_SSR_SS_LVL_Msk) 44 #define SPI_SS0_ACTIVE_LOW (0x0) 47 #define SPI_SS1_ACTIVE_HIGH (SPI_SSR_SS_LVL_Msk) 48 #define SPI_SS1_ACTIVE_LOW (0x0) 50 #define SPI_IE_MASK (0x01) 51 #define SPI_SSTA_INTEN_MASK (0x04) 66 #define SPI_ABORT_3WIRE_TRANSFER(spi) ( (spi)->SSR |= SPI_SSR_SLV_ABORT_Msk ) 74 #define SPI_CLR_3WIRE_START_INT_FLAG(spi) ( (spi)->STATUS = SPI_STATUS_SLV_START_INTSTS_Msk ) 82 #define SPI_CLR_UNIT_TRANS_INT_FLAG(spi) ( (spi)->STATUS = SPI_STATUS_INTSTS_Msk ) 90 #define SPI_DISABLE_3WIRE_MODE(spi) ( (spi)->SSR &= ~SPI_SSR_NOSLVSEL_Msk ) 98 #define SPI_ENABLE_3WIRE_MODE(spi) ( (spi)->SSR |= SPI_SSR_NOSLVSEL_Msk ) 108 #define SPI_GET_RX_FIFO_EMPTY_FLAG(spi) ( ((spi)->STATUS & SPI_STATUS_RX_EMPTY_Msk) == SPI_STATUS_RX_EMPTY_Msk ? 1:0) 118 #define SPI_GET_TX_FIFO_EMPTY_FLAG(spi) ( ((spi)->STATUS & SPI_STATUS_TX_EMPTY_Msk) == SPI_STATUS_TX_EMPTY_Msk ? 1:0) 128 #define SPI_GET_TX_FIFO_FULL_FLAG(spi) ( ((spi)->STATUS & SPI_STATUS_TX_FULL_Msk) == SPI_STATUS_TX_FULL_Msk ? 1:0) 136 #define SPI_READ_RX0(spi) ( (spi)->RX0 ) 143 #define SPI_READ_RX1(spi) ( (spi)->RX1 ) 152 #define SPI_WRITE_TX0(spi, u32TxData) ( (spi)->TX0 = u32TxData ) 161 #define SPI_WRITE_TX1(spi, u32TxData) ( (spi)->TX1 = u32TxData ) 225 #define SPI_ENABLE_BYTE_REORDER(spi) ( (spi)->CTL |= SPI_CTL_REORDER_Msk ) 233 #define SPI_DISABLE_BYTE_REORDER(spi) ( (spi)->CTL &= ~SPI_CTL_REORDER_Msk ) 242 #define SPI_SET_SUSPEND_CYCLE(spi, u32SuspCycle) ( (spi)->CTL = ((spi)->CTL & ~SPI_CTL_SP_CYCLE_Msk) | (u32SuspCycle << SPI_CTL_SP_CYCLE_Pos) ) 250 #define SPI_SET_LSB_FIRST(spi) ( (spi)->CTL |= SPI_CTL_LSB_Msk ) 258 #define SPI_SET_MSB_FIRST(spi) ( (spi)->CTL &= ~SPI_CTL_LSB_Msk ) 283 #define SPI_IS_BUSY(spi) ( ((spi)->CTL & SPI_CTL_GO_BUSY_Msk) == SPI_CTL_GO_BUSY_Msk ? 1:0) 291 #define SPI_TRIGGER(spi) ( (spi)->CTL |= SPI_CTL_GO_BUSY_Msk ) 299 #define SPI_TRIGGER_RX_PDMA(spi) ( (spi)->PDMA |= SPI_PDMA_RX_DMA_EN_Msk ) 307 #define SPI_TRIGGER_TX_PDMA(spi) ( (spi)->PDMA |= SPI_PDMA_TX_DMA_EN_Msk ) 315 #define SPI_ENABLE_2BIT_MODE(spi) ( (spi)->CTL |= SPI_CTL_TWOB_Msk ) 323 #define SPI_DISABLE_2BIT_MODE(spi) ( (spi)->CTL &= ~SPI_CTL_TWOB_Msk ) 331 #define SPI_GET_STATUS(spi) ( (spi)->STATUS ) 333 uint32_t
SPI_Open(
SPI_T *spi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock);
void SPI_DisableAutoSS(SPI_T *spi)
Disable the automatic slave select function.
void SPI_EnableFIFO(SPI_T *spi)
Enable FIFO mode with user-specified Tx FIFO threshold and Rx FIFO threshold configurations.
#define SPI_CTL_TX_BIT_LEN_Pos
uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock)
Set the SPI bus clock. Only available in Master mode.
#define SPI_SSR_SS_LVL_Msk
static __INLINE void SPI_SET_SS1_HIGH(SPI_T *spi)
Disable automatic slave select function and set SPI_SS pin to high state.
void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask)
Enable FIFO related interrupts specified by u32Mask parameter.
void SPI_ClearRxFIFO(SPI_T *spi)
Clear Rx FIFO buffer.
static __INLINE void SPI_SET_SS0_HIGH(SPI_T *spi)
Disable automatic slave select function and set SPI_SS pin to high state.
static __INLINE void SPI_SET_SS0_LOW(SPI_T *spi)
Disable automatic slave select function and set SPI_SS pin to low state.
void SPI_Close(SPI_T *spi)
Reset SPI module.
static __INLINE void SPI_SET_SS1_LOW(SPI_T *spi)
Disable automatic slave select function and set SPI_SS pin to low state.
void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask)
Disable FIFO related interrupts specified by u32Mask parameter.
uint32_t SPI_GetBusClock(SPI_T *spi)
Get the actual frequency of SPI bus clock. Only available in Master mode.
void SPI_DisableFIFO(SPI_T *spi)
Disable FIFO mode.
void SPI_ClearTxFIFO(SPI_T *spi)
Clear Tx FIFO buffer.
void SPI_DisableWakeup(SPI_T *spi)
Disable wake-up function.
#define SPI_STATUS_LTRIG_FLAG_Msk
#define SPI_CTL_TX_BIT_LEN_Msk
void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel)
Enable the automatic slave select function. Only available in Master mode.
uint32_t SPI_Open(SPI_T *spi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock)
This function make SPI module be ready to transfer. By default, the SPI transfer sequence is MSB firs...
#define SPI_SSR_AUTOSS_Msk
static __INLINE void SPI_SET_DATA_WIDTH(SPI_T *spi, uint32_t u32Width)
Set the data width of a SPI transaction.
void SPI_EnableWakeup(SPI_T *spi)
Enable wake-up function.