| Nano100AN Series BSP V3.02.002 The Board Support Package for Nano100AN Series

Data Fields
CLK_T Struct Reference
NANO100 Definitions

`#include <Nano100Series.h>`

## Data Fields
__IO uint32_t | PWRCTL
__IO uint32_t | AHBCLK
__IO uint32_t | APBCLK
__I uint32_t | CLKSTATUS
__IO uint32_t | CLKSEL0
__IO uint32_t | CLKSEL1
__IO uint32_t | CLKSEL2
__IO uint32_t | CLKDIV0
__IO uint32_t | CLKDIV1
__IO uint32_t | PLLCTL
__IO uint32_t | FRQDIV
__IO uint32_t | WK_IS

## Detailed Description

    @addtogroup CLK System Clock Controller(CLK)
    Memory Mapped Structure for CLK Controller

Definition at line 608 of file Nano100Series.h.

## Field Documentation

## ◆ AHBCLK

__IO uint32_t CLK_T::AHBCLK

# AHBCLK

## Offset: 0x04 AHB Devices Clock Enable Control Register

Bits | Field | Descriptions
--- | --- | ---
[0] | GPIO_EN | GPIO Controller Clock Enable
|  | 0 = Disabled.
|  | 1 = Enabled.
[1] | DMA_EN | DMA Controller Clock Enable
|  | 0 = Disabled.
|  | 1 = Enabled.
[2] | ISP_EN | Flash ISP Controller Clock Enable
|  | 0 = Disabled.
|  | 1 = Enabled.
[3] | EBI_EN | EBI Controller Clock Enable
|  | 0 = Disabled.
|  | 1 = Enabled.
[4] | SRAM_EN | SRAM Controller Clock Enable
|  | 0 = Disabled.
|  | 1 = Enabled.
[5] | TICK_EN | System Tick Clock Enable
|  | 0 = Disabled.
|  | 1 = Enabled.

Definition at line 704 of file Nano100Series.h.

## ◆ APBCLK

__IO uint32_t CLK_T::APBCLK

# APBCLK

## Offset: 0x08 APB Devices Clock Enable Control Register

Bits | Field | Descriptions
--- | --- | ---
[0] | WDT_EN | Watch-Dog Timer Clock Enable Control
|  | This is a protected register. Please refer to open lock sequence to program it.
|  | This bit is used to control the WDT APB clock only, The WDT engine Clock Source is from LIRC.
|  | 0 = Disabled.
|  | 1 = Enabled.
[1] | RTC_EN | Real-Time-Clock Clock Enable Control
|  | This bit is used to control the RTC APB clock only, The RTC engine Clock Source is from LXT.
|  | 0 = Disabled.
|  | 1 = Enabled.
[2] | TMR0_EN | Timer0 Clock Enable Control
|  | 0 = Disabled.
|  | 1 = Enabled.
[3] | TMR1_EN | Timer1 Clock Enable Control
|  | 0 = Disabled.
|  | 1 = Enabled.
[4] | TMR2_EN | Timer2 Clock Enable Control
|  | 0 = Disabled.
|  | 1 = Enabled.
[5] | TMR3_EN | Timer3 Clock Enable Control
|  | 0 = Disabled.
|  | 1 = Enabled.
[6] | FDIV_EN | Frequency Divider Output Clock Enable Control
|  | 0 = Disabled.
|  | 1 = Enabled.
[8] | I2C0_EN | I2C0 Clock Enable Control
|  | 0 = Disabled.
|  | 1 = Enabled.
[9] | I2C1_EN | I2C1 Clock Enable Control
|  | 0 = Disabled.
|  | 1 = Enabled.
[12] | SPI0_EN | SPI0 Clock Enable Control
|  | 0 = Disabled.
|  | 1 = Enabled.
[13] | SPI1_EN | SPI1 Clock Enable Control
|  | 0 = Disabled.
|  | 1 = Enabled.
[14] | SPI2_EN | SPI2 Clock Enable Control
|  | 0 = Disabled.
|  | 1 = Enabled.
[16] | UART0_EN | UART0 Clock Enable Control
|  | 0 = Disabled.
|  | 1 = Enabled.
[17] | UART1_EN | UART1 Clock Enable Control
|  | 0 = Disabled.
|  | 1 = Enabled.
[20] | PWM0_CH01_EN | PWM0 Channel 0 And Channel 1Clock Enable Control
|  | 0 = Disabled.
|  | 1 = Enabled.
[21] | PWM0_CH23_EN | PWM0 Channel 2 And Channel 3 Clock Enable Control
|  | 0 = Disabled.
|  | 1 = Enabled.
[22] | PWM1_CH01_EN | PWM1 Channel 0 And Channel 1 Clock Enable Control
|  | 0 = Disabled.
|  | 1 = Enabled.
[23] | PWM1_CH23_EN | PWM1 Channel 2 And Channel 3 Clock Enable Control
|  | 0 = Disabled.
|  | 1 = Enabled.
[27] | USBD_EN | USB FS Device Controller Clock Enable Control
|  | 0 = Disabled.
|  | 1 = Enabled.
[28] | ADC_EN | Analog-Digital-Converter (ADC) Clock Enable Control
|  | 0 = Disabled.
|  | 1 = Enabled.
[29] | I2S_EN | I2S Clock Enable Control
|  | 0 = Disabled.
|  | 1 = Enabled.
[30] | SC0_EN | SmartCard 0 Clock Enable Control
|  | 0 = Disabled.
|  | 1 = Enabled.
[31] | SC1_EN | SmartCard 1 Clock Enable Control
|  | 0 = Disabled.
|  | 1 = Enabled.

Definition at line 786 of file Nano100Series.h.

## ◆ CLKDIV0

__IO uint32_t CLK_T::CLKDIV0

# CLKDIV0

## Offset: 0x1C Clock Divider Number Register 0

Bits | Field | Descriptions
--- | --- | ---
[3:0] | HCLK_N | HCLK Clock Divide Number From HCLK Clock Source
|  | The HCLK clock frequency = (HCLK Clock Source frequency) / (HCLK_N + 1).
[7:4] | USB_N | USB Clock Divide Number From PLL Clock
|  | The USB clock frequency = (PLL frequency ) / (USB_N + 1).
[11:8] | UART_N | UART Clock Divide Number From UART Clock Source
|  | The UART clock frequency = (UART Clock Source frequency ) / (UART_N + 1).
[15:12] | I2S_N | I2S Clock Divide Number From I2S Clock Source
|  | The I2S clock frequency = (I2S Clock Source frequency ) / (I2S_N + 1).
[23:16] | ADC_N | ADC Clock Divide Number From ADC Clock Source
|  | The ADC clock frequency = (ADC Clock Source frequency ) / (ADC_N + 1).
[31:28] | SC0_N | SC 0 Clock Divide Number From SC 0 Clock Source
|  | The SC 0 clock frequency = (SC0 Clock Source frequency ) / (SC0_N + 1).

Definition at line 957 of file Nano100Series.h.

## ◆ CLKDIV1

__IO uint32_t CLK_T::CLKDIV1

# CLKDIV1

## Offset: 0x20 Clock Divider Number Register 1

Bits | Field | Descriptions
--- | --- | ---
[3:0] | SC1_N | SC 1 Clock Divide Number From SC 1 Clock Source
|  | The SC 1 clock frequency = (SC 1 Clock Source frequency ) / (SC1_N + 1).

Definition at line 969 of file Nano100Series.h.

## ◆ CLKSEL0

__IO uint32_t CLK_T::CLKSEL0

# CLKSEL0

## Offset: 0x10 Clock Source Select Control Register 0

Bits | Field | Descriptions
--- | --- | ---
[2:0] | HCLK_S | HCLK Clock Source Selection
|  | This is a protected register. Please refer to open lock sequence to program it.
|  | Note:
|  | Before Clock Source switches, the related clock sources (pre-select and new-select) must be turn on
|  | The 3-bit default value is reloaded with the value of CFOSC (Config0[26:24]) in user configuration register in Flash controller by any reset.
|  | Therefore the default value is either 000b or 111b.
|  | 000 = HXT.
|  | 001 = LXT.
|  | 010 = PLL.
|  | 011 = LIRC.
|  | 111 = HIRC.
|  | Others = Reserved.

Definition at line 837 of file Nano100Series.h.

## ◆ CLKSEL1

__IO uint32_t CLK_T::CLKSEL1

# CLKSEL1

## Offset: 0x14 Clock Source Select Control Register 1

Bits | Field | Descriptions
--- | --- | ---
[1:0] | UART_S | UART 0/1 Clock Source Selection (UART0 And UART1 Use The Same Clock Source Selection)
|  | 00 = HXT.
|  | 01 = LXT.
|  | 10 = PLL.
|  | 11 = HIRC.
[3:2] | ADC_S | ADC Clock Source Selection
|  | 00 = HXT.
|  | 01 = LXT.
|  | 10 = PLL.
|  | 11 = HIRC.
[5:4] | PWM0_CH01_S | PWM0 Channel 0 And Channel 1 Clock Source Selection
|  | PWM0 channel 0 and channel 1 use the same Engine clock source, both of them with the same prescaler
|  | 00 = HXT.
|  | 01 = LXT.
|  | 10 = HCLK.
|  | 11 = HIRC.
[7:6] | PWM0_CH23_S | PWM0 Channel 2 And Channel 3 Clock Source Selection
|  | PWM0 channel 2 and channel 3 use the same Engine clock source, both of them with the same prescaler
|  | 00 = HXT.
|  | 01 = LXT.
|  | 10 = HCLK.
|  | 11 = HIRC.
[10:8] | TMR0_S | TIMER 0 Clock Source Selection
|  | 000 = HXT.
|  | 001 = LXT.
|  | 010 = LIRC.
|  | 011 = External pin.
|  | 111 = HIRC.
|  | Others = Reserved.
[14:12] | TMR1_S | TIMER 1 Clock Source Selection
|  | 000 = HXT.
|  | 001 = LXT.
|  | 010 = LIRC.
|  | 011 = External pin.
|  | 111 = HIRC.
|  | Others = Reserved.

Definition at line 883 of file Nano100Series.h.

## ◆ CLKSEL2

__IO uint32_t CLK_T::CLKSEL2

# CLKSEL2

## Offset: 0x18 Clock Source Select Control Register 2

Bits | Field | Descriptions
--- | --- | ---
[3:2] | FRQDIV_S | Clock Divider Clock Source Selection
|  | 00 = HXT.
|  | 01 = LXT.
|  | 10 = HCLK.
|  | 11 = HIRC.
[5:4] | PWM1_CH01_S | PWM1 Channel 0 And Channel 1 Clock Source Selection
|  | PWM1 channel 0 and channel 1 use the same Engine clock source, both of them with the same pre-scale
|  | 00 = HXT.
|  | 01 = LXT.
|  | 10 = HCLK.
|  | 11 = HIRC.
[7:6] | PWM1_CH23_S | PWM1 Channel 2 And Channel 2 Clock Source Selection
|  | PWM1 channel 2 and channel 3 use the same Engine clock source, both of them with the same pre-scale
|  | 00 = HXT.
|  | 01 = LXT.
|  | 10 = HCLK.
|  | 11 = HIRC.
[10:8] | TMR2_S | TIMER 2 Clock Source Selection
|  | 000 = HXT.
|  | 001 = LXT.
|  | 010 = LIRC.
|  | 011 = External pin.
|  | 111 = HIRC.
|  | Others = Reserved.
[14:12] | TMR3_S | TIMER 3 Clock Source Selection
|  | 000 = HXT.
|  | 001 = LXT.
|  | 010 = LIRC.
|  | 011 = External pin.
|  | 111 = HIRC.
|  | Others = Reserved.
[17:16] | I2S_S | I2S Clock Source Selection
|  | 00 = HXT.
|  | 01 = PLL.
|  | 10 = HIRC.
|  | 11 = HIRC.
[19:18] | SC_S | SC Clock Source Selection
|  | 00 = HXT.
|  | 01 = PLL.
|  | 10 = HIRC.
|  | 11 = HIRC.
|  | NOTE: SC0 and SC1 use the same Clock Source selection but they have different clock divider number.

Definition at line 935 of file Nano100Series.h.

## ◆ CLKSTATUS

__I uint32_t CLK_T::CLKSTATUS

# CLKSTATUS

## Offset: 0x0C Clock status monitor Register

Bits | Field | Descriptions
--- | --- | ---
[0] | HXT_STB | HEXT Clock Source Stable Flag
|  | 0 = HXT clock is not stable or not enable.
|  | 1 = HXT clock is stable.
[1] | LXT_STB | LEXT Clock Source Stable Flag
|  | 0 = LXT clock is not stable or not enable.
|  | 1 = LXT clock is stable.
[2] | PLL_STB | PLL Clock Source Stable Flag
|  | 0 = PLL clock is not stable or not enable.
|  | 1 = PLL clock is stable.
[3] | LIRC_STB | LIRC Clock Source Stable Flag
|  | 0 = LIRC clock is not stable or not enable.
|  | 1 = LIRC clock is stable.
[4] | HIRC_STB | HIRC Clock Source Stable Flag
|  | 0 = HIRC clock is not stable or not enable.
|  | 1 = HIRC clock is stable.
[7] | CLK_SW_FAIL | Clock Switch Fail Flag
|  | 0 = Clock switch success.
|  | 1 = Clock switch fail.
|  | This bit will be set when target switch Clock Source is not stable. This bit is write 1 clear

Definition at line 815 of file Nano100Series.h.

## ◆ FRQDIV

__IO uint32_t CLK_T::FRQDIV

# FRQDIV

## Offset: 0x28 Frequency Divider Control Register

Bits | Field | Descriptions
--- | --- | ---
[3:0] | FSEL | Divider Output Frequency Selection Bits
|  | The formula of output frequency is
|  | Fout = Fin/2(N+1),.
|  | Where Fin is the input clock frequency, Fout is the frequency of divider output clock and N is the 4-bit value of FSEL[3:0].
[4] | FDIV_EN | Frequency Divider Enable Bit
|  | 0 = Frequency Divider Disabled.
|  | 1 = Frequency Divider Enabled.

Definition at line 1010 of file Nano100Series.h.

## ◆ PLLCTL

__IO uint32_t CLK_T::PLLCTL

# PLLCTL

## Offset: 0x24 PLL Control Register

Bits | Field | Descriptions
--- | --- | ---
[4:0] | FB_DV | PLL Feedback Divider Control Pins
|  | Refer to the formulas below the table.
|  | The range of FB_DV is from 0 to 63.
[9:8] | IN_DV | PLL Input Divider Control Pins
|  | Refer to the formulas below the table.
[12] | OUT_DV | PLL Output Divider Control Pins
|  | Refer to the formulas below the table.
[16] | PD | Power-Down Mode
|  | If set the PD_EN bit "1" in PWR_CTL register, the PLL will enter Power-down mode too
|  | 0 = PLL is in normal mode.
|  | 1 = PLL is in power-down mode (default).
[17] | PLL_SRC | PLL Source Clock Select
|  | 0 = PLL source clock from HXT.
|  | 1 = PLL source clock from HIRC.

Definition at line 993 of file Nano100Series.h.

## ◆ PWRCTL

__IO uint32_t CLK_T::PWRCTL

# PWRCTL

## Offset: 0x00 System Power Down Control Register

Bits | Field | Descriptions
--- | --- | ---
[0] | HXT_EN | HXT Control
|  | This is a protected register. Please refer to open lock sequence to program it.
|  | The bit default value is set by flash controller user configuration register config0 [26].
|  | 0 = Disabled.
|  | 1 = Enabled.
|  | HXT is disabled by default.
[1] | LXT_EN | LXT Control
|  | This is a protected register. Please refer to open lock sequence to program it.
|  | 0 = Disabled.
|  | 1 = Enabled.
|  | LXT is disabled by default.
[2] | HIRC_EN | HIRC Control
|  | This is a protected register. Please refer to open lock sequence to program it.
|  | 0 = Disabled.
|  | 1 = Enabled.
|  | HIRC is enabled by default.
[3] | LIRC_EN | LIRC Control
|  | This is a protected register. Please refer to open lock sequence to program it.
|  | 0 = Disabled.
|  | 1 = Enabled.
|  | LIRC is enabled by default.
[4] | WK_DLY | Wake-Up Delay Counter Enable
|  | This is a protected register. Please refer to open lock sequence to program it.
|  | When chip wakes up from Power-down mode, the clock control will delay 4096 clock cycles to wait HXT stable or 16 clock cycles to wait HIRC stable.
|  | 0 = Delay clock cycle delay Disabled.
|  | 1 = Delay clock cycle delay Enabled.
[5] | PD_WK_IE | Power-Down Mode Wake-Up Interrupt Enable
|  | This is a protected register. Please refer to open lock sequence to program it.
|  | 0 = Disabled.
|  | 1 = Enabled.
|  | PD_WK_INT will be set if both PD_WK_IS and PD_WK_IE are high.
[6] | PD_EN | Chip Power-Down Mode Enable Bit
|  | This is a protected register. Please refer to open lock sequence to program it.
|  | When CPU sets this bit, the chip power down is enabled and chip will not enter Power-down mode until CPU sleep mode is also active
|  | When chip wakes up from Power-down mode, this bit will be auto cleared.
|  | When chip is in Power-down mode, the LDO, HXT and HIRC will be disabled, but LXT and LIRC are not controlled by Power-down mode.
|  | When power down, the PLL and system clock (CPU, HCLKx and PCLKx) are also disabled no matter the Clock Source selection.
|  | Peripheral clocks are not controlled by this bit, if peripheral Clock Source is from LXT or LIRC.
|  | In Power-down mode, flash macro power is ON.
|  | 0 = Chip operated in Normal mode.
|  | 1 = Chip power down Enabled.
|  | NOTE: It inhibits to set both PD_EN and DPD_EN high.
[8] | HXT_SELXT | HXT SELXT
|  | This is a protected register. Please refer to open lock sequence to program it.
|  | 0 = High frequency crystal loop back path Disabled. It is used for external oscillator.
|  | 1 = High frequency crystal loop back path Enabled. It is used for external crystal.
[9] | HXT_GAIN | HXT Gain Control Bit
|  | This is a protected register. Please refer to open lock sequence to program it.
|  | Gain control is used to enlarge the gain of crystal to make sure crystal wok normally.
|  | If gain control is enabled, crystal will consume more power than gain control off.
|  | 0 = Gain control Disabled. It means HXT gain is always high.
|  | 1 = Gain control Enabled. HXT gain will be high lasting 2ms then low. This is for power saving.
[10] | LXT_SCNT | LXT Stable Time Control
|  | This is a protected register. Please refer to open lock sequence to program it.
|  | 0 = Delay 4096 LXT before LXT output.
|  | 1 = Delay 8192 LXT before LXT output.

Definition at line 676 of file Nano100Series.h.

## ◆ WK_IS

__IO uint32_t CLK_T::WK_IS

# WK_IS

## Offset: 0x30 Power-down Wake-up Interrupt Status Register

Bits | Field | Descriptions
--- | --- | ---
[0] | PD_WK_IS | Wake-Up Interrupt Status In Chip Power-Down Mode
|  | This bit indicates that some event resumes chip from Power-down mode
|  | The status is set if external interrupts, UART, GPIO, RTC, USB, SPI, Timer, WDT, and BOD wake-up occurred.
|  | Write 1 to clear this bit.

Definition at line 1029 of file Nano100Series.h.

The documentation for this struct was generated from the following file:

- C:/Users/yachen/workzone/bsp/nano100absp/Library/Device/Nuvoton/Nano100Series/Include/Nano100Series.h