| Nano100AN Series BSP V3.02.002 The Board Support Package for Nano100AN Series

Data Fields
TIMER_T Struct Reference

`#include <Nano100Series.h>`

## Data Fields
__IO uint32_t | CTL
__IO uint32_t | PRECNT
__IO uint32_t | CMPR
__IO uint32_t | IER
__IO uint32_t | ISR
__I uint32_t | DR
__I uint32_t | TCAP

## Detailed Description

    @addtogroup TMR Timer Controller(TMR)
    Memory Mapped Structure for TMR Controller

Definition at line 8365 of file Nano100Series.h.

## Field Documentation

## ◆ CMPR

__IO uint32_t TIMER_T::CMPR

# CMPR

## Offset: 0x08 Timer x Compare Register

Bits | Field | Descriptions
--- | --- | ---
[23:0] | TMR_CMP | Timer Compared Value
|  | TMR_CMP is a 24-bit compared register.
|  | When the internal 24-bit up-counter counts and its value is equal to TMR_CMP value, a Timer Interrupt is requested if the timer interrupt is enabled with TMR_IER [TMR_IE] is enabled.
|  | The TMR_CMP value defines the timer counting cycle time.
|  | Time out period = (Period of timer clock input) * (8-bit PRESCALE_CNT + 1) * (24-bit TMR_CMP).
|  | NOTE1: Never write 0x0 or 0x1 in TMR_CMP, or the core will run into unknown state.
|  | NOTE2: No matter TMR_CTL [TMR_EN] is 0 or 1, whenever software write a new value into this register, TIMER will restart counting using this new value and abort previous count.

Definition at line 8525 of file Nano100Series.h.

## ◆ CTL

__IO uint32_t TIMER_T::CTL

# CTL

## Offset: 0x00 Timer x Control Register

Bits | Field | Descriptions
--- | --- | ---
[0] | TMR_EN | Timer Counter Enable Bit
|  | 0 = Stops/Suspends counting.
|  | 1 = Starts counting.
|  | Note1: Set TMR_EN to 1 enables 24-bit counter keeps up counting from the last stop counting value.
|  | Note2: This bit is auto-cleared by hardware in one-shot mode (MODE_SEL [5:4] =2'b00) once the value of 24-bit up counter equals the TMRx_CMPRn.
[1] | SW_RST | Software Reset
|  | Set this bit will reset the timer counter, pre-scale counter and also force TMR_CTL [TMR_EN] to 0.
|  | 0 = No effect.
|  | 1 = Reset Timer's pre-scale counter, internal 24-bit up-counter and TMR_CTL [TMR_EN] bit.
|  | Note: This bit will auto clear and takes at least 3 TMRx_CLK clock cycles.
[2] | WAKE_EN | Wake-Up Enable
|  | When WAKE_EN is set and the TMR_IS or TCAP_IS is set, the timer controller will generate a wake-up trigger event to CPU.
|  | 0 = Wake-up trigger event disable.
|  | 1 = Wake-up trigger event enable.
[3] | DBGACK_EN | ICE Debug Mode Acknowledge Ineffective Enable
|  | 0 = ICE debug mode acknowledgement effects TIMER counting and TIMER counter will be held while ICE debug mode acknowledged.
|  | 1 = ICE debug mode acknowledgement is ineffective and TIMER counter will keep going no matter ICE debug mode acknowledged or not.
[5:4] | MODE_SEL | Timer Operating Mode Select
|  | 00 = The timer is operating in the one-shot mode.
|  | In this mode, the associated interrupt signal is generated (if TMR_IER [TMR_IE] is enabled) once the value of 24-bit up counter equals the TMRx_CMPRn.
|  | And TMR_CTL [TMR_EN] is automatically cleared by hardware.
|  | 01 = The timer is operating in the periodic mode.
|  | In this mode, the associated interrupt signal is generated periodically (if TMR_IER [TMR_IE] is enabled) while the value of 24-bit up counter equals the TMRx_CMPRn.
|  | After that, the 24-bit counter will be reset and starts counting from zero again.
|  | 10 = The timer is operating in the periodic mode with output toggling.
|  | In this mode, the associated interrupt signal is generated periodically (if TMR_IER [TMR_IE] is enabled) while the value of 24-bit up counter equals the TMRx_CMPRn.
|  | After that, the 24-bit counter will be reset and starts counting from zero again.
|  | At the same time, timer controller will also toggle the output pin TMRxn_TOG_OUT to its inverse level (from low to high or from high to low).
|  | Note: The default level of TMRxn_TOG_OUT after reset is low.
|  | 11 = Reserved.
[7] | TMR_ACT | Timer Active Status Bit (Read Only)
|  | This bit indicates the timer counter status of timer.
|  | 0 = Timer is not active.
|  | 1 = Timer is in active.
[8] | ADC_TEEN | TMR_IS Or TCAP_IS Trigger ADC Enable
|  | This bit controls if TMR_IS or TCAP_IS could trigger ADC.
|  | When ADC_TEEN is set, TMR_IS is set and the CAP_TRG_EN is low, the timer controller will generate an internal trigger event to ADC controller.
|  | When ADC_TEEN is set, TCAP_IS is set and the CAP_TRG_EN is high, the timer controller will generate an internal trigger event to ADC controller.
|  | 0 = TMR_IS or TCAP_IS trigger ADC disable.
|  | 1 = TMR_IS or TCAP_IS trigger ADC enable.
[10] | PDMA_TEEN | TMR_IS Or TCAP_IS Trigger PDMA Enable
|  | This bit controls if TMR_IS or TCAP_IS could trigger PDMA.
|  | When PDMA_TEEN is set, TMR_IS is set and the CAP_TRG_EN is low, the timer controller will generate an internal trigger event to PDMA controller.
|  | When PDMA_TEEN is set, TCAP_IS is set and the CAP_TRG_EN is high, the timer controller will generate an internal trigger event to PDMA controller.
|  | 0 = TMR_IS or TCAP_IS trigger PDMA disable.
|  | 1 = TMR_IS or TCAP_IS trigger PDMA enable.
[11] | CAP_TRG_EN | TCAP_IS Trigger Mode Enable
|  | This bit controls if the TMR_IS or TCAP_IS is used to trigger PDMA and ADC while TMR_IS or TCAP_IS is set.
|  | If this bit is low and TMR_IS is set, timer will generate an internal trigger event to PDMA or ADC while related trigger enable bit (PDMA_TEEN or ADC_TEEN) is also set.
|  | If this bit is set high and TCAP_IS is set, timer will generate an internal trigger event to PDMA or ADC while related trigger enable bit (PDMA_TEEN or ADC_TEEN) is also set.
|  | 0 = TMR_IS is used to trigger PDMA and ADC.
|  | 1 = TCAP_IS is used to trigger PDMA and ADC.
[12] | EVENT_EN | Event Counting Mode Enable
|  | When EVENT_EN is set, the increase of 24-bit up-counting timer is controlled by external event pin.
|  | While the transition of external event pin matches the definition of EVENT_EDGE, the 24-bit up-counting timer increases by 1.
|  | Or, the 24-bit up-counting timer will keep its value unchanged.
|  | 0 = Timer counting is not controlled by external event pin.
|  | 1 = Timer counting is controlled by external event pin.
[13] | EVENT_EDGE | Event Counting Mode Edge Selection
|  | This bit indicates which edge of external event pin enabling the timer to increase 1.
|  | 0 = A falling edge of external event enabling the timer to increase 1.
|  | 1 = A rising edge of external event enabling the timer to increase 1.
[14] | EVNT_DEB_EN | External Event De-Bounce Enable
|  | When EVNT_DEB_EN is set, the external event pin de-bounce circuit will be enabled to eliminate the bouncing of the signal.
|  | In de-bounce circuit the external event pin will be sampled 4 times by TMRx_CLK.
|  | 0 = De-bounce circuit Disabled.
|  | 1 = De-bounce circuit Enabled.
|  | Note: When EVENT_EN is enabled, enable this bit is recommended.
|  | And, while EVENT_EN is disabled, disable this bit is recommended to save power consumption.
[16] | TCAP_EN | TCapture Pin Functional Enable
|  | This bit controls if the transition on TCapture pin could be used as timer counter reset function or timer capture function.
|  | 0 = The transition on TCapture pin is ignored.
|  | 1 = The transition on TCapture pin will result in the capture or reset of 24-bit timer counter.
|  | Note: For TMRx_CTL0, if INTR_TRG_EN is set, the TCAP_EN will be forced to low and the TCapture pin transition is ignored.
|  | Note: For TMRx_CTL1, if INTR_TRG_EN is set, the TCAP_EN will be forced to high.
[17] | TCAP_MODE | TCapture Pin Function Mode Selection
|  | This bit indicates if the transition on TCapture pin is used as timer counter reset function or timer capture function.
|  | 0 = Transition on TCapture pin is used as timer capture function.
|  | 1 = Transition on TCapture pin is used as timer counter reset function.
|  | Note: For TMRx_CTL1, if INTR_TRG_EN is set, the TCAP_MODE will be forced to low.
[19:18] | TCAP_EDGE | TCapture Pin Edge Detect Selection
|  | This field defines that active transition of TCapture pin is for timer counter reset function or for timer capture function.
|  | For timer counter reset function and free-counting mode of timer capture function, the configurations are:
|  | 00 = A falling edge (1 to 0 transition) on TCapture pin is an active transition.
|  | 01 = A rising edge (0 to 1 transition) on TCapture pin is an active transition.
|  | 10 = Both falling edge (1 to 0 transition) and rising edge (0 to 1 transition) on TCapture pin are active transitions.
|  | 11 = Both falling edge (1 to 0 transition) and rising edge (0 to 1 transition) on TCapture pin are active transitions.
|  | For trigger-counting mode of timer capture function, the configurations are:
|  | 00 = 1st falling edge on TCapture pin triggers 24-bit timer to start counting, while 2nd falling edge triggers 24-bit timer to stop counting.
|  | 01 = 1st rising edge on TCapture pin triggers 24-bit timer to start counting, while 2nd rising edge triggers 24-bit timer to stop counting.
|  | 10 = Falling edge on TCapture pin triggers 24-bit timer to start counting, while rising edge triggers 24-bit timer to stop counting.
|  | 11 = Rising edge on TCapture pin triggers 24-bit timer to start counting, while falling edge triggers 24-bit timer to stop counting.
|  | Note: For TMRx_CTL1, if INTR_TRG_EN is set, the TCAP_EDGE will be forced to 11.
[20] | TCAP_CNT_MOD | Timer Capture Counting Mode Selection
|  | This bit indicates the behavior of 24-bit up-counting timer while TCAP_EN is set to high.
|  | If this bit is 0, the free-counting mode, the behavior of 24-bit up-counting timer is defined by MODE_SEL field.
|  | When TCAP_EN is set, TCAP_MODE is 0, and the transition of TCapture pin matches the TCAP_EDGE setting, the value of 24-bit up-counting timer will be saved into register TMRx_TCAPn.
|  | If this bit is 1, the trigger-counting mode, 24-bit up-counting timer will be not counting and keep its value at zero.
|  | When TCAP_EN is set, TCAP_MODE is 0, and once the transition of external pin matches the 1st transition of TCAP_EDGE setting, the 24-bit up-counting timer will start counting.
|  | And then if the transition of external pin matches the 2nd transition of TCAP_EDGE setting, the 24-bit up-counting timer will stop counting.
|  | And its value will be saved into register TMRx_TCAPn.
|  | 0 = Capture with free-counting timer mode.
|  | 1 = Capture with trigger-counting timer mode.
|  | Note: For TMRx_CTL1, if INTR_TRG_EN is set, the CAP_CNT_MOD will be forced to high, the capture with trigger-counting timer mode.
[22] | TCAP_DEB_EN | TCapture Pin De-Bounce Enable
|  | When CAP_DEB_EN is set, the TCapture pin de-bounce circuit will be enabled to eliminate the bouncing of the signal.
|  | In de-bounce circuit the TCapture pin signal will be sampled 4 times by TMRx_CLK.
|  | 0 = De-bounce circuit Disabled.
|  | 1 = De-bounce circuit Enabled.
|  | Note: When TCAP_EN is enabled, enable this bit is recommended.
|  | And, while TCAP_EN is disabled, disable this bit is recommended to save power consumption.
[24] | INTR_TRG_EN | Inter-Timer Trigger Mode Enable
|  | This bit controls if the inter-timer trigger mode is enabled.
|  | If inter-timer trigger mode is enabled, the TIMERx_CH0 will be in counter mode and counting with external Clock Source or event.
|  | And, TIMERx_CH1 will be in trigger-counting mode of capture function.
|  | 0 = Inter-timer trigger mode is disabled.
|  | 1 = Inter-timer trigger mode is enabled.
|  | Note: For TMRx_CTL1, this bit is ignored and the read back value is always 1'b0.

Definition at line 8495 of file Nano100Series.h.

## ◆ DR

__I uint32_t TIMER_T::DR

# DR

## Offset: 0x14 Timer x Data Register

Bits | Field | Descriptions
--- | --- | ---
[23:0] | TDR | Timer Data Register
|  | User can read this register for internal 24-bit timer up-counter value.

Definition at line 8586 of file Nano100Series.h.

## ◆ IER

__IO uint32_t TIMER_T::IER

# IER

## Offset: 0x0C Timer x Interrupt Enable Register

Bits | Field | Descriptions
--- | --- | ---
[0] | TMR_IE | Timer Interrupt Enable
|  | 0 = Timer Interrupt Disabled.
|  | 1 = Timer Interrupt Enabled.
|  | NOTE: If timer interrupt is enabled, the timer asserts its interrupt signal when the associated counter is equal to TMR_CMPR.
[1] | TCAP_IE | Timer Capture Function Interrupt Enable
|  | 0 = Timer External Pin Function Interrupt Disabled.
|  | 1 = Timer External Pin Function Interrupt Enabled.
|  | NOTE: If timer external pin function interrupt is enabled, the timer asserts its interrupt signal when the TCAP_EN is set and the transition of external pin matches the TCAP_EDGE setting

Definition at line 8543 of file Nano100Series.h.

## ◆ ISR

__IO uint32_t TIMER_T::ISR

# ISR

## Offset: 0x10 Timer x Interrupt Status Register

Bits | Field | Descriptions
--- | --- | ---
[0] | TMR_IS | Timer Interrupt Status
|  | This bit indicates the interrupt status of Timer.
|  | This bit is set by hardware when the up counting value of internal 24-bit counter matches the timer compared value (TMR_CMPR).
|  | Write 1 to clear this bit to zero.
|  | If this bit is active and TMR_IE is enabled, Timer will trigger an interrupt to CPU.
[1] | TCAP_IS | Timer Capture Function Interrupt Status
|  | This bit indicates the external pin function interrupt status of Timer.
|  | This bit is set by hardware when TCAP_EN is set high, and the transition of external pin matches the TCAP_EDGE setting.
|  | Write 1 to clear this bit to zero.
|  | If this bit is active and TCAP_IE is enabled, Timer will trigger an interrupt to CPU.
[4] | TMR_Wake_STS | Timer Wake-Up Status
|  | If timer causes CPU wakes up from power-down mode, this bit will be set to high.
|  | It must be cleared by software with a write 1 to this bit.
|  | 0: Timer does not cause system wake-up.
|  | 1: Wakes system up from power-down mode by Timer timeout.
[5] | NCAP_DET_STS | New Capture Detected Status
|  | This status is to indicate there is a new incoming capture event detected before CPU clearing the TCAP_IS status.
|  | If the above condition occurred, the Timer will keep register TMRx_CAPn unchanged and drop the new capture value.
|  | This bit is also cleared to 0 while TCAP_IS is cleared.
|  | 0: New incoming capture event didn't detect before CPU clearing TCAP_IS status.
|  | 1: New incoming capture event detected before CPU clearing TCAP_IS status.

Definition at line 8574 of file Nano100Series.h.

## ◆ PRECNT

__IO uint32_t TIMER_T::PRECNT

# PRECNT

## Offset: 0x04 Timer x Pre-Scale Counter Register

Bits | Field | Descriptions
--- | --- | ---
[7:0] | PRESCALE_CNT | Pre-Scale Counter
|  | Clock input is divided by PRESCALE_CNT + 1 before it is fed to the counter.
|  | If PRESCALE_CNT =0, then there is no scaling.

Definition at line 8508 of file Nano100Series.h.

## ◆ TCAP

__I uint32_t TIMER_T::TCAP

# TCAP

## Offset: 0x18 Timer x Capture Data Register

Bits | Field | Descriptions
--- | --- | ---
[23:0] | CAP | Timer Capture Data Register
|  | When TCAP_EN is set, TCAP_MODE is 0, and the transition of external pin matches the TCAP_EDGE setting, the value of 24-bit up-counting timer will be saved into register TMRx_TCAPn.
|  | User can read this register for the counter value.

Definition at line 8599 of file Nano100Series.h.

The documentation for this struct was generated from the following file:

- C:/Users/yachen/workzone/bsp/nano100absp/Library/Device/Nuvoton/Nano100Series/Include/Nano100Series.h