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Nano100AN Series BSP
V3.02.002
The Board Support Package for Nano100AN Series
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#include <Nano100Series.h>
Data Fields | |
| __IO uint32_t | DBNCECON |
Definition at line 4315 of file Nano100Series.h.
| __IO uint32_t GP_DB_T::DBNCECON |
| Bits | Field | Descriptions |
|---|---|---|
| [3:0] | PUEN | De-Bounce Sampling Cycle Selection |
| 0000 = Sample interrupt input once per 1 clock. | ||
| 0001 = Sample interrupt input once per 2 clock. | ||
| 0010 = Sample interrupt input once per 4 clock. | ||
| 0011 = Sample interrupt input once per 8 clock. | ||
| 0100 = Sample interrupt input once per 16 clock. | ||
| 0101 = Sample interrupt input once per 32 clock. | ||
| 0110 = Sample interrupt input once per 64 clock. | ||
| 0111 = Sample interrupt input once per 128 clock. | ||
| 1000 = Sample interrupt input once per 256 clock. | ||
| 1001 = Sample interrupt input once per 512 clock. | ||
| 1010 = Sample interrupt input once per 1024 clock. | ||
| 1011 = Sample interrupt input once per 2048 clock. | ||
| 1100 = Sample interrupt input once per 4096 clock. | ||
| 1101 = Sample interrupt input once per 8192 clock. | ||
| 1110 = Sample interrupt input once per 16384 clock. | ||
| 1111 = Sample interrupt input once per 32768 clock. | ||
| [4] | DBCLKSRC | De-Bounce Counter Clock Source Selection |
| 0 = De-bounce counter Clock Source is the HCLK. | ||
| 1 = De-bounce counter Clock Source is the internal 10 kHz clock. | ||
| [5] | DBCLK_ON | De-Bounce Clock Enable |
| This bit controls if the de-bounce clock is enabled. | ||
| However, if GPI/O pin's interrupt is enabled, the de-bounce clock will be enabled automatically no matter what the DBCLK_ON value is. | ||
| If CPU is in sleep mode, this bit didn't take effect. | ||
| And only the GPI/O pin with interrupt enable could get de-bounce clock. | ||
| 0 = De-bounce clock Disabled. | ||
| 1 = De-bounce clock Enabled. |
Definition at line 4352 of file Nano100Series.h.
1.8.15