#include <Nano100Series.h>
Definition at line 1616 of file Nano100Series.h.
◆ BCR
| __IO uint32_t VDMA_T::BCR |
BCR
Offset: 0x0C VDMA Transfer Byte Count Register
| Bits | Field | Descriptions |
| [15:0] | VDMA_BCR | VDMA Transfer Byte Count Register |
| | This field indicates a 16-bit transfer byte count of VDMA. |
| | Note: In Stride Enable mode (VDMA_CSR [10] = "0"), the transfer byte count (VDMA_BCR) must be an integer multiple of STBC (VDMA_SASOCR [31:16]). |
Definition at line 1686 of file Nano100Series.h.
◆ BUF0
| __I uint32_t VDMA_T::BUF0 |
BUF0
Offset: 0x80 VDMA Internal Buffer FIFO 0
| Bits | Field | Descriptions |
| [31:0] | VDMA_BUF0 | VDMA Internal Buffer FIFO 0 (Read Only) |
| | VDMA channel has its own 2 words internal buffer. |
Definition at line 1813 of file Nano100Series.h.
◆ BUF1
| __I uint32_t VDMA_T::BUF1 |
BUF1
Offset: 0x84 VDMA Internal Buffer FIFO 1
| Bits | Field | Descriptions |
| [31:0] | VDMA_BUF1 | VDMA Internal Buffer FIFO 1 (Read Only) |
| | VDMA channel has its own 2 words internal buffer. |
Definition at line 1825 of file Nano100Series.h.
◆ CBCR
| __I uint32_t VDMA_T::CBCR |
CBCR
Offset: 0x1C VDMA Current Transfer Byte Count Register
| Bits | Field | Descriptions |
| [15:0] | VDMA_CBCR | VDMA Current Byte Count Register (Read Only) |
| | This field indicates the current remained byte count of VDMA. |
Definition at line 1727 of file Nano100Series.h.
◆ CDAR
| __I uint32_t VDMA_T::CDAR |
CDAR
Offset: 0x18 VDMA Current Destination Address Register
| Bits | Field | Descriptions |
| [31:0] | VDMA_CDAR | VDMA Current Destination Address Register (Read Only) |
| | This field indicates the destination address where the VDMA transfer is just occurring. |
Definition at line 1715 of file Nano100Series.h.
◆ CSAR
| __I uint32_t VDMA_T::CSAR |
CSAR
Offset: 0x14 VDMA Current Source Address Register
| Bits | Field | Descriptions |
| [31:0] | VDMA_CSAR | VDMA Current Source Address Register (Read Only) |
| | This field indicates the source address where the VDMA transfer is just occurring. |
Definition at line 1703 of file Nano100Series.h.
◆ CSR
| __IO uint32_t VDMA_T::CSR |
CSR
Offset: 0x00 VDMA Control Register
| Bits | Field | Descriptions |
| [0] | VDMACEN | VDMA Channel Enable |
| | Setting this bit to "1" enables VDMA's operation. |
| | If this bit is cleared, VDMA will ignore all VDMA request and force Bus Master into IDLE state. |
| | Note: SW_RST will clear this bit. |
| [1] | SW_RST | Software Engine Reset |
| | 0 = No effect. |
| | 1 = Reset the internal state machine and pointers. |
| | The contents of control register will not be cleared. |
| | This bit will auto clear after few clock cycles. |
| [10] | STRIDE_EN | Stride Mode Enable |
| | 0 = Stride transfer mode Disabled. |
| | 1 = Stride transfer mode Enabled. |
| [11] | DIR_SEL | Transfer Source/Destination Address Direction Select |
| | 0 = Transfer address is incremented successively. |
| | 1 = Transfer address is decremented successively. |
| [23] | TRIG_EN | TRIG_EN |
| | 0 = No effect. |
| | 1 = VDMA data read or write transfer Enabled. |
| | Note1: When VDMA transfer is completed, this bit will be cleared automatically. |
| | Note2: If the bus error occurs, all VDMA transfer will be stopped. |
| | Software must reset all VDMA channel, and then trig again. |
Definition at line 1649 of file Nano100Series.h.
◆ DAR
| __IO uint32_t VDMA_T::DAR |
DAR
Offset: 0x08 VDMA Destination Address Register
| Bits | Field | Descriptions |
| [31:0] | VDMA_DAR | VDMA Transfer Destination Address Register |
| | This field indicates a 32-bit destination address of VDMA. |
Definition at line 1673 of file Nano100Series.h.
◆ DASOCR
| __IO uint32_t VDMA_T::DASOCR |
DASOCR
Offset: 0x30 VDMA Destination Address Stride Offset Register
| Bits | Field | Descriptions |
| [15:0] | DASTOBL | VDMA Destination Address Stride Offset Byte Length |
| | The 16-bit register defines the destination address stride transfer offset count of each row. |
Definition at line 1796 of file Nano100Series.h.
◆ IER
| __IO uint32_t VDMA_T::IER |
IER
Offset: 0x20 VDMA Interrupt Enable Register
| Bits | Field | Descriptions |
| [0] | TABORT_IE | VDMA Read/Write Target Abort Interrupt Enable |
| | 0 = Disabled target abort interrupt generation during VDMA transfer. |
| | 1 = Enabled target abort interrupt generation during VDMA transfer. |
| [1] | TD_IE | VDMA Transfer Done Interrupt Enable |
| | 0 = Disabled interrupt generator during VDMA transfer done. |
| | 1 = Enabled interrupt generator during VDMA transfer done. |
Definition at line 1743 of file Nano100Series.h.
◆ ISR
| __IO uint32_t VDMA_T::ISR |
ISR
Offset: 0x24 VDMA Interrupt Status Register
| Bits | Field | Descriptions |
| [0] | TABORT_IS | VDMA Read/Write Target Abort Interrupt Status Flag |
| | 0 = No bus ERROR response received. |
| | 1 = Bus ERROR response received. |
| | NOTE1: This bit is cleared by writing "1" to itself. |
| | NOTE2: The VDMA_ISR [TABORT_IF] indicate bus master received ERROR response or not, if bus master received occur it means that target abort is happened. |
| | VDMA controller will stop transfer and respond this event to software then go to IDLE state. |
| | When target abort occurred, software must reset VDMA controller, and then transfer those data again. |
| [1] | TD_IS | Transfer Done Interrupt Status Flag |
| | This bit indicates that VDMA has finished all transfer. |
| | 0 = Not finished yet. |
| | 1 = Done. |
| | Note: This bit is cleared by writing "1" to itself. |
Definition at line 1765 of file Nano100Series.h.
◆ SAR
| __IO uint32_t VDMA_T::SAR |
SAR
Offset: 0x04 VDMA Source Address Register
| Bits | Field | Descriptions |
| [31:0] | VDMA_SAR | VDMA Transfer Source Address Register |
| | This field indicates a 32-bit source address of VDMA. |
Definition at line 1661 of file Nano100Series.h.
◆ SASOCR
| __IO uint32_t VDMA_T::SASOCR |
SASOCR
Offset: 0x2C VDMA Source Address Stride Offset Register
| Bits | Field | Descriptions |
| [15:0] | SASTOBL | VDMA Source Address Stride Offset Byte Length |
| | The 16-bit register defines the source address stride transfer offset count of each row. |
| [31:16] | STBC | VDMA Stride Transfer Byte Count |
| | The 16-bit register defines the stride transfer byte count of each row. |
Definition at line 1784 of file Nano100Series.h.
The documentation for this struct was generated from the following file:
- C:/Users/yachen/workzone/bsp/nano100absp/Library/Device/Nuvoton/Nano100Series/Include/Nano100Series.h