| Nano100AN Series BSP V3.02.002 The Board Support Package for Nano100AN Series

pdma.c
Go to the documentation of this file.
1 /**************************************************************************/
12 #include "Nano100Series.h"
13
14
15
38 void PDMA_Open(uint32_t u32Mask)
39 {
40 PDMAGCR->GCRCSR |= (u32Mask << 8);
41 }
42
52 void PDMA_Close(void)
53 {
54 PDMAGCR->GCRCSR = 0;
55 }
56
68 void PDMA_SetTransferCnt(uint32_t u32Ch, uint32_t u32Width, uint32_t u32TransCount)
69 {
70 PDMA_T *pdma;
71 pdma = (PDMA_T *)((uint32_t) PDMA1_BASE + (0x100 * (u32Ch-1)));
72 pdma->CSR = (pdma->CSR & ~PDMA_CSR_APB_TWS_Msk) | u32Width;
73 switch (u32Width)
74 {
75 case PDMA_WIDTH_32:
76 pdma->BCR = (u32TransCount << 2);
77 break;
78
79 case PDMA_WIDTH_8:
80 pdma->BCR = u32TransCount;
81 break;
82
83 case PDMA_WIDTH_16:
84 pdma->BCR = (u32TransCount << 1);
85 break;
86
87 default:
88 ;
89 }
90 }
91
105 void PDMA_SetTransferAddr(uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl)
106 {
107 PDMA_T *pdma;
108 pdma = (PDMA_T *)((uint32_t) PDMA1_BASE + (0x100 * (u32Ch-1)));
109
110 pdma->SAR = u32SrcAddr;
111 pdma->DAR = u32DstAddr;
112 pdma->CSR = (pdma->CSR & ~(PDMA_CSR_SAD_SEL_Msk|PDMA_CSR_DAD_SEL_Msk)) | (u32SrcCtrl | u32DstCtrl);
113 }
114
127 void PDMA_SetTransferMode(uint32_t u32Ch, uint32_t u32Peripheral, uint32_t u32ScatterEn, uint32_t u32DescAddr)
128 {
129 PDMA_T *pdma;
130 pdma = (PDMA_T *)((uint32_t) PDMA1_BASE + (0x100 * (u32Ch-1)));
131
132 switch (u32Ch)
133 {
134 case 1:
135 PDMAGCR->DSSR0 = (PDMAGCR->DSSR0 & ~DMA_GCR_DSSR0_CH1_SEL_Msk) | (u32Peripheral << DMA_GCR_DSSR0_CH1_SEL_Pos);
136 break;
137 case 2:
138 PDMAGCR->DSSR0 = (PDMAGCR->DSSR0 & ~DMA_GCR_DSSR0_CH2_SEL_Msk) | (u32Peripheral << DMA_GCR_DSSR0_CH2_SEL_Pos);
139 break;
140 case 3:
141 PDMAGCR->DSSR0 = (PDMAGCR->DSSR0 & ~DMA_GCR_DSSR0_CH3_SEL_Msk) | (u32Peripheral << DMA_GCR_DSSR0_CH3_SEL_Pos);
142 break;
143 case 4:
144 PDMAGCR->DSSR1 = (PDMAGCR->DSSR1 & ~DMA_GCR_DSSR1_CH4_SEL_Msk) | u32Peripheral;
145 break;
146 default:
147 ;
148 }
149 if (u32Peripheral == PDMA_MEM)
150 pdma->CSR &= ~PDMA_CSR_MODE_SEL_Msk;
151 else if (u32Peripheral & 0x10)
152 pdma->CSR = (pdma->CSR & ~PDMA_CSR_MODE_SEL_Msk) | 0x4; /* IP to memory */
153 else
154 pdma->CSR = (pdma->CSR & ~PDMA_CSR_MODE_SEL_Msk) | 0x8; /* memory to IP */
155 }
156
168 void PDMA_SetTimeOut(uint32_t u32Ch, uint32_t u32OnOff, uint32_t u32TimeOutCnt)
169 {
170 PDMA_T *pdma;
171 pdma = (PDMA_T *)((uint32_t) PDMA1_BASE + (0x100 * (u32Ch-1)));
172
173 pdma->TCR = (pdma->TCR & ~PDMA_TCR_PDMA_TCR_Msk) | u32TimeOutCnt;
174 pdma->CSR = (pdma->CSR & ~PDMA_CSR_TO_EN_Msk) | (u32OnOff << PDMA_CSR_TO_EN_Pos);
175
176 }
177
187 void PDMA_Trigger(uint32_t u32Ch)
188 {
189 PDMA_T *pdma;
190 pdma = (PDMA_T *)((uint32_t) PDMA1_BASE + (0x100 * (u32Ch-1)));
191
192 pdma->CSR |= (PDMA_CSR_TRIG_EN_Msk | PDMA_CSR_PDMACEN_Msk);
193 }
194
205 void PDMA_EnableInt(uint32_t u32Ch, uint32_t u32Mask)
206 {
207 PDMA_T *pdma;
208 pdma = (PDMA_T *)((uint32_t) PDMA1_BASE + (0x100 * (u32Ch-1)));
209
210 pdma->IER |= u32Mask;
211 }
212
223 void PDMA_DisableInt(uint32_t u32Ch, uint32_t u32Mask)
224 {
225 PDMA_T *pdma;
226 pdma = (PDMA_T *)((uint32_t) PDMA1_BASE + (0x100 * (u32Ch-1)));
227
228 pdma->IER &= ~u32Mask;
229 }
230
231 /* end of group NANO100_PDMA_EXPORTED_FUNCTIONS */
233 /* end of group NANO100_PDMA_Driver */
235 /* end of group NANO100_Device_Driver */
237
238 /*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
PDMA_T::DAR
__IO uint32_t DAR
Definition: Nano100Series.h:1470
PDMA_Trigger
void PDMA_Trigger(uint32_t u32Ch)
Trigger PDMA.
Definition: pdma.c:187
PDMA_TCR_PDMA_TCR_Msk
#define PDMA_TCR_PDMA_TCR_Msk
Definition: Nano100Series.h:1951
PDMA_CSR_DAD_SEL_Msk
#define PDMA_CSR_DAD_SEL_Msk
Definition: Nano100Series.h:1897
PDMA_CSR_PDMACEN_Msk
#define PDMA_CSR_PDMACEN_Msk
Definition: Nano100Series.h:1885
PDMA_T::CSR
__IO uint32_t CSR
Definition: Nano100Series.h:1444
DMA_GCR_DSSR0_CH2_SEL_Msk
#define DMA_GCR_DSSR0_CH2_SEL_Msk
Definition: Nano100Series.h:1854
PDMA_DisableInt
void PDMA_DisableInt(uint32_t u32Ch, uint32_t u32Mask)
Disable Interrupt.
Definition: pdma.c:223
PDMA_EnableInt
void PDMA_EnableInt(uint32_t u32Ch, uint32_t u32Mask)
Enable Interrupt.
Definition: pdma.c:205
DMA_GCR_DSSR1_CH4_SEL_Msk
#define DMA_GCR_DSSR1_CH4_SEL_Msk
Definition: Nano100Series.h:1860
PDMA_SetTransferAddr
void PDMA_SetTransferAddr(uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl)
Set PDMA Transfer Address.
Definition: pdma.c:105
Nano100Series.h
Nano100 series peripheral access layer header file. This file contains all the peripheral register's ...
PDMA_T
Definition: Nano100Series.h:1388
PDMA_SetTransferMode
void PDMA_SetTransferMode(uint32_t u32Ch, uint32_t u32Periphral, uint32_t u32ScatterEn, uint32_t u32DescAddr)
Set PDMA Transfer Mode.
Definition: pdma.c:127
PDMA_CSR_TO_EN_Pos
#define PDMA_CSR_TO_EN_Pos
Definition: Nano100Series.h:1899
PDMA_CSR_APB_TWS_Msk
#define PDMA_CSR_APB_TWS_Msk
Definition: Nano100Series.h:1903
PDMA_T::IER
__IO uint32_t IER
Definition: Nano100Series.h:1548
PDMA_WIDTH_16
#define PDMA_WIDTH_16
Definition: pdma.h:37
PDMA_Open
void PDMA_Open(uint32_t u32Mask)
PDMA Open.
Definition: pdma.c:38
PDMA_SetTimeOut
void PDMA_SetTimeOut(uint32_t u32Ch, uint32_t u32OnOff, uint32_t u32TimeOutCnt)
Set PDMA Timeout.
Definition: pdma.c:168
PDMA_CSR_TRIG_EN_Msk
#define PDMA_CSR_TRIG_EN_Msk
Definition: Nano100Series.h:1906
DMA_GCR_DSSR0_CH1_SEL_Pos
#define DMA_GCR_DSSR0_CH1_SEL_Pos
Definition: Nano100Series.h:1850
PDMA_MEM
#define PDMA_MEM
Definition: pdma.h:79
PDMA_CSR_TO_EN_Msk
#define PDMA_CSR_TO_EN_Msk
Definition: Nano100Series.h:1900
DMA_GCR_DSSR0_CH3_SEL_Pos
#define DMA_GCR_DSSR0_CH3_SEL_Pos
Definition: Nano100Series.h:1856
PDMA_T::BCR
__IO uint32_t BCR
Definition: Nano100Series.h:1483
PDMA_T::TCR
__IO uint32_t TCR
Definition: Nano100Series.h:1594
PDMA_SetTransferCnt
void PDMA_SetTransferCnt(uint32_t u32Ch, uint32_t u32Width, uint32_t u32TransCount)
Set PDMA Transfer Count.
Definition: pdma.c:68
DMA_GCR_DSSR0_CH2_SEL_Pos
#define DMA_GCR_DSSR0_CH2_SEL_Pos
Definition: Nano100Series.h:1853
PDMA_WIDTH_32
#define PDMA_WIDTH_32
Definition: pdma.h:38
PDMA_Close
void PDMA_Close(void)
PDMA Close.
Definition: pdma.c:52
DMA_GCR_DSSR0_CH3_SEL_Msk
#define DMA_GCR_DSSR0_CH3_SEL_Msk
Definition: Nano100Series.h:1857
PDMA_CSR_SAD_SEL_Msk
#define PDMA_CSR_SAD_SEL_Msk
Definition: Nano100Series.h:1894
PDMA_T::SAR
__IO uint32_t SAR
Definition: Nano100Series.h:1457
PDMA_CSR_MODE_SEL_Msk
#define PDMA_CSR_MODE_SEL_Msk
Definition: Nano100Series.h:1891
PDMAGCR
#define PDMAGCR
Pointer to PDMA global control register structure.
Definition: Nano100Series.h:10134
DMA_GCR_DSSR0_CH1_SEL_Msk
#define DMA_GCR_DSSR0_CH1_SEL_Msk
Definition: Nano100Series.h:1851
PDMA1_BASE
#define PDMA1_BASE
PDMA1 register base address.
Definition: Nano100Series.h:10084
PDMA_WIDTH_8
#define PDMA_WIDTH_8
Definition: pdma.h:36