Nano100AN Series BSP  V3.02.002
The Board Support Package for Nano100AN Series
spi.c
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1 /****************************************************************************/
13 #include "Nano100Series.h"
14 
41 uint32_t SPI_Open(SPI_T *spi,
42  uint32_t u32MasterSlave,
43  uint32_t u32SPIMode,
44  uint32_t u32DataWidth,
45  uint32_t u32BusClock)
46 {
47  if(u32DataWidth == 32)
48  u32DataWidth = 0;
49 
50  spi->CTL = u32MasterSlave | (u32DataWidth << SPI_CTL_TX_BIT_LEN_Pos) | (u32SPIMode);
51 
52  return ( SPI_SetBusClock(spi, u32BusClock) );
53 }
54 
60 void SPI_Close(SPI_T *spi)
61 {
62  /* Reset SPI */
63  if(spi == SPI0)
64  {
65  SYS->IPRST_CTL2 |= SYS_IPRST_CTL2_SPI0_RST_Msk;
66  SYS->IPRST_CTL2 &= ~SYS_IPRST_CTL2_SPI0_RST_Msk;
67  }
68  else if(spi == SPI1)
69  {
70  SYS->IPRST_CTL2 |= SYS_IPRST_CTL2_SPI1_RST_Msk;
71  SYS->IPRST_CTL2 &= ~SYS_IPRST_CTL2_SPI1_RST_Msk;
72  }
73  else
74  {
75  SYS->IPRST_CTL2 |= SYS_IPRST_CTL2_SPI2_RST_Msk;
76  SYS->IPRST_CTL2 &= ~SYS_IPRST_CTL2_SPI2_RST_Msk;
77  }
78 }
79 
86 {
88 }
89 
96 {
98 }
99 
106 {
107  spi->SSR &= ~SPI_SSR_AUTOSS_Msk;
108 }
109 
117 void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel)
118 {
119  spi->SSR = (spi->SSR & ~(SPI_SSR_SS_LVL_Msk | SPI_SSR_SSR_Msk)) | (u32SSPinMask | u32ActiveLevel) | SPI_SSR_AUTOSS_Msk;
120 }
121 
128 uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock)
129 {
130  uint32_t u32ClkSrc, u32Div = 0;
131 
132  u32ClkSrc = CLK_GetHCLKFreq();
133 
134  if(u32BusClock > u32ClkSrc)
135  u32BusClock = u32ClkSrc;
136 
137  if(u32BusClock != 0 )
138  {
139  u32Div = (u32ClkSrc / u32BusClock) - 1;
140  if(u32Div > SPI_CLKDIV_DIVIDER1_Msk)
141  u32Div = SPI_CLKDIV_DIVIDER1_Msk;
142  }
143  else
144  return 0;
145 
146  spi->CLKDIV = (spi->CLKDIV & ~SPI_CLKDIV_DIVIDER1_Msk) | u32Div;
147 
148  return ( u32ClkSrc / (u32Div+1) );
149 }
150 
157 {
158  spi->CTL |= SPI_CTL_FIFOM_Msk;
159 }
160 
167 {
168  spi->CTL &= ~SPI_CTL_FIFOM_Msk;
169 }
170 
176 uint32_t SPI_GetBusClock(SPI_T *spi)
177 {
178  uint32_t u32Div;
179  uint32_t u32ClkSrc;
180 
181  u32ClkSrc = CLK_GetHCLKFreq();
182 
183  u32Div = spi->CLKDIV & SPI_CLKDIV_DIVIDER1_Msk;
184  return (u32ClkSrc / (u32Div + 1));
185 }
186 
197 void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask)
198 {
199  if((u32Mask & SPI_IE_MASK) == SPI_IE_MASK)
200  spi->CTL |= SPI_CTL_INTEN_Msk;
201 
202  if((u32Mask & SPI_SSTA_INTEN_MASK) == SPI_SSTA_INTEN_MASK)
203  spi->SSR |= SPI_SSR_SSTA_INTEN_Msk;
204 }
205 
216 void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask)
217 {
218  if((u32Mask & SPI_IE_MASK) == SPI_IE_MASK)
219  spi->CTL &= ~SPI_CTL_INTEN_Msk;
220 
221  if((u32Mask & SPI_SSTA_INTEN_MASK) == SPI_SSTA_INTEN_MASK)
222  spi->SSR &= ~SPI_SSR_SSTA_INTEN_Msk;
223 }
224 
231 {
232  spi->CTL |= SPI_CTL_WKEUP_EN_Msk;
233 }
234 
241 {
242  spi->CTL &= ~SPI_CTL_WKEUP_EN_Msk;
243 }
244  /* end of group NANO100_SPI_EXPORTED_FUNCTIONS */
246  /* end of group NANO100_SPI_Driver */
248  /* end of group NANO100_Device_Driver */
250 
251 /*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
#define SPI_CTL_INTEN_Msk
#define SPI_SSTA_INTEN_MASK
Definition: spi.h:51
void SPI_DisableAutoSS(SPI_T *spi)
Disable the automatic slave select function.
Definition: spi.c:105
void SPI_EnableFIFO(SPI_T *spi)
Enable FIFO mode with user-specified Tx FIFO threshold and Rx FIFO threshold configurations.
Definition: spi.c:156
#define SPI_CTL_TX_BIT_LEN_Pos
#define SPI_FFCLR_RX_CLR_Msk
uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock)
Set the SPI bus clock. Only available in Master mode.
Definition: spi.c:128
#define SPI_CTL_FIFOM_Msk
#define SPI_SSR_SS_LVL_Msk
__IO uint32_t SSR
#define SPI0
Pointer to SPI0 register structure.
uint32_t CLK_GetHCLKFreq(void)
This function get HCLK frequency. The frequency unit is Hz.
Definition: clk.c:121
#define SPI1
Pointer to SPI1 register structure.
void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask)
Enable FIFO related interrupts specified by u32Mask parameter.
Definition: spi.c:197
Nano100 series peripheral access layer header file. This file contains all the peripheral register's ...
void SPI_ClearRxFIFO(SPI_T *spi)
Clear Rx FIFO buffer.
Definition: spi.c:85
#define SYS_IPRST_CTL2_SPI0_RST_Msk
void SPI_Close(SPI_T *spi)
Reset SPI module.
Definition: spi.c:60
__IO uint32_t CTL
#define SPI_CLKDIV_DIVIDER1_Msk
void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask)
Disable FIFO related interrupts specified by u32Mask parameter.
Definition: spi.c:216
uint32_t SPI_GetBusClock(SPI_T *spi)
Get the actual frequency of SPI bus clock. Only available in Master mode.
Definition: spi.c:176
#define SYS_IPRST_CTL2_SPI1_RST_Msk
void SPI_DisableFIFO(SPI_T *spi)
Disable FIFO mode.
Definition: spi.c:166
void SPI_ClearTxFIFO(SPI_T *spi)
Clear Tx FIFO buffer.
Definition: spi.c:95
void SPI_DisableWakeup(SPI_T *spi)
Disable wake-up function.
Definition: spi.c:240
#define SPI_IE_MASK
Definition: spi.h:50
__IO uint32_t FFCLR
#define SPI_FFCLR_TX_CLR_Msk
void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel)
Enable the automatic slave select function. Only available in Master mode.
Definition: spi.c:117
uint32_t SPI_Open(SPI_T *spi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock)
This function make SPI module be ready to transfer. By default, the SPI transfer sequence is MSB firs...
Definition: spi.c:41
#define SPI_SSR_AUTOSS_Msk
__IO uint32_t CLKDIV
#define SPI_SSR_SSR_Msk
#define SPI_SSR_SSTA_INTEN_Msk
void SPI_EnableWakeup(SPI_T *spi)
Enable wake-up function.
Definition: spi.c:230
#define SYS_IPRST_CTL2_SPI2_RST_Msk
#define SPI_CTL_WKEUP_EN_Msk
#define SYS
Pointer to SYS register structure.