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Nano100AN Series BSP
V3.02.002
The Board Support Package for Nano100AN Series
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#include <Nano100Series.h>
Data Fields | |
| __IO uint32_t | PRES |
| __IO uint32_t | CLKSEL |
| __IO uint32_t | CTL |
| __IO uint32_t | INTEN |
| __IO uint32_t | INTSTS |
| __IO uint32_t | OE |
| __IO uint32_t | DUTY0 |
| __I uint32_t | DATA0 |
| __IO uint32_t | DUTY1 |
| __I uint32_t | DATA1 |
| __IO uint32_t | DUTY2 |
| __I uint32_t | DATA2 |
| __IO uint32_t | DUTY3 |
| __I uint32_t | DATA3 |
| __IO uint32_t | CAPCTL |
| __IO uint32_t | CAPINTEN |
| __IO uint32_t | CAPINTSTS |
| __I uint32_t | CRL0 |
| __I uint32_t | CFL0 |
| __I uint32_t | CRL1 |
| __I uint32_t | CFL1 |
| __I uint32_t | CRL2 |
| __I uint32_t | CFL2 |
| __I uint32_t | CRL3 |
| __I uint32_t | CFL3 |
| __I uint32_t | PDMACH0 |
| __I uint32_t | PDMACH2 |
@addtogroup PWM Pulse Width Modulation Controller(PWM) Memory Mapped Structure for PWM Controller
Definition at line 5283 of file Nano100Series.h.
| __IO uint32_t PWM_T::CAPCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | INV0 | Channel 0 Inverter ON/OFF |
| 0 = Inverter OFF. | ||
| 1 = Inverter ON. Reverse the input signal from GPIO before fed to Capture timer | ||
| [1] | CAPCH0EN | Capture Channel 0 Transition Enable/Disable |
| 0 = Capture function on channel 0 Disabled. | ||
| 1 = Capture function on channel 0 Enabled. | ||
| When Enabled, Capture latched the PWM-timer value and saved to PWM_CRL0 (Rising latch) and PWM_CFL0 (Falling latch). | ||
| When Disabled, Capture does not update PWM_CRL0 and PWM_CFL0, and disable Channel 0 Interrupt. | ||
| [2] | CAPCH0PADEN | Capture Input Enable |
| 0 = OFF. | ||
| 1 = ON. | ||
| [3] | CH0PDMAEN | Channel 0 PDMA Enable |
| 0 = Channel 0 PDMA function Disabled. | ||
| 1 = Channel 0 PDMA function Enabled for the channel 0 captured data and transfer to memory. | ||
| [5:4] | PDMACAPMOD0 | Select CRL0 Or CFL0 For PDMA Transfer |
| 00 = Reserved. | ||
| 01 = CRL0. | ||
| 10 = CFL0. | ||
| 11 = Both CRL0 and CFL0. | ||
| [6] | CAPRELOADREN0 | Reload CNR0 When CH0 Capture Rising Event Comes |
| 0 = Rising capture reload for CH0 Disabled. | ||
| 1 = Rising capture reload for CH0 Enabled. | ||
| [7] | CAPRELOADFEN0 | Reload CNR0 When CH0 Capture Falling Event Comes |
| 0 = Falling capture reload for CH0 Disabled. | ||
| 1 = Falling capture reload for CH0 Enabled. | ||
| [8] | INV1 | Channel 1 Inverter ON/OFF |
| 0 = Inverter OFF. | ||
| 1 = Inverter ON. Reverse the input signal from GPIO before fed to Capture timer | ||
| [9] | CAPCH1EN | Capture Channel 1 Transition Enable/Disable |
| 0 = Capture function on channel 1 Disabled. | ||
| 1 = Capture function on channel 1 Enabled. | ||
| When Enabled, Capture latched the PMW-counter and saved to PWM_CRL1 (Rising latch) and PWM_CFL1 (Falling latch). | ||
| When Disabled, Capture does not update PWM_CRL1 and PWM_CFL1, and disable Channel 1 Interrupt. | ||
| [10] | CAPCH1PADEN | Capture Input Enable |
| 0 = OFF. | ||
| 1 = ON. | ||
| [12] | CH0RFORDER | Channel 0 capture order control |
| Set this bit to determine whether the PWM_CRL0 or PWM_CFL0 is the first captured data transferred to memory through PDMA when PDMACAPMOD0 =2'b11. | ||
| 0 = PWM_CFL0 is the first captured data to memory. | ||
| 1 = PWM_CRL0 is the first captured data to memory. | ||
| [13] | CH01CASK | Cascade channel 0 and channel 1 PWM timer for capturing usage |
| [14] | CAPRELOADREN1 | Reload CNR1 When CH1 Capture Rising Event Comes |
| 0 = Rising capture reload for CH1 Disabled. | ||
| 1 = Rising capture reload for CH1 Enabled. | ||
| [15] | CAPRELOADFEN1 | Reload CNR1 When CH1 Capture Falling Event Coming |
| 0 = Capture falling reload for CH1 Disabled. | ||
| 1 = Capture falling reload for CH1 Enabled. | ||
| [16] | INV2 | Channel 2 Inverter ON/OFF |
| 0 = Inverter OFF. | ||
| 1 = Inverter ON. Reverse the input signal from GPIO before fed to Capture timer | ||
| [17] | CAPCH2EN | Capture Channel 2 Transition Enable/Disable |
| 0 = Capture function on channel 2 Disabled. | ||
| 1 = Capture function on channel 2 Enabled. | ||
| When Enabled, Capture latched the PWM-timer value and saved to PWM_CRL2 (Rising latch) and PWM_CFL2 (Falling latch). | ||
| When Disabled, Capture does not update PWM_CRL2 and PWM_CFL2, and disable Channel 2 Interrupt. | ||
| [18] | CAPCH2PADEN | Capture Input Enable |
| 0 = OFF. | ||
| 1 = ON. | ||
| [19] | CH2PDMAEN | Channel 2 PDMA Enable |
| 0 = Channel 2 PDMA function Disabled. | ||
| 1 = Channel 2 PDMA function Enabled for the channel 2 captured data and transfer to memory. | ||
| [21:20] | PDMACAPMOD2 | Select CRL2 Or CFL2 For PDMA Transfer |
| 00 = Reserved. | ||
| 01 = CRL2. | ||
| 10 = CFL2. | ||
| 11 = Both CRL2 and CFL2. | ||
| [22] | CAPRELOADREN2 | Reload CNR2 When CH2 Capture Rising Event Coming |
| 0 = Rising capture reload for CH2 Disabled. | ||
| 1 = Rising capture reload for CH2 Enabled. | ||
| [23] | CAPRELOADFEN2 | Reload CNR2 When CH2 Capture Failing Event Coming |
| 0 = Failing capture reload for CH2 Disabled. | ||
| 1 = Failing capture reload for CH2 Enabled. | ||
| [24] | INV3 | Channel 3 Inverter ON/OFF |
| 0 = Inverter OFF. | ||
| 1 = Inverter ON. Reverse the input signal from GPIO before fed to Capture timer | ||
| [25] | CAPCH3EN | Capture Channel 3 Transition Enable/Disable |
| 0 = Capture function on channel 3 Disabled. | ||
| 1 = Capture function on channel 3 Enabled. | ||
| When Enabled, Capture latched the PMW-timer and saved to PWM_CRL3 (Rising latch) and PWM_CFL3 (Falling latch). | ||
| When Disabled, Capture does not update PWM_CRL3 and PWM_CFL3, and disable Channel 3 Interrupt. | ||
| [26] | CAPCH3PADEN | Capture Input Enable |
| 0 = OFF. | ||
| 1 = ON. | ||
| [28] | CH2RFORDER | Channel 0 capture order control |
| Set this bit to determine whether the PWM_CRL2 or PWM_CFL2 is the first captured data transferred to memory through PDMA when PDMACAPMOD2 = 2'b11. | ||
| 0 = PWM_CFL2 is the first captured data to memory. | ||
| 1 = PWM_CRL2 is the first captured data to memory. | ||
| [29] | CH23CASK | Cascade channel 2 and channel 3 PWM counter for capturing usage |
| [30] | CAPRELOADREN3 | Reload CNR3 When CH3 Rising Capture Event Comes |
| 0 = Rising capture reload for CH3 Disabled. | ||
| 1 = Rising capture reload for CH3 Enabled. | ||
| [31] | CAPRELOADFEN3 | Reload CNR3 When CH3 Falling Capture Event Comes |
| 0 = Falling capture reload for CH3 Disabled. | ||
| 1 = Falling capture reload for CH3 Enabled. |
Definition at line 5796 of file Nano100Series.h.
| __IO uint32_t PWM_T::CAPINTEN |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | CRL_IE0 | Channel 0 Rising Latch Interrupt Enable ON/OFF |
| 0 = Rising latch interrupt Disabled. | ||
| 1 = Rising latch interrupt Enabled. | ||
| When Enabled, if Capture detects Channel 0 has rising transition, Capture issues an Interrupt. | ||
| [1] | CFL_IE0 | Channel 0 Falling Latch Interrupt Enable ON/OFF |
| 0 = Falling latch interrupt Disabled. | ||
| 1 = Falling latch interrupt Enabled. | ||
| When Enabled, if Capture detects Channel 0 has falling transition, Capture issues an Interrupt. | ||
| [8] | CRL_IE1 | Channel 1 Rising Latch Interrupt Enable |
| 0 = Rising latch interrupt Disabled. | ||
| 1 = Rising latch interrupt Enabled. | ||
| When Enabled, if Capture detects Channel 1 has rising transition, Capture issues an Interrupt. | ||
| [9] | CFL_IE1 | Channel 1 Falling Latch Interrupt Enable |
| 0 = Falling latch interrupt Disabled. | ||
| 1 = Falling latch interrupt Enabled. | ||
| When Enabled, if Capture detects Channel 1 has falling transition, Capture issues an Interrupt. | ||
| [16] | CRL_IE2 | Channel 2 Rising Latch Interrupt Enable ON/OFF |
| 0 = Rising latch interrupt Disabled. | ||
| 1 = Rising latch interrupt Enabled. | ||
| When Enabled, if Capture detects Channel 2 has rising transition, Capture issues an Interrupt. | ||
| [17] | CFL_IE2 | Channel 2 Falling Latch Interrupt Enable ON/OFF |
| 0 = Falling latch interrupt Disabled. | ||
| 1 = Falling latch interrupt Enabled. | ||
| When Enabled, if Capture detects Channel 2 has falling transition, Capture issues an Interrupt. | ||
| [24] | CRL_IE3 | Channel 3 Rising Latch Interrupt Enable ON/OFF |
| 0 = Rising latch interrupt Disabled. | ||
| 1 = Rising latch interrupt Enabled. | ||
| When Enabled, if Capture detects Channel 3 has rising transition, Capture issues an Interrupt. | ||
| [25] | CFL_IE3 | Channel 3 Falling Latch Interrupt Enable ON/OFF |
| 0 = Falling latch interrupt Disabled. | ||
| 1 = Falling latch interrupt Enabled. | ||
| When Enabled, if Capture detects Channel 3 has falling transition, Capture issues an Interrupt. |
Definition at line 5838 of file Nano100Series.h.
| __IO uint32_t PWM_T::CAPINTSTS |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | CAPIF0 | Capture0 Interrupt Indication Flag |
| If channel 0 rising latch interrupt is enabled (CRL_IE0=1), a rising transition occurs at input channel 0 will result in CAPIF0 to high; Similarly, a falling transition will cause CAPIF0 to be set high if channel 0 falling latch interrupt is enabled (CFL_IE0=1). | ||
| This flag is clear by software with a write one on it. | ||
| [1] | CRLI0 | PWM_CRL0 Latched Indicator Bit |
| When input channel 0 has a rising transition, PWM0_CRL0 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing 1 to it. | ||
| [2] | CFLRI0 | PWM_CFL0 Latched Indicator Bit |
| When input channel 0 has a falling transition, PWM0_CFL0 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing 1 to it. | ||
| [3] | CAPOVR0 | Capture Rising Flag Over Run For Channel 0 |
| This flag indicate CRL0 update faster than software reading it when it is set | ||
| This bit will be cleared automatically when user clear CRLI0 bit 1 of PWM_CAPINTSTS | ||
| [4] | CAPOVF0 | Capture Falling Flag Over Run For Channel 0 |
| This flag indicate CFL0 update faster than software reading it when it is set | ||
| This bit will be cleared automatically when user clear CFLI0 bit 2 of PWM_CAPINTSTS | ||
| [8] | CAPIF1 | Capture1 Interrupt Indication Flag |
| If channel 1 rising latch interrupt is enabled (CRL_IE1=1), a rising transition occurs at input channel 1 will result in CAPIF1 to high; Similarly, a falling transition will cause CAPIF1 to be set high if channel 1 falling latch interrupt is enabled (CFL_IE1=1). | ||
| This flag is clear by software with a write one on it. | ||
| [9] | CRLI1 | PWM_CRL1 Latched Indicator Bit |
| When input channel 1 has a rising transition, PWM0_CRL1 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing 1 to it. | ||
| [10] | CFLI1 | PWM_CFL1 Latched Indicator Bit |
| When input channel 1 has a falling transition, PWM0_CFL1 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing a 1 to it. | ||
| [11] | CAPOVR1 | Capture Rising Flag Over Run For Channel 1 |
| This flag indicate CRL1 update faster than software reading it when it is set | ||
| This bit will be cleared automatically when user clear CRLI1 bit 9 of PWM_CAPINTSTS | ||
| [12] | CAPOVF1 | Capture Falling Flag Over Run For Channel 1 |
| This flag indicate CFL1 update faster than software reading it when it is set | ||
| This bit will be cleared automatically when user clear CFLI1 bit 10 of PWM_CAPINTSTS | ||
| [16] | CAPIF2 | Capture2 Interrupt Indication Flag |
| If channel 2 rising latch interrupt is enabled (CRL_IE2=1), a rising transition occurs at input channel 2 will result in CAPIF2 to high; Similarly, a falling transition will cause CAPIF2 to be set high if channel 2 falling latch interrupt is enabled (CFL_IE2=1). | ||
| This flag is clear by software with a write one on it. | ||
| [17] | CRLI2 | PWM_CRL2 Latched Indicator Bit |
| When input channel 2 has a rising transition, PWM0_CRL2 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing 1 to it. | ||
| [18] | CFLI2 | PWM_CFL2 Latched Indicator Bit |
| When input channel 2 has a falling transition, PWM0_CFL2 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing 1 to it. | ||
| [19] | CAPOVR2 | Capture Rising Flag Over Run For Channel 2 |
| This flag indicate CRL2 update faster than software reading it when it is set | ||
| This bit will be cleared automatically when user clear CRLI2 bit 17 of PWM_CAPINTSTS | ||
| [20] | CAPOVF2 | Capture Falling Flag Over Run For Channel 2 |
| This flag indicate CFL2 update faster than software reading it when it is set | ||
| This bit will be cleared automatically when user clear CFLI2 bit 18 of PWM_CAPINTSTS | ||
| [24] | CAPIF3 | Capture3 Interrupt Indication Flag |
| If channel 3 rising latch interrupt is enabled (CRL_IE0=1), a rising transition occurs at input channel 3 will result in CAPIF3 to high; Similarly, a falling transition will cause CAPIF3 to be set high if channel 3 falling latch interrupt is enabled (CFL_IE3=1). | ||
| This flag is clear by software with a write one on it. | ||
| [25] | CRLI3 | PWM_CRL3 Latched Indicator Bit |
| When input channel 3 has a rising transition, PWM_CRL3 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing 1 to it. | ||
| [26] | CFLI3 | PWM_CFL3 Latched Indicator Bit |
| When input channel 3 has a falling transition, PWM_CFL3 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing 1 to it. | ||
| [27] | CAPOVR3 | Capture Rising Flag Over Run For Channel 3 |
| This flag indicate CRL3update faster than software reading it when it is set | ||
| This bit will be cleared automatically when user clear CRLI3 bit 25 of PWM_CAPINTSTS | ||
| [28] | CAPOVF3 | Capture Falling Flag Over Run For Channel 3 |
| This flag indicate CFL3 update faster than software reading it when it is set | ||
| This bit will be cleared automatically when user clear CFLI3 bit 26 of PWM_CAPINTSTS |
Definition at line 5900 of file Nano100Series.h.
| __I uint32_t PWM_T::CFL0 |
| Bits | Field | Descriptions |
|---|---|---|
| [15:0] | CFL15_0 | Capture Falling Latch Register |
| Latch the PWM counter when Channel 01/2/3 has Falling transition. | ||
| [31:16] | CFL31_16 | Upper Half Word Of 32 Bit Capture Data When Cascade Is Enable |
| When cascade is enabled for capture channel 0 ,2,the original 16 bit counter extend to 32 bit, and capture result CFL0 and CFL2 are also extend to 32 bit. |
Definition at line 5928 of file Nano100Series.h.
| __I uint32_t PWM_T::CFL1 |
| Bits | Field | Descriptions |
|---|---|---|
| [15:0] | CFL15_0 | Capture Falling Latch Register |
| Latch the PWM counter when Channel 01/2/3 has Falling transition. | ||
| [31:16] | CFL31_16 | Upper Half Word Of 32 Bit Capture Data When Cascade Is Enable |
| When cascade is enabled for capture channel 0 ,2,the original 16 bit counter extend to 32 bit, and capture result CFL0 and CFL2 are also extend to 32 bit. |
Definition at line 5956 of file Nano100Series.h.
| __I uint32_t PWM_T::CFL2 |
| Bits | Field | Descriptions |
|---|---|---|
| [15:0] | CFL15_0 | Capture Falling Latch Register |
| Latch the PWM counter when Channel 01/2/3 has Falling transition. | ||
| [31:16] | CFL31_16 | Upper Half Word Of 32 Bit Capture Data When Cascade Is Enable |
| When cascade is enabled for capture channel 0 ,2,the original 16 bit counter extend to 32 bit, and capture result CFL0 and CFL2 are also extend to 32 bit. |
Definition at line 5984 of file Nano100Series.h.
| __I uint32_t PWM_T::CFL3 |
| Bits | Field | Descriptions |
|---|---|---|
| [15:0] | CFL15_0 | Capture Falling Latch Register |
| Latch the PWM counter when Channel 01/2/3 has Falling transition. | ||
| [31:16] | CFL31_16 | Upper Half Word Of 32 Bit Capture Data When Cascade Is Enable |
| When cascade is enabled for capture channel 0 ,2,the original 16 bit counter extend to 32 bit, and capture result CFL0 and CFL2 are also extend to 32 bit. |
Definition at line 6012 of file Nano100Series.h.
| __IO uint32_t PWM_T::CLKSEL |
| Bits | Field | Descriptions |
|---|---|---|
| [2:0] | CLKSEL0 | Timer 0 Clock Source Selection |
| Select clock input for timer 0. | ||
| (Table is the same as CLKSEL3) | ||
| [6:4] | CLKSEL1 | Timer 1 Clock Source Selection |
| Select clock input for timer 1. | ||
| (Table is the same as CLKSEL3) | ||
| [10:8] | CLKSEL2 | Timer 2Clock Source Selection |
| Select clock input for timer 2. | ||
| (Table is the same as CLKSEL3) | ||
| [14:12] | CLKSEL3 | Timer 3 Clock Source Selection |
| Select clock input for timer 3. | ||
| 000 = Input Clock Divided by 2. | ||
| 001 = Input Clock Divided by 4. | ||
| 010 = Input Clock Divided by 8. | ||
| 011 = Input Clock Divided by 16. | ||
| 100 = Input Clock Divided by 1. |
Definition at line 5335 of file Nano100Series.h.
| __I uint32_t PWM_T::CRL0 |
| Bits | Field | Descriptions |
|---|---|---|
| [15:0] | CRL15_0 | Capture Rising Latch Register |
| Latch the PWM counter when Channel 0/1/2/3 has rising transition. | ||
| [31:16] | CRL31_16 | Upper Half Word Of 32 Bit Capture Data When Cascade Is Enable |
| When cascade is enabled for capture channel 0 ,2,the original 16 bit counter extend to 32 bit, and capture result CRL0 and CRL2 are also extend to 32 bit. |
Definition at line 5914 of file Nano100Series.h.
| __I uint32_t PWM_T::CRL1 |
| Bits | Field | Descriptions |
|---|---|---|
| [15:0] | CRL15_0 | Capture Rising Latch Register |
| Latch the PWM counter when Channel 0/1/2/3 has rising transition. | ||
| [31:16] | CRL31_16 | Upper Half Word Of 32 Bit Capture Data When Cascade Is Enable |
| When cascade is enabled for capture channel 0 ,2,the original 16 bit counter extend to 32 bit, and capture result CRL0 and CRL2 are also extend to 32 bit. |
Definition at line 5942 of file Nano100Series.h.
| __I uint32_t PWM_T::CRL2 |
| Bits | Field | Descriptions |
|---|---|---|
| [15:0] | CRL15_0 | Capture Rising Latch Register |
| Latch the PWM counter when Channel 0/1/2/3 has rising transition. | ||
| [31:16] | CRL31_16 | Upper Half Word Of 32 Bit Capture Data When Cascade Is Enable |
| When cascade is enabled for capture channel 0 ,2,the original 16 bit counter extend to 32 bit, and capture result CRL0 and CRL2 are also extend to 32 bit. |
Definition at line 5970 of file Nano100Series.h.
| __I uint32_t PWM_T::CRL3 |
| Bits | Field | Descriptions |
|---|---|---|
| [15:0] | CRL15_0 | Capture Rising Latch Register |
| Latch the PWM counter when Channel 0/1/2/3 has rising transition. | ||
| [31:16] | CRL31_16 | Upper Half Word Of 32 Bit Capture Data When Cascade Is Enable |
| When cascade is enabled for capture channel 0 ,2,the original 16 bit counter extend to 32 bit, and capture result CRL0 and CRL2 are also extend to 32 bit. |
Definition at line 5998 of file Nano100Series.h.
| __IO uint32_t PWM_T::CTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | CH0EN | PWM-Timer 0 Enable/Disable Start Run |
| 0 = PWM-Timer 0 Running Stopped. | ||
| 1 = PWM-Timer 0 Start Run Enabled. | ||
| [2] | CH0INV | PWM-Timer 0 Output Inverter ON/OFF |
| 0 = Inverter OFF. | ||
| 1 = Inverter ON. | ||
| [3] | CH0MOD | PWM-Timer 0 Continuous/One-Shot Mode |
| 0 = One-Shot Mode. | ||
| 1 = Continuous Mode. | ||
| Note: If there is a rising transition at this bit, it will cause CN and CM of PWM0_DUTY0 to be cleared. | ||
| [4] | DZEN01 | Dead-Zone 0 Generator Enable/Disable |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| Note: When Dead-Zone Generator is enabled, the pair of PWM0 and PWM1 becomes a complementary pair. | ||
| [5] | DZEN23 | Dead-Zone 2 Generator Enable/Disable |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| Note: When Dead-Zone Generator is enabled, the pair of PWM2 and PWM3 becomes a complementary pair. | ||
| [8] | CH1EN | PWM-Timer 1 Enable/Disable Start Run |
| 0 = PWM-Timer 1 Running Stopped. | ||
| 1 = PWM-Timer 1 Start Run Enabled. | ||
| [10] | CH1INV | PWM-Timer 1 Output Inverter ON/OFF |
| 0 = Inverter OFF. | ||
| 1 = Inverter ON. | ||
| [11] | CH1MOD | PWM-Timer 1 Continuous/One-Shot Mode |
| 0 = One-Shot Mode. | ||
| 1 = Continuous Mode. | ||
| Note: If there is a rising transition at this bit, it will cause CN and CM of PWM0_DUTY1 to be cleared. | ||
| [16] | CH2EN | PWM-Timer 2 Enable/Disable Start Run |
| 0 = PWM-Timer 2 Running Stopped. | ||
| 1 = PWM-Timer 2 Start Run Enabled. | ||
| [18] | CH2INV | PWM-Timer 2 Output Inverter ON/OFF |
| 0 = Inverter OFF. | ||
| 1 = Inverter ON. | ||
| [19] | CH2MOD | PWM-Timer 2 Continuous/One-Shot Mode |
| 0 = One-Shot Mode. | ||
| 1 = Continuous Mode. | ||
| Note: If there is a rising transition at this bit, it will cause CN and CM of PWM0_DUTY2 be cleared. | ||
| [24] | CH3EN | PWM-Timer 3 Enable/Disable Start Run |
| 0 = PWM-Timer 3 Running Stopped. | ||
| 1 = PWM-Timer 3 Start Run Enabled. | ||
| [26] | CH3INV | PWM-Timer 3 Output Inverter ON/OFF |
| 0 = Inverter OFF. | ||
| 1 = Inverter ON. | ||
| [27] | CH3MOD | PWM-Timer 3 Continuous/One-Shot Mode |
| 0 = One-Shot Mode. | ||
| 1 = Continuous Mode. | ||
| Note: If there is a rising transition at this bit, it will cause CN and CM of PWM0_DUTY3 to be clear. |
Definition at line 5393 of file Nano100Series.h.
| __I uint32_t PWM_T::DATA0 |
| Bits | Field | Descriptions |
|---|---|---|
| [15:0] | PWMx_DATAy15_0 | PWM Data Register ( x=0~1,y=0~3). |
| User can monitor PWMx_DATAy to know the current value in 16-bit down count counter. | ||
| [30:16] | PWMx_DATAy30_16 | PWM Data Register ( x=0~1,y=0,2). |
| User can monitor PWMx_DATAy to know the current value in 32-bit down count counter | ||
| Notes:This will be valid only for the corresponding cascade enable .bit is set | ||
| [31] | sync | Indicate That CNR Value Is Sync To PWM Counter |
| 0 = CNR value is sync to PWM counter. | ||
| 1 = CNR value is not sync to PWM counter. | ||
| Note: when the corresponding cascade enable .bit is set is bit will not appear in the corresponding channel |
Definition at line 5531 of file Nano100Series.h.
| __I uint32_t PWM_T::DATA1 |
| Bits | Field | Descriptions |
|---|---|---|
| [15:0] | PWMx_DATAy15_0 | PWM Data Register ( x=0~1,y=0~3). |
| User can monitor PWMx_DATAy to know the current value in 16-bit down count counter. | ||
| [30:16] | PWMx_DATAy30_16 | PWM Data Register ( x=0~1,y=0,2). |
| User can monitor PWMx_DATAy to know the current value in 32-bit down count counter | ||
| Notes:This will be valid only for the corresponding cascade enable .bit is set | ||
| [31] | sync | Indicate That CNR Value Is Sync To PWM Counter |
| 0 = CNR value is sync to PWM counter. | ||
| 1 = CNR value is not sync to PWM counter. | ||
| Note: when the corresponding cascade enable .bit is set is bit will not appear in the corresponding channel |
Definition at line 5583 of file Nano100Series.h.
| __I uint32_t PWM_T::DATA2 |
| Bits | Field | Descriptions |
|---|---|---|
| [15:0] | PWMx_DATAy15_0 | PWM Data Register ( x=0~1,y=0~3). |
| User can monitor PWMx_DATAy to know the current value in 16-bit down count counter. | ||
| [30:16] | PWMx_DATAy30_16 | PWM Data Register ( x=0~1,y=0,2). |
| User can monitor PWMx_DATAy to know the current value in 32-bit down count counter | ||
| Notes:This will be valid only for the corresponding cascade enable .bit is set | ||
| [31] | sync | Indicate That CNR Value Is Sync To PWM Counter |
| 0 = CNR value is sync to PWM counter. | ||
| 1 = CNR value is not sync to PWM counter. | ||
| Note: when the corresponding cascade enable .bit is set is bit will not appear in the corresponding channel |
Definition at line 5635 of file Nano100Series.h.
| __I uint32_t PWM_T::DATA3 |
| Bits | Field | Descriptions |
|---|---|---|
| [15:0] | PWMx_DATAy15_0 | PWM Data Register ( x=0~1,y=0~3). |
| User can monitor PWMx_DATAy to know the current value in 16-bit down count counter. | ||
| [30:16] | PWMx_DATAy30_16 | PWM Data Register ( x=0~1,y=0,2). |
| User can monitor PWMx_DATAy to know the current value in 32-bit down count counter | ||
| Notes:This will be valid only for the corresponding cascade enable .bit is set | ||
| [31] | sync | Indicate That CNR Value Is Sync To PWM Counter |
| 0 = CNR value is sync to PWM counter. | ||
| 1 = CNR value is not sync to PWM counter. | ||
| Note: when the corresponding cascade enable .bit is set is bit will not appear in the corresponding channel |
Definition at line 5687 of file Nano100Series.h.
| __IO uint32_t PWM_T::DUTY0 |
| Bits | Field | Descriptions |
|---|---|---|
| [15:0] | CN | PWM Counter/Timer Loaded Value |
| CN determines the PWM period. | ||
| PWM frequency = PWMxy_CLK/(prescale+1)*(clock divider)/(CN+1); where xy, could be 01, 23, depends on selected PWM channel. | ||
| Duty ratio = (CM+1)/(CN+1). | ||
| CM >= CN: PWM output is always high. | ||
| CM < CN: PWM low width = (CN-CM) unit; PWM high width = (CM+1) unit. | ||
| CM = 0: PWM low width = (CN) unit; PWM high width = 1 unit. | ||
| (Unit = one PWM clock cycle). | ||
| Note: Any write to CN will take effect in next PWM cycle. | ||
| [31:16] | CM | PWM Comparator Register |
| CM determines the PWM duty. | ||
| PWM frequency = PWMxy_CLK/(prescale+1)*(clock divider)/(CN+1); where xy, could be 01, 23 , depends on selected PWM channel. | ||
| Duty ratio = (CM+1)/(CN+1). | ||
| CM >= CN: PWM output is always high. | ||
| CM < CN: PWM low width = (CN-CM) unit; PWM high width = (CM+1) unit. | ||
| CM = 0: PWM low width = (CN) unit; PWM high width = 1 unit. | ||
| (Unit = one PWM clock cycle). | ||
| Note: Any write to CM will take effect in next PWM cycle. |
Definition at line 5512 of file Nano100Series.h.
| __IO uint32_t PWM_T::DUTY1 |
| Bits | Field | Descriptions |
|---|---|---|
| [15:0] | CN | PWM Counter/Timer Loaded Value |
| CN determines the PWM period. | ||
| PWM frequency = PWMxy_CLK/(prescale+1)*(clock divider)/(CN+1); where xy, could be 01, 23, depends on selected PWM channel. | ||
| Duty ratio = (CM+1)/(CN+1). | ||
| CM >= CN: PWM output is always high. | ||
| CM < CN: PWM low width = (CN-CM) unit; PWM high width = (CM+1) unit. | ||
| CM = 0: PWM low width = (CN) unit; PWM high width = 1 unit. | ||
| (Unit = one PWM clock cycle). | ||
| Note: Any write to CN will take effect in next PWM cycle. | ||
| [31:16] | CM | PWM Comparator Register |
| CM determines the PWM duty. | ||
| PWM frequency = PWMxy_CLK/(prescale+1)*(clock divider)/(CN+1); where xy, could be 01, 23 , depends on selected PWM channel. | ||
| Duty ratio = (CM+1)/(CN+1). | ||
| CM >= CN: PWM output is always high. | ||
| CM < CN: PWM low width = (CN-CM) unit; PWM high width = (CM+1) unit. | ||
| CM = 0: PWM low width = (CN) unit; PWM high width = 1 unit. | ||
| (Unit = one PWM clock cycle). | ||
| Note: Any write to CM will take effect in next PWM cycle. |
Definition at line 5564 of file Nano100Series.h.
| __IO uint32_t PWM_T::DUTY2 |
| Bits | Field | Descriptions |
|---|---|---|
| [15:0] | CN | PWM Counter/Timer Loaded Value |
| CN determines the PWM period. | ||
| PWM frequency = PWMxy_CLK/(prescale+1)*(clock divider)/(CN+1); where xy, could be 01, 23, depends on selected PWM channel. | ||
| Duty ratio = (CM+1)/(CN+1). | ||
| CM >= CN: PWM output is always high. | ||
| CM < CN: PWM low width = (CN-CM) unit; PWM high width = (CM+1) unit. | ||
| CM = 0: PWM low width = (CN) unit; PWM high width = 1 unit. | ||
| (Unit = one PWM clock cycle). | ||
| Note: Any write to CN will take effect in next PWM cycle. | ||
| [31:16] | CM | PWM Comparator Register |
| CM determines the PWM duty. | ||
| PWM frequency = PWMxy_CLK/(prescale+1)*(clock divider)/(CN+1); where xy, could be 01, 23 , depends on selected PWM channel. | ||
| Duty ratio = (CM+1)/(CN+1). | ||
| CM >= CN: PWM output is always high. | ||
| CM < CN: PWM low width = (CN-CM) unit; PWM high width = (CM+1) unit. | ||
| CM = 0: PWM low width = (CN) unit; PWM high width = 1 unit. | ||
| (Unit = one PWM clock cycle). | ||
| Note: Any write to CM will take effect in next PWM cycle. |
Definition at line 5616 of file Nano100Series.h.
| __IO uint32_t PWM_T::DUTY3 |
| Bits | Field | Descriptions |
|---|---|---|
| [15:0] | CN | PWM Counter/Timer Loaded Value |
| CN determines the PWM period. | ||
| PWM frequency = PWMxy_CLK/(prescale+1)*(clock divider)/(CN+1); where xy, could be 01, 23, depends on selected PWM channel. | ||
| Duty ratio = (CM+1)/(CN+1). | ||
| CM >= CN: PWM output is always high. | ||
| CM < CN: PWM low width = (CN-CM) unit; PWM high width = (CM+1) unit. | ||
| CM = 0: PWM low width = (CN) unit; PWM high width = 1 unit. | ||
| (Unit = one PWM clock cycle). | ||
| Note: Any write to CN will take effect in next PWM cycle. | ||
| [31:16] | CM | PWM Comparator Register |
| CM determines the PWM duty. | ||
| PWM frequency = PWMxy_CLK/(prescale+1)*(clock divider)/(CN+1); where xy, could be 01, 23 , depends on selected PWM channel. | ||
| Duty ratio = (CM+1)/(CN+1). | ||
| CM >= CN: PWM output is always high. | ||
| CM < CN: PWM low width = (CN-CM) unit; PWM high width = (CM+1) unit. | ||
| CM = 0: PWM low width = (CN) unit; PWM high width = 1 unit. | ||
| (Unit = one PWM clock cycle). | ||
| Note: Any write to CM will take effect in next PWM cycle. |
Definition at line 5668 of file Nano100Series.h.
| __IO uint32_t PWM_T::INTEN |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | TMIE0 | PWM Timer 0 Interrupt Enable |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [1] | TMIE1 | PWM Timer 1 Interrupt Enable |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [2] | TMIE2 | PWM Timer 2 Interrupt Enable |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [3] | TMIE3 | PWM Timer 3 Interrupt Enable |
| 0 = Disabled. | ||
| 1 = Enabled. |
Definition at line 5415 of file Nano100Series.h.
| __IO uint32_t PWM_T::INTSTS |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | TMINT0 | PWM Timer 0 Interrupt Flag |
| Flag is set by hardware when PWM0 down counter reaches zero, software can clear this bit by writing a one to it. | ||
| [1] | TMINT1 | PWM Timer 1 Interrupt Flag |
| Flag is set by hardware when PWM1 down counter reaches zero, software can clear this bit by writing a one to it. | ||
| [2] | TMINT2 | PWM Timer 2 Interrupt Flag |
| Flag is set by hardware when PWM2 down counter reaches zero, software can clear this bit by writing a one to it. | ||
| [3] | TMINT3 | PWM Timer 3 Interrupt Flag |
| Flag is set by hardware when PWM3 down counter reaches zero, software can clear this bit by writing a one to it. | ||
| [4] | Duty0Syncflag | Duty0 Synchronize Flag |
| 0 = Duty0 has been synchronized to ECLK domain. | ||
| 1 = Duty0 is synchronizing to ECLK domain. | ||
| Note: software should check this flag when writing duty0, if this flag is set, and user ignore this flag and change duty0, the corresponding CNR and CMR may be wrong for one duty cycle | ||
| [5] | Duty1Syncflag | Duty1 Synchronize Flag |
| 0 = Duty1 has been synchronized to ECLK domain. | ||
| 1 = Duty1 is synchronizing to ECLK domain. | ||
| Note: software should check this flag when writing duty1, if this flag is set, and user ignore this flag and change duty1, the corresponding CNR and CMR may be wrong for one duty cycle | ||
| [6] | Duty2Syncflag | Duty2 Synchronize Flag |
| 0 = Duty2 has been synchronized to ECLK domain. | ||
| 1 = Duty2 is synchronizing to ECLK domain. | ||
| Note: software should check this flag when writing duty2, if this flag is set, and user ignore this flag and change duty2, the corresponding CNR and CMR may be wrong for one duty cycle | ||
| [7] | Duty3Syncflag | Duty3 Synchronize Flag |
| 0 = Duty3 has been synchronized to ECLK domain. | ||
| 1 = Duty3 is synchronizing to ECLK domain. | ||
| Note: software should check this flag when writing duty0, if this flag is set, and user ignore this flag and change duty3, the corresponding CNR and CMR may be wrong for one duty cycle | ||
| [8] | PresSyncFlag | Prescale Synchronize Flag |
| 0 = Prescale has been synchronized to ECLK domain. | ||
| 1 = Prescale is synchronizing to ECLK domain. | ||
| Note: software should check this flag when writing Prescale, if this flag is set, and user ignore this flag and change Prescale, the Prescale may be wrong for one prescale cycle |
Definition at line 5453 of file Nano100Series.h.
| __IO uint32_t PWM_T::OE |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | CH0_OE | PWM CH0 Output Enable Register |
| 0 = PWM CH0 output to pin Disabled. | ||
| 1 = PWM CH0 output to pin Enabled. | ||
| Note: The corresponding GPIO pin also must be switched to PWM function (refer to GPx_MFP) | ||
| [1] | CH1_OE | PWM CH1 Output Enable Register |
| 0 = PWM CH1 output to pin Disabled. | ||
| 1 = PWM CH1 output to pin Enabled. | ||
| Note: The corresponding GPIO pin also must be switched to PWM function (refer to GPx_MFP) | ||
| [2] | CH2_OE | PWM CH2 Output Enable Register |
| 0 = PWM CH2 output to pin Disabled. | ||
| 1 = PWM CH2 output to pin Enabled. | ||
| Note: The corresponding GPIO pin also must be switched to PWM function (refer to GPx_MFP) | ||
| [3] | CH3_OE | PWM CH3 Output Enable Register |
| 0 = PWM CH3 output to pin Disabled. | ||
| 1 = PWM CH3 output to pin Enabled. | ||
| Note: The corresponding GPIO pin also must be switched to PWM function (refer to GPx_MFP) |
Definition at line 5479 of file Nano100Series.h.
| __I uint32_t PWM_T::PDMACH0 |
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | Captureddata7_0 | PDMACH0 |
| When CH01CASK is disabled, it is the capturing value(CFL0/CRL0) for channel 0 | ||
| When CH01CASK is enabled, It is the for the first byte of 32 bit capturing data for channel 0 | ||
| [15:8] | Captureddata15_8 | PDMACH0 |
| When CH01CASK is disabled, it is the capturing value(CFL0/CRL0) for channel 0 | ||
| When CH01CASK is enabled, It is the second byte of 32 bit capturing data for channel 0 | ||
| [23:16] | Captureddata23_16 | PDMACH0 |
| When CH01CASK is disabled, this byte is 0 | ||
| When CH01CASK is enabled, It is the third byte of 32 bit capturing data for channel 0 | ||
| [31:24] | Captureddata31_24 | PDMACH0 |
| When CH01CASK is disabled, this byte is 0 | ||
| When CH01CASK is enabled, It is the 4th byte of 32 bit capturing data for channel 0 |
Definition at line 6034 of file Nano100Series.h.
| __I uint32_t PWM_T::PDMACH2 |
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | Captureddata7_0 | PDMACH2 |
| When CH23CASK is disabled, it is the capturing value(CFL0/CRL0) for channel 2 | ||
| When CH23CASK is enabled, It is the for the first byte of 32 bit capturing data for channel 2 | ||
| [15:8] | Captureddata15_8 | PDMACH2 |
| When CH23CASK is disabled, it is the capturing value(CFL0/CRL0) for channel 2 | ||
| When CH23CASK is enabled, It is the second byte of 32 bit capturing data for channel 2 | ||
| [23:16] | Captureddata23_16 | PDMACH2 |
| When CH23CASK is disabled, this byte is 0 | ||
| When CH23CASK is enabled, It is the third byte of 32 bit capturing data for channel 2 | ||
| [31:24] | Captureddata31_24 | PDMACH2 |
| When CH23CASK is disabled, this byte is 0 | ||
| When CH23CASK is enabled, It is the 4th byte of 32 bit capturing data for channel 2 |
Definition at line 6056 of file Nano100Series.h.
| __IO uint32_t PWM_T::PRES |
| Bits | Field | Descriptions |
|---|---|---|
| [7:0] | CP01 | Clock Prescaler 0 For PWM Timer 0 & 1 |
| Clock input is divided by (CP01 + 1) before it is fed to the counter 0 & 1 | ||
| If CP01=0, then the prescaler 0 output clock will be stopped. | ||
| So PWM counter 0 and 1 will be stopped also. | ||
| [15:8] | CP23 | Clock Prescaler 2 For PWM Timer 2 & 3 |
| Clock input is divided by (CP23 + 1) before it is fed to the counter 2 & 3 | ||
| If CP23=0, then the prescaler 2 output clock will be stopped. | ||
| So PWM counter2 and 3 will be stopped also. | ||
| [23:16] | DZ01 | Dead Zone Interval Register For Pair Of CH0 And CH1 |
| These 8 bits determine dead zone length. | ||
| The unit time of dead zone length is received from clock selector 0. | ||
| [31:24] | DZ23 | Dead Zone Interval Register For Pair Of CH2 And CH3 |
| These 8 bits determine dead zone length. | ||
| The unit time of dead zone length is received from clock selector 2. |
Definition at line 5309 of file Nano100Series.h.
1.8.15