| Nano100AN Series BSP V3.02.002 The Board Support Package for Nano100AN Series

spi.h
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1 /****************************************************************************/
12 #ifndef __SPI_H__
13 #define __SPI_H__
14
15 #ifdef __cplusplus
16 extern "C"
17 {
18 #endif
19
20
34 #define SPI_MODE_0 (SPI_CTL_TX_NEG_Msk)
35 #define SPI_MODE_1 (SPI_CTL_RX_NEG_Msk)
36 #define SPI_MODE_2 (SPI_CTL_CLKP_Msk | SPI_CTL_RX_NEG_Msk)
37 #define SPI_MODE_3 (SPI_CTL_CLKP_Msk | SPI_CTL_TX_NEG_Msk)
39 #define SPI_SLAVE (SPI_CTL_SLAVE_Msk)
40 #define SPI_MASTER (0x0)
42 #define SPI_SS0 (0x1)
43 #define SPI_SS0_ACTIVE_HIGH (SPI_SSR_SS_LVL_Msk)
44 #define SPI_SS0_ACTIVE_LOW (0x0)
46 #define SPI_SS1 (0x2)
47 #define SPI_SS1_ACTIVE_HIGH (SPI_SSR_SS_LVL_Msk)
48 #define SPI_SS1_ACTIVE_LOW (0x0)
50 #define SPI_IE_MASK (0x01)
51 #define SPI_SSTA_INTEN_MASK (0x04)
53 /* end of group NANO100_SPI_EXPORTED_CONSTANTS */
54
55
66 #define SPI_ABORT_3WIRE_TRANSFER(spi) ( (spi)->SSR |= SPI_SSR_SLV_ABORT_Msk )
67
74 #define SPI_CLR_3WIRE_START_INT_FLAG(spi) ( (spi)->STATUS = SPI_STATUS_SLV_START_INTSTS_Msk )
75
82 #define SPI_CLR_UNIT_TRANS_INT_FLAG(spi) ( (spi)->STATUS = SPI_STATUS_INTSTS_Msk )
83
90 #define SPI_DISABLE_3WIRE_MODE(spi) ( (spi)->SSR &= ~SPI_SSR_NOSLVSEL_Msk )
91
98 #define SPI_ENABLE_3WIRE_MODE(spi) ( (spi)->SSR |= SPI_SSR_NOSLVSEL_Msk )
99
108 #define SPI_GET_RX_FIFO_EMPTY_FLAG(spi) ( ((spi)->STATUS & SPI_STATUS_RX_EMPTY_Msk) == SPI_STATUS_RX_EMPTY_Msk ? 1:0)
109
118 #define SPI_GET_TX_FIFO_EMPTY_FLAG(spi) ( ((spi)->STATUS & SPI_STATUS_TX_EMPTY_Msk) == SPI_STATUS_TX_EMPTY_Msk ? 1:0)
119
128 #define SPI_GET_TX_FIFO_FULL_FLAG(spi) ( ((spi)->STATUS & SPI_STATUS_TX_FULL_Msk) == SPI_STATUS_TX_FULL_Msk ? 1:0)
129
136 #define SPI_READ_RX0(spi) ( (spi)->RX0 )
137
143 #define SPI_READ_RX1(spi) ( (spi)->RX1 )
144
152 #define SPI_WRITE_TX0(spi, u32TxData) ( (spi)->TX0 = u32TxData )
153
161 #define SPI_WRITE_TX1(spi, u32TxData) ( (spi)->TX1 = u32TxData )
162
169 static __INLINE void SPI_SET_SS0_HIGH(SPI_T *spi)
170 {
171 spi->SSR &= ~SPI_SSR_AUTOSS_Msk;
172 spi->STATUS = SPI_STATUS_LTRIG_FLAG_Msk;
173 spi->SSR |= SPI_SSR_SS_LVL_Msk;
174 spi->SSR = (spi->SSR & ~SPI_SSR_SSR_Msk) | 0x1;
175 }
176
183 static __INLINE void SPI_SET_SS0_LOW(SPI_T *spi)
184 {
185 spi->SSR &= ~SPI_SSR_AUTOSS_Msk;
186 spi->STATUS = SPI_STATUS_LTRIG_FLAG_Msk;
187 spi->SSR &= ~SPI_SSR_SS_LVL_Msk;
188 spi->SSR = (spi->SSR & ~SPI_SSR_SSR_Msk) | 0x1;
189 }
190
197 static __INLINE void SPI_SET_SS1_HIGH(SPI_T *spi)
198 {
199 spi->SSR &= ~SPI_SSR_AUTOSS_Msk;
200 spi->STATUS = SPI_STATUS_LTRIG_FLAG_Msk;
201 spi->SSR |= SPI_SSR_SS_LVL_Msk;
202 spi->SSR = (spi->SSR & ~SPI_SSR_SSR_Msk) | 0x2;
203 }
204
211 static __INLINE void SPI_SET_SS1_LOW(SPI_T *spi)
212 {
213 spi->SSR &= ~SPI_SSR_AUTOSS_Msk;
214 spi->STATUS = SPI_STATUS_LTRIG_FLAG_Msk;
215 spi->SSR |= SPI_SSR_SS_LVL_Msk;
216 spi->SSR = (spi->SSR & ~SPI_SSR_SSR_Msk) | 0x2;
217 }
218
225 #define SPI_ENABLE_BYTE_REORDER(spi) ( (spi)->CTL |= SPI_CTL_REORDER_Msk )
226
233 #define SPI_DISABLE_BYTE_REORDER(spi) ( (spi)->CTL &= ~SPI_CTL_REORDER_Msk )
234
242 #define SPI_SET_SUSPEND_CYCLE(spi, u32SuspCycle) ( (spi)->CTL = ((spi)->CTL & ~SPI_CTL_SP_CYCLE_Msk) | (u32SuspCycle << SPI_CTL_SP_CYCLE_Pos) )
243
250 #define SPI_SET_LSB_FIRST(spi) ( (spi)->CTL |= SPI_CTL_LSB_Msk )
251
258 #define SPI_SET_MSB_FIRST(spi) ( (spi)->CTL &= ~SPI_CTL_LSB_Msk )
259
267 static __INLINE void SPI_SET_DATA_WIDTH(SPI_T *spi, uint32_t u32Width)
268 {
269 if(u32Width == 32)
270 u32Width = 0;
271
272 spi->CTL = (spi->CTL & ~SPI_CTL_TX_BIT_LEN_Msk) | (u32Width << SPI_CTL_TX_BIT_LEN_Pos);
273 }
274
283 #define SPI_IS_BUSY(spi) ( ((spi)->CTL & SPI_CTL_GO_BUSY_Msk) == SPI_CTL_GO_BUSY_Msk ? 1:0)
284
291 #define SPI_TRIGGER(spi) ( (spi)->CTL |= SPI_CTL_GO_BUSY_Msk )
292
299 #define SPI_TRIGGER_RX_PDMA(spi) ( (spi)->PDMA |= SPI_PDMA_RX_DMA_EN_Msk )
300
307 #define SPI_TRIGGER_TX_PDMA(spi) ( (spi)->PDMA |= SPI_PDMA_TX_DMA_EN_Msk )
308
315 #define SPI_ENABLE_2BIT_MODE(spi) ( (spi)->CTL |= SPI_CTL_TWOB_Msk )
316
323 #define SPI_DISABLE_2BIT_MODE(spi) ( (spi)->CTL &= ~SPI_CTL_TWOB_Msk )
324
331 #define SPI_GET_STATUS(spi) ( (spi)->STATUS )
332
333 uint32_t SPI_Open(SPI_T *spi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock);
334 void SPI_Close(SPI_T *spi);
335 void SPI_ClearRxFIFO(SPI_T *spi);
336 void SPI_ClearTxFIFO(SPI_T *spi);
337 void SPI_DisableAutoSS(SPI_T *spi);
338 void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel);
339 uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock);
340 void SPI_EnableFIFO(SPI_T *spi);
341 void SPI_DisableFIFO(SPI_T *spi);
342 uint32_t SPI_GetBusClock(SPI_T *spi);
343 void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask);
344 void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask);
345 void SPI_EnableWakeup(SPI_T *spi);
346 void SPI_DisableWakeup(SPI_T *spi); /* end of group NANO100_SPI_EXPORTED_FUNCTIONS */
348 /* end of group NANO100_SPI_Driver */
350 /* end of group NANO100_Device_Driver */
352
353 #ifdef __cplusplus
354 }
355 #endif
356
357 #endif //__SPI_H__
358
359 /*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
SPI_DisableAutoSS
void SPI_DisableAutoSS(SPI_T *spi)
Disable the automatic slave select function.
Definition: spi.c:105
SPI_EnableFIFO
void SPI_EnableFIFO(SPI_T *spi)
Enable FIFO mode with user-specified Tx FIFO threshold and Rx FIFO threshold configurations.
Definition: spi.c:156
SPI_CTL_TX_BIT_LEN_Pos
#define SPI_CTL_TX_BIT_LEN_Pos
Definition: Nano100Series.h:8241
SPI_SetBusClock
uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock)
Set the SPI bus clock. Only available in Master mode.
Definition: spi.c:128
SPI_SSR_SS_LVL_Msk
#define SPI_SSR_SS_LVL_Msk
Definition: Nano100Series.h:8308
SPI_T::SSR
__IO uint32_t SSR
Definition: Nano100Series.h:8086
SPI_SET_SS1_HIGH
static __INLINE void SPI_SET_SS1_HIGH(SPI_T *spi)
Disable automatic slave select function and set SPI_SS pin to high state.
Definition: spi.h:197
SPI_T::STATUS
__IO uint32_t STATUS
Definition: Nano100Series.h:8020
SPI_EnableInt
void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask)
Enable FIFO related interrupts specified by u32Mask parameter.
Definition: spi.c:197
SPI_ClearRxFIFO
void SPI_ClearRxFIFO(SPI_T *spi)
Clear Rx FIFO buffer.
Definition: spi.c:85
SPI_T
Definition: Nano100Series.h:7871
SPI_SET_SS0_HIGH
static __INLINE void SPI_SET_SS0_HIGH(SPI_T *spi)
Disable automatic slave select function and set SPI_SS pin to high state.
Definition: spi.h:169
SPI_SET_SS0_LOW
static __INLINE void SPI_SET_SS0_LOW(SPI_T *spi)
Disable automatic slave select function and set SPI_SS pin to low state.
Definition: spi.h:183
SPI_Close
void SPI_Close(SPI_T *spi)
Reset SPI module.
Definition: spi.c:60
SPI_T::CTL
__IO uint32_t CTL
Definition: Nano100Series.h:7984
SPI_SET_SS1_LOW
static __INLINE void SPI_SET_SS1_LOW(SPI_T *spi)
Disable automatic slave select function and set SPI_SS pin to low state.
Definition: spi.h:211
SPI_DisableInt
void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask)
Disable FIFO related interrupts specified by u32Mask parameter.
Definition: spi.c:216
SPI_GetBusClock
uint32_t SPI_GetBusClock(SPI_T *spi)
Get the actual frequency of SPI bus clock. Only available in Master mode.
Definition: spi.c:176
SPI_DisableFIFO
void SPI_DisableFIFO(SPI_T *spi)
Disable FIFO mode.
Definition: spi.c:166
SPI_ClearTxFIFO
void SPI_ClearTxFIFO(SPI_T *spi)
Clear Tx FIFO buffer.
Definition: spi.c:95
SPI_DisableWakeup
void SPI_DisableWakeup(SPI_T *spi)
Disable wake-up function.
Definition: spi.c:240
SPI_STATUS_LTRIG_FLAG_Msk
#define SPI_STATUS_LTRIG_FLAG_Msk
Definition: Nano100Series.h:8290
SPI_CTL_TX_BIT_LEN_Msk
#define SPI_CTL_TX_BIT_LEN_Msk
Definition: Nano100Series.h:8242
SPI_EnableAutoSS
void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel)
Enable the automatic slave select function. Only available in Master mode.
Definition: spi.c:117
SPI_Open
uint32_t SPI_Open(SPI_T *spi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock)
This function make SPI module be ready to transfer. By default, the SPI transfer sequence is MSB firs...
Definition: spi.c:41
SPI_SSR_AUTOSS_Msk
#define SPI_SSR_AUTOSS_Msk
Definition: Nano100Series.h:8311
SPI_SSR_SSR_Msk
#define SPI_SSR_SSR_Msk
Definition: Nano100Series.h:8305
SPI_SET_DATA_WIDTH
static __INLINE void SPI_SET_DATA_WIDTH(SPI_T *spi, uint32_t u32Width)
Set the data width of a SPI transaction.
Definition: spi.h:267
SPI_EnableWakeup
void SPI_EnableWakeup(SPI_T *spi)
Enable wake-up function.
Definition: spi.c:230