#include <Nano100Series.h>
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| __IO uint32_t | CTL |
| |
| __IO uint32_t | IER |
| |
| __IO uint32_t | ISR |
| |
@addtogroup WDT Watch Dog Timer Controller(WDT)
Memory Mapped Structure for WDT Controller
Definition at line 9914 of file Nano100Series.h.
◆ CTL
CTL
Offset: 0x00 Watchdog Timer Control Register
| Bits | Field | Descriptions |
| [0] | WTR | Clear Watchdog Timer |
| | This is a protected register. Please refer to open lock sequence to program it. |
| | Set this bit will clear the Watchdog timer. |
| | 0 = No effect. |
| | 1 = Reset the contents of the Watchdog timer. |
| | NOTE: This bit will auto clear after few clock cycle |
| [1] | WTRE | Watchdog Timer Reset Function Enable |
| | This is a protected register. Please refer to open lock sequence to program it. |
| | Setting this bit will enable the Watchdog timer reset function. |
| | 0 = Watchdog timer reset function Disabled. |
| | 1 = Watchdog timer reset function Enabled. |
| [2] | WTWKE | Watchdog Timer Wake-Up Function Enable |
| | This is a protected register. Please refer to open lock sequence to program it. |
| | 0 = Watchdog timer Wake-up CPU function Disabled. |
| | 1 = Wake-up function Enabled so that Watchdog timer time-out can wake up CPU from power-down mode. |
| [3] | WTE | Watchdog Timer Enable |
| | This is a protected register. Please refer to open lock sequence to program it. |
| | 0 = Watchdog timer Disabled (this action will reset the internal counter). |
| | 1 = Watchdog timer Enabled. |
| [6:4] | WTIS | Watchdog Timer Interval Selection |
| | This is a protected register. Please refer to open lock sequence to program it. |
| | These three bits select the time-out interval for the Watchdog timer. |
| | This count is free running counter. |
| | Please refer to TRM Table 5.20-1 Watchdog Time-out Interval Selection |
Definition at line 9950 of file Nano100Series.h.
◆ IER
IER
Offset: 0x04 Watchdog Timer Interrupt Enable Register
| Bits | Field | Descriptions |
| [0] | IE | Watchdog Timer Interrupt Enable |
| | 0 = Watchdog timer interrupt Disabled. |
| | 1 = Watchdog timer interrupt Enabled. |
Definition at line 9963 of file Nano100Series.h.
◆ ISR
ISR
Offset: 0x08 Watchdog Timer Interrupt Status Register
| Bits | Field | Descriptions |
| [0] | IS | Watchdog Timer Interrupt Status |
| | If the Watchdog timer interrupt is enabled, then the hardware will set this bit to indicate that the Watchdog timer interrupt has occurred. |
| | If the Watchdog timer interrupt is not enabled, then this bit indicates that a time-out period has elapsed. |
| | 0 = Watchdog timer interrupt did not occur. |
| | 1 = Watchdog timer interrupt occurs. |
| | Note: This bit is read only, but can be cleared by writing "1" to it. |
| [1] | RST_IS | Watchdog Timer Reset Status |
| | When the Watchdog timer initiates a reset, the hardware will set this bit. |
| | This flag can be read by software to determine the source of reset. |
| | Software is responsible to clear it manually by writing "1" to it. |
| | If WTRE is disabled, then the Watchdog timer has no effect on this bit. |
| | 0 = Watchdog timer reset did not occur. |
| | 1 = Watchdog timer reset occurs. |
| | Note: This bit is read only, but can be cleared by writing "1" to it. |
| [2] | WAKE_IS | Watchdog Timer Wake-Up Status |
| | If Watchdog timer causes system to wake up from power-down mode, this bit will be set to high. |
| | It must be cleared by software with a write "1" to this bit. |
| | 0 = Watchdog timer does not cause system wake-up. |
| | 1 = Wake system up from power-down mode by Watchdog time-out. |
| | Note1: When system in power-down mode and watchdog time-out, hardware will set WDT_WAKE_IS and WDT_IS. |
| | Note2: After one engine clock, this bit can be cleared by writing "1" to it |
Definition at line 9994 of file Nano100Series.h.
The documentation for this struct was generated from the following file:
- C:/Users/yachen/workzone/bsp/nano100absp/Library/Device/Nuvoton/Nano100Series/Include/Nano100Series.h