33 #define ADC_CH_0_MASK (1UL << 0) 34 #define ADC_CH_1_MASK (1UL << 1) 35 #define ADC_CH_2_MASK (1UL << 2) 36 #define ADC_CH_3_MASK (1UL << 3) 37 #define ADC_CH_4_MASK (1UL << 4) 38 #define ADC_CH_5_MASK (1UL << 5) 39 #define ADC_CH_6_MASK (1UL << 6) 40 #define ADC_CH_7_MASK (1UL << 7) 41 #define ADC_CH_10_MASK (1UL << 10) 42 #define ADC_CH10_VTEMP (0UL) 43 #define ADC_CH10_AVDD (2 << ADC_CHEN_CH10SEL_Pos) 44 #define ADC_CH10_AVSS (3 << ADC_CHEN_CH10SEL_Pos) 45 #define ADC_CHEN_Msk (0x7FF) 46 #define ADC_PDMADATA_AD_PDMA_Msk (0xFFF) 47 #define ADC_CMP_LESS_THAN (0UL) 48 #define ADC_CMP_GREATER_OR_EQUAL_TO (ADC_CMPR0_CMPCOND_Msk) 49 #define ADC_TRIGGER_BY_EXT_PIN (1UL) 50 #define ADC_LOW_LEVEL_TRIGGER (0UL << ADC_CR_TRGCOND_Pos) 51 #define ADC_HIGH_LEVEL_TRIGGER (1UL << ADC_CR_TRGCOND_Pos) 52 #define ADC_FALLING_EDGE_TRIGGER (2UL << ADC_CR_TRGCOND_Pos) 53 #define ADC_RISING_EDGE_TRIGGER (3UL << ADC_CR_TRGCOND_Pos) 54 #define ADC_ADF_INT (ADC_SR_ADF_Msk) 55 #define ADC_CMP0_INT (ADC_SR_CMPF0_Msk) 56 #define ADC_CMP1_INT (ADC_SR_CMPF1_Msk) 57 #define ADC_OPERATION_MODE_SINGLE (0UL << ADC_CR_ADMD_Pos) 58 #define ADC_OPERATION_MODE_SINGLE_CYCLE (2UL << ADC_CR_ADMD_Pos) 59 #define ADC_OPERATION_MODE_CONTINUOUS (3UL << ADC_CR_ADMD_Pos) 60 #define ADC_REFSEL_POWER (0UL << ADC_CR_REFSEL_Pos) 61 #define ADC_REFSEL_INT_VREF (1UL << ADC_CR_REFSEL_Pos) 62 #define ADC_REFSEL_VREF (2UL << ADC_CR_REFSEL_Pos) 63 #define ADC_REFSEL_CH7 (3UL << ADC_CR_REFSEL_Pos) 79 #define ADC_GET_CONVERSION_DATA(adc, u32ChNum) (ADC->RESULT[u32ChNum] & ADC_RESULT_RSLT_Msk) 91 #define ADC_CONFIG_CH10(adc, u32Source) (ADC->CHEN = ((adc)->CHEN & ~ADC_CHEN_CHEN10_Msk) | (u32Source)) 103 #define ADC_GET_INT_FLAG(adc, u32Mask) (ADC->SR & (u32Mask)) 115 #define ADC_CLR_INT_FLAG(adc, u32Mask) (ADC->SR = (ADC->SR & ~(ADC_SR_ADF_Msk | \ 117 ADC_SR_CMPF1_Msk)) | (u32Mask)) 127 #define ADC_IS_BUSY(adc) (ADC->SR & ADC_SR_BUSY_Msk ? 1 : 0) 138 #define ADC_IS_DATA_OVERRUN(adc, u32ChNum) ((ADC->SR & ((1 << u32ChNum) << ADC_SR_OVERRUN_Pos)) ? 1 : 0) 149 #define ADC_IS_DATA_VALID(adc, u32ChNum) ((ADC->SR & ((1 << u32ChNum) << ADC_SR_VALID_Pos)) ? 1 : 0) 157 #define ADC_POWER_DOWN(adc) (ADC->CR &= ~ADC_CR_ADEN_Msk) 165 #define ADC_POWER_ON(adc) (ADC->CR |= ADC_CR_ADEN_Msk) 182 #define ADC_ENABLE_CMP0(adc, \ 186 u32MatchCount) (ADC->CMPR0 = ((u32ChNum) << ADC_CMPR0_CMPCH_Pos) | \ 188 ((u32Data) << ADC_CMPR0_CMPD_Pos) | \ 189 (((u32MatchCount) - 1) << ADC_CMPR0_CMPMATCNT_Pos) |\ 198 #define ADC_DISABLE_CMP0(adc) (ADC->CMPR0 = 0) 215 #define ADC_ENABLE_CMP1(adc, \ 219 u32MatchCount) (ADC->CMPR1 = ((u32ChNum) << ADC_CMPR1_CMPCH_Pos) | \ 221 ((u32Data) << ADC_CMPR1_CMPD_Pos) | \ 222 ((u32MatchCount - 1) << ADC_CMPR1_CMPMATCNT_Pos) |\ 231 #define ADC_DISABLE_CMP1(adc) (ADC->CMPR1 = 0) 240 #define ADC_SET_INPUT_CHANNEL(adc, u32Mask) (ADC->CHEN = (ADC->CHEN & ~ADC_CHEN_Msk) | (u32Mask)) 248 #define ADC_START_CONV(adc) (ADC->CR |= ADC_CR_ADST_Msk) 256 #define ADC_STOP_CONV(adc) (ADC->CR &= ~ADC_CR_ADST_Msk) 270 #define ADC_SET_REF_VOLTAGE(adc, u32Ref) (ADC->CR = (ADC->CR & ~ADC_CR_REFSEL_Msk) | u32Ref) 278 #define ADC_ENABLE_PDMA(adc) (ADC->CR |= ADC_CR_PTEN_Msk) 286 #define ADC_DISABLE_PDMA(adc) (ADC->CR &= ~ADC_CR_PTEN_Msk) 294 #define ADC_GET_PDMA_DATA(adc) (ADC->PDMA & ADC_PDMADATA_AD_PDMA_Msk) 297 uint32_t u32InputMode,
307 uint32_t u32PDMACnt);
311 uint32_t u32SampleTime);
void ADC_EnableTimerTrigger(ADC_T *adc, uint32_t u32Source, uint32_t u32PDMACnt)
Config and enable timer trigger.
void ADC_Close(ADC_T *adc)
Disable ADC module.
void ADC_Open(ADC_T *adc, uint32_t u32InputMode, uint32_t u32OpMode, uint32_t u32ChMask)
This API configures ADC module to be ready for convert the input from selected channel.
void ADC_DisableHWTrigger(ADC_T *adc)
Disable hardware trigger ADC function.
void ADC_DisableTimerTrigger(ADC_T *adc)
Disable timer trigger ADC function.
void ADC_EnableInt(ADC_T *adc, uint32_t u32Mask)
Enable the interrupt(s) selected by u32Mask parameter.
void ADC_EnableHWTrigger(ADC_T *adc, uint32_t u32Source, uint32_t u32Param)
Configure the hardware trigger condition and enable hardware trigger.
void ADC_SetExtraSampleTime(ADC_T *adc, uint32_t u32ChNum, uint32_t u32SampleTime)
Configure the extend sampling counter.
void ADC_DisableInt(ADC_T *adc, uint32_t u32Mask)
Disable the interrupt(s) selected by u32Mask parameter.