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Nano100AN Series BSP
V3.02.002
The Board Support Package for Nano100AN Series
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#include <Nano100Series.h>
Data Fields | |
| __IO uint32_t | ISPCON |
| __IO uint32_t | ISPADR |
| __IO uint32_t | ISPDAT |
| __IO uint32_t | ISPCMD |
| __IO uint32_t | ISPTRG |
| __I uint32_t | DFBADR |
| __IO uint32_t | ISPSTA |
@addtogroup FMC Flash Memory Controller(FMC) Memory Mapped Structure for FMC Controller
Definition at line 2147 of file Nano100Series.h.
| __I uint32_t FMC_T::DFBADR |
| Bits | Field | Descriptions |
|---|---|---|
| [31:0] | DFBA | Data Flash Base Address |
| This register indicates data flash start address. It is a read only register. | ||
| The data flash start address is defined by user. | ||
| Since on chip flash erase unit is 512 bytes, it is mandatory to keep bit 8-0 as 0. |
Definition at line 2283 of file Nano100Series.h.
| __IO uint32_t FMC_T::ISPADR |
| Bits | Field | Descriptions |
|---|---|---|
| [31:0] | ISPADR | ISP Address |
| This chip supports word program only. ISPADR[1:0] must be kept 00b for ISP operation. |
Definition at line 2221 of file Nano100Series.h.
| __IO uint32_t FMC_T::ISPCMD |
| Bits | Field | Descriptions |
|---|---|---|
| [3:0] | FCTRL | ISP Command |
| The ISP command table is shown as follows | ||
| Read (FOEN = 0, FCEN = 0, FCRTL = 0000) | ||
| Program (FOEN = 1, FCEN = 0, FCRTL = 0001) | ||
| Page Erase (FOEN = 1, FCEN = 0, FCRTL = 0010) | ||
| Read CID (FOEN = 0, FCEN = 0, FCRTL = 1011) | ||
| Read DID (FOEN = 0, FCEN = 0, FCRTL = 1100) | ||
| [4] | FCEN | ISP Command |
| The ISP command table is shown as above. | ||
| [5] | FOEN | ISP Command |
| The ISP command table is shown as above. |
Definition at line 2255 of file Nano100Series.h.
| __IO uint32_t FMC_T::ISPCON |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | ISPEN | ISP Enable (Write-Protection Bit) |
| ISP function enable bit. Set this bit to enable ISP function. | ||
| 0 = ISP function Disabled. | ||
| 1 = ISP function Enabled. | ||
| [1] | BS | Boot Select (Write-Protection Bit) |
| Set/clear this bit to select next booting from LDROM/APROM, respectively. | ||
| This bit also functions as chip booting status flag, which can be used to check where chip booted from. | ||
| This bit is initiated with the inversed value of CBS in Config0 after power-on reset; It keeps the same value at other reset. | ||
| 0 = boot from APROM. | ||
| 1 = boot from LDROM. | ||
| [3] | APUEN | APROM Update Enable Control (Write Protect) |
| 0 = APROM cannot be updated when the chip runs in APROM. | ||
| 1 = APROM can be updated when the chip runs in APROM. | ||
| [4] | CFGUEN | Config-Bits Update By ISP (Write Protect) Enable Control |
| 0 = ISP Disabled to update config-bits. | ||
| 1 = ISP Enabled to update config-bits. | ||
| Note: This bit is fixed to 0 in Secure mode. | ||
| [5] | LDUEN | LDROM Update Enable Control (Write Protect) |
| LDROM update enable bit. | ||
| 0 = LDROM cannot be updated. | ||
| 1 = LDROM can be updated. | ||
| Note: This bit is fixed to 0 in Secure mode. | ||
| [6] | ISPFF | ISP Fail Flag (Write-Protection Bit) |
| This bit is set by hardware when a triggered ISP meets any of the following conditions: | ||
| (1) APROM writes to itself | ||
| (2) LDROM writes to itself | ||
| (3) CONFIG is erased/programmed if CFGUEN is set to 0 | ||
| (4) Destination address is illegal, such as over an available range | ||
| Write 1 to clear. | ||
| [7] | SWRST | Software Reset |
| Writing 1 to this bit to start software reset. | ||
| It is cleared by hardware after reset is finished. | ||
| [10:8] | PT | Flash Program Time (Write-Protection Bits) |
| 000 = 40us. | ||
| 001 = 45us. | ||
| 010 = 50us. | ||
| 011 = 55us. | ||
| 100 = 20us. | ||
| 101 = 25us. | ||
| 110 = 30us. | ||
| 111 = 35us. | ||
| [14:12] | ET | Flash Erase Time (Write-Protection Bits) |
| 000 = 20ms. | ||
| 001 = 25ms. | ||
| 010 = 30ms. | ||
| 011 = 35ms. | ||
| 100 = 3ms. | ||
| 101 = 5ms. | ||
| 110 = 10ms. | ||
| 111 = 15ms. |
Definition at line 2209 of file Nano100Series.h.
| __IO uint32_t FMC_T::ISPDAT |
| Bits | Field | Descriptions |
|---|---|---|
| [31:0] | ISPDAT | ISP Data |
| Write data to this register before ISP program operation | ||
| Read data from this register after ISP read operation |
Definition at line 2234 of file Nano100Series.h.
| __IO uint32_t FMC_T::ISPSTA |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | ISPBUSY | ISP BUSY |
| 0 = ISP operation is finished. | ||
| 1 = ISP operation is busy. | ||
| Read Only | ||
| [2:1] | CBS | Config Boot Selection Status |
| 00 = Reserved. | ||
| 01 = Chip boot from LDROM; APROM is unreadable. | ||
| 10 = Reserved. | ||
| 11 = Chip boot from APROM; LDROM is unreadable. | ||
| [6] | ISPFF | ISP Fail Flag |
| This bit is set by hardware when a triggered ISP meets any of the following conditions: | ||
| (1) APROM writes to itself. | ||
| (2) LDROM writes to itself. | ||
| (3) CONFIG is erased/programmed when the MCU is running in APROM. | ||
| (4) Destination address is illegal, such as over an available range. | ||
| Write 1 to clear. |
Definition at line 2314 of file Nano100Series.h.
| __IO uint32_t FMC_T::ISPTRG |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | ISPGO | ISP Start Trigger |
| Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished. | ||
| 0 = ISP operation is finished. | ||
| 1 = ISP is on going. |
Definition at line 2269 of file Nano100Series.h.
1.8.15