Nano100AN Series BSP  V3.02.002
The Board Support Package for Nano100AN Series
Data Fields
SYS_T Struct Reference

#include <Nano100Series.h>

Data Fields

__I uint32_t PDID
 
__IO uint32_t RST_SRC
 
__IO uint32_t IPRST_CTL1
 
__IO uint32_t IPRST_CTL2
 
__IO uint32_t CPR
 
__IO uint32_t TEMPCTL
 
__IO uint32_t PA_L_MFP
 
__IO uint32_t PA_H_MFP
 
__IO uint32_t PB_L_MFP
 
__IO uint32_t PB_H_MFP
 
__IO uint32_t PC_L_MFP
 
__IO uint32_t PC_H_MFP
 
__IO uint32_t PD_L_MFP
 
__IO uint32_t PD_H_MFP
 
__IO uint32_t PE_L_MFP
 
__IO uint32_t PE_H_MFP
 
__IO uint32_t PF_L_MFP
 
__IO uint32_t PORCTL
 
__IO uint32_t BODCTL
 
__IO uint32_t BODSTS
 
__IO uint32_t VREFCTL
 
__IO uint32_t IRCTRIMCTL
 
__IO uint32_t IRCTRIMIEN
 
__IO uint32_t IRCTRIMINT
 
__IO uint32_t RegLockAddr
 

Detailed Description

@addtogroup GCR System Global Control Registers(GCR)
Memory Mapped Structure for GCR Controller

Definition at line 2390 of file Nano100Series.h.

Field Documentation

◆ BODCTL

__IO uint32_t SYS_T::BODCTL

BODCTL

Offset: 0x64 Brown-out Detector Control Register

Bits Field Descriptions
[0] BOD17_EN Brown-Out Detector 1.7V Function Enable
This is a protected register. Please refer to open lock sequence to program it.
The default value is set by flash controller user configuration register config0 bit[20:19]
Users can disable BOD17_EN but it takes effective (disabled) only in Power-down mode.
Once existing Power-down mode, BOD17 will be enabled by HW automatically.
When CPU reads this bit, CPU will read whether BOD17 function enabled or not.
In other words,CPU will always read high.
0= Brown-out Detector 1.7V function Disabled.
1= Brown-out Detector 1.7V function Enabled.
[1] BOD20_EN Brown-Out Detector 2.0 V Function Enable
This is a protected register. Please refer to open lock sequence to program it.
0= Brown-out Detector 2.0 V function Disabled.
1= Brown-out Detector 2.0 V function Enabled.
BOD20_EN is default on.
If SW disables it, Brown-out Detector 2.0 V function is not disabled until chip enters power-down mode.
If system is not in power-down mode, BOD20_EN will be enabled by hardware automatically.
[2] BOD25_EN Brown-Out Detector 2.5 V Function Enable
This is a protected register. Please refer to open lock sequence to program it.
0= Brown-out Detector 2.5 V function Disabled.
1= Brown-out Detector 2.5 V function Enabled.
[4] BOD17_RST_EN BOD 1.7 V Reset Enable
This is a protected register. Please refer to open lock sequence to program it.
0 = Reset does not issue when BOD17 occurs.
1 = Reset issues when BOD17 occurs.
The default value is set by flash controller user configuration register config0 bit[20:19]
BOD17_RST_EN can be controlled (enable or disable) only when BOD17_EN is high.
[5] BOD20_RST_EN BOD 2.0 V Reset Enable
This is a protected register. Please refer to open lock sequence to program it.
0 = Reset does not issue when BOD20 occurs.
1 = Reset issues when BOD20 occurs.
The default value is set by flash controller user configuration register config0 bit[20:19]
[6] BOD25_RST_EN BOD 2.5 V Reset Enable
This is a protected register. Please refer to open lock sequence to program it.
0 = Reset does not issue when BOD25 occurs.
1 = Reset issues when BOD25 occurs.
The default value is set by flash controller user configuration register config0 bit[20:19]
[8] BOD17_INT_EN BOD 1.7 V Interrupt Enable
This is a protected register. Please refer to open lock sequence to program it.
0 = Interrupt does not issue when BOD17 occurs.
1 = Interrupt issues when BOD17 occurs.
[9] BOD20_INT_EN BOD 2.0 V Interrupt Enable
This is a protected register. Please refer to open lock sequence to program it.
0 = Interrupt does not issue when BOD20 occurs.
1 = Interrupt issues when BOD20 occurs.
[10] BOD25_INT_EN BOD 2.5 V Interrupt Enable
This is a protected register. Please refer to open lock sequence to program it.
0 = Interrupt does not issue when BOD25 occurs.
1 = Interrupt issues when BOD25 occurs.

Definition at line 3127 of file Nano100Series.h.

◆ BODSTS

__IO uint32_t SYS_T::BODSTS

BODSTS

Offset: 0x68 Brown-out Detector Status Register

Bits Field Descriptions
[0] BOD_INT Brown-Out Detector Interrupt Status
0 = Brown-out Detector does not detect any voltage drift at VDD down through or up through the target detected voltage after interrupt is enabled.
1 = When Brown-out Detector detects the VDD is dropped down through the target detected voltage or the VDD is raised up through the target detected voltage and Brown-out interrupt is enabled, this bit will be set to 1.
This bit is cleared by writing 1 to itself.
[1] BOD17_OUT Brown-Out Detector Output Status
0 = Brown-out Detector output status is 0.
It means the detected voltage is higher than target detected voltage setting.
1 = Brown-out Detector output status is 1.
It means the detected voltage is lower than target detected voltage setting (1.7V).
If the BOD17_EN is "0", BOD17 function disabled, this bit always responds "0".
[2] BOD20_OUT Brown-Out Detector Output Status
0 = Brown-out Detector output status is 0.
It means the detected voltage is higher than target detected voltage setting.
1 = Brown-out Detector output status is 1.
It means the detected voltage is lower than target detected voltage setting (2.0 V).
If the BOD20_EN is "0", BOD20 function disabled, this bit always responds "0".
[3] BOD25_OUT Brown-Out Detector Output Status
0 = Brown-out Detector output status is 0.
It means the detected voltage is higher than target detected voltage setting.
1 = Brown-out Detector output status is 1.
It means the detected voltage is lower than target detected voltage setting (2.5 V).
If the BOD25_EN is "0", BOD25 function disabled, this bit always responds "0".

Definition at line 3159 of file Nano100Series.h.

◆ CPR

__IO uint32_t SYS_T::CPR

CPR

Offset: 0x10 Chip Performance Register

Bits Field Descriptions
[0] HPE High Performance Enable
This bit is used to control chip operation performance.
When this bit set, internal RAM and GPIO access is working with zero wait state, Flash controller will predict next address more efficiently
0 = Chip operation at normal mode.
1= Chip operation at high performance mode.

Definition at line 2565 of file Nano100Series.h.

◆ IPRST_CTL1

__IO uint32_t SYS_T::IPRST_CTL1

IPRST_CTL1

Offset: 0x08 IP Reset Control Resister 1

Bits Field Descriptions
[0] CHIP_RST CHIP One Shot Reset
This is a protected register. Please refer to open lock sequence to program it.
Setting this bit will reset the whole chip, including CPU kernel and all peripherals like power-on reset and this bit will automatically return to "0" after the 2 clock cycles.
The chip setting from flash will be also reloaded when chip one shot reset.
0= Normal.
1= Reset CHIP.
NOTE: In the following condition, chip setting from flash will be reloaded
The Power-On Reset
Brown-Out-Detected Reset
The low level on the /RESET pin
Set IPRST_CTL1[CHIP_RST]
[1] CPU_RST CPU Kernel One Shot Reset
This is a protected register. Please refer to open lock sequence to program it.
Setting this bit will only reset the CPU kernel and Flash Memory Controller(FMC), and this bit will automatically return to "0" after the 2 clock cycles
0= Normal.
1= Reset CPU.
[2] DMA_RST DMA Controller Reset
This is a protected register. Please refer to open lock sequence to program it.
Set this bit "1" will generate a reset signal to the DMA.
SW needs to set this bit to low to release reset signal.
0= Normal operation.
1= DMA IP reset.
[3] EBI_RST EBI Controller Reset
This is a protected register. Please refer to open lock sequence to program it.
Set this bit "1" will generate a reset signal to the EBI.
SW needs to set this bit to low to release reset signal.
0= Normal operation.
1= EBI IP reset.

Definition at line 2483 of file Nano100Series.h.

◆ IPRST_CTL2

__IO uint32_t SYS_T::IPRST_CTL2

IPRST_CTL2

Offset: 0x0C IP Reset Control Resister 2

Bits Field Descriptions
[1] GPIO_RST GPIO Controller Reset
0= GPIO normal operation.
1= GPIO reset.
[2] TMR0_RST Timer0 Controller Reset
0= Timer0 normal operation.
1= Timer0 reset.
[3] TMR1_RST Timer1 Controller Reset
0= Timer1 normal operation.
1= Timer1 block reset.
[4] TMR2_RST Timer2 Controller Reset
0= Timer2 normal operation.
1= Timer2 block reset.
[5] TMR3_RST Timer3 Controller Reset
0= Timer3 normal operation.
1= Timer3 block reset.
[8] I2C0_RST I2C0 Controller Reset
0= I2C0 normal operation.
1= I2C0 block reset.
[9] I2C1_RST I2C1 Controller Reset
0= I2C1 block normal operation.
1= I2C1 block reset.
[12] SPI0_RST SPI0 Controller Reset
0= SPI0 block normal operation.
1= SPI0 block reset.
[13] SPI1_RST SPI1 Controller Reset
0= SPI1 normal operation.
1= SPI1 block reset.
[14] SPI2_RST SPI2 Controller Reset
0= SPI2 normal operation.
1= SPI2 block reset.
[16] UART0_RST UART0 Controller Reset
0= UART0 normal operation.
1= UART0 block reset.
[17] UART1_RST UART1 Controller Reset
0= UART1 normal operation.
1= UART1 block reset.
[20] PWM0_RST PWM0 Controller Reset
0= PWM0 block normal operation.
1= PWM0 block reset.
[21] PWM1_RST PWM1 Controller Reset
0= PWM1 block normal operation.
1= PWM1 block reset.
[27] USBD_RST USB Device Controller Reset
0= USB block normal operation.
1= USB block reset.
[28] ADC_RST ADC Controller Reset
0= ADC block normal operation.
1= ADC block reset.
[29] I2S_RST I2S Controller Reset
0= I2S block normal operation.
1= I2S block reset.
[30] SC0_RST SC 0 Controller Reset
0= SC block normal operation.
1= SC block reset.
[31] SC1_RST SC 1 Controller Reset
0= SC block normal operation.
1= SC block reset.

Definition at line 2550 of file Nano100Series.h.

◆ IRCTRIMCTL

__IO uint32_t SYS_T::IRCTRIMCTL

IRCTRIMCTL

Offset: 0x80 HIRC Trim Control Register

Bits Field Descriptions
[1:0] TRIM_SEL Trim Frequency Selection
This field indicates the target frequency of HIRC auto trim.
If no any target frequency is selected (TRIM_SEL is 00), the HIRC auto trim function is disabled.
During auto trim operation, if 32.768 kHz clock error detected or trim retry limitation count reached, this field will be cleared to 00 automatically.
00 = Disable HIRC auto trim function.
01 = Enable HIRC auto trim function and trim HIRC to 11.0592 MHz.
10 = Enable HIRC auto trim function and trim HIRC to 12 MHz.
11 = Enable HIRC auto trim function and trim HIRC to 12.288 MHz.
[5:4] TRIM_LOOP Trim Calculation Loop
This field defines that trim value calculation is based on how many 32.768 kHz clock.
For example, if TRIM_LOOP is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 32.768 kHz clock.
00 = 4 32.768 kHz clock.
01 = 8 32.768 kHz clock.
10 = 16 32.768 kHz clock.
11 = 32 32.768 kHz clock.
[7:6] TRIM_RETRY_CNT Trim Value Update Limitation Count
This field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked.
Once the HIRC locked, the internal trim value update counter will be reset.
If the trim value update counter reached this limitation value and frequency of HIRC still doesn't lock, the auto trim operation will be disabled and TRIM_SEL will be cleared to 00.
00 = Trim retry count limitation is 64.
01 = Trim retry count limitation is 128.
10 = Trim retry count limitation is 256.
11 = Trim retry count limitation is 512.

Definition at line 3234 of file Nano100Series.h.

◆ IRCTRIMIEN

__IO uint32_t SYS_T::IRCTRIMIEN

IRCTRIMIEN

Offset: 0x84 HIRC Trim Interrupt Enable Register

Bits Field Descriptions
[1] TRIM_FAIL_IEN Trim Failure Interrupt Enable
This bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by TRIM_SEL.
If this bit is high and TRIM_FAIL_INT is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached.
0 = TRIM_FAIL_INT status Disabled to trigger an interrupt to CPU.
1 = TRIM_FAIL_INT status Enabled to trigger an interrupt to CPU.
[2] 32K_ERR_IEN 32.768 KHz Clock Error Interrupt Enable
This bit controls if CPU would get an interrupt while 32.768 kHz clock is inaccuracy during auto trim operation.
If this bit is high, and 32K_ERR_INT is set during auto trim operation, an interrupt will be triggered to notify the 32.768 kHz clock frequency is inaccuracy.
0 = 2K_ERR_INT status Disabled 3to trigger an interrupt to CPU.
1 = 32K_ERR_INT status Enabled to trigger an interrupt to CPU.

Definition at line 3254 of file Nano100Series.h.

◆ IRCTRIMINT

__IO uint32_t SYS_T::IRCTRIMINT

IRCTRIMINT

Offset: 0x88 HIRC Trim Interrupt Status Register

Bits Field Descriptions
[0] FREQ_LOCK HIRC Frequency Lock Status
This bit indicates the HIRC frequency lock.
This is a status bit and doesn't trigger any interrupt.
[1] TRIM_FAIL_INT Trim Failure Interrupt Status
This bit indicates that HIRC trim value update limitation count reached and HIRC clock frequency still doesn't lock.
Once this bit is set, the auto trim operation stopped and TRIM_SEL will be cleared to 00 by hardware automatically.
If this bit is set and TRIM_FAIL_IEN is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached.
Write 1 to clear this to zero.
0 = Trim value update limitation count doesn't reach.
1 = Trim value update limitation count reached and HIRC frequency still doesn't lock.
[2] 32K_ERR_INT 32.768 KHz Clock Error Interrupt Status
This bit indicates that 32.768 kHz clock frequency is inaccuracy.
Once this bit is set, the auto trim operation stopped and TRIM_SEL will be cleared to 00 by hardware automatically.
If this bit is set and 32K_ERR_IEN is high, an interrupt will be triggered to notify the 32.768 kHz clock frequency is inaccuracy.
Write 1 to clear this to zero.
0 = 32.768 kHz clock frequency is accuracy.
1 = 32.768 kHz clock frequency is inaccuracy.

Definition at line 3281 of file Nano100Series.h.

◆ PA_H_MFP

__IO uint32_t SYS_T::PA_H_MFP

PA_H_MFP

Offset: 0x34 Port A high byte multiple function control register

Bits Field Descriptions
[2:0] PA8_MFP PA.8 Pin Function Selection
001 = I2C0 SDA
011 = SmartCard0 clock
100 = SPI2 1st slave select pin
Others = GPIOA[8]
[6:4] PA9_MFP PA.9 Pin Function Selection
001 = I2C0 SCL
011 = SmartCard0 DATA
100 = SPI2 SCLK
Others = GPIOA[9]
[10:8] PA10_MFP PA.10 Pin Function Selection
001 = I2C1 SDA
010 = EBI nWR
011 = SmartCard0 Power
100 = SPI2 MISO0
Others = GPIOA[10]
[14:12] PA11_MFP PA.11 Pin Function Selection
001 = I2C1 SCL
010 = EBI nRE
011 = SmartCard0 RST
100 = SPI2 MOSI0
Others = GPIOA[11]
[18:16] PA12_MFP PA.12 Pin Function Selection
001 = PWM0 Channel 0
010 = EBI AD[13]
011 = Timer0 capture event
101 = I2C0 SDA
Others = GPIOA[12]
[22:20] PA13_MFP PA.13 Pin Function Selection
001 = PWM0 Channel 1
010 = EBI AD[14]
011 = Timer1 capture event
101 = I2C0 SCL
Others = GPIOA[13]
[26:24] PA14_MFP PA.14 Pin Function Selection
001 = PWM0 Channel 2
010 = EBI AD[15]
011 = Timer2 capture event
110 = UART0 RX
Others = GPIOA[14]
[30:28] PA15_MFP PA.15 Pin Function Selection
001 = PWM0 Channel 3
010 = I2S MCLK
011 = Timer3 capture event
110 = UART0 TX
Others = GPIOA[15]

Definition at line 2693 of file Nano100Series.h.

◆ PA_L_MFP

__IO uint32_t SYS_T::PA_L_MFP

PA_L_MFP

Offset: 0x30 Port A low byte multiple function control register

Bits Field Descriptions
[2:0] PA0_MFP PA.0 Pin Function Selection
001 = ADC input channel 0
Others = GPIOA[0]
[6:4] PA1_MFP PA.1 Pin Function Selection
001 = ADC input channel 1
010 = EBI AD[12]
Others = GPIOA[1]
[10:8] PA2_MFP PA.2 Pin Function Selection
001 = ADC input channel 2
010 = EBI AD[11]
101 = UART1_RXD
Others = GPIOA[2]
[14:12] PA3_MFP PA.3 Pin Function Selection
001 = ADC input channel 3
010 = EBI AD[10]
101 = UART1_TXD
Others = GPIOA[3]
[18:16] PA4_MFP PA.4 Pin Function Selection
001 = ADC input channel 4
010 = EBI AD[9]
101 = I2C0 SDA
Others = GPIOA[4]
[22:20] PA5_MFP PA.5 Pin Function Selection
001 = ADC input channel 5
010 = EBI AD[8]
101 = I2C0 SCL
Others = GPIOA[5]
[26:24] PA6_MFP PA.6 Pin Function Selection
001 = ADC input channel 6
010 = EBI AD[7]
011 = Timer 3 Capture event
101 = PWM0 Channel 3
Others = GPIOA[6]
[30:28] PA7_MFP PA.7 Pin Function Selection
001 = ADC input channel 7
010 = EBI AD[6]
011 = Timer 2 capture event
101 = PWM0 Channel 2
Others = GPIOA[7]

Definition at line 2637 of file Nano100Series.h.

◆ PB_H_MFP

__IO uint32_t SYS_T::PB_H_MFP

PB_H_MFP

Offset: 0x3C Port B high byte multiple function control register

Bits Field Descriptions
[2:0] PB8_MFP PB.8 Pin Function Selection
001 = ADC external trigger
010 = Timer0 external event input or Timer0 toggle output
011 = External interrupt 0
Others = GPIOB[8]
[6:4] PB9_MFP PB.9 Pin Function Selection
001 = SPI1 2nd slave select pin
010 = Timer1 external event input or Timer1 toggle output
101 = External interrupt 0
Others = GPIOB[9]
[10:8] PB10_MFP PB.10 Pin Function Selection
001 = SPI0 2nd slave select pin
010 = Timer2 external event input or Timer2 toggle output
101 = SPI0 MOSI0
Others = GPIOB[10]
[14:12] PB11_MFP PB.11 Pin Function Selection
001 = PWM1 Channel 0
010 = Timer3 external event input or Timer3 toggle output
101 = SPI0 MISO0
Others = GPIOB[11]
[18:16] PB12_MFP PB.12 Pin Function Selection
010 = EBI AD[0]
100 = FRQDIV_CLK
Others = GPIOB[12]
[22:20] PB13_MFP PB.13 Pin Function Selection
010 = EBI AD[1]
Others = GPIOB[13]
[26:24] PB14_MFP PB.14 Pin Function Selection
001 = External interrupt 0
100 = SPI2 2nd slave select pin
Others = GPIOB[14]
[30:28] PB15_MFP PB.15 Pin Function Selection
001 = External interrupt 1
011 = Snooper pin
Others = GPIOB[15]

Definition at line 2785 of file Nano100Series.h.

◆ PB_L_MFP

__IO uint32_t SYS_T::PB_L_MFP

PB_L_MFP

Offset: 0x38 Port B low byte multiple function control register

Bits Field Descriptions
[2:0] PB0_MFP PB.0 Pin Function Selection
001 = UART0 RX
011 = SPI1 MOSI0
Others = GPIOB[0]
[6:4] PB1_MFP PB.1 Pin Function Selection
001 = UART0 TX
011 = SPI1 MISO0
Others = GPIOB[1]
[10:8] PB2_MFP PB.2 Pin Function Selection
001 = UART0 RTSn
010 = EBI nWRL
011 = SPI1 SCLK
Others = GPIOB[2]
[14:12] PB3_MFP PB.3 Pin Function Selection
001 = UART0 CTSn
010 = EBI nWRH
011 = SPI1 1st slave select pin
Others = GPIOB[3]
[18:16] PB4_MFP PB.4 Pin Function Selection
001 = UART1 RX
011 = SmartCard0 card detection
100 = SPI2 1st slave select pin
Others = GPIOB[4]
[22:20] PB5_MFP PB.5 Pin Function Selection
001 = UART1 TX
100 = SPI2 SCLK
Others = GPIOB[5]
[26:24] PB6_MFP PB.6 Pin Function Selection
001 = UART1 RTSn
010 = EBI ALE
100 = SPI2 MISO0
Others = GPIOB[6]
[30:28] PB7_MFP PB.7 Pin Function Selection
001 = UART1 CTSn
010 = EBI nCS
100 = SPI2 MOSI0
Others = GPIOB[7]

Definition at line 2740 of file Nano100Series.h.

◆ PC_H_MFP

__IO uint32_t SYS_T::PC_H_MFP

PC_H_MFP

Offset: 0x44 Port C high byte multiple function control register

Bits Field Descriptions
[2:0] PC8_MFP PC.8 Pin Function Selection
001 = SPI1 1st slave select pin
010 = EBI MCLK
101 = I2C1 SDA
Others = GPIOC[8]
[6:4] PC9_MFP PC.9 Pin Function Selection
001 = SPI1 SCLK
101 = I2C1 SCL
Others = GPIOC[9]
[10:8] PC10_MFP PC.10 Pin Function Selection
001 = SPI1 MISO0
101 = UART1 RX
Others = GPIOC[10]
[14:12] PC11_MFP PC.11 Pin Function Selection
001 = SPI1 MOSI0
101 = UART1 TX
Others = GPIOC[11]
[18:16] PC12_MFP PC.12 Pin Function Selection
001 = SPI1 MISO1
010 = PWM1 Channel 1
100 = Snooper pin
101 = External interrupt 0
110 = I2C0 SDA
Others = GPIOC[12]
[22:20] PC13_MFP PC.13 Pin Function Selection
001 = SPI1 MOSI1
010 = PWM1 Channel 1
100 = Snooper pin
101 = External interrupt 1
110 = I2C0 SCL
Others = GPIOC[13]
[26:24] PC14_MFP PC.14 Pin Function Selection
010 = EBI AD[2]
100 = PWM1 Channel 3
Others = GPIOC[14]
[30:28] PC15_MFP PC.15 Pin Function Selection
010 = EBI AD[3]
011 = Timer0 capture event
100 = PWM1 Channel 2
Others = GPIOC[15]

Definition at line 2884 of file Nano100Series.h.

◆ PC_L_MFP

__IO uint32_t SYS_T::PC_L_MFP

PC_L_MFP

Offset: 0x40 Port C low byte multiple function control register

Bits Field Descriptions
[2:0] PC0_MFP PC.0 Pin Function Selection
001 = SPI0 1st slave select pin
010 = I2S WS
100 = SmartCard0 clock
Others = GPIOC[0]
[6:4] PC1_MFP PC.1 Pin Function Selection
001 = SPI0 SCLK
010 = I2S BCLK
100 = SmartCard0 DATA
Others = GPIOC[1]
[10:8] PC2_MFP PC.2 Pin Function Selection
001 = SPI0 MISO0
010 = I2S Din
100 = SmartCard0 Power
Others = GPIOC[2]
[14:12] PC3_MFP PC.3 Pin Function Selection
001 = SPI0 MOSI0
010 = I2S Dout
100 = SmartCard0 RST
Others = GPIOC[3]
[18:16] PC4_MFP PC.4 Pin Function Selection
001 = SPI0 MISO1
Others = GPIOC[4]
[22:20] PC5_MFP PC.5 Pin Function Selection
001 = SPI0 MOSI1
Others = GPIOC[5]
[26:24] PC6_MFP PC.6 Pin Function Selection
001 = DA out0
010 = EBI AD[4]
011 = Timer0 capture event
100 = SmartCard1 card detection
101 = PWM0 Channel 0
Others = GPIOC[6]
[30:28] PC7_MFP PC.7 Pin Function Selection
001 = DA out1
010 = EBI AD[5]
011 = Timer1 capture event
101 = PWM0 Channel 1
Others = GPIOC[7]

Definition at line 2834 of file Nano100Series.h.

◆ PD_H_MFP

__IO uint32_t SYS_T::PD_H_MFP

PD_H_MFP

Offset: 0x4C Port D high byte multiple function control register

Bits Field Descriptions
[2:0] PD8_MFP PD.8 Pin Function Selection
All settings = GPIOD[8]
[6:4] PD9_MFP PD.9 Pin Function Selection
All settings = GPIOD[9]
[10:8] PD10_MFP PD.10 Pin Function Selection
All settings = GPIOD[10]
[14:12] PD11_MFP PD.11 Pin Function Selection
All settings = GPIOD[11]
[18:16] PD12_MFP PD.12 Pin Function Selection
All settings = GPIOD[12]
[22:20] PD13_MFP PD.13 Pin Function Selection
All settings = GPIOD[13]
[26:24] PD14_MFP PD.14 Pin Function Selection
All settings = GPIOD[14]
[30:28] PD15_MFP PD.15 Pin Function Selection
All settings = GPIOD[15]

Definition at line 2955 of file Nano100Series.h.

◆ PD_L_MFP

__IO uint32_t SYS_T::PD_L_MFP

PD_L_MFP

Offset: 0x48 Port D low byte multiple function control register

Bits Field Descriptions
[2:0] PD0_MFP PD.0 Pin Function Selection
001 = UART1 RX
011 = SPI2 1st slave select pin
100 = SmartCard1 clock
Others = GPIOD[0]
[6:4] PD1_MFP PD.1 Pin Function Selection
001 = UART1 TX
011 = SPI2 SCLK
100 = SmartCard1 DATA
Others = GPIOD[1]
[10:8] PD2_MFP PD.2 Pin Function Selection
001 = UART1 RTSn
010 = I2S WS
011 = SPI2 MISO0
100 = SmartCard1 power
Others = GPIOD[2]
[14:12] PD3_MFP PD.3 Pin Function Selection
001 = UART1 CTSn
010 = I2S BCLK
011 = SPI2 MOSI0
100 = SmartCard1 reset
Others = GPIOD[3]
[18:16] PD4_MFP PD.4 Pin Function Selection
010 = I2S Din
011 = SPI2 MISO1
100 = SmartCard1 card detection
Others = GPIOD[4]
[22:20] PD5_MFP PD.5 Pin Function Selection
010 = I2S Dout
011 = SPI2 MOSI1
Others = GPIOD[5]
[26:24] PD6_MFP PD.6 Pin Function Selection
All settings = GPIOD[6]
[30:28] PD7_MFP PD.7 Pin Function Selection
All settings = GPIOD[7]

Definition at line 2929 of file Nano100Series.h.

◆ PDID

__I uint32_t SYS_T::PDID

PDID

Offset: 0x00 Part Device Identification number Register

Bits Field Descriptions
[31:0] PDID Part Device ID
This register reflects device part number code.
Software can read this register to identify which device is used.

Definition at line 2405 of file Nano100Series.h.

◆ PE_H_MFP

__IO uint32_t SYS_T::PE_H_MFP

PE_H_MFP

Offset: 0x54 Port E high byte multiple function control register

Bits Field Descriptions
[2:0] PE8_MFP PE.8 Pin Function Selection
All settings = GPIOE[8]
[6:4] PE9_MFP PE.9 Pin Function Selection
111 = UART1 RX
Others = GPIOE[9]
[10:8] PE10_MFP PE.10 Pin Function Selection
111 = UART1 TX
Others = GPIOE[10]
[14:12] PE11_MFP PE.11 Pin Function Selection
111 = UART1 RTSn
Others = GPIOE[11]
[18:16] PE12_MFP PE.12 Pin Function Selection
111 = UART1 CTSn
Others = GPIOE[12]
[22:20] PE13_MFP PE.13 Pin Function Selection
All settings = GPIOE[13]
[26:24] PE14_MFP PE.14 Pin Function Selection
All settings = GPIOE[14]
[30:28] PE15_MFP PE.15 Pin Function Selection
All settings = GPIOE[15]

Definition at line 3019 of file Nano100Series.h.

◆ PE_L_MFP

__IO uint32_t SYS_T::PE_L_MFP

PE_L_MFP

Offset: 0x50 Port E low byte multiple function control register

Bits Field Descriptions
[2:0] PE0_MFP PE.0 Pin Function Selection
001 = PWM1 Channel 2
010 = I2S MCLK
Others = GPIOE[0]
[6:4] PE1_MFP PE.1 Pin Function Selection
001 = PWM1 Channel 3
110 = SPI0 1st slave select pin
Others = GPIOE[1]
[10:8] PE2_MFP PE.2 Pin Function Selection
110 = SPI0 SCLK
Others = GPIOE[2]
[14:12] PE3_MFP PE.3 Pin Function Selection
110 = SPI0 MISO0
Others = GPIOE[3]
[18:16] PE4_MFP PE.4 Pin Function Selection
110 = SPI0 MOSI0
Others = GPIOE[4]
[22:20] PE5_MFP PE.5 Pin Function Selection
001 = PWM1 Channel 1
Others = GPIOE[5]
[26:24] PE6_MFP PE.6 Pin Function Selection
All settings = GPIOE[6]
[30:28] PE7_MFP PE.7 Pin Function Selection
All settings = GPIOE[7]

Definition at line 2989 of file Nano100Series.h.

◆ PF_L_MFP

__IO uint32_t SYS_T::PF_L_MFP

PF_L_MFP

Offset: 0x58 Port F low byte multiple function control register

Bits Field Descriptions
[2:0] PF0_MFP PF.0 Pin Function Selection
101 = External interrupt 0
111 = ICE DATA
Others = GPIOF[1]
[6:4] PF1_MFP PF.1 Pin Function Selection
100 = FRQDIV_CLK
101 = External interrupt 1
111 = ICE CLOCK
Others = GPIOF[1]
[10:8] PF2_MFP PF.2 Pin Function Selection
111 = HXT OUT
Others = GPIOF[2]
[14:12] PF3_MFP PF.3 Pin Function Selection
111 = HXT IN
Others = GPIOF[3]
[18:16] PF4_MFP PF.4 Pin Function Selection
001 = I2C0 SDA
Others = GPIOF[4]
[22:20] PF5_MFP PF.5 Pin Function Selection
001 = I2C0 SCL
Others = GPIOF[5]

Definition at line 3050 of file Nano100Series.h.

◆ PORCTL

__IO uint32_t SYS_T::PORCTL

PORCTL

Offset: 0x60 Power-On-Reset Controller Register

Bits Field Descriptions
[15:0] POR_DIS_CODE Power-On Reset Enable Control
This is a protected register. Please refer to open lock sequence to program it.
When powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again.
If setting the POR_DIS_CODE to 0x5AA5, the POR reset function will be disabled and the POR function will be active again when POR_DIS_CODE is set to another value or POR_DIS_CODE is reset by chip other reset functions, including: /RESET, Watchdog Timer reset, BOD reset, ICE reset command and the software-chip reset function.

Definition at line 3069 of file Nano100Series.h.

◆ RegLockAddr

__IO uint32_t SYS_T::RegLockAddr

RegLockAddr

Offset: 0x100 Register Lock Key Address register

Bits Field Descriptions
[0] RegUnLock Protected Register Unlock Status
0 = Protected register are locked. Any write to the target register is ignored.
1 = Protected registers are Unlock.

Definition at line 3299 of file Nano100Series.h.

◆ RST_SRC

__IO uint32_t SYS_T::RST_SRC

RST_SRC

Offset: 0x04 System Reset Source Register

Bits Field Descriptions
[0] RSTS_POR Reset by Power-On Reset
The RSTS_POR Flag Is Set By The "Reset Signal" From The Power-On Reset (POR) Module Or Bit CHIP_RST (IPRSTC1[0]) To Indicate The Previous Reset Source
0= No reset from POR or CHIP_RST.
1= The Power-On Reset (POR) or CHIP_RST had issued the reset signal to reset the system.
This bit is cleared by writing 1 to itself.
[1] RSTS_PAD Reset by /RESET Pin
The RSTS_PAD Flag Is Set By The "Reset Signal" From The /RESET Pin To Indicate The Previous Reset Source
0= No reset from /RESET pin.
1= The /RESET pin had issued the reset signal to reset the system.
This bit is cleared by writing 1 to itself.
[2] RSTS_WDT Reset by Watch-Dog Timer
The RSTS_WDT Flag Is Set By The "Reset Signal" From The Watch-Dog Timer Module To Indicate The Previous Reset Source
0= No reset from Watch-Dog Timer.
1= The Watch-Dog Timer module had issued the reset signal to reset the system.
This bit is cleared by writing 1 to itself.
[4] RSTS_BOD Reset by Brown-Out-Detect
The RSTS_BOD Flag Is Set By The "Reset Signal" From The Brown-Out-Detected Module To Indicate The Previous Reset Source
0= No reset from BOD.
1= The Brown-Out-Detected module had issued the reset signal to reset the system.
This bit is cleared by writing 1 to itself.
[5] RSTS_SYS Reset by Cortex_M0 Kernel
The RSTS_SYS Flag Is Set By The "Reset Signal" From The Cortex_M0 Kernel To Indicate The Previous Reset Source
0= No reset from Cortex_M0.
1= The Cortex_M0 had issued the reset signal to reset the system by software writing 1 to bit SYSRESTREQ(AIRCR[2], Application Interrupt and Reset Control Register) in system control registers of Cortex_M0 kernel.
This bit is cleared by writing 1 to itself.
[7] RSTS_CPU Reset by CPU
The RSTS_CPU Flag Is Set By Hardware If Software Writes CPU_RST (IPRST_CTL1[1]) "1" To Rest Cortex-M0 CPU Kernel And Flash Memory Controller (FMC)
0= No reset from CPU.
1= The Cortex-M0 CPU kernel and FMC are reset by software setting CPU_RST to 1.
This bit is cleared by writing 1 to itself.

Definition at line 2445 of file Nano100Series.h.

◆ TEMPCTL

__IO uint32_t SYS_T::TEMPCTL

TEMPCTL

Offset: 0x20 Temperature Sensor Control Register

Bits Field Descriptions
[0] VTEMP_EN Temperature Sensor Enable
0 = Temperature sensor function Disabled (default).
1 = Temperature sensor function Enabled.

Definition at line 2583 of file Nano100Series.h.

◆ VREFCTL

__IO uint32_t SYS_T::VREFCTL

VREFCTL

Offset: 0x6C Voltage reference Control register

Bits Field Descriptions
[0] BGP_EN Band-Gap Enable
This is a protected register. Please refer to open lock sequence to program it.
Band-gap is the reference voltage of internal reference voltage.
User must enable band-gap if want to enable internal 1.5V or 2.5V reference voltage.
0 = Disabled.
1 = Enabled.
[1] REG_EN Regulator Enable
Enable internal 1.5V or 2.5V reference voltage.
This is a protected register. Please refer to open lock sequence to program it.
0 = Disabled.
1 = Enabled.
[2] SEL25 Regulator Output Voltage Selection
Select internal reference voltage level.
This is a protected register. Please refer to open lock sequence to program it.
0 = 1.5V.
1 = 2.5V.
[3] EXT_MODE Regulator External Mode
This is a protected register. Please refer to open lock sequence to program it.
Users can output regulator output voltage in Vref pin if EXT_MODE is high.
0 = No connection with external VREF pin.
1 = Connect to external VREF pin.
Connect a 1uF to 10uF capacitor to AVSS will let internal voltage reference be more stable.
[11:8] BGP_TRIM Band-Gap Trim Value
This is a protected register. Please refer to open lock sequence to program it.
It is used to modify Band-gap output voltage.
Each step can adjust 2 % of band-gap output voltage.
The higher value, the lower band-gap output voltage.

Definition at line 3196 of file Nano100Series.h.


The documentation for this struct was generated from the following file: