| Nano100AN Series BSP V3.02.002 The Board Support Package for Nano100AN Series

Data Fields
SPI_T Struct Reference

`#include <Nano100Series.h>`

## Data Fields
__IO uint32_t | CTL
__IO uint32_t | STATUS
__IO uint32_t | CLKDIV
__IO uint32_t | SSR
__I uint32_t | RX0
__I uint32_t | RX1
__O uint32_t | TX0
__O uint32_t | TX1
__IO uint32_t | VARCLK
__IO uint32_t | PDMA
__IO uint32_t | FFCLR

## Detailed Description

    @addtogroup SPI Serial Peripheral Interface Controller(SPI)
    Memory Mapped Structure for SPI Controller

Definition at line 7871 of file Nano100Series.h.

## Field Documentation

## ◆ CLKDIV

__IO uint32_t SPI_T::CLKDIV

# CLKDIV

## Offset: 0x08 SPI Clock Divider Register

Bits | Field | Descriptions
--- | --- | ---
[15:0] | DIVIDER1 | Clock Divider 1 Register
|  | The value in this field is the 1th frequency divider of the PCLK to generate the serial clock of SPI_SCLK.
|  | The desired frequency is obtained according to the following equation:
|  | Note 1: The DIVIDER1 can be set as 0. If the DIVIDER1 is set as zero, the frequency of SPI_SCLK is the same as PCLK in Master mode.
|  | Note 2: In Slave mode, the period of SPI clock driven by a master shall equal to or over 5 times the period of PCLK.
|  | In other words, the maximum frequency of SPI clock is the fifth of the frequency of slave's PCLK.
[31:16] | DIVIDER2 | Clock Divider 2 Register
|  | The value in this field is the 2nd frequency divider of the PCLK to generate the serial clock of SPI_SCLK.
|  | The desired frequency is obtained according to the following equation:

Definition at line 8039 of file Nano100Series.h.

## ◆ CTL

__IO uint32_t SPI_T::CTL

# CTL

## Offset: 0x00 SPI Control Register

Bits | Field | Descriptions
--- | --- | ---
[0] | GO_BUSY | Go And Busy Status
|  | 0 = Writing this bit "0" to stop data transfer if SPI is transferring.
|  | 1 = In Master mode, writing "1" to this bit to start the SPI data transfer; In Slave mode, writing '1' to this bit indicates that the salve is ready to communicate with a master.
|  | During the data transfer, this bit keeps the value of '1'.
|  | As the transfer is finished, this bit will be cleared automatically.
|  | Note:
|  | 1. All registers should be set before writing "1" to the GO_BUSY bit in the SPI_CTL register.
|  | 2. In FIFO mode, this bit will be controlled by hardware. Software should not modify this bit.
[1] | RX_NEG | Receive At Negative Edge
|  | 0 = The received data is latched on the rising edge of SPI_SCLK.
|  | 1 = The received data is latched on the falling edge of SPI_SCLK.
[2] | TX_NEG | Transmit At Negative Edge
|  | 0 = The transmitted data output is changed on the rising edge of SPI_SCLK.
|  | 1 = The transmitted data output is changed on the falling edge of SPI_SCLK.
[7:3] | TX_BIT_LEN | Transmit Bit Length
|  | This field specifies how many bits are transmitted in one transmit/receive transaction.
|  | Up to 32 bits can be transmitted.
|  | 00001 ~ 00111 aren't be used.
|  | TX_BIT_LEN Description
|  | 01000 8 bits are transmitted in one transaction
|  | 01001 9 bits are transmitted in one transaction
|  | ---— -------—
|  | 11111 31 bits are transmitted in one transaction
|  | 00000 32 bits are transmitted in one transaction
[9:8] | TX_NUM | Number Of Transmit/Receive Transaction
|  | This field specifies how many transmit/receive transaction should be executed in one transfer.
|  | 00 = Only one transmit/receive transaction will be executed in one transfer.
|  | 01 = Two successive transmit/receive transaction will be executed in one transfer (burst mode).
|  | 10 = Reserved.
|  | 11 = Reserved.
[10] | LSB | Send LSB First
|  | 0 = The MSB is transmitted/received first (which bit in SPI_TX register will be transmitted/received that is depends on the TX_BIT_LEN field in the CTRL register).
|  | 1 = The LSB is sent first on the data line (TDATA[0]), and the first bit received from the data line will be put in the LSB position in the SPI_RX register (RDATA[0]).
[11] | CLKP | Clock Polarity
|  | 0 = The default level of SCLK is low in idle state.
|  | 1 = The default level of SCLK is high in idle state.
[15:12] | SP_CYCLE | Suspend Interval (Master Only)
|  | These four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer.
|  | The suspend interval is from the last falling clock edge of the current transaction to the first rising clock edge of the successive transaction if CLKP = "0".
|  | If CLKP = "1", the interval is from the rising clock edge to the falling clock edge.
|  | The default value is 0000.
|  | When TX_NUM = 00, setting this field has no effect on transfer.
|  | The desired suspend interval is obtained according to the following equation:(SP_CYCLE[3:0] + 2)*period of SPICLK.
|  | For byte suspend interval and burst mode suspend interval, suspend interval is SP__CYCLE + 2
|  | For FIFO mode suspend interval:
|  | SP_CYCLE can't be set as 1.
|  | If SP_CYCLE equals from 2 to 15, suspend interval period is
|  | (SP_CYCLE[3:0] + 3) * system clock period + 1 SPICLK clock cycle
|  | If SP_CYCLE = 0, suspend interval period is.
|  | 35 * period of system clock + 1 SPICLK clock cycle
|  | In case of DIVIDER = 0, if SP_CYCLE = 2~15, suspend interval period is.
|  | (SP_CYCLE[3:0] + 3.5) * system clock period
|  | Ex:
|  | SP_CYCLE = 0x2 ... 5.5 system clock periods.
|  | ......
|  | SP_CYCLE = 0xE ... 17.5 system clock periods.
|  | SP_CYCLE = 0xF ... 18.5 system clock periods.
|  | if SP_CYCLE = 0, suspend interval period is.
|  | 35.5 * system clock period
[17] | INTEN | Interrupt Enable
|  | 0 = SPI Interrupt Disabled.
|  | 1 = SPI Interrupt Enabled.
[18] | SLAVE | Slave Mode Indication
|  | 0 = SPI controller is set as Master mode.
|  | 1 = SPI controller is set as Slave mode.
[20:19] | REORDER | Reorder Mode Selection
|  | 00 = Disable both byte reorder and suspend functions.
|  | 01 = Enable byte reorder function and insert a byte suspend interval among each byte.
|  | The setting of TX_BIT_LEN must be configured as 00b ( 32 bits/ word).
|  | 10 = Enable byte reorder function, but disable byte suspend function.
|  | 11 = Disable byte reorder function, but insert a suspend interval among each byte.
|  | The setting of TX_BIT_LEN must be configured as 00b ( 32 bits/ word).
|  | The suspend interval is defined in SP_CYCLE.
|  | Note 1: Byte reorder function is only available if TX_BIT_LEN is defined as 16, 24, and 32 bits.
|  | Note 2: In Slave mode with level-trigger configuration, if the byte suspend function is enabled, the slave select pin must be kept at active state during the successive four bytes transfer.
[21] | FIFOM | Dual FIFO Mode Enable
|  | There is another shadow FIFO in each FIFO register.
|  | User can use it to improve the performance.
|  | In normal mode, the transmitted/received data can only be updated/read back after the current transfer done.
|  | In FIFO mode, the next transmitted and previous received data can be updated/read back during the current transfer period.
|  | 0 = Normal mode. The dual transmitting and receiving FIFO is not used.
|  | 1 = Dual FIFO mode. User can use the dual transmitting and receiving FIFO to improve its performance.
|  | Note 1:The FIFOM is active in one word transaction only. That means the TX_NUM shall be set as 00.
|  | Note 2: Before enabling FIFO mode, the other related settings should be set in advance.
|  | Note 3: In Slave mode with level-trigger configuration, the slave select pin must be kept at active state during the successive data transfer.
|  | Note 4: In FIFO mode, both the REORDER field and the TX_NUM field must be configured as 0.
|  | In other words, the byte-reorder function, byte suspend function and burst mode must be disabled.
[22] | TWOB | Two Bit Transfer Mode Active
|  | 0 = Two-bit transfer mode Disabled.
|  | 1 = Two-bit transfer mode Enabled.
|  | Note that when enabling TWOB, the serial transmitted 2-bits data output are from SPI_TX1/0, and the received 2-bits data input are put into SPI_RX1/0.
|  | Note that when enabling TWOB, the setting of TX_NUM must be programmed as 00.
[23] | VARCLK_EN | Variable Clock Enable
|  | 0 = The serial clock output frequency is fixed and only decided by the value of DIVIDER1 (SPI_CLKDIV[15:0]).
|  | 1 = The serial clock output frequency is variable.
|  | The output frequency is decided by the value of VARCLK (SPI_VARCLK), DIVIDER1(SPI_CLKDIV[15:0]), and DIVIDER2(SPI_CLKDIV[31:16]).
[31] | WKEUP_EN | Wake-Up Enable
|  | 0 = Wake-up function Disabled when the system enters the power-down mode.
|  | 1 = Wake-up function Enabled.
|  | When the system enters the power-down mode, the system can be wake-up from the SPI controller when this bit is enabled and if there is any toggle in the SPICLK port.
|  | After the system wake-up, this bit must be clear by user to disable the wake-up requirement.

Definition at line 7984 of file Nano100Series.h.

## ◆ FFCLR

__IO uint32_t SPI_T::FFCLR

# FFCLR

## Offset: 0x3C SPI FIFO Counter Clear Control Register

Bits | Field | Descriptions
--- | --- | ---
[0] | RX_CLR | Receiving FIFO Counter Clear
|  | This bit is used to clear the receiver counter in FIFO Mode.
|  | This bit can be written "1" to clear the receiver counter and this bit will be clear to "0" automatically after clearing receiving counter.
|  | After the clear operation, the flag of RX_EMPTY in SPI_STATUS[0] will be set to "1".
[1] | TX_CLR | Transmitting FIFO Counter Clear
|  | This bit is used to clear the transmit counter in FIFO Mode.
|  | This bit can be written "1" to clear the transmitting counter and this bit will be clear to "0" automatically after clearing transmitting counter.
|  | After the clear operation, the flag of TX_EMPTY in SPI_STATUS[2] will be set to "1".

Definition at line 8223 of file Nano100Series.h.

## ◆ PDMA

__IO uint32_t SPI_T::PDMA

# PDMA

## Offset: 0x38 SPI PDMA Control Register

Bits | Field | Descriptions
--- | --- | ---
[0] | TX_DMA_EN | Transmit PDMA Enable (PDMA Writes Data To SPI)
|  | Set this bit to "1" will enable the transmitting PDMA process.
|  | SPI transmit PDMA request will issue automatically when this bit is active and the GO_BUSY set "1".
|  | 0 = SPI transmit PDMA function Disabled.
|  | 1 = SPI transmit PDMA function Enabled.
|  | Note 1: The bit shall be programmed before the GO_BUSY bit if the user wants to enable the DMA function.
|  | Note 2: In DMA mode, the burst mode and FIFO mode are not support.
|  | Note 3: It is auto cleared to 0 after the PDMA function done.
[1] | RX_DMA_EN | Receiving PDMA Enable(PDMA Reads SPI Data To Memory)
|  | Set this bit to "1" will enable the receive PDMA process.
|  | SPI module will issue request the PDMA function in receive channel when this bit active and the transaction has done.
|  | If the transmit PDMA process is enabled, the priority of receive PDMA in DMA block shall be higher than the transmit PDMA.
|  | 0 = SPI receive PDMA function Disabled.
|  | 1 = SPI receive PDMA function Enabled.
|  | Note: It is auto cleared to "0" after the PDMA function done.
[2] | PDMA_RST | PDMA Reset
|  | It is used to reset the SPI PDMA function into default state.
|  | 0 = After reset PDMA function or in normal operation.
|  | 1 = Reset PDMA function.
|  | Note: it is auto cleared to "0" after the reset function done.

Definition at line 8205 of file Nano100Series.h.

## ◆ RX0

__I uint32_t SPI_T::RX0

# RX0

## Offset: 0x10 SPI Receive Data FIFO Register 0

Bits | Field | Descriptions
--- | --- | ---
[31:0] | RDATA | Receive Data FIFO Register
|  | The received data FIFO registers hold the value of received data of the last executed transfer.
|  | Valid bits depend on the transaction bit length field in the SPI_CTL register.
|  | For example :
|  | If TX_BIT_LEN is set to 01000 and TX_NUM is set to 00, RDATA[7:0] holds the received data.
|  | Note: These registers are read only.

Definition at line 8102 of file Nano100Series.h.

## ◆ RX1

__I uint32_t SPI_T::RX1

# RX1

## Offset: 0x14 SPI Receive Data FIFO Register 1

Bits | Field | Descriptions
--- | --- | ---
[31:0] | RDATA | Receive Data FIFO Register
|  | The received data FIFO registers hold the value of received data of the last executed transfer.
|  | Valid bits depend on the transaction bit length field in the SPI_CTL register.
|  | For example :
|  | If TX_BIT_LEN is set to 01000 and TX_NUM is set to 00, RDATA[7:0] holds the received data.
|  | Note: These registers are read only.

Definition at line 8118 of file Nano100Series.h.

## ◆ SSR

__IO uint32_t SPI_T::SSR

# SSR

## Offset: 0x0C SPI Slave Select Register

Bits | Field | Descriptions
--- | --- | ---
[1:0] | SSR | Slave Select Active Register (Master Only)
|  | If AUTOSS bit is cleared, writing "1" to SSR[0] bit sets the SPISS[0] line to an active state and writing "0" sets the line back to inactive state.(the same as SSR[1] for SPISS[1])
|  | If AUTOSS bit is set, writing "1" to any bit location of this field will select appropriate SPISS[1:0] line to be automatically driven to active state for the duration of the transaction, and will be driven to inactive state for the rest of the time.
|  | (The active level of SPISS[1:0] is specified in SS_LVL).
|  | Note 1: This interface can only drive one device/slave at a given time.
|  | Therefore, the slaves select of the selected device must be set to its active level before starting any read or write transfer.
|  | Note 2: SPISS[0] is also defined as device/slave select input in Slave mode.
|  | And that the slave select input must be driven by edge active trigger which level depend on the SS_LVL setting, otherwise the SPI slave core will go into dead path until the edge active triggers again or reset the SPI core by software.
[2] | SS_LVL | Slave Select Active Level
|  | It defines the active level of device/slave select signal (SPISS[1:0]).
|  | 0 = The SPI_SS slave select signal is active Low.
|  | 1 = The SPI_SS slave select signal is active High.
[3] | AUTOSS | Automatic Slave Selection (Master Only)
|  | 0 = If this bit is set as "0", slave select signals are asserted and de-asserted by setting and clearing related bits in SSR[1:0] register.
|  | 1 = If this bit is set as "1", SPISS[1:0] signals are generated automatically.
|  | It means that device/slave select signal, which is set in SSR[1:0] register is asserted by the SPI controller when transmit/receive is started by setting the GO_BUSY bit, and is de-asserted after each transaction is done.
[4] | SS_LTRIG | Slave Select Level Trigger
|  | 0 = The input slave select signal is edge-trigger.
|  | 1 = The slave select signal will be level-trigger.
|  | It depends on SS_LVL to decide the signal is active low or active high.
[5] | NOSLVSEL | No Slave Selected In Slave Mode
|  | This is used to ignore the slave select signal in Slave mode.
|  | The SPI controller can work on 3 wire interface including SPICLK, SPI_MISO, and SPI_MOSI when it is set as a slave device.
|  | 0 = The controller is 4-wire bi-direction interface.
|  | 1 = The controller is 3-wire bi-direction interface in Slave mode.
|  | When this bit is set as 1, the controller start to transmit/receive data after the GO_BUSY bit active and the serial clock input.
|  | Note: In no slave select signal mode, the SS_LTRIG, SPI_SSR[4], shall be set as "1".
[8] | SLV_ABORT | Abort In Slave Mode With No Slave Selected
|  | In normal operation, there is interrupt event when the received data meet the required bits which define in TX_BIT_LEN and TX_NUM.
|  | If the received bits are less than the requirement and there is no more serial clock input over the time period which is defined by user in slave mode with no slave select, the user can set this bit to force the current transfer done and then the user can get a transfer done interrupt event.
|  | Note: It is auto clear to "0" by hardware when the abort event is active.
[9] | SSTA_INTEN | Slave Start Interrupt Enable
|  | It is used to enable interrupt when the transfer has started in Slave mode with no slave select.
|  | If there is no transfer done interrupt over the time period which is defined by user after the transfer start, the user can set the SLV_ABORT bit to force the transfer done.
|  | 0 = Transfer start interrupt Disabled.
|  | 1 = Transaction start interrupt Enabled.
|  | It is cleared when the current transfer done or the SLV_START_INTSTS bit cleared (write one clear).

Definition at line 8086 of file Nano100Series.h.

## ◆ STATUS

__IO uint32_t SPI_T::STATUS

# STATUS

## Offset: 0x04 SPI Status Register

Bits | Field | Descriptions
--- | --- | ---
[0] | RX_EMPTY | Received Dual FIFO_EMPTY Status
|  | 0 = Received data FIFO is not empty in the dual FIFO mode.
|  | 1 = Received data FIFO is empty in the dual FIFO mode.
[1] | RX_FULL | Received Dual FIFO_FULL Status
|  | 0 = Received data FIFO is not full in dual FIFO mode.
|  | 1 = Received data FIFO is full in the dual FIFO mode.
[2] | TX_EMPTY | Transmitted Dual FIFO_EMPTY Status
|  | 0 = Transmitted data FIFO is not empty in the dual FIFO mode.
|  | 1 =Transmitted data FIFO is empty in the dual FIFO mode.
[3] | TX_FULL | Transmitted Dual FIFO_FULL Status
|  | 0 = Transmitted data FIFO is not full in the dual FIFO mode.
|  | 1 = Transmitted data FIFO is full in the dual FIFO mode.
[4] | LTRIG_FLAG | Level Trigger Flag
|  | When the SS_LTRIG bit is set as level trigger in Slave mode, this bit can be read to indicate the received bit number is met the requirement or not.
|  | 0 = One of the received number and the received bit length doesn't meet the requirement in one transfer.
|  | 1 = The received number and received bits met the requirement which defines in TX_NUM and TX_BIT_LEN among one transfer.
|  | Note: This bit is READ only
[6] | SLV_START_INTSTS | Slave Start Interrupt Status
|  | It is used to dedicate that the transfer has started in Slave mode with no slave select.
|  | 0 = Slave started transfer no active.
|  | 1 = Transfer has started in Slave mode with no slave select.
|  | It is auto clear by transfer done or writing one clear.
[7] | INTSTS | Interrupt Status
|  | 0 = Transfer is not finished yet.
|  | 1 = Transfer is done. The interrupt is requested when the INTEN bit is enabled.
|  | Note: This bit is read only, but can be cleared by writing "1" to this bit.

Definition at line 8020 of file Nano100Series.h.

## ◆ TX0

__O uint32_t SPI_T::TX0

# TX0

## Offset: 0x20 SPI Transmit Data FIFO Register 0

Bits | Field | Descriptions
--- | --- | ---
[31:0] | TDATA | Transmit Data FIFO Register
|  | The transmit data FIFO registers hold the data to be transmitted in the next transfer.
|  | Valid bits depend on the transaction bit length field in the SPI_CTL register.
|  | For example :
|  | (1). If TX_BIT_LEN is set to 01000 and the TX_NUM is set to 00, TDATA[7:0] will be transmitted in next transaction.
|  | (2). If TX_BIT_LEN is set to 00000 and TX_NUM is set to 01, the core will perform two 32-bit transmit/receive successive using the same setting (the order is TDATA0[31:0], TDATA1[31:0]).

Definition at line 8139 of file Nano100Series.h.

## ◆ TX1

__O uint32_t SPI_T::TX1

# TX1

## Offset: 0x24 SPI Transmit Data FIFO Register 1

Bits | Field | Descriptions
--- | --- | ---
[31:0] | TDATA | Transmit Data FIFO Register
|  | The transmit data FIFO registers hold the data to be transmitted in the next transfer.
|  | Valid bits depend on the transaction bit length field in the SPI_CTL register.
|  | For example :
|  | (1). If TX_BIT_LEN is set to 01000 and the TX_NUM is set to 00, TDATA[7:0] will be transmitted in next transaction.
|  | (2). If TX_BIT_LEN is set to 00000 and TX_NUM is set to 01, the core will perform two 32-bit transmit/receive successive using the same setting (the order is TDATA0[31:0], TDATA1[31:0]).

Definition at line 8155 of file Nano100Series.h.

## ◆ VARCLK

__IO uint32_t SPI_T::VARCLK

# VARCLK

## Offset: 0x34 SPI Variable Clock Pattern Flag Register

Bits | Field | Descriptions
--- | --- | ---
[31:0] | VARCLK | Variable Clock Pattern Flag
|  | The value in this field is the frequency patterns of the SPICLK.
|  | If the bit pattern of VARCLK is '0', the output frequency of SPICLK is according the value of DIVIDER1.
|  | If the bit patterns of VARCLK are '1', the output frequency of SPICLK is according the value of DIVIDER2.
|  | Note: It is used for CLKP = 0 only.

Definition at line 8175 of file Nano100Series.h.

The documentation for this struct was generated from the following file:

- C:/Users/yachen/workzone/bsp/nano100absp/Library/Device/Nuvoton/Nano100Series/Include/Nano100Series.h