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Nano100AN Series BSP
V3.02.002
The Board Support Package for Nano100AN Series
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#include <Nano100Series.h>
Data Fields | |
| __IO uint32_t | CTRL |
| __IO uint32_t | CLKDIV |
| __IO uint32_t | INTEN |
| __IO uint32_t | STATUS |
| __O uint32_t | TXFIFO |
| __I uint32_t | RXFIFO |
@addtogroup I2S I2S Interface Controller(I2S) Memory Mapped Structure for I2S Controller
Definition at line 4838 of file Nano100Series.h.
| __IO uint32_t I2S_T::CLKDIV |
| Bits | Field | Descriptions |
|---|---|---|
| [2:0] | MCLK_DIV | Master Clock Divider |
| If the external crystal frequency is (2xMCLK_DIV)*256fs then software can program these bits to generate 256fs clock frequency to audio CODEC chip. | ||
| If MCLK_DIV is set to "0", MCLK is the same as external clock input. | ||
| For example, sampling rate is 48 kHz and the external crystal clock is 12.288 MHz, set MCLK_DIV=0. | ||
| MCLK = I2SCLK/(2x(MCLK_DIV)). | ||
| [15:8] | BCLK_DIV | Bit Clock Divider |
| If I2S is operated in Master mode, bit clock is provided by this chip. | ||
| Software can program these bits to generate sampling rate clock frequency. | ||
| BCLK = I2SCLK /(2x(BCLK_DIV + 1)). |
Definition at line 4947 of file Nano100Series.h.
| __IO uint32_t I2S_T::CTRL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | I2SEN | I2S Controller Enable |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [1] | TXEN | Transmit Enable |
| 0 = Data transmitting Disabled. | ||
| 1 = Data transmitting Enabled. | ||
| [2] | RXEN | Receive Enable |
| 0 = Data receiving Disabled. | ||
| 1 = Data receiving Enabled. | ||
| [3] | MUTE | Transmitting Mute Enable |
| 0 = Transmit data in buffer to channel. | ||
| 1= Transmit '0' to channel. | ||
| [5:4] | WORDWIDTH | Word Width |
| 00 = Data is 8 bit. | ||
| 01 = Data is 16 bit. | ||
| 10 = Data is 24 bit. | ||
| 11 = Data is 32 bit. | ||
| [6] | MONO | Monaural Data |
| 0 = Data is stereo format. | ||
| 1 = Data is monaural format and gets the right channel data from I2S bus when this mode is enabled. | ||
| [7] | FORMAT | Data Format |
| 0 = I2S data format. | ||
| 1 = MSB justified data format. | ||
| [8] | SLAVE | Slave Mode |
| I2S can operate as master or Slave mode. | ||
| For Master mode, I2S_BCLK and I2S_LRCLK pins are output mode and also outputs I2S_BCLK and I2S_LRCLK signals to the audio CODEC. | ||
| When act as Slave mode, I2S_BCLK and I2S_LRCLK pins are input mode and I2S_BCLK and I2S_LRCLK signals are received from the outer audio CODEC chip. | ||
| 0 = Master mode. | ||
| 1 = Slave mode. | ||
| [11:9] | TXTH | Transmit FIFO Threshold Level |
| If remain data word (32 bits) in transmitting FIFO is the same or less than threshold level then TXTHF flag is set. | ||
| 000 = 1 word data in transmitting FIFO. | ||
| 001 = 2 word data in transmitting FIFO. | ||
| 010 = 3 word data in transmitting FIFO. | ||
| 011 = 4 word data in transmitting FIFO. | ||
| 100 = 5 word data in transmitting FIFO. | ||
| 101 = 6 word data in transmitting FIFO. | ||
| 110 = 7 word data in transmitting FIFO. | ||
| 111 = 8 word data in transmitting FIFO. | ||
| [14:12] | RXTH | Receiving FIFO Threshold Level |
| When received data word(s) in buffer is equal to or higher than threshold level then RXTHF flag is set. | ||
| 000 = 1 word data in receiving FIFO. | ||
| 001 = 2 word data in receiving FIFO. | ||
| 010 = 3 word data in receiving FIFO. | ||
| 011 = 4 word data in receiving FIFO. | ||
| 100 = 5 word data in receiving FIFO. | ||
| 101 = 6 word data in receiving FIFO. | ||
| 110 = 7 word data in receiving FIFO. | ||
| 111 = 8 word data in receiving FIFO. | ||
| [15] | MCLKEN | Master Clock Enable |
| Enable master MCLK timing output to the external audio codec device. | ||
| The output frequency is according to MCLK_DIV[2:0] in the I2S_CLKDIV register. | ||
| 0 = Master Clock Disabled. | ||
| 1 = Master Clock Enabled. | ||
| [16] | RCHZCEN | Right Channel Zero Cross Detect Enable |
| If this bit is set to "1", when right channel data sign bit is changed or next shift data bits are all zero then RZCF flag in I2S_STATUS register is set to "1". | ||
| It works on transmitting mode only. | ||
| 0 = Right channel zero cross detection Disabled. | ||
| 1 = Right channel zero cross detection Enabled. | ||
| [17] | LCHZCEN | Left Channel Zero Cross Detect Enable |
| If this bit is set to "1", when left channel data sign bit is changed or next shift data bits are all zero then LZCF flag in I2S_STATUS register is set to "1". | ||
| It works on transmitting mode only. | ||
| 0 = Left channel zero cross detection Disabled. | ||
| 1 = Left channel zero cross detection Enabled. | ||
| [18] | CLR_TXFIFO | Clear Transmit FIFO |
| Write "1" to clear transmitting FIFO, internal pointer is reset to FIFO start point, TX_LEVEL[3:0] returns to zero and transmitting FIFO becomes empty but data in transmit FIFO is not changed. | ||
| This bit is clear by hardware automatically, read it return zero. | ||
| [19] | CLR_RXFIFO | Clear Receiving FIFO |
| Write "1" to clear receiving FIFO, internal pointer is reset to FIFO start point, and RX_LEVEL[3:0] returns to zero and receiving FIFO becomes empty. | ||
| This bit is cleared by hardware automatically, and read it return zero. | ||
| [20] | TXDMA | Enable Transmit DMA |
| When TX DMA is enabled, I2S requests PDMA to transfer data from memory to transmitting FIFO if FIFO is not full | ||
| 0 = TX DMA Disabled. | ||
| 1 = TX DMA Enabled. | ||
| [21] | RXDMA | Enable Receive DMA |
| When RX DMA is enabled, I2S requests PDMA to transfer data from receiving FIFO to memory if FIFO is not empty. | ||
| 0 = RX DMA Disabled. | ||
| 1 = RX DMA Enabled. |
Definition at line 4928 of file Nano100Series.h.
| __IO uint32_t I2S_T::INTEN |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | RXUDFIE | Receiving FIFO Underflow Interrupt Enable |
| Interrupt occurs if this bit is set to "1" and receiving FIFO underflow flag is set to "1". | ||
| 0 = Interrupt Disabled. | ||
| 1 = Interrupt Enabled. | ||
| [1] | RXOVFIE | Receiving FIFO Overflow Interrupt Enable |
| Interrupt occurs if this bit is set to "1" and receiving FIFO overflow flag is set to "1" | ||
| 0 = Interrupt Disabled. | ||
| 1 = Interrupt Enabled. | ||
| [2] | RXTHIE | Receiving FIFO Threshold Level Interrupt Enable |
| Interrupt occurs if this bit is set to "1" and data words in receiving FIFO is less than RXTH[2:0]. | ||
| 0 = Interrupt Disabled. | ||
| 1 = Interrupt Enabled. | ||
| [8] | TXUDFIE | Transmitting FIFO Underflow Interrupt Enable |
| Interrupt occurs if this bit is set to "1" and transmitting FIFO underflow flag is set to "1". | ||
| 0 = Interrupt Disabled. | ||
| 1 = Interrupt Enabled. | ||
| [9] | TXOVFIE | Transmitting FIFO Overflow Interrupt Enable |
| Interrupt occurs if this bit is set to "1" and transmitting FIFO overflow flag is set to "1" | ||
| 0 = Interrupt Disabled. | ||
| 1 = Interrupt Enabled. | ||
| [10] | TXTHIE | Transmitting FIFO Threshold Level Interrupt Enable |
| Interrupt occurs if this bit is set to "1" and data words in transmitting FIFO is less than TXTH[2:0]. | ||
| 0 = Interrupt Disabled. | ||
| 1 = Interrupt Enabled. | ||
| [11] | RZCIE | Right Channel Zero Cross Interrupt Enable |
| Interrupt occurs if this bit is set to "1" and right channel is zero crossing. | ||
| 0 = Interrupt Disabled. | ||
| 1 = Interrupt Enabled. | ||
| [12] | LZCIE | Left Channel Zero Cross Interrupt Enable |
| Interrupt occurs if this bit is set to "1" and left channel is zero crossing. | ||
| 0 = Interrupt Disabled. | ||
| 1 = Interrupt Enabled. |
Definition at line 4989 of file Nano100Series.h.
| __I uint32_t I2S_T::RXFIFO |
| Bits | Field | Descriptions |
|---|---|---|
| [31:0] | RXFIFO | Receiving FIFO Register |
| I2S contains 8 words (8x32-bit) data buffer for data receiving. | ||
| Read this register to get data in FIFO. | ||
| The remaining data word number is indicated by RX_LEVEL[3:0] in the I2S_STATUS register. | ||
| This register is read only. |
Definition at line 5120 of file Nano100Series.h.
| __IO uint32_t I2S_T::STATUS |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | I2SINT | I2S Interrupt Flag |
| 0 = No I2S interrupt. | ||
| 1 = I2S interrupt occurs. | ||
| It is wire-OR of I2STXINT and I2SRXINT bits. | ||
| This bit is read only. | ||
| [1] | I2SRXINT | I2S Receiving Interrupt |
| 0 = No receiving interrupt occurs. | ||
| 1 = Receiving interrupt occurs. | ||
| This bit is read only | ||
| [2] | I2STXINT | I2S Transmit Interrupt |
| 0 = No transmit interrupt occurs. | ||
| 1 = Transmit interrupt occurs. | ||
| This bit is read only | ||
| [3] | RIGHT | Right Channel |
| This bit indicates the current transmitting data is belong to right channel | ||
| 0 = Left channel. | ||
| 1 = Right channel. | ||
| This bit is read only | ||
| [8] | RXUDF | Receiving FIFO Underflow Flag |
| Read the receiving FIFO when it is empty, this bit set to "1" indicate underflow occur. | ||
| 0 = No underflow occur. | ||
| 1 = Underflow occurs. | ||
| This bit is cleared by writing 1. | ||
| [9] | RXOVF | Receiving FIFO Overflow Flag |
| When the receiving FIFO is full and receiving hardware attempts to write data into receiving FIFO then this bit is set to "1". | ||
| Data in 1st buffer is overwritten. | ||
| 0 = No overflow occur. | ||
| 1 = Overflow occurs. | ||
| This bit is cleared by writing 1. | ||
| [10] | RXTHF | Receiving FIFO Threshold Flag |
| When data word(s) in the receiving FIFO is equal to or higher than threshold value set in RXTH[2:0], the RXTHF bit becomes to "1". | ||
| It keeps at "1" till RX_LEVEL[3:0] less than RXTH[1:0] after software reads data from the RXFIFO register. | ||
| 0 = Data word(s) in receiving FIFO is lower than threshold level. | ||
| 1 = Data word(s) in receiving FIFO is equal to or higher than threshold level. | ||
| This bit is read only | ||
| [11] | RXFULL | Receiving FIFO Full |
| This bit reflect data word number in the receiving FIFO is 8 | ||
| 0 = Not full. | ||
| 1 = Full. | ||
| This bit is read only | ||
| [12] | RXEMPTY | Receiving FIFO Empty |
| This bit reflect data word number in the receiving FIFO is zero | ||
| 0 = Empty. | ||
| 1 = Not empty. | ||
| This bit is read only. | ||
| [16] | TXUDF | Transmitting FIFO Underflow Flag |
| When the transmitting FIFO is empty and shift logic hardware read data from the data FIFO causes this set to "1". | ||
| 0 = No underflow. | ||
| 1 = Underflow. | ||
| This bit is cleared by writing 1. | ||
| [17] | TXOVF | Transmit FIFO Overflow Flag |
| Write data to the transmitting FIFO when it is full and this bit will set to "1" | ||
| 0 = No overflow. | ||
| 1 = Overflow. | ||
| This bit is cleared by writing 1. | ||
| [18] | TXTHF | Transmitting FIFO Threshold Flag |
| When data word(s) in the transmitting FIFO is equal to or lower than threshold value set in TXTH[2:0],the TXTHF bit becomes to "1". | ||
| It keeps at 1 till TX_LEVEL[3:0] is higher than TXTH[1:0] after software writes data into the TXFIFO register. | ||
| 0 = Data word(s) in transmitting FIFO is higher than threshold level. | ||
| 1 = Data word(s) in transmitting FIFO is equal or lower than threshold level. | ||
| This bit is read only | ||
| [19] | TXFULL | Transmitting FIFO Full |
| This bit reflect data word number in the transmitting FIFO is 8 | ||
| 0 = Not full. | ||
| 1 = Full. | ||
| This bit is read only | ||
| [20] | TXEMPTY | Transmitting FIFO Empty |
| This bit reflect data word number in the transmitting FIFO is zero | ||
| 0 = Empty. | ||
| 1 = Not empty. | ||
| This bit is read only. | ||
| [21] | TXBUSY | Transmitting Busy |
| This bit is clear to 0 when all data in the transmitting FIFO and shift buffer is shifted out. | ||
| Set this bit to 1 when 1st data is loading to shift buffer. | ||
| 0 = Transmit shift buffer is empty. | ||
| 1 = Transmit shift buffer is busy. | ||
| This bit is read only. | ||
| [22] | RZCF | Right Channel Zero Cross Flag |
| It indicates the data sign of right channel next sample data is changed or all data bits are zero. | ||
| 0 = No zero cross. | ||
| 1 = Right channel zero cross is detected. | ||
| This bit is cleared by writing 1. | ||
| [23] | LZCF | Left Channel Zero Cross Flag |
| It indicates the next sample data sign bit of left channel is changed or all data bits are zero. | ||
| 0 = No zero cross. | ||
| 1 = Left channel zero cross is detected. | ||
| This bit is cleared by writing 1. | ||
| [27:24] | RX_LEVEL | Receive FIFO Level |
| These bits indicate the number of word(s) in the receiving FIFO | ||
| [31:28] | TX_LEVEL | Transmitting FIFO Level |
| These bits indicate the number of word(s) in the transmitting FIFO |
Definition at line 5090 of file Nano100Series.h.
| __O uint32_t I2S_T::TXFIFO |
| Bits | Field | Descriptions |
|---|---|---|
| [31:0] | TXFIFO | Transmitting FIFO Register |
| I2S contains 8 words (8x32-bit) data buffer for data transmitting. | ||
| Write data to this register in order to prepare data for transmitting. | ||
| The remaining word number is indicated by TX_LEVEL[3:0] in the I2S_STATUS register. | ||
| This register is write only. |
Definition at line 5105 of file Nano100Series.h.
1.8.15