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Nano100AN Series BSP
V3.02.002
The Board Support Package for Nano100AN Series
|
Macros | |
| #define | FLASH_BASE ((uint32_t)0x00000000) |
| Flash base address. More... | |
| #define | SRAM_BASE ((uint32_t)0x20000000) |
| SRAM base address. More... | |
| #define | APB1PERIPH_BASE ((uint32_t)0x40000000) |
| APB1 base address. More... | |
| #define | APB2PERIPH_BASE ((uint32_t)0x40100000) |
| APB2 base address. More... | |
| #define | AHBPERIPH_BASE ((uint32_t)0x50000000) |
| AHB base address. More... | |
| #define | WDT_BASE (APB1PERIPH_BASE + 0x04000) |
| WDT register base address. More... | |
| #define | RTC_BASE (APB1PERIPH_BASE + 0x08000) |
| RTC register base address. More... | |
| #define | TIMER0_BASE (APB1PERIPH_BASE + 0x10000) |
| TIMER0 register base address. More... | |
| #define | TIMER1_BASE (APB1PERIPH_BASE + 0x10100) |
| TIMER1 register base address. More... | |
| #define | I2C0_BASE (APB1PERIPH_BASE + 0x20000) |
| I2C0 register base address. More... | |
| #define | SPI0_BASE (APB1PERIPH_BASE + 0x30000) |
| SPI0 register base address. More... | |
| #define | PWM0_BASE (APB1PERIPH_BASE + 0x40000) |
| PWM0 register base address. More... | |
| #define | UART0_BASE (APB1PERIPH_BASE + 0x50000) |
| UART0 register base address. More... | |
| #define | SPI2_BASE (APB1PERIPH_BASE + 0xD0000) |
| SPI2 register base address. More... | |
| #define | ADC_BASE (APB1PERIPH_BASE + 0xE0000) |
| ADC register base address. More... | |
| #define | TIMER2_BASE (APB2PERIPH_BASE + 0x10000) |
| TIMER2 register base address. More... | |
| #define | TIMER3_BASE (APB2PERIPH_BASE + 0x10100) |
| TIMER3 register base address. More... | |
| #define | I2C1_BASE (APB2PERIPH_BASE + 0x20000) |
| I2C1 register base address. More... | |
| #define | SPI1_BASE (APB2PERIPH_BASE + 0x30000) |
| SPI1 register base address. More... | |
| #define | PWM1_BASE (APB2PERIPH_BASE + 0x40000) |
| PWM1 register base address. More... | |
| #define | UART1_BASE (APB2PERIPH_BASE + 0x50000) |
| UART1 register base address. More... | |
| #define | USBD_BASE (APB1PERIPH_BASE + 0x60000) |
| USBD register base address. More... | |
| #define | SC0_BASE (APB2PERIPH_BASE + 0x90000) |
| SC0 register base address. More... | |
| #define | I2S_BASE (APB2PERIPH_BASE + 0xA0000) |
| I2S register base address. More... | |
| #define | SC1_BASE (APB2PERIPH_BASE + 0xB0000) |
| SC1 register base address. More... | |
| #define | SYS_BASE (AHBPERIPH_BASE + 0x00000) |
| SYS register base address. More... | |
| #define | CLK_BASE (AHBPERIPH_BASE + 0x00200) |
| CLK register base address. More... | |
| #define | GPIOA_BASE (AHBPERIPH_BASE + 0x04000) |
| GPIO port A register base address. More... | |
| #define | GPIOB_BASE (AHBPERIPH_BASE + 0x04040) |
| GPIO port B register base address. More... | |
| #define | GPIOC_BASE (AHBPERIPH_BASE + 0x04080) |
| GPIO port C register base address. More... | |
| #define | GPIOD_BASE (AHBPERIPH_BASE + 0x040C0) |
| GPIO port D register base address. More... | |
| #define | GPIOE_BASE (AHBPERIPH_BASE + 0x04100) |
| GPIO port E register base address. More... | |
| #define | GPIOF_BASE (AHBPERIPH_BASE + 0x04140) |
| GPIO port F register base address. More... | |
| #define | GPIODBNCE_BASE (AHBPERIPH_BASE + 0x04180) |
| GPIO debounce register base address. More... | |
| #define | GPIO_PIN_DATA_BASE (AHBPERIPH_BASE + 0x04200) |
| GPIO bit access register base address. More... | |
| #define | VDMA_BASE (AHBPERIPH_BASE + 0x08000) |
| VDMA register base address. More... | |
| #define | PDMA1_BASE (AHBPERIPH_BASE + 0x08100) |
| PDMA1 register base address. More... | |
| #define | PDMA2_BASE (AHBPERIPH_BASE + 0x08200) |
| PDMA2 register base address. More... | |
| #define | PDMA3_BASE (AHBPERIPH_BASE + 0x08300) |
| PDMA3 register base address. More... | |
| #define | PDMA4_BASE (AHBPERIPH_BASE + 0x08400) |
| PDMA4 register base address. More... | |
| #define | PDMAGCR_BASE (AHBPERIPH_BASE + 0x08F00) |
| PDMA GCR register base address. More... | |
| #define | FMC_BASE (AHBPERIPH_BASE + 0x0C000) |
| FMC register base address. More... | |
| #define | EBI_BASE (AHBPERIPH_BASE + 0x10000) |
| EBI register base address. More... | |
Memory Mapped Structure for NANO100 Series Peripheral
| #define ADC_BASE (APB1PERIPH_BASE + 0xE0000) |
ADC register base address.
Definition at line 10060 of file Nano100Series.h.
| #define AHBPERIPH_BASE ((uint32_t)0x50000000) |
| #define APB1PERIPH_BASE ((uint32_t)0x40000000) |
APB1 base address.
Definition at line 10044 of file Nano100Series.h.
| #define APB2PERIPH_BASE ((uint32_t)0x40100000) |
APB2 base address.
Definition at line 10045 of file Nano100Series.h.
| #define CLK_BASE (AHBPERIPH_BASE + 0x00200) |
CLK register base address.
Definition at line 10074 of file Nano100Series.h.
| #define EBI_BASE (AHBPERIPH_BASE + 0x10000) |
EBI register base address.
Definition at line 10090 of file Nano100Series.h.
| #define FLASH_BASE ((uint32_t)0x00000000) |
Flash base address.
<Peripheral and SRAM base address
Definition at line 10042 of file Nano100Series.h.
| #define FMC_BASE (AHBPERIPH_BASE + 0x0C000) |
FMC register base address.
Definition at line 10089 of file Nano100Series.h.
| #define GPIO_PIN_DATA_BASE (AHBPERIPH_BASE + 0x04200) |
GPIO bit access register base address.
Definition at line 10082 of file Nano100Series.h.
| #define GPIOA_BASE (AHBPERIPH_BASE + 0x04000) |
GPIO port A register base address.
Definition at line 10075 of file Nano100Series.h.
| #define GPIOB_BASE (AHBPERIPH_BASE + 0x04040) |
GPIO port B register base address.
Definition at line 10076 of file Nano100Series.h.
| #define GPIOC_BASE (AHBPERIPH_BASE + 0x04080) |
GPIO port C register base address.
Definition at line 10077 of file Nano100Series.h.
| #define GPIOD_BASE (AHBPERIPH_BASE + 0x040C0) |
GPIO port D register base address.
Definition at line 10078 of file Nano100Series.h.
| #define GPIODBNCE_BASE (AHBPERIPH_BASE + 0x04180) |
GPIO debounce register base address.
Definition at line 10081 of file Nano100Series.h.
| #define GPIOE_BASE (AHBPERIPH_BASE + 0x04100) |
GPIO port E register base address.
Definition at line 10079 of file Nano100Series.h.
| #define GPIOF_BASE (AHBPERIPH_BASE + 0x04140) |
GPIO port F register base address.
Definition at line 10080 of file Nano100Series.h.
| #define I2C0_BASE (APB1PERIPH_BASE + 0x20000) |
I2C0 register base address.
Definition at line 10055 of file Nano100Series.h.
| #define I2C1_BASE (APB2PERIPH_BASE + 0x20000) |
I2C1 register base address.
Definition at line 10064 of file Nano100Series.h.
| #define I2S_BASE (APB2PERIPH_BASE + 0xA0000) |
I2S register base address.
Definition at line 10070 of file Nano100Series.h.
| #define PDMA1_BASE (AHBPERIPH_BASE + 0x08100) |
PDMA1 register base address.
Definition at line 10084 of file Nano100Series.h.
| #define PDMA2_BASE (AHBPERIPH_BASE + 0x08200) |
PDMA2 register base address.
Definition at line 10085 of file Nano100Series.h.
| #define PDMA3_BASE (AHBPERIPH_BASE + 0x08300) |
PDMA3 register base address.
Definition at line 10086 of file Nano100Series.h.
| #define PDMA4_BASE (AHBPERIPH_BASE + 0x08400) |
PDMA4 register base address.
Definition at line 10087 of file Nano100Series.h.
| #define PDMAGCR_BASE (AHBPERIPH_BASE + 0x08F00) |
PDMA GCR register base address.
Definition at line 10088 of file Nano100Series.h.
| #define PWM0_BASE (APB1PERIPH_BASE + 0x40000) |
PWM0 register base address.
Definition at line 10057 of file Nano100Series.h.
| #define PWM1_BASE (APB2PERIPH_BASE + 0x40000) |
PWM1 register base address.
Definition at line 10066 of file Nano100Series.h.
| #define RTC_BASE (APB1PERIPH_BASE + 0x08000) |
RTC register base address.
Definition at line 10052 of file Nano100Series.h.
| #define SC0_BASE (APB2PERIPH_BASE + 0x90000) |
SC0 register base address.
Definition at line 10069 of file Nano100Series.h.
| #define SC1_BASE (APB2PERIPH_BASE + 0xB0000) |
SC1 register base address.
Definition at line 10071 of file Nano100Series.h.
| #define SPI0_BASE (APB1PERIPH_BASE + 0x30000) |
SPI0 register base address.
Definition at line 10056 of file Nano100Series.h.
| #define SPI1_BASE (APB2PERIPH_BASE + 0x30000) |
SPI1 register base address.
Definition at line 10065 of file Nano100Series.h.
| #define SPI2_BASE (APB1PERIPH_BASE + 0xD0000) |
SPI2 register base address.
Definition at line 10059 of file Nano100Series.h.
| #define SRAM_BASE ((uint32_t)0x20000000) |
SRAM base address.
Definition at line 10043 of file Nano100Series.h.
| #define SYS_BASE (AHBPERIPH_BASE + 0x00000) |
SYS register base address.
Definition at line 10073 of file Nano100Series.h.
| #define TIMER0_BASE (APB1PERIPH_BASE + 0x10000) |
TIMER0 register base address.
Definition at line 10053 of file Nano100Series.h.
| #define TIMER1_BASE (APB1PERIPH_BASE + 0x10100) |
TIMER1 register base address.
Definition at line 10054 of file Nano100Series.h.
| #define TIMER2_BASE (APB2PERIPH_BASE + 0x10000) |
TIMER2 register base address.
Definition at line 10062 of file Nano100Series.h.
| #define TIMER3_BASE (APB2PERIPH_BASE + 0x10100) |
TIMER3 register base address.
Definition at line 10063 of file Nano100Series.h.
| #define UART0_BASE (APB1PERIPH_BASE + 0x50000) |
UART0 register base address.
Definition at line 10058 of file Nano100Series.h.
| #define UART1_BASE (APB2PERIPH_BASE + 0x50000) |
UART1 register base address.
Definition at line 10067 of file Nano100Series.h.
| #define USBD_BASE (APB1PERIPH_BASE + 0x60000) |
USBD register base address.
Definition at line 10068 of file Nano100Series.h.
| #define VDMA_BASE (AHBPERIPH_BASE + 0x08000) |
VDMA register base address.
Definition at line 10083 of file Nano100Series.h.
| #define WDT_BASE (APB1PERIPH_BASE + 0x04000) |
WDT register base address.
Definition at line 10050 of file Nano100Series.h.
1.8.15