| Nano100AN Series BSP V3.02.002 The Board Support Package for Nano100AN Series

Nano100Series.h
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1 /**************************************************************************/
50 #ifndef __NANO100SERIES_H__
51 #define __NANO100SERIES_H__
52
53 #ifdef __cplusplus
54 extern "C" {
55 #endif
56
67 /******************************************************************************/
68 /* Processor and Core Peripherals */
69 /******************************************************************************/
78 typedef enum IRQn
79 {
80 /****** Cortex-M0 Processor Exceptions Numbers *****************************************/
81
82 NonMaskableInt_IRQn = -14,
83 HardFault_IRQn = -13,
84 SVCall_IRQn = -5,
85 PendSV_IRQn = -2,
86 SysTick_IRQn = -1,
88 /****** Nano100 specific Interrupt Numbers ***********************************************/
89 BOD_IRQn = 0,
90 WDT_IRQn = 1,
91 EINT0_IRQn = 2,
92 EINT1_IRQn = 3,
93 GPABC_IRQn = 4,
94 GPDEF_IRQn = 5,
95 PWM0_IRQn = 6,
96 PWM1_IRQn = 7,
97 TMR0_IRQn = 8,
98 TMR1_IRQn = 9,
99 TMR2_IRQn = 10,
100 TMR3_IRQn = 11,
101 UART0_IRQn = 12,
102 UART1_IRQn = 13,
103 SPI0_IRQn = 14,
104 SPI1_IRQn = 15,
105 SPI2_IRQn = 16,
106 HIRC_IRQn = 17,
107 I2C0_IRQn = 18,
108 I2C1_IRQn = 19,
109 SC0_IRQn = 21,
110 SC1_IRQn = 22,
111 USBD_IRQn = 23,
112 PDMA_IRQn = 26,
113 I2S_IRQn = 27,
114 PDWU_IRQn = 28,
115 ADC_IRQn = 29,
116 RTC_IRQn = 31
117 } IRQn_Type;
118
119
120 /*
121 * ==========================================================================
122 * ----------- Processor and Core Peripheral Section ------------------------
123 * ==========================================================================
124 */
125
126 /* Configuration of the Cortex-M0 Processor and Core Peripherals */
127 #define __CM0_REV 0x0201
128 #define __NVIC_PRIO_BITS 2
129 #define __Vendor_SysTickConfig 0
130 #define __MPU_PRESENT 0
131 #define __FPU_PRESENT 0
133 /* end of group NANO100_CMSIS */
134
135
136 #include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
137 #include "system_Nano100Series.h" /* Nano100 Series System include file */
138 #include <stdint.h>
139
140 /******************************************************************************/
141 /* Device Specific Peripheral registers structures */
142 /******************************************************************************/
148 #if defined ( __CC_ARM )
149 #pragma anon_unions
150 #endif
151
152
153 /*---------------------- Analog to Digital Converter -------------------------*/
159 typedef struct
160 {
161
162
173 __I uint32_t RESULT[11];
174
176 uint32_t RESERVE0[1];
178
179
245 __IO uint32_t CR;
246
289 __IO uint32_t CHEN;
290
330 __IO uint32_t CMPR0;
331
371 __IO uint32_t CMPR1;
372
414 __IO uint32_t SR;
415
417 uint32_t RESERVE1[7];
419
431 __I uint32_t PDMA;
432
454 __IO uint32_t DELSEL;
455
456 } ADC_T;
457
463 #define ADC_RESULT_RSLT_Pos (0)
464 #define ADC_RESULT_RSLT_Msk (0xffful << ADC_RESULT_RSLT_Pos)
466 #define ADC_CR_ADEN_Pos (0)
467 #define ADC_CR_ADEN_Msk (0x1ul << ADC_CR_ADEN_Pos)
469 #define ADC_CR_ADIE_Pos (1)
470 #define ADC_CR_ADIE_Msk (0x1ul << ADC_CR_ADIE_Pos)
472 #define ADC_CR_ADMD_Pos (2)
473 #define ADC_CR_ADMD_Msk (0x3ul << ADC_CR_ADMD_Pos)
475 #define ADC_CR_TRGS_Pos (4)
476 #define ADC_CR_TRGS_Msk (0x3ul << ADC_CR_TRGS_Pos)
478 #define ADC_CR_TRGCOND_Pos (6)
479 #define ADC_CR_TRGCOND_Msk (0x3ul << ADC_CR_TRGCOND_Pos)
481 #define ADC_CR_TRGE_Pos (8)
482 #define ADC_CR_TRGE_Msk (0x1ul << ADC_CR_TRGE_Pos)
484 #define ADC_CR_PTEN_Pos (9)
485 #define ADC_CR_PTEN_Msk (0x1ul << ADC_CR_PTEN_Pos)
487 #define ADC_CR_ADST_Pos (11)
488 #define ADC_CR_ADST_Msk (0x1ul << ADC_CR_ADST_Pos)
490 #define ADC_CR_TMSEL_Pos (12)
491 #define ADC_CR_TMSEL_Msk (0x3ul << ADC_CR_TMSEL_Pos)
493 #define ADC_CR_TMTRGMOD_Pos (15)
494 #define ADC_CR_TMTRGMOD_Msk (0x1ul << ADC_CR_TMTRGMOD_Pos)
496 #define ADC_CR_REFSEL_Pos (16)
497 #define ADC_CR_REFSEL_Msk (0x3ul << ADC_CR_REFSEL_Pos)
499 #define ADC_CHEN_CHEN0_Pos (0)
500 #define ADC_CHEN_CHEN0_Msk (0x1ul << ADC_CHEN_CHEN0_Pos)
502 #define ADC_CHEN_CHEN1_Pos (1)
503 #define ADC_CHEN_CHEN1_Msk (0x1ul << ADC_CHEN_CHEN1_Pos)
505 #define ADC_CHEN_CHEN2_Pos (2)
506 #define ADC_CHEN_CHEN2_Msk (0x1ul << ADC_CHEN_CHEN2_Pos)
508 #define ADC_CHEN_CHEN3_Pos (3)
509 #define ADC_CHEN_CHEN3_Msk (0x1ul << ADC_CHEN_CHEN3_Pos)
511 #define ADC_CHEN_CHEN4_Pos (4)
512 #define ADC_CHEN_CHEN4_Msk (0x1ul << ADC_CHEN_CHEN4_Pos)
514 #define ADC_CHEN_CHEN5_Pos (5)
515 #define ADC_CHEN_CHEN5_Msk (0x1ul << ADC_CHEN_CHEN5_Pos)
517 #define ADC_CHEN_CHEN6_Pos (6)
518 #define ADC_CHEN_CHEN6_Msk (0x1ul << ADC_CHEN_CHEN6_Pos)
520 #define ADC_CHEN_CHEN7_Pos (7)
521 #define ADC_CHEN_CHEN7_Msk (0x1ul << ADC_CHEN_CHEN7_Pos)
523 #define ADC_CHEN_CHEN10_Pos (10)
524 #define ADC_CHEN_CHEN10_Msk (0x1ul << ADC_CHEN_CHEN10_Pos)
526 #define ADC_CHEN_CH10SEL_Pos (11)
527 #define ADC_CHEN_CH10SEL_Msk (0x3ul << ADC_CHEN_CH10SEL_Pos)
529 #define ADC_CMPR0_CMPEN_Pos (0)
530 #define ADC_CMPR0_CMPEN_Msk (0x1ul << ADC_CMPR0_CMPEN_Pos)
532 #define ADC_CMPR0_CMPIE_Pos (1)
533 #define ADC_CMPR0_CMPIE_Msk (0x1ul << ADC_CMPR0_CMPIE_Pos)
535 #define ADC_CMPR0_CMPCOND_Pos (2)
536 #define ADC_CMPR0_CMPCOND_Msk (0x1ul << ADC_CMPR0_CMPCOND_Pos)
538 #define ADC_CMPR0_CMPCH_Pos (3)
539 #define ADC_CMPR0_CMPCH_Msk (0xful << ADC_CMPR0_CMPCH_Pos)
541 #define ADC_CMPR0_CMPMATCNT_Pos (8)
542 #define ADC_CMPR0_CMPMATCNT_Msk (0xful << ADC_CMPR0_CMPMATCNT_Pos)
544 #define ADC_CMPR0_CMPD_Pos (16)
545 #define ADC_CMPR0_CMPD_Msk (0xffful << ADC_CMPR0_CMPD_Pos)
547 #define ADC_CMPR1_CMPEN_Pos (0)
548 #define ADC_CMPR1_CMPEN_Msk (0x1ul << ADC_CMPR1_CMPEN_Pos)
550 #define ADC_CMPR1_CMPIE_Pos (1)
551 #define ADC_CMPR1_CMPIE_Msk (0x1ul << ADC_CMPR1_CMPIE_Pos)
553 #define ADC_CMPR1_CMPCOND_Pos (2)
554 #define ADC_CMPR1_CMPCOND_Msk (0x1ul << ADC_CMPR1_CMPCOND_Pos)
556 #define ADC_CMPR1_CMPCH_Pos (3)
557 #define ADC_CMPR1_CMPCH_Msk (0xful << ADC_CMPR1_CMPCH_Pos)
559 #define ADC_CMPR1_CMPMATCNT_Pos (8)
560 #define ADC_CMPR1_CMPMATCNT_Msk (0xful << ADC_CMPR1_CMPMATCNT_Pos)
562 #define ADC_CMPR1_CMPD_Pos (16)
563 #define ADC_CMPR1_CMPD_Msk (0xffful << ADC_CMPR1_CMPD_Pos)
565 #define ADC_SR_ADF_Pos (0)
566 #define ADC_SR_ADF_Msk (0x1ul << ADC_SR_ADF_Pos)
568 #define ADC_SR_CMPF0_Pos (1)
569 #define ADC_SR_CMPF0_Msk (0x1ul << ADC_SR_CMPF0_Pos)
571 #define ADC_SR_CMPF1_Pos (2)
572 #define ADC_SR_CMPF1_Msk (0x1ul << ADC_SR_CMPF1_Pos)
574 #define ADC_SR_BUSY_Pos (3)
575 #define ADC_SR_BUSY_Msk (0x1ul << ADC_SR_BUSY_Pos)
577 #define ADC_SR_CHANNEL_Pos (4)
578 #define ADC_SR_CHANNEL_Msk (0xful << ADC_SR_CHANNEL_Pos)
580 #define ADC_SR_VALID_Pos (8)
581 #define ADC_SR_VALID_Msk (0x4fful << ADC_SR_VALID_Pos)
583 #define ADC_SR_OVERRUN_Pos (20)
584 #define ADC_SR_OVERRUN_Msk (0x4fful << ADC_SR_OVERRUN_Pos)
586 #define ADC_PDMA_AD_PDMA_Pos (0)
587 #define ADC_PDMA_AD_PDMA_Msk (0xffful << ADC_PDMA_AD_PDMA_Pos)
589 #define ADC_DELSEL_En2StDelay_Pos (0)
590 #define ADC_DELSEL_En2StDelay_Msk (0xfful << ADC_DELSEL_En2StDelay_Pos)
592 #define ADC_DELSEL_TMPDMACNT_Pos (8)
593 #define ADC_DELSEL_TMPDMACNT_Msk (0xfful << ADC_DELSEL_TMPDMACNT_Pos)
595 #define ADC_DELSEL_ADCSTHOLDCNT_Pos (16)
596 #define ADC_DELSEL_ADCSTHOLDCNT_Msk (0xfful << ADC_DELSEL_ADCSTHOLDCNT_Pos) /* ADC_CONST */
599 /* end of ADC register group */
600
601
602 /*---------------------- System Clock Controller -------------------------*/
608 typedef struct
609 {
610
611
676 __IO uint32_t PWRCTL;
677
704 __IO uint32_t AHBCLK;
705
786 __IO uint32_t APBCLK;
787
815 __I uint32_t CLKSTATUS;
816
837 __IO uint32_t CLKSEL0;
838
883 __IO uint32_t CLKSEL1;
884
935 __IO uint32_t CLKSEL2;
936
957 __IO uint32_t CLKDIV0;
958
969 __IO uint32_t CLKDIV1;
970
993 __IO uint32_t PLLCTL;
994
1010 __IO uint32_t FRQDIV;
1011
1013 uint32_t RESERVE0[1];
1015
1016
1029 __IO uint32_t WK_IS;
1030
1031 } CLK_T;
1032
1038 #define CLK_PWRCTL_HXT_EN_Pos (0)
1039 #define CLK_PWRCTL_HXT_EN_Msk (0x1ul << CLK_PWRCTL_HXT_EN_Pos)
1041 #define CLK_PWRCTL_LXT_EN_Pos (1)
1042 #define CLK_PWRCTL_LXT_EN_Msk (0x1ul << CLK_PWRCTL_LXT_EN_Pos)
1044 #define CLK_PWRCTL_HIRC_EN_Pos (2)
1045 #define CLK_PWRCTL_HIRC_EN_Msk (0x1ul << CLK_PWRCTL_HIRC_EN_Pos)
1047 #define CLK_PWRCTL_LIRC_EN_Pos (3)
1048 #define CLK_PWRCTL_LIRC_EN_Msk (0x1ul << CLK_PWRCTL_LIRC_EN_Pos)
1050 #define CLK_PWRCTL_WK_DLY_Pos (4)
1051 #define CLK_PWRCTL_WK_DLY_Msk (0x1ul << CLK_PWRCTL_WK_DLY_Pos)
1053 #define CLK_PWRCTL_PD_WK_IE_Pos (5)
1054 #define CLK_PWRCTL_PD_WK_IE_Msk (0x1ul << CLK_PWRCTL_PD_WK_IE_Pos)
1056 #define CLK_PWRCTL_PD_EN_Pos (6)
1057 #define CLK_PWRCTL_PD_EN_Msk (0x1ul << CLK_PWRCTL_PD_EN_Pos)
1059 #define CLK_PWRCTL_HXT_SELXT_Pos (8)
1060 #define CLK_PWRCTL_HXT_SELXT_Msk (0x1ul << CLK_PWRCTL_HXT_SELXT_Pos)
1062 #define CLK_PWRCTL_HXT_GAIN_Pos (9)
1063 #define CLK_PWRCTL_HXT_GAIN_Msk (0x1ul << CLK_PWRCTL_HXT_GAIN_Pos)
1065 #define CLK_PWRCTL_LXT_SCNT_Pos (10)
1066 #define CLK_PWRCTL_LXT_SCNT_Msk (0x1ul << CLK_PWRCTL_LXT_SCNT_Pos)
1068 #define CLK_AHBCLK_GPIO_EN_Pos (0)
1069 #define CLK_AHBCLK_GPIO_EN_Msk (0x1ul << CLK_AHBCLK_GPIO_EN_Pos)
1071 #define CLK_AHBCLK_DMA_EN_Pos (1)
1072 #define CLK_AHBCLK_DMA_EN_Msk (0x1ul << CLK_AHBCLK_DMA_EN_Pos)
1074 #define CLK_AHBCLK_ISP_EN_Pos (2)
1075 #define CLK_AHBCLK_ISP_EN_Msk (0x1ul << CLK_AHBCLK_ISP_EN_Pos)
1077 #define CLK_AHBCLK_EBI_EN_Pos (3)
1078 #define CLK_AHBCLK_EBI_EN_Msk (0x1ul << CLK_AHBCLK_EBI_EN_Pos)
1080 #define CLK_AHBCLK_SRAM_EN_Pos (4)
1081 #define CLK_AHBCLK_SRAM_EN_Msk (0x1ul << CLK_AHBCLK_SRAM_EN_Pos)
1083 #define CLK_AHBCLK_TICK_EN_Pos (5)
1084 #define CLK_AHBCLK_TICK_EN_Msk (0x1ul << CLK_AHBCLK_TICK_EN_Pos)
1086 #define CLK_APBCLK_WDT_EN_Pos (0)
1087 #define CLK_APBCLK_WDT_EN_Msk (0x1ul << CLK_APBCLK_WDT_EN_Pos)
1089 #define CLK_APBCLK_RTC_EN_Pos (1)
1090 #define CLK_APBCLK_RTC_EN_Msk (0x1ul << CLK_APBCLK_RTC_EN_Pos)
1092 #define CLK_APBCLK_TMR0_EN_Pos (2)
1093 #define CLK_APBCLK_TMR0_EN_Msk (0x1ul << CLK_APBCLK_TMR0_EN_Pos)
1095 #define CLK_APBCLK_TMR1_EN_Pos (3)
1096 #define CLK_APBCLK_TMR1_EN_Msk (0x1ul << CLK_APBCLK_TMR1_EN_Pos)
1098 #define CLK_APBCLK_TMR2_EN_Pos (4)
1099 #define CLK_APBCLK_TMR2_EN_Msk (0x1ul << CLK_APBCLK_TMR2_EN_Pos)
1101 #define CLK_APBCLK_TMR3_EN_Pos (5)
1102 #define CLK_APBCLK_TMR3_EN_Msk (0x1ul << CLK_APBCLK_TMR3_EN_Pos)
1104 #define CLK_APBCLK_FDIV_EN_Pos (6)
1105 #define CLK_APBCLK_FDIV_EN_Msk (0x1ul << CLK_APBCLK_FDIV_EN_Pos)
1107 #define CLK_APBCLK_I2C0_EN_Pos (8)
1108 #define CLK_APBCLK_I2C0_EN_Msk (0x1ul << CLK_APBCLK_I2C0_EN_Pos)
1110 #define CLK_APBCLK_I2C1_EN_Pos (9)
1111 #define CLK_APBCLK_I2C1_EN_Msk (0x1ul << CLK_APBCLK_I2C1_EN_Pos)
1113 #define CLK_APBCLK_SPI0_EN_Pos (12)
1114 #define CLK_APBCLK_SPI0_EN_Msk (0x1ul << CLK_APBCLK_SPI0_EN_Pos)
1116 #define CLK_APBCLK_SPI1_EN_Pos (13)
1117 #define CLK_APBCLK_SPI1_EN_Msk (0x1ul << CLK_APBCLK_SPI1_EN_Pos)
1119 #define CLK_APBCLK_SPI2_EN_Pos (14)
1120 #define CLK_APBCLK_SPI2_EN_Msk (0x1ul << CLK_APBCLK_SPI2_EN_Pos)
1122 #define CLK_APBCLK_UART0_EN_Pos (16)
1123 #define CLK_APBCLK_UART0_EN_Msk (0x1ul << CLK_APBCLK_UART0_EN_Pos)
1125 #define CLK_APBCLK_UART1_EN_Pos (17)
1126 #define CLK_APBCLK_UART1_EN_Msk (0x1ul << CLK_APBCLK_UART1_EN_Pos)
1128 #define CLK_APBCLK_PWM0_CH01_EN_Pos (20)
1129 #define CLK_APBCLK_PWM0_CH01_EN_Msk (0x1ul << CLK_APBCLK_PWM0_CH01_EN_Pos)
1131 #define CLK_APBCLK_PWM0_CH23_EN_Pos (21)
1132 #define CLK_APBCLK_PWM0_CH23_EN_Msk (0x1ul << CLK_APBCLK_PWM0_CH23_EN_Pos)
1134 #define CLK_APBCLK_PWM1_CH01_EN_Pos (22)
1135 #define CLK_APBCLK_PWM1_CH01_EN_Msk (0x1ul << CLK_APBCLK_PWM1_CH01_EN_Pos)
1137 #define CLK_APBCLK_PWM1_CH23_EN_Pos (23)
1138 #define CLK_APBCLK_PWM1_CH23_EN_Msk (0x1ul << CLK_APBCLK_PWM1_CH23_EN_Pos)
1140 #define CLK_APBCLK_USBD_EN_Pos (27)
1141 #define CLK_APBCLK_USBD_EN_Msk (0x1ul << CLK_APBCLK_USBD_EN_Pos)
1143 #define CLK_APBCLK_ADC_EN_Pos (28)
1144 #define CLK_APBCLK_ADC_EN_Msk (0x1ul << CLK_APBCLK_ADC_EN_Pos)
1146 #define CLK_APBCLK_I2S_EN_Pos (29)
1147 #define CLK_APBCLK_I2S_EN_Msk (0x1ul << CLK_APBCLK_I2S_EN_Pos)
1149 #define CLK_APBCLK_SC0_EN_Pos (30)
1150 #define CLK_APBCLK_SC0_EN_Msk (0x1ul << CLK_APBCLK_SC0_EN_Pos)
1152 #define CLK_APBCLK_SC1_EN_Pos (31)
1153 #define CLK_APBCLK_SC1_EN_Msk (0x1ul << CLK_APBCLK_SC1_EN_Pos)
1155 #define CLK_CLKSTATUS_HXT_STB_Pos (0)
1156 #define CLK_CLKSTATUS_HXT_STB_Msk (0x1ul << CLK_CLKSTATUS_HXT_STB_Pos)
1158 #define CLK_CLKSTATUS_LXT_STB_Pos (1)
1159 #define CLK_CLKSTATUS_LXT_STB_Msk (0x1ul << CLK_CLKSTATUS_LXT_STB_Pos)
1161 #define CLK_CLKSTATUS_PLL_STB_Pos (2)
1162 #define CLK_CLKSTATUS_PLL_STB_Msk (0x1ul << CLK_CLKSTATUS_PLL_STB_Pos)
1164 #define CLK_CLKSTATUS_LIRC_STB_Pos (3)
1165 #define CLK_CLKSTATUS_LIRC_STB_Msk (0x1ul << CLK_CLKSTATUS_LIRC_STB_Pos)
1167 #define CLK_CLKSTATUS_HIRC_STB_Pos (4)
1168 #define CLK_CLKSTATUS_HIRC_STB_Msk (0x1ul << CLK_CLKSTATUS_HIRC_STB_Pos)
1170 #define CLK_CLKSTATUS_CLK_SW_FAIL_Pos (7)
1171 #define CLK_CLKSTATUS_CLK_SW_FAIL_Msk (0x1ul << CLK_CLKSTATUS_CLK_SW_FAIL_Pos)
1173 #define CLK_CLKSEL0_HCLK_S_Pos (0)
1174 #define CLK_CLKSEL0_HCLK_S_Msk (0x7ul << CLK_CLKSEL0_HCLK_S_Pos)
1176 #define CLK_CLKSEL1_UART_S_Pos (0)
1177 #define CLK_CLKSEL1_UART_S_Msk (0x3ul << CLK_CLKSEL1_UART_S_Pos)
1179 #define CLK_CLKSEL1_ADC_S_Pos (2)
1180 #define CLK_CLKSEL1_ADC_S_Msk (0x3ul << CLK_CLKSEL1_ADC_S_Pos)
1182 #define CLK_CLKSEL1_PWM0_CH01_S_Pos (4)
1183 #define CLK_CLKSEL1_PWM0_CH01_S_Msk (0x3ul << CLK_CLKSEL1_PWM0_CH01_S_Pos)
1185 #define CLK_CLKSEL1_PWM0_CH23_S_Pos (6)
1186 #define CLK_CLKSEL1_PWM0_CH23_S_Msk (0x3ul << CLK_CLKSEL1_PWM0_CH23_S_Pos)
1188 #define CLK_CLKSEL1_TMR0_S_Pos (8)
1189 #define CLK_CLKSEL1_TMR0_S_Msk (0x7ul << CLK_CLKSEL1_TMR0_S_Pos)
1191 #define CLK_CLKSEL1_TMR1_S_Pos (12)
1192 #define CLK_CLKSEL1_TMR1_S_Msk (0x7ul << CLK_CLKSEL1_TMR1_S_Pos)
1194 #define CLK_CLKSEL2_FRQDIV_S_Pos (2)
1195 #define CLK_CLKSEL2_FRQDIV_S_Msk (0x3ul << CLK_CLKSEL2_FRQDIV_S_Pos)
1197 #define CLK_CLKSEL2_PWM1_CH01_S_Pos (4)
1198 #define CLK_CLKSEL2_PWM1_CH01_S_Msk (0x3ul << CLK_CLKSEL2_PWM1_CH01_S_Pos)
1200 #define CLK_CLKSEL2_PWM1_CH23_S_Pos (6)
1201 #define CLK_CLKSEL2_PWM1_CH23_S_Msk (0x3ul << CLK_CLKSEL2_PWM1_CH23_S_Pos)
1203 #define CLK_CLKSEL2_TMR2_S_Pos (8)
1204 #define CLK_CLKSEL2_TMR2_S_Msk (0x7ul << CLK_CLKSEL2_TMR2_S_Pos)
1206 #define CLK_CLKSEL2_TMR3_S_Pos (12)
1207 #define CLK_CLKSEL2_TMR3_S_Msk (0x7ul << CLK_CLKSEL2_TMR3_S_Pos)
1209 #define CLK_CLKSEL2_I2S_S_Pos (16)
1210 #define CLK_CLKSEL2_I2S_S_Msk (0x3ul << CLK_CLKSEL2_I2S_S_Pos)
1212 #define CLK_CLKSEL2_SC_S_Pos (18)
1213 #define CLK_CLKSEL2_SC_S_Msk (0x3ul << CLK_CLKSEL2_SC_S_Pos)
1215 #define CLK_CLKDIV0_HCLK_N_Pos (0)
1216 #define CLK_CLKDIV0_HCLK_N_Msk (0xful << CLK_CLKDIV0_HCLK_N_Pos)
1218 #define CLK_CLKDIV0_USB_N_Pos (4)
1219 #define CLK_CLKDIV0_USB_N_Msk (0xful << CLK_CLKDIV0_USB_N_Pos)
1221 #define CLK_CLKDIV0_UART_N_Pos (8)
1222 #define CLK_CLKDIV0_UART_N_Msk (0xful << CLK_CLKDIV0_UART_N_Pos)
1224 #define CLK_CLKDIV0_I2S_N_Pos (12)
1225 #define CLK_CLKDIV0_I2S_N_Msk (0xful << CLK_CLKDIV0_I2S_N_Pos)
1227 #define CLK_CLKDIV0_ADC_N_Pos (16)
1228 #define CLK_CLKDIV0_ADC_N_Msk (0xfful << CLK_CLKDIV0_ADC_N_Pos)
1230 #define CLK_CLKDIV0_SC0_N_Pos (28)
1231 #define CLK_CLKDIV0_SC0_N_Msk (0xful << CLK_CLKDIV0_SC0_N_Pos)
1233 #define CLK_CLKDIV1_SC1_N_Pos (0)
1234 #define CLK_CLKDIV1_SC1_N_Msk (0xful << CLK_CLKDIV1_SC1_N_Pos)
1236 #define CLK_PLLCTL_FB_DV_Pos (0)
1237 #define CLK_PLLCTL_FB_DV_Msk (0x3ful << CLK_PLLCTL_FB_DV_Pos)
1239 #define CLK_PLLCTL_IN_DV_Pos (8)
1240 #define CLK_PLLCTL_IN_DV_Msk (0x3ul << CLK_PLLCTL_IN_DV_Pos)
1242 #define CLK_PLLCTL_OUT_DV_Pos (12)
1243 #define CLK_PLLCTL_OUT_DV_Msk (0x1ul << CLK_PLLCTL_OUT_DV_Pos)
1245 #define CLK_PLLCTL_PD_Pos (16)
1246 #define CLK_PLLCTL_PD_Msk (0x1ul << CLK_PLLCTL_PD_Pos)
1248 #define CLK_PLLCTL_PLL_SRC_Pos (17)
1249 #define CLK_PLLCTL_PLL_SRC_Msk (0x1ul << CLK_PLLCTL_PLL_SRC_Pos)
1251 #define CLK_FRQDIV_FSEL_Pos (0)
1252 #define CLK_FRQDIV_FSEL_Msk (0xful << CLK_FRQDIV_FSEL_Pos)
1254 #define CLK_FRQDIV_FDIV_EN_Pos (4)
1255 #define CLK_FRQDIV_FDIV_EN_Msk (0x1ul << CLK_FRQDIV_FDIV_EN_Pos)
1257 #define CLK_PD_WK_IS_PD_WK_IS_Pos (0)
1258 #define CLK_PD_WK_IS_PD_WK_IS_Msk (0x1ul << CLK_PD_WK_IS_PD_WK_IS_Pos) /* CLK_CONST */
1261 /* end of CLK register group */
1262
1263
1264 /*---------------------- Peripheral Direct Memory Access Controller -------------------------*/
1270 typedef struct
1271 {
1272
1273
1297 __IO uint32_t GCRCSR;
1298
1343 __IO uint32_t DSSR0;
1344
1358 __IO uint32_t DSSR1;
1359
1383 __I uint32_t GCRISR;
1384
1385 } DMA_GCR_T;
1386
1387
1388 typedef struct
1389 {
1390
1391
1444 __IO uint32_t CSR;
1445
1457 __IO uint32_t SAR;
1458
1470 __IO uint32_t DAR;
1471
1483 __IO uint32_t BCR;
1484
1486 uint32_t RESERVE0[1];
1488
1489
1500 __I uint32_t CSAR;
1501
1512 __I uint32_t CDAR;
1513
1525 __I uint32_t CBCR;
1526
1548 __IO uint32_t IER;
1549
1581 __IO uint32_t ISR;
1582
1594 __IO uint32_t TCR;
1595
1597 uint32_t RESERVE1[21];
1599
1600
1611 __I uint32_t BUF;
1612
1613 } PDMA_T;
1614
1615
1616 typedef struct
1617 {
1618
1619
1649 __IO uint32_t CSR;
1650
1661 __IO uint32_t SAR;
1662
1673 __IO uint32_t DAR;
1674
1686 __IO uint32_t BCR;
1687
1689 uint32_t RESERVE0[1];
1691
1692
1703 __I uint32_t CSAR;
1704
1715 __I uint32_t CDAR;
1716
1727 __I uint32_t CBCR;
1728
1743 __IO uint32_t IER;
1744
1765 __IO uint32_t ISR;
1766
1768 uint32_t RESERVE1[1];
1770
1771
1784 __IO uint32_t SASOCR;
1785
1796 __IO uint32_t DASOCR;
1797
1799 uint32_t RESERVE2[19];
1801
1802
1813 __I uint32_t BUF0;
1814
1825 __I uint32_t BUF1;
1826
1827 } VDMA_T;
1828
1829
1835 #define DMA_GCR_GCRCSR_CLK0_EN_Pos (8)
1836 #define DMA_GCR_GCRCSR_CLK0_EN_Msk (0x1ul << DMA_GCR_GCRCSR_CLK0_EN_Pos)
1838 #define DMA_GCR_GCRCSR_CLK1_EN_Pos (9)
1839 #define DMA_GCR_GCRCSR_CLK1_EN_Msk (0x1ul << DMA_GCR_GCRCSR_CLK1_EN_Pos)
1841 #define DMA_GCR_GCRCSR_CLK2_EN_Pos (10)
1842 #define DMA_GCR_GCRCSR_CLK2_EN_Msk (0x1ul << DMA_GCR_GCRCSR_CLK2_EN_Pos)
1844 #define DMA_GCR_GCRCSR_CLK3_EN_Pos (11)
1845 #define DMA_GCR_GCRCSR_CLK3_EN_Msk (0x1ul << DMA_GCR_GCRCSR_CLK3_EN_Pos)
1847 #define DMA_GCR_GCRCSR_CLK4_EN_Pos (12)
1848 #define DMA_GCR_GCRCSR_CLK4_EN_Msk (0x1ul << DMA_GCR_GCRCSR_CLK4_EN_Pos)
1850 #define DMA_GCR_DSSR0_CH1_SEL_Pos (8)
1851 #define DMA_GCR_DSSR0_CH1_SEL_Msk (0x1ful << DMA_GCR_DSSR0_CH1_SEL_Pos)
1853 #define DMA_GCR_DSSR0_CH2_SEL_Pos (16)
1854 #define DMA_GCR_DSSR0_CH2_SEL_Msk (0x1ful << DMA_GCR_DSSR0_CH2_SEL_Pos)
1856 #define DMA_GCR_DSSR0_CH3_SEL_Pos (24)
1857 #define DMA_GCR_DSSR0_CH3_SEL_Msk (0x1ful << DMA_GCR_DSSR0_CH3_SEL_Pos)
1859 #define DMA_GCR_DSSR1_CH4_SEL_Pos (0)
1860 #define DMA_GCR_DSSR1_CH4_SEL_Msk (0x1ful << DMA_GCR_DSSR1_CH4_SEL_Pos)
1862 #define DMA_GCR_GCRISR_INTR0_Pos (0)
1863 #define DMA_GCR_GCRISR_INTR0_Msk (0x1ul << DMA_GCR_GCRISR_INTR0_Pos)
1865 #define DMA_GCR_GCRISR_INTR1_Pos (1)
1866 #define DMA_GCR_GCRISR_INTR1_Msk (0x1ul << DMA_GCR_GCRISR_INTR1_Pos)
1868 #define DMA_GCR_GCRISR_INTR2_Pos (2)
1869 #define DMA_GCR_GCRISR_INTR2_Msk (0x1ul << DMA_GCR_GCRISR_INTR2_Pos)
1871 #define DMA_GCR_GCRISR_INTR3_Pos (3)
1872 #define DMA_GCR_GCRISR_INTR3_Msk (0x1ul << DMA_GCR_GCRISR_INTR3_Pos)
1874 #define DMA_GCR_GCRISR_INTR4_Pos (4)
1875 #define DMA_GCR_GCRISR_INTR4_Msk (0x1ul << DMA_GCR_GCRISR_INTR4_Pos) /* DMA_GCR_CONST */
1878
1884 #define PDMA_CSR_PDMACEN_Pos (0)
1885 #define PDMA_CSR_PDMACEN_Msk (0x1ul << PDMA_CSR_PDMACEN_Pos)
1887 #define PDMA_CSR_SW_RST_Pos (1)
1888 #define PDMA_CSR_SW_RST_Msk (0x1ul << PDMA_CSR_SW_RST_Pos)
1890 #define PDMA_CSR_MODE_SEL_Pos (2)
1891 #define PDMA_CSR_MODE_SEL_Msk (0x3ul << PDMA_CSR_MODE_SEL_Pos)
1893 #define PDMA_CSR_SAD_SEL_Pos (4)
1894 #define PDMA_CSR_SAD_SEL_Msk (0x3ul << PDMA_CSR_SAD_SEL_Pos)
1896 #define PDMA_CSR_DAD_SEL_Pos (6)
1897 #define PDMA_CSR_DAD_SEL_Msk (0x3ul << PDMA_CSR_DAD_SEL_Pos)
1899 #define PDMA_CSR_TO_EN_Pos (12)
1900 #define PDMA_CSR_TO_EN_Msk (0x1ul << PDMA_CSR_TO_EN_Pos)
1902 #define PDMA_CSR_APB_TWS_Pos (19)
1903 #define PDMA_CSR_APB_TWS_Msk (0x3ul << PDMA_CSR_APB_TWS_Pos)
1905 #define PDMA_CSR_TRIG_EN_Pos (23)
1906 #define PDMA_CSR_TRIG_EN_Msk (0x1ul << PDMA_CSR_TRIG_EN_Pos)
1908 #define PDMA_SAR_PDMA_SAR_Pos (0)
1909 #define PDMA_SAR_PDMA_SAR_Msk (0xfffffffful << PDMA_SAR_PDMA_SAR_Pos)
1911 #define PDMA_DAR_PDMA_DAR_Pos (0)
1912 #define PDMA_DAR_PDMA_DAR_Msk (0xfffffffful << PDMA_DAR_PDMA_DAR_Pos)
1914 #define PDMA_BCR_PDMA_BCR_Pos (0)
1915 #define PDMA_BCR_PDMA_BCR_Msk (0xfffful << PDMA_BCR_PDMA_BCR_Pos)
1917 #define PDMA_CSAR_PDMA_CSAR_Pos (0)
1918 #define PDMA_CSAR_PDMA_CSAR_Msk (0xfffffffful << PDMA_CSAR_PDMA_CSAR_Pos)
1920 #define PDMA_CDAR_PDMA_CDAR_Pos (0)
1921 #define PDMA_CDAR_PDMA_CDAR_Msk (0xfffffffful << PDMA_CDAR_PDMA_CDAR_Pos)
1923 #define PDMA_CBCR_PDMA_CBCR_Pos (0)
1924 #define PDMA_CBCR_PDMA_CBCR_Msk (0xfffffful << PDMA_CBCR_PDMA_CBCR_Pos)
1926 #define PDMA_IER_TABORT_IE_Pos (0)
1927 #define PDMA_IER_TABORT_IE_Msk (0x1ul << PDMA_IER_TABORT_IE_Pos)
1929 #define PDMA_IER_TD_IE_Pos (1)
1930 #define PDMA_IER_TD_IE_Msk (0x1ul << PDMA_IER_TD_IE_Pos)
1932 #define PDMA_IER_WRA_BCR_IE_Pos (2)
1933 #define PDMA_IER_WRA_BCR_IE_Msk (0xful << PDMA_IER_WRA_BCR_IE_Pos)
1935 #define PDMA_IER_TO_IE_Pos (6)
1936 #define PDMA_IER_TO_IE_Msk (0x1ul << PDMA_IER_TO_IE_Pos)
1938 #define PDMA_ISR_TABORT_IS_Pos (0)
1939 #define PDMA_ISR_TABORT_IS_Msk (0x1ul << PDMA_ISR_TABORT_IS_Pos)
1941 #define PDMA_ISR_TD_IS_Pos (1)
1942 #define PDMA_ISR_TD_IS_Msk (0x1ul << PDMA_ISR_TD_IS_Pos)
1944 #define PDMA_ISR_WRA_BCR_IS_Pos (2)
1945 #define PDMA_ISR_WRA_BCR_IS_Msk (0xful << PDMA_ISR_WRA_BCR_IS_Pos)
1947 #define PDMA_ISR_TO_IS_Pos (6)
1948 #define PDMA_ISR_TO_IS_Msk (0x1ul << PDMA_ISR_TO_IS_Pos)
1950 #define PDMA_TCR_PDMA_TCR_Pos (0)
1951 #define PDMA_TCR_PDMA_TCR_Msk (0xfffful << PDMA_TCR_PDMA_TCR_Pos)
1953 #define PDMA_BUF_PDMA_BUF_Pos (0)
1954 #define PDMA_BUF_PDMA_BUF_Msk (0xfffffffful << PDMA_BUF_PDMA_BUF_Pos) /* PDMA_CONST */
1957
1963 #define VDMA_CSR_VDMACEN_Pos (0)
1964 #define VDMA_CSR_VDMACEN_Msk (0x1ul << VDMA_CSR_VDMACEN_Pos)
1966 #define VDMA_CSR_SW_RST_Pos (1)
1967 #define VDMA_CSR_SW_RST_Msk (0x1ul << VDMA_CSR_SW_RST_Pos)
1969 #define VDMA_CSR_STRIDE_EN_Pos (10)
1970 #define VDMA_CSR_STRIDE_EN_Msk (0x1ul << VDMA_CSR_STRIDE_EN_Pos)
1972 #define VDMA_CSR_DIR_SEL_Pos (11)
1973 #define VDMA_CSR_DIR_SEL_Msk (0x1ul << VDMA_CSR_DIR_SEL_Pos)
1975 #define VDMA_CSR_TRIG_EN_Pos (23)
1976 #define VDMA_CSR_TRIG_EN_Msk (0x1ul << VDMA_CSR_TRIG_EN_Pos)
1978 #define VDMA_SAR_VDMA_SAR_Pos (0)
1979 #define VDMA_SAR_VDMA_SAR_Msk (0xfffffffful << VDMA_SAR_VDMA_SAR_Pos)
1981 #define VDMA_DAR_VDMA_DAR_Pos (0)
1982 #define VDMA_DAR_VDMA_DAR_Msk (0xfffffffful << VDMA_DAR_VDMA_DAR_Pos)
1984 #define VDMA_BCR_VDMA_BCR_Pos (0)
1985 #define VDMA_BCR_VDMA_BCR_Msk (0xfffful << VDMA_BCR_VDMA_BCR_Pos)
1987 #define VDMA_CSAR_VDMA_CSAR_Pos (0)
1988 #define VDMA_CSAR_VDMA_CSAR_Msk (0xfffffffful << VDMA_CSAR_VDMA_CSAR_Pos)
1990 #define VDMA_CDAR_VDMA_CDAR_Pos (0)
1991 #define VDMA_CDAR_VDMA_CDAR_Msk (0xfffffffful << VDMA_CDAR_VDMA_CDAR_Pos)
1993 #define VDMA_CBCR_VDMA_CBCR_Pos (0)
1994 #define VDMA_CBCR_VDMA_CBCR_Msk (0xfffful << VDMA_CBCR_VDMA_CBCR_Pos)
1996 #define VDMA_IER_TABORT_IE_Pos (0)
1997 #define VDMA_IER_TABORT_IE_Msk (0x1ul << VDMA_IER_TABORT_IE_Pos)
1999 #define VDMA_IER_TD_IE_Pos (1)
2000 #define VDMA_IER_TD_IE_Msk (0x1ul << VDMA_IER_TD_IE_Pos)
2002 #define VDMA_ISR_TABORT_IS_Pos (0)
2003 #define VDMA_ISR_TABORT_IS_Msk (0x1ul << VDMA_ISR_TABORT_IS_Pos)
2005 #define VDMA_ISR_TD_IS_Pos (1)
2006 #define VDMA_ISR_TD_IS_Msk (0x1ul << VDMA_ISR_TD_IS_Pos)
2008 #define VDMA_SASOCR_SASTOBL_Pos (0)
2009 #define VDMA_SASOCR_SASTOBL_Msk (0xfffful << VDMA_SASOCR_SASTOBL_Pos)
2011 #define VDMA_SASOCR_STBC_Pos (16)
2012 #define VDMA_SASOCR_STBC_Msk (0xfffful << VDMA_SASOCR_STBC_Pos)
2014 #define VDMA_DASOCR_DASTOBL_Pos (0)
2015 #define VDMA_DASOCR_DASTOBL_Msk (0xfffful << VDMA_DASOCR_DASTOBL_Pos)
2017 #define VDMA_BUF0_VDMA_BUF0_Pos (0)
2018 #define VDMA_BUF0_VDMA_BUF0_Msk (0xfffffffful << VDMA_BUF0_VDMA_BUF0_Pos)
2020 #define VDMA_BUF1_VDMA_BUF1_Pos (0)
2021 #define VDMA_BUF1_VDMA_BUF1_Msk (0xfffffffful << VDMA_BUF1_VDMA_BUF1_Pos) /* VDMA_CONST */
2024 /* end of DMA register group */
2025
2026
2027 /*---------------------- External Bus Interface Controller -------------------------*/
2033 typedef struct
2034 {
2035
2036
2073 __IO uint32_t EBICON;
2074
2098 __IO uint32_t EXTIME;
2099
2100 } EBI_T;
2101
2107 #define EBI_EBICON_ExtEN_Pos (0)
2108 #define EBI_EBICON_ExtEN_Msk (0x1ul << EBI_EBICON_ExtEN_Pos)
2110 #define EBI_EBICON_ExtBW16_Pos (1)
2111 #define EBI_EBICON_ExtBW16_Msk (0x1ul << EBI_EBICON_ExtBW16_Pos)
2113 #define EBI_EBICON_MCLKDIV_Pos (8)
2114 #define EBI_EBICON_MCLKDIV_Msk (0x7ul << EBI_EBICON_MCLKDIV_Pos)
2116 #define EBI_EBICON_MCLKEN_Pos (11)
2117 #define EBI_EBICON_MCLKEN_Msk (0x1ul << EBI_EBICON_MCLKEN_Pos)
2119 #define EBI_EBICON_ExttALE_Pos (16)
2120 #define EBI_EBICON_ExttALE_Msk (0x7ul << EBI_EBICON_ExttALE_Pos)
2122 #define EBI_EXTIME_ExttACC_Pos (0)
2123 #define EBI_EXTIME_ExttACC_Msk (0x1ful << EBI_EXTIME_ExttACC_Pos)
2125 #define EBI_EXTIME_ExttAHD_Pos (8)
2126 #define EBI_EXTIME_ExttAHD_Msk (0x7ul << EBI_EXTIME_ExttAHD_Pos)
2128 #define EBI_EXTIME_ExtIW2X_Pos (12)
2129 #define EBI_EXTIME_ExtIW2X_Msk (0xful << EBI_EXTIME_ExtIW2X_Pos)
2131 #define EBI_EXTIME_ExtIR2W_Pos (16)
2132 #define EBI_EXTIME_ExtIR2W_Msk (0xful << EBI_EXTIME_ExtIR2W_Pos)
2134 #define EBI_EXTIME_ExtIR2R_Pos (24)
2135 #define EBI_EXTIME_ExtIR2R_Msk (0xful << EBI_EXTIME_ExtIR2R_Pos) /* EBI_CONST */
2138 /* end of EBI register group */
2139
2140
2141 /*---------------------- Flash Memory Controller -------------------------*/
2147 typedef struct
2148 {
2149
2150
2209 __IO uint32_t ISPCON;
2210
2221 __IO uint32_t ISPADR;
2222
2234 __IO uint32_t ISPDAT;
2235
2255 __IO uint32_t ISPCMD;
2256
2269 __IO uint32_t ISPTRG;
2270
2283 __I uint32_t DFBADR;
2284
2286 uint32_t RESERVE0[10];
2288
2289
2314 __IO uint32_t ISPSTA;
2315
2316 } FMC_T;
2317
2323 #define FMC_ISPCON_ISPEN_Pos (0)
2324 #define FMC_ISPCON_ISPEN_Msk (0x1ul << FMC_ISPCON_ISPEN_Pos)
2326 #define FMC_ISPCON_BS_Pos (1)
2327 #define FMC_ISPCON_BS_Msk (0x1ul << FMC_ISPCON_BS_Pos)
2329 #define FMC_ISPCON_APUEN_Pos (3)
2330 #define FMC_ISPCON_APUEN_Msk (0x1ul << FMC_ISPCON_APUEN_Pos)
2332 #define FMC_ISPCON_CFGUEN_Pos (4)
2333 #define FMC_ISPCON_CFGUEN_Msk (0x1ul << FMC_ISPCON_CFGUEN_Pos)
2335 #define FMC_ISPCON_LDUEN_Pos (5)
2336 #define FMC_ISPCON_LDUEN_Msk (0x1ul << FMC_ISPCON_LDUEN_Pos)
2338 #define FMC_ISPCON_ISPFF_Pos (6)
2339 #define FMC_ISPCON_ISPFF_Msk (0x1ul << FMC_ISPCON_ISPFF_Pos)
2341 #define FMC_ISPCON_SWRST_Pos (7)
2342 #define FMC_ISPCON_SWRST_Msk (0x1ul << FMC_ISPCON_SWRST_Pos)
2344 #define FMC_ISPCON_PT_Pos (8)
2345 #define FMC_ISPCON_PT_Msk (0x7ul << FMC_ISPCON_PT_Pos)
2347 #define FMC_ISPCON_ET_Pos (12)
2348 #define FMC_ISPCON_ET_Msk (0x7ul << FMC_ISPCON_ET_Pos)
2350 #define FMC_ISPADR_ISPADR_Pos (0)
2351 #define FMC_ISPADR_ISPADR_Msk (0xfffffffful << FMC_ISPADR_ISPADR_Pos)
2353 #define FMC_ISPDAT_ISPDAT_Pos (0)
2354 #define FMC_ISPDAT_ISPDAT_Msk (0xfffffffful << FMC_ISPDAT_ISPDAT_Pos)
2356 #define FMC_ISPCMD_FCTRL_Pos (0)
2357 #define FMC_ISPCMD_FCTRL_Msk (0xful << FMC_ISPCMD_FCTRL_Pos)
2359 #define FMC_ISPCMD_FCEN_Pos (4)
2360 #define FMC_ISPCMD_FCEN_Msk (0x1ul << FMC_ISPCMD_FCEN_Pos)
2362 #define FMC_ISPCMD_FOEN_Pos (5)
2363 #define FMC_ISPCMD_FOEN_Msk (0x1ul << FMC_ISPCMD_FOEN_Pos)
2365 #define FMC_ISPTRG_ISPGO_Pos (0)
2366 #define FMC_ISPTRG_ISPGO_Msk (0x1ul << FMC_ISPTRG_ISPGO_Pos)
2368 #define FMC_DFBADR_DFBA_Pos (0)
2369 #define FMC_DFBADR_DFBA_Msk (0xfffffffful << FMC_DFBADR_DFBA_Pos)
2371 #define FMC_ISPSTA_ISPBUSY_Pos (0)
2372 #define FMC_ISPSTA_ISPBUSY_Msk (0x1ul << FMC_ISPSTA_ISPBUSY_Pos)
2374 #define FMC_ISPSTA_CBS_Pos (1)
2375 #define FMC_ISPSTA_CBS_Msk (0x3ul << FMC_ISPSTA_CBS_Pos)
2377 #define FMC_ISPSTA_ISPFF_Pos (6)
2378 #define FMC_ISPSTA_ISPFF_Msk (0x1ul << FMC_ISPSTA_ISPFF_Pos) /* FMC_CONST */
2381 /* end of FMC register group */
2382
2383
2384 /*---------------------- System Global Control Registers -------------------------*/
2390 typedef struct
2391 {
2392
2393
2405 __I uint32_t PDID;
2406
2445 __IO uint32_t RST_SRC;
2446
2483 __IO uint32_t IPRST_CTL1;
2484
2550 __IO uint32_t IPRST_CTL2;
2551
2565 __IO uint32_t CPR;
2566
2568 uint32_t RESERVE0[3];
2570
2571
2583 __IO uint32_t TEMPCTL;
2584
2586 uint32_t RESERVE1[3];
2588
2589
2637 __IO uint32_t PA_L_MFP;
2638
2693 __IO uint32_t PA_H_MFP;
2694
2740 __IO uint32_t PB_L_MFP;
2741
2785 __IO uint32_t PB_H_MFP;
2786
2834 __IO uint32_t PC_L_MFP;
2835
2884 __IO uint32_t PC_H_MFP;
2885
2929 __IO uint32_t PD_L_MFP;
2930
2955 __IO uint32_t PD_H_MFP;
2956
2989 __IO uint32_t PE_L_MFP;
2990
3019 __IO uint32_t PE_H_MFP;
3020
3050 __IO uint32_t PF_L_MFP;
3051
3053 uint32_t RESERVE2[1];
3055
3056
3069 __IO uint32_t PORCTL;
3070
3127 __IO uint32_t BODCTL;
3128
3159 __IO uint32_t BODSTS;
3160
3196 __IO uint32_t VREFCTL;
3197
3199 uint32_t RESERVE3[4];
3201
3202
3234 __IO uint32_t IRCTRIMCTL;
3235
3254 __IO uint32_t IRCTRIMIEN;
3255
3281 __IO uint32_t IRCTRIMINT;
3282
3284 uint32_t RESERVE4[29];
3286
3287
3299 __IO uint32_t RegLockAddr;
3300
3301 } SYS_T;
3302
3309 #define SYS_PDID_PDID_Pos (0)
3310 #define SYS_PDID_PDID_Msk (0xfffffffful << SYS_PDID_PDID_Pos)
3312 #define SYS_RST_SRC_RSTS_POR_Pos (0)
3313 #define SYS_RST_SRC_RSTS_POR_Msk (0x1ul << SYS_RST_SRC_RSTS_POR_Pos)
3315 #define SYS_RST_SRC_RSTS_PAD_Pos (1)
3316 #define SYS_RST_SRC_RSTS_PAD_Msk (0x1ul << SYS_RST_SRC_RSTS_PAD_Pos)
3318 #define SYS_RST_SRC_RSTS_WDT_Pos (2)
3319 #define SYS_RST_SRC_RSTS_WDT_Msk (0x1ul << SYS_RST_SRC_RSTS_WDT_Pos)
3321 #define SYS_RST_SRC_RSTS_BOD_Pos (4)
3322 #define SYS_RST_SRC_RSTS_BOD_Msk (0x1ul << SYS_RST_SRC_RSTS_BOD_Pos)
3324 #define SYS_RST_SRC_RSTS_SYS_Pos (5)
3325 #define SYS_RST_SRC_RSTS_SYS_Msk (0x1ul << SYS_RST_SRC_RSTS_SYS_Pos)
3327 #define SYS_RST_SRC_RSTS_CPU_Pos (7)
3328 #define SYS_RST_SRC_RSTS_CPU_Msk (0x1ul << SYS_RST_SRC_RSTS_CPU_Pos)
3330 #define SYS_IPRST_CTL1_CHIP_RST_Pos (0)
3331 #define SYS_IPRST_CTL1_CHIP_RST_Msk (0x1ul << SYS_IPRST_CTL1_CHIP_RST_Pos)
3333 #define SYS_IPRST_CTL1_CPU_RST_Pos (1)
3334 #define SYS_IPRST_CTL1_CPU_RST_Msk (0x1ul << SYS_IPRST_CTL1_CPU_RST_Pos)
3336 #define SYS_IPRST_CTL1_DMA_RST_Pos (2)
3337 #define SYS_IPRST_CTL1_DMA_RST_Msk (0x1ul << SYS_IPRST_CTL1_DMA_RST_Pos)
3339 #define SYS_IPRST_CTL1_EBI_RST_Pos (3)
3340 #define SYS_IPRST_CTL1_EBI_RST_Msk (0x1ul << SYS_IPRST_CTL1_EBI_RST_Pos)
3342 #define SYS_IPRST_CTL2_GPIO_RST_Pos (1)
3343 #define SYS_IPRST_CTL2_GPIO_RST_Msk (0x1ul << SYS_IPRST_CTL2_GPIO_RST_Pos)
3345 #define SYS_IPRST_CTL2_TMR0_RST_Pos (2)
3346 #define SYS_IPRST_CTL2_TMR0_RST_Msk (0x1ul << SYS_IPRST_CTL2_TMR0_RST_Pos)
3348 #define SYS_IPRST_CTL2_TMR1_RST_Pos (3)
3349 #define SYS_IPRST_CTL2_TMR1_RST_Msk (0x1ul << SYS_IPRST_CTL2_TMR1_RST_Pos)
3351 #define SYS_IPRST_CTL2_TMR2_RST_Pos (4)
3352 #define SYS_IPRST_CTL2_TMR2_RST_Msk (0x1ul << SYS_IPRST_CTL2_TMR2_RST_Pos)
3354 #define SYS_IPRST_CTL2_TMR3_RST_Pos (5)
3355 #define SYS_IPRST_CTL2_TMR3_RST_Msk (0x1ul << SYS_IPRST_CTL2_TMR3_RST_Pos)
3357 #define SYS_IPRST_CTL2_I2C0_RST_Pos (8)
3358 #define SYS_IPRST_CTL2_I2C0_RST_Msk (0x1ul << SYS_IPRST_CTL2_I2C0_RST_Pos)
3360 #define SYS_IPRST_CTL2_I2C1_RST_Pos (9)
3361 #define SYS_IPRST_CTL2_I2C1_RST_Msk (0x1ul << SYS_IPRST_CTL2_I2C1_RST_Pos)
3363 #define SYS_IPRST_CTL2_SPI0_RST_Pos (12)
3364 #define SYS_IPRST_CTL2_SPI0_RST_Msk (0x1ul << SYS_IPRST_CTL2_SPI0_RST_Pos)
3366 #define SYS_IPRST_CTL2_SPI1_RST_Pos (13)
3367 #define SYS_IPRST_CTL2_SPI1_RST_Msk (0x1ul << SYS_IPRST_CTL2_SPI1_RST_Pos)
3369 #define SYS_IPRST_CTL2_SPI2_RST_Pos (14)
3370 #define SYS_IPRST_CTL2_SPI2_RST_Msk (0x1ul << SYS_IPRST_CTL2_SPI2_RST_Pos)
3372 #define SYS_IPRST_CTL2_UART0_RST_Pos (16)
3373 #define SYS_IPRST_CTL2_UART0_RST_Msk (0x1ul << SYS_IPRST_CTL2_UART0_RST_Pos)
3375 #define SYS_IPRST_CTL2_UART1_RST_Pos (17)
3376 #define SYS_IPRST_CTL2_UART1_RST_Msk (0x1ul << SYS_IPRST_CTL2_UART1_RST_Pos)
3378 #define SYS_IPRST_CTL2_PWM0_RST_Pos (20)
3379 #define SYS_IPRST_CTL2_PWM0_RST_Msk (0x1ul << SYS_IPRST_CTL2_PWM0_RST_Pos)
3381 #define SYS_IPRST_CTL2_PWM1_RST_Pos (21)
3382 #define SYS_IPRST_CTL2_PWM1_RST_Msk (0x1ul << SYS_IPRST_CTL2_PWM1_RST_Pos)
3384 #define SYS_IPRST_CTL2_USBD_RST_Pos (27)
3385 #define SYS_IPRST_CTL2_USBD_RST_Msk (0x1ul << SYS_IPRST_CTL2_USBD_RST_Pos)
3387 #define SYS_IPRST_CTL2_ADC_RST_Pos (28)
3388 #define SYS_IPRST_CTL2_ADC_RST_Msk (0x1ul << SYS_IPRST_CTL2_ADC_RST_Pos)
3390 #define SYS_IPRST_CTL2_I2S_RST_Pos (29)
3391 #define SYS_IPRST_CTL2_I2S_RST_Msk (0x1ul << SYS_IPRST_CTL2_I2S_RST_Pos)
3393 #define SYS_IPRST_CTL2_SC0_RST_Pos (30)
3394 #define SYS_IPRST_CTL2_SC0_RST_Msk (0x1ul << SYS_IPRST_CTL2_SC0_RST_Pos)
3396 #define SYS_IPRST_CTL2_SC1_RST_Pos (31)
3397 #define SYS_IPRST_CTL2_SC1_RST_Msk (0x1ul << SYS_IPRST_CTL2_SC1_RST_Pos)
3399 #define SYS_CPR_HPE_Pos (0)
3400 #define SYS_CPR_HPE_Msk (0x1ul << SYS_CPR_HPE_Pos)
3402 #define SYS_TEMPCTL_VTEMP_EN_Pos (0)
3403 #define SYS_TEMPCTL_VTEMP_EN_Msk (0x1ul << SYS_TEMPCTL_VTEMP_EN_Pos)
3405 #define SYS_PA_L_MFP_PA0_MFP_Pos (0)
3406 #define SYS_PA_L_MFP_PA0_MFP_Msk (0x7ul << SYS_PA_L_MFP_PA0_MFP_Pos)
3408 #define SYS_PA_L_MFP_PA1_MFP_Pos (4)
3409 #define SYS_PA_L_MFP_PA1_MFP_Msk (0x7ul << SYS_PA_L_MFP_PA1_MFP_Pos)
3411 #define SYS_PA_L_MFP_PA2_MFP_Pos (8)
3412 #define SYS_PA_L_MFP_PA2_MFP_Msk (0x7ul << SYS_PA_L_MFP_PA2_MFP_Pos)
3414 #define SYS_PA_L_MFP_PA3_MFP_Pos (12)
3415 #define SYS_PA_L_MFP_PA3_MFP_Msk (0x7ul << SYS_PA_L_MFP_PA3_MFP_Pos)
3417 #define SYS_PA_L_MFP_PA4_MFP_Pos (16)
3418 #define SYS_PA_L_MFP_PA4_MFP_Msk (0x7ul << SYS_PA_L_MFP_PA4_MFP_Pos)
3420 #define SYS_PA_L_MFP_PA5_MFP_Pos (20)
3421 #define SYS_PA_L_MFP_PA5_MFP_Msk (0x7ul << SYS_PA_L_MFP_PA5_MFP_Pos)
3423 #define SYS_PA_L_MFP_PA6_MFP_Pos (24)
3424 #define SYS_PA_L_MFP_PA6_MFP_Msk (0x7ul << SYS_PA_L_MFP_PA6_MFP_Pos)
3426 #define SYS_PA_L_MFP_PA7_MFP_Pos (28)
3427 #define SYS_PA_L_MFP_PA7_MFP_Msk (0x7ul << SYS_PA_L_MFP_PA7_MFP_Pos)
3429 #define SYS_PA_H_MFP_PA8_MFP_Pos (0)
3430 #define SYS_PA_H_MFP_PA8_MFP_Msk (0x7ul << SYS_PA_H_MFP_PA8_MFP_Pos)
3432 #define SYS_PA_H_MFP_PA9_MFP_Pos (4)
3433 #define SYS_PA_H_MFP_PA9_MFP_Msk (0x7ul << SYS_PA_H_MFP_PA9_MFP_Pos)
3435 #define SYS_PA_H_MFP_PA10_MFP_Pos (8)
3436 #define SYS_PA_H_MFP_PA10_MFP_Msk (0x7ul << SYS_PA_H_MFP_PA10_MFP_Pos)
3438 #define SYS_PA_H_MFP_PA11_MFP_Pos (12)
3439 #define SYS_PA_H_MFP_PA11_MFP_Msk (0x7ul << SYS_PA_H_MFP_PA11_MFP_Pos)
3441 #define SYS_PA_H_MFP_PA12_MFP_Pos (16)
3442 #define SYS_PA_H_MFP_PA12_MFP_Msk (0x7ul << SYS_PA_H_MFP_PA12_MFP_Pos)
3444 #define SYS_PA_H_MFP_PA13_MFP_Pos (20)
3445 #define SYS_PA_H_MFP_PA13_MFP_Msk (0x7ul << SYS_PA_H_MFP_PA13_MFP_Pos)
3447 #define SYS_PA_H_MFP_PA14_MFP_Pos (24)
3448 #define SYS_PA_H_MFP_PA14_MFP_Msk (0x7ul << SYS_PA_H_MFP_PA14_MFP_Pos)
3450 #define SYS_PA_H_MFP_PA15_MFP_Pos (28)
3451 #define SYS_PA_H_MFP_PA15_MFP_Msk (0x7ul << SYS_PA_H_MFP_PA15_MFP_Pos)
3453 #define SYS_PB_L_MFP_PB0_MFP_Pos (0)
3454 #define SYS_PB_L_MFP_PB0_MFP_Msk (0x7ul << SYS_PB_L_MFP_PB0_MFP_Pos)
3456 #define SYS_PB_L_MFP_PB1_MFP_Pos (4)
3457 #define SYS_PB_L_MFP_PB1_MFP_Msk (0x7ul << SYS_PB_L_MFP_PB1_MFP_Pos)
3459 #define SYS_PB_L_MFP_PB2_MFP_Pos (8)
3460 #define SYS_PB_L_MFP_PB2_MFP_Msk (0x7ul << SYS_PB_L_MFP_PB2_MFP_Pos)
3462 #define SYS_PB_L_MFP_PB3_MFP_Pos (12)
3463 #define SYS_PB_L_MFP_PB3_MFP_Msk (0x7ul << SYS_PB_L_MFP_PB3_MFP_Pos)
3465 #define SYS_PB_L_MFP_PB4_MFP_Pos (16)
3466 #define SYS_PB_L_MFP_PB4_MFP_Msk (0x7ul << SYS_PB_L_MFP_PB4_MFP_Pos)
3468 #define SYS_PB_L_MFP_PB5_MFP_Pos (20)
3469 #define SYS_PB_L_MFP_PB5_MFP_Msk (0x7ul << SYS_PB_L_MFP_PB5_MFP_Pos)
3471 #define SYS_PB_L_MFP_PB6_MFP_Pos (24)
3472 #define SYS_PB_L_MFP_PB6_MFP_Msk (0x7ul << SYS_PB_L_MFP_PB6_MFP_Pos)
3474 #define SYS_PB_L_MFP_PB7_MFP_Pos (28)
3475 #define SYS_PB_L_MFP_PB7_MFP_Msk (0x7ul << SYS_PB_L_MFP_PB7_MFP_Pos)
3477 #define SYS_PB_H_MFP_PB8_MFP_Pos (0)
3478 #define SYS_PB_H_MFP_PB8_MFP_Msk (0x7ul << SYS_PB_H_MFP_PB8_MFP_Pos)
3480 #define SYS_PB_H_MFP_PB9_MFP_Pos (4)
3481 #define SYS_PB_H_MFP_PB9_MFP_Msk (0x7ul << SYS_PB_H_MFP_PB9_MFP_Pos)
3483 #define SYS_PB_H_MFP_PB10_MFP_Pos (8)
3484 #define SYS_PB_H_MFP_PB10_MFP_Msk (0x7ul << SYS_PB_H_MFP_PB10_MFP_Pos)
3486 #define SYS_PB_H_MFP_PB11_MFP_Pos (12)
3487 #define SYS_PB_H_MFP_PB11_MFP_Msk (0x7ul << SYS_PB_H_MFP_PB11_MFP_Pos)
3489 #define SYS_PB_H_MFP_PB12_MFP_Pos (16)
3490 #define SYS_PB_H_MFP_PB12_MFP_Msk (0x7ul << SYS_PB_H_MFP_PB12_MFP_Pos)
3492 #define SYS_PB_H_MFP_PB13_MFP_Pos (20)
3493 #define SYS_PB_H_MFP_PB13_MFP_Msk (0x7ul << SYS_PB_H_MFP_PB13_MFP_Pos)
3495 #define SYS_PB_H_MFP_PB14_MFP_Pos (24)
3496 #define SYS_PB_H_MFP_PB14_MFP_Msk (0x7ul << SYS_PB_H_MFP_PB14_MFP_Pos)
3498 #define SYS_PB_H_MFP_PB15_MFP_Pos (28)
3499 #define SYS_PB_H_MFP_PB15_MFP_Msk (0x7ul << SYS_PB_H_MFP_PB15_MFP_Pos)
3501 #define SYS_PC_L_MFP_PC0_MFP_Pos (0)
3502 #define SYS_PC_L_MFP_PC0_MFP_Msk (0x7ul << SYS_PC_L_MFP_PC0_MFP_Pos)
3504 #define SYS_PC_L_MFP_PC1_MFP_Pos (4)
3505 #define SYS_PC_L_MFP_PC1_MFP_Msk (0x7ul << SYS_PC_L_MFP_PC1_MFP_Pos)
3507 #define SYS_PC_L_MFP_PC2_MFP_Pos (8)
3508 #define SYS_PC_L_MFP_PC2_MFP_Msk (0x7ul << SYS_PC_L_MFP_PC2_MFP_Pos)
3510 #define SYS_PC_L_MFP_PC3_MFP_Pos (12)
3511 #define SYS_PC_L_MFP_PC3_MFP_Msk (0x7ul << SYS_PC_L_MFP_PC3_MFP_Pos)
3513 #define SYS_PC_L_MFP_PC4_MFP_Pos (16)
3514 #define SYS_PC_L_MFP_PC4_MFP_Msk (0x7ul << SYS_PC_L_MFP_PC4_MFP_Pos)
3516 #define SYS_PC_L_MFP_PC5_MFP_Pos (20)
3517 #define SYS_PC_L_MFP_PC5_MFP_Msk (0x7ul << SYS_PC_L_MFP_PC5_MFP_Pos)
3519 #define SYS_PC_L_MFP_PC6_MFP_Pos (24)
3520 #define SYS_PC_L_MFP_PC6_MFP_Msk (0x7ul << SYS_PC_L_MFP_PC6_MFP_Pos)
3522 #define SYS_PC_L_MFP_PC7_MFP_Pos (28)
3523 #define SYS_PC_L_MFP_PC7_MFP_Msk (0x7ul << SYS_PC_L_MFP_PC7_MFP_Pos)
3525 #define SYS_PC_H_MFP_PC8_MFP_Pos (0)
3526 #define SYS_PC_H_MFP_PC8_MFP_Msk (0x7ul << SYS_PC_H_MFP_PC8_MFP_Pos)
3528 #define SYS_PC_H_MFP_PC9_MFP_Pos (4)
3529 #define SYS_PC_H_MFP_PC9_MFP_Msk (0x7ul << SYS_PC_H_MFP_PC9_MFP_Pos)
3531 #define SYS_PC_H_MFP_PC10_MFP_Pos (8)
3532 #define SYS_PC_H_MFP_PC10_MFP_Msk (0x7ul << SYS_PC_H_MFP_PC10_MFP_Pos)
3534 #define SYS_PC_H_MFP_PC11_MFP_Pos (12)
3535 #define SYS_PC_H_MFP_PC11_MFP_Msk (0x7ul << SYS_PC_H_MFP_PC11_MFP_Pos)
3537 #define SYS_PC_H_MFP_PC12_MFP_Pos (16)
3538 #define SYS_PC_H_MFP_PC12_MFP_Msk (0x7ul << SYS_PC_H_MFP_PC12_MFP_Pos)
3540 #define SYS_PC_H_MFP_PC13_MFP_Pos (20)
3541 #define SYS_PC_H_MFP_PC13_MFP_Msk (0x7ul << SYS_PC_H_MFP_PC13_MFP_Pos)
3543 #define SYS_PC_H_MFP_PC14_MFP_Pos (24)
3544 #define SYS_PC_H_MFP_PC14_MFP_Msk (0x7ul << SYS_PC_H_MFP_PC14_MFP_Pos)
3546 #define SYS_PC_H_MFP_PC15_MFP_Pos (28)
3547 #define SYS_PC_H_MFP_PC15_MFP_Msk (0x7ul << SYS_PC_H_MFP_PC15_MFP_Pos)
3549 #define SYS_PD_L_MFP_PD0_MFP_Pos (0)
3550 #define SYS_PD_L_MFP_PD0_MFP_Msk (0x7ul << SYS_PD_L_MFP_PD0_MFP_Pos)
3552 #define SYS_PD_L_MFP_PD1_MFP_Pos (4)
3553 #define SYS_PD_L_MFP_PD1_MFP_Msk (0x7ul << SYS_PD_L_MFP_PD1_MFP_Pos)
3555 #define SYS_PD_L_MFP_PD2_MFP_Pos (8)
3556 #define SYS_PD_L_MFP_PD2_MFP_Msk (0x7ul << SYS_PD_L_MFP_PD2_MFP_Pos)
3558 #define SYS_PD_L_MFP_PD3_MFP_Pos (12)
3559 #define SYS_PD_L_MFP_PD3_MFP_Msk (0x7ul << SYS_PD_L_MFP_PD3_MFP_Pos)
3561 #define SYS_PD_L_MFP_PD4_MFP_Pos (16)
3562 #define SYS_PD_L_MFP_PD4_MFP_Msk (0x7ul << SYS_PD_L_MFP_PD4_MFP_Pos)
3564 #define SYS_PD_L_MFP_PD5_MFP_Pos (20)
3565 #define SYS_PD_L_MFP_PD5_MFP_Msk (0x7ul << SYS_PD_L_MFP_PD5_MFP_Pos)
3567 #define SYS_PD_L_MFP_PD6_MFP_Pos (24)
3568 #define SYS_PD_L_MFP_PD6_MFP_Msk (0x7ul << SYS_PD_L_MFP_PD6_MFP_Pos)
3570 #define SYS_PD_L_MFP_PD7_MFP_Pos (28)
3571 #define SYS_PD_L_MFP_PD7_MFP_Msk (0x7ul << SYS_PD_L_MFP_PD7_MFP_Pos)
3573 #define SYS_PD_H_MFP_PD8_MFP_Pos (0)
3574 #define SYS_PD_H_MFP_PD8_MFP_Msk (0x7ul << SYS_PD_H_MFP_PD8_MFP_Pos)
3576 #define SYS_PD_H_MFP_PD9_MFP_Pos (4)
3577 #define SYS_PD_H_MFP_PD9_MFP_Msk (0x7ul << SYS_PD_H_MFP_PD9_MFP_Pos)
3579 #define SYS_PD_H_MFP_PD10_MFP_Pos (8)
3580 #define SYS_PD_H_MFP_PD10_MFP_Msk (0x7ul << SYS_PD_H_MFP_PD10_MFP_Pos)
3582 #define SYS_PD_H_MFP_PD11_MFP_Pos (12)
3583 #define SYS_PD_H_MFP_PD11_MFP_Msk (0x7ul << SYS_PD_H_MFP_PD11_MFP_Pos)
3585 #define SYS_PD_H_MFP_PD12_MFP_Pos (16)
3586 #define SYS_PD_H_MFP_PD12_MFP_Msk (0x7ul << SYS_PD_H_MFP_PD12_MFP_Pos)
3588 #define SYS_PD_H_MFP_PD13_MFP_Pos (20)
3589 #define SYS_PD_H_MFP_PD13_MFP_Msk (0x7ul << SYS_PD_H_MFP_PD13_MFP_Pos)
3591 #define SYS_PD_H_MFP_PD14_MFP_Pos (24)
3592 #define SYS_PD_H_MFP_PD14_MFP_Msk (0x7ul << SYS_PD_H_MFP_PD14_MFP_Pos)
3594 #define SYS_PD_H_MFP_PD15_MFP_Pos (28)
3595 #define SYS_PD_H_MFP_PD15_MFP_Msk (0x7ul << SYS_PD_H_MFP_PD15_MFP_Pos)
3597 #define SYS_PE_L_MFP_PE0_MFP_Pos (0)
3598 #define SYS_PE_L_MFP_PE0_MFP_Msk (0x7ul << SYS_PE_L_MFP_PE0_MFP_Pos)
3600 #define SYS_PE_L_MFP_PE1_MFP_Pos (4)
3601 #define SYS_PE_L_MFP_PE1_MFP_Msk (0x7ul << SYS_PE_L_MFP_PE1_MFP_Pos)
3603 #define SYS_PE_L_MFP_PE2_MFP_Pos (8)
3604 #define SYS_PE_L_MFP_PE2_MFP_Msk (0x7ul << SYS_PE_L_MFP_PE2_MFP_Pos)
3606 #define SYS_PE_L_MFP_PE3_MFP_Pos (12)
3607 #define SYS_PE_L_MFP_PE3_MFP_Msk (0x7ul << SYS_PE_L_MFP_PE3_MFP_Pos)
3609 #define SYS_PE_L_MFP_PE4_MFP_Pos (16)
3610 #define SYS_PE_L_MFP_PE4_MFP_Msk (0x7ul << SYS_PE_L_MFP_PE4_MFP_Pos)
3612 #define SYS_PE_L_MFP_PE5_MFP_Pos (20)
3613 #define SYS_PE_L_MFP_PE5_MFP_Msk (0x7ul << SYS_PE_L_MFP_PE5_MFP_Pos)
3615 #define SYS_PE_L_MFP_PE6_MFP_Pos (24)
3616 #define SYS_PE_L_MFP_PE6_MFP_Msk (0x7ul << SYS_PE_L_MFP_PE6_MFP_Pos)
3618 #define SYS_PE_L_MFP_PE7_MFP_Pos (28)
3619 #define SYS_PE_L_MFP_PE7_MFP_Msk (0x7ul << SYS_PE_L_MFP_PE7_MFP_Pos)
3621 #define SYS_PE_H_MFP_PE8_MFP_Pos (0)
3622 #define SYS_PE_H_MFP_PE8_MFP_Msk (0x7ul << SYS_PE_H_MFP_PE8_MFP_Pos)
3624 #define SYS_PE_H_MFP_PE9_MFP_Pos (4)
3625 #define SYS_PE_H_MFP_PE9_MFP_Msk (0x7ul << SYS_PE_H_MFP_PE9_MFP_Pos)
3627 #define SYS_PE_H_MFP_PE10_MFP_Pos (8)
3628 #define SYS_PE_H_MFP_PE10_MFP_Msk (0x7ul << SYS_PE_H_MFP_PE10_MFP_Pos)
3630 #define SYS_PE_H_MFP_PE11_MFP_Pos (12)
3631 #define SYS_PE_H_MFP_PE11_MFP_Msk (0x7ul << SYS_PE_H_MFP_PE11_MFP_Pos)
3633 #define SYS_PE_H_MFP_PE12_MFP_Pos (16)
3634 #define SYS_PE_H_MFP_PE12_MFP_Msk (0x7ul << SYS_PE_H_MFP_PE12_MFP_Pos)
3636 #define SYS_PE_H_MFP_PE13_MFP_Pos (20)
3637 #define SYS_PE_H_MFP_PE13_MFP_Msk (0x7ul << SYS_PE_H_MFP_PE13_MFP_Pos)
3639 #define SYS_PE_H_MFP_PE14_MFP_Pos (24)
3640 #define SYS_PE_H_MFP_PE14_MFP_Msk (0x7ul << SYS_PE_H_MFP_PE14_MFP_Pos)
3642 #define SYS_PE_H_MFP_PE15_MFP_Pos (28)
3643 #define SYS_PE_H_MFP_PE15_MFP_Msk (0x7ul << SYS_PE_H_MFP_PE15_MFP_Pos)
3645 #define SYS_PF_L_MFP_PF0_MFP_Pos (0)
3646 #define SYS_PF_L_MFP_PF0_MFP_Msk (0x7ul << SYS_PF_L_MFP_PF0_MFP_Pos)
3648 #define SYS_PF_L_MFP_PF1_MFP_Pos (4)
3649 #define SYS_PF_L_MFP_PF1_MFP_Msk (0x7ul << SYS_PF_L_MFP_PF1_MFP_Pos)
3651 #define SYS_PF_L_MFP_PF2_MFP_Pos (8)
3652 #define SYS_PF_L_MFP_PF2_MFP_Msk (0x7ul << SYS_PF_L_MFP_PF2_MFP_Pos)
3654 #define SYS_PF_L_MFP_PF3_MFP_Pos (12)
3655 #define SYS_PF_L_MFP_PF3_MFP_Msk (0x7ul << SYS_PF_L_MFP_PF3_MFP_Pos)
3657 #define SYS_PF_L_MFP_PF4_MFP_Pos (16)
3658 #define SYS_PF_L_MFP_PF4_MFP_Msk (0x7ul << SYS_PF_L_MFP_PF4_MFP_Pos)
3660 #define SYS_PF_L_MFP_PF5_MFP_Pos (20)
3661 #define SYS_PF_L_MFP_PF5_MFP_Msk (0x7ul << SYS_PF_L_MFP_PF5_MFP_Pos)
3663 #define SYS_PORCTL_POR_DIS_CODE_Pos (0)
3664 #define SYS_PORCTL_POR_DIS_CODE_Msk (0xfffful << SYS_PORCTL_POR_DIS_CODE_Pos)
3666 #define SYS_BODCTL_BOD17_EN_Pos (0)
3667 #define SYS_BODCTL_BOD17_EN_Msk (0x1ul << SYS_BODCTL_BOD17_EN_Pos)
3669 #define SYS_BODCTL_BOD20_EN_Pos (1)
3670 #define SYS_BODCTL_BOD20_EN_Msk (0x1ul << SYS_BODCTL_BOD20_EN_Pos)
3672 #define SYS_BODCTL_BOD25_EN_Pos (2)
3673 #define SYS_BODCTL_BOD25_EN_Msk (0x1ul << SYS_BODCTL_BOD25_EN_Pos)
3675 #define SYS_BODCTL_BOD17_RST_EN_Pos (4)
3676 #define SYS_BODCTL_BOD17_RST_EN_Msk (0x1ul << SYS_BODCTL_BOD17_RST_EN_Pos)
3678 #define SYS_BODCTL_BOD20_RST_EN_Pos (5)
3679 #define SYS_BODCTL_BOD20_RST_EN_Msk (0x1ul << SYS_BODCTL_BOD20_RST_EN_Pos)
3681 #define SYS_BODCTL_BOD25_RST_EN_Pos (6)
3682 #define SYS_BODCTL_BOD25_RST_EN_Msk (0x1ul << SYS_BODCTL_BOD25_RST_EN_Pos)
3684 #define SYS_BODCTL_BOD17_INT_EN_Pos (8)
3685 #define SYS_BODCTL_BOD17_INT_EN_Msk (0x1ul << SYS_BODCTL_BOD17_INT_EN_Pos)
3687 #define SYS_BODCTL_BOD20_INT_EN_Pos (9)
3688 #define SYS_BODCTL_BOD20_INT_EN_Msk (0x1ul << SYS_BODCTL_BOD20_INT_EN_Pos)
3690 #define SYS_BODCTL_BOD25_INT_EN_Pos (10)
3691 #define SYS_BODCTL_BOD25_INT_EN_Msk (0x1ul << SYS_BODCTL_BOD25_INT_EN_Pos)
3693 #define SYS_BODSTS_BOD_INT_Pos (0)
3694 #define SYS_BODSTS_BOD_INT_Msk (0x1ul << SYS_BODSTS_BOD_INT_Pos)
3696 #define SYS_BODSTS_BOD17_OUT_Pos (1)
3697 #define SYS_BODSTS_BOD17_OUT_Msk (0x1ul << SYS_BODSTS_BOD17_OUT_Pos)
3699 #define SYS_BODSTS_BOD20_OUT_Pos (2)
3700 #define SYS_BODSTS_BOD20_OUT_Msk (0x1ul << SYS_BODSTS_BOD20_OUT_Pos)
3702 #define SYS_BODSTS_BOD25_OUT_Pos (3)
3703 #define SYS_BODSTS_BOD25_OUT_Msk (0x1ul << SYS_BODSTS_BOD25_OUT_Pos)
3705 #define SYS_VREFCTL_BGP_EN_Pos (0)
3706 #define SYS_VREFCTL_BGP_EN_Msk (0x1ul << SYS_VREFCTL_BGP_EN_Pos)
3708 #define SYS_VREFCTL_REG_EN_Pos (1)
3709 #define SYS_VREFCTL_REG_EN_Msk (0x1ul << SYS_VREFCTL_REG_EN_Pos)
3711 #define SYS_VREFCTL_SEL25_Pos (2)
3712 #define SYS_VREFCTL_SEL25_Msk (0x1ul << SYS_VREFCTL_SEL25_Pos)
3714 #define SYS_VREFCTL_EXT_MODE_Pos (3)
3715 #define SYS_VREFCTL_EXT_MODE_Msk (0x1ul << SYS_VREFCTL_EXT_MODE_Pos)
3717 #define SYS_IRCTRIMCTL_TRIM_SEL_Pos (0)
3718 #define SYS_IRCTRIMCTL_TRIM_SEL_Msk (0x3ul << SYS_IRCTRIMCTL_TRIM_SEL_Pos)
3720 #define SYS_IRCTRIMCTL_TRIM_LOOP_Pos (4)
3721 #define SYS_IRCTRIMCTL_TRIM_LOOP_Msk (0x3ul << SYS_IRCTRIMCTL_TRIM_LOOP_Pos)
3723 #define SYS_IRCTRIMCTL_TRIM_RETRY_CNT_Pos (6)
3724 #define SYS_IRCTRIMCTL_TRIM_RETRY_CNT_Msk (0x3ul << SYS_IRCTRIMCTL_TRIM_RETRY_CNT_Pos)
3726 #define SYS_IRCTRIMIEN_TRIM_FAIL_IEN_Pos (1)
3727 #define SYS_IRCTRIMIEN_TRIM_FAIL_IEN_Msk (0x1ul << SYS_IRCTRIMIEN_TRIM_FAIL_IEN_Pos)
3729 #define SYS_IRCTRIMIEN_32K_ERR_IEN_Pos (2)
3730 #define SYS_IRCTRIMIEN_32K_ERR_IEN_Msk (0x1ul << SYS_IRCTRIMIEN_32K_ERR_IEN_Pos)
3732 #define SYS_IRCTRIMINT_FREQ_LOCK_Pos (0)
3733 #define SYS_IRCTRIMINT_FREQ_LOCK_Msk (0x1ul << SYS_IRCTRIMINT_FREQ_LOCK_Pos)
3735 #define SYS_IRCTRIMINT_TRIM_FAIL_INT_Pos (1)
3736 #define SYS_IRCTRIMINT_TRIM_FAIL_INT_Msk (0x1ul << SYS_IRCTRIMINT_TRIM_FAIL_INT_Pos)
3738 #define SYS_IRCTRIMINT_32K_ERR_INT_Pos (2)
3739 #define SYS_IRCTRIMINT_32K_ERR_INT_Msk (0x1ul << SYS_IRCTRIMINT_32K_ERR_INT_Pos)
3741 #define SYS_RegLockAddr_RegUnLock_Pos (0)
3742 #define SYS_RegLockAddr_RegUnLock_Msk (0x1ul << SYS_RegLockAddr_RegUnLock_Pos) /* SYS_CONST */
3745 /* end of SYS register group */
3746
3747
3748 /*---------------------- General Purpose Input/Output Controller -------------------------*/
3754 typedef struct
3755 {
3756
3757
3878 __IO uint32_t PMD;
3879
3893 __IO uint32_t OFFD;
3894
3908 __IO uint32_t DOUT;
3909
3927 __IO uint32_t DMASK;
3928
3940 __I uint32_t PIN;
3941
3959 __IO uint32_t DBEN;
3960
3980 __IO uint32_t IMD;
3981
4278 __IO uint32_t IER;
4279
4296 __IO uint32_t ISRC;
4297
4310 __IO uint32_t PUEN;
4311
4312 } GPIO_T;
4313
4314
4315 typedef struct
4316 {
4352 __IO uint32_t DBNCECON;
4353 } GP_DB_T;
4354
4355
4361 #define GP_PMD_PMD0_Pos (0)
4362 #define GP_PMD_PMD0_Msk (0x3ul << GP_PMD_PMD0_Pos)
4364 #define GP_PMD_PMD1_Pos (2)
4365 #define GP_PMD_PMD1_Msk (0x3ul << GP_PMD_PMD1_Pos)
4367 #define GP_PMD_PMD2_Pos (4)
4368 #define GP_PMD_PMD2_Msk (0x3ul << GP_PMD_PMD2_Pos)
4370 #define GP_PMD_PMD3_Pos (6)
4371 #define GP_PMD_PMD3_Msk (0x3ul << GP_PMD_PMD3_Pos)
4373 #define GP_PMD_PMD4_Pos (8)
4374 #define GP_PMD_PMD4_Msk (0x3ul << GP_PMD_PMD4_Pos)
4376 #define GP_PMD_PMD5_Pos (10)
4377 #define GP_PMD_PMD5_Msk (0x3ul << GP_PMD_PMD5_Pos)
4379 #define GP_PMD_PMD6_Pos (12)
4380 #define GP_PMD_PMD6_Msk (0x3ul << GP_PMD_PMD6_Pos)
4382 #define GP_PMD_PMD7_Pos (14)
4383 #define GP_PMD_PMD7_Msk (0x3ul << GP_PMD_PMD7_Pos)
4385 #define GP_PMD_PMD8_Pos (16)
4386 #define GP_PMD_PMD8_Msk (0x3ul << GP_PMD_PMD8_Pos)
4388 #define GP_PMD_PMD9_Pos (18)
4389 #define GP_PMD_PMD9_Msk (0x3ul << GP_PMD_PMD9_Pos)
4391 #define GP_PMD_PMD10_Pos (20)
4392 #define GP_PMD_PMD10_Msk (0x3ul << GP_PMD_PMD10_Pos)
4394 #define GP_PMD_PMD11_Pos (22)
4395 #define GP_PMD_PMD11_Msk (0x3ul << GP_PMD_PMD11_Pos)
4397 #define GP_PMD_PMD12_Pos (24)
4398 #define GP_PMD_PMD12_Msk (0x3ul << GP_PMD_PMD12_Pos)
4400 #define GP_PMD_PMD13_Pos (26)
4401 #define GP_PMD_PMD13_Msk (0x3ul << GP_PMD_PMD13_Pos)
4403 #define GP_PMD_PMD14_Pos (28)
4404 #define GP_PMD_PMD14_Msk (0x3ul << GP_PMD_PMD14_Pos)
4406 #define GP_PMD_PMD15_Pos (30)
4407 #define GP_PMD_PMD15_Msk (0x3ul << GP_PMD_PMD15_Pos)
4409 #define GP_OFFD_OFFD_Pos (16)
4410 #define GP_OFFD_OFFD_Msk (0xfffful << GP_OFFD_OFFD_Pos)
4412 #define GP_DOUT_DOUT_Pos (0)
4413 #define GP_DOUT_DOUT_Msk (0xfffful << GP_DOUT_DOUT_Pos)
4415 #define GP_DMASK_DMASK_Pos (0)
4416 #define GP_DMASK_DMASK_Msk (0xfffful << GP_DMASK_DMASK_Pos)
4418 #define GP_PIN_PIN_Pos (0)
4419 #define GP_PIN_PIN_Msk (0xfffful << GP_PIN_PIN_Pos)
4421 #define GP_DBEN_DBEN_Pos (0)
4422 #define GP_DBEN_DBEN_Msk (0xfffful << GP_DBEN_DBEN_Pos)
4424 #define GP_IMD_IMD_Pos (0)
4425 #define GP_IMD_IMD_Msk (0xfffful << GP_IMD_IMD_Pos)
4427 #define GP_IER_FIER0_Pos (0)
4428 #define GP_IER_FIER0_Msk (0x1ul << GP_IER_FIER0_Pos)
4430 #define GP_IER_FIER1_Pos (1)
4431 #define GP_IER_FIER1_Msk (0x1ul << GP_IER_FIER1_Pos)
4433 #define GP_IER_FIER2_Pos (2)
4434 #define GP_IER_FIER2_Msk (0x1ul << GP_IER_FIER2_Pos)
4436 #define GP_IER_FIER3_Pos (3)
4437 #define GP_IER_FIER3_Msk (0x1ul << GP_IER_FIER3_Pos)
4439 #define GP_IER_FIER4_Pos (4)
4440 #define GP_IER_FIER4_Msk (0x1ul << GP_IER_FIER4_Pos)
4442 #define GP_IER_FIER5_Pos (5)
4443 #define GP_IER_FIER5_Msk (0x1ul << GP_IER_FIER5_Pos)
4445 #define GP_IER_FIER6_Pos (6)
4446 #define GP_IER_FIER6_Msk (0x1ul << GP_IER_FIER6_Pos)
4448 #define GP_IER_FIER7_Pos (7)
4449 #define GP_IER_FIER7_Msk (0x1ul << GP_IER_FIER7_Pos)
4451 #define GP_IER_FIER8_Pos (8)
4452 #define GP_IER_FIER8_Msk (0x1ul << GP_IER_FIER8_Pos)
4454 #define GP_IER_FIER9_Pos (9)
4455 #define GP_IER_FIER9_Msk (0x1ul << GP_IER_FIER9_Pos)
4457 #define GP_IER_FIER10_Pos (10)
4458 #define GP_IER_FIER10_Msk (0x1ul << GP_IER_FIER10_Pos)
4460 #define GP_IER_FIER11_Pos (11)
4461 #define GP_IER_FIER11_Msk (0x1ul << GP_IER_FIER11_Pos)
4463 #define GP_IER_FIER12_Pos (12)
4464 #define GP_IER_FIER12_Msk (0x1ul << GP_IER_FIER12_Pos)
4466 #define GP_IER_FIER13_Pos (13)
4467 #define GP_IER_FIER13_Msk (0x1ul << GP_IER_FIER13_Pos)
4469 #define GP_IER_FIER14_Pos (14)
4470 #define GP_IER_FIER14_Msk (0x1ul << GP_IER_FIER14_Pos)
4472 #define GP_IER_FIER15_Pos (15)
4473 #define GP_IER_FIER15_Msk (0x1ul << GP_IER_FIER15_Pos)
4475 #define GP_IER_RIER0_Pos (16)
4476 #define GP_IER_RIER0_Msk (0x1ul << GP_IER_RIER0_Pos)
4478 #define GP_IER_RIER1_Pos (17)
4479 #define GP_IER_RIER1_Msk (0x1ul << GP_IER_RIER1_Pos)
4481 #define GP_IER_RIER2_Pos (18)
4482 #define GP_IER_RIER2_Msk (0x1ul << GP_IER_RIER2_Pos)
4484 #define GP_IER_RIER3_Pos (19)
4485 #define GP_IER_RIER3_Msk (0x1ul << GP_IER_RIER3_Pos)
4487 #define GP_IER_RIER4_Pos (20)
4488 #define GP_IER_RIER4_Msk (0x1ul << GP_IER_RIER4_Pos)
4490 #define GP_IER_RIER5_Pos (21)
4491 #define GP_IER_RIER5_Msk (0x1ul << GP_IER_RIER5_Pos)
4493 #define GP_IER_RIER6_Pos (22)
4494 #define GP_IER_RIER6_Msk (0x1ul << GP_IER_RIER6_Pos)
4496 #define GP_IER_RIER7_Pos (23)
4497 #define GP_IER_RIER7_Msk (0x1ul << GP_IER_RIER7_Pos)
4499 #define GP_IER_RIER8_Pos (24)
4500 #define GP_IER_RIER8_Msk (0x1ul << GP_IER_RIER8_Pos)
4502 #define GP_IER_RIER9_Pos (25)
4503 #define GP_IER_RIER9_Msk (0x1ul << GP_IER_RIER9_Pos)
4505 #define GP_IER_RIER10_Pos (26)
4506 #define GP_IER_RIER10_Msk (0x1ul << GP_IER_RIER10_Pos)
4508 #define GP_IER_RIER11_Pos (27)
4509 #define GP_IER_RIER11_Msk (0x1ul << GP_IER_RIER11_Pos)
4511 #define GP_IER_RIER12_Pos (28)
4512 #define GP_IER_RIER12_Msk (0x1ul << GP_IER_RIER12_Pos)
4514 #define GP_IER_RIER13_Pos (29)
4515 #define GP_IER_RIER13_Msk (0x1ul << GP_IER_RIER13_Pos)
4517 #define GP_IER_RIER14_Pos (30)
4518 #define GP_IER_RIER14_Msk (0x1ul << GP_IER_RIER14_Pos)
4520 #define GP_IER_RIER15_Pos (31)
4521 #define GP_IER_RIER15_Msk (0x1ul << GP_IER_RIER15_Pos)
4523 #define GP_ISRC_ISRC_Pos (0)
4524 #define GP_ISRC_ISRC_Msk (0xfffful << GP_ISRC_ISRC_Pos)
4526 #define GP_PUEN_PUEN_Pos (0)
4527 #define GP_PUEN_PUEN_Msk (0xfffful << GP_PUEN_PUEN_Pos) /* GPIO_CONST */
4529
4534 #define GP_DBNCECON_DBCLKSEL_Pos (0)
4535 #define GP_DBNCECON_DBCLKSEL_Msk (0xful << GP_DBNCECON_DBCLKSEL_Pos)
4537 #define GP_DBNCECON_DBCLKSRC_Pos (4)
4538 #define GP_DBNCECON_DBCLKSRC_Msk (0x1ul << GP_DBNCECON_DBCLKSRC_Pos)
4540 #define GP_DBNCECON_DBCLK_ON_Pos (5)
4541 #define GP_DBNCECON_DBCLK_ON_Msk (0x1ul << GP_DBNCECON_DBCLK_ON_Pos) /* GP_DB_CONST */
4545 /* end of GP register group */
4546
4547
4548 /*---------------------- Inter-IC Bus Controller -------------------------*/
4554 typedef struct
4555 {
4556
4557
4593 __IO uint32_t CON;
4594
4609 __IO uint32_t INTSTS;
4610
4631 __I uint32_t STATUS;
4632
4644 __IO uint32_t DIV;
4645
4663 __IO uint32_t TOUT;
4664
4683 __IO uint32_t DATA;
4684
4704 __IO uint32_t SADDR0;
4705
4725 __IO uint32_t SADDR1;
4726
4728 uint32_t RESERVE0[2];
4730
4731
4746 __IO uint32_t SAMASK0;
4747
4762 __IO uint32_t SAMASK1;
4763
4764 } I2C_T;
4765
4771 #define I2C_CON_IPEN_Pos (0)
4772 #define I2C_CON_IPEN_Msk (0x1ul << I2C_CON_IPEN_Pos)
4774 #define I2C_CON_ACK_Pos (1)
4775 #define I2C_CON_ACK_Msk (0x1ul << I2C_CON_ACK_Pos)
4777 #define I2C_CON_STOP_Pos (2)
4778 #define I2C_CON_STOP_Msk (0x1ul << I2C_CON_STOP_Pos)
4780 #define I2C_CON_START_Pos (3)
4781 #define I2C_CON_START_Msk (0x1ul << I2C_CON_START_Pos)
4783 #define I2C_CON_I2C_STS_Pos (4)
4784 #define I2C_CON_I2C_STS_Msk (0x1ul << I2C_CON_I2C_STS_Pos)
4786 #define I2C_CON_INTEN_Pos (7)
4787 #define I2C_CON_INTEN_Msk (0x1ul << I2C_CON_INTEN_Pos)
4789 #define I2C_INTSTS_INTSTS_Pos (0)
4790 #define I2C_INTSTS_INTSTS_Msk (0x1ul << I2C_INTSTS_INTSTS_Pos)
4792 #define I2C_INTSTS_TIF_Pos (1)
4793 #define I2C_INTSTS_TIF_Msk (0x1ul << I2C_INTSTS_TIF_Pos)
4795 #define I2C_STATUS_STATUS_Pos (0)
4796 #define I2C_STATUS_STATUS_Msk (0xfful << I2C_STATUS_STATUS_Pos)
4798 #define I2C_DIV_CLK_DIV_Pos (0)
4799 #define I2C_DIV_CLK_DIV_Msk (0xfful << I2C_DIV_CLK_DIV_Pos)
4801 #define I2C_TOUT_TOUTEN_Pos (0)
4802 #define I2C_TOUT_TOUTEN_Msk (0x1ul << I2C_TOUT_TOUTEN_Pos)
4804 #define I2C_TOUT_DIV4_Pos (1)
4805 #define I2C_TOUT_DIV4_Msk (0x1ul << I2C_TOUT_DIV4_Pos)
4807 #define I2C_DATA_DATA_Pos (0)
4808 #define I2C_DATA_DATA_Msk (0xfful << I2C_DATA_DATA_Pos)
4810 #define I2C_SADDR0_GCALL_Pos (0)
4811 #define I2C_SADDR0_GCALL_Msk (0x1ul << I2C_SADDR0_GCALL_Pos)
4813 #define I2C_SADDR0_SADDR_Pos (1)
4814 #define I2C_SADDR0_SADDR_Msk (0x7ful << I2C_SADDR0_SADDR_Pos)
4816 #define I2C_SADDR1_GCALL_Pos (0)
4817 #define I2C_SADDR1_GCALL_Msk (0x1ul << I2C_SADDR1_GCALL_Pos)
4819 #define I2C_SADDR1_SADDR_Pos (1)
4820 #define I2C_SADDR1_SADDR_Msk (0x7ful << I2C_SADDR1_SADDR_Pos)
4822 #define I2C_SAMASK0_SAMASK_Pos (1)
4823 #define I2C_SAMASK0_SAMASK_Msk (0x7ful << I2C_SAMASK0_SAMASK_Pos)
4825 #define I2C_SAMASK1_SAMASK_Pos (1)
4826 #define I2C_SAMASK1_SAMASK_Msk (0x7ful << I2C_SAMASK1_SAMASK_Pos) /* I2C_CONST */
4829 /* end of I2C register group */
4830
4831
4832 /*---------------------- I2S Interface Controller -------------------------*/
4838 typedef struct
4839 {
4840
4841
4928 __IO uint32_t CTRL;
4929
4947 __IO uint32_t CLKDIV;
4948
4989 __IO uint32_t INTEN;
4990
5090 __IO uint32_t STATUS;
5091
5105 __O uint32_t TXFIFO;
5106
5120 __I uint32_t RXFIFO;
5121
5122 } I2S_T;
5123
5129 #define I2S_CTRL_I2SEN_Pos (0)
5130 #define I2S_CTRL_I2SEN_Msk (0x1ul << I2S_CTRL_I2SEN_Pos)
5132 #define I2S_CTRL_TXEN_Pos (1)
5133 #define I2S_CTRL_TXEN_Msk (0x1ul << I2S_CTRL_TXEN_Pos)
5135 #define I2S_CTRL_RXEN_Pos (2)
5136 #define I2S_CTRL_RXEN_Msk (0x1ul << I2S_CTRL_RXEN_Pos)
5138 #define I2S_CTRL_MUTE_Pos (3)
5139 #define I2S_CTRL_MUTE_Msk (0x1ul << I2S_CTRL_MUTE_Pos)
5141 #define I2S_CTRL_WORDWIDTH_Pos (4)
5142 #define I2S_CTRL_WORDWIDTH_Msk (0x3ul << I2S_CTRL_WORDWIDTH_Pos)
5144 #define I2S_CTRL_MONO_Pos (6)
5145 #define I2S_CTRL_MONO_Msk (0x1ul << I2S_CTRL_MONO_Pos)
5147 #define I2S_CTRL_FORMAT_Pos (7)
5148 #define I2S_CTRL_FORMAT_Msk (0x1ul << I2S_CTRL_FORMAT_Pos)
5150 #define I2S_CTRL_SLAVE_Pos (8)
5151 #define I2S_CTRL_SLAVE_Msk (0x1ul << I2S_CTRL_SLAVE_Pos)
5153 #define I2S_CTRL_TXTH_Pos (9)
5154 #define I2S_CTRL_TXTH_Msk (0x7ul << I2S_CTRL_TXTH_Pos)
5156 #define I2S_CTRL_RXTH_Pos (12)
5157 #define I2S_CTRL_RXTH_Msk (0x7ul << I2S_CTRL_RXTH_Pos)
5159 #define I2S_CTRL_MCLKEN_Pos (15)
5160 #define I2S_CTRL_MCLKEN_Msk (0x1ul << I2S_CTRL_MCLKEN_Pos)
5162 #define I2S_CTRL_RCHZCEN_Pos (16)
5163 #define I2S_CTRL_RCHZCEN_Msk (0x1ul << I2S_CTRL_RCHZCEN_Pos)
5165 #define I2S_CTRL_LCHZCEN_Pos (17)
5166 #define I2S_CTRL_LCHZCEN_Msk (0x1ul << I2S_CTRL_LCHZCEN_Pos)
5168 #define I2S_CTRL_CLR_TXFIFO_Pos (18)
5169 #define I2S_CTRL_CLR_TXFIFO_Msk (0x1ul << I2S_CTRL_CLR_TXFIFO_Pos)
5171 #define I2S_CTRL_CLR_RXFIFO_Pos (19)
5172 #define I2S_CTRL_CLR_RXFIFO_Msk (0x1ul << I2S_CTRL_CLR_RXFIFO_Pos)
5174 #define I2S_CTRL_TXDMA_Pos (20)
5175 #define I2S_CTRL_TXDMA_Msk (0x1ul << I2S_CTRL_TXDMA_Pos)
5177 #define I2S_CTRL_RXDMA_Pos (21)
5178 #define I2S_CTRL_RXDMA_Msk (0x1ul << I2S_CTRL_RXDMA_Pos)
5180 #define I2S_CLKDIV_MCLK_DIV_Pos (0)
5181 #define I2S_CLKDIV_MCLK_DIV_Msk (0x7ul << I2S_CLKDIV_MCLK_DIV_Pos)
5183 #define I2S_CLKDIV_BCLK_DIV_Pos (8)
5184 #define I2S_CLKDIV_BCLK_DIV_Msk (0xfful << I2S_CLKDIV_BCLK_DIV_Pos)
5186 #define I2S_INTEN_RXUDFIE_Pos (0)
5187 #define I2S_INTEN_RXUDFIE_Msk (0x1ul << I2S_INTEN_RXUDFIE_Pos)
5189 #define I2S_INTEN_RXOVFIE_Pos (1)
5190 #define I2S_INTEN_RXOVFIE_Msk (0x1ul << I2S_INTEN_RXOVFIE_Pos)
5192 #define I2S_INTEN_RXTHIE_Pos (2)
5193 #define I2S_INTEN_RXTHIE_Msk (0x1ul << I2S_INTEN_RXTHIE_Pos)
5195 #define I2S_INTEN_TXUDFIE_Pos (8)
5196 #define I2S_INTEN_TXUDFIE_Msk (0x1ul << I2S_INTEN_TXUDFIE_Pos)
5198 #define I2S_INTEN_TXOVFIE_Pos (9)
5199 #define I2S_INTEN_TXOVFIE_Msk (0x1ul << I2S_INTEN_TXOVFIE_Pos)
5201 #define I2S_INTEN_TXTHIE_Pos (10)
5202 #define I2S_INTEN_TXTHIE_Msk (0x1ul << I2S_INTEN_TXTHIE_Pos)
5204 #define I2S_INTEN_RZCIE_Pos (11)
5205 #define I2S_INTEN_RZCIE_Msk (0x1ul << I2S_INTEN_RZCIE_Pos)
5207 #define I2S_INTEN_LZCIE_Pos (12)
5208 #define I2S_INTEN_LZCIE_Msk (0x1ul << I2S_INTEN_LZCIE_Pos)
5210 #define I2S_STATUS_I2SINT_Pos (0)
5211 #define I2S_STATUS_I2SINT_Msk (0x1ul << I2S_STATUS_I2SINT_Pos)
5213 #define I2S_STATUS_I2SRXINT_Pos (1)
5214 #define I2S_STATUS_I2SRXINT_Msk (0x1ul << I2S_STATUS_I2SRXINT_Pos)
5216 #define I2S_STATUS_I2STXINT_Pos (2)
5217 #define I2S_STATUS_I2STXINT_Msk (0x1ul << I2S_STATUS_I2STXINT_Pos)
5219 #define I2S_STATUS_RIGHT_Pos (3)
5220 #define I2S_STATUS_RIGHT_Msk (0x1ul << I2S_STATUS_RIGHT_Pos)
5222 #define I2S_STATUS_RXUDF_Pos (8)
5223 #define I2S_STATUS_RXUDF_Msk (0x1ul << I2S_STATUS_RXUDF_Pos)
5225 #define I2S_STATUS_RXOVF_Pos (9)
5226 #define I2S_STATUS_RXOVF_Msk (0x1ul << I2S_STATUS_RXOVF_Pos)
5228 #define I2S_STATUS_RXTHF_Pos (10)
5229 #define I2S_STATUS_RXTHF_Msk (0x1ul << I2S_STATUS_RXTHF_Pos)
5231 #define I2S_STATUS_RXFULL_Pos (11)
5232 #define I2S_STATUS_RXFULL_Msk (0x1ul << I2S_STATUS_RXFULL_Pos)
5234 #define I2S_STATUS_RXEMPTY_Pos (12)
5235 #define I2S_STATUS_RXEMPTY_Msk (0x1ul << I2S_STATUS_RXEMPTY_Pos)
5237 #define I2S_STATUS_TXUDF_Pos (16)
5238 #define I2S_STATUS_TXUDF_Msk (0x1ul << I2S_STATUS_TXUDF_Pos)
5240 #define I2S_STATUS_TXOVF_Pos (17)
5241 #define I2S_STATUS_TXOVF_Msk (0x1ul << I2S_STATUS_TXOVF_Pos)
5243 #define I2S_STATUS_TXTHF_Pos (18)
5244 #define I2S_STATUS_TXTHF_Msk (0x1ul << I2S_STATUS_TXTHF_Pos)
5246 #define I2S_STATUS_TXFULL_Pos (19)
5247 #define I2S_STATUS_TXFULL_Msk (0x1ul << I2S_STATUS_TXFULL_Pos)
5249 #define I2S_STATUS_TXEMPTY_Pos (20)
5250 #define I2S_STATUS_TXEMPTY_Msk (0x1ul << I2S_STATUS_TXEMPTY_Pos)
5252 #define I2S_STATUS_TXBUSY_Pos (21)
5253 #define I2S_STATUS_TXBUSY_Msk (0x1ul << I2S_STATUS_TXBUSY_Pos)
5255 #define I2S_STATUS_RZCF_Pos (22)
5256 #define I2S_STATUS_RZCF_Msk (0x1ul << I2S_STATUS_RZCF_Pos)
5258 #define I2S_STATUS_LZCF_Pos (23)
5259 #define I2S_STATUS_LZCF_Msk (0x1ul << I2S_STATUS_LZCF_Pos)
5261 #define I2S_STATUS_RX_LEVEL_Pos (24)
5262 #define I2S_STATUS_RX_LEVEL_Msk (0xful << I2S_STATUS_RX_LEVEL_Pos)
5264 #define I2S_STATUS_TX_LEVEL_Pos (28)
5265 #define I2S_STATUS_TX_LEVEL_Msk (0xful << I2S_STATUS_TX_LEVEL_Pos)
5267 #define I2S_TXFIFO_TXFIFO_Pos (0)
5268 #define I2S_TXFIFO_TXFIFO_Msk (0xfffffffful << I2S_TXFIFO_TXFIFO_Pos)
5270 #define I2S_RXFIFO_RXFIFO_Pos (0)
5271 #define I2S_RXFIFO_RXFIFO_Msk (0xfffffffful << I2S_RXFIFO_RXFIFO_Pos) /* I2S_CONST */
5274 /* end of I2S register group */
5275
5276
5277 /*---------------------- Pulse Width Modulation Controller -------------------------*/
5283 typedef struct
5284 {
5285
5286
5309 __IO uint32_t PRES;
5310
5335 __IO uint32_t CLKSEL;
5336
5393 __IO uint32_t CTL;
5394
5415 __IO uint32_t INTEN;
5416
5453 __IO uint32_t INTSTS;
5454
5479 __IO uint32_t OE;
5480
5482 uint32_t RESERVE0[1];
5484
5485
5512 __IO uint32_t DUTY0;
5513
5531 __I uint32_t DATA0;
5532
5534 uint32_t RESERVE1[1];
5536
5537
5564 __IO uint32_t DUTY1;
5565
5583 __I uint32_t DATA1;
5584
5586 uint32_t RESERVE2[1];
5588
5589
5616 __IO uint32_t DUTY2;
5617
5635 __I uint32_t DATA2;
5636
5638 uint32_t RESERVE3[1];
5640
5641
5668 __IO uint32_t DUTY3;
5669
5687 __I uint32_t DATA3;
5688
5690 uint32_t RESERVE4[3];
5692
5693
5796 __IO uint32_t CAPCTL;
5797
5838 __IO uint32_t CAPINTEN;
5839
5900 __IO uint32_t CAPINTSTS;
5901
5914 __I uint32_t CRL0;
5915
5928 __I uint32_t CFL0;
5929
5942 __I uint32_t CRL1;
5943
5956 __I uint32_t CFL1;
5957
5970 __I uint32_t CRL2;
5971
5984 __I uint32_t CFL2;
5985
5998 __I uint32_t CRL3;
5999
6012 __I uint32_t CFL3;
6013
6034 __I uint32_t PDMACH0;
6035
6056 __I uint32_t PDMACH2;
6057
6058 } PWM_T;
6059
6065 #define PWM_PRES_CP01_Pos (0)
6066 #define PWM_PRES_CP01_Msk (0xfful << PWM_PRES_CP01_Pos)
6068 #define PWM_PRES_CP23_Pos (8)
6069 #define PWM_PRES_CP23_Msk (0xfful << PWM_PRES_CP23_Pos)
6071 #define PWM_PRES_DZ01_Pos (16)
6072 #define PWM_PRES_DZ01_Msk (0xfful << PWM_PRES_DZ01_Pos)
6074 #define PWM_PRES_DZ23_Pos (24)
6075 #define PWM_PRES_DZ23_Msk (0xfful << PWM_PRES_DZ23_Pos)
6077 #define PWM_CLKSEL_CLKSEL0_Pos (0)
6078 #define PWM_CLKSEL_CLKSEL0_Msk (0x7ul << PWM_CLKSEL_CLKSEL0_Pos)
6080 #define PWM_CLKSEL_CLKSEL1_Pos (4)
6081 #define PWM_CLKSEL_CLKSEL1_Msk (0x7ul << PWM_CLKSEL_CLKSEL1_Pos)
6083 #define PWM_CLKSEL_CLKSEL2_Pos (8)
6084 #define PWM_CLKSEL_CLKSEL2_Msk (0x7ul << PWM_CLKSEL_CLKSEL2_Pos)
6086 #define PWM_CLKSEL_CLKSEL3_Pos (12)
6087 #define PWM_CLKSEL_CLKSEL3_Msk (0x7ul << PWM_CLKSEL_CLKSEL3_Pos)
6089 #define PWM_CTL_CH0EN_Pos (0)
6090 #define PWM_CTL_CH0EN_Msk (0x1ul << PWM_CTL_CH0EN_Pos)
6092 #define PWM_CTL_CH0INV_Pos (2)
6093 #define PWM_CTL_CH0INV_Msk (0x1ul << PWM_CTL_CH0INV_Pos)
6095 #define PWM_CTL_CH0MOD_Pos (3)
6096 #define PWM_CTL_CH0MOD_Msk (0x1ul << PWM_CTL_CH0MOD_Pos)
6098 #define PWM_CTL_DZEN01_Pos (4)
6099 #define PWM_CTL_DZEN01_Msk (0x1ul << PWM_CTL_DZEN01_Pos)
6101 #define PWM_CTL_DZEN23_Pos (5)
6102 #define PWM_CTL_DZEN23_Msk (0x1ul << PWM_CTL_DZEN23_Pos)
6104 #define PWM_CTL_CH1EN_Pos (8)
6105 #define PWM_CTL_CH1EN_Msk (0x1ul << PWM_CTL_CH1EN_Pos)
6107 #define PWM_CTL_CH1INV_Pos (10)
6108 #define PWM_CTL_CH1INV_Msk (0x1ul << PWM_CTL_CH1INV_Pos)
6110 #define PWM_CTL_CH1MOD_Pos (11)
6111 #define PWM_CTL_CH1MOD_Msk (0x1ul << PWM_CTL_CH1MOD_Pos)
6113 #define PWM_CTL_CH2EN_Pos (16)
6114 #define PWM_CTL_CH2EN_Msk (0x1ul << PWM_CTL_CH2EN_Pos)
6116 #define PWM_CTL_CH2INV_Pos (18)
6117 #define PWM_CTL_CH2INV_Msk (0x1ul << PWM_CTL_CH2INV_Pos)
6119 #define PWM_CTL_CH2MOD_Pos (19)
6120 #define PWM_CTL_CH2MOD_Msk (0x1ul << PWM_CTL_CH2MOD_Pos)
6122 #define PWM_CTL_CH3EN_Pos (24)
6123 #define PWM_CTL_CH3EN_Msk (0x1ul << PWM_CTL_CH3EN_Pos)
6125 #define PWM_CTL_CH3INV_Pos (26)
6126 #define PWM_CTL_CH3INV_Msk (0x1ul << PWM_CTL_CH3INV_Pos)
6128 #define PWM_CTL_CH3MOD_Pos (27)
6129 #define PWM_CTL_CH3MOD_Msk (0x1ul << PWM_CTL_CH3MOD_Pos)
6131 #define PWM_INTEN_TMIE0_Pos (0)
6132 #define PWM_INTEN_TMIE0_Msk (0x1ul << PWM_INTEN_TMIE0_Pos)
6134 #define PWM_INTEN_TMIE1_Pos (1)
6135 #define PWM_INTEN_TMIE1_Msk (0x1ul << PWM_INTEN_TMIE1_Pos)
6137 #define PWM_INTEN_TMIE2_Pos (2)
6138 #define PWM_INTEN_TMIE2_Msk (0x1ul << PWM_INTEN_TMIE2_Pos)
6140 #define PWM_INTEN_TMIE3_Pos (3)
6141 #define PWM_INTEN_TMIE3_Msk (0x1ul << PWM_INTEN_TMIE3_Pos)
6143 #define PWM_INTSTS_TMINT0_Pos (0)
6144 #define PWM_INTSTS_TMINT0_Msk (0x1ul << PWM_INTSTS_TMINT0_Pos)
6146 #define PWM_INTSTS_TMINT1_Pos (1)
6147 #define PWM_INTSTS_TMINT1_Msk (0x1ul << PWM_INTSTS_TMINT1_Pos)
6149 #define PWM_INTSTS_TMINT2_Pos (2)
6150 #define PWM_INTSTS_TMINT2_Msk (0x1ul << PWM_INTSTS_TMINT2_Pos)
6152 #define PWM_INTSTS_TMINT3_Pos (3)
6153 #define PWM_INTSTS_TMINT3_Msk (0x1ul << PWM_INTSTS_TMINT3_Pos)
6155 #define PWM_INTSTS_Duty0Syncflag_Pos (4)
6156 #define PWM_INTSTS_Duty0Syncflag_Msk (0x1ul << PWM_INTSTS_Duty0Syncflag_Pos)
6158 #define PWM_INTSTS_Duty1Syncflag_Pos (5)
6159 #define PWM_INTSTS_Duty1Syncflag_Msk (0x1ul << PWM_INTSTS_Duty1Syncflag_Pos)
6161 #define PWM_INTSTS_Duty2Syncflag_Pos (6)
6162 #define PWM_INTSTS_Duty2Syncflag_Msk (0x1ul << PWM_INTSTS_Duty2Syncflag_Pos)
6164 #define PWM_INTSTS_Duty3Syncflag_Pos (7)
6165 #define PWM_INTSTS_Duty3Syncflag_Msk (0x1ul << PWM_INTSTS_Duty3Syncflag_Pos)
6167 #define PWM_INTSTS_PresSyncFlag_Pos (8)
6168 #define PWM_INTSTS_PresSyncFlag_Msk (0x1ul << PWM_INTSTS_PresSyncFlag_Pos)
6170 #define PWM_OE_CH0_OE_Pos (0)
6171 #define PWM_OE_CH0_OE_Msk (0x1ul << PWM_OE_CH0_OE_Pos)
6173 #define PWM_OE_CH1_OE_Pos (1)
6174 #define PWM_OE_CH1_OE_Msk (0x1ul << PWM_OE_CH1_OE_Pos)
6176 #define PWM_OE_CH2_OE_Pos (2)
6177 #define PWM_OE_CH2_OE_Msk (0x1ul << PWM_OE_CH2_OE_Pos)
6179 #define PWM_OE_CH3_OE_Pos (3)
6180 #define PWM_OE_CH3_OE_Msk (0x1ul << PWM_OE_CH3_OE_Pos)
6182 #define PWM_DUTY0_CN_Pos (0)
6183 #define PWM_DUTY0_CN_Msk (0xfffful << PWM_DUTY0_CN_Pos)
6185 #define PWM_DUTY0_CM_Pos (16)
6186 #define PWM_DUTY0_CM_Msk (0xfffful << PWM_DUTY0_CM_Pos)
6188 #define PWM_DATA0_PWMx_DATAy15_0_Pos (0)
6189 #define PWM_DATA0_PWMx_DATAy15_0_Msk (0xfffful << PWM_DATA0_PWMx_DATAy15_0_Pos)
6191 #define PWM_DATA0_PWMx_DATAy30_16_Pos (16)
6192 #define PWM_DATA0_PWMx_DATAy30_16_Msk (0x7ffful << PWM_DATA0_PWMx_DATAy30_16_Pos)
6194 #define PWM_DATA0_sync_Pos (31)
6195 #define PWM_DATA0_sync_Msk (0x1ul << PWM_DATA0_sync_Pos)
6197 #define PWM_DUTY1_CN_Pos (0)
6198 #define PWM_DUTY1_CN_Msk (0xfffful << PWM_DUTY1_CN_Pos)
6200 #define PWM_DUTY1_CM_Pos (16)
6201 #define PWM_DUTY1_CM_Msk (0xfffful << PWM_DUTY1_CM_Pos)
6203 #define PWM_DATA1_PWMx_DATAy15_0_Pos (0)
6204 #define PWM_DATA1_PWMx_DATAy15_0_Msk (0xfffful << PWM_DATA1_PWMx_DATAy15_0_Pos)
6206 #define PWM_DATA1_PWMx_DATAy30_16_Pos (16)
6207 #define PWM_DATA1_PWMx_DATAy30_16_Msk (0x7ffful << PWM_DATA1_PWMx_DATAy30_16_Pos)
6209 #define PWM_DATA1_sync_Pos (31)
6210 #define PWM_DATA1_sync_Msk (0x1ul << PWM_DATA1_sync_Pos)
6212 #define PWM_DUTY2_CN_Pos (0)
6213 #define PWM_DUTY2_CN_Msk (0xfffful << PWM_DUTY2_CN_Pos)
6215 #define PWM_DUTY2_CM_Pos (16)
6216 #define PWM_DUTY2_CM_Msk (0xfffful << PWM_DUTY2_CM_Pos)
6218 #define PWM_DATA2_PWMx_DATAy15_0_Pos (0)
6219 #define PWM_DATA2_PWMx_DATAy15_0_Msk (0xfffful << PWM_DATA2_PWMx_DATAy15_0_Pos)
6221 #define PWM_DATA2_PWMx_DATAy30_16_Pos (16)
6222 #define PWM_DATA2_PWMx_DATAy30_16_Msk (0x7ffful << PWM_DATA2_PWMx_DATAy30_16_Pos)
6224 #define PWM_DATA2_sync_Pos (31)
6225 #define PWM_DATA2_sync_Msk (0x1ul << PWM_DATA2_sync_Pos)
6227 #define PWM_DUTY3_CN_Pos (0)
6228 #define PWM_DUTY3_CN_Msk (0xfffful << PWM_DUTY3_CN_Pos)
6230 #define PWM_DUTY3_CM_Pos (16)
6231 #define PWM_DUTY3_CM_Msk (0xfffful << PWM_DUTY3_CM_Pos)
6233 #define PWM_DATA3_PWMx_DATAy15_0_Pos (0)
6234 #define PWM_DATA3_PWMx_DATAy15_0_Msk (0xfffful << PWM_DATA3_PWMx_DATAy15_0_Pos)
6236 #define PWM_DATA3_PWMx_DATAy30_16_Pos (16)
6237 #define PWM_DATA3_PWMx_DATAy30_16_Msk (0x7ffful << PWM_DATA3_PWMx_DATAy30_16_Pos)
6239 #define PWM_DATA3_sync_Pos (31)
6240 #define PWM_DATA3_sync_Msk (0x1ul << PWM_DATA3_sync_Pos)
6242 #define PWM_CAPCTL_INV0_Pos (0)
6243 #define PWM_CAPCTL_INV0_Msk (0x1ul << PWM_CAPCTL_INV0_Pos)
6245 #define PWM_CAPCTL_CAPCH0EN_Pos (1)
6246 #define PWM_CAPCTL_CAPCH0EN_Msk (0x1ul << PWM_CAPCTL_CAPCH0EN_Pos)
6248 #define PWM_CAPCTL_CAPCH0PADEN_Pos (2)
6249 #define PWM_CAPCTL_CAPCH0PADEN_Msk (0x1ul << PWM_CAPCTL_CAPCH0PADEN_Pos)
6251 #define PWM_CAPCTL_CH0PDMAEN_Pos (3)
6252 #define PWM_CAPCTL_CH0PDMAEN_Msk (0x1ul << PWM_CAPCTL_CH0PDMAEN_Pos)
6254 #define PWM_CAPCTL_PDMACAPMOD0_Pos (4)
6255 #define PWM_CAPCTL_PDMACAPMOD0_Msk (0x3ul << PWM_CAPCTL_PDMACAPMOD0_Pos)
6257 #define PWM_CAPCTL_CAPRELOADREN0_Pos (6)
6258 #define PWM_CAPCTL_CAPRELOADREN0_Msk (0x1ul << PWM_CAPCTL_CAPRELOADREN0_Pos)
6260 #define PWM_CAPCTL_CAPRELOADFEN0_Pos (7)
6261 #define PWM_CAPCTL_CAPRELOADFEN0_Msk (0x1ul << PWM_CAPCTL_CAPRELOADFEN0_Pos)
6263 #define PWM_CAPCTL_INV1_Pos (8)
6264 #define PWM_CAPCTL_INV1_Msk (0x1ul << PWM_CAPCTL_INV1_Pos)
6266 #define PWM_CAPCTL_CAPCH1EN_Pos (9)
6267 #define PWM_CAPCTL_CAPCH1EN_Msk (0x1ul << PWM_CAPCTL_CAPCH1EN_Pos)
6269 #define PWM_CAPCTL_CAPCH1PADEN_Pos (10)
6270 #define PWM_CAPCTL_CAPCH1PADEN_Msk (0x1ul << PWM_CAPCTL_CAPCH1PADEN_Pos)
6272 #define PWM_CAPCTL_CH0RFORDER_Pos (12)
6273 #define PWM_CAPCTL_CH0RFORDER_Msk (0x1ul << PWM_CAPCTL_CH0RFORDER_Pos)
6275 #define PWM_CAPCTL_CH01CASK_Pos (13)
6276 #define PWM_CAPCTL_CH01CASK_Msk (0x1ul << PWM_CAPCTL_CH01CASK_Pos)
6278 #define PWM_CAPCTL_CAPRELOADREN1_Pos (14)
6279 #define PWM_CAPCTL_CAPRELOADREN1_Msk (0x1ul << PWM_CAPCTL_CAPRELOADREN1_Pos)
6281 #define PWM_CAPCTL_CAPRELOADFEN1_Pos (15)
6282 #define PWM_CAPCTL_CAPRELOADFEN1_Msk (0x1ul << PWM_CAPCTL_CAPRELOADFEN1_Pos)
6284 #define PWM_CAPCTL_INV2_Pos (16)
6285 #define PWM_CAPCTL_INV2_Msk (0x1ul << PWM_CAPCTL_INV2_Pos)
6287 #define PWM_CAPCTL_CAPCH2EN_Pos (17)
6288 #define PWM_CAPCTL_CAPCH2EN_Msk (0x1ul << PWM_CAPCTL_CAPCH2EN_Pos)
6290 #define PWM_CAPCTL_CAPCH2PADEN_Pos (18)
6291 #define PWM_CAPCTL_CAPCH2PADEN_Msk (0x1ul << PWM_CAPCTL_CAPCH2PADEN_Pos)
6293 #define PWM_CAPCTL_CH2PDMAEN_Pos (19)
6294 #define PWM_CAPCTL_CH2PDMAEN_Msk (0x1ul << PWM_CAPCTL_CH2PDMAEN_Pos)
6296 #define PWM_CAPCTL_PDMACAPMOD2_Pos (20)
6297 #define PWM_CAPCTL_PDMACAPMOD2_Msk (0x3ul << PWM_CAPCTL_PDMACAPMOD2_Pos)
6299 #define PWM_CAPCTL_CAPRELOADREN2_Pos (22)
6300 #define PWM_CAPCTL_CAPRELOADREN2_Msk (0x1ul << PWM_CAPCTL_CAPRELOADREN2_Pos)
6302 #define PWM_CAPCTL_CAPRELOADFEN2_Pos (23)
6303 #define PWM_CAPCTL_CAPRELOADFEN2_Msk (0x1ul << PWM_CAPCTL_CAPRELOADFEN2_Pos)
6305 #define PWM_CAPCTL_INV3_Pos (24)
6306 #define PWM_CAPCTL_INV3_Msk (0x1ul << PWM_CAPCTL_INV3_Pos)
6308 #define PWM_CAPCTL_CAPCH3EN_Pos (25)
6309 #define PWM_CAPCTL_CAPCH3EN_Msk (0x1ul << PWM_CAPCTL_CAPCH3EN_Pos)
6311 #define PWM_CAPCTL_CAPCH3PADEN_Pos (26)
6312 #define PWM_CAPCTL_CAPCH3PADEN_Msk (0x1ul << PWM_CAPCTL_CAPCH3PADEN_Pos)
6314 #define PWM_CAPCTL_CH2RFORDER_Pos (28)
6315 #define PWM_CAPCTL_CH2RFORDER_Msk (0x1ul << PWM_CAPCTL_CH2RFORDER_Pos)
6317 #define PWM_CAPCTL_CH23CASK_Pos (29)
6318 #define PWM_CAPCTL_CH23CASK_Msk (0x1ul << PWM_CAPCTL_CH23CASK_Pos)
6320 #define PWM_CAPCTL_CAPRELOADREN3_Pos (30)
6321 #define PWM_CAPCTL_CAPRELOADREN3_Msk (0x1ul << PWM_CAPCTL_CAPRELOADREN3_Pos)
6323 #define PWM_CAPCTL_CAPRELOADFEN3_Pos (31)
6324 #define PWM_CAPCTL_CAPRELOADFEN3_Msk (0x1ul << PWM_CAPCTL_CAPRELOADFEN3_Pos)
6326 #define PWM_CAPINTEN_CRL_IE0_Pos (0)
6327 #define PWM_CAPINTEN_CRL_IE0_Msk (0x1ul << PWM_CAPINTEN_CRL_IE0_Pos)
6329 #define PWM_CAPINTEN_CFL_IE0_Pos (1)
6330 #define PWM_CAPINTEN_CFL_IE0_Msk (0x1ul << PWM_CAPINTEN_CFL_IE0_Pos)
6332 #define PWM_CAPINTEN_CRL_IE1_Pos (8)
6333 #define PWM_CAPINTEN_CRL_IE1_Msk (0x1ul << PWM_CAPINTEN_CRL_IE1_Pos)
6335 #define PWM_CAPINTEN_CFL_IE1_Pos (9)
6336 #define PWM_CAPINTEN_CFL_IE1_Msk (0x1ul << PWM_CAPINTEN_CFL_IE1_Pos)
6338 #define PWM_CAPINTEN_CRL_IE2_Pos (16)
6339 #define PWM_CAPINTEN_CRL_IE2_Msk (0x1ul << PWM_CAPINTEN_CRL_IE2_Pos)
6341 #define PWM_CAPINTEN_CFL_IE2_Pos (17)
6342 #define PWM_CAPINTEN_CFL_IE2_Msk (0x1ul << PWM_CAPINTEN_CFL_IE2_Pos)
6344 #define PWM_CAPINTEN_CRL_IE3_Pos (24)
6345 #define PWM_CAPINTEN_CRL_IE3_Msk (0x1ul << PWM_CAPINTEN_CRL_IE3_Pos)
6347 #define PWM_CAPINTEN_CFL_IE3_Pos (25)
6348 #define PWM_CAPINTEN_CFL_IE3_Msk (0x1ul << PWM_CAPINTEN_CFL_IE3_Pos)
6350 #define PWM_CAPINTSTS_CAPIF0_Pos (0)
6351 #define PWM_CAPINTSTS_CAPIF0_Msk (0x1ul << PWM_CAPINTSTS_CAPIF0_Pos)
6353 #define PWM_CAPINTSTS_CRLI0_Pos (1)
6354 #define PWM_CAPINTSTS_CRLI0_Msk (0x1ul << PWM_CAPINTSTS_CRLI0_Pos)
6356 #define PWM_CAPINTSTS_CFLRI0_Pos (2)
6357 #define PWM_CAPINTSTS_CFLRI0_Msk (0x1ul << PWM_CAPINTSTS_CFLRI0_Pos)
6359 #define PWM_CAPINTSTS_CAPOVR0_Pos (3)
6360 #define PWM_CAPINTSTS_CAPOVR0_Msk (0x1ul << PWM_CAPINTSTS_CAPOVR0_Pos)
6362 #define PWM_CAPINTSTS_CAPOVF0_Pos (4)
6363 #define PWM_CAPINTSTS_CAPOVF0_Msk (0x1ul << PWM_CAPINTSTS_CAPOVF0_Pos)
6365 #define PWM_CAPINTSTS_CAPIF1_Pos (8)
6366 #define PWM_CAPINTSTS_CAPIF1_Msk (0x1ul << PWM_CAPINTSTS_CAPIF1_Pos)
6368 #define PWM_CAPINTSTS_CRLI1_Pos (9)
6369 #define PWM_CAPINTSTS_CRLI1_Msk (0x1ul << PWM_CAPINTSTS_CRLI1_Pos)
6371 #define PWM_CAPINTSTS_CFLI1_Pos (10)
6372 #define PWM_CAPINTSTS_CFLI1_Msk (0x1ul << PWM_CAPINTSTS_CFLI1_Pos)
6374 #define PWM_CAPINTSTS_CAPOVR1_Pos (11)
6375 #define PWM_CAPINTSTS_CAPOVR1_Msk (0x1ul << PWM_CAPINTSTS_CAPOVR1_Pos)
6377 #define PWM_CAPINTSTS_CAPOVF1_Pos (12)
6378 #define PWM_CAPINTSTS_CAPOVF1_Msk (0x1ul << PWM_CAPINTSTS_CAPOVF1_Pos)
6380 #define PWM_CAPINTSTS_CAPIF2_Pos (16)
6381 #define PWM_CAPINTSTS_CAPIF2_Msk (0x1ul << PWM_CAPINTSTS_CAPIF2_Pos)
6383 #define PWM_CAPINTSTS_CRLI2_Pos (17)
6384 #define PWM_CAPINTSTS_CRLI2_Msk (0x1ul << PWM_CAPINTSTS_CRLI2_Pos)
6386 #define PWM_CAPINTSTS_CFLI2_Pos (18)
6387 #define PWM_CAPINTSTS_CFLI2_Msk (0x1ul << PWM_CAPINTSTS_CFLI2_Pos)
6389 #define PWM_CAPINTSTS_CAPOVR2_Pos (19)
6390 #define PWM_CAPINTSTS_CAPOVR2_Msk (0x1ul << PWM_CAPINTSTS_CAPOVR2_Pos)
6392 #define PWM_CAPINTSTS_CAPOVF2_Pos (20)
6393 #define PWM_CAPINTSTS_CAPOVF2_Msk (0x1ul << PWM_CAPINTSTS_CAPOVF2_Pos)
6395 #define PWM_CAPINTSTS_CAPIF3_Pos (24)
6396 #define PWM_CAPINTSTS_CAPIF3_Msk (0x1ul << PWM_CAPINTSTS_CAPIF3_Pos)
6398 #define PWM_CAPINTSTS_CRLI3_Pos (25)
6399 #define PWM_CAPINTSTS_CRLI3_Msk (0x1ul << PWM_CAPINTSTS_CRLI3_Pos)
6401 #define PWM_CAPINTSTS_CFLI3_Pos (26)
6402 #define PWM_CAPINTSTS_CFLI3_Msk (0x1ul << PWM_CAPINTSTS_CFLI3_Pos)
6404 #define PWM_CAPINTSTS_CAPOVR3_Pos (27)
6405 #define PWM_CAPINTSTS_CAPOVR3_Msk (0x1ul << PWM_CAPINTSTS_CAPOVR3_Pos)
6407 #define PWM_CAPINTSTS_CAPOVF3_Pos (28)
6408 #define PWM_CAPINTSTS_CAPOVF3_Msk (0x1ul << PWM_CAPINTSTS_CAPOVF3_Pos)
6410 #define PWM_CRL0_CRL15_0_Pos (0)
6411 #define PWM_CRL0_CRL15_0_Msk (0xfffful << PWM_CRL0_CRL15_0_Pos)
6413 #define PWM_CRL0_CRL31_16_Pos (16)
6414 #define PWM_CRL0_CRL31_16_Msk (0xfffful << PWM_CRL0_CRL31_16_Pos)
6416 #define PWM_CFL0_CFL15_0_Pos (0)
6417 #define PWM_CFL0_CFL15_0_Msk (0xfffful << PWM_CFL0_CFL15_0_Pos)
6419 #define PWM_CFL0_CFL31_16_Pos (16)
6420 #define PWM_CFL0_CFL31_16_Msk (0xfffful << PWM_CFL0_CFL31_16_Pos)
6422 #define PWM_CRL1_CRL15_0_Pos (0)
6423 #define PWM_CRL1_CRL15_0_Msk (0xfffful << PWM_CRL1_CRL15_0_Pos)
6425 #define PWM_CRL1_CRL31_16_Pos (16)
6426 #define PWM_CRL1_CRL31_16_Msk (0xfffful << PWM_CRL1_CRL31_16_Pos)
6428 #define PWM_CFL1_CFL15_0_Pos (0)
6429 #define PWM_CFL1_CFL15_0_Msk (0xfffful << PWM_CFL1_CFL15_0_Pos)
6431 #define PWM_CFL1_CFL31_16_Pos (16)
6432 #define PWM_CFL1_CFL31_16_Msk (0xfffful << PWM_CFL1_CFL31_16_Pos)
6434 #define PWM_CRL2_CRL15_0_Pos (0)
6435 #define PWM_CRL2_CRL15_0_Msk (0xfffful << PWM_CRL2_CRL15_0_Pos)
6437 #define PWM_CRL2_CRL31_16_Pos (16)
6438 #define PWM_CRL2_CRL31_16_Msk (0xfffful << PWM_CRL2_CRL31_16_Pos)
6440 #define PWM_CFL2_CFL15_0_Pos (0)
6441 #define PWM_CFL2_CFL15_0_Msk (0xfffful << PWM_CFL2_CFL15_0_Pos)
6443 #define PWM_CFL2_CFL31_16_Pos (16)
6444 #define PWM_CFL2_CFL31_16_Msk (0xfffful << PWM_CFL2_CFL31_16_Pos)
6446 #define PWM_CRL3_CRL15_0_Pos (0)
6447 #define PWM_CRL3_CRL15_0_Msk (0xfffful << PWM_CRL3_CRL15_0_Pos)
6449 #define PWM_CRL3_CRL31_16_Pos (16)
6450 #define PWM_CRL3_CRL31_16_Msk (0xfffful << PWM_CRL3_CRL31_16_Pos)
6452 #define PWM_CFL3_CFL15_0_Pos (0)
6453 #define PWM_CFL3_CFL15_0_Msk (0xfffful << PWM_CFL3_CFL15_0_Pos)
6455 #define PWM_CFL3_CFL31_16_Pos (16)
6456 #define PWM_CFL3_CFL31_16_Msk (0xfffful << PWM_CFL3_CFL31_16_Pos)
6458 #define PWM_PDMACH0_Captureddata7_0_Pos (0)
6459 #define PWM_PDMACH0_Captureddata7_0_Msk (0xfful << PWM_PDMACH0_Captureddata7_0_Pos)
6461 #define PWM_PDMACH0_Captureddata15_8_Pos (8)
6462 #define PWM_PDMACH0_Captureddata15_8_Msk (0xfful << PWM_PDMACH0_Captureddata15_8_Pos)
6464 #define PWM_PDMACH0_Captureddata23_16_Pos (16)
6465 #define PWM_PDMACH0_Captureddata23_16_Msk (0xfful << PWM_PDMACH0_Captureddata23_16_Pos)
6467 #define PWM_PDMACH0_Captureddata31_24_Pos (24)
6468 #define PWM_PDMACH0_Captureddata31_24_Msk (0xfful << PWM_PDMACH0_Captureddata31_24_Pos)
6470 #define PWM_PDMACH2_Captureddata7_0_Pos (0)
6471 #define PWM_PDMACH2_Captureddata7_0_Msk (0xfful << PWM_PDMACH2_Captureddata7_0_Pos)
6473 #define PWM_PDMACH2_Captureddata15_8_Pos (8)
6474 #define PWM_PDMACH2_Captureddata15_8_Msk (0xfful << PWM_PDMACH2_Captureddata15_8_Pos)
6476 #define PWM_PDMACH2_Captureddata23_16_Pos (16)
6477 #define PWM_PDMACH2_Captureddata23_16_Msk (0xfful << PWM_PDMACH2_Captureddata23_16_Pos)
6479 #define PWM_PDMACH2_Captureddata31_24_Pos (24)
6480 #define PWM_PDMACH2_Captureddata31_24_Msk (0xfful << PWM_PDMACH2_Captureddata31_24_Pos) /* PWM_CONST */
6483 /* end of PWM register group */
6484
6485
6486 /*---------------------- Real Time Clock Controller -------------------------*/
6492 typedef struct
6493 {
6494
6495
6512 __IO uint32_t INIR;
6513
6528 __IO uint32_t AER;
6529
6558 __IO uint32_t FCR;
6559
6574 __IO uint32_t TLR;
6575
6590 __IO uint32_t CLR;
6591
6604 __IO uint32_t TSSR;
6605
6622 __IO uint32_t DWR;
6623
6638 __IO uint32_t TAR;
6639
6654 __IO uint32_t CAR;
6655
6667 __I uint32_t LIR;
6668
6686 __IO uint32_t RIER;
6687
6714 __IO uint32_t RIIR;
6715
6740 __IO uint32_t TTR;
6741
6743 uint32_t RESERVE0[2];
6745
6746
6772 __IO uint32_t SPRCTL;
6773
6785 __IO uint32_t SPR[20];
6786
6787 } RTC_T;
6788
6794 #define RTC_INIR_ACTIVE_Pos (0)
6795 #define RTC_INIR_ACTIVE_Msk (0x1ul << RTC_INIR_ACTIVE_Pos)
6797 #define RTC_INIR_INIR_Pos (0)
6798 #define RTC_INIR_INIR_Msk (0xfffffffful << RTC_INIR_INIR_Pos)
6800 #define RTC_AER_AER_Pos (0)
6801 #define RTC_AER_AER_Msk (0xfffful << RTC_AER_AER_Pos)
6803 #define RTC_AER_ENF_Pos (16)
6804 #define RTC_AER_ENF_Msk (0x1ul << RTC_AER_ENF_Pos)
6806 #define RTC_FCR_FRACTION_Pos (0)
6807 #define RTC_FCR_FRACTION_Msk (0x3ful << RTC_FCR_FRACTION_Pos)
6809 #define RTC_FCR_INTEGER_Pos (8)
6810 #define RTC_FCR_INTEGER_Msk (0xful << RTC_FCR_INTEGER_Pos)
6812 #define RTC_TLR_1SEC_Pos (0)
6813 #define RTC_TLR_1SEC_Msk (0xful << RTC_TLR_1SEC_Pos)
6815 #define RTC_TLR_10SEC_Pos (4)
6816 #define RTC_TLR_10SEC_Msk (0x7ul << RTC_TLR_10SEC_Pos)
6818 #define RTC_TLR_1MIN_Pos (8)
6819 #define RTC_TLR_1MIN_Msk (0xful << RTC_TLR_1MIN_Pos)
6821 #define RTC_TLR_10MIN_Pos (12)
6822 #define RTC_TLR_10MIN_Msk (0x7ul << RTC_TLR_10MIN_Pos)
6824 #define RTC_TLR_1HR_Pos (16)
6825 #define RTC_TLR_1HR_Msk (0xful << RTC_TLR_1HR_Pos)
6827 #define RTC_TLR_10HR_Pos (20)
6828 #define RTC_TLR_10HR_Msk (0x3ul << RTC_TLR_10HR_Pos)
6830 #define RTC_CLR_1DAY_Pos (0)
6831 #define RTC_CLR_1DAY_Msk (0xful << RTC_CLR_1DAY_Pos)
6833 #define RTC_CLR_10DAY_Pos (4)
6834 #define RTC_CLR_10DAY_Msk (0x3ul << RTC_CLR_10DAY_Pos)
6836 #define RTC_CLR_1MON_Pos (8)
6837 #define RTC_CLR_1MON_Msk (0xful << RTC_CLR_1MON_Pos)
6839 #define RTC_CLR_10MON_Pos (12)
6840 #define RTC_CLR_10MON_Msk (0x1ul << RTC_CLR_10MON_Pos)
6842 #define RTC_CLR_1YEAR_Pos (16)
6843 #define RTC_CLR_1YEAR_Msk (0xful << RTC_CLR_1YEAR_Pos)
6845 #define RTC_CLR_10YEAR_Pos (20)
6846 #define RTC_CLR_10YEAR_Msk (0xful << RTC_CLR_10YEAR_Pos)
6848 #define RTC_TSSR_24H_12H_Pos (0)
6849 #define RTC_TSSR_24H_12H_Msk (0x1ul << RTC_TSSR_24H_12H_Pos)
6851 #define RTC_DWR_DWR_Pos (0)
6852 #define RTC_DWR_DWR_Msk (0x7ul << RTC_DWR_DWR_Pos)
6854 #define RTC_TAR_1SEC_Pos (0)
6855 #define RTC_TAR_1SEC_Msk (0xful << RTC_TAR_1SEC_Pos)
6857 #define RTC_TAR_10SEC_Pos (4)
6858 #define RTC_TAR_10SEC_Msk (0x7ul << RTC_TAR_10SEC_Pos)
6860 #define RTC_TAR_1MIN_Pos (8)
6861 #define RTC_TAR_1MIN_Msk (0xful << RTC_TAR_1MIN_Pos)
6863 #define RTC_TAR_10MIN_Pos (12)
6864 #define RTC_TAR_10MIN_Msk (0x7ul << RTC_TAR_10MIN_Pos)
6866 #define RTC_TAR_1HR_Pos (16)
6867 #define RTC_TAR_1HR_Msk (0xful << RTC_TAR_1HR_Pos)
6869 #define RTC_TAR_10HR_Pos (20)
6870 #define RTC_TAR_10HR_Msk (0x3ul << RTC_TAR_10HR_Pos)
6872 #define RTC_CAR_1DAY_Pos (0)
6873 #define RTC_CAR_1DAY_Msk (0xful << RTC_CAR_1DAY_Pos)
6875 #define RTC_CAR_10DAY_Pos (4)
6876 #define RTC_CAR_10DAY_Msk (0x3ul << RTC_CAR_10DAY_Pos)
6878 #define RTC_CAR_1MON_Pos (8)
6879 #define RTC_CAR_1MON_Msk (0xful << RTC_CAR_1MON_Pos)
6881 #define RTC_CAR_10MON_Pos (12)
6882 #define RTC_CAR_10MON_Msk (0x1ul << RTC_CAR_10MON_Pos)
6884 #define RTC_CAR_1YEAR_Pos (16)
6885 #define RTC_CAR_1YEAR_Msk (0xful << RTC_CAR_1YEAR_Pos)
6887 #define RTC_CAR_10YEAR_Pos (20)
6888 #define RTC_CAR_10YEAR_Msk (0xful << RTC_CAR_10YEAR_Pos)
6890 #define RTC_LIR_LIR_Pos (0)
6891 #define RTC_LIR_LIR_Msk (0x1ul << RTC_LIR_LIR_Pos)
6893 #define RTC_RIER_AIER_Pos (0)
6894 #define RTC_RIER_AIER_Msk (0x1ul << RTC_RIER_AIER_Pos)
6896 #define RTC_RIER_TIER_Pos (1)
6897 #define RTC_RIER_TIER_Msk (0x1ul << RTC_RIER_TIER_Pos)
6899 #define RTC_RIER_SNOOPIER_Pos (2)
6900 #define RTC_RIER_SNOOPIER_Msk (0x1ul << RTC_RIER_SNOOPIER_Pos)
6902 #define RTC_RIIR_AIF_Pos (0)
6903 #define RTC_RIIR_AIF_Msk (0x1ul << RTC_RIIR_AIF_Pos)
6905 #define RTC_RIIR_TIF_Pos (1)
6906 #define RTC_RIIR_TIF_Msk (0x1ul << RTC_RIIR_TIF_Pos)
6908 #define RTC_RIIR_SNOOPIF_Pos (2)
6909 #define RTC_RIIR_SNOOPIF_Msk (0x1ul << RTC_RIIR_SNOOPIF_Pos)
6911 #define RTC_TTR_TTR_Pos (0)
6912 #define RTC_TTR_TTR_Msk (0x7ul << RTC_TTR_TTR_Pos)
6914 #define RTC_TTR_TWKE_Pos (3)
6915 #define RTC_TTR_TWKE_Msk (0x1ul << RTC_TTR_TWKE_Pos)
6917 #define RTC_SPRCTL_SNOOPEN_Pos (0)
6918 #define RTC_SPRCTL_SNOOPEN_Msk (0x1ul << RTC_SPRCTL_SNOOPEN_Pos)
6920 #define RTC_SPRCTL_SNOOPEDGE_Pos (1)
6921 #define RTC_SPRCTL_SNOOPEDGE_Msk (0x1ul << RTC_SPRCTL_SNOOPEDGE_Pos)
6923 #define RTC_SPRCTL_SPRRDY_Pos (7)
6924 #define RTC_SPRCTL_SPRRDY_Msk (0x1ul << RTC_SPRCTL_SPRRDY_Pos)
6926 #define RTC_SPR0_SPARE_Pos (0)
6927 #define RTC_SPR0_SPARE_Msk (0xfffffffful << RTC_SPR0_SPARE_Pos)
6929 #define RTC_SPR1_SPARE_Pos (0)
6930 #define RTC_SPR1_SPARE_Msk (0xfffffffful << RTC_SPR1_SPARE_Pos)
6932 #define RTC_SPR2_SPARE_Pos (0)
6933 #define RTC_SPR2_SPARE_Msk (0xfffffffful << RTC_SPR2_SPARE_Pos)
6935 #define RTC_SPR3_SPARE_Pos (0)
6936 #define RTC_SPR3_SPARE_Msk (0xfffffffful << RTC_SPR3_SPARE_Pos)
6938 #define RTC_SPR4_SPARE_Pos (0)
6939 #define RTC_SPR4_SPARE_Msk (0xfffffffful << RTC_SPR4_SPARE_Pos)
6941 #define RTC_SPR5_SPARE_Pos (0)
6942 #define RTC_SPR5_SPARE_Msk (0xfffffffful << RTC_SPR5_SPARE_Pos)
6944 #define RTC_SPR6_SPARE_Pos (0)
6945 #define RTC_SPR6_SPARE_Msk (0xfffffffful << RTC_SPR6_SPARE_Pos)
6947 #define RTC_SPR7_SPARE_Pos (0)
6948 #define RTC_SPR7_SPARE_Msk (0xfffffffful << RTC_SPR7_SPARE_Pos)
6950 #define RTC_SPR8_SPARE_Pos (0)
6951 #define RTC_SPR8_SPARE_Msk (0xfffffffful << RTC_SPR8_SPARE_Pos)
6953 #define RTC_SPR9_SPARE_Pos (0)
6954 #define RTC_SPR9_SPARE_Msk (0xfffffffful << RTC_SPR9_SPARE_Pos)
6956 #define RTC_SPR10_SPARE_Pos (0)
6957 #define RTC_SPR10_SPARE_Msk (0xfffffffful << RTC_SPR10_SPARE_Pos)
6959 #define RTC_SPR11_SPARE_Pos (0)
6960 #define RTC_SPR11_SPARE_Msk (0xfffffffful << RTC_SPR11_SPARE_Pos)
6962 #define RTC_SPR12_SPARE_Pos (0)
6963 #define RTC_SPR12_SPARE_Msk (0xfffffffful << RTC_SPR12_SPARE_Pos)
6965 #define RTC_SPR13_SPARE_Pos (0)
6966 #define RTC_SPR13_SPARE_Msk (0xfffffffful << RTC_SPR13_SPARE_Pos)
6968 #define RTC_SPR14_SPARE_Pos (0)
6969 #define RTC_SPR14_SPARE_Msk (0xfffffffful << RTC_SPR14_SPARE_Pos)
6971 #define RTC_SPR15_SPARE_Pos (0)
6972 #define RTC_SPR15_SPARE_Msk (0xfffffffful << RTC_SPR15_SPARE_Pos)
6974 #define RTC_SPR16_SPARE_Pos (0)
6975 #define RTC_SPR16_SPARE_Msk (0xfffffffful << RTC_SPR16_SPARE_Pos)
6977 #define RTC_SPR17_SPARE_Pos (0)
6978 #define RTC_SPR17_SPARE_Msk (0xfffffffful << RTC_SPR17_SPARE_Pos)
6980 #define RTC_SPR18_SPARE_Pos (0)
6981 #define RTC_SPR18_SPARE_Msk (0xfffffffful << RTC_SPR18_SPARE_Pos)
6983 #define RTC_SPR19_SPARE_Pos (0)
6984 #define RTC_SPR19_SPARE_Msk (0xfffffffful << RTC_SPR19_SPARE_Pos) /* RTC_CONST */
6987 /* end of RTC register group */
6988
6989
6990 /*---------------------- Smart Card Host Interface Controller -------------------------*/
6996 typedef struct
6997 {
6998
6999
7000 union
7001 {
7012 __I uint32_t RBR;
7023 __O uint32_t THR;
7024 };
7025
7110 __IO uint32_t CTL;
7111
7200 __IO uint32_t ALTCTL;
7201
7213 __IO uint32_t EGTR;
7214
7228 __IO uint32_t RFTMR;
7229
7248 __IO uint32_t ETUCR;
7249
7309 __IO uint32_t IER;
7310
7361 __IO uint32_t ISR;
7362
7436 __IO uint32_t TRSR;
7437
7503 __IO uint32_t PINCSR;
7504
7517 __IO uint32_t TMR0;
7518
7531 __IO uint32_t TMR1;
7532
7545 __IO uint32_t TMR2;
7546
7548 uint32_t RESERVE0[1];
7550
7551
7562 __I uint32_t TDRA;
7563
7576 __I uint32_t TDRB;
7577
7578 } SC_T;
7579
7585 #define SC_DAT_DAT_Pos (0)
7586 #define SC_DAT_DAT_Msk (0xfful << SC_DAT_DAT_Pos)
7588 #define SC_CTL_SC_CEN_Pos (0)
7589 #define SC_CTL_SC_CEN_Msk (0x1ul << SC_CTL_SC_CEN_Pos)
7591 #define SC_CTL_DIS_RX_Pos (1)
7592 #define SC_CTL_DIS_RX_Msk (0x1ul << SC_CTL_DIS_RX_Pos)
7594 #define SC_CTL_DIS_TX_Pos (2)
7595 #define SC_CTL_DIS_TX_Msk (0x1ul << SC_CTL_DIS_TX_Pos)
7597 #define SC_CTL_AUTO_CON_EN_Pos (3)
7598 #define SC_CTL_AUTO_CON_EN_Msk (0x1ul << SC_CTL_AUTO_CON_EN_Pos)
7600 #define SC_CTL_CON_SEL_Pos (4)
7601 #define SC_CTL_CON_SEL_Msk (0x3ul << SC_CTL_CON_SEL_Pos)
7603 #define SC_CTL_RX_FTRI_LEV_Pos (6)
7604 #define SC_CTL_RX_FTRI_LEV_Msk (0x3ul << SC_CTL_RX_FTRI_LEV_Pos)
7606 #define SC_CTL_BGT_Pos (8)
7607 #define SC_CTL_BGT_Msk (0x1ful << SC_CTL_BGT_Pos)
7609 #define SC_CTL_TMR_SEL_Pos (13)
7610 #define SC_CTL_TMR_SEL_Msk (0x3ul << SC_CTL_TMR_SEL_Pos)
7612 #define SC_CTL_SLEN_Pos (15)
7613 #define SC_CTL_SLEN_Msk (0x1ul << SC_CTL_SLEN_Pos)
7615 #define SC_CTL_RX_ERETRY_Pos (16)
7616 #define SC_CTL_RX_ERETRY_Msk (0x7ul << SC_CTL_RX_ERETRY_Pos)
7618 #define SC_CTL_RX_ERETRY_EN_Pos (19)
7619 #define SC_CTL_RX_ERETRY_EN_Msk (0x1ul << SC_CTL_RX_ERETRY_EN_Pos)
7621 #define SC_CTL_TX_ERETRY_Pos (20)
7622 #define SC_CTL_TX_ERETRY_Msk (0x7ul << SC_CTL_TX_ERETRY_Pos)
7624 #define SC_CTL_TX_ERETRY_EN_Pos (23)
7625 #define SC_CTL_TX_ERETRY_EN_Msk (0x1ul << SC_CTL_TX_ERETRY_EN_Pos)
7627 #define SC_CTL_CD_DEB_SEL_Pos (24)
7628 #define SC_CTL_CD_DEB_SEL_Msk (0x3ul << SC_CTL_CD_DEB_SEL_Pos)
7630 #define SC_ALTCTL_TX_RST_Pos (0)
7631 #define SC_ALTCTL_TX_RST_Msk (0x1ul << SC_ALTCTL_TX_RST_Pos)
7633 #define SC_ALTCTL_RX_RST_Pos (1)
7634 #define SC_ALTCTL_RX_RST_Msk (0x1ul << SC_ALTCTL_RX_RST_Pos)
7636 #define SC_ALTCTL_DACT_EN_Pos (2)
7637 #define SC_ALTCTL_DACT_EN_Msk (0x1ul << SC_ALTCTL_DACT_EN_Pos)
7639 #define SC_ALTCTL_ACT_EN_Pos (3)
7640 #define SC_ALTCTL_ACT_EN_Msk (0x1ul << SC_ALTCTL_ACT_EN_Pos)
7642 #define SC_ALTCTL_WARST_EN_Pos (4)
7643 #define SC_ALTCTL_WARST_EN_Msk (0x1ul << SC_ALTCTL_WARST_EN_Pos)
7645 #define SC_ALTCTL_TMR0_SEN_Pos (5)
7646 #define SC_ALTCTL_TMR0_SEN_Msk (0x1ul << SC_ALTCTL_TMR0_SEN_Pos)
7648 #define SC_ALTCTL_TMR1_SEN_Pos (6)
7649 #define SC_ALTCTL_TMR1_SEN_Msk (0x1ul << SC_ALTCTL_TMR1_SEN_Pos)
7651 #define SC_ALTCTL_TMR2_SEN_Pos (7)
7652 #define SC_ALTCTL_TMR2_SEN_Msk (0x1ul << SC_ALTCTL_TMR2_SEN_Pos)
7654 #define SC_ALTCTL_INIT_SEL_Pos (8)
7655 #define SC_ALTCTL_INIT_SEL_Msk (0x3ul << SC_ALTCTL_INIT_SEL_Pos)
7657 #define SC_ALTCTL_RX_BGT_EN_Pos (12)
7658 #define SC_ALTCTL_RX_BGT_EN_Msk (0x1ul << SC_ALTCTL_RX_BGT_EN_Pos)
7660 #define SC_ALTCTL_TMR0_ATV_Pos (13)
7661 #define SC_ALTCTL_TMR0_ATV_Msk (0x1ul << SC_ALTCTL_TMR0_ATV_Pos)
7663 #define SC_ALTCTL_TMR1_ATV_Pos (14)
7664 #define SC_ALTCTL_TMR1_ATV_Msk (0x1ul << SC_ALTCTL_TMR1_ATV_Pos)
7666 #define SC_ALTCTL_TMR2_ATV_Pos (15)
7667 #define SC_ALTCTL_TMR2_ATV_Msk (0x1ul << SC_ALTCTL_TMR2_ATV_Pos)
7669 #define SC_EGTR_EGT_Pos (0)
7670 #define SC_EGTR_EGT_Msk (0xfful << SC_EGTR_EGT_Pos)
7672 #define SC_RFTMR_RFTM_Pos (0)
7673 #define SC_RFTMR_RFTM_Msk (0x1fful << SC_RFTMR_RFTM_Pos)
7675 #define SC_ETUCR_ETU_RDIV_Pos (0)
7676 #define SC_ETUCR_ETU_RDIV_Msk (0xffful << SC_ETUCR_ETU_RDIV_Pos)
7678 #define SC_ETUCR_COMPEN_EN_Pos (15)
7679 #define SC_ETUCR_COMPEN_EN_Msk (0x1ul << SC_ETUCR_COMPEN_EN_Pos)
7681 #define SC_IER_RDA_IE_Pos (0)
7682 #define SC_IER_RDA_IE_Msk (0x1ul << SC_IER_RDA_IE_Pos)
7684 #define SC_IER_TBE_IE_Pos (1)
7685 #define SC_IER_TBE_IE_Msk (0x1ul << SC_IER_TBE_IE_Pos)
7687 #define SC_IER_TERR_IE_Pos (2)
7688 #define SC_IER_TERR_IE_Msk (0x1ul << SC_IER_TERR_IE_Pos)
7690 #define SC_IER_TMR0_IE_Pos (3)
7691 #define SC_IER_TMR0_IE_Msk (0x1ul << SC_IER_TMR0_IE_Pos)
7693 #define SC_IER_TMR1_IE_Pos (4)
7694 #define SC_IER_TMR1_IE_Msk (0x1ul << SC_IER_TMR1_IE_Pos)
7696 #define SC_IER_TMR2_IE_Pos (5)
7697 #define SC_IER_TMR2_IE_Msk (0x1ul << SC_IER_TMR2_IE_Pos)
7699 #define SC_IER_BGT_IE_Pos (6)
7700 #define SC_IER_BGT_IE_Msk (0x1ul << SC_IER_BGT_IE_Pos)
7702 #define SC_IER_CD_IE_Pos (7)
7703 #define SC_IER_CD_IE_Msk (0x1ul << SC_IER_CD_IE_Pos)
7705 #define SC_IER_INIT_IE_Pos (8)
7706 #define SC_IER_INIT_IE_Msk (0x1ul << SC_IER_INIT_IE_Pos)
7708 #define SC_IER_RTMR_IE_Pos (9)
7709 #define SC_IER_RTMR_IE_Msk (0x1ul << SC_IER_RTMR_IE_Pos)
7711 #define SC_IER_ACON_ERR_IE_Pos (10)
7712 #define SC_IER_ACON_ERR_IE_Msk (0x1ul << SC_IER_ACON_ERR_IE_Pos)
7714 #define SC_IER_COMPEN_EN_Pos (15)
7715 #define SC_IER_COMPEN_EN_Msk (0x1ul << SC_IER_COMPEN_EN_Pos)
7717 #define SC_ISR_RDA_IS_Pos (0)
7718 #define SC_ISR_RDA_IS_Msk (0x1ul << SC_ISR_RDA_IS_Pos)
7720 #define SC_ISR_TBE_IS_Pos (1)
7721 #define SC_ISR_TBE_IS_Msk (0x1ul << SC_ISR_TBE_IS_Pos)
7723 #define SC_ISR_TERR_IS_Pos (2)
7724 #define SC_ISR_TERR_IS_Msk (0x1ul << SC_ISR_TERR_IS_Pos)
7726 #define SC_ISR_TMR0_IS_Pos (3)
7727 #define SC_ISR_TMR0_IS_Msk (0x1ul << SC_ISR_TMR0_IS_Pos)
7729 #define SC_ISR_TMR1_IS_Pos (4)
7730 #define SC_ISR_TMR1_IS_Msk (0x1ul << SC_ISR_TMR1_IS_Pos)
7732 #define SC_ISR_TMR2_IS_Pos (5)
7733 #define SC_ISR_TMR2_IS_Msk (0x1ul << SC_ISR_TMR2_IS_Pos)
7735 #define SC_ISR_BGT_IS_Pos (6)
7736 #define SC_ISR_BGT_IS_Msk (0x1ul << SC_ISR_BGT_IS_Pos)
7738 #define SC_ISR_CD_IS_Pos (7)
7739 #define SC_ISR_CD_IS_Msk (0x1ul << SC_ISR_CD_IS_Pos)
7741 #define SC_ISR_INIT_IS_Pos (8)
7742 #define SC_ISR_INIT_IS_Msk (0x1ul << SC_ISR_INIT_IS_Pos)
7744 #define SC_ISR_RTMR_IS_Pos (9)
7745 #define SC_ISR_RTMR_IS_Msk (0x1ul << SC_ISR_RTMR_IS_Pos)
7747 #define SC_ISR_ACON_ERR_IS_Pos (10)
7748 #define SC_ISR_ACON_ERR_IS_Msk (0x1ul << SC_ISR_ACON_ERR_IS_Pos)
7750 #define SC_TRSR_RX_OVER_F_Pos (0)
7751 #define SC_TRSR_RX_OVER_F_Msk (0x1ul << SC_TRSR_RX_OVER_F_Pos)
7753 #define SC_TRSR_RX_EMPTY_F_Pos (1)
7754 #define SC_TRSR_RX_EMPTY_F_Msk (0x1ul << SC_TRSR_RX_EMPTY_F_Pos)
7756 #define SC_TRSR_RX_FULL_F_Pos (2)
7757 #define SC_TRSR_RX_FULL_F_Msk (0x1ul << SC_TRSR_RX_FULL_F_Pos)
7759 #define SC_TRSR_RX_EPA_F_Pos (4)
7760 #define SC_TRSR_RX_EPA_F_Msk (0x1ul << SC_TRSR_RX_EPA_F_Pos)
7762 #define SC_TRSR_RX_EFR_F_Pos (5)
7763 #define SC_TRSR_RX_EFR_F_Msk (0x1ul << SC_TRSR_RX_EFR_F_Pos)
7765 #define SC_TRSR_RX_EBR_F_Pos (6)
7766 #define SC_TRSR_RX_EBR_F_Msk (0x1ul << SC_TRSR_RX_EBR_F_Pos)
7768 #define SC_TRSR_TX_OVER_F_Pos (8)
7769 #define SC_TRSR_TX_OVER_F_Msk (0x1ul << SC_TRSR_TX_OVER_F_Pos)
7771 #define SC_TRSR_TX_EMPTY_F_Pos (9)
7772 #define SC_TRSR_TX_EMPTY_F_Msk (0x1ul << SC_TRSR_TX_EMPTY_F_Pos)
7774 #define SC_TRSR_TX_FULL_F_Pos (10)
7775 #define SC_TRSR_TX_FULL_F_Msk (0x1ul << SC_TRSR_TX_FULL_F_Pos)
7777 #define SC_TRSR_RX_POINT_F_Pos (16)
7778 #define SC_TRSR_RX_POINT_F_Msk (0x7ul << SC_TRSR_RX_POINT_F_Pos)
7780 #define SC_TRSR_RX_REERR_Pos (21)
7781 #define SC_TRSR_RX_REERR_Msk (0x1ul << SC_TRSR_RX_REERR_Pos)
7783 #define SC_TRSR_RX_OVER_ERETRY_Pos (22)
7784 #define SC_TRSR_RX_OVER_ERETRY_Msk (0x1ul << SC_TRSR_RX_OVER_ERETRY_Pos)
7786 #define SC_TRSR_RX_ATV_Pos (23)
7787 #define SC_TRSR_RX_ATV_Msk (0x1ul << SC_TRSR_RX_ATV_Pos)
7789 #define SC_TRSR_TX_POINT_F_Pos (24)
7790 #define SC_TRSR_TX_POINT_F_Msk (0x7ul << SC_TRSR_TX_POINT_F_Pos)
7792 #define SC_TRSR_TX_REERR_Pos (29)
7793 #define SC_TRSR_TX_REERR_Msk (0x1ul << SC_TRSR_TX_REERR_Pos)
7795 #define SC_TRSR_TX_OVER_ERETRY_Pos (30)
7796 #define SC_TRSR_TX_OVER_ERETRY_Msk (0x1ul << SC_TRSR_TX_OVER_ERETRY_Pos)
7798 #define SC_TRSR_TX_ATV_Pos (31)
7799 #define SC_TRSR_TX_ATV_Msk (0x1ul << SC_TRSR_TX_ATV_Pos)
7801 #define SC_PINCSR_POW_EN_Pos (0)
7802 #define SC_PINCSR_POW_EN_Msk (0x1ul << SC_PINCSR_POW_EN_Pos)
7804 #define SC_PINCSR_SC_RST_Pos (1)
7805 #define SC_PINCSR_SC_RST_Msk (0x1ul << SC_PINCSR_SC_RST_Pos)
7807 #define SC_PINCSR_CD_REM_F_Pos (2)
7808 #define SC_PINCSR_CD_REM_F_Msk (0x1ul << SC_PINCSR_CD_REM_F_Pos)
7810 #define SC_PINCSR_CD_INS_F_Pos (3)
7811 #define SC_PINCSR_CD_INS_F_Msk (0x1ul << SC_PINCSR_CD_INS_F_Pos)
7813 #define SC_PINCSR_CD_PIN_ST_Pos (4)
7814 #define SC_PINCSR_CD_PIN_ST_Msk (0x1ul << SC_PINCSR_CD_PIN_ST_Pos)
7816 #define SC_PINCSR_CLK_KEEP_Pos (6)
7817 #define SC_PINCSR_CLK_KEEP_Msk (0x1ul << SC_PINCSR_CLK_KEEP_Pos)
7819 #define SC_PINCSR_ADAC_CD_EN_Pos (7)
7820 #define SC_PINCSR_ADAC_CD_EN_Msk (0x1ul << SC_PINCSR_ADAC_CD_EN_Pos)
7822 #define SC_PINCSR_SC_OEN_ST_Pos (8)
7823 #define SC_PINCSR_SC_OEN_ST_Msk (0x1ul << SC_PINCSR_SC_OEN_ST_Pos)
7825 #define SC_PINCSR_SC_DATA_O_Pos (9)
7826 #define SC_PINCSR_SC_DATA_O_Msk (0x1ul << SC_PINCSR_SC_DATA_O_Pos)
7828 #define SC_PINCSR_CD_LEV_Pos (10)
7829 #define SC_PINCSR_CD_LEV_Msk (0x1ul << SC_PINCSR_CD_LEV_Pos)
7831 #define SC_PINCSR_SC_DATA_I_ST_Pos (16)
7832 #define SC_PINCSR_SC_DATA_I_ST_Msk (0x1ul << SC_PINCSR_SC_DATA_I_ST_Pos)
7834 #define SC_TMR0_CNT_Pos (0)
7835 #define SC_TMR0_CNT_Msk (0xfffffful << SC_TMR0_CNT_Pos)
7837 #define SC_TMR0_MODE_Pos (24)
7838 #define SC_TMR0_MODE_Msk (0xful << SC_TMR0_MODE_Pos)
7840 #define SC_TMR1_CNT_Pos (0)
7841 #define SC_TMR1_CNT_Msk (0xfful << SC_TMR1_CNT_Pos)
7843 #define SC_TMR1_MODE_Pos (24)
7844 #define SC_TMR1_MODE_Msk (0xful << SC_TMR1_MODE_Pos)
7846 #define SC_TMR2_CNT_Pos (0)
7847 #define SC_TMR2_CNT_Msk (0xfful << SC_TMR2_CNT_Pos)
7849 #define SC_TMR2_MODE_Pos (24)
7850 #define SC_TMR2_MODE_Msk (0xful << SC_TMR2_MODE_Pos)
7852 #define SC_TDRA_TDR0_Pos (0)
7853 #define SC_TDRA_TDR0_Msk (0xfffffful << SC_TDRA_TDR0_Pos)
7855 #define SC_TDRB_TDR1_Pos (0)
7856 #define SC_TDRB_TDR1_Msk (0xfful << SC_TDRB_TDR1_Pos)
7858 #define SC_TDRB_TDR2_Pos (8)
7859 #define SC_TDRB_TDR2_Msk (0xfful << SC_TDRB_TDR2_Pos) /* SC_CONST */
7862 /* end of SC register group */
7863
7864
7865 /*---------------------- Serial Peripheral Interface Controller -------------------------*/
7871 typedef struct
7872 {
7873
7874
7984 __IO uint32_t CTL;
7985
8020 __IO uint32_t STATUS;
8021
8039 __IO uint32_t CLKDIV;
8040
8086 __IO uint32_t SSR;
8087
8102 __I uint32_t RX0;
8103
8118 __I uint32_t RX1;
8119
8121 uint32_t RESERVE0[2];
8123
8124
8139 __O uint32_t TX0;
8140
8155 __O uint32_t TX1;
8156
8158 uint32_t RESERVE1[3];
8160
8161
8175 __IO uint32_t VARCLK;
8176
8205 __IO uint32_t PDMA;
8206
8223 __IO uint32_t FFCLR;
8224
8225 } SPI_T;
8226
8232 #define SPI_CTL_GO_BUSY_Pos (0)
8233 #define SPI_CTL_GO_BUSY_Msk (0x1ul << SPI_CTL_GO_BUSY_Pos)
8235 #define SPI_CTL_RX_NEG_Pos (1)
8236 #define SPI_CTL_RX_NEG_Msk (0x1ul << SPI_CTL_RX_NEG_Pos)
8238 #define SPI_CTL_TX_NEG_Pos (2)
8239 #define SPI_CTL_TX_NEG_Msk (0x1ul << SPI_CTL_TX_NEG_Pos)
8241 #define SPI_CTL_TX_BIT_LEN_Pos (3)
8242 #define SPI_CTL_TX_BIT_LEN_Msk (0x1ful << SPI_CTL_TX_BIT_LEN_Pos)
8244 #define SPI_CTL_TX_NUM_Pos (8)
8245 #define SPI_CTL_TX_NUM_Msk (0x3ul << SPI_CTL_TX_NUM_Pos)
8247 #define SPI_CTL_LSB_Pos (10)
8248 #define SPI_CTL_LSB_Msk (0x1ul << SPI_CTL_LSB_Pos)
8250 #define SPI_CTL_CLKP_Pos (11)
8251 #define SPI_CTL_CLKP_Msk (0x1ul << SPI_CTL_CLKP_Pos)
8253 #define SPI_CTL_SP_CYCLE_Pos (12)
8254 #define SPI_CTL_SP_CYCLE_Msk (0xful << SPI_CTL_SP_CYCLE_Pos)
8256 #define SPI_CTL_INTEN_Pos (17)
8257 #define SPI_CTL_INTEN_Msk (0x1ul << SPI_CTL_INTEN_Pos)
8259 #define SPI_CTL_SLAVE_Pos (18)
8260 #define SPI_CTL_SLAVE_Msk (0x1ul << SPI_CTL_SLAVE_Pos)
8262 #define SPI_CTL_REORDER_Pos (19)
8263 #define SPI_CTL_REORDER_Msk (0x3ul << SPI_CTL_REORDER_Pos)
8265 #define SPI_CTL_FIFOM_Pos (21)
8266 #define SPI_CTL_FIFOM_Msk (0x1ul << SPI_CTL_FIFOM_Pos)
8268 #define SPI_CTL_TWOB_Pos (22)
8269 #define SPI_CTL_TWOB_Msk (0x1ul << SPI_CTL_TWOB_Pos)
8271 #define SPI_CTL_VARCLK_EN_Pos (23)
8272 #define SPI_CTL_VARCLK_EN_Msk (0x1ul << SPI_CTL_VARCLK_EN_Pos)
8274 #define SPI_CTL_WKEUP_EN_Pos (31)
8275 #define SPI_CTL_WKEUP_EN_Msk (0x1ul << SPI_CTL_WKEUP_EN_Pos)
8277 #define SPI_STATUS_RX_EMPTY_Pos (0)
8278 #define SPI_STATUS_RX_EMPTY_Msk (0x1ul << SPI_STATUS_RX_EMPTY_Pos)
8280 #define SPI_STATUS_RX_FULL_Pos (1)
8281 #define SPI_STATUS_RX_FULL_Msk (0x1ul << SPI_STATUS_RX_FULL_Pos)
8283 #define SPI_STATUS_TX_EMPTY_Pos (2)
8284 #define SPI_STATUS_TX_EMPTY_Msk (0x1ul << SPI_STATUS_TX_EMPTY_Pos)
8286 #define SPI_STATUS_TX_FULL_Pos (3)
8287 #define SPI_STATUS_TX_FULL_Msk (0x1ul << SPI_STATUS_TX_FULL_Pos)
8289 #define SPI_STATUS_LTRIG_FLAG_Pos (4)
8290 #define SPI_STATUS_LTRIG_FLAG_Msk (0x1ul << SPI_STATUS_LTRIG_FLAG_Pos)
8292 #define SPI_STATUS_SLV_START_INTSTS_Pos (6)
8293 #define SPI_STATUS_SLV_START_INTSTS_Msk (0x1ul << SPI_STATUS_SLV_START_INTSTS_Pos)
8295 #define SPI_STATUS_INTSTS_Pos (7)
8296 #define SPI_STATUS_INTSTS_Msk (0x1ul << SPI_STATUS_INTSTS_Pos)
8298 #define SPI_CLKDIV_DIVIDER1_Pos (0)
8299 #define SPI_CLKDIV_DIVIDER1_Msk (0xfffful << SPI_CLKDIV_DIVIDER1_Pos)
8301 #define SPI_CLKDIV_DIVIDER2_Pos (16)
8302 #define SPI_CLKDIV_DIVIDER2_Msk (0xfffful << SPI_CLKDIV_DIVIDER2_Pos)
8304 #define SPI_SSR_SSR_Pos (0)
8305 #define SPI_SSR_SSR_Msk (0x3ul << SPI_SSR_SSR_Pos)
8307 #define SPI_SSR_SS_LVL_Pos (2)
8308 #define SPI_SSR_SS_LVL_Msk (0x1ul << SPI_SSR_SS_LVL_Pos)
8310 #define SPI_SSR_AUTOSS_Pos (3)
8311 #define SPI_SSR_AUTOSS_Msk (0x1ul << SPI_SSR_AUTOSS_Pos)
8313 #define SPI_SSR_SS_LTRIG_Pos (4)
8314 #define SPI_SSR_SS_LTRIG_Msk (0x1ul << SPI_SSR_SS_LTRIG_Pos)
8316 #define SPI_SSR_NOSLVSEL_Pos (5)
8317 #define SPI_SSR_NOSLVSEL_Msk (0x1ul << SPI_SSR_NOSLVSEL_Pos)
8319 #define SPI_SSR_SLV_ABORT_Pos (8)
8320 #define SPI_SSR_SLV_ABORT_Msk (0x1ul << SPI_SSR_SLV_ABORT_Pos)
8322 #define SPI_SSR_SSTA_INTEN_Pos (9)
8323 #define SPI_SSR_SSTA_INTEN_Msk (0x1ul << SPI_SSR_SSTA_INTEN_Pos)
8325 #define SPI_RX0_RDATA_Pos (0)
8326 #define SPI_RX0_RDATA_Msk (0xfffffffful << SPI_RX0_RDATA_Pos)
8328 #define SPI_RX1_RDATA_Pos (0)
8329 #define SPI_RX1_RDATA_Msk (0xfffffffful << SPI_RX1_RDATA_Pos)
8331 #define SPI_TX0_TDATA_Pos (0)
8332 #define SPI_TX0_TDATA_Msk (0xfffffffful << SPI_TX0_TDATA_Pos)
8334 #define SPI_TX1_TDATA_Pos (0)
8335 #define SPI_TX1_TDATA_Msk (0xfffffffful << SPI_TX1_TDATA_Pos)
8337 #define SPI_VARCLK_VARCLK_Pos (0)
8338 #define SPI_VARCLK_VARCLK_Msk (0xfffffffful << SPI_VARCLK_VARCLK_Pos)
8340 #define SPI_PDMA_TX_DMA_EN_Pos (0)
8341 #define SPI_PDMA_TX_DMA_EN_Msk (0x1ul << SPI_PDMA_TX_DMA_EN_Pos)
8343 #define SPI_PDMA_RX_DMA_EN_Pos (1)
8344 #define SPI_PDMA_RX_DMA_EN_Msk (0x1ul << SPI_PDMA_RX_DMA_EN_Pos)
8346 #define SPI_PDMA_PDMA_RST_Pos (2)
8347 #define SPI_PDMA_PDMA_RST_Msk (0x1ul << SPI_PDMA_PDMA_RST_Pos)
8349 #define SPI_FFCLR_RX_CLR_Pos (0)
8350 #define SPI_FFCLR_RX_CLR_Msk (0x1ul << SPI_FFCLR_RX_CLR_Pos)
8352 #define SPI_FFCLR_TX_CLR_Pos (1)
8353 #define SPI_FFCLR_TX_CLR_Msk (0x1ul << SPI_FFCLR_TX_CLR_Pos) /* SPI_CONST */
8356 /* end of SPI register group */
8357
8358
8359 /*---------------------- Timer Controller -------------------------*/
8365 typedef struct
8366 {
8367
8368
8495 __IO uint32_t CTL;
8496
8508 __IO uint32_t PRECNT;
8509
8525 __IO uint32_t CMPR;
8526
8543 __IO uint32_t IER;
8544
8574 __IO uint32_t ISR;
8575
8586 __I uint32_t DR;
8587
8599 __I uint32_t TCAP;
8600 } TIMER_T;
8601
8602
8608 #define TIMER_CTL_TMR_EN_Pos (0)
8609 #define TIMER_CTL_TMR_EN_Msk (0x1ul << TIMER_CTL_TMR_EN_Pos)
8611 #define TIMER_CTL_SW_RST_Pos (1)
8612 #define TIMER_CTL_SW_RST_Msk (0x1ul << TIMER_CTL_SW_RST_Pos)
8614 #define TIMER_CTL_WAKE_EN_Pos (2)
8615 #define TIMER_CTL_WAKE_EN_Msk (0x1ul << TIMER_CTL_WAKE_EN_Pos)
8617 #define TIMER_CTL_DBGACK_EN_Pos (3)
8618 #define TIMER_CTL_DBGACK_EN_Msk (0x1ul << TIMER_CTL_DBGACK_EN_Pos)
8620 #define TIMER_CTL_MODE_SEL_Pos (4)
8621 #define TIMER_CTL_MODE_SEL_Msk (0x3ul << TIMER_CTL_MODE_SEL_Pos)
8623 #define TIMER_CTL_TMR_ACT_Pos (7)
8624 #define TIMER_CTL_TMR_ACT_Msk (0x1ul << TIMER_CTL_TMR_ACT_Pos)
8626 #define TIMER_CTL_ADC_TEEN_Pos (8)
8627 #define TIMER_CTL_ADC_TEEN_Msk (0x1ul << TIMER_CTL_ADC_TEEN_Pos)
8629 #define TIMER_CTL_PDMA_TEEN_Pos (10)
8630 #define TIMER_CTL_PDMA_TEEN_Msk (0x1ul << TIMER_CTL_PDMA_TEEN_Pos)
8632 #define TIMER_CTL_CAP_TRG_EN_Pos (11)
8633 #define TIMER_CTL_CAP_TRG_EN_Msk (0x1ul << TIMER_CTL_CAP_TRG_EN_Pos)
8635 #define TIMER_CTL_EVENT_EN_Pos (12)
8636 #define TIMER_CTL_EVENT_EN_Msk (0x1ul << TIMER_CTL_EVENT_EN_Pos)
8638 #define TIMER_CTL_EVENT_EDGE_Pos (13)
8639 #define TIMER_CTL_EVENT_EDGE_Msk (0x1ul << TIMER_CTL_EVENT_EDGE_Pos)
8641 #define TIMER_CTL_EVNT_DEB_EN_Pos (14)
8642 #define TIMER_CTL_EVNT_DEB_EN_Msk (0x1ul << TIMER_CTL_EVNT_DEB_EN_Pos)
8644 #define TIMER_CTL_TCAP_EN_Pos (16)
8645 #define TIMER_CTL_TCAP_EN_Msk (0x1ul << TIMER_CTL_TCAP_EN_Pos)
8647 #define TIMER_CTL_TCAP_MODE_Pos (17)
8648 #define TIMER_CTL_TCAP_MODE_Msk (0x1ul << TIMER_CTL_TCAP_MODE_Pos)
8650 #define TIMER_CTL_TCAP_EDGE_Pos (18)
8651 #define TIMER_CTL_TCAP_EDGE_Msk (0x3ul << TIMER_CTL_TCAP_EDGE_Pos)
8653 #define TIMER_CTL_TCAP_CNT_MODE_Pos (20)
8654 #define TIMER_CTL_TCAP_CNT_MODE_Msk (0x1ul << TIMER_CTL_TCAP_CNT_MODE_Pos)
8656 #define TIMER_CTL_TCAP_DEB_EN_Pos (22)
8657 #define TIMER_CTL_TCAP_DEB_EN_Msk (0x1ul << TIMER_CTL_TCAP_DEB_EN_Pos)
8659 #define TIMER_CTL_INTR_TRG_EN_Pos (24)
8660 #define TIMER_CTL_INTR_TRG_EN_Msk (0x1ul << TIMER_CTL_INTR_TRG_EN_Pos)
8662 #define TIMER_PRECNT_PRESCALE_CNT_Pos (0)
8663 #define TIMER_PRECNT_PRESCALE_CNT_Msk (0xfful << TIMER_PRECNT_PRESCALE_CNT_Pos)
8665 #define TIMER_CMPR_TMR_CMP_Pos (0)
8666 #define TIMER_CMPR_TMR_CMP_Msk (0xfffffful << TIMER_CMPR_TMR_CMP_Pos)
8668 #define TIMER_IER_TMR_IE_Pos (0)
8669 #define TIMER_IER_TMR_IE_Msk (0x1ul << TIMER_IER_TMR_IE_Pos)
8671 #define TIMER_IER_TCAP_IE_Pos (1)
8672 #define TIMER_IER_TCAP_IE_Msk (0x1ul << TIMER_IER_TCAP_IE_Pos)
8674 #define TIMER_ISR_TMR_IS_Pos (0)
8675 #define TIMER_ISR_TMR_IS_Msk (0x1ul << TIMER_ISR_TMR_IS_Pos)
8677 #define TIMER_ISR_TCAP_IS_Pos (1)
8678 #define TIMER_ISR_TCAP_IS_Msk (0x1ul << TIMER_ISR_TCAP_IS_Pos)
8680 #define TIMER_ISR_TMR_WAKE_STS_Pos (4)
8681 #define TIMER_ISR_TMR_WAKE_STS_Msk (0x1ul << TIMER_ISR_TMR_WAKE_STS_Pos)
8683 #define TIMER_ISR_NCAP_DET_STS_Pos (5)
8684 #define TIMER_ISR_NCAP_DET_STS_Msk (0x1ul << TIMER_ISR_NCAP_DET_STS_Pos)
8686 #define TIMER_DR_TDR_Pos (0)
8687 #define TIMER_DR_TDR_Msk (0xfffffful << TIMER_DR_TDR_Pos)
8689 #define TIMER_TCAP_CAP_Pos (0)
8690 #define TIMER_TCAP_CAP_Msk (0xfffffful << TIMER_TCAP_CAP_Pos) /* TIMER_CONST */
8692
8693 /* end of TMR register group */
8695
8696
8697
8698
8699 /*---------------------- Universal Asynchronous Receiver/Transmitter Controller -------------------------*/
8705 typedef struct
8706 {
8707
8708
8709 union
8710 {
8711
8722 __I uint32_t RBR;
8723
8724
8735 __O uint32_t THR;
8736 };
8737
8794 __IO uint32_t CTL;
8795
8838 __IO uint32_t TLCTL;
8839
8875 __IO uint32_t IER;
8876
8923 __IO uint32_t ISR;
8924
8975 __IO uint32_t TRSR;
8976
9026 __IO uint32_t FSR;
9027
9052 __IO uint32_t MCSR;
9053
9075 __IO uint32_t TMCTL;
9076
9091 __IO uint32_t BAUD;
9092
9094 uint32_t RESERVE0[2];
9096
9097
9116 __IO uint32_t IRCR;
9117
9169 __IO uint32_t ALT_CTL;
9170
9184 __IO uint32_t FUN_SEL;
9185
9186 } UART_T;
9187
9193 #define UART_DAT_DAT_Pos (0)
9194 #define UART_DAT_DAT_Msk (0xfful << UART_DAT_DAT_Pos)
9196 #define UART_CTL_RX_RST_Pos (0)
9197 #define UART_CTL_RX_RST_Msk (0x1ul << UART_CTL_RX_RST_Pos)
9199 #define UART_CTL_TX_RST_Pos (1)
9200 #define UART_CTL_TX_RST_Msk (0x1ul << UART_CTL_TX_RST_Pos)
9202 #define UART_CTL_RX_DIS_Pos (2)
9203 #define UART_CTL_RX_DIS_Msk (0x1ul << UART_CTL_RX_DIS_Pos)
9205 #define UART_CTL_TX_DIS_Pos (3)
9206 #define UART_CTL_TX_DIS_Msk (0x1ul << UART_CTL_TX_DIS_Pos)
9208 #define UART_CTL_AUTO_RTS_EN_Pos (4)
9209 #define UART_CTL_AUTO_RTS_EN_Msk (0x1ul << UART_CTL_AUTO_RTS_EN_Pos)
9211 #define UART_CTL_AUTO_CTS_EN_Pos (5)
9212 #define UART_CTL_AUTO_CTS_EN_Msk (0x1ul << UART_CTL_AUTO_CTS_EN_Pos)
9214 #define UART_CTL_DMA_RX_EN_Pos (6)
9215 #define UART_CTL_DMA_RX_EN_Msk (0x1ul << UART_CTL_DMA_RX_EN_Pos)
9217 #define UART_CTL_DMA_TX_EN_Pos (7)
9218 #define UART_CTL_DMA_TX_EN_Msk (0x1ul << UART_CTL_DMA_TX_EN_Pos)
9220 #define UART_CTL_WAKE_CTS_EN_Pos (8)
9221 #define UART_CTL_WAKE_CTS_EN_Msk (0x1ul << UART_CTL_WAKE_CTS_EN_Pos)
9223 #define UART_CTL_WAKE_DATA_EN_Pos (9)
9224 #define UART_CTL_WAKE_DATA_EN_Msk (0x1ul << UART_CTL_WAKE_DATA_EN_Pos)
9226 #define UART_CTL_ABAUD_EN_Pos (12)
9227 #define UART_CTL_ABAUD_EN_Msk (0x1ul << UART_CTL_ABAUD_EN_Pos)
9229 #define UART_TLCTL_DATA_LEN_Pos (0)
9230 #define UART_TLCTL_DATA_LEN_Msk (0x3ul << UART_TLCTL_DATA_LEN_Pos)
9232 #define UART_TLCTL_NSB_Pos (2)
9233 #define UART_TLCTL_NSB_Msk (0x1ul << UART_TLCTL_NSB_Pos)
9235 #define UART_TLCTL_PBE_Pos (3)
9236 #define UART_TLCTL_PBE_Msk (0x1ul << UART_TLCTL_PBE_Pos)
9238 #define UART_TLCTL_EPE_Pos (4)
9239 #define UART_TLCTL_EPE_Msk (0x1ul << UART_TLCTL_EPE_Pos)
9241 #define UART_TLCTL_SPE_Pos (5)
9242 #define UART_TLCTL_SPE_Msk (0x1ul << UART_TLCTL_SPE_Pos)
9244 #define UART_TLCTL_BCB_Pos (6)
9245 #define UART_TLCTL_BCB_Msk (0x1ul << UART_TLCTL_BCB_Pos)
9247 #define UART_TLCTL_RFITL_Pos (8)
9248 #define UART_TLCTL_RFITL_Msk (0x3ul << UART_TLCTL_RFITL_Pos)
9250 #define UART_TLCTL_RTS_TRI_LEV_Pos (12)
9251 #define UART_TLCTL_RTS_TRI_LEV_Msk (0x3ul << UART_TLCTL_RTS_TRI_LEV_Pos)
9253 #define UART_IER_RDA_IE_Pos (0)
9254 #define UART_IER_RDA_IE_Msk (0x1ul << UART_IER_RDA_IE_Pos)
9256 #define UART_IER_THRE_IE_Pos (1)
9257 #define UART_IER_THRE_IE_Msk (0x1ul << UART_IER_THRE_IE_Pos)
9259 #define UART_IER_RLS_IE_Pos (2)
9260 #define UART_IER_RLS_IE_Msk (0x1ul << UART_IER_RLS_IE_Pos)
9262 #define UART_IER_MODEM_IE_Pos (3)
9263 #define UART_IER_MODEM_IE_Msk (0x1ul << UART_IER_MODEM_IE_Pos)
9265 #define UART_IER_RTO_IE_Pos (4)
9266 #define UART_IER_RTO_IE_Msk (0x1ul << UART_IER_RTO_IE_Pos)
9268 #define UART_IER_BUF_ERR_IE_Pos (5)
9269 #define UART_IER_BUF_ERR_IE_Msk (0x1ul << UART_IER_BUF_ERR_IE_Pos)
9271 #define UART_IER_WAKE_IE_Pos (6)
9272 #define UART_IER_WAKE_IE_Msk (0x1ul << UART_IER_WAKE_IE_Pos)
9274 #define UART_IER_ABAUD_IE_Pos (7)
9275 #define UART_IER_ABAUD_IE_Msk (0x1ul << UART_IER_ABAUD_IE_Pos)
9277 #define UART_IER_LIN_IE_Pos (8)
9278 #define UART_IER_LIN_IE_Msk (0x1ul << UART_IER_LIN_IE_Pos)
9280 #define UART_ISR_RDA_IS_Pos (0)
9281 #define UART_ISR_RDA_IS_Msk (0x1ul << UART_ISR_RDA_IS_Pos)
9283 #define UART_ISR_THRE_IS_Pos (1)
9284 #define UART_ISR_THRE_IS_Msk (0x1ul << UART_ISR_THRE_IS_Pos)
9286 #define UART_ISR_RLS_IS_Pos (2)
9287 #define UART_ISR_RLS_IS_Msk (0x1ul << UART_ISR_RLS_IS_Pos)
9289 #define UART_ISR_MODEM_IS_Pos (3)
9290 #define UART_ISR_MODEM_IS_Msk (0x1ul << UART_ISR_MODEM_IS_Pos)
9292 #define UART_ISR_RTO_IS_Pos (4)
9293 #define UART_ISR_RTO_IS_Msk (0x1ul << UART_ISR_RTO_IS_Pos)
9295 #define UART_ISR_BUF_ERR_IS_Pos (5)
9296 #define UART_ISR_BUF_ERR_IS_Msk (0x1ul << UART_ISR_BUF_ERR_IS_Pos)
9298 #define UART_ISR_WAKE_IS_Pos (6)
9299 #define UART_ISR_WAKE_IS_Msk (0x1ul << UART_ISR_WAKE_IS_Pos)
9301 #define UART_ISR_ABAUD_IS_Pos (7)
9302 #define UART_ISR_ABAUD_IS_Msk (0x1ul << UART_ISR_ABAUD_IS_Pos)
9304 #define UART_ISR_LIN_IS_Pos (8)
9305 #define UART_ISR_LIN_IS_Msk (0x1ul << UART_ISR_LIN_IS_Pos)
9307 #define UART_TRSR_RS485_ADDET_F_Pos (0)
9308 #define UART_TRSR_RS485_ADDET_F_Msk (0x1ul << UART_TRSR_RS485_ADDET_F_Pos)
9310 #define UART_TRSR_ABAUD_F_Pos (1)
9311 #define UART_TRSR_ABAUD_F_Msk (0x1ul << UART_TRSR_ABAUD_F_Pos)
9313 #define UART_TRSR_ABAUD_TOUT_F_Pos (2)
9314 #define UART_TRSR_ABAUD_TOUT_F_Msk (0x1ul << UART_TRSR_ABAUD_TOUT_F_Pos)
9316 #define UART_TRSR_LIN_TX_F_Pos (3)
9317 #define UART_TRSR_LIN_TX_F_Msk (0x1ul << UART_TRSR_LIN_TX_F_Pos)
9319 #define UART_TRSR_LIN_RX_F_Pos (4)
9320 #define UART_TRSR_LIN_RX_F_Msk (0x1ul << UART_TRSR_LIN_RX_F_Pos)
9322 #define UART_TRSR_BIT_ERR_F_Pos (5)
9323 #define UART_TRSR_BIT_ERR_F_Msk (0x1ul << UART_TRSR_BIT_ERR_F_Pos)
9325 #define UART_TRSR_LIN_RX_SYNC_ERR_F_Pos (8)
9326 #define UART_TRSR_LIN_RX_SYNC_ERR_F_Msk (0x1ul << UART_TRSR_LIN_RX_SYNC_ERR_F_Pos)
9328 #define UART_FSR_RX_OVER_F_Pos (0)
9329 #define UART_FSR_RX_OVER_F_Msk (0x1ul << UART_FSR_RX_OVER_F_Pos)
9331 #define UART_FSR_RX_EMPTY_F_Pos (1)
9332 #define UART_FSR_RX_EMPTY_F_Msk (0x1ul << UART_FSR_RX_EMPTY_F_Pos)
9334 #define UART_FSR_RX_FULL_F_Pos (2)
9335 #define UART_FSR_RX_FULL_F_Msk (0x1ul << UART_FSR_RX_FULL_F_Pos)
9337 #define UART_FSR_PE_F_Pos (4)
9338 #define UART_FSR_PE_F_Msk (0x1ul << UART_FSR_PE_F_Pos)
9340 #define UART_FSR_FE_F_Pos (5)
9341 #define UART_FSR_FE_F_Msk (0x1ul << UART_FSR_FE_F_Pos)
9343 #define UART_FSR_BI_F_Pos (6)
9344 #define UART_FSR_BI_F_Msk (0x1ul << UART_FSR_BI_F_Pos)
9346 #define UART_FSR_TX_OVER_F_Pos (8)
9347 #define UART_FSR_TX_OVER_F_Msk (0x1ul << UART_FSR_TX_OVER_F_Pos)
9349 #define UART_FSR_TX_EMPTY_F_Pos (9)
9350 #define UART_FSR_TX_EMPTY_F_Msk (0x1ul << UART_FSR_TX_EMPTY_F_Pos)
9352 #define UART_FSR_TX_FULL_F_Pos (10)
9353 #define UART_FSR_TX_FULL_F_Msk (0x1ul << UART_FSR_TX_FULL_F_Pos)
9355 #define UART_FSR_TE_F_Pos (11)
9356 #define UART_FSR_TE_F_Msk (0x1ul << UART_FSR_TE_F_Pos)
9358 #define UART_FSR_RX_POINTER_F_Pos (16)
9359 #define UART_FSR_RX_POINTER_F_Msk (0x1ful << UART_FSR_RX_POINTER_F_Pos)
9361 #define UART_FSR_TX_POINTER_F_Pos (24)
9362 #define UART_FSR_TX_POINTER_F_Msk (0x1ful << UART_FSR_TX_POINTER_F_Pos)
9364 #define UART_MCSR_LEV_RTS_Pos (0)
9365 #define UART_MCSR_LEV_RTS_Msk (0x1ul << UART_MCSR_LEV_RTS_Pos)
9367 #define UART_MCSR_RTS_ST_Pos (1)
9368 #define UART_MCSR_RTS_ST_Msk (0x1ul << UART_MCSR_RTS_ST_Pos)
9370 #define UART_MCSR_LEV_CTS_Pos (16)
9371 #define UART_MCSR_LEV_CTS_Msk (0x1ul << UART_MCSR_LEV_CTS_Pos)
9373 #define UART_MCSR_CTS_ST_Pos (17)
9374 #define UART_MCSR_CTS_ST_Msk (0x1ul << UART_MCSR_CTS_ST_Pos)
9376 #define UART_MCSR_DCT_F_Pos (18)
9377 #define UART_MCSR_DCT_F_Msk (0x1ul << UART_MCSR_DCT_F_Pos)
9379 #define UART_TMCTL_TOIC_Pos (0)
9380 #define UART_TMCTL_TOIC_Msk (0x1fful << UART_TMCTL_TOIC_Pos)
9382 #define UART_TMCTL_DLY_Pos (16)
9383 #define UART_TMCTL_DLY_Msk (0xfful << UART_TMCTL_DLY_Pos)
9385 #define UART_BAUD_BRD_Pos (0)
9386 #define UART_BAUD_BRD_Msk (0xfffful << UART_BAUD_BRD_Pos)
9388 #define UART_BAUD_DIV_16_EN_Pos (31)
9389 #define UART_BAUD_DIV_16_EN_Msk (0x1ul << UART_BAUD_DIV_16_EN_Pos)
9391 #define UART_IRCR_TX_SELECT_Pos (1)
9392 #define UART_IRCR_TX_SELECT_Msk (0x1ul << UART_IRCR_TX_SELECT_Pos)
9394 #define UART_IRCR_INV_TX_Pos (5)
9395 #define UART_IRCR_INV_TX_Msk (0x1ul << UART_IRCR_INV_TX_Pos)
9397 #define UART_IRCR_INV_RX_Pos (6)
9398 #define UART_IRCR_INV_RX_Msk (0x1ul << UART_IRCR_INV_RX_Pos)
9400 #define UART_ALT_CTL_LIN_TX_BCNT_Pos (0)
9401 #define UART_ALT_CTL_LIN_TX_BCNT_Msk (0x7ul << UART_ALT_CTL_LIN_TX_BCNT_Pos)
9403 #define UART_ALT_CTL_LIN_HEAD_SEL_Pos (4)
9404 #define UART_ALT_CTL_LIN_HEAD_SEL_Msk (0x3ul << UART_ALT_CTL_LIN_HEAD_SEL_Pos)
9406 #define UART_ALT_CTL_LIN_RX_EN_Pos (6)
9407 #define UART_ALT_CTL_LIN_RX_EN_Msk (0x1ul << UART_ALT_CTL_LIN_RX_EN_Pos)
9409 #define UART_ALT_CTL_LIN_TX_EN_Pos (7)
9410 #define UART_ALT_CTL_LIN_TX_EN_Msk (0x1ul << UART_ALT_CTL_LIN_TX_EN_Pos)
9412 #define UART_ALT_CTL_Bit_ERR_EN_Pos (8)
9413 #define UART_ALT_CTL_Bit_ERR_EN_Msk (0x1ul << UART_ALT_CTL_Bit_ERR_EN_Pos)
9415 #define UART_ALT_CTL_RS485_NMM_Pos (16)
9416 #define UART_ALT_CTL_RS485_NMM_Msk (0x1ul << UART_ALT_CTL_RS485_NMM_Pos)
9418 #define UART_ALT_CTL_RS485_AAD_Pos (17)
9419 #define UART_ALT_CTL_RS485_AAD_Msk (0x1ul << UART_ALT_CTL_RS485_AAD_Pos)
9421 #define UART_ALT_CTL_RS485_AUD_Pos (18)
9422 #define UART_ALT_CTL_RS485_AUD_Msk (0x1ul << UART_ALT_CTL_RS485_AUD_Pos)
9424 #define UART_ALT_CTL_RS485_ADD_EN_Pos (19)
9425 #define UART_ALT_CTL_RS485_ADD_EN_Msk (0x1ul << UART_ALT_CTL_RS485_ADD_EN_Pos)
9427 #define UART_ALT_CTL_ADDR_PID_MATCH_Pos (24)
9428 #define UART_ALT_CTL_ADDR_PID_MATCH_Msk (0xfful << UART_ALT_CTL_ADDR_PID_MATCH_Pos)
9430 #define UART_FUN_SEL_FUN_SEL_Pos (0)
9431 #define UART_FUN_SEL_FUN_SEL_Msk (0x3ul << UART_FUN_SEL_FUN_SEL_Pos) /* UART_CONST */
9434 /* end of UART register group */
9435
9436
9437 /*---------------------- USB Device Controller -------------------------*/
9446 typedef struct
9447 {
9448
9449
9460 __IO uint32_t BUFSEG;
9461
9480 __IO uint32_t MXPLD;
9481
9517 __IO uint32_t CFG;
9519 uint32_t RESERVE;
9521
9522 } USBD_EP_T;
9523
9524 typedef struct
9525 {
9526
9527
9559 __IO uint32_t CTL;
9560
9584 __I uint32_t BUSSTS;
9585
9606 __IO uint32_t INTEN;
9607
9653 __IO uint32_t INTSTS;
9654
9665 __IO uint32_t FADDR;
9666
9702 __I uint32_t EPSTS;
9703
9715 __IO uint32_t BUFSEG;
9716
9718 uint32_t RESERVE0;
9720
9721 USBD_EP_T EP[6];
9722
9724 uint32_t RESERVE1[9];
9726
9727
9751 __IO uint32_t PDMA;
9752
9753 } USBD_T;
9754
9760 #define USBD_CTL_USB_EN_Pos (0)
9761 #define USBD_CTL_USB_EN_Msk (0x1ul << USBD_CTL_USB_EN_Pos)
9763 #define USBD_CTL_PHY_EN_Pos (1)
9764 #define USBD_CTL_PHY_EN_Msk (0x1ul << USBD_CTL_PHY_EN_Pos)
9766 #define USBD_CTL_PWRDB_Pos (2)
9767 #define USBD_CTL_PWRDB_Msk (0x1ul << USBD_CTL_PWRDB_Pos)
9769 #define USBD_CTL_DPPU_EN_Pos (3)
9770 #define USBD_CTL_DPPU_EN_Msk (0x1ul << USBD_CTL_DPPU_EN_Pos)
9772 #define USBD_CTL_DRVSE0_Pos (4)
9773 #define USBD_CTL_DRVSE0_Msk (0x1ul << USBD_CTL_DRVSE0_Pos)
9775 #define USBD_CTL_RWAKEUP_Pos (8)
9776 #define USBD_CTL_RWAKEUP_Msk (0x1ul << USBD_CTL_RWAKEUP_Pos)
9778 #define USBD_CTL_WAKEUP_EN_Pos (9)
9779 #define USBD_CTL_WAKEUP_EN_Msk (0x1ul << USBD_CTL_WAKEUP_EN_Pos)
9781 #define USBD_BUSSTS_USBRST_Pos (0)
9782 #define USBD_BUSSTS_USBRST_Msk (0x1ul << USBD_BUSSTS_USBRST_Pos)
9784 #define USBD_BUSSTS_SUSPEND_Pos (1)
9785 #define USBD_BUSSTS_SUSPEND_Msk (0x1ul << USBD_BUSSTS_SUSPEND_Pos)
9787 #define USBD_BUSSTS_RESUME_Pos (2)
9788 #define USBD_BUSSTS_RESUME_Msk (0x1ul << USBD_BUSSTS_RESUME_Pos)
9790 #define USBD_BUSSTS_TIMEOUT_Pos (3)
9791 #define USBD_BUSSTS_TIMEOUT_Msk (0x1ul << USBD_BUSSTS_TIMEOUT_Pos)
9793 #define USBD_BUSSTS_FLDET_Pos (4)
9794 #define USBD_BUSSTS_FLDET_Msk (0x1ul << USBD_BUSSTS_FLDET_Pos)
9796 #define USBD_INTEN_BUSEVT_IE_Pos (0)
9797 #define USBD_INTEN_BUSEVT_IE_Msk (0x1ul << USBD_INTEN_BUSEVT_IE_Pos)
9799 #define USBD_INTEN_USBEVT_IE_Pos (1)
9800 #define USBD_INTEN_USBEVT_IE_Msk (0x1ul << USBD_INTEN_USBEVT_IE_Pos)
9802 #define USBD_INTEN_FLDET_IE_Pos (2)
9803 #define USBD_INTEN_FLDET_IE_Msk (0x1ul << USBD_INTEN_FLDET_IE_Pos)
9805 #define USBD_INTEN_WAKEUP_IE_Pos (3)
9806 #define USBD_INTEN_WAKEUP_IE_Msk (0x1ul << USBD_INTEN_WAKEUP_IE_Pos)
9808 #define USBD_INTSTS_BUS_STS_Pos (0)
9809 #define USBD_INTSTS_BUS_STS_Msk (0x1ul << USBD_INTSTS_BUS_STS_Pos)
9811 #define USBD_INTSTS_USB_STS_Pos (1)
9812 #define USBD_INTSTS_USB_STS_Msk (0x1ul << USBD_INTSTS_USB_STS_Pos)
9814 #define USBD_INTSTS_FLD_STS_Pos (2)
9815 #define USBD_INTSTS_FLD_STS_Msk (0x1ul << USBD_INTSTS_FLD_STS_Pos)
9817 #define USBD_INTSTS_WKEUP_STS_Pos (3)
9818 #define USBD_INTSTS_WKEUP_STS_Msk (0x1ul << USBD_INTSTS_WKEUP_STS_Pos)
9820 #define USBD_INTSTS_EPEVT0_Pos (16)
9821 #define USBD_INTSTS_EPEVT0_Msk (0x1ul << USBD_INTSTS_EPEVT0_Pos)
9823 #define USBD_INTSTS_EPEVT1_Pos (17)
9824 #define USBD_INTSTS_EPEVT1_Msk (0x1ul << USBD_INTSTS_EPEVT1_Pos)
9826 #define USBD_INTSTS_EPEVT2_Pos (18)
9827 #define USBD_INTSTS_EPEVT2_Msk (0x1ul << USBD_INTSTS_EPEVT2_Pos)
9829 #define USBD_INTSTS_EPEVT3_Pos (19)
9830 #define USBD_INTSTS_EPEVT3_Msk (0x1ul << USBD_INTSTS_EPEVT3_Pos)
9832 #define USBD_INTSTS_EPEVT4_Pos (20)
9833 #define USBD_INTSTS_EPEVT4_Msk (0x1ul << USBD_INTSTS_EPEVT4_Pos)
9835 #define USBD_INTSTS_EPEVT5_Pos (21)
9836 #define USBD_INTSTS_EPEVT5_Msk (0x1ul << USBD_INTSTS_EPEVT5_Pos)
9838 #define USBD_INTSTS_SETUP_Pos (31)
9839 #define USBD_INTSTS_SETUP_Msk (0x1ul << USBD_INTSTS_SETUP_Pos)
9841 #define USBD_FADDR_FADDR_Pos (0)
9842 #define USBD_FADDR_FADDR_Msk (0x7ful << USBD_FADDR_FADDR_Pos)
9844 #define USBD_EPSTS_OVERRUN_Pos (7)
9845 #define USBD_EPSTS_OVERRUN_Msk (0x1ul << USBD_EPSTS_OVERRUN_Pos)
9847 #define USBD_EPSTS_EPSTS0_Pos (8)
9848 #define USBD_EPSTS_EPSTS0_Msk (0xful << USBD_EPSTS_EPSTS0_Pos)
9850 #define USBD_EPSTS_EPSTS1_Pos (12)
9851 #define USBD_EPSTS_EPSTS1_Msk (0xful << USBD_EPSTS_EPSTS1_Pos)
9853 #define USBD_EPSTS_EPSTS2_Pos (16)
9854 #define USBD_EPSTS_EPSTS2_Msk (0xful << USBD_EPSTS_EPSTS2_Pos)
9856 #define USBD_EPSTS_EPSTS3_Pos (20)
9857 #define USBD_EPSTS_EPSTS3_Msk (0xful << USBD_EPSTS_EPSTS3_Pos)
9859 #define USBD_EPSTS_EPSTS4_Pos (24)
9860 #define USBD_EPSTS_EPSTS4_Msk (0xful << USBD_EPSTS_EPSTS4_Pos)
9862 #define USBD_EPSTS_EPSTS5_Pos (28)
9863 #define USBD_EPSTS_EPSTS5_Msk (0xful << USBD_EPSTS_EPSTS5_Pos)
9865 #define USBD_BUFSEG_BUFSEG_Pos (3)
9866 #define USBD_BUFSEG_BUFSEG_Msk (0x3ful << USBD_BUFSEG_BUFSEG_Pos)
9868 #define USBD_MXPLD_MXPLD_Pos (0)
9869 #define USBD_MXPLD_MXPLD_Msk (0x1fful << USBD_MXPLD_MXPLD_Pos)
9871 #define USBD_CFG_EP_NUM_Pos (0)
9872 #define USBD_CFG_EP_NUM_Msk (0xful << USBD_CFG_EP_NUM_Pos)
9874 #define USBD_CFG_ISOCH_Pos (4)
9875 #define USBD_CFG_ISOCH_Msk (0x1ul << USBD_CFG_ISOCH_Pos)
9877 #define USBD_CFG_EPMODE_Pos (5)
9878 #define USBD_CFG_EPMODE_Msk (0x3ul << USBD_CFG_EPMODE_Pos)
9880 #define USBD_CFG_DSQ_SYNC_Pos (7)
9881 #define USBD_CFG_DSQ_SYNC_Msk (0x1ul << USBD_CFG_DSQ_SYNC_Pos)
9883 #define USBD_CFG_CSTALL_Pos (8)
9884 #define USBD_CFG_CSTALL_Msk (0x1ul << USBD_CFG_CSTALL_Pos)
9886 #define USBD_CFG_SSTALL_Pos (9)
9887 #define USBD_CFG_SSTALL_Msk (0x1ul << USBD_CFG_SSTALL_Pos)
9889 #define USBD_CFG_CLRRDY_Pos (15)
9890 #define USBD_CFG_CLRRDY_Msk (0x1ul << USBD_CFG_CLRRDY_Pos)
9892 #define USBD_PDMA_PDMA_RW_Pos (0)
9893 #define USBD_PDMA_PDMA_RW_Msk (0x1ul << USBD_PDMA_PDMA_RW_Pos)
9895 #define USBD_PDMA_PDMA_TRG_Pos (1)
9896 #define USBD_PDMA_PDMA_TRG_Msk (0x1ul << USBD_PDMA_PDMA_TRG_Pos)
9898 #define USBD_PDMA_BYTEM_Pos (2)
9899 #define USBD_PDMA_BYTEM_Msk (0x1ul << USBD_PDMA_BYTEM_Pos)
9901 #define USBD_PDMA_PDMA_RST_Pos (3)
9902 #define USBD_PDMA_PDMA_RST_Msk (0x1ul << USBD_PDMA_PDMA_RST_Pos) /* USBD_CONST */
9905 /* end of USBD register group */
9906
9907
9908 /*---------------------- Watch Dog Timer Controller -------------------------*/
9914 typedef struct
9915 {
9916
9917
9950 __IO uint32_t CTL;
9951
9963 __IO uint32_t IER;
9964
9994 __IO uint32_t ISR;
9995
9996 } WDT_T;
9997
10003 #define WDT_CTL_WTR_Pos (0)
10004 #define WDT_CTL_WTR_Msk (0x1ul << WDT_CTL_WTR_Pos)
10006 #define WDT_CTL_WTRE_Pos (1)
10007 #define WDT_CTL_WTRE_Msk (0x1ul << WDT_CTL_WTRE_Pos)
10009 #define WDT_CTL_WTWKE_Pos (2)
10010 #define WDT_CTL_WTWKE_Msk (0x1ul << WDT_CTL_WTWKE_Pos)
10012 #define WDT_CTL_WTE_Pos (3)
10013 #define WDT_CTL_WTE_Msk (0x1ul << WDT_CTL_WTE_Pos)
10015 #define WDT_CTL_WTIS_Pos (4)
10016 #define WDT_CTL_WTIS_Msk (0x7ul << WDT_CTL_WTIS_Pos)
10018 #define WDT_IER_IE_Pos (0)
10019 #define WDT_IER_IE_Msk (0x1ul << WDT_IER_IE_Pos)
10021 #define WDT_ISR_IS_Pos (0)
10022 #define WDT_ISR_IS_Msk (0x1ul << WDT_ISR_IS_Pos)
10024 #define WDT_ISR_RST_IS_Pos (1)
10025 #define WDT_ISR_RST_IS_Msk (0x1ul << WDT_ISR_RST_IS_Pos)
10027 #define WDT_ISR_WAKE_IS_Pos (2)
10028 #define WDT_ISR_WAKE_IS_Msk (0x1ul << WDT_ISR_WAKE_IS_Pos) /* WDT_CONST */
10031 /* end of WDT register group */
10032
10033 #if defined ( __CC_ARM )
10034 #pragma no_anon_unions
10035 #endif
10036
10042 #define FLASH_BASE ((uint32_t)0x00000000)
10043 #define SRAM_BASE ((uint32_t)0x20000000)
10044 #define APB1PERIPH_BASE ((uint32_t)0x40000000)
10045 #define APB2PERIPH_BASE ((uint32_t)0x40100000)
10046 #define AHBPERIPH_BASE ((uint32_t)0x50000000)
10047
10048
10050 #define WDT_BASE (APB1PERIPH_BASE + 0x04000)
10051
10052 #define RTC_BASE (APB1PERIPH_BASE + 0x08000)
10053 #define TIMER0_BASE (APB1PERIPH_BASE + 0x10000)
10054 #define TIMER1_BASE (APB1PERIPH_BASE + 0x10100)
10055 #define I2C0_BASE (APB1PERIPH_BASE + 0x20000)
10056 #define SPI0_BASE (APB1PERIPH_BASE + 0x30000)
10057 #define PWM0_BASE (APB1PERIPH_BASE + 0x40000)
10058 #define UART0_BASE (APB1PERIPH_BASE + 0x50000)
10059 #define SPI2_BASE (APB1PERIPH_BASE + 0xD0000)
10060 #define ADC_BASE (APB1PERIPH_BASE + 0xE0000)
10061
10062 #define TIMER2_BASE (APB2PERIPH_BASE + 0x10000)
10063 #define TIMER3_BASE (APB2PERIPH_BASE + 0x10100)
10064 #define I2C1_BASE (APB2PERIPH_BASE + 0x20000)
10065 #define SPI1_BASE (APB2PERIPH_BASE + 0x30000)
10066 #define PWM1_BASE (APB2PERIPH_BASE + 0x40000)
10067 #define UART1_BASE (APB2PERIPH_BASE + 0x50000)
10068 #define USBD_BASE (APB1PERIPH_BASE + 0x60000)
10069 #define SC0_BASE (APB2PERIPH_BASE + 0x90000)
10070 #define I2S_BASE (APB2PERIPH_BASE + 0xA0000)
10071 #define SC1_BASE (APB2PERIPH_BASE + 0xB0000)
10072
10073 #define SYS_BASE (AHBPERIPH_BASE + 0x00000)
10074 #define CLK_BASE (AHBPERIPH_BASE + 0x00200)
10075 #define GPIOA_BASE (AHBPERIPH_BASE + 0x04000)
10076 #define GPIOB_BASE (AHBPERIPH_BASE + 0x04040)
10077 #define GPIOC_BASE (AHBPERIPH_BASE + 0x04080)
10078 #define GPIOD_BASE (AHBPERIPH_BASE + 0x040C0)
10079 #define GPIOE_BASE (AHBPERIPH_BASE + 0x04100)
10080 #define GPIOF_BASE (AHBPERIPH_BASE + 0x04140)
10081 #define GPIODBNCE_BASE (AHBPERIPH_BASE + 0x04180)
10082 #define GPIO_PIN_DATA_BASE (AHBPERIPH_BASE + 0x04200)
10083 #define VDMA_BASE (AHBPERIPH_BASE + 0x08000)
10084 #define PDMA1_BASE (AHBPERIPH_BASE + 0x08100)
10085 #define PDMA2_BASE (AHBPERIPH_BASE + 0x08200)
10086 #define PDMA3_BASE (AHBPERIPH_BASE + 0x08300)
10087 #define PDMA4_BASE (AHBPERIPH_BASE + 0x08400)
10088 #define PDMAGCR_BASE (AHBPERIPH_BASE + 0x08F00)
10089 #define FMC_BASE (AHBPERIPH_BASE + 0x0C000)
10090 #define EBI_BASE (AHBPERIPH_BASE + 0x10000)
10091
10092 /* end of group NANO100_PERIPHERAL_MEM_MAP */
10093
10094
10099 #define WDT ((WDT_T *) WDT_BASE)
10100 #define RTC ((RTC_T *) RTC_BASE)
10101 #define TIMER0 ((TIMER_T *) TIMER0_BASE)
10102 #define TIMER1 ((TIMER_T *) TIMER1_BASE)
10103 #define TIMER2 ((TIMER_T *) TIMER2_BASE)
10104 #define TIMER3 ((TIMER_T *) TIMER3_BASE)
10105 #define I2C0 ((I2C_T *) I2C0_BASE)
10106 #define I2C1 ((I2C_T *) I2C1_BASE)
10107 #define SPI0 ((SPI_T *) SPI0_BASE)
10108 #define SPI1 ((SPI_T *) SPI1_BASE)
10109 #define SPI2 ((SPI_T *) SPI2_BASE)
10110 #define PWM0 ((PWM_T *) PWM0_BASE)
10111 #define PWM1 ((PWM_T *) PWM1_BASE)
10112 #define UART0 ((UART_T *) UART0_BASE)
10113 #define UART1 ((UART_T *) UART1_BASE)
10114 #define ADC ((ADC_T *) ADC_BASE)
10115 #define SC0 ((SC_T *) SC0_BASE)
10116 #define SC1 ((SC_T *) SC1_BASE)
10117 #define USBD ((USBD_T *) USBD_BASE)
10118 #define I2S ((I2S_T *) I2S_BASE)
10119
10120 #define SYS ((SYS_T *) SYS_BASE)
10121 #define CLK ((CLK_T *) CLK_BASE)
10122 #define PA ((GPIO_T *) GPIOA_BASE)
10123 #define PB ((GPIO_T *) GPIOB_BASE)
10124 #define PC ((GPIO_T *) GPIOC_BASE)
10125 #define PD ((GPIO_T *) GPIOD_BASE)
10126 #define PE ((GPIO_T *) GPIOE_BASE)
10127 #define PF ((GPIO_T *) GPIOF_BASE)
10128 #define GPIO ((GP_DB_T *) GPIODBNCE_BASE)
10129 #define VDMA ((VDMA_T *) VDMA_BASE)
10130 #define PDMA1 ((PDMA_T *) PDMA1_BASE)
10131 #define PDMA2 ((PDMA_T *) PDMA2_BASE)
10132 #define PDMA3 ((PDMA_T *) PDMA3_BASE)
10133 #define PDMA4 ((PDMA_T *) PDMA4_BASE)
10134 #define PDMAGCR ((DMA_GCR_T *) PDMAGCR_BASE)
10135 #define FMC ((FMC_T *) FMC_BASE)
10136 #define EBI ((EBI_T *) EBI_BASE)
10137
10138 /* end of group NANO100_PERIPHERAL_DECLARATION */
10139 /* end of group NANO100_Peripherals */
10141
10147 typedef volatile unsigned char vu8;
10148 typedef volatile unsigned short vu16;
10149 typedef volatile unsigned long vu32;
10150
10156 #define M8(addr) (*((vu8 *) (addr)))
10157
10164 #define M16(addr) (*((vu16 *) (addr)))
10165
10172 #define M32(addr) (*((vu32 *) (addr)))
10173
10181 #define outpw(port,value) *((volatile unsigned int *)(port)) = value
10182
10189 #define inpw(port) (*((volatile unsigned int *)(port)))
10190
10198 #define outps(port,value) *((volatile unsigned short *)(port)) = value
10199
10206 #define inps(port) (*((volatile unsigned short *)(port)))
10207
10214 #define outpb(port,value) *((volatile unsigned char *)(port)) = value
10215
10221 #define inpb(port) (*((volatile unsigned char *)(port)))
10222
10230 #define outp32(port,value) *((volatile unsigned int *)(port)) = value
10231
10238 #define inp32(port) (*((volatile unsigned int *)(port)))
10239
10247 #define outp16(port,value) *((volatile unsigned short *)(port)) = value
10248
10255 #define inp16(port) (*((volatile unsigned short *)(port)))
10256
10263 #define outp8(port,value) *((volatile unsigned char *)(port)) = value
10264
10270 #define inp8(port) (*((volatile unsigned char *)(port)))
10271 /* end of group NANO100_IO_ROUTINE */
10273
10274 /******************************************************************************/
10275 /* Legacy Constants */
10276 /******************************************************************************/
10282 #ifndef NULL
10283 #define NULL (0)
10284 #endif
10285
10286 #define TRUE (1)
10287 #define FALSE (0)
10288
10289 #define ENABLE (1)
10290 #define DISABLE (0)
10291
10292 /* Define one bit mask */
10293 #define BIT0 (0x00000001)
10294 #define BIT1 (0x00000002)
10295 #define BIT2 (0x00000004)
10296 #define BIT3 (0x00000008)
10297 #define BIT4 (0x00000010)
10298 #define BIT5 (0x00000020)
10299 #define BIT6 (0x00000040)
10300 #define BIT7 (0x00000080)
10301 #define BIT8 (0x00000100)
10302 #define BIT9 (0x00000200)
10303 #define BIT10 (0x00000400)
10304 #define BIT11 (0x00000800)
10305 #define BIT12 (0x00001000)
10306 #define BIT13 (0x00002000)
10307 #define BIT14 (0x00004000)
10308 #define BIT15 (0x00008000)
10309 #define BIT16 (0x00010000)
10310 #define BIT17 (0x00020000)
10311 #define BIT18 (0x00040000)
10312 #define BIT19 (0x00080000)
10313 #define BIT20 (0x00100000)
10314 #define BIT21 (0x00200000)
10315 #define BIT22 (0x00400000)
10316 #define BIT23 (0x00800000)
10317 #define BIT24 (0x01000000)
10318 #define BIT25 (0x02000000)
10319 #define BIT26 (0x04000000)
10320 #define BIT27 (0x08000000)
10321 #define BIT28 (0x10000000)
10322 #define BIT29 (0x20000000)
10323 #define BIT30 (0x40000000)
10324 #define BIT31 (0x80000000)
10325
10326 /* Byte Mask Definitions */
10327 #define BYTE0_Msk (0x000000FF)
10328 #define BYTE1_Msk (0x0000FF00)
10329 #define BYTE2_Msk (0x00FF0000)
10330 #define BYTE3_Msk (0xFF000000)
10331
10332 #define GET_BYTE0(u32Param) ((u32Param & BYTE0_Msk) )
10333 #define GET_BYTE1(u32Param) ((u32Param & BYTE1_Msk) >> 8)
10334 #define GET_BYTE2(u32Param) ((u32Param & BYTE2_Msk) >> 16)
10335 #define GET_BYTE3(u32Param) ((u32Param & BYTE3_Msk) >> 24)
10337 /* end of group NANO100_legacy_Constants */
10338 /* end of group NANO100_Definitions */
10340
10341 #ifdef __cplusplus
10342 }
10343 #endif
10344
10345
10346 /******************************************************************************/
10347 /* Peripheral header files */
10348 /******************************************************************************/
10349 #include "sys.h"
10350 #include "clk.h"
10351 #include "adc.h"
10352 #include "fmc.h"
10353 #include "ebi.h"
10354 #include "gpio.h"
10355 #include "i2c.h"
10356 #include "pdma.h"
10357 #include "pwm.h"
10358 #include "rtc.h"
10359 #include "sc.h"
10360 #include "spi.h"
10361 #include "timer.h"
10362 #include "uart.h"
10363 #include "usbd.h"
10364 #include "wdt.h"
10365 #include "i2s.h"
10366
10367 #endif // __NANO100SERIES_H__
10368
10369 /*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
10370
WDT_T::IER
__IO uint32_t IER
Definition: Nano100Series.h:9963
PDMA_T::DAR
__IO uint32_t DAR
Definition: Nano100Series.h:1470
SYS_T::IRCTRIMCTL
__IO uint32_t IRCTRIMCTL
Definition: Nano100Series.h:3234
RTC_T::TLR
__IO uint32_t TLR
Definition: Nano100Series.h:6574
RTC_T
Definition: Nano100Series.h:6492
rtc.h
Nano100 series RTC driver header file.
I2C0_IRQn
Definition: Nano100Series.h:107
UART_T::ALT_CTL
__IO uint32_t ALT_CTL
Definition: Nano100Series.h:9169
VDMA_T::DAR
__IO uint32_t DAR
Definition: Nano100Series.h:1673
uart.h
Nano100 Series uart control header file.
RTC_T::RIER
__IO uint32_t RIER
Definition: Nano100Series.h:6686
GPIO_T
Definition: Nano100Series.h:3754
PWM_T::CRL3
__I uint32_t CRL3
Definition: Nano100Series.h:5998
SYS_T::VREFCTL
__IO uint32_t VREFCTL
Definition: Nano100Series.h:3196
PDMA_T::CSR
__IO uint32_t CSR
Definition: Nano100Series.h:1444
UART_T::FUN_SEL
__IO uint32_t FUN_SEL
Definition: Nano100Series.h:9184
SVCall_IRQn
Definition: Nano100Series.h:84
pwm.h
NANO100 series PWM driver header file.
I2S_T::CTRL
__IO uint32_t CTRL
Definition: Nano100Series.h:4928
SC_T::ETUCR
__IO uint32_t ETUCR
Definition: Nano100Series.h:7248
CLK_T::CLKSEL2
__IO uint32_t CLKSEL2
Definition: Nano100Series.h:935
SC_T
Definition: Nano100Series.h:6996
PWM_T::DUTY1
__IO uint32_t DUTY1
Definition: Nano100Series.h:5564
GPDEF_IRQn
Definition: Nano100Series.h:94
ADC_IRQn
Definition: Nano100Series.h:115
PDWU_IRQn
Definition: Nano100Series.h:114
FMC_T::ISPCMD
__IO uint32_t ISPCMD
Definition: Nano100Series.h:2255
vu8
volatile unsigned char vu8
Define 8-bit unsigned volatile data type.
Definition: Nano100Series.h:10147
RTC_T::INIR
__IO uint32_t INIR
Definition: Nano100Series.h:6512
VDMA_T
Definition: Nano100Series.h:1616
RTC_T::CAR
__IO uint32_t CAR
Definition: Nano100Series.h:6654
SPI_T::SSR
__IO uint32_t SSR
Definition: Nano100Series.h:8086
FMC_T::ISPDAT
__IO uint32_t ISPDAT
Definition: Nano100Series.h:2234
RTC_T::RIIR
__IO uint32_t RIIR
Definition: Nano100Series.h:6714
GPIO_T::DMASK
__IO uint32_t DMASK
Definition: Nano100Series.h:3927
FMC_T::DFBADR
__I uint32_t DFBADR
Definition: Nano100Series.h:2283
PWM_T::CRL1
__I uint32_t CRL1
Definition: Nano100Series.h:5942
SC_T::TMR1
__IO uint32_t TMR1
Definition: Nano100Series.h:7531
SC_T::ALTCTL
__IO uint32_t ALTCTL
Definition: Nano100Series.h:7200
CLK_T::CLKDIV1
__IO uint32_t CLKDIV1
Definition: Nano100Series.h:969
SYS_T::PD_H_MFP
__IO uint32_t PD_H_MFP
Definition: Nano100Series.h:2955
gpio.h
Nano100 series GPIO driver header file.
SYS_T::IRCTRIMIEN
__IO uint32_t IRCTRIMIEN
Definition: Nano100Series.h:3254
GPIO_T::DBEN
__IO uint32_t DBEN
Definition: Nano100Series.h:3959
PWM_T::INTEN
__IO uint32_t INTEN
Definition: Nano100Series.h:5415
CLK_T::APBCLK
__IO uint32_t APBCLK
Definition: Nano100Series.h:786
I2C_T
Definition: Nano100Series.h:4554
UART_T::FSR
__IO uint32_t FSR
Definition: Nano100Series.h:9026
PDMA_T::ISR
__IO uint32_t ISR
Definition: Nano100Series.h:1581
TIMER_T::DR
__I uint32_t DR
Definition: Nano100Series.h:8586
IRQn_Type
enum IRQn IRQn_Type
UART_T::TRSR
__IO uint32_t TRSR
Definition: Nano100Series.h:8975
PWM_T::CAPINTSTS
__IO uint32_t CAPINTSTS
Definition: Nano100Series.h:5900
USBD_EP_T
USBD endpoints register.
Definition: Nano100Series.h:9446
PWM_T::CRL2
__I uint32_t CRL2
Definition: Nano100Series.h:5970
UART_T::IER
__IO uint32_t IER
Definition: Nano100Series.h:8875
SC_T::TRSR
__IO uint32_t TRSR
Definition: Nano100Series.h:7436
PWM_T::CFL2
__I uint32_t CFL2
Definition: Nano100Series.h:5984
DMA_GCR_T::DSSR0
__IO uint32_t DSSR0
Definition: Nano100Series.h:1343
VDMA_T::DASOCR
__IO uint32_t DASOCR
Definition: Nano100Series.h:1796
sys.h
Nano100 Series system control header file.
VDMA_T::BUF0
__I uint32_t BUF0
Definition: Nano100Series.h:1813
PWM_T::DUTY3
__IO uint32_t DUTY3
Definition: Nano100Series.h:5668
VDMA_T::SASOCR
__IO uint32_t SASOCR
Definition: Nano100Series.h:1784
DMA_GCR_T
Definition: Nano100Series.h:1270
I2S_T::STATUS
__IO uint32_t STATUS
Definition: Nano100Series.h:5090
CLK_T
Definition: Nano100Series.h:608
SPI_T::STATUS
__IO uint32_t STATUS
Definition: Nano100Series.h:8020
FMC_T::ISPADR
__IO uint32_t ISPADR
Definition: Nano100Series.h:2221
USBD_T::PDMA
__IO uint32_t PDMA
Definition: Nano100Series.h:9751
PWM_T::OE
__IO uint32_t OE
Definition: Nano100Series.h:5479
VDMA_T::CDAR
__I uint32_t CDAR
Definition: Nano100Series.h:1715
UART_T::RBR
__I uint32_t RBR
Definition: Nano100Series.h:8722
USBD_EP_T::CFG
__IO uint32_t CFG
Definition: Nano100Series.h:9517
PDMA_IRQn
Definition: Nano100Series.h:112
VDMA_T::BCR
__IO uint32_t BCR
Definition: Nano100Series.h:1686
PWM_T::PRES
__IO uint32_t PRES
Definition: Nano100Series.h:5309
GPIO_T::OFFD
__IO uint32_t OFFD
Definition: Nano100Series.h:3893
RTC_T::FCR
__IO uint32_t FCR
Definition: Nano100Series.h:6558
PWM_T::DATA3
__I uint32_t DATA3
Definition: Nano100Series.h:5687
I2C_T::STATUS
__I uint32_t STATUS
Definition: Nano100Series.h:4631
UART_T::ISR
__IO uint32_t ISR
Definition: Nano100Series.h:8923
SYS_T::RST_SRC
__IO uint32_t RST_SRC
Definition: Nano100Series.h:2445
pdma.h
Nano100 series PDMA driver header file.
PDMA_T
Definition: Nano100Series.h:1388
SC_T::EGTR
__IO uint32_t EGTR
Definition: Nano100Series.h:7213
GPABC_IRQn
Definition: Nano100Series.h:93
sc.h
Nano100 series Smartcard (SC) driver header file.
SYS_T::PDID
__I uint32_t PDID
Definition: Nano100Series.h:2405
timer.h
Nano100 series TIMER driver header file.
UART_T::TMCTL
__IO uint32_t TMCTL
Definition: Nano100Series.h:9075
adc.h
NANO100 series ADC driver header file.
DMA_GCR_T::GCRCSR
__IO uint32_t GCRCSR
Definition: Nano100Series.h:1297
TIMER_T::IER
__IO uint32_t IER
Definition: Nano100Series.h:8543
USBD_T::BUSSTS
__I uint32_t BUSSTS
Definition: Nano100Series.h:9584
SPI_T
Definition: Nano100Series.h:7871
PWM_T::CFL1
__I uint32_t CFL1
Definition: Nano100Series.h:5956
I2S_T::TXFIFO
__O uint32_t TXFIFO
Definition: Nano100Series.h:5105
PWM_T::DUTY2
__IO uint32_t DUTY2
Definition: Nano100Series.h:5616
SPI0_IRQn
Definition: Nano100Series.h:103
wdt.h
Nano100 series WDT driver header file.
SYS_T::BODSTS
__IO uint32_t BODSTS
Definition: Nano100Series.h:3159
WDT_IRQn
Definition: Nano100Series.h:90
PWM_T::CFL3
__I uint32_t CFL3
Definition: Nano100Series.h:6012
GPIO_T::ISRC
__IO uint32_t ISRC
Definition: Nano100Series.h:4296
TMR2_IRQn
Definition: Nano100Series.h:99
spi.h
NANO100 series SPI driver header file.
PDMA_T::IER
__IO uint32_t IER
Definition: Nano100Series.h:1548
UART_T::CTL
__IO uint32_t CTL
Definition: Nano100Series.h:8794
SPI_T::TX0
__O uint32_t TX0
Definition: Nano100Series.h:8139
VDMA_T::CBCR
__I uint32_t CBCR
Definition: Nano100Series.h:1727
TIMER_T::ISR
__IO uint32_t ISR
Definition: Nano100Series.h:8574
SYS_T
Definition: Nano100Series.h:2390
PWM_T::PDMACH0
__I uint32_t PDMACH0
Definition: Nano100Series.h:6034
EBI_T
Definition: Nano100Series.h:2033
I2S_T::INTEN
__IO uint32_t INTEN
Definition: Nano100Series.h:4989
DMA_GCR_T::GCRISR
__I uint32_t GCRISR
Definition: Nano100Series.h:1383
vu32
volatile unsigned long vu32
Define 32-bit unsigned volatile data type.
Definition: Nano100Series.h:10149
SysTick_IRQn
Definition: Nano100Series.h:86
SC_T::ISR
__IO uint32_t ISR
Definition: Nano100Series.h:7361
EINT1_IRQn
Definition: Nano100Series.h:92
BOD_IRQn
Definition: Nano100Series.h:89
WDT_T::CTL
__IO uint32_t CTL
Definition: Nano100Series.h:9950
PendSV_IRQn
Definition: Nano100Series.h:85
I2C1_IRQn
Definition: Nano100Series.h:108
RTC_T::CLR
__IO uint32_t CLR
Definition: Nano100Series.h:6590
RTC_T::TAR
__IO uint32_t TAR
Definition: Nano100Series.h:6638
SPI2_IRQn
Definition: Nano100Series.h:105
CLK_T::CLKSTATUS
__I uint32_t CLKSTATUS
Definition: Nano100Series.h:815
I2C_T::INTSTS
__IO uint32_t INTSTS
Definition: Nano100Series.h:4609
WDT_T
Definition: Nano100Series.h:9914
ADC_T::CR
__IO uint32_t CR
Definition: Nano100Series.h:245
PWM_T::CFL0
__I uint32_t CFL0
Definition: Nano100Series.h:5928
FMC_T::ISPCON
__IO uint32_t ISPCON
Definition: Nano100Series.h:2209
GPIO_T::IMD
__IO uint32_t IMD
Definition: Nano100Series.h:3980
PDMA_T::CBCR
__I uint32_t CBCR
Definition: Nano100Series.h:1525
RTC_T::DWR
__IO uint32_t DWR
Definition: Nano100Series.h:6622
PWM_T::CRL0
__I uint32_t CRL0
Definition: Nano100Series.h:5914
RTC_T::SPRCTL
__IO uint32_t SPRCTL
Definition: Nano100Series.h:6772
ADC_T::DELSEL
__IO uint32_t DELSEL
Definition: Nano100Series.h:454
vu16
volatile unsigned short vu16
Define 16-bit unsigned volatile data type.
Definition: Nano100Series.h:10148
fmc.h
Nano100 Series Flash Memory Controller Driver Header File.
I2C_T::SAMASK1
__IO uint32_t SAMASK1
Definition: Nano100Series.h:4762
PDMA_T::BUF
__I uint32_t BUF
Definition: Nano100Series.h:1611
SPI_T::CTL
__IO uint32_t CTL
Definition: Nano100Series.h:7984
TMR3_IRQn
Definition: Nano100Series.h:100
SYS_T::PE_L_MFP
__IO uint32_t PE_L_MFP
Definition: Nano100Series.h:2989
DMA_GCR_T::DSSR1
__IO uint32_t DSSR1
Definition: Nano100Series.h:1358
PDMA_T::CDAR
__I uint32_t CDAR
Definition: Nano100Series.h:1512
UART_T::MCSR
__IO uint32_t MCSR
Definition: Nano100Series.h:9052
USBD_T::CTL
__IO uint32_t CTL
Definition: Nano100Series.h:9559
SPI_T::RX0
__I uint32_t RX0
Definition: Nano100Series.h:8102
FMC_T::ISPTRG
__IO uint32_t ISPTRG
Definition: Nano100Series.h:2269
USBD_T::INTEN
__IO uint32_t INTEN
Definition: Nano100Series.h:9606
SYS_T::PE_H_MFP
__IO uint32_t PE_H_MFP
Definition: Nano100Series.h:3019
EINT0_IRQn
Definition: Nano100Series.h:91
I2C_T::SADDR0
__IO uint32_t SADDR0
Definition: Nano100Series.h:4704
clk.h
Nano100 series CLK driver header file.
GPIO_T::PMD
__IO uint32_t PMD
Definition: Nano100Series.h:3878
I2S_T
Definition: Nano100Series.h:4838
RTC_T::TSSR
__IO uint32_t TSSR
Definition: Nano100Series.h:6604
SC_T::TDRA
__I uint32_t TDRA
Definition: Nano100Series.h:7562
ADC_T::CMPR1
__IO uint32_t CMPR1
Definition: Nano100Series.h:371
TMR0_IRQn
Definition: Nano100Series.h:97
IRQn
IRQn
Definition: Nano100Series.h:78
i2s.h
Nano100 series I2S driver header file.
USBD_EP_T::MXPLD
__IO uint32_t MXPLD
Definition: Nano100Series.h:9480
VDMA_T::CSAR
__I uint32_t CSAR
Definition: Nano100Series.h:1703
USBD_IRQn
Definition: Nano100Series.h:111
SYS_T::PC_L_MFP
__IO uint32_t PC_L_MFP
Definition: Nano100Series.h:2834
GPIO_T::DOUT
__IO uint32_t DOUT
Definition: Nano100Series.h:3908
UART_T::TLCTL
__IO uint32_t TLCTL
Definition: Nano100Series.h:8838
EBI_T::EBICON
__IO uint32_t EBICON
Definition: Nano100Series.h:2073
PWM_T::DATA0
__I uint32_t DATA0
Definition: Nano100Series.h:5531
RTC_T::LIR
__I uint32_t LIR
Definition: Nano100Series.h:6667
RTC_T::TTR
__IO uint32_t TTR
Definition: Nano100Series.h:6740
SYS_T::IPRST_CTL2
__IO uint32_t IPRST_CTL2
Definition: Nano100Series.h:2550
HIRC_IRQn
Definition: Nano100Series.h:106
system_Nano100Series.h
Nano100 series system clock definition file.
I2C_T::DIV
__IO uint32_t DIV
Definition: Nano100Series.h:4644
SC_T::TMR0
__IO uint32_t TMR0
Definition: Nano100Series.h:7517
SYS_T::BODCTL
__IO uint32_t BODCTL
Definition: Nano100Series.h:3127
RTC_IRQn
Definition: Nano100Series.h:116
FMC_T::ISPSTA
__IO uint32_t ISPSTA
Definition: Nano100Series.h:2314
SC_T::TDRB
__I uint32_t TDRB
Definition: Nano100Series.h:7576
SYS_T::PF_L_MFP
__IO uint32_t PF_L_MFP
Definition: Nano100Series.h:3050
ADC_T
Definition: Nano100Series.h:159
HardFault_IRQn
Definition: Nano100Series.h:83
SPI_T::PDMA
__IO uint32_t PDMA
Definition: Nano100Series.h:8205
SC1_IRQn
Definition: Nano100Series.h:110
SC0_IRQn
Definition: Nano100Series.h:109
SC_T::RBR
__I uint32_t RBR
Definition: Nano100Series.h:7012
UART1_IRQn
Definition: Nano100Series.h:102
EBI_T::EXTIME
__IO uint32_t EXTIME
Definition: Nano100Series.h:2098
SYS_T::PB_L_MFP
__IO uint32_t PB_L_MFP
Definition: Nano100Series.h:2740
CLK_T::WK_IS
__IO uint32_t WK_IS
Definition: Nano100Series.h:1029
PWM1_IRQn
Definition: Nano100Series.h:96
I2S_IRQn
Definition: Nano100Series.h:113
SYS_T::PB_H_MFP
__IO uint32_t PB_H_MFP
Definition: Nano100Series.h:2785
SYS_T::IRCTRIMINT
__IO uint32_t IRCTRIMINT
Definition: Nano100Series.h:3281
ADC_T::SR
__IO uint32_t SR
Definition: Nano100Series.h:414
SC_T::TMR2
__IO uint32_t TMR2
Definition: Nano100Series.h:7545
SYS_T::PA_L_MFP
__IO uint32_t PA_L_MFP
Definition: Nano100Series.h:2637
I2S_T::RXFIFO
__I uint32_t RXFIFO
Definition: Nano100Series.h:5120
SPI_T::RX1
__I uint32_t RX1
Definition: Nano100Series.h:8118
VDMA_T::CSR
__IO uint32_t CSR
Definition: Nano100Series.h:1649
TIMER_T::TCAP
__I uint32_t TCAP
Definition: Nano100Series.h:8599
FMC_T
Definition: Nano100Series.h:2147
SYS_T::PD_L_MFP
__IO uint32_t PD_L_MFP
Definition: Nano100Series.h:2929
USBD_T
Definition: Nano100Series.h:9524
CLK_T::CLKSEL0
__IO uint32_t CLKSEL0
Definition: Nano100Series.h:837
PDMA_T::CSAR
__I uint32_t CSAR
Definition: Nano100Series.h:1500
PDMA_T::BCR
__IO uint32_t BCR
Definition: Nano100Series.h:1483
TIMER_T::CMPR
__IO uint32_t CMPR
Definition: Nano100Series.h:8525
PDMA_T::TCR
__IO uint32_t TCR
Definition: Nano100Series.h:1594
PWM_T::CAPCTL
__IO uint32_t CAPCTL
Definition: Nano100Series.h:5796
SC_T::RFTMR
__IO uint32_t RFTMR
Definition: Nano100Series.h:7228
SPI_T::FFCLR
__IO uint32_t FFCLR
Definition: Nano100Series.h:8223
VDMA_T::SAR
__IO uint32_t SAR
Definition: Nano100Series.h:1661
SPI1_IRQn
Definition: Nano100Series.h:104
SYS_T::PA_H_MFP
__IO uint32_t PA_H_MFP
Definition: Nano100Series.h:2693
PWM_T::PDMACH2
__I uint32_t PDMACH2
Definition: Nano100Series.h:6056
TIMER_T
Definition: Nano100Series.h:8365
I2S_T::CLKDIV
__IO uint32_t CLKDIV
Definition: Nano100Series.h:4947
PWM_T::DATA2
__I uint32_t DATA2
Definition: Nano100Series.h:5635
SYS_T::IPRST_CTL1
__IO uint32_t IPRST_CTL1
Definition: Nano100Series.h:2483
SYS_T::PC_H_MFP
__IO uint32_t PC_H_MFP
Definition: Nano100Series.h:2884
I2C_T::DATA
__IO uint32_t DATA
Definition: Nano100Series.h:4683
I2C_T::TOUT
__IO uint32_t TOUT
Definition: Nano100Series.h:4663
TIMER_T::PRECNT
__IO uint32_t PRECNT
Definition: Nano100Series.h:8508
VDMA_T::ISR
__IO uint32_t ISR
Definition: Nano100Series.h:1765
RTC_T::AER
__IO uint32_t AER
Definition: Nano100Series.h:6528
ebi.h
Nano100 Series Flash Memory Controller Driver Header File.
CLK_T::CLKSEL1
__IO uint32_t CLKSEL1
Definition: Nano100Series.h:883
SYS_T::RegLockAddr
__IO uint32_t RegLockAddr
Definition: Nano100Series.h:3299
GPIO_T::IER
__IO uint32_t IER
Definition: Nano100Series.h:4278
SYS_T::CPR
__IO uint32_t CPR
Definition: Nano100Series.h:2565
PWM_T::DATA1
__I uint32_t DATA1
Definition: Nano100Series.h:5583
UART0_IRQn
Definition: Nano100Series.h:101
PWM_T::CTL
__IO uint32_t CTL
Definition: Nano100Series.h:5393
PWM_T::CLKSEL
__IO uint32_t CLKSEL
Definition: Nano100Series.h:5335
PDMA_T::SAR
__IO uint32_t SAR
Definition: Nano100Series.h:1457
SC_T::THR
__O uint32_t THR
Definition: Nano100Series.h:7023
GPIO_T::PUEN
__IO uint32_t PUEN
Definition: Nano100Series.h:4310
GP_DB_T::DBNCECON
__IO uint32_t DBNCECON
Definition: Nano100Series.h:4352
SPI_T::VARCLK
__IO uint32_t VARCLK
Definition: Nano100Series.h:8175
PWM_T::DUTY0
__IO uint32_t DUTY0
Definition: Nano100Series.h:5512
UART_T
Definition: Nano100Series.h:8705
UART_T::IRCR
__IO uint32_t IRCR
Definition: Nano100Series.h:9116
USBD_EP_T::BUFSEG
__IO uint32_t BUFSEG
Definition: Nano100Series.h:9460
ADC_T::PDMA
__I uint32_t PDMA
Definition: Nano100Series.h:431
SPI_T::CLKDIV
__IO uint32_t CLKDIV
Definition: Nano100Series.h:8039
CLK_T::PLLCTL
__IO uint32_t PLLCTL
Definition: Nano100Series.h:993
I2C_T::SAMASK0
__IO uint32_t SAMASK0
Definition: Nano100Series.h:4746
CLK_T::AHBCLK
__IO uint32_t AHBCLK
Definition: Nano100Series.h:704
GP_DB_T
Definition: Nano100Series.h:4315
SC_T::PINCSR
__IO uint32_t PINCSR
Definition: Nano100Series.h:7503
CLK_T::PWRCTL
__IO uint32_t PWRCTL
Definition: Nano100Series.h:676
USBD_T::EPSTS
__I uint32_t EPSTS
Definition: Nano100Series.h:9702
SC_T::CTL
__IO uint32_t CTL
Definition: Nano100Series.h:7110
CLK_T::CLKDIV0
__IO uint32_t CLKDIV0
Definition: Nano100Series.h:957
UART_T::THR
__O uint32_t THR
Definition: Nano100Series.h:8735
TMR1_IRQn
Definition: Nano100Series.h:98
USBD_T::INTSTS
__IO uint32_t INTSTS
Definition: Nano100Series.h:9653
CLK_T::FRQDIV
__IO uint32_t FRQDIV
Definition: Nano100Series.h:1010
TIMER_T::CTL
__IO uint32_t CTL
Definition: Nano100Series.h:8495
I2C_T::SADDR1
__IO uint32_t SADDR1
Definition: Nano100Series.h:4725
PWM_T::CAPINTEN
__IO uint32_t CAPINTEN
Definition: Nano100Series.h:5838
SC_T::IER
__IO uint32_t IER
Definition: Nano100Series.h:7309
ADC_T::CMPR0
__IO uint32_t CMPR0
Definition: Nano100Series.h:330
NonMaskableInt_IRQn
Definition: Nano100Series.h:82
PWM_T::INTSTS
__IO uint32_t INTSTS
Definition: Nano100Series.h:5453
SPI_T::TX1
__O uint32_t TX1
Definition: Nano100Series.h:8155
ADC_T::CHEN
__IO uint32_t CHEN
Definition: Nano100Series.h:289
WDT_T::ISR
__IO uint32_t ISR
Definition: Nano100Series.h:9994
VDMA_T::IER
__IO uint32_t IER
Definition: Nano100Series.h:1743
SYS_T::TEMPCTL
__IO uint32_t TEMPCTL
Definition: Nano100Series.h:2583
PWM0_IRQn
Definition: Nano100Series.h:95
USBD_T::BUFSEG
__IO uint32_t BUFSEG
Definition: Nano100Series.h:9715
USBD_T::FADDR
__IO uint32_t FADDR
Definition: Nano100Series.h:9665
SYS_T::PORCTL
__IO uint32_t PORCTL
Definition: Nano100Series.h:3069
GPIO_T::PIN
__I uint32_t PIN
Definition: Nano100Series.h:3940
UART_T::BAUD
__IO uint32_t BAUD
Definition: Nano100Series.h:9091
VDMA_T::BUF1
__I uint32_t BUF1
Definition: Nano100Series.h:1825
usbd.h
NANO100 series USB driver header file.
I2C_T::CON
__IO uint32_t CON
Definition: Nano100Series.h:4593
i2c.h
Nano100 series I2C driver header file.
PWM_T
Definition: Nano100Series.h:5283