| Nano100AN Series BSP V3.02.002 The Board Support Package for Nano100AN Series

Data Fields
PDMA_T Struct Reference

`#include <Nano100Series.h>`

## Data Fields
__IO uint32_t | CSR
__IO uint32_t | SAR
__IO uint32_t | DAR
__IO uint32_t | BCR
__I uint32_t | CSAR
__I uint32_t | CDAR
__I uint32_t | CBCR
__IO uint32_t | IER
__IO uint32_t | ISR
__IO uint32_t | TCR
__I uint32_t | BUF

## Detailed Description

Definition at line 1388 of file Nano100Series.h.

## Field Documentation

## ◆ BCR

__IO uint32_t PDMA_T::BCR

# BCR

## Offset: 0x0C PDMA Transfer Byte Count Register

Bits | Field | Descriptions
--- | --- | ---
[15:0] | PDMA_BCR | PDMA Transfer Byte Count Register
|  | This field indicates a 16-bit transfer byte count of PDMA.
|  | Note: In Memory-to-memory (PDMA_CSR [MODE_SEL] = 00) mode, the transfer byte count must be word alignment.

Definition at line 1483 of file Nano100Series.h.

## ◆ BUF

__I uint32_t PDMA_T::BUF

# BUF

## Offset: 0x80 PDMA Internal Buffer FIFO

Bits | Field | Descriptions
--- | --- | ---
[31:0] | PDMA_BUF | PDMA Internal Buffer FIFO (Read Only)
|  | Each channel has its own 1 words internal buffer.

Definition at line 1611 of file Nano100Series.h.

## ◆ CBCR

__I uint32_t PDMA_T::CBCR

# CBCR

## Offset: 0x1C PDMA Current Transfer Byte Count Register

Bits | Field | Descriptions
--- | --- | ---
[23:0] | PDMA_CBCR | PDMA Current Byte Count Register (Read Only)
|  | This field indicates the current remained byte count of PDMA.
|  | Note: These fields will be changed when PDMA finish data transfer (data transfer to destination address),

Definition at line 1525 of file Nano100Series.h.

## ◆ CDAR

__I uint32_t PDMA_T::CDAR

# CDAR

## Offset: 0x18 PDMA Current Destination Address Register

Bits | Field | Descriptions
--- | --- | ---
[31:0] | PDMA_CDAR | PDMA Current Destination Address Register (Read Only)
|  | This field indicates the destination address where the PDMA transfer is just occurring.

Definition at line 1512 of file Nano100Series.h.

## ◆ CSAR

__I uint32_t PDMA_T::CSAR

# CSAR

## Offset: 0x14 PDMA Current Source Address Register

Bits | Field | Descriptions
--- | --- | ---
[31:0] | PDMA_CSAR | PDMA Current Source Address Register (Read Only)
|  | This field indicates the source address where the PDMA transfer is just occurring.

Definition at line 1500 of file Nano100Series.h.

## ◆ CSR

__IO uint32_t PDMA_T::CSR

# CSR

## Offset: 0x00 PDMA Control Register

Bits | Field | Descriptions
--- | --- | ---
[0] | PDMACEN | PDMA Channel Enable
|  | Setting this bit to "1" enables PDMA's operation.
|  | If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state.
|  | Note: SW_RST will clear this bit.
[1] | SW_RST | Software Engine Reset
|  | 0 = No effect.
|  | 1 = Reset the internal state machine and pointers.
|  | The contents of control register will not be cleared.
|  | This bit will auto clear after few clock cycles.
[3:2] | MODE_SEL | PDMA Mode Select
|  | 00 = Memory to Memory mode (Memory-to-Memory).
|  | 01 = IP to Memory mode (APB-to-Memory).
|  | 10 = Memory to IP mode (Memory-to-APB).
|  | 11 = Reserved.
[5:4] | SAD_SEL | Transfer Source Address Direction Selection
|  | 00 = Transfer Source address is incremented successively.
|  | 01 = Reserved.
|  | 10 = Transfer Source address is fixed (This feature can be used when data where transferred from a single source to multiple destinations).
|  | 11 = Transfer Source address is wrap around (When the PDMA_CBCR equal zero, the PDMA_CSAR and PDMA_CBCR register will updated by PDMA_SAR and PDMA_BCR automatically.
|  | PDMA will start another transfer which without software trigger until PDMA_EN disable.
|  | When the PDMA_EN disable, the PDMA will complete the active transfer but the remained data which in the PDMA_BUF will not transfer to destination address).
[7:6] | DAD_SEL | Transfer Destination Address Direction Selection
|  | 00 = Transfer Destination address is incremented successively.
|  | 01 = Reserved.
|  | 10 = Transfer Destination address is fixed (This feature can be used when data where transferred from multiple sources to a single destination).
|  | 11 = Transfer Destination address is wrap around (When the PDMA_CBCR equal zero, the PDMA_CDAR and PDMA_CBCR register will updated by PDMA_DAR and PDMA_BCR automatically.
|  | PDMA will start another transfer which without software trigger until PDMA_EN disable.
|  | When the PDMA_EN disable, the PDMA will complete the active transfer but the remained data which in the PDMA_BUF will not transfer to destination address).
[12] | TO_EN | Time-Out Enable
|  | This bit will enable PDMA internal Timer. While Timer is counted to zero, the TO_IS will be set.
|  | 0 = PDMA internal Timer Disabled.
|  | 1 = PDMA internal Timer Enabled.
[20:19] | APB_TWS | Peripheral Transfer Width Selection
|  | 00 = One word (32 bits) is transferred for every PDMA operation.
|  | 01 = One byte (8 bits) is transferred for every PDMA operation.
|  | 10 = One half-word (16 bits) is transferred for every PDMA operation.
|  | 11 = Reserved.
|  | Note: This field is meaningful only when MODE_SEL is IP to Memory mode (APB-to-Memory) or Memory to IP mode (Memory-to-APB).
[23] | TRIG_EN | TRIG_EN
|  | 0 = No effect.
|  | 1 = PDMA data read or write transfer Enabled.
|  | Note1: When PDMA transfer completed, this bit will be cleared automatically.
|  | Note2: If the bus error occurs, all PDMA transfer will be stopped.
|  | Software must reset all PDMA channel, and then trig again.

Definition at line 1444 of file Nano100Series.h.

## ◆ DAR

__IO uint32_t PDMA_T::DAR

# DAR

## Offset: 0x08 PDMA Destination Address Register

Bits | Field | Descriptions
--- | --- | ---
[31:0] | PDMA_DAR | PDMA Transfer Destination Address Register
|  | This field indicates a 32-bit destination address of PDMA.
|  | Note : The destination address must be word alignment

Definition at line 1470 of file Nano100Series.h.

## ◆ IER

__IO uint32_t PDMA_T::IER

# IER

## Offset: 0x20 PDMA Interrupt Enable Register

Bits | Field | Descriptions
--- | --- | ---
[0] | TABORT_IE | PDMA Read/Write Target Abort Interrupt Enable
|  | 0 = Disabled target abort interrupt generation during PDMA transfer.
|  | 1 = Enabled target abort interrupt generation during PDMA transfer.
[1] | TD_IE | PDMA Transfer Done Interrupt Enable
|  | 0 = Disabled interrupt generator when PDMA transfer is done.
|  | 1 = Enabled interrupt generator when PDMA transfer is done.
[5:2] | WRA_BCR_IE | Wrap Around Byte Count Interrupt Enable
|  | 0001 = Interrupt enable of PDMA_CBCR equal 0.
|  | 0100 = Interrupt enable of PDMA_CBCR equal 1/2 PDMA_BCR.
|  | Others = Reserved.
[6] | TO_IE | Time-Out Interrupt Enable
|  | 0 = Time-out interrupt Disabled.
|  | 1 = Time-out interrupt Enabled.

Definition at line 1548 of file Nano100Series.h.

## ◆ ISR

__IO uint32_t PDMA_T::ISR

# ISR

## Offset: 0x24 PDMA Interrupt Status Register

Bits | Field | Descriptions
--- | --- | ---
[0] | TABORT_IS | PDMA Read/Write Target Abort Interrupt Status Flag
|  | 0 = No bus ERROR response received.
|  | 1 = Bus ERROR response received.
|  | NOTE1: This bit is cleared by writing "1" to itself.
|  | NOTE2: The PDMA_ISR [TABORT_IF] indicate bus master received ERROR response or not, if bus master received occur it means that target abort is happened.
|  | PDMA controller will stop transfer and respond this event to software then go to IDLE state.
|  | When target abort occurred, software must reset PDMA controller, and then transfer those data again.
[1] | TD_IS | Transfer Done Interrupt Status Flag
|  | This bit indicates that PDMA has finished all transfer.
|  | 0 = Not finished yet.
|  | 1 = Done.
|  | NOTE: This bit is cleared by writing "1" to itself.
[5:2] | WRA_BCR_IS | Wrap Around Transfer Byte Count Interrupt Status Flag
|  | WAR_BCR_IS [0] (xxx1) = PDMA_CBCR equal 0 flag.
|  | WAR_BCR_IS [2] (x1xx) = PDMA_CBCR equal 1/2 PDMA_BCR flag.
|  | NOTE: Each bit is cleared by writing "1" to itself.
|  | This field is only valid in wrap around mode.
|  | (PDMA_CSR[DAD_SEL] =11 or PDMA_CSR[SAD_SEL] =11).
[6] | TO_IS | Time-Out Interrupt Status Flag
|  | This flag indicated that PDMA has waited peripheral request for a period defined by PDMA_TCR.
|  | 0 = No time-out flag.
|  | 1 = Time-out flag.
|  | NOTE: This bit is cleared by writing "1" to itself.

Definition at line 1581 of file Nano100Series.h.

## ◆ SAR

__IO uint32_t PDMA_T::SAR

# SAR

## Offset: 0x04 PDMA Source Address Register

Bits | Field | Descriptions
--- | --- | ---
[31:0] | PDMA_SAR | PDMA Transfer Source Address Register
|  | This field indicates a 32-bit source address of PDMA.
|  | Note: The source address must be word alignment.

Definition at line 1457 of file Nano100Series.h.

## ◆ TCR

__IO uint32_t PDMA_T::TCR

# TCR

## Offset: 0x28 PDMA Timer Counter Setting Register

Bits | Field | Descriptions
--- | --- | ---
[15:0] | PDMA_TCR | PDMA Timer Count Setting Register
|  | Each PDMA controller contains an internal counter.
|  | The internal counter starts counting when setting PDMA_CSRx [TO_EN] register, clearing and restart counting when complete each peripheral request service.

Definition at line 1594 of file Nano100Series.h.

The documentation for this struct was generated from the following file:

- C:/Users/yachen/workzone/bsp/nano100absp/Library/Device/Nuvoton/Nano100Series/Include/Nano100Series.h