| Nano100AN Series BSP V3.02.002 The Board Support Package for Nano100AN Series

Data Fields
ADC_T Struct Reference
NANO100 Definitions » NANO100 Peripherals

`#include <Nano100Series.h>`

## Data Fields
__I uint32_t | RESULT [11]
__IO uint32_t | CR
__IO uint32_t | CHEN
__IO uint32_t | CMPR0
__IO uint32_t | CMPR1
__IO uint32_t | SR
__I uint32_t | PDMA
__IO uint32_t | DELSEL

## Detailed Description

    @addtogroup ADC Analog to Digital Converter(ADC)
    Memory Mapped Structure for ADC Controller

Definition at line 159 of file Nano100Series.h.

## Field Documentation

## ◆ CHEN

__IO uint32_t ADC_T::CHEN

# CHEN

## Offset: 0x34 A/D Channel Enable Register

Bits | Field | Descriptions
--- | --- | ---
[0] | CHEN0 | Analog Input Channel 0 Enable
|  | 0 = Disabled.
|  | 1 = Enabled.
|  | This channel is enabled if CHEN1~7 are set as 0s.
|  | If software enables more than one channel in single mode, the least channel is converted and other enabled channels will be ignored.
[1] | CHEN1 | Analog Input Channel 1 Enable
|  | 0 = Disabled.
|  | 1 = Enabled.
[2] | CHEN2 | Analog Input Channel 2 Enable
|  | 0 = Disabled.
|  | 1 = Enabled.
[3] | CHEN3 | Analog Input Channel 3 Enable
|  | 0 = Disabled.
|  | 1 = Enabled.
[4] | CHEN4 | Analog Input Channel 4 Enable
|  | 0 = Disabled.
|  | 1 = Enabled.
[5] | CHEN5 | Analog Input Channel 5 Enable
|  | 0 = Disabled.
|  | 1 = Enabled.
[6] | CHEN6 | Analog Input Channel 6 Enable
|  | 0 = Disabled.
|  | 1 = Enabled.
[7] | CHEN7 | Analog Input Channel 7 Enable
|  | 0 = Disabled.
|  | 1 = Enabled.
[10] | CHEN10 | Analog Input Channel 10 Enable
|  | 0 = Disabled.
|  | 1 = Enabled.
[12:11] | CH10SEL | Select The VTEMP,VBG,AVDD,AVSS, As Channel 10 Input
|  | 00 = VTEMP.
|  | 01 = VBG.
|  | 10 = AVDD.
|  | 11 = AVSS.

Definition at line 289 of file Nano100Series.h.

## ◆ CMPR0

__IO uint32_t ADC_T::CMPR0

# CMPR0

## Offset: 0x38 A/D Compare Register 0

Bits | Field | Descriptions
--- | --- | ---
[0] | CMPEN | Compare Enable
|  | 0 = Compare Disabled.
|  | 1 = Compare Enabled.
|  | Set this bit to 1 to enable compare CMPD[11:0] with specified channel conversion result when converted data is loaded into ADC_RESULTx register.
|  | When this bit is set to 1, and CMPMATCNT is 0, the CMPF will be set once the match is hit
[1] | CMPIE | Compare Interrupt Enable
|  | 0 = Compare function interrupt Disabled.
|  | 1 = Compare function interrupt Enabled.
|  | If the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT, CMPF bit will be asserted, in the meanwhile, if CMPIE is set to 1, a compare interrupt request is generated.
[2] | CMPCOND | Compare Condition
|  | 0= Set the compare condition as that when a 12-bit A/D conversion result is less than the 12-bit CMPD (ADCMPRx[27:16]), the internal match counter will increase one.
|  | 1= Set the compare condition as that when a 12-bit A/D conversion result is greater or equal to the 12-bit CMPD (ADCMPRx[27:16]), the internal match counter will increase by one.
|  | Note: When the internal counter reaches the value to (CMPMATCNT +1), the CMPF bit will be set.
[6:3] | CMPCH | Compare Channel Selection
|  | 0000 = Channel 0 conversion result is selected to be compared.
|  | 0001 = Channel 1 conversion result is selected to be compared.
|  | 0010 = Channel 2 conversion result is selected to be compared.
|  | 0011 = Channel 3 conversion result is selected to be compared.
|  | 0100 = Channel 4 conversion result is selected to be compared.
|  | 0101 = Channel 5 conversion result is selected to be compared.
|  | 0110 = Channel 6 conversion result is selected to be compared.
|  | 0111 = Channel 7 conversion result is selected to be compared.
|  | 1000 = Channel 8 conversion result is selected to be compared.
|  | 1001 = Channel 9 conversion result is selected to be compared.
|  | 1010 = Channel 10 conversion result is selected to be compared.
[11:8] | CMPMATCNT | Compare Match Count
|  | When the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND[2], the internal match counter will increase 1.
|  | When the internal counter reaches the value to (CMPMATCNT +1), the CMPF bit will be set.
[27:16] | CMPD | Comparison Data
|  | The 12 bits data is used to compare with conversion result of specified channel.
|  | Software can use it to monitor the external analog input pin voltage variation in scan mode without imposing a load on software.

Definition at line 330 of file Nano100Series.h.

## ◆ CMPR1

__IO uint32_t ADC_T::CMPR1

# CMPR1

## Offset: 0x3C A/D Compare Register 1

Bits | Field | Descriptions
--- | --- | ---
[0] | CMPEN | Compare Enable
|  | 0 = Compare Disabled.
|  | 1 = Compare Enabled.
|  | Set this bit to 1 to enable compare CMPD[11:0] with specified channel conversion result when converted data is loaded into ADC_RESULTx register.
|  | When this bit is set to 1, and CMPMATCNT is 0, the CMPF will be set once the match is hit
[1] | CMPIE | Compare Interrupt Enable
|  | 0 = Compare function interrupt Disabled.
|  | 1 = Compare function interrupt Enabled.
|  | If the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT, CMPF bit will be asserted, in the meanwhile, if CMPIE is set to 1, a compare interrupt request is generated.
[2] | CMPCOND | Compare Condition
|  | 0= Set the compare condition as that when a 12-bit A/D conversion result is less than the 12-bit CMPD (ADCMPRx[27:16]), the internal match counter will increase one.
|  | 1= Set the compare condition as that when a 12-bit A/D conversion result is greater or equal to the 12-bit CMPD (ADCMPRx[27:16]), the internal match counter will increase by one.
|  | Note: When the internal counter reaches the value to (CMPMATCNT +1), the CMPF bit will be set.
[6:3] | CMPCH | Compare Channel Selection
|  | 0000 = Channel 0 conversion result is selected to be compared.
|  | 0001 = Channel 1 conversion result is selected to be compared.
|  | 0010 = Channel 2 conversion result is selected to be compared.
|  | 0011 = Channel 3 conversion result is selected to be compared.
|  | 0100 = Channel 4 conversion result is selected to be compared.
|  | 0101 = Channel 5 conversion result is selected to be compared.
|  | 0110 = Channel 6 conversion result is selected to be compared.
|  | 0111 = Channel 7 conversion result is selected to be compared.
|  | 1000 = Channel 8 conversion result is selected to be compared.
|  | 1001 = Channel 9 conversion result is selected to be compared.
|  | 1010 = Channel 10 conversion result is selected to be compared.
[11:8] | CMPMATCNT | Compare Match Count
|  | When the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND[2], the internal match counter will increase 1.
|  | When the internal counter reaches the value to (CMPMATCNT +1), the CMPF bit will be set.
[27:16] | CMPD | Comparison Data
|  | The 12 bits data is used to compare with conversion result of specified channel.
|  | Software can use it to monitor the external analog input pin voltage variation in scan mode without imposing a load on software.

Definition at line 371 of file Nano100Series.h.

## ◆ CR

__IO uint32_t ADC_T::CR

# CR

## Offset: 0x30 A/D Control Register

Bits | Field | Descriptions
--- | --- | ---
[0] | ADEN | A/D Converter Enable
|  | 0 = Disabled.
|  | 1 = Enabled.
|  | Before starting A/D conversion function, this bit should be set to 1.
|  | Clear it to 0 to disable A/D converter analog circuit power consumption.
[1] | ADIE | A/D Interrupt Enable
|  | 0 = A/D interrupt function Disabled.
|  | 1 = A/D interrupt function Enabled.
|  | A/D conversion end interrupt request is generated if ADIE bit is set to 1.
[3:2] | ADMD | A/D Converter Operation Mode
|  | 00 = Single conversion.
|  | 01 = Reserved.
|  | 10 = Single-cycle scan.
|  | 11 = Continuous scan.
[5:4] | TRGS | Hardware Trigger Source
|  | 00 = A/D conversion is started by external STADC pin.
|  | Others = Reserved.
|  | Software should disable TRGE and ADST before change TRGS.
|  | In hardware trigger mode, the ADST bit is set by the external trigger from STADC, However software has the highest priority to set or cleared ADST bit at any time.
[7:6] | TRGCOND | External Trigger Condition
|  | These two bits decide external pin STADC trigger event is level or edge.
|  | The signal must be kept at stable state at least 8 PCLKs for level trigger and 4 PCLKs at high and low state.
|  | 00 = Low level.
|  | 01 = High level.
|  | 10 = Falling edge.
|  | 11 = Rising edge.
[8] | TRGE | External Trigger Enable
|  | Enable or disable triggering of A/D conversion by external STADC pin.
|  | 0= Disabled.
|  | 1= Enabled.
[9] | PTEN | PDMA Transfer Enable
|  | 0 = PDMA data transfer Disabled.
|  | 1 = PDMA data transfer in ADC_RESULT 0~10 Enabled.
|  | When A/D conversion is completed, the converted data is loaded into ADC_RESULT 0~10, software can enable this bit to generate a PDMA data transfer request.
|  | When PTEN=1, software must set ADIE=0 to disable interrupt.
|  | PDMA can access ADC_RESULT 0-10 registers by block or single transfer mode.
[11] | ADST | A/D Conversion Start
|  | 0 = Conversion stopped and A/D converter enter idle state.
|  | 1 = Conversion starts.
|  | ADST bit can be set to 1 from two sources: software write and external pin STADC.
|  | ADST is cleared to 0 by hardware automatically at the end of single mode and single-cycle scan mode on specified channels.
|  | In continuous scan mode, A/D conversion is continuously performed sequentially unless software writes 0 to this bit or chip reset.
|  | Note: After ADC conversion done, SW needs to wait at least one ADC clock before to set this bit high again.
[13:12] | TMSEL | Select A/D Enable Time-Out Source
|  | 00 = TMR0_CH0.
|  | 01 = TMR0_CH1.
|  | 10 = TMR1_CH0.
|  | 11 = TMR1_CH1.
[15] | TMTRGMOD | Time Out Event Trigger ADC Conversion
|  | 0 = Disabled this function.
|  | 1 = Enabled ADC by TIMER OUT event.
|  | setting TMSEL to select time out event from timer 0~3
[17:16] | REFSEL | Reference Voltage Source Selection
|  | 00 = Select power as reference voltage.
|  | 01 = Select VBG as reference voltage.
|  | 10 = Select external voltage as reference voltage.
|  | 11 = CH7.

Definition at line 245 of file Nano100Series.h.

## ◆ DELSEL

__IO uint32_t ADC_T::DELSEL

# DELSEL

## Offset: 0x64 PDMA counter for delay time and PDMA transfer count and ADC start hold counter

Bits | Field | Descriptions
--- | --- | ---
[7:0] | En2StDelay | A/D Delay Time Select Register
|  | Set this register to adjust the time interval (in PCLK unit )between start signal and enable signal of ADC
|  | Note: The time interval is En2StDelay+1 PCLK cycle
[15:8] | TMPDMACNT | PDMA Count
|  | When each time out event occur PDMA will transfer TMPDMACNT +1 ADC result in the amount of this register setting
|  | Note: The total amount of PDMA transferring data should be set in PDMA byte count register.
|  | When PDMA finish is set, ADC will not be enabled and start transfer even though the time out event occur.
[23:16] | ADCSTHOLDCNT | ADC Start Hold Time Counter
|  | This ADC start is the start signal from ADC controller to analog ADC, not the ADST in ADCR[11],.
|  | In Figure 5-15, when ADC start signal transition from high to low, the ADC reset signal will transition from low to high, at this moment the ADC hold the input analog single and stop holding when ADC start signal transition from low to high.
|  | The interval of the holding time is programmable by setting this register.
|  | ADC need ADC start signal to keep low level at least 2 ADC CLOCK in order to get converting result more accurately.
|  | Setting this register will change the interval in ADC CLOCK unit.

Definition at line 454 of file Nano100Series.h.

## ◆ PDMA

__I uint32_t ADC_T::PDMA

# PDMA

## Offset: 0x60 A/D PDMA current transfer data Register

Bits | Field | Descriptions
--- | --- | ---
[11:0] | AD_PDMA | ADC PDMA Current Transfer Data Register
|  | When PDMA transferring, read this register can monitor current PDMA transfer data.
|  | This is a read only register.

Definition at line 431 of file Nano100Series.h.

## ◆ RESULT

__I uint32_t ADC_T::RESULT[11]

# RESULT0, RESULT1 .. RESULT10

## Offset: 0x00 ~ 0x28 A/D result Register 0

Bits | Field | Descriptions
--- | --- | ---
[11:0] | RSLT | A/D Conversion Result
|  | This field contains 12 bits conversion result.

Definition at line 173 of file Nano100Series.h.

## ◆ SR

__IO uint32_t ADC_T::SR

# SR

## Offset: 0x40 A/D Status Register

Bits | Field | Descriptions
--- | --- | ---
[0] | ADF | A/D Conversion End Flag
|  | A status flag that indicates the end of A/D conversion.
|  | ADF is set to 1 at these two conditions:
|  | When A/D conversion ends in single mode
|  | When A/D conversion ends on all specified channels in scan mode.
|  | This flag can be cleared by writing 1 to it.
[1] | CMPF0 | Compare Flag
|  | When the selected channel A/D conversion result meets setting condition in ADCMPR0 then this bit is set to 1.
|  | And it is cleared by writing 1 to self.
|  | 0 = Conversion result in ADC_RESULTx does not meet ADCMPR0setting.
|  | 1 = Conversion result in ADC_RESULTx meets ADCMPR0setting.
|  | This flag can be cleared by writing 1 to it.
|  | Note: when this flag is set, the matching counter will be reset to 0,and continue to count when user write 1 to clear CMPF0
[2] | CMPF1 | Compare Flag
|  | When the selected channel A/D conversion result meets setting condition in ADCMPR1 then this bit is set to 1.
|  | And it is cleared by writing 1 to self.
|  | 0 = Conversion result in ADC_RESULTx does not meet ADCMPR1 setting.
|  | 1 = Conversion result in ADC_RESULTx meets ADCMPR1 setting.
|  | This flag can be cleared by writing 1 to it.
|  | Note: when this flag is set, the matching counter will be reset to 0,and continue to count when user write 1 to clear CMPF1
[3] | BUSY | BUSY/IDLE
|  | 0 = A/D converter is in idle state.
|  | 1 = A/D converter is busy at conversion.
|  | This bit is a mirror of ADST bit in ADCR. That is to say if ADST = 1,then BUSY is 1 and vice versa.
|  | It is read only.
[7:4] | CHANNEL | Current Conversion Channel
|  | This filed reflects current conversion channel when BUSY=1.
|  | When BUSY=0, it shows the next channel to be converted.
|  | It is read only.
[16:8] | VALID | Data Valid Flag
|  | It is a mirror of VALID bit in ADC_RESULTx
[28:20] | OVERRUN | Over Run Flag
|  | It is a mirror to OVERRUN bit in ADC_RESULTx

Definition at line 414 of file Nano100Series.h.

The documentation for this struct was generated from the following file:

- C:/Users/yachen/workzone/bsp/nano100absp/Library/Device/Nuvoton/Nano100Series/Include/Nano100Series.h