33 #define ADC_CH_0_MASK (1UL << 0) 34 #define ADC_CH_1_MASK (1UL << 1) 35 #define ADC_CH_2_MASK (1UL << 2) 36 #define ADC_CH_3_MASK (1UL << 3) 37 #define ADC_CH_4_MASK (1UL << 4) 38 #define ADC_CH_5_MASK (1UL << 5) 39 #define ADC_CH_6_MASK (1UL << 6) 40 #define ADC_CH_7_MASK (1UL << 7) 41 #define ADC_CH_8_MASK (1UL << 8) 42 #define ADC_CH_9_MASK (1UL << 9) 43 #define ADC_CH_10_MASK (1UL << 10) 44 #define ADC_CH_11_MASK (1UL << 11) 45 #define ADC_CH_12_MASK (1UL << 12) 46 #define ADC_CH_13_MASK (1UL << 13) 47 #define ADC_CH_14_MASK (1UL << 14) 48 #define ADC_CH_15_MASK (1UL << 15) 49 #define ADC_CH_16_MASK (1UL << 16) 50 #define ADC_CH_17_MASK (1UL << 17) 51 #define ADC_CHEN_Msk (0x3FFFF) 52 #define ADC_PDMADATA_AD_PDMA_Msk (0xFFF) 53 #define ADC_CMP_LESS_THAN (0UL) 54 #define ADC_CMP_GREATER_OR_EQUAL_TO (ADC_CMPR_CMPCOND_Msk) 55 #define ADC_TRIGGER_BY_EXT_PIN (0UL) 56 #define ADC_LOW_LEVEL_TRIGGER (0UL << ADC_CR_TRGCOND_Pos) 57 #define ADC_HIGH_LEVEL_TRIGGER (1UL << ADC_CR_TRGCOND_Pos) 58 #define ADC_FALLING_EDGE_TRIGGER (2UL << ADC_CR_TRGCOND_Pos) 59 #define ADC_RISING_EDGE_TRIGGER (3UL << ADC_CR_TRGCOND_Pos) 60 #define ADC_ADF_INT (ADC_SR_ADF_Msk) 61 #define ADC_CMP0_INT (ADC_SR_CMPF0_Msk) 62 #define ADC_CMP1_INT (ADC_SR_CMPF1_Msk) 63 #define ADC_INPUT_MODE_SINGLE_END (0UL << ADC_CR_DIFF_Pos) 64 #define ADC_INPUT_MODE_DIFFERENTIAL (1UL << ADC_CR_DIFF_Pos) 65 #define ADC_OPERATION_MODE_SINGLE (0UL << ADC_CR_ADMD_Pos) 66 #define ADC_OPERATION_MODE_SINGLE_CYCLE (2UL << ADC_CR_ADMD_Pos) 67 #define ADC_OPERATION_MODE_CONTINUOUS (3UL << ADC_CR_ADMD_Pos) 68 #define ADC_DMODE_OUT_FORMAT_UNSIGNED (0UL << ADC_CR_DIFF_Pos) 69 #define ADC_DMODE_OUT_FORMAT_2COMPLEMENT (1UL << ADC_CR_DIFF_Pos) 70 #define ADC_RESSEL_6_BIT (0UL << ADC_CR_RESSEL_Pos) 71 #define ADC_RESSEL_8_BIT (1UL << ADC_CR_RESSEL_Pos) 72 #define ADC_RESSEL_10_BIT (2UL << ADC_CR_RESSEL_Pos) 73 #define ADC_RESSEL_12_BIT (3UL << ADC_CR_RESSEL_Pos) 74 #define ADC_REFSEL_POWER (0UL << ADC_CR_REFSEL_Pos) 75 #define ADC_REFSEL_INT_VREF (1UL << ADC_CR_REFSEL_Pos) 76 #define ADC_REFSEL_VREF (2UL << ADC_CR_REFSEL_Pos) 92 #define ADC_GET_CONVERSION_DATA(adc, u32ChNum) (ADC->RESULT[u32ChNum] & ADC_RESULT_RSLT_Msk) 104 #define ADC_GET_INT_FLAG(adc, u32Mask) (ADC->SR & (u32Mask)) 116 #define ADC_CLR_INT_FLAG(adc, u32Mask) (ADC->SR = (ADC->SR & ~(ADC_SR_ADF_Msk | \ 118 ADC_SR_CMPF1_Msk)) | (u32Mask)) 128 #define ADC_IS_BUSY(adc) (ADC->SR & ADC_SR_BUSY_Msk ? 1 : 0) 139 #define ADC_IS_DATA_OVERRUN(adc, u32ChNum) (ADC->RESULT[u32ChNum] & ADC_RESULT_OVERRUN_Msk ? 1 : 0) 150 #define ADC_IS_DATA_VALID(adc, u32ChNum) (ADC->RESULT[u32ChNum] & ADC_RESULT_VALID_Msk ? 1 : 0) 158 #define ADC_POWER_DOWN(adc) (ADC->CR &= ~ADC_CR_ADEN_Msk) 166 #define ADC_POWER_ON(adc) \ 168 ADC->CR |= ADC_CR_ADEN_Msk; \ 169 while ((!(ADC->SR & ADC_SR_INITRDY_Msk)) || (!(ADC->PWRCTL & ADC_PWRCTL_PWUPRDY_Msk))); \ 187 #define ADC_ENABLE_CMP0(adc, \ 191 u32MatchCount) (ADC->CMPR0 = ((u32ChNum) << ADC_CMPR_CMPCH_Pos) | \ 193 ((u32Data) << ADC_CMPR_CMPD_Pos) | \ 194 (((u32MatchCount) - 1) << ADC_CMPR_CMPMATCNT_Pos) |\ 203 #define ADC_DISABLE_CMP0(adc) (ADC->CMPR0 = 0) 220 #define ADC_ENABLE_CMP1(adc, \ 224 u32MatchCount) (ADC->CMPR1 = ((u32ChNum) << ADC_CMPR_CMPCH_Pos) | \ 226 ((u32Data) << ADC_CMPR_CMPD_Pos) | \ 227 ((u32MatchCount - 1) << ADC_CMPR_CMPMATCNT_Pos) |\ 236 #define ADC_DISABLE_CMP1(adc) (ADC->CMPR1 = 0) 245 #define ADC_SET_INPUT_CHANNEL(adc, u32Mask) (ADC->CHEN = (ADC->CHEN & ~ADC_CHEN_Msk) | (u32Mask)) 253 #define ADC_START_CONV(adc) (ADC->CR |= ADC_CR_ADST_Msk) 261 #define ADC_STOP_CONV(adc) (ADC->CR &= ~ADC_CR_ADST_Msk) 272 #define ADC_SET_DMOF(adc, u32Format) (ADC->CR = (ADC->CR & ~ADC_CR_DIFF_Msk) | u32Format) 285 #define ADC_SET_RESOLUTION(adc, u32Resolution) (ADC->CR = (ADC->CR & ~ADC_CR_RESSEL_Msk) | u32Resolution) 297 #define ADC_SET_REF_VOLTAGE(adc, u32Ref) (ADC->CR = (ADC->CR & ~ADC_CR_REFSEL_Msk) | u32Ref) 307 #define ADC_SET_POWERDOWN_MODE(adc, u32Mode, u32CalEn) \ 308 ADC->PWRCTL = (ADC->PWRCTL & ~(ADC_PWRCTL_PWDMOD_Msk | ADC_PWRCTL_PWDCALEN_Msk)) \ 309 | (u32Mode << ADC_PWRCTL_PWDMOD_Pos) | (u32CalEn << ADC_PWRCTL_PWDCALEN_Pos) 317 #define ADC_ENABLE_PDMA(adc) (ADC->CR |= ADC_CR_PTEN_Msk) 325 #define ADC_DISABLE_PDMA(adc) (ADC->CR &= ~ADC_CR_PTEN_Msk) 333 #define ADC_GET_PDMA_DATA(adc) (ADC->PDMA & ADC_PDMADATA_AD_PDMA_Msk) 336 uint32_t u32InputMode,
346 uint32_t u32PDMACnt);
350 uint32_t u32SampleTime);
void ADC_EnableTimerTrigger(ADC_T *adc, uint32_t u32Source, uint32_t u32PDMACnt)
Config and enable timer trigger.
void ADC_Close(ADC_T *adc)
Disable ADC module.
void ADC_Open(ADC_T *adc, uint32_t u32InputMode, uint32_t u32OpMode, uint32_t u32ChMask)
This API configures ADC module to be ready for convert the input from selected channel.
void ADC_DisableHWTrigger(ADC_T *adc)
Disable hardware trigger ADC function.
void ADC_DisableTimerTrigger(ADC_T *adc)
Disable timer trigger ADC function.
void ADC_EnableInt(ADC_T *adc, uint32_t u32Mask)
Enable the interrupt(s) selected by u32Mask parameter.
void ADC_EnableHWTrigger(ADC_T *adc, uint32_t u32Source, uint32_t u32Param)
Configure the hardware trigger condition and enable hardware trigger.
void ADC_SetExtraSampleTime(ADC_T *adc, uint32_t u32ChNum, uint32_t u32SampleTime)
Configure the extended sampling time.
void ADC_DisableInt(ADC_T *adc, uint32_t u32Mask)
Disable the interrupt(s) selected by u32Mask parameter.