Nano100BN Series BSP  V3.03.002
The Board Support Package for Nano100BN Series
Data Fields
FMC_T Struct Reference

#include <Nano100Series.h>

Data Fields

__IO uint32_t ISPCON
 
__IO uint32_t ISPADR
 
__IO uint32_t ISPDAT
 
__IO uint32_t ISPCMD
 
__IO uint32_t ISPTRG
 
__I uint32_t DFBADR
 
uint32_t RESERVE0 [10]
 
__IO uint32_t ISPSTA
 

Detailed Description

@addtogroup FMC Flash Memory Controller(FMC)
Memory Mapped Structure for FMC Controller

Definition at line 1792 of file Nano100Series.h.

Field Documentation

◆ DFBADR

__I uint32_t FMC_T::DFBADR

DFBADR

Offset: 0x14 Data Flash Base Address

Bits Field Descriptions
[31:0] DFBA Data Flash Base Address
This register indicates data flash start address. It is a read only register.
The data flash start address is defined by user.
Since on chip flash erase unit is 512 bytes, it is mandatory to keep bit 8-0 as 0.

Definition at line 1902 of file Nano100Series.h.

◆ ISPADR

__IO uint32_t FMC_T::ISPADR

ISPADR

Offset: 0x04 ISP Address Register

Bits Field Descriptions
[31:0] ISPADR ISP Address
This chip supports word program only.
ISPADR[1:0] must be kept 00b for ISP operation, and ISPADR[8:0] must be kept 0_0000_0000b for Vector Page Re-map Command.

Definition at line 1845 of file Nano100Series.h.

◆ ISPCMD

__IO uint32_t FMC_T::ISPCMD

ISPCMD

Offset: 0x0C ISP Command Register

Bits Field Descriptions
[3:0] FCTRL ISP Command
The ISP command table is shown as follows.
[4] FCEN ISP Command
The ISP command table is shown as follows.
[5] FOEN ISP Command
The ISP command table is shown as follows.

Definition at line 1874 of file Nano100Series.h.

◆ ISPCON

__IO uint32_t FMC_T::ISPCON

ISPCON

Offset: 0x00 ISP Control Register

Bits Field Descriptions
[0] ISPEN ISP Enable (Write-Protection Bit)
ISP function enable bit. Set this bit to enable ISP function.
0 = ISP function Disabled.
1 = ISP function Enabled.
[1] BS Boot Select (Write-Protection Bit)
Set/clear this bit to select next booting from LDROM/APROM, respectively.
This bit also functions as chip booting status flag, which can be used to check where chip booted from.
This bit is initiated with the inversed value of CBS in Config0 after power-on reset; It keeps the same value at other reset.
0 = boot from APROM.
1 = boot from LDROM.
[3] APUEN APROM Update Enable (Write-Protection Bit)
APROM update enable bit.
0 = APROM can not be updated.
1 = APROM can be updated when the MCU runs in APROM.
[4] CFGUEN Enable Config-Bits Update By ISP (Write-Protection Bit)
0 = Disabling ISP can update config-bits.
1 = Enabling ISP can update config-bits.
[5] LDUEN LDROM Update Enable (Write-Protection Bit)
LDROM update enable bit.
0 = LDROM cannot be updated.
1 = LDROM can be updated when the chip runs in APROM.
[6] ISPFF ISP Fail Flag (Write-Protection Bit)
This bit is set by hardware when a triggered ISP meets any of the following conditions:
(1) APROM writes to itself
(2) LDROM writes to itself
(3) CONFIG is erased/programmed if CFGUEN is set to 0
(4) Destination address is illegal, such as over an available range
Write 1 to clear.

Definition at line 1832 of file Nano100Series.h.

◆ ISPDAT

__IO uint32_t FMC_T::ISPDAT

ISPDAT

Offset: 0x08 ISP Data Register

Bits Field Descriptions
[31:0] ISPDAT ISP Data
Write data to this register before ISP program operation
Read data from this register after ISP read operation

Definition at line 1858 of file Nano100Series.h.

◆ ISPSTA

__IO uint32_t FMC_T::ISPSTA

ISPSTA

Offset: 0x40 ISP Status Register

Bits Field Descriptions
[0] ISPBUSY ISP BUSY
0 = ISP operation is finished.
1 = ISP operation is busy.
Read Only
[2:1] CBS Config Boot Selection Status
[6] ISPFF ISP Fail Flag
This bit is set by hardware when a triggered ISP meets any of the following conditions:
(1) APROM writes to itself.
(2) LDROM writes to itself.
(3) CONFIG is erased/programmed when the MCU is running in APROM.
(4) Destination address is illegal, such as over an available range.
Write 1 to clear.

Definition at line 1926 of file Nano100Series.h.

◆ ISPTRG

__IO uint32_t FMC_T::ISPTRG

ISPTRG

Offset: 0x10 ISP Trigger Register

Bits Field Descriptions
[0] ISPGO ISP Start Trigger
Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.
0 = ISP operation is finished.
1 = ISP is progressing.

Definition at line 1888 of file Nano100Series.h.

◆ RESERVE0

uint32_t FMC_T::RESERVE0[10]

Definition at line 1903 of file Nano100Series.h.


The documentation for this struct was generated from the following file: