34 #define FREQ_128MHZ 128000000 35 #define FREQ_120MHZ 120000000 36 #define FREQ_48MHZ 48000000 37 #define FREQ_42MHZ 42000000 38 #define FREQ_32MHZ 32000000 39 #define FREQ_24MHZ 24000000 40 #define FREQ_12MHZ 12000000 43 #define CLK_PWRCTL_HXT_EN (0x1UL<<CLK_PWRCTL_HXT_EN_Pos) 44 #define CLK_PWRCTL_LXT_EN (0x1UL<<CLK_PWRCTL_LXT_EN_Pos) 45 #define CLK_PWRCTL_HIRC_EN (0x1UL<<CLK_PWRCTL_HIRC_EN_Pos) 46 #define CLK_PWRCTL_LIRC_EN (0x1UL<<CLK_PWRCTL_LIRC_EN_Pos) 47 #define CLK_PWRCTL_DELY_EN (0x1UL<<CLK_PWRCTL_WK_DLY_Pos) 48 #define CLK_PWRCTL_WAKEINT_EN (0x1UL<<CLK_PWRCTL_PD_WK_IE_Pos) 49 #define CLK_PWRCTL_PWRDOWN_EN (0x1UL<<CLK_PWRCTL_PD_EN_Pos) 50 #define CLK_PWRCTL_HXT_SELXT (0x1UL<<CLK_PWRCTL_HXT_SELXT_Pos) 51 #define CLK_PWRCTL_HXT_GAIN (0x1UL<<CLK_PWRCTL_HXT_GAIN_Pos) 52 #define CLK_PWRCTL_LXT_SCNT (0x1UL<<CLK_PWRCTL_LXT_SCNT_Pos) 56 #define CLK_AHBCLK_GPIO_EN (0x1UL<<CLK_AHBCLK_GPIO_EN_Pos) 57 #define CLK_AHBCLK_DMA_EN (0x1UL<<CLK_AHBCLK_DMA_EN_Pos) 58 #define CLK_AHBCLK_ISP_EN (0x1UL<<CLK_AHBCLK_ISP_EN_Pos) 59 #define CLK_AHBCLK_EBI_EN (0x1UL<<CLK_AHBCLK_EBI_EN_Pos) 60 #define CLK_AHBCLK_SRAM_EN (0x1UL<<CLK_AHBCLK_SRAM_EN_Pos) 61 #define CLK_AHBCLK_TICK_EN (0x1UL<<CLK_AHBCLK_TICK_EN_Pos) 64 #define CLK_APBCLK_WDT_EN (0x1UL<<CLK_APBCLK_WDT_EN_Pos) 65 #define CLK_APBCLK_RTC_EN (0x1UL<<CLK_APBCLK_RTC_EN_Pos) 66 #define CLK_APBCLK_TMR0_EN (0x1UL<<CLK_APBCLK_TMR0_EN_Pos) 67 #define CLK_APBCLK_TMR1_EN (0x1UL<<CLK_APBCLK_TMR1_EN_Pos) 68 #define CLK_APBCLK_TMR2_EN (0x1UL<<CLK_APBCLK_TMR2_EN_Pos) 69 #define CLK_APBCLK_TMR3_EN (0x1UL<<CLK_APBCLK_TMR3_EN_Pos) 70 #define CLK_APBCLK_FDIV_EN (0x1UL<<CLK_APBCLK_FDIV_EN_Pos) 71 #define CLK_APBCLK_SC2_EN (0x1UL<<CLK_APBCLK_SC2_EN_Pos) 72 #define CLK_APBCLK_I2C0_EN (0x1UL<<CLK_APBCLK_I2C0_EN_Pos) 73 #define CLK_APBCLK_I2C1_EN (0x1UL<<CLK_APBCLK_I2C1_EN_Pos) 74 #define CLK_APBCLK_SPI0_EN (0x1UL<<CLK_APBCLK_SPI0_EN_Pos) 75 #define CLK_APBCLK_SPI1_EN (0x1UL<<CLK_APBCLK_SPI1_EN_Pos) 76 #define CLK_APBCLK_SPI2_EN (0x1UL<<CLK_APBCLK_SPI2_EN_Pos) 77 #define CLK_APBCLK_UART0_EN (0x1UL<<CLK_APBCLK_UART0_EN_Pos) 78 #define CLK_APBCLK_UART1_EN (0x1UL<<CLK_APBCLK_UART1_EN_Pos) 79 #define CLK_APBCLK_PWM0_CH01_EN (0x1UL<<CLK_APBCLK_PWM0_CH01_EN_Pos) 80 #define CLK_APBCLK_PWM0_CH23_EN (0x1UL<<CLK_APBCLK_PWM0_CH23_EN_Pos) 81 #define CLK_APBCLK_PWM1_CH01_EN (0x1UL<<CLK_APBCLK_PWM1_CH01_EN_Pos) 82 #define CLK_APBCLK_PWM1_CH23_EN (0x1UL<<CLK_APBCLK_PWM1_CH23_EN_Pos) 83 #define CLK_APBCLK_DAC_EN (0x1UL<<CLK_APBCLK_DAC_EN_Pos) 84 #define CLK_APBCLK_LCD_EN (0x1UL<<CLK_APBCLK_LCD_EN_Pos) 85 #define CLK_APBCLK_USBD_EN (0x1UL<<CLK_APBCLK_USBD_EN_Pos) 86 #define CLK_APBCLK_ADC_EN (0x1UL<<CLK_APBCLK_ADC_EN_Pos) 87 #define CLK_APBCLK_I2S_EN (0x1UL<<CLK_APBCLK_I2S_EN_Pos) 88 #define CLK_APBCLK_SC0_EN (0x1UL<<CLK_APBCLK_SC0_EN_Pos) 89 #define CLK_APBCLK_SC1_EN (0x1UL<<CLK_APBCLK_SC1_EN_Pos) 92 #define CLK_CLKSTATUS_HXT_STB (0x1UL<<CLK_CLKSTATUS_HXT_STB_Pos) 93 #define CLK_CLKSTATUS_LXT_STB (0x1UL<<CLK_CLKSTATUS_LXT_STB_Pos) 94 #define CLK_CLKSTATUS_PLL_STB (0x1UL<<CLK_CLKSTATUS_PLL_STB_Pos) 95 #define CLK_CLKSTATUS_LIRC_STB (0x1UL<<CLK_CLKSTATUS_LIRC_STB_Pos) 96 #define CLK_CLKSTATUS_HIRC_STB (0x1UL<<CLK_CLKSTATUS_HIRC_STB_Pos) 97 #define CLK_CLKSTATUS_CLK_SW_FAIL (0x1UL<<CLK_CLKSTATUS_CLK_SW_FAIL_Pos) 101 #define CLK_CLKSEL0_HCLK_S_HXT (0UL<<CLK_CLKSEL0_HCLK_S_Pos) 102 #define CLK_CLKSEL0_HCLK_S_LXT (1UL<<CLK_CLKSEL0_HCLK_S_Pos) 103 #define CLK_CLKSEL0_HCLK_S_PLL (2UL<<CLK_CLKSEL0_HCLK_S_Pos) 104 #define CLK_CLKSEL0_HCLK_S_LIRC (3UL<<CLK_CLKSEL0_HCLK_S_Pos) 105 #define CLK_CLKSEL0_HCLK_S_HIRC (7UL<<CLK_CLKSEL0_HCLK_S_Pos) 108 #define CLK_CLKSEL1_LCD_S_LXT (0x0UL<<CLK_CLKSEL1_LCD_S_Pos) 110 #define CLK_CLKSEL1_TMR1_S_HXT (0x0UL<<CLK_CLKSEL1_TMR1_S_Pos) 111 #define CLK_CLKSEL1_TMR1_S_LXT (0x1UL<<CLK_CLKSEL1_TMR1_S_Pos) 112 #define CLK_CLKSEL1_TMR1_S_LIRC (0x2UL<<CLK_CLKSEL1_TMR1_S_Pos) 113 #define CLK_CLKSEL1_TMR1_S_EXT (0x3UL<<CLK_CLKSEL1_TMR1_S_Pos) 114 #define CLK_CLKSEL1_TMR1_S_HIRC (0x4UL<<CLK_CLKSEL1_TMR1_S_Pos) 116 #define CLK_CLKSEL1_TMR0_S_HXT (0x0UL<<CLK_CLKSEL1_TMR0_S_Pos) 117 #define CLK_CLKSEL1_TMR0_S_LXT (0x1UL<<CLK_CLKSEL1_TMR0_S_Pos) 118 #define CLK_CLKSEL1_TMR0_S_LIRC (0x2UL<<CLK_CLKSEL1_TMR0_S_Pos) 119 #define CLK_CLKSEL1_TMR0_S_EXT (0x3UL<<CLK_CLKSEL1_TMR0_S_Pos) 120 #define CLK_CLKSEL1_TMR0_S_HIRC (0x4UL<<CLK_CLKSEL1_TMR0_S_Pos) 122 #define CLK_CLKSEL1_PWM0_CH01_S_HXT (0x0UL<<CLK_CLKSEL1_PWM0_CH01_S_Pos) 123 #define CLK_CLKSEL1_PWM0_CH01_S_LXT (0x1UL<<CLK_CLKSEL1_PWM0_CH01_S_Pos) 124 #define CLK_CLKSEL1_PWM0_CH01_S_HCLK (0x2UL<<CLK_CLKSEL1_PWM0_CH01_S_Pos) 125 #define CLK_CLKSEL1_PWM0_CH01_S_HIRC (0x3UL<<CLK_CLKSEL1_PWM0_CH01_S_Pos) 127 #define CLK_CLKSEL1_PWM0_CH23_S_HXT (0x0UL<<CLK_CLKSEL1_PWM0_CH23_S_Pos) 128 #define CLK_CLKSEL1_PWM0_CH23_S_LXT (0x1UL<<CLK_CLKSEL1_PWM0_CH23_S_Pos) 129 #define CLK_CLKSEL1_PWM0_CH23_S_HCLK (0x2UL<<CLK_CLKSEL1_PWM0_CH23_S_Pos) 130 #define CLK_CLKSEL1_PWM0_CH23_S_HIRC (0x3UL<<CLK_CLKSEL1_PWM0_CH23_S_Pos) 132 #define CLK_CLKSEL1_ADC_S_HXT (0x0UL<<CLK_CLKSEL1_ADC_S_Pos) 133 #define CLK_CLKSEL1_ADC_S_LXT (0x1UL<<CLK_CLKSEL1_ADC_S_Pos) 134 #define CLK_CLKSEL1_ADC_S_PLL (0x2UL<<CLK_CLKSEL1_ADC_S_Pos) 135 #define CLK_CLKSEL1_ADC_S_HIRC (0x3UL<<CLK_CLKSEL1_ADC_S_Pos) 137 #define CLK_CLKSEL1_UART_S_HXT (0x0UL<<CLK_CLKSEL1_UART_S_Pos) 138 #define CLK_CLKSEL1_UART_S_LXT (0x1UL<<CLK_CLKSEL1_UART_S_Pos) 139 #define CLK_CLKSEL1_UART_S_PLL (0x2UL<<CLK_CLKSEL1_UART_S_Pos) 140 #define CLK_CLKSEL1_UART_S_HIRC (0x3UL<<CLK_CLKSEL1_UART_S_Pos) 143 #define CLK_CLKSEL2_SPI2_S_PLL (0x0UL<<CLK_CLKSEL2_SPI2_S_Pos) 144 #define CLK_CLKSEL2_SPI2_S_HCLK (0x1UL<<CLK_CLKSEL2_SPI2_S_Pos) 146 #define CLK_CLKSEL2_SPI1_S_PLL (0x0UL<<CLK_CLKSEL2_SPI1_S_Pos) 147 #define CLK_CLKSEL2_SPI1_S_HCLK (0x1UL<<CLK_CLKSEL2_SPI1_S_Pos) 149 #define CLK_CLKSEL2_SPI0_S_PLL (0x0UL<<CLK_CLKSEL2_SPI0_S_Pos) 150 #define CLK_CLKSEL2_SPI0_S_HCLK (0x1UL<<CLK_CLKSEL2_SPI0_S_Pos) 152 #define CLK_CLKSEL2_SC_S_HXT (0x0UL<<CLK_CLKSEL2_SC_S_Pos) 153 #define CLK_CLKSEL2_SC_S_PLL (0x1UL<<CLK_CLKSEL2_SC_S_Pos) 154 #define CLK_CLKSEL2_SC_S_HIRC (0x2UL<<CLK_CLKSEL2_SC_S_Pos) 156 #define CLK_CLKSEL2_I2S_S_HXT (0x0UL<<CLK_CLKSEL2_I2S_S_Pos) 157 #define CLK_CLKSEL2_I2S_S_PLL (0x1UL<<CLK_CLKSEL2_I2S_S_Pos) 158 #define CLK_CLKSEL2_I2S_S_HIRC (0x2UL<<CLK_CLKSEL2_I2S_S_Pos) 160 #define CLK_CLKSEL2_TMR3_S_HXT (0x0UL<<CLK_CLKSEL2_TMR3_S_Pos) 161 #define CLK_CLKSEL2_TMR3_S_LXT (0x1UL<<CLK_CLKSEL2_TMR3_S_Pos) 162 #define CLK_CLKSEL2_TMR3_S_LIRC (0x2UL<<CLK_CLKSEL2_TMR3_S_Pos) 163 #define CLK_CLKSEL2_TMR3_S_EXT (0x3UL<<CLK_CLKSEL2_TMR3_S_Pos) 164 #define CLK_CLKSEL2_TMR3_S_HIRC (0x4UL<<CLK_CLKSEL2_TMR3_S_Pos) 166 #define CLK_CLKSEL2_TMR2_S_HXT (0x0UL<<CLK_CLKSEL2_TMR2_S_Pos) 167 #define CLK_CLKSEL2_TMR2_S_LXT (0x1UL<<CLK_CLKSEL2_TMR2_S_Pos) 168 #define CLK_CLKSEL2_TMR2_S_LIRC (0x2UL<<CLK_CLKSEL2_TMR2_S_Pos) 169 #define CLK_CLKSEL2_TMR2_S_EXT (0x3UL<<CLK_CLKSEL2_TMR2_S_Pos) 170 #define CLK_CLKSEL2_TMR2_S_HIRC (0x4UL<<CLK_CLKSEL2_TMR2_S_Pos) 172 #define CLK_CLKSEL2_PWM1_CH01_S_HXT (0x0UL<<CLK_CLKSEL2_PWM1_CH01_S_Pos) 173 #define CLK_CLKSEL2_PWM1_CH01_S_LXT (0x1UL<<CLK_CLKSEL2_PWM1_CH01_S_Pos) 174 #define CLK_CLKSEL2_PWM1_CH01_S_HCLK (0x2UL<<CLK_CLKSEL2_PWM1_CH01_S_Pos) 175 #define CLK_CLKSEL2_PWM1_CH01_S_HIRC (0x3UL<<CLK_CLKSEL2_PWM1_CH01_S_Pos) 177 #define CLK_CLKSEL2_PWM1_CH23_S_HXT (0x0UL<<CLK_CLKSEL2_PWM1_CH23_S_Pos) 178 #define CLK_CLKSEL2_PWM1_CH23_S_LXT (0x1UL<<CLK_CLKSEL2_PWM1_CH23_S_Pos) 179 #define CLK_CLKSEL2_PWM1_CH23_S_HCLK (0x2UL<<CLK_CLKSEL2_PWM1_CH23_S_Pos) 180 #define CLK_CLKSEL2_PWM1_CH23_S_HIRC (0x3UL<<CLK_CLKSEL2_PWM1_CH23_S_Pos) 182 #define CLK_CLKSEL2_FRQDIV_S_HXT (0x0UL<<CLK_CLKSEL2_FRQDIV_S_Pos) 183 #define CLK_CLKSEL2_FRQDIV_S_LXT (0x1UL<<CLK_CLKSEL2_FRQDIV_S_Pos) 184 #define CLK_CLKSEL2_FRQDIV_S_HCLK (0x2UL<<CLK_CLKSEL2_FRQDIV_S_Pos) 185 #define CLK_CLKSEL2_FRQDIV_S_HIRC (0x3UL<<CLK_CLKSEL2_FRQDIV_S_Pos) 188 #define CLK_HCLK_CLK_DIVIDER(x) (((x-1)<< CLK_CLKDIV0_HCLK_N_Pos) & CLK_CLKDIV0_HCLK_N_Msk) 189 #define CLK_USB_CLK_DIVIDER(x) (((x-1)<< CLK_CLKDIV0_USB_N_Pos) & CLK_CLKDIV0_USB_N_Msk) 190 #define CLK_UART_CLK_DIVIDER(x) (((x-1)<< CLK_CLKDIV0_UART_N_Pos) & CLK_CLKDIV0_UART_N_Msk) 191 #define CLK_ADC_CLK_DIVIDER(x) (((x-1)<< CLK_CLKDIV0_ADC_N_Pos) & CLK_CLKDIV0_ADC_N_Msk) 192 #define CLK_SC0_CLK_DIVIDER(x) (((x-1)<< CLK_CLKDIV0_SC0_N_Pos) & CLK_CLKDIV0_SC0_N_Msk) 193 #define CLK_I2S_CLK_DIVIDER(x) (((x-1)<< CLK_CLKDIV0_I2S_N_Pos) & CLK_CLKDIV0_I2S_N_Msk) 196 #define CLK_SC2_CLK_DIVIDER(x) (((x-1)<< CLK_CLKDIV1_SC2_N_Pos ) & CLK_CLKDIV1_SC2_N_Msk) 197 #define CLK_SC1_CLK_DIVIDER(x) (((x-1)<< CLK_CLKDIV1_SC1_N_Pos ) & CLK_CLKDIV1_SC1_N_Msk) 200 #define CLK_CLKSEL0_STCLKSEL_HCLK (1) 201 #define CLK_CLKSEL0_STCLKSEL_HCLK_DIV8 (2) 204 #define CLK_PLLCTL_OUT_DV (0x1UL<<CLK_PLLCTL_OUT_DV_Pos) 205 #define CLK_PLLCTL_PD (0x1UL<<CLK_PLLCTL_PD_Pos) 206 #define CLK_PLLCTL_PLL_SRC_HIRC (0x1UL<<CLK_PLLCTL_PLL_SRC_Pos) 207 #define CLK_PLLCTL_PLL_SRC_HXT (0x0UL<<CLK_PLLCTL_PLL_SRC_Pos) 209 #define CLK_PLLCTL_NR_2 0x000 210 #define CLK_PLLCTL_NR_4 0x100 211 #define CLK_PLLCTL_NR_8 0x200 212 #define CLK_PLLCTL_NR_16 0x300 213 #define CLK_PLLCON_NF(x) ((x)-32) 215 #define CLK_PLLCON_NO_1 0x0000UL 216 #define CLK_PLLCON_NO_2 0x1000UL 218 #if (__HXT == 12000000) 219 #define CLK_PLLCTL_120MHz_HXT (CLK_PLLCTL_PLL_SRC_HXT | CLK_PLLCON_NO_1 | CLK_PLLCTL_NR_4 | CLK_PLLCON_NF(40) ) 220 #define CLK_PLLCTL_96MHz_HXT (CLK_PLLCTL_PLL_SRC_HXT | CLK_PLLCON_NO_1 | CLK_PLLCTL_NR_8 | CLK_PLLCON_NF(64) ) 221 #define CLK_PLLCTL_48MHz_HXT (CLK_PLLCTL_PLL_SRC_HXT | CLK_PLLCON_NO_1 | CLK_PLLCTL_NR_16| CLK_PLLCON_NF(64) ) 222 #define CLK_PLLCTL_84MHz_HXT (CLK_PLLCTL_PLL_SRC_HXT | CLK_PLLCON_NO_1 | CLK_PLLCTL_NR_8 | CLK_PLLCON_NF(56) ) 223 #define CLK_PLLCTL_42MHz_HXT (CLK_PLLCTL_PLL_SRC_HXT | CLK_PLLCON_NO_1 | CLK_PLLCTL_NR_16| CLK_PLLCON_NF(56) ) 225 # error "The PLL pre-definitions are only valid when external crystal is 12MHz" 227 #define CLK_PLLCTL_120MHz_HIRC (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLLCON_NO_1 | CLK_PLLCTL_NR_4 | CLK_PLLCON_NF(40) ) 228 #define CLK_PLLCTL_96MHz_HIRC (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLLCON_NO_1 | CLK_PLLCTL_NR_8 | CLK_PLLCON_NF(64) ) 229 #define CLK_PLLCTL_48MHz_HIRC (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLLCON_NO_1 | CLK_PLLCTL_NR_16| CLK_PLLCON_NF(64) ) 230 #define CLK_PLLCTL_84MHz_HIRC (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLLCON_NO_1 | CLK_PLLCTL_NR_8 | CLK_PLLCON_NF(56) ) 231 #define CLK_PLLCTL_42MHz_HIRC (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLLCON_NO_1 | CLK_PLLCTL_NR_16| CLK_PLLCON_NF(56) ) 234 #define CLK_FRQDIV_EN (0x1UL<<CLK_FRQDIV_FDIV_EN_Pos) 237 #define CLK_WK_INTSTS_IS (0x1UL<<CLK_WK_INTSTS_PD_WK_IS_Pos) 240 #define CLK_MCLKO_MCLK_SEL_ISP_CLK (0x00<<CLK_MCLKO_MCLK_SEL_Pos) 241 #define CLK_MCLKO_MCLK_SEL_HIRC (0x01<<CLK_MCLKO_MCLK_SEL_Pos) 242 #define CLK_MCLKO_MCLK_SEL_HXT (0x02<<CLK_MCLKO_MCLK_SEL_Pos) 243 #define CLK_MCLKO_MCLK_SEL_LXT (0x03<<CLK_MCLKO_MCLK_SEL_Pos) 244 #define CLK_MCLKO_MCLK_SEL_LIRC (0x04<<CLK_MCLKO_MCLK_SEL_Pos) 245 #define CLK_MCLKO_MCLK_SEL_PLLO (0x05<<CLK_MCLKO_MCLK_SEL_Pos) 246 #define CLK_MCLKO_MCLK_SEL_PLLI (0x06<<CLK_MCLKO_MCLK_SEL_Pos) 247 #define CLK_MCLKO_MCLK_SEL_SYSTICK (0x07<<CLK_MCLKO_MCLK_SEL_Pos) 248 #define CLK_MCLKO_MCLK_SEL_HCLK (0x08<<CLK_MCLKO_MCLK_SEL_Pos) 249 #define CLK_MCLKO_MCLK_SEL_PCLK (0x0A<<CLK_MCLKO_MCLK_SEL_Pos) 250 #define CLK_MCLKO_MCLK_SEL_TMR0 (0x20<<CLK_MCLKO_MCLK_SEL_Pos) 251 #define CLK_MCLKO_MCLK_SEL_TMR1 (0x21<<CLK_MCLKO_MCLK_SEL_Pos) 252 #define CLK_MCLKO_MCLK_SEL_UART0 (0x22<<CLK_MCLKO_MCLK_SEL_Pos) 253 #define CLK_MCLKO_MCLK_SEL_USB (0x23<<CLK_MCLKO_MCLK_SEL_Pos) 254 #define CLK_MCLKO_MCLK_SEL_ADC (0x24<<CLK_MCLKO_MCLK_SEL_Pos) 255 #define CLK_MCLKO_MCLK_SEL_WDT (0x25<<CLK_MCLKO_MCLK_SEL_Pos) 256 #define CLK_MCLKO_MCLK_SEL_PWM0CH01 (0x26<<CLK_MCLKO_MCLK_SEL_Pos) 257 #define CLK_MCLKO_MCLK_SEL_PWM0CH23 (0x27<<CLK_MCLKO_MCLK_SEL_Pos) 258 #define CLK_MCLKO_MCLK_SEL_LCD (0x29<<CLK_MCLKO_MCLK_SEL_Pos) 259 #define CLK_MCLKO_MCLK_SEL_TMR2 (0x38<<CLK_MCLKO_MCLK_SEL_Pos) 260 #define CLK_MCLKO_MCLK_SEL_TMR3 (0x39<<CLK_MCLKO_MCLK_SEL_Pos) 261 #define CLK_MCLKO_MCLK_SEL_UART1 (0x3A<<CLK_MCLKO_MCLK_SEL_Pos) 262 #define CLK_MCLKO_MCLK_SEL_PWM1CH01 (0x3B<<CLK_MCLKO_MCLK_SEL_Pos) 263 #define CLK_MCLKO_MCLK_SEL_PWM1CH23 (0x3C<<CLK_MCLKO_MCLK_SEL_Pos) 264 #define CLK_MCLKO_MCLK_SEL_I2S (0x3D<<CLK_MCLKO_MCLK_SEL_Pos) 265 #define CLK_MCLKO_MCLK_SEL_SC0 (0x3E<<CLK_MCLKO_MCLK_SEL_Pos) 266 #define CLK_MCLKO_MCLK_SEL_SC1 (0x3F<<CLK_MCLKO_MCLK_SEL_Pos) 272 #define MODULE_APBCLK(x) ((x >>31) & 0x1) 273 #define MODULE_CLKSEL(x) ((x >>29) & 0x3) 274 #define MODULE_CLKSEL_Msk(x) ((x >>25) & 0xf) 275 #define MODULE_CLKSEL_Pos(x) ((x >>20) & 0x1f) 276 #define MODULE_CLKDIV(x) ((x >>18) & 0x3) 277 #define MODULE_CLKDIV_Msk(x) ((x >>10) & 0xff) 278 #define MODULE_CLKDIV_Pos(x) ((x >>5 ) & 0x1f) 279 #define MODULE_IP_EN_Pos(x) ((x >>0 ) & 0x1f) 280 #define MODULE_NoMsk 0x0 281 #define NA MODULE_NoMsk 283 #define MODULE_APBCLK_ENC(x) (((x) & 0x01) << 31) 284 #define MODULE_CLKSEL_ENC(x) (((x) & 0x03) << 29) 285 #define MODULE_CLKSEL_Msk_ENC(x) (((x) & 0x0f) << 25) 286 #define MODULE_CLKSEL_Pos_ENC(x) (((x) & 0x1f) << 20) 287 #define MODULE_CLKDIV_ENC(x) (((x) & 0x03) << 18) 288 #define MODULE_CLKDIV_Msk_ENC(x) (((x) & 0xff) << 10) 289 #define MODULE_CLKDIV_Pos_ENC(x) (((x) & 0x1f) << 5) 290 #define MODULE_IP_EN_Pos_ENC(x) (((x) & 0x1f) << 0) 294 #define TICK_MODULE ((0UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(1<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_TICK_EN_Pos ) 295 #define SRAM_MODULE ((0UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(1<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_SRAM_EN_Pos ) 296 #define EBI_MODULE ((0UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(1<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_EBI_EN_Pos ) 297 #define ISP_MODULE ((0UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(1<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_ISP_EN_Pos ) 298 #define DMA_MODULE ((0UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_DMA_EN_Pos ) 299 #define GPIO_MODULE ((0UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_GPIO_EN_Pos ) 301 #define SC2_MODULE ((1UL<<31)|(2<<29)|(3<<25) |(18<<20)|(1<<18)|(0xF<<10) |( 4<<5)|CLK_APBCLK_SC2_EN_Pos ) 302 #define SC1_MODULE ((1UL<<31)|(2<<29)|(3<<25) |(18<<20)|(1<<18)|(0xF<<10) |( 0<<5)|CLK_APBCLK_SC1_EN_Pos ) 303 #define SC0_MODULE ((1UL<<31)|(2<<29)|(3<<25) |(18<<20)|(0<<18)|(0xF<<10) |(28<<5)|CLK_APBCLK_SC0_EN_Pos ) 304 #define I2S_MODULE ((1UL<<31)|(2<<29)|(3<<25) |(16<<20)|(0<<18)|(0xF<<10) |(12<<5)|CLK_APBCLK_I2S_EN_Pos ) 305 #define ADC_MODULE ((1UL<<31)|(1<<29)|(3<<25) |( 2<<20)|(0<<18)|(0xFF<<10) |(16<<5)|CLK_APBCLK_ADC_EN_Pos ) 306 #define USBD_MODULE ((1UL<<31)|(1<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(0xF<<10) |( 4<<5)|CLK_APBCLK_USBD_EN_Pos ) 307 #define PWM1_CH23_MODULE ((1UL<<31)|(2<<29)|(3<<25) |( 6<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_PWM1_CH23_EN_Pos) 308 #define PWM1_CH01_MODULE ((1UL<<31)|(2<<29)|(3<<25) |( 4<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_PWM1_CH01_EN_Pos) 309 #define PWM0_CH23_MODULE ((1UL<<31)|(1<<29)|(3<<25) |( 6<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_PWM0_CH23_EN_Pos) 310 #define PWM0_CH01_MODULE ((1UL<<31)|(1<<29)|(3<<25) |( 4<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_PWM0_CH01_EN_Pos) 311 #define UART1_MODULE ((1UL<<31)|(1<<29)|(3<<25) |( 0<<20)|(0<<18)|(0xF<<10) |( 8<<5)|CLK_APBCLK_UART1_EN_Pos ) 312 #define UART0_MODULE ((1UL<<31)|(1<<29)|(3<<25) |( 0<<20)|(0<<18)|(0xF<<10) |( 8<<5)|CLK_APBCLK_UART0_EN_Pos ) 313 #define SPI2_MODULE ((1UL<<31)|(2<<29)|(1<<25) |(22<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_SPI2_EN_Pos ) 314 #define SPI1_MODULE ((1UL<<31)|(2<<29)|(1<<25) |(21<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_SPI1_EN_Pos ) 315 #define SPI0_MODULE ((1UL<<31)|(2<<29)|(1<<25) |(20<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_SPI0_EN_Pos ) 316 #define I2C1_MODULE ((1UL<<31)|(0<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_I2C1_EN_Pos ) 317 #define I2C0_MODULE ((1UL<<31)|(0<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_I2C0_EN_Pos ) 318 #define FDIV_MODULE ((1UL<<31)|(2<<29)|(3<<25) |( 2<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_FDIV_EN_Pos ) 319 #define TMR3_MODULE ((1UL<<31)|(2<<29)|(7<<25) |(12<<20)|(1<<18)|(0xF<<10) |(20<<5)|CLK_APBCLK_TMR3_EN_Pos ) 320 #define TMR2_MODULE ((1UL<<31)|(2<<29)|(7<<25) |( 8<<20)|(1<<18)|(0xF<<10) |(16<<5)|CLK_APBCLK_TMR2_EN_Pos ) 321 #define TMR1_MODULE ((1UL<<31)|(1<<29)|(7<<25) |(12<<20)|(1<<18)|(0xF<<10) |(12<<5)|CLK_APBCLK_TMR1_EN_Pos ) 322 #define TMR0_MODULE ((1UL<<31)|(1<<29)|(7<<25) |( 8<<20)|(1<<18)|(0xF<<10) |( 8<<5)|CLK_APBCLK_TMR0_EN_Pos ) 323 #define RTC_MODULE ((1UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_RTC_EN_Pos ) 324 #define WDT_MODULE ((1UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_WDT_EN_Pos ) 325 #define LCD_MODULE ((1UL<<31)|(1<<29)|(1<<25) |(18<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_LCD_EN_Pos ) 326 #define DAC_MODULE ((1UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_DAC_EN_Pos ) 343 void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv);
344 void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv);
349 uint32_t
CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq);
void CLK_DisableSysTick(void)
Disable System Tick counter.
void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count)
Enable System Tick counter.
uint32_t CLK_GetLXTFreq(void)
This function get external low frequency crystal frequency. The frequency unit is Hz.
void CLK_EnableModuleClock(uint32_t u32ModuleIdx)
This function enable module clock.
void CLK_SysTickDelay(uint32_t us)
This function execute delay function.
void CLK_DisableModuleClock(uint32_t u32ModuleIdx)
This function disable module clock.
uint32_t CLK_GetHCLKFreq(void)
This function get HCLK frequency. The frequency unit is Hz.
uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq)
This function set PLL frequency.
void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv)
This function set HCLK clock source and HCLK clock divider.
uint32_t CLK_GetHXTFreq(void)
This function get external high frequency crystal frequency. The frequency unit is Hz.
uint32_t CLK_SetCoreClock(uint32_t u32Hclk)
This function set HCLK frequency. The frequency unit is Hz. The range of u32Hclk is 24 ~ 42 MHz.
uint32_t CLK_WaitClockReady(uint32_t u32ClkMask)
This function check selected clock source status.
uint32_t CLK_GetPLLClockFreq(void)
This function get PLL frequency. The frequency unit is Hz.
void CLK_DisableXtalRC(uint32_t u32ClkMask)
This function disable clock source.
void CLK_Idle(void)
This function let system enter to Idle mode.
uint32_t CLK_GetCPUFreq(void)
This function get CPU frequency. The frequency unit is Hz.
void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv)
This function enable frequency divider module clock, enable frequency divider clock function and conf...
void CLK_DisablePLL(void)
This function disable PLL.
void CLK_EnableXtalRC(uint32_t u32ClkMask)
This function enable clock source.
void CLK_PowerDown(void)
This function let system enter to Power-down mode.
void CLK_DisableCKO(void)
This function disable frequency output function.
void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv)
This function set selected module clock source and module clock divider.