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Nano100BN Series BSP
V3.03.002
The Board Support Package for Nano100BN Series
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#include <Nano100Series.h>
Data Fields | |
| __IO uint32_t | PWRCTL |
| __IO uint32_t | AHBCLK |
| __IO uint32_t | APBCLK |
| __I uint32_t | CLKSTATUS |
| __IO uint32_t | CLKSEL0 |
| __IO uint32_t | CLKSEL1 |
| __IO uint32_t | CLKSEL2 |
| __IO uint32_t | CLKDIV0 |
| __IO uint32_t | CLKDIV1 |
| __IO uint32_t | PLLCTL |
| __IO uint32_t | FRQDIV |
| __IO uint32_t | MCLKO |
| __IO uint32_t | WK_INTSTS |
@addtogroup CLK System Clock Controller(CLK) Memory Mapped Structure for CLK Controller
Definition at line 714 of file Nano100Series.h.
| __IO uint32_t CLK_T::AHBCLK |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | GPIO_EN | GPIO Controller Clock Enable |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [1] | DMA_EN | DMA Controller Clock Enable |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [2] | ISP_EN | Flash ISP Controller Clock Enable |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [3] | EBI_EN | EBI Controller Clock Enable |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [4] | SRAM_EN | SRAM Controller Clock Enable |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [5] | TICK_EN | System Tick Clock Enable |
| 0 = Disabled. | ||
| 1 = Enabled. |
Definition at line 817 of file Nano100Series.h.
| __IO uint32_t CLK_T::APBCLK |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | WDT_EN | Watchdog Timer Clock Enable Control |
| This is a protected register. Please refer to open lock sequence to program it. | ||
| This bit is used to control the WDT APB clock only, The WDT engine Clock Source is from LIRC. | ||
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [1] | RTC_EN | Real-Time-Clock Clock Enable Control |
| This bit is used to control the RTC APB clock only, The RTC engine Clock Source is from LXT. | ||
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [2] | TMR0_EN | Timer0 Clock Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [3] | TMR1_EN | Timer1 Clock Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [4] | TMR2_EN | Timer2 Clock Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [5] | TMR3_EN | Timer3 Clock Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [6] | FDIV_EN | Frequency Divider Output Clock Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [7] | SC2_EN | SmartCard 2 Clock Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [8] | I2C0_EN | I2C0 Clock Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [9] | I2C1_EN | I2C1 Clock Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [12] | SPI0_EN | SPI0 Clock Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [13] | SPI1_EN | SPI1 Clock Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [14] | SPI2_EN | SPI2 Clock Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [16] | UART0_EN | UART0 Clock Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [17] | UART1_EN | UART1 Clock Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [20] | PWM0_CH01_EN | PWM0 Channel 0 And Channel 1Clock Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [21] | PWM0_CH23_EN | PWM0 Channel 2 And Channel 3 Clock Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [22] | PWM1_CH01_EN | PWM1 Channel 0 And Channel 1 Clock Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [23] | PWM1_CH23_EN | PWM1 Channel 2 And Channel 3 Clock Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [25] | DAC_EN | 12-Bit DAC Clock Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [26] | LCD_EN | LCD Controller Clock Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [27] | USBD_EN | USB FS Device Controller Clock Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [28] | ADC_EN | Analog-Digital-Converter (ADC) Clock Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [29] | I2S_EN | I2S Clock Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [30] | SC0_EN | SmartCard 0 Clock Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| [31] | SC1_EN | SmartCard 1 Clock Enable Control |
| 0 = Disabled. | ||
| 1 = Enabled. |
Definition at line 908 of file Nano100Series.h.
| __IO uint32_t CLK_T::CLKDIV0 |
| Bits | Field | Descriptions |
|---|---|---|
| [3:0] | HCLK_N | HCLK Clock Divide Number From HCLK Clock Source |
| The HCLK clock frequency = (HCLK Clock Source frequency) / (HCLK_N + 1). | ||
| [7:4] | USB_N | USB Clock Divide Number From PLL Clock |
| The USB clock frequency = (PLL frequency ) / (USB_N + 1). | ||
| [11:8] | UART_N | UART Clock Divide Number From UART Clock Source |
| The UART clock frequency = (UART Clock Source frequency ) / (UART_N + 1). | ||
| [15:12] | I2S_N | I2S Clock Divide Number From I2S Clock Source |
| The I2S clock frequency = (I2S Clock Source frequency ) / (I2S_N + 1). | ||
| [23:16] | ADC_N | ADC Clock Divide Number From ADC Clock Source |
| The ADC clock frequency = (ADC Clock Source frequency ) / (ADC_N + 1). | ||
| [31:28] | SC0_N | SC 0 Clock Divide Number From SC 0 Clock Source |
| The SC 0 clock frequency = (SC0 Clock Source frequency ) / (SC0_N + 1). |
Definition at line 1091 of file Nano100Series.h.
| __IO uint32_t CLK_T::CLKDIV1 |
| Bits | Field | Descriptions |
|---|---|---|
| [3:0] | SC1_N | SC 1 Clock Divide Number From SC 1 Clock Source |
| The SC 1 clock frequency = (SC 1 Clock Source frequency ) / (SC1_N + 1). | ||
| [7:4] | SC2_N | SC 2 Clock Divide Number From SC2 Clock Source |
| The SC 2 clock frequency = (SC 2 Clock Source frequency ) / (SC2_N + 1). |
Definition at line 1105 of file Nano100Series.h.
| __IO uint32_t CLK_T::CLKSEL0 |
| Bits | Field | Descriptions |
|---|---|---|
| [2:0] | HCLK_S | HCLK Clock Source Selection |
| This is a protected register. Please refer to open lock sequence to program it. | ||
| Note: | ||
| Before Clock Source switches, the related clock sources (pre-select and new-select) must be turn on | ||
| The 3-bit default value is reloaded with the value of CFOSC (Config0[26:24]) in user configuration register in Flash controller by any reset. | ||
| Therefore the default value is either 000b or 111b. | ||
| 000 = HXT | ||
| 001 = LXT | ||
| 010 = PLL Clock | ||
| 011 = LIRC | ||
| 111 = HIRC | ||
| Others = Reserved |
Definition at line 959 of file Nano100Series.h.
| __IO uint32_t CLK_T::CLKSEL1 |
| Bits | Field | Descriptions |
|---|---|---|
| [1:0] | UART_S | UART 0/1 Clock Source Selection (UART0 And UART1 Use The Same Clock Source Selection) |
| 00 = HXT | ||
| 01 = LXT | ||
| 10 = PLL Clock | ||
| 11 = HIRC | ||
| [3:2] | ADC_S | ADC Clock Source Selection |
| 00 = HXT | ||
| 01 = LXT | ||
| 10 = PLL Clock | ||
| 11 = HIRC | ||
| [5:4] | PWM0_CH01_S | PWM0 Channel 0 And Channel 1 Clock Source Selection |
| PWM0 channel 0 and channel 1 use the same Engine clock source, both of them with the same prescaler | ||
| 00 = HXT | ||
| 01 = LXT | ||
| 10 = HCLK | ||
| 11 = HIRC | ||
| [7:6] | PWM0_CH23_S | PWM0 Channel 2 And Channel 3 Clock Source Selection |
| PWM0 channel 2 and channel 3 use the same Engine clock source, both of them with the same prescaler | ||
| 00 = HXT | ||
| 01 = LXT | ||
| 10 = HCLK | ||
| 11 = HIRC | ||
| [10:8] | TMR0_S | Timer0 Clock Source Selection |
| 000 = HXT | ||
| 001 = LXT | ||
| 010 = LIRC | ||
| 011 = External Pin | ||
| 111 = HIRC | ||
| Others = Reserved | ||
| [14:12] | TMR1_S | Timer1 Clock Source Selection |
| 000 = HXT | ||
| 001 = LXT | ||
| 010 = LIRC | ||
| 011 = External Pin | ||
| 111 = HIRC | ||
| Others = Reserved | ||
| [18] | LCD_S | LCD Clock Source Selection |
| 0 = Clock Source from LXT. | ||
| 1 = Reserved. |
Definition at line 1008 of file Nano100Series.h.
| __IO uint32_t CLK_T::CLKSEL2 |
| Bits | Field | Descriptions |
|---|---|---|
| [3:2] | FRQDIV_S | Clock Divider Clock Source Selection |
| 00 = HXT | ||
| 01 = LXT | ||
| 10 = HCLK | ||
| 11 = HIRC | ||
| [5:4] | PWM1_CH01_S | PWM1 Channel 0 And Channel 1 Clock Source Selection |
| PWM1 channel 0 and channel 1 use the same Engine clock source, both of them with the same pre-scale | ||
| 00 = HXT | ||
| 01 = LXT | ||
| 10 = HCLK | ||
| 11 = HIRC | ||
| [7:6] | PWM1_CH23_S | PWM1 Channel 2 And Channel 2 Clock Source Selection |
| PWM1 channel 2 and channel 3 use the same Engine clock source, both of them with the same pre-scale | ||
| 00 = HXT | ||
| 01 = LXT | ||
| 10 = HCLK | ||
| 11 = HIRC | ||
| [10:8] | TMR2_S | Timer2 Clock Source Selection |
| 000 = HXT | ||
| 001 = LXT | ||
| 010 = LIRC | ||
| 011 = External Pin | ||
| 111 = HIRC | ||
| Others = Reserved | ||
| [14:12] | TMR3_S | Timer3 Clock Source Selection |
| 000 = HXT | ||
| 001 = LXT | ||
| 010 = LIRC | ||
| 011 = External Pin | ||
| 111 = HIRC | ||
| Others = Reserved | ||
| [17:16] | I2S_S | I2S Clock Source Selection |
| 00 = HXT | ||
| 01 = PLL Clock | ||
| 10 = HIRC | ||
| 11 = HIRC | ||
| [19:18] | SC_S | SC Clock Source Selection |
| 00 = HXT | ||
| 01 = PLL Clock | ||
| 10 = HIRC | ||
| 11 = HIRC | ||
| Note: SC0,SC1 and SC2 use the same Clock Source selection but they have different clock divider number. | ||
| [20] | SPI0_S | SPI0 Clock Source Selection |
| 0 = PLL. | ||
| 1 = HCLK. | ||
| [21] | SPI1_S | SPI1 Clock Source Selection |
| 0 = PLL. | ||
| 1 = HCLK. | ||
| [22] | SPI2_S | SPI2 Clock Source Selection |
| 0 = PLL. | ||
| 1 = HCLK. |
Definition at line 1069 of file Nano100Series.h.
| __I uint32_t CLK_T::CLKSTATUS |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | HXT_STB | HXT Clock Source Stable Flag |
| 0 = HXT clock is not stable or not enable. | ||
| 1 = HXT clock is stable. | ||
| [1] | LXT_STB | LXT Clock Source Stable Flag |
| 0 = LXT clock is not stable or not enable. | ||
| 1 = LXT clock is stable. | ||
| [2] | PLL_STB | PLL Clock Source Stable Flag |
| 0 = PLL clock is not stable or not enable. | ||
| 1 = PLL clock is stable. | ||
| [3] | LIRC_STB | LIRC Clock Source Stable Flag |
| 0 = LIRC clock is not stable or not enable. | ||
| 1 = LIRC clock is stable. | ||
| [4] | HIRC_STB | HIRC Clock Source Stable Flag |
| 0 = HIRC clock is not stable or not enable. | ||
| 1 = HIRC clock is stable. | ||
| [7] | CLK_SW_FAIL | Clock Switch Fail Flag |
| 0 = Clock switch success. | ||
| 1 = Clock switch fail. | ||
| This bit will be set when target switch Clock Source is not stable. This bit is write 1 clear |
Definition at line 937 of file Nano100Series.h.
| __IO uint32_t CLK_T::FRQDIV |
| Bits | Field | Descriptions |
|---|---|---|
| [3:0] | FSEL | Divider Output Frequency Selection Bits |
| The formula of output frequency is | ||
| Fout = Fin/2^(N+1),. | ||
| Where Fin is the input clock frequency, Fout is the frequency of divider output clock and N is the 4-bit value of FSEL[3:0]. | ||
| [4] | FDIV_EN | Frequency Divider Enable Bit |
| 0 = Frequency Divider Disabled. | ||
| 1 = Frequency Divider Enabled. |
Definition at line 1146 of file Nano100Series.h.
| __IO uint32_t CLK_T::MCLKO |
| Bits | Field | Descriptions |
|---|---|---|
| [5:0] | MCLK_SEL | Module Clock Output Source Selection (PC.0) |
| 000000 = ISP_CLK | ||
| 000001 = HIRC | ||
| 000010 = HXT | ||
| 000011 = LXT | ||
| 000100 = LIRC | ||
| 000101 = PLL output | ||
| 000110 = PLL input | ||
| 000111 = System Tick | ||
| 001000 = HCLK clock | ||
| 001010 = PCLK clock | ||
| 100000 = TMR0_CLK | ||
| 100001 = TMR1_CLK | ||
| 100010 = UART0_CLK | ||
| 100011 = USB_CLK | ||
| 100100 = ADC_CLK | ||
| 100101 = WDT_CLK | ||
| 100110 = PWM0_CH01_CLK | ||
| 100111 = PWM0_CH32_CLK | ||
| 101001 = LCD_CLK | ||
| 111000 = TMR2_CLK | ||
| 111001 = TMR3_CLK | ||
| 111010 = UART1_CLK | ||
| 111011 = PWM1_CH01_CLK | ||
| 111100 = PWM1_CH23_CLK | ||
| 111101 = I²S_CLK | ||
| 111110 = SC0_CLK | ||
| 111111 = SC1_CLK | ||
| [7] | MCLK_EN | Module Clock Output Enable |
| User can get the module clock output from PC.0 pin via choosing the clock source in the MCLK_SEL bit field and then setting MCLK_EN bit to 1. | ||
| 0 = Module clock output Disabled. | ||
| 1 = Module clock output Enabled. | ||
| Note: If this bit is enabled, PC.0 will be configured to module clock output and the setting of PC0_MFP will be ineffective |
Definition at line 1189 of file Nano100Series.h.
| __IO uint32_t CLK_T::PLLCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [4:0] | FB_DV | PLL Feedback Divider Control Pins |
| Refer to the formulas below the table. | ||
| The range of FB_DV is from 0 to 63. | ||
| [9:8] | IN_DV | PLL Input Divider Control Pins |
| Refer to the formulas below the table. | ||
| [12] | OUT_DV | PLL Output Divider Control Pins |
| Refer to the formulas below the table. This bit MUST be 0 for PLL output low deviation. | ||
| [16] | PD | Power-Down Mode |
| If set the PD_EN bit "1" in PWR_CTL register, the PLL will enter Power-down mode too | ||
| 0 = PLL is in normal mode. | ||
| 1 = PLL is in power-down mode (default). | ||
| [17] | PLL_SRC | PLL Source Clock Select |
| 0 = PLL source clock from HXT. | ||
| 1 = PLL source clock from HIRC. |
Definition at line 1129 of file Nano100Series.h.
| __IO uint32_t CLK_T::PWRCTL |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | HXT_EN | HXT Control |
| This is a protected register. Please refer to open lock sequence to program it. | ||
| The bit default value is set by flash controller user configuration register config0 [26]. | ||
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| HXT is disabled by default. | ||
| [1] | LXT_EN | LXT Control |
| This is a protected register. Please refer to open lock sequence to program it. | ||
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| LXT is disabled by default. | ||
| [2] | HIRC_EN | HIRC Control |
| This is a protected register. Please refer to open lock sequence to program it. | ||
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| HIRC is enabled by default. | ||
| [3] | LIRC_EN | LIRC Control |
| This is a protected register. Please refer to open lock sequence to program it. | ||
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| LIRC is enabled by default. | ||
| [4] | WK_DLY | Wake-Up Delay Counter Enable |
| This is a protected register. Please refer to open lock sequence to program it. | ||
| When chip wakes up from Power-down mode, the clock control will delay 4096 clock cycles to wait HXT stable or 16 clock cycles to wait HIRC stable. | ||
| 0 = Delay clock cycle Disabled. | ||
| 1 = Delay clock cycle Enabled. | ||
| [5] | PD_WK_IE | Power-Down Mode Wake-Up Interrupt Enable |
| This is a protected register. Please refer to open lock sequence to program it. | ||
| 0 = Disabled. | ||
| 1 = Enabled. | ||
| PD_WK_INT will be set if both PD_WK_IS and PD_WK_IE are high. | ||
| [6] | PD_EN | Chip Power-Down Mode Enable Bit |
| This is a protected register. Please refer to open lock sequence to program it. | ||
| When CPU sets this bit, the chip power down is enabled and chip will not enter Power-down mode until CPU sleep mode is also active | ||
| When chip wakes up from Power-down mode, this bit will be auto cleared. | ||
| When chip is in Power-down mode, the LDO, HXT and HIRC will be disabled, but LXT and LIRC are not controlled by Power-down mode. | ||
| When power down, the PLL and system clock (CPU, HCLKx and PCLKx) are also disabled no matter the Clock Source selection. | ||
| Peripheral clocks are not controlled by this bit, if peripheral Clock Source is from LXT or LIRC. | ||
| In Power-down mode, flash macro power is ON. | ||
| 0 = Chip operated in Normal mode. | ||
| 1 = Chip power down Enabled. | ||
| [8] | HXT_SELXT | HXT SELXT |
| This is a protected register. Please refer to open lock sequence to program it. | ||
| 0 = High frequency crystal loop back path Disabled. It is used for external oscillator. | ||
| 1 = High frequency crystal loop back path Enabled. It is used for external crystal. | ||
| [9] | HXT_GAIN | HXT Gain Control Bit |
| This is a protected register. Please refer to open lock sequence to program it. | ||
| Gain control is used to enlarge the gain of crystal to make sure crystal wok normally. | ||
| If gain control is enabled, crystal will consume more power than gain control off. | ||
| 0 = Gain control Disabled. It means HXT gain is always high. | ||
| For 16MHz to 24MHz crystal. | ||
| 1 = Gain control Enabled. HXT gain will be high lasting 2ms then low. This is for power saving. | ||
| For 4MHz to 16MHz crystal. | ||
| [10] | LXT_SCNT | LXT Stable Time Control |
| This is a protected register. Please refer to open lock sequence to program it. | ||
| 0 = Delay 4096 LXT before LXT output. | ||
| 1 = Delay 8192 LXT before LXT output. | ||
| [12:11] | HXT_HF_ST | HXT Frequency Selection |
| Set this bit to meet HXT frequency selection (Recommended) | ||
| 00 = HXT frequency is from 4 MHz to 12 MHz. | ||
| 01 = HXT frequency is from 12 MHz to 16 MHz. | ||
| 10 = HXT frequency is from 16 MHz to 24 MHz. | ||
| 11 = Reserved. |
Definition at line 789 of file Nano100Series.h.
| __IO uint32_t CLK_T::WK_INTSTS |
| Bits | Field | Descriptions |
|---|---|---|
| [0] | PD_WK_IS | Wake-Up Interrupt Status In Chip Power-Down Mode |
| This bit indicates that some event resumes chip from Power-down mode | ||
| The status is set if external interrupts, UART, GPIO, RTC, USB, SPI, Timer, WDT, and BOD wake-up occurred. | ||
| Write 1 to clear this bit. |
Definition at line 1203 of file Nano100Series.h.
1.8.15