Nano100BN Series BSP  V3.03.002
The Board Support Package for Nano100BN Series
Data Fields
DAC_T Struct Reference

#include <Nano100Series.h>

Data Fields

__IO uint32_t CTL0
 
__IO uint32_t DATA0
 
__IO uint32_t STS0
 
uint32_t RESERVE0 [1]
 
__IO uint32_t CTL1
 
__IO uint32_t DATA1
 
__IO uint32_t STS1
 
uint32_t RESERVE1 [1]
 
__IO uint32_t COMCTL
 

Detailed Description

@addtogroup DAC Digital to Analog Converter(DAC)
Memory Mapped Structure for DAC Controller

Definition at line 1477 of file Nano100Series.h.

Field Documentation

◆ COMCTL

__IO uint32_t DAC_T::COMCTL

COMCTL

Offset: 0x20 DAC01 Common Control Register

Bits Field Descriptions
[7:0] WAITDACCONV Wait DAC Conversion Complete
The DAC needs at least 2 us to settle down every time when each data deliver to DAC, which means user cannot update each DACx_data register faster than 2 us; otherwise data will lost.
Setting this register can adjust the time interval in PCLK unit between each DACx_data into DAC in order to meet the 2 us requirement.
[8] DAC01GRP Group DAC0 And DAC1
0 = Not grouped.
1 = Grouped.
[10:9] REFSEL Reference Voltage Selection
00 = AVDD
01 = Internal reference voltage
10 = External reference voltage
11= Reserved

Definition at line 1626 of file Nano100Series.h.

◆ CTL0

__IO uint32_t DAC_T::CTL0

CTL0

Offset: 0x00 DAC0 Control Register

Bits Field Descriptions
[0] DACEN DAC Enable
0 = Power down DAC.
1 = Power on DAC.
Note: When DAC is powered on, DAC will automatically start conversion after waiting for DACPWONSTBCNT+1 PCLK cycle
[1] DACIE DAC Interrupt Enable
0 = Disabled.
1 = Enabled.
[6:4] DACLSEL DAC Load Selection
Select the load trigger for the DAC latch.
000 = DAC latch loads when DACx_DAT written
001 = PDMA ACK
010 = Rising edge of TMR0
011 = Rising edge of TMR1
100 = Rising edge of TMR2
101 = Rising edge of TMR3
Others = Reserved
[21:8] DACPWONSTBCNT DACPWONSTBCNT
DAC need 6 us to be stable after DAC is power on from power down state.
This field controls a internal counter (in PCLK unit) to guarantee DAC stable time requirement.

Definition at line 1508 of file Nano100Series.h.

◆ CTL1

__IO uint32_t DAC_T::CTL1

CTL1

Offset: 0x10 DAC1 Control Register

Bits Field Descriptions
[0] DACEN DAC Enable
0 = Power down DAC.
1 = Power on DAC.
Note: When DAC is powered on, DAC will automatically start conversion after waiting for DACPWONSTBCNT+1 PCLK cycle
[1] DACIE DAC Interrupt Enable
0 = Disabled.
1 = Enabled.
[6:4] DACLSEL DAC Load Selection
Select the load trigger for the DAC latch.
000 = DAC latch loads when DACx_DAT written
001 = PDMA ACK
010 = Rising edge of TMR0
011 = Rising edge of TMR1
100 = Rising edge of TMR2
101 = Rising edge of TMR3
Others = Reserved
[21:8] DACPWONSTBCNT DACPWONSTBCNT
DAC need 6 us to be stable after DAC is power on from power down state.
This field controls a internal counter (in PCLK unit) to guarantee DAC stable time requirement.

Definition at line 1571 of file Nano100Series.h.

◆ DATA0

__IO uint32_t DAC_T::DATA0

DATA0

Offset: 0x04 DAC0 Data Register

Bits Field Descriptions
[11:0] DACData DAC data

Definition at line 1519 of file Nano100Series.h.

◆ DATA1

__IO uint32_t DAC_T::DATA1

DATA1

Offset: 0x14 DAC1 Data Register

Bits Field Descriptions
[11:0] DACData DAC data

Definition at line 1582 of file Nano100Series.h.

◆ RESERVE0

uint32_t DAC_T::RESERVE0[1]

Definition at line 1541 of file Nano100Series.h.

◆ RESERVE1

uint32_t DAC_T::RESERVE1[1]

Definition at line 1604 of file Nano100Series.h.

◆ STS0

__IO uint32_t DAC_T::STS0

STS0

Offset: 0x08 DAC0 Status Register

Bits Field Descriptions
[0] DACIFG DAC Interrupt Flag
0 = No interrupt pending.
1 = Interrupt pending.
Note: This bit is read only.
[1] DACSTFG DAC Start Flag
0 = DAC is not start yet.
1 = DAC has been started.
Note: this bit is read only.
[2] BUSY BUSY Bit
0 = DAC is not busy.
1 = DAC is busy.

Definition at line 1540 of file Nano100Series.h.

◆ STS1

__IO uint32_t DAC_T::STS1

STS1

Offset: 0x18 DAC1 Status Register

Bits Field Descriptions
[0] DACIFG DAC Interrupt Flag
0 = No interrupt pending.
1 = Interrupt pending.
Note: This bit is read only.
[1] DACSTFG DAC Start Flag
0 = DAC is not start yet.
1 = DAC has been started.
Note: this bit is read only.
[2] BUSY BUSY Bit
0 = DAC is not busy.
1 = DAC is busy.

Definition at line 1603 of file Nano100Series.h.


The documentation for this struct was generated from the following file: