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Nano100BN Series BSP
V3.03.002
The Board Support Package for Nano100BN Series
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Macros | |
| #define | __CM0_REV 0x0201 |
| #define | __NVIC_PRIO_BITS 2 |
| #define | __Vendor_SysTickConfig 0 |
| #define | __MPU_PRESENT 0 |
| #define | __FPU_PRESENT 0 |
Typedefs | |
| typedef enum IRQn | IRQn_Type |
Enumerations | |
| enum | IRQn { NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, SVCall_IRQn = -5, PendSV_IRQn = -2, SysTick_IRQn = -1, BOD_IRQn = 0, WDT_IRQn = 1, EINT0_IRQn = 2, EINT1_IRQn = 3, GPABC_IRQn = 4, GPDEF_IRQn = 5, PWM0_IRQn = 6, PWM1_IRQn = 7, TMR0_IRQn = 8, TMR1_IRQn = 9, TMR2_IRQn = 10, TMR3_IRQn = 11, UART0_IRQn = 12, UART1_IRQn = 13, SPI0_IRQn = 14, SPI1_IRQn = 15, SPI2_IRQn = 16, HIRC_IRQn = 17, I2C0_IRQn = 18, I2C1_IRQn = 19, SC2_IRQn = 20, SC0_IRQn = 21, SC1_IRQn = 22, USBD_IRQn = 23, LCD_IRQn = 25, PDMA_IRQn = 26, I2S_IRQn = 27, PDWU_IRQn = 28, ADC_IRQn = 29, DAC_IRQn = 30, RTC_IRQn = 31 } |
Configuration of the Cortex-M0 Processor and Core Peripherals
| #define __CM0_REV 0x0201 |
Core Revision r2p1
Definition at line 131 of file Nano100Series.h.
| #define __FPU_PRESENT 0 |
FPU present or not
Definition at line 135 of file Nano100Series.h.
| #define __MPU_PRESENT 0 |
MPU present or not
Definition at line 134 of file Nano100Series.h.
| #define __NVIC_PRIO_BITS 2 |
Number of Bits used for Priority Levels
Definition at line 132 of file Nano100Series.h.
| #define __Vendor_SysTickConfig 0 |
Set to 1 if different SysTick Config is used
Definition at line 133 of file Nano100Series.h.
Interrupt Number Definition. The maximum of 32 Specific Interrupts are possible.
| enum IRQn |
Interrupt Number Definition. The maximum of 32 Specific Interrupts are possible.
Definition at line 79 of file Nano100Series.h.
1.8.15