Nano100BN Series BSP  V3.03.002
The Board Support Package for Nano100BN Series
NuEdu-Basic01_UART.c
Go to the documentation of this file.
1 /**************************************************************************/
13 #include <stdio.h>
14 #include "Nano100Series.h"
15 #include "NuEdu-Basic01_UART.h"
16 
34 void UART0_Init(void)
35 {
36  /* Enable IP clock */
38 
39  /* Select IP clock source */
41 
42  /* Set PA multi-function pins for UART0 RXD and TXD */
45 
47 
48  /* Configure UART0 and set UART0 Baudrate */
49  //UART_Open(UART0, 115200);
50 
51  CLK->CLKSEL1 = (CLK->CLKSEL1 & ~CLK_CLKSEL1_UART_S_Msk) | CLK_CLKSEL1_UART_S_HXT; /* Select 12 Mhz XTAL */
52 
53  UART0->BAUD = 0x67; /* Baud Rate:115200 OSC:12MHz */
54  UART0->TLCTL = 0x03; /* Character len is 8 bits */
55 
56 }
57  /* end of group Nano130_Basic01_FUNCTIONS */
59  /* end of group NuEdu-SDK-Nano130_Basic01 */
61  /* end of group NANO100_Library */
63 
64 /*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
NuEdu-Basic01 UART driver header file.
void CLK_EnableModuleClock(uint32_t u32ModuleIdx)
This function enable module clock.
Definition: clk.c:436
#define CLK
Pointer to CLK register structure.
#define SYS_PB_L_MFP_PB0_MFP_UART0_RX
Definition: sys.h:260
#define CLK_CLKSEL1_UART_S_Msk
Nano100 series peripheral access layer header file. This file contains all the peripheral register's ...
#define CLK_CLKSEL1_UART_S_HXT
Definition: clk.h:137
#define UART0
Pointer to UART0 register structure.
#define SYS_PB_L_MFP_PB0_MFP_Msk
void UART0_Init(void)
Initiate UART0 as 8-N-1 and 115200 BPS.
#define SYS_PB_L_MFP_PB1_MFP_Msk
#define UART0_MODULE
Definition: clk.h:312
#define SYS_PB_L_MFP_PB1_MFP_UART0_TX
Definition: sys.h:254
#define CLK_UART_CLK_DIVIDER(x)
Definition: clk.h:190
void SYS_ResetModule(uint32_t u32ModuleIndex)
This function reset selected modules.
Definition: sys.c:129
#define CLK_CLKSEL1_UART_S_HIRC
Definition: clk.h:140
#define UART0_RST
Definition: sys.h:48
void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv)
This function set selected module clock source and module clock divider.
Definition: clk.c:339
#define SYS
Pointer to SYS register structure.