| Nano100BN Series BSP V3.03.002 The Board Support Package for Nano100BN Series

Nano100Series.h
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1 /**************************************************************************/
51 #ifndef __NANO100SERIES_H__
52 #define __NANO100SERIES_H__
53
54 #ifdef __cplusplus
55 extern "C" {
56 #endif
57
68 /******************************************************************************/
69 /* Processor and Core Peripherals */
70 /******************************************************************************/
79 typedef enum IRQn
80 {
81 /****** Cortex-M0 Processor Exceptions Numbers *****************************************/
82
83 NonMaskableInt_IRQn = -14,
84 HardFault_IRQn = -13,
85 SVCall_IRQn = -5,
86 PendSV_IRQn = -2,
87 SysTick_IRQn = -1,
89 /****** Nano100 specific Interrupt Numbers ***********************************************/
90 BOD_IRQn = 0,
91 WDT_IRQn = 1,
92 EINT0_IRQn = 2,
93 EINT1_IRQn = 3,
94 GPABC_IRQn = 4,
95 GPDEF_IRQn = 5,
96 PWM0_IRQn = 6,
97 PWM1_IRQn = 7,
98 TMR0_IRQn = 8,
99 TMR1_IRQn = 9,
100 TMR2_IRQn = 10,
101 TMR3_IRQn = 11,
102 UART0_IRQn = 12,
103 UART1_IRQn = 13,
104 SPI0_IRQn = 14,
105 SPI1_IRQn = 15,
106 SPI2_IRQn = 16,
107 HIRC_IRQn = 17,
108 I2C0_IRQn = 18,
109 I2C1_IRQn = 19,
110 SC2_IRQn = 20,
111 SC0_IRQn = 21,
112 SC1_IRQn = 22,
113 USBD_IRQn = 23,
114 LCD_IRQn = 25,
115 PDMA_IRQn = 26,
116 I2S_IRQn = 27,
117 PDWU_IRQn = 28,
118 ADC_IRQn = 29,
119 DAC_IRQn = 30,
120 RTC_IRQn = 31
121 } IRQn_Type;
122
123
124 /*
125 * ==========================================================================
126 * ----------- Processor and Core Peripheral Section ------------------------
127 * ==========================================================================
128 */
129
130 /* Configuration of the Cortex-M0 Processor and Core Peripherals */
131 #define __CM0_REV 0x0201
132 #define __NVIC_PRIO_BITS 2
133 #define __Vendor_SysTickConfig 0
134 #define __MPU_PRESENT 0
135 #define __FPU_PRESENT 0
137 /* end of group NANO100_CMSIS */
138
139
140 #include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
141 #include "system_Nano100Series.h" /* Nano100 Series System include file */
142 #include <stdint.h>
143
144 /******************************************************************************/
145 /* Device Specific Peripheral registers structures */
146 /******************************************************************************/
152 #if defined ( __CC_ARM )
153 #pragma anon_unions
154 #endif
155
156
157
158 /*---------------------- Analog to Digital Converter -------------------------*/
164 typedef struct
165 {
166
167
182 __I uint32_t RESULT[18];
183
184
267 __IO uint32_t CR;
268
332 __IO uint32_t CHEN;
333
363 __IO uint32_t CMPR0;
364
394 __IO uint32_t CMPR1;
395
437 __IO uint32_t SR;
438 uint32_t RESERVE0[1];
439
440
452 __I uint32_t PDMA;
453
475 __IO uint32_t PWRCTL;
476
499 __IO uint32_t CALCTL;
500
513 __IO uint32_t CALWORD;
514
550 __IO uint32_t SMPLCNT0;
551
570 __IO uint32_t SMPLCNT1;
571
572 } ADC_T;
573
578 #define ADC_RESULT_RSLT_Pos (0)
579 #define ADC_RESULT_RSLT_Msk (0xffful << ADC_RESULT_RSLT_Pos)
581 #define ADC_RESULT_VALID_Pos (16)
582 #define ADC_RESULT_VALID_Msk (0x1ul << ADC_RESULT_VALID_Pos)
584 #define ADC_RESULT_OVERRUN_Pos (17)
585 #define ADC_RESULT_OVERRUN_Msk (0x1ul << ADC_RESULT_OVERRUN_Pos)
587 #define ADC_CR_ADEN_Pos (0)
588 #define ADC_CR_ADEN_Msk (0x1ul << ADC_CR_ADEN_Pos)
590 #define ADC_CR_ADIE_Pos (1)
591 #define ADC_CR_ADIE_Msk (0x1ul << ADC_CR_ADIE_Pos)
593 #define ADC_CR_ADMD_Pos (2)
594 #define ADC_CR_ADMD_Msk (0x3ul << ADC_CR_ADMD_Pos)
596 #define ADC_CR_TRGS_Pos (4)
597 #define ADC_CR_TRGS_Msk (0x3ul << ADC_CR_TRGS_Pos)
599 #define ADC_CR_TRGCOND_Pos (6)
600 #define ADC_CR_TRGCOND_Msk (0x3ul << ADC_CR_TRGCOND_Pos)
602 #define ADC_CR_TRGE_Pos (8)
603 #define ADC_CR_TRGE_Msk (0x1ul << ADC_CR_TRGE_Pos)
605 #define ADC_CR_PTEN_Pos (9)
606 #define ADC_CR_PTEN_Msk (0x1ul << ADC_CR_PTEN_Pos)
608 #define ADC_CR_DIFF_Pos (10)
609 #define ADC_CR_DIFF_Msk (0x1ul << ADC_CR_DIFF_Pos)
611 #define ADC_CR_ADST_Pos (11)
612 #define ADC_CR_ADST_Msk (0x1ul << ADC_CR_ADST_Pos)
614 #define ADC_CR_TMSEL_Pos (12)
615 #define ADC_CR_TMSEL_Msk (0x3ul << ADC_CR_TMSEL_Pos)
617 #define ADC_CR_TMTRGMOD_Pos (15)
618 #define ADC_CR_TMTRGMOD_Msk (0x1ul << ADC_CR_TMTRGMOD_Pos)
620 #define ADC_CR_REFSEL_Pos (16)
621 #define ADC_CR_REFSEL_Msk (0x3ul << ADC_CR_REFSEL_Pos)
623 #define ADC_CR_RESSEL_Pos (18)
624 #define ADC_CR_RESSEL_Msk (0x3ul << ADC_CR_RESSEL_Pos)
626 #define ADC_CR_TMPDMACNT_Pos (24)
627 #define ADC_CR_TMPDMACNT_Msk (0xfful << ADC_CR_TMPDMACNT_Pos)
629 #define ADC_CHEN_CHEN0_Pos (0)
630 #define ADC_CHEN_CHEN0_Msk (0x1ul << ADC_CHEN_CHEN0_Pos)
632 #define ADC_CMPR_CMPEN_Pos (0)
633 #define ADC_CMPR_CMPEN_Msk (0x1ul << ADC_CMPR_CMPEN_Pos)
635 #define ADC_CMPR_CMPIE_Pos (1)
636 #define ADC_CMPR_CMPIE_Msk (0x1ul << ADC_CMPR_CMPIE_Pos)
638 #define ADC_CMPR_CMPCOND_Pos (2)
639 #define ADC_CMPR_CMPCOND_Msk (0x1ul << ADC_CMPR_CMPCOND_Pos)
641 #define ADC_CMPR_CMPCH_Pos (3)
642 #define ADC_CMPR_CMPCH_Msk (0x1ful << ADC_CMPR_CMPCH_Pos)
644 #define ADC_CMPR_CMPMATCNT_Pos (8)
645 #define ADC_CMPR_CMPMATCNT_Msk (0xful << ADC_CMPR_CMPMATCNT_Pos)
647 #define ADC_CMPR_CMPD_Pos (16)
648 #define ADC_CMPR_CMPD_Msk (0xffful << ADC_CMPR_CMPD_Pos)
650 #define ADC_SR_ADF_Pos (0)
651 #define ADC_SR_ADF_Msk (0x1ul << ADC_SR_ADF_Pos)
653 #define ADC_SR_CMPF0_Pos (1)
654 #define ADC_SR_CMPF0_Msk (0x1ul << ADC_SR_CMPF0_Pos)
656 #define ADC_SR_CMPF1_Pos (2)
657 #define ADC_SR_CMPF1_Msk (0x1ul << ADC_SR_CMPF1_Pos)
659 #define ADC_SR_BUSY_Pos (3)
660 #define ADC_SR_BUSY_Msk (0x1ul << ADC_SR_BUSY_Pos)
662 #define ADC_SR_CHANNEL_Pos (4)
663 #define ADC_SR_CHANNEL_Msk (0x1ful << ADC_SR_CHANNEL_Pos)
665 #define ADC_SR_INITRDY_Pos (16)
666 #define ADC_SR_INITRDY_Msk (0x1ul << ADC_SR_INITRDY_Pos)
668 #define ADC_PDMA_AD_PDMA_Pos (0)
669 #define ADC_PDMA_AD_PDMA_Msk (0xffful << ADC_PDMA_AD_PDMA_Pos)
671 #define ADC_PWRCTL_PWUPRDY_Pos (0)
672 #define ADC_PWRCTL_PWUPRDY_Msk (0x1ul << ADC_PWRCTL_PWUPRDY_Pos)
674 #define ADC_PWRCTL_PWDCALEN_Pos (1)
675 #define ADC_PWRCTL_PWDCALEN_Msk (0x1ul << ADC_PWRCTL_PWDCALEN_Pos)
677 #define ADC_PWRCTL_PWDMOD_Pos (2)
678 #define ADC_PWRCTL_PWDMOD_Msk (0x3ul << ADC_PWRCTL_PWDMOD_Pos)
680 #define ADC_CALCTL_CALEN_Pos (0)
681 #define ADC_CALCTL_CALEN_Msk (0x1ul << ADC_CALCTL_CALEN_Pos)
683 #define ADC_CALCTL_CALSTART_Pos (1)
684 #define ADC_CALCTL_CALSTART_Msk (0x1ul << ADC_CALCTL_CALSTART_Pos)
686 #define ADC_CALCTL_CALDONE_Pos (2)
687 #define ADC_CALCTL_CALDONE_Msk (0x1ul << ADC_CALCTL_CALDONE_Pos)
689 #define ADC_CALCTL_CALSEL_Pos (3)
690 #define ADC_CALCTL_CALSEL_Msk (0x1ul << ADC_CALCTL_CALSEL_Pos)
692 #define ADC_CALWORD_CALWORD_Pos (0)
693 #define ADC_CALWORD_CALWORD_Msk (0x7ful << ADC_CALWORD_CALWORD_Pos)
695 #define ADC_SMPLCNT0_CH0SAMPCNT_Pos (0)
696 #define ADC_SMPLCNT0_CH0SAMPCNT_Msk (0xful << ADC_SMPLCNT0_CH0SAMPCNT_Pos)
698 #define ADC_SMPLCNT1_CH8SAMPCNT_Pos (0)
699 #define ADC_SMPLCNT1_CH8SAMPCNT_Msk (0xful << ADC_SMPLCNT1_CH8SAMPCNT_Pos)
701 #define ADC_SMPLCNT1_INTCHSAMPCNT_Pos (16)
702 #define ADC_SMPLCNT1_INTCHSAMPCNT_Msk (0xful << ADC_SMPLCNT1_INTCHSAMPCNT_Pos) /* ADC_CONST */
705 /* end of ADC register group */
706
707
708 /*---------------------- System Clock Controller -------------------------*/
714 typedef struct
715 {
716
717
789 __IO uint32_t PWRCTL;
790
817 __IO uint32_t AHBCLK;
818
908 __IO uint32_t APBCLK;
909
937 __I uint32_t CLKSTATUS;
938
959 __IO uint32_t CLKSEL0;
960
1008 __IO uint32_t CLKSEL1;
1009
1069 __IO uint32_t CLKSEL2;
1070
1091 __IO uint32_t CLKDIV0;
1092
1105 __IO uint32_t CLKDIV1;
1106
1129 __IO uint32_t PLLCTL;
1130
1146 __IO uint32_t FRQDIV;
1147
1189 __IO uint32_t MCLKO;
1190
1203 __IO uint32_t WK_INTSTS;
1204
1205 } CLK_T;
1206
1212 #define CLK_PWRCTL_HXT_EN_Pos (0)
1213 #define CLK_PWRCTL_HXT_EN_Msk (0x1ul << CLK_PWRCTL_HXT_EN_Pos)
1215 #define CLK_PWRCTL_LXT_EN_Pos (1)
1216 #define CLK_PWRCTL_LXT_EN_Msk (0x1ul << CLK_PWRCTL_LXT_EN_Pos)
1218 #define CLK_PWRCTL_HIRC_EN_Pos (2)
1219 #define CLK_PWRCTL_HIRC_EN_Msk (0x1ul << CLK_PWRCTL_HIRC_EN_Pos)
1221 #define CLK_PWRCTL_LIRC_EN_Pos (3)
1222 #define CLK_PWRCTL_LIRC_EN_Msk (0x1ul << CLK_PWRCTL_LIRC_EN_Pos)
1224 #define CLK_PWRCTL_WK_DLY_Pos (4)
1225 #define CLK_PWRCTL_WK_DLY_Msk (0x1ul << CLK_PWRCTL_WK_DLY_Pos)
1227 #define CLK_PWRCTL_PD_WK_IE_Pos (5)
1228 #define CLK_PWRCTL_PD_WK_IE_Msk (0x1ul << CLK_PWRCTL_PD_WK_IE_Pos)
1230 #define CLK_PWRCTL_PD_EN_Pos (6)
1231 #define CLK_PWRCTL_PD_EN_Msk (0x1ul << CLK_PWRCTL_PD_EN_Pos)
1233 #define CLK_PWRCTL_HXT_SELXT_Pos (8)
1234 #define CLK_PWRCTL_HXT_SELXT_Msk (0x1ul << CLK_PWRCTL_HXT_SELXT_Pos)
1236 #define CLK_PWRCTL_HXT_GAIN_Pos (9)
1237 #define CLK_PWRCTL_HXT_GAIN_Msk (0x1ul << CLK_PWRCTL_HXT_GAIN_Pos)
1239 #define CLK_PWRCTL_LXT_SCNT_Pos (10)
1240 #define CLK_PWRCTL_LXT_SCNT_Msk (0x1ul << CLK_PWRCTL_LXT_SCNT_Pos)
1242 #define CLK_PWRCTL_HXT_HF_ST_Pos (11)
1243 #define CLK_PWRCTL_HXT_HF_ST_Msk (0x3ul << CLK_PWRCTL_HXT_HF_ST_Pos)
1245 #define CLK_AHBCLK_GPIO_EN_Pos (0)
1246 #define CLK_AHBCLK_GPIO_EN_Msk (0x1ul << CLK_AHBCLK_GPIO_EN_Pos)
1248 #define CLK_AHBCLK_DMA_EN_Pos (1)
1249 #define CLK_AHBCLK_DMA_EN_Msk (0x1ul << CLK_AHBCLK_DMA_EN_Pos)
1251 #define CLK_AHBCLK_ISP_EN_Pos (2)
1252 #define CLK_AHBCLK_ISP_EN_Msk (0x1ul << CLK_AHBCLK_ISP_EN_Pos)
1254 #define CLK_AHBCLK_EBI_EN_Pos (3)
1255 #define CLK_AHBCLK_EBI_EN_Msk (0x1ul << CLK_AHBCLK_EBI_EN_Pos)
1257 #define CLK_AHBCLK_SRAM_EN_Pos (4)
1258 #define CLK_AHBCLK_SRAM_EN_Msk (0x1ul << CLK_AHBCLK_SRAM_EN_Pos)
1260 #define CLK_AHBCLK_TICK_EN_Pos (5)
1261 #define CLK_AHBCLK_TICK_EN_Msk (0x1ul << CLK_AHBCLK_TICK_EN_Pos)
1263 #define CLK_APBCLK_WDT_EN_Pos (0)
1264 #define CLK_APBCLK_WDT_EN_Msk (0x1ul << CLK_APBCLK_WDT_EN_Pos)
1266 #define CLK_APBCLK_RTC_EN_Pos (1)
1267 #define CLK_APBCLK_RTC_EN_Msk (0x1ul << CLK_APBCLK_RTC_EN_Pos)
1269 #define CLK_APBCLK_TMR0_EN_Pos (2)
1270 #define CLK_APBCLK_TMR0_EN_Msk (0x1ul << CLK_APBCLK_TMR0_EN_Pos)
1272 #define CLK_APBCLK_TMR1_EN_Pos (3)
1273 #define CLK_APBCLK_TMR1_EN_Msk (0x1ul << CLK_APBCLK_TMR1_EN_Pos)
1275 #define CLK_APBCLK_TMR2_EN_Pos (4)
1276 #define CLK_APBCLK_TMR2_EN_Msk (0x1ul << CLK_APBCLK_TMR2_EN_Pos)
1278 #define CLK_APBCLK_TMR3_EN_Pos (5)
1279 #define CLK_APBCLK_TMR3_EN_Msk (0x1ul << CLK_APBCLK_TMR3_EN_Pos)
1281 #define CLK_APBCLK_FDIV_EN_Pos (6)
1282 #define CLK_APBCLK_FDIV_EN_Msk (0x1ul << CLK_APBCLK_FDIV_EN_Pos)
1284 #define CLK_APBCLK_SC2_EN_Pos (7)
1285 #define CLK_APBCLK_SC2_EN_Msk (0x1ul << CLK_APBCLK_SC2_EN_Pos)
1287 #define CLK_APBCLK_I2C0_EN_Pos (8)
1288 #define CLK_APBCLK_I2C0_EN_Msk (0x1ul << CLK_APBCLK_I2C0_EN_Pos)
1290 #define CLK_APBCLK_I2C1_EN_Pos (9)
1291 #define CLK_APBCLK_I2C1_EN_Msk (0x1ul << CLK_APBCLK_I2C1_EN_Pos)
1293 #define CLK_APBCLK_SPI0_EN_Pos (12)
1294 #define CLK_APBCLK_SPI0_EN_Msk (0x1ul << CLK_APBCLK_SPI0_EN_Pos)
1296 #define CLK_APBCLK_SPI1_EN_Pos (13)
1297 #define CLK_APBCLK_SPI1_EN_Msk (0x1ul << CLK_APBCLK_SPI1_EN_Pos)
1299 #define CLK_APBCLK_SPI2_EN_Pos (14)
1300 #define CLK_APBCLK_SPI2_EN_Msk (0x1ul << CLK_APBCLK_SPI2_EN_Pos)
1302 #define CLK_APBCLK_UART0_EN_Pos (16)
1303 #define CLK_APBCLK_UART0_EN_Msk (0x1ul << CLK_APBCLK_UART0_EN_Pos)
1305 #define CLK_APBCLK_UART1_EN_Pos (17)
1306 #define CLK_APBCLK_UART1_EN_Msk (0x1ul << CLK_APBCLK_UART1_EN_Pos)
1308 #define CLK_APBCLK_PWM0_CH01_EN_Pos (20)
1309 #define CLK_APBCLK_PWM0_CH01_EN_Msk (0x1ul << CLK_APBCLK_PWM0_CH01_EN_Pos)
1311 #define CLK_APBCLK_PWM0_CH23_EN_Pos (21)
1312 #define CLK_APBCLK_PWM0_CH23_EN_Msk (0x1ul << CLK_APBCLK_PWM0_CH23_EN_Pos)
1314 #define CLK_APBCLK_PWM1_CH01_EN_Pos (22)
1315 #define CLK_APBCLK_PWM1_CH01_EN_Msk (0x1ul << CLK_APBCLK_PWM1_CH01_EN_Pos)
1317 #define CLK_APBCLK_PWM1_CH23_EN_Pos (23)
1318 #define CLK_APBCLK_PWM1_CH23_EN_Msk (0x1ul << CLK_APBCLK_PWM1_CH23_EN_Pos)
1320 #define CLK_APBCLK_DAC_EN_Pos (25)
1321 #define CLK_APBCLK_DAC_EN_Msk (0x1ul << CLK_APBCLK_DAC_EN_Pos)
1323 #define CLK_APBCLK_LCD_EN_Pos (26)
1324 #define CLK_APBCLK_LCD_EN_Msk (0x1ul << CLK_APBCLK_LCD_EN_Pos)
1326 #define CLK_APBCLK_USBD_EN_Pos (27)
1327 #define CLK_APBCLK_USBD_EN_Msk (0x1ul << CLK_APBCLK_USBD_EN_Pos)
1329 #define CLK_APBCLK_ADC_EN_Pos (28)
1330 #define CLK_APBCLK_ADC_EN_Msk (0x1ul << CLK_APBCLK_ADC_EN_Pos)
1332 #define CLK_APBCLK_I2S_EN_Pos (29)
1333 #define CLK_APBCLK_I2S_EN_Msk (0x1ul << CLK_APBCLK_I2S_EN_Pos)
1335 #define CLK_APBCLK_SC0_EN_Pos (30)
1336 #define CLK_APBCLK_SC0_EN_Msk (0x1ul << CLK_APBCLK_SC0_EN_Pos)
1338 #define CLK_APBCLK_SC1_EN_Pos (31)
1339 #define CLK_APBCLK_SC1_EN_Msk (0x1ul << CLK_APBCLK_SC1_EN_Pos)
1341 #define CLK_CLKSTATUS_HXT_STB_Pos (0)
1342 #define CLK_CLKSTATUS_HXT_STB_Msk (0x1ul << CLK_CLKSTATUS_HXT_STB_Pos)
1344 #define CLK_CLKSTATUS_LXT_STB_Pos (1)
1345 #define CLK_CLKSTATUS_LXT_STB_Msk (0x1ul << CLK_CLKSTATUS_LXT_STB_Pos)
1347 #define CLK_CLKSTATUS_PLL_STB_Pos (2)
1348 #define CLK_CLKSTATUS_PLL_STB_Msk (0x1ul << CLK_CLKSTATUS_PLL_STB_Pos)
1350 #define CLK_CLKSTATUS_LIRC_STB_Pos (3)
1351 #define CLK_CLKSTATUS_LIRC_STB_Msk (0x1ul << CLK_CLKSTATUS_LIRC_STB_Pos)
1353 #define CLK_CLKSTATUS_HIRC_STB_Pos (4)
1354 #define CLK_CLKSTATUS_HIRC_STB_Msk (0x1ul << CLK_CLKSTATUS_HIRC_STB_Pos)
1356 #define CLK_CLKSTATUS_CLK_SW_FAIL_Pos (7)
1357 #define CLK_CLKSTATUS_CLK_SW_FAIL_Msk (0x1ul << CLK_CLKSTATUS_CLK_SW_FAIL_Pos)
1359 #define CLK_CLKSEL0_HCLK_S_Pos (0)
1360 #define CLK_CLKSEL0_HCLK_S_Msk (0x7ul << CLK_CLKSEL0_HCLK_S_Pos)
1362 #define CLK_CLKSEL1_UART_S_Pos (0)
1363 #define CLK_CLKSEL1_UART_S_Msk (0x3ul << CLK_CLKSEL1_UART_S_Pos)
1365 #define CLK_CLKSEL1_ADC_S_Pos (2)
1366 #define CLK_CLKSEL1_ADC_S_Msk (0x3ul << CLK_CLKSEL1_ADC_S_Pos)
1368 #define CLK_CLKSEL1_PWM0_CH01_S_Pos (4)
1369 #define CLK_CLKSEL1_PWM0_CH01_S_Msk (0x3ul << CLK_CLKSEL1_PWM0_CH01_S_Pos)
1371 #define CLK_CLKSEL1_PWM0_CH23_S_Pos (6)
1372 #define CLK_CLKSEL1_PWM0_CH23_S_Msk (0x3ul << CLK_CLKSEL1_PWM0_CH23_S_Pos)
1374 #define CLK_CLKSEL1_TMR0_S_Pos (8)
1375 #define CLK_CLKSEL1_TMR0_S_Msk (0x7ul << CLK_CLKSEL1_TMR0_S_Pos)
1377 #define CLK_CLKSEL1_TMR1_S_Pos (12)
1378 #define CLK_CLKSEL1_TMR1_S_Msk (0x7ul << CLK_CLKSEL1_TMR1_S_Pos)
1380 #define CLK_CLKSEL1_LCD_S_Pos (18)
1381 #define CLK_CLKSEL1_LCD_S_Msk (0x1ul << CLK_CLKSEL1_LCD_S_Pos)
1383 #define CLK_CLKSEL2_FRQDIV_S_Pos (2)
1384 #define CLK_CLKSEL2_FRQDIV_S_Msk (0x3ul << CLK_CLKSEL2_FRQDIV_S_Pos)
1386 #define CLK_CLKSEL2_PWM1_CH01_S_Pos (4)
1387 #define CLK_CLKSEL2_PWM1_CH01_S_Msk (0x3ul << CLK_CLKSEL2_PWM1_CH01_S_Pos)
1389 #define CLK_CLKSEL2_PWM1_CH23_S_Pos (6)
1390 #define CLK_CLKSEL2_PWM1_CH23_S_Msk (0x3ul << CLK_CLKSEL2_PWM1_CH23_S_Pos)
1392 #define CLK_CLKSEL2_TMR2_S_Pos (8)
1393 #define CLK_CLKSEL2_TMR2_S_Msk (0x7ul << CLK_CLKSEL2_TMR2_S_Pos)
1395 #define CLK_CLKSEL2_TMR3_S_Pos (12)
1396 #define CLK_CLKSEL2_TMR3_S_Msk (0x7ul << CLK_CLKSEL2_TMR3_S_Pos)
1398 #define CLK_CLKSEL2_I2S_S_Pos (16)
1399 #define CLK_CLKSEL2_I2S_S_Msk (0x3ul << CLK_CLKSEL2_I2S_S_Pos)
1401 #define CLK_CLKSEL2_SC_S_Pos (18)
1402 #define CLK_CLKSEL2_SC_S_Msk (0x3ul << CLK_CLKSEL2_SC_S_Pos)
1404 #define CLK_CLKSEL2_SPI0_S_Pos (20)
1405 #define CLK_CLKSEL2_SPI0_S_Msk (0x1ul << CLK_CLKSEL2_SPI0_S_Pos)
1407 #define CLK_CLKSEL2_SPI1_S_Pos (21)
1408 #define CLK_CLKSEL2_SPI1_S_Msk (0x1ul << CLK_CLKSEL2_SPI1_S_Pos)
1410 #define CLK_CLKSEL2_SPI2_S_Pos (22)
1411 #define CLK_CLKSEL2_SPI2_S_Msk (0x1ul << CLK_CLKSEL2_SPI2_S_Pos)
1413 #define CLK_CLKDIV0_HCLK_N_Pos (0)
1414 #define CLK_CLKDIV0_HCLK_N_Msk (0xful << CLK_CLKDIV0_HCLK_N_Pos)
1416 #define CLK_CLKDIV0_USB_N_Pos (4)
1417 #define CLK_CLKDIV0_USB_N_Msk (0xful << CLK_CLKDIV0_USB_N_Pos)
1419 #define CLK_CLKDIV0_UART_N_Pos (8)
1420 #define CLK_CLKDIV0_UART_N_Msk (0xful << CLK_CLKDIV0_UART_N_Pos)
1422 #define CLK_CLKDIV0_I2S_N_Pos (12)
1423 #define CLK_CLKDIV0_I2S_N_Msk (0xful << CLK_CLKDIV0_I2S_N_Pos)
1425 #define CLK_CLKDIV0_ADC_N_Pos (16)
1426 #define CLK_CLKDIV0_ADC_N_Msk (0xfful << CLK_CLKDIV0_ADC_N_Pos)
1428 #define CLK_CLKDIV0_SC0_N_Pos (28)
1429 #define CLK_CLKDIV0_SC0_N_Msk (0xful << CLK_CLKDIV0_SC0_N_Pos)
1431 #define CLK_CLKDIV1_SC1_N_Pos (0)
1432 #define CLK_CLKDIV1_SC1_N_Msk (0xful << CLK_CLKDIV1_SC1_N_Pos)
1434 #define CLK_CLKDIV1_SC2_N_Pos (4)
1435 #define CLK_CLKDIV1_SC2_N_Msk (0xful << CLK_CLKDIV1_SC2_N_Pos)
1437 #define CLK_PLLCTL_FB_DV_Pos (0)
1438 #define CLK_PLLCTL_FB_DV_Msk (0x3ful << CLK_PLLCTL_FB_DV_Pos)
1440 #define CLK_PLLCTL_IN_DV_Pos (8)
1441 #define CLK_PLLCTL_IN_DV_Msk (0x3ul << CLK_PLLCTL_IN_DV_Pos)
1443 #define CLK_PLLCTL_OUT_DV_Pos (12)
1444 #define CLK_PLLCTL_OUT_DV_Msk (0x1ul << CLK_PLLCTL_OUT_DV_Pos)
1446 #define CLK_PLLCTL_PD_Pos (16)
1447 #define CLK_PLLCTL_PD_Msk (0x1ul << CLK_PLLCTL_PD_Pos)
1449 #define CLK_PLLCTL_PLL_SRC_Pos (17)
1450 #define CLK_PLLCTL_PLL_SRC_Msk (0x1ul << CLK_PLLCTL_PLL_SRC_Pos)
1452 #define CLK_FRQDIV_FSEL_Pos (0)
1453 #define CLK_FRQDIV_FSEL_Msk (0xful << CLK_FRQDIV_FSEL_Pos)
1455 #define CLK_FRQDIV_FDIV_EN_Pos (4)
1456 #define CLK_FRQDIV_FDIV_EN_Msk (0x1ul << CLK_FRQDIV_FDIV_EN_Pos)
1458 #define CLK_MCLKO_MCLK_SEL_Pos (0)
1459 #define CLK_MCLKO_MCLK_SEL_Msk (0x3ful << CLK_MCLKO_MCLK_SEL_Pos)
1461 #define CLK_MCLKO_MCLK_EN_Pos (7)
1462 #define CLK_MCLKO_MCLK_EN_Msk (0x1ul << CLK_MCLKO_MCLK_EN_Pos)
1464 #define CLK_WK_INTSTS_PD_WK_IS_Pos (0)
1465 #define CLK_WK_INTSTS_PD_WK_IS_Msk (0x1ul << CLK_WK_INTSTS_PD_WK_IS_Pos) /* CLK_CONST */
1468 /* end of CLK register group */
1469
1470
1471 /*---------------------- Digital to Analog Converter -------------------------*/
1477 typedef struct
1478 {
1479
1480
1508 __IO uint32_t CTL0;
1509
1519 __IO uint32_t DATA0;
1520
1540 __IO uint32_t STS0;
1541 uint32_t RESERVE0[1];
1542
1543
1571 __IO uint32_t CTL1;
1572
1582 __IO uint32_t DATA1;
1583
1603 __IO uint32_t STS1;
1604 uint32_t RESERVE1[1];
1605
1606
1626 __IO uint32_t COMCTL;
1627
1628 } DAC_T;
1629
1635 #define DAC_CTL_DACEN_Pos (0)
1636 #define DAC_CTL_DACEN_Msk (0x1ul << DAC_CTL_DACEN_Pos)
1638 #define DAC_CTL_DACIE_Pos (1)
1639 #define DAC_CTL_DACIE_Msk (0x1ul << DAC_CTL_DACIE_Pos)
1641 #define DAC_CTL_DACLSEL_Pos (4)
1642 #define DAC_CTL_DACLSEL_Msk (0x7ul << DAC_CTL_DACLSEL_Pos)
1644 #define DAC_CTL_DACPWONSTBCNT_Pos (8)
1645 #define DAC_CTL_DACPWONSTBCNT_Msk (0x3ffful << DAC_CTL_DACPWONSTBCNT_Pos)
1647 #define DAC_DATA_DACData_Pos (0)
1648 #define DAC_DATA_DACData_Msk (0xffful << DAC_DATA_DACData_Pos)
1650 #define DAC_STS_DACIFG_Pos (0)
1651 #define DAC_STS_DACIFG_Msk (0x1ul << DAC_STS_DACIFG_Pos)
1653 #define DAC_STS_DACSTFG_Pos (1)
1654 #define DAC_STS_DACSTFG_Msk (0x1ul << DAC_STS_DACSTFG_Pos)
1656 #define DAC_STS_BUSY_Pos (2)
1657 #define DAC_STS_BUSY_Msk (0x1ul << DAC_STS_BUSY_Pos)
1659 #define DAC_COMCTL_WAITDACCONV_Pos (0)
1660 #define DAC_COMCTL_WAITDACCONV_Msk (0xfful << DAC_COMCTL_WAITDACCONV_Pos)
1662 #define DAC_COMCTL_DAC01GRP_Pos (8)
1663 #define DAC_COMCTL_DAC01GRP_Msk (0x1ul << DAC_COMCTL_DAC01GRP_Pos)
1665 #define DAC_COMCTL_REFSEL_Pos (9)
1666 #define DAC_COMCTL_REFSEL_Msk (0x3ul << DAC_COMCTL_REFSEL_Pos) /* DAC_CONST */
1669 /* end of DAC register group */
1670
1671
1672 /*---------------------- External Bus Interface Controller -------------------------*/
1678 typedef struct
1679 {
1680
1681
1718 __IO uint32_t EBICON;
1719
1743 __IO uint32_t EXTIME;
1744
1745 } EBI_T;
1746
1752 #define EBI_EBICON_ExtEN_Pos (0)
1753 #define EBI_EBICON_ExtEN_Msk (0x1ul << EBI_EBICON_ExtEN_Pos)
1755 #define EBI_EBICON_ExtBW16_Pos (1)
1756 #define EBI_EBICON_ExtBW16_Msk (0x1ul << EBI_EBICON_ExtBW16_Pos)
1758 #define EBI_EBICON_MCLKDIV_Pos (8)
1759 #define EBI_EBICON_MCLKDIV_Msk (0x7ul << EBI_EBICON_MCLKDIV_Pos)
1761 #define EBI_EBICON_MCLKEN_Pos (11)
1762 #define EBI_EBICON_MCLKEN_Msk (0x1ul << EBI_EBICON_MCLKEN_Pos)
1764 #define EBI_EBICON_ExttALE_Pos (16)
1765 #define EBI_EBICON_ExttALE_Msk (0x7ul << EBI_EBICON_ExttALE_Pos)
1767 #define EBI_EXTIME_ExttACC_Pos (0)
1768 #define EBI_EXTIME_ExttACC_Msk (0x1ful << EBI_EXTIME_ExttACC_Pos)
1770 #define EBI_EXTIME_ExttAHD_Pos (8)
1771 #define EBI_EXTIME_ExttAHD_Msk (0x7ul << EBI_EXTIME_ExttAHD_Pos)
1773 #define EBI_EXTIME_ExtIW2X_Pos (12)
1774 #define EBI_EXTIME_ExtIW2X_Msk (0xful << EBI_EXTIME_ExtIW2X_Pos)
1776 #define EBI_EXTIME_ExtIR2W_Pos (16)
1777 #define EBI_EXTIME_ExtIR2W_Msk (0xful << EBI_EXTIME_ExtIR2W_Pos)
1779 #define EBI_EXTIME_ExtIR2R_Pos (24)
1780 #define EBI_EXTIME_ExtIR2R_Msk (0xful << EBI_EXTIME_ExtIR2R_Pos) /* EBI_CONST */
1783 /* end of EBI register group */
1784
1785
1786 /*---------------------- Flash Memory Controller -------------------------*/
1792 typedef struct
1793 {
1794
1795
1832 __IO uint32_t ISPCON;
1833
1845 __IO uint32_t ISPADR;
1846
1858 __IO uint32_t ISPDAT;
1859
1874 __IO uint32_t ISPCMD;
1875
1888 __IO uint32_t ISPTRG;
1889
1902 __I uint32_t DFBADR;
1903 uint32_t RESERVE0[10];
1904
1905
1926 __IO uint32_t ISPSTA;
1927
1928 } FMC_T;
1929
1935 #define FMC_ISPCON_ISPEN_Pos (0)
1936 #define FMC_ISPCON_ISPEN_Msk (0x1ul << FMC_ISPCON_ISPEN_Pos)
1938 #define FMC_ISPCON_BS_Pos (1)
1939 #define FMC_ISPCON_BS_Msk (0x1ul << FMC_ISPCON_BS_Pos)
1941 #define FMC_ISPCON_APUEN_Pos (3)
1942 #define FMC_ISPCON_APUEN_Msk (0x1ul << FMC_ISPCON_APUEN_Pos)
1944 #define FMC_ISPCON_CFGUEN_Pos (4)
1945 #define FMC_ISPCON_CFGUEN_Msk (0x1ul << FMC_ISPCON_CFGUEN_Pos)
1947 #define FMC_ISPCON_LDUEN_Pos (5)
1948 #define FMC_ISPCON_LDUEN_Msk (0x1ul << FMC_ISPCON_LDUEN_Pos)
1950 #define FMC_ISPCON_ISPFF_Pos (6)
1951 #define FMC_ISPCON_ISPFF_Msk (0x1ul << FMC_ISPCON_ISPFF_Pos)
1953 #define FMC_ISPADR_ISPADR_Pos (0)
1954 #define FMC_ISPADR_ISPADR_Msk (0xfffffffful << FMC_ISPADR_ISPADR_Pos)
1956 #define FMC_ISPDAT_ISPDAT_Pos (0)
1957 #define FMC_ISPDAT_ISPDAT_Msk (0xfffffffful << FMC_ISPDAT_ISPDAT_Pos)
1959 #define FMC_ISPCMD_FCTRL_Pos (0)
1960 #define FMC_ISPCMD_FCTRL_Msk (0xful << FMC_ISPCMD_FCTRL_Pos)
1962 #define FMC_ISPCMD_FCEN_Pos (4)
1963 #define FMC_ISPCMD_FCEN_Msk (0x1ul << FMC_ISPCMD_FCEN_Pos)
1965 #define FMC_ISPCMD_FOEN_Pos (5)
1966 #define FMC_ISPCMD_FOEN_Msk (0x1ul << FMC_ISPCMD_FOEN_Pos)
1968 #define FMC_ISPTRG_ISPGO_Pos (0)
1969 #define FMC_ISPTRG_ISPGO_Msk (0x1ul << FMC_ISPTRG_ISPGO_Pos)
1971 #define FMC_DFBADR_DFBA_Pos (0)
1972 #define FMC_DFBADR_DFBA_Msk (0xfffffffful << FMC_DFBADR_DFBA_Pos)
1974 #define FMC_ISPSTA_ISPBUSY_Pos (0)
1975 #define FMC_ISPSTA_ISPBUSY_Msk (0x1ul << FMC_ISPSTA_ISPBUSY_Pos)
1977 #define FMC_ISPSTA_CBS_Pos (1)
1978 #define FMC_ISPSTA_CBS_Msk (0x3ul << FMC_ISPSTA_CBS_Pos)
1980 #define FMC_ISPSTA_ISPFF_Pos (6)
1981 #define FMC_ISPSTA_ISPFF_Msk (0x1ul << FMC_ISPSTA_ISPFF_Pos) /* FMC_CONST */
1984 /* end of FMC register group */
1985
1986
1987 /*---------------------- System Global Control Registers -------------------------*/
1993 typedef struct
1994 {
1995
1996
2008 __I uint32_t PDID;
2009
2042 __IO uint32_t RST_SRC;
2043
2080 __IO uint32_t IPRST_CTL1;
2081
2156 __IO uint32_t IPRST_CTL2;
2157 uint32_t RESERVE0[4];
2158
2159
2171 __IO uint32_t TEMPCTL;
2172 uint32_t RESERVE1[3];
2173
2174
2231 __IO uint32_t PA_L_MFP;
2232
2292 __IO uint32_t PA_H_MFP;
2293
2348 __IO uint32_t PB_L_MFP;
2349
2407 __IO uint32_t PB_H_MFP;
2408
2462 __IO uint32_t PC_L_MFP;
2463
2513 __IO uint32_t PC_H_MFP;
2514
2566 __IO uint32_t PD_L_MFP;
2567
2600 __IO uint32_t PD_H_MFP;
2601
2635 __IO uint32_t PE_L_MFP;
2636
2669 __IO uint32_t PE_H_MFP;
2670
2700 __IO uint32_t PF_L_MFP;
2701 uint32_t RESERVE2[1];
2702
2703
2716 __IO uint32_t PORCTL;
2717
2774 __IO uint32_t BODCTL;
2775
2806 __IO uint32_t BODSTS;
2807
2838 __IO uint32_t Int_VREFCTL;
2839 uint32_t RESERVE3[4];
2840
2841
2879 __IO uint32_t IRCTRIMCTL;
2880
2899 __IO uint32_t IRCTRIMIEN;
2900
2926 __IO uint32_t IRCTRIMINT;
2927 uint32_t RESERVE4[29];
2928
2929
2941 __IO uint32_t RegLockAddr;
2942
2943 } SYS_T;
2944
2950 #define SYS_PDID_PDID_Pos (0)
2951 #define SYS_PDID_PDID_Msk (0xfffffffful << SYS_PDID_PDID_Pos)
2953 #define SYS_RST_SRC_RSTS_POR_Pos (0)
2954 #define SYS_RST_SRC_RSTS_POR_Msk (0x1ul << SYS_RST_SRC_RSTS_POR_Pos)
2956 #define SYS_RST_SRC_RSTS_PAD_Pos (1)
2957 #define SYS_RST_SRC_RSTS_PAD_Msk (0x1ul << SYS_RST_SRC_RSTS_PAD_Pos)
2959 #define SYS_RST_SRC_RSTS_WDT_Pos (2)
2960 #define SYS_RST_SRC_RSTS_WDT_Msk (0x1ul << SYS_RST_SRC_RSTS_WDT_Pos)
2962 #define SYS_RST_SRC_RSTS_BOD_Pos (4)
2963 #define SYS_RST_SRC_RSTS_BOD_Msk (0x1ul << SYS_RST_SRC_RSTS_BOD_Pos)
2965 #define SYS_RST_SRC_RSTS_SYS_Pos (5)
2966 #define SYS_RST_SRC_RSTS_SYS_Msk (0x1ul << SYS_RST_SRC_RSTS_SYS_Pos)
2968 #define SYS_RST_SRC_RSTS_CPU_Pos (7)
2969 #define SYS_RST_SRC_RSTS_CPU_Msk (0x1ul << SYS_RST_SRC_RSTS_CPU_Pos)
2971 #define SYS_IPRST_CTL1_CHIP_RST_Pos (0)
2972 #define SYS_IPRST_CTL1_CHIP_RST_Msk (0x1ul << SYS_IPRST_CTL1_CHIP_RST_Pos)
2974 #define SYS_IPRST_CTL1_CPU_RST_Pos (1)
2975 #define SYS_IPRST_CTL1_CPU_RST_Msk (0x1ul << SYS_IPRST_CTL1_CPU_RST_Pos)
2977 #define SYS_IPRST_CTL1_DMA_RST_Pos (2)
2978 #define SYS_IPRST_CTL1_DMA_RST_Msk (0x1ul << SYS_IPRST_CTL1_DMA_RST_Pos)
2980 #define SYS_IPRST_CTL1_EBI_RST_Pos (3)
2981 #define SYS_IPRST_CTL1_EBI_RST_Msk (0x1ul << SYS_IPRST_CTL1_EBI_RST_Pos)
2983 #define SYS_IPRST_CTL2_GPIO_RST_Pos (1)
2984 #define SYS_IPRST_CTL2_GPIO_RST_Msk (0x1ul << SYS_IPRST_CTL2_GPIO_RST_Pos)
2986 #define SYS_IPRST_CTL2_TMR0_RST_Pos (2)
2987 #define SYS_IPRST_CTL2_TMR0_RST_Msk (0x1ul << SYS_IPRST_CTL2_TMR0_RST_Pos)
2989 #define SYS_IPRST_CTL2_TMR1_RST_Pos (3)
2990 #define SYS_IPRST_CTL2_TMR1_RST_Msk (0x1ul << SYS_IPRST_CTL2_TMR1_RST_Pos)
2992 #define SYS_IPRST_CTL2_TMR2_RST_Pos (4)
2993 #define SYS_IPRST_CTL2_TMR2_RST_Msk (0x1ul << SYS_IPRST_CTL2_TMR2_RST_Pos)
2995 #define SYS_IPRST_CTL2_TMR3_RST_Pos (5)
2996 #define SYS_IPRST_CTL2_TMR3_RST_Msk (0x1ul << SYS_IPRST_CTL2_TMR3_RST_Pos)
2998 #define SYS_IPRST_CTL2_SC2_RST_Pos (7)
2999 #define SYS_IPRST_CTL2_SC2_RST_Msk (0x1ul << SYS_IPRST_CTL2_SC2_RST_Pos)
3001 #define SYS_IPRST_CTL2_I2C0_RST_Pos (8)
3002 #define SYS_IPRST_CTL2_I2C0_RST_Msk (0x1ul << SYS_IPRST_CTL2_I2C0_RST_Pos)
3004 #define SYS_IPRST_CTL2_I2C1_RST_Pos (9)
3005 #define SYS_IPRST_CTL2_I2C1_RST_Msk (0x1ul << SYS_IPRST_CTL2_I2C1_RST_Pos)
3007 #define SYS_IPRST_CTL2_SPI0_RST_Pos (12)
3008 #define SYS_IPRST_CTL2_SPI0_RST_Msk (0x1ul << SYS_IPRST_CTL2_SPI0_RST_Pos)
3010 #define SYS_IPRST_CTL2_SPI1_RST_Pos (13)
3011 #define SYS_IPRST_CTL2_SPI1_RST_Msk (0x1ul << SYS_IPRST_CTL2_SPI1_RST_Pos)
3013 #define SYS_IPRST_CTL2_SPI2_RST_Pos (14)
3014 #define SYS_IPRST_CTL2_SPI2_RST_Msk (0x1ul << SYS_IPRST_CTL2_SPI2_RST_Pos)
3016 #define SYS_IPRST_CTL2_UART0_RST_Pos (16)
3017 #define SYS_IPRST_CTL2_UART0_RST_Msk (0x1ul << SYS_IPRST_CTL2_UART0_RST_Pos)
3019 #define SYS_IPRST_CTL2_UART1_RST_Pos (17)
3020 #define SYS_IPRST_CTL2_UART1_RST_Msk (0x1ul << SYS_IPRST_CTL2_UART1_RST_Pos)
3022 #define SYS_IPRST_CTL2_PWM0_RST_Pos (20)
3023 #define SYS_IPRST_CTL2_PWM0_RST_Msk (0x1ul << SYS_IPRST_CTL2_PWM0_RST_Pos)
3025 #define SYS_IPRST_CTL2_PWM1_RST_Pos (21)
3026 #define SYS_IPRST_CTL2_PWM1_RST_Msk (0x1ul << SYS_IPRST_CTL2_PWM1_RST_Pos)
3028 #define SYS_IPRST_CTL2_DAC_RST_Pos (25)
3029 #define SYS_IPRST_CTL2_DAC_RST_Msk (0x1ul << SYS_IPRST_CTL2_DAC_RST_Pos)
3031 #define SYS_IPRST_CTL2_LCD_RST_Pos (26)
3032 #define SYS_IPRST_CTL2_LCD_RST_Msk (0x1ul << SYS_IPRST_CTL2_LCD_RST_Pos)
3034 #define SYS_IPRST_CTL2_USBD_RST_Pos (27)
3035 #define SYS_IPRST_CTL2_USBD_RST_Msk (0x1ul << SYS_IPRST_CTL2_USBD_RST_Pos)
3037 #define SYS_IPRST_CTL2_ADC_RST_Pos (28)
3038 #define SYS_IPRST_CTL2_ADC_RST_Msk (0x1ul << SYS_IPRST_CTL2_ADC_RST_Pos)
3040 #define SYS_IPRST_CTL2_I2S_RST_Pos (29)
3041 #define SYS_IPRST_CTL2_I2S_RST_Msk (0x1ul << SYS_IPRST_CTL2_I2S_RST_Pos)
3043 #define SYS_IPRST_CTL2_SC0_RST_Pos (30)
3044 #define SYS_IPRST_CTL2_SC0_RST_Msk (0x1ul << SYS_IPRST_CTL2_SC0_RST_Pos)
3046 #define SYS_IPRST_CTL2_SC1_RST_Pos (31)
3047 #define SYS_IPRST_CTL2_SC1_RST_Msk (0x1ul << SYS_IPRST_CTL2_SC1_RST_Pos)
3049 #define SYS_TEMPCTL_VTEMP_EN_Pos (0)
3050 #define SYS_TEMPCTL_VTEMP_EN_Msk (0x1ul << SYS_TEMPCTL_VTEMP_EN_Pos)
3052 #define SYS_PA_L_MFP_PA0_MFP_Pos (0)
3053 #define SYS_PA_L_MFP_PA0_MFP_Msk (0x7ul << SYS_PA_L_MFP_PA0_MFP_Pos)
3055 #define SYS_PA_L_MFP_PA1_MFP_Pos (4)
3056 #define SYS_PA_L_MFP_PA1_MFP_Msk (0x7ul << SYS_PA_L_MFP_PA1_MFP_Pos)
3058 #define SYS_PA_L_MFP_PA2_MFP_Pos (8)
3059 #define SYS_PA_L_MFP_PA2_MFP_Msk (0x7ul << SYS_PA_L_MFP_PA2_MFP_Pos)
3061 #define SYS_PA_L_MFP_PA3_MFP_Pos (12)
3062 #define SYS_PA_L_MFP_PA3_MFP_Msk (0x7ul << SYS_PA_L_MFP_PA3_MFP_Pos)
3064 #define SYS_PA_L_MFP_PA4_MFP_Pos (16)
3065 #define SYS_PA_L_MFP_PA4_MFP_Msk (0x7ul << SYS_PA_L_MFP_PA4_MFP_Pos)
3067 #define SYS_PA_L_MFP_PA5_MFP_Pos (20)
3068 #define SYS_PA_L_MFP_PA5_MFP_Msk (0x7ul << SYS_PA_L_MFP_PA5_MFP_Pos)
3070 #define SYS_PA_L_MFP_PA6_MFP_Pos (24)
3071 #define SYS_PA_L_MFP_PA6_MFP_Msk (0x7ul << SYS_PA_L_MFP_PA6_MFP_Pos)
3073 #define SYS_PA_L_MFP_PA7_MFP_Pos (28)
3074 #define SYS_PA_L_MFP_PA7_MFP_Msk (0x7ul << SYS_PA_L_MFP_PA7_MFP_Pos)
3076 #define SYS_PA_H_MFP_PA8_MFP_Pos (0)
3077 #define SYS_PA_H_MFP_PA8_MFP_Msk (0x7ul << SYS_PA_H_MFP_PA8_MFP_Pos)
3079 #define SYS_PA_H_MFP_PA9_MFP_Pos (4)
3080 #define SYS_PA_H_MFP_PA9_MFP_Msk (0x7ul << SYS_PA_H_MFP_PA9_MFP_Pos)
3082 #define SYS_PA_H_MFP_PA10_MFP_Pos (8)
3083 #define SYS_PA_H_MFP_PA10_MFP_Msk (0x7ul << SYS_PA_H_MFP_PA10_MFP_Pos)
3085 #define SYS_PA_H_MFP_PA11_MFP_Pos (12)
3086 #define SYS_PA_H_MFP_PA11_MFP_Msk (0x7ul << SYS_PA_H_MFP_PA11_MFP_Pos)
3088 #define SYS_PA_H_MFP_PA12_MFP_Pos (16)
3089 #define SYS_PA_H_MFP_PA12_MFP_Msk (0x7ul << SYS_PA_H_MFP_PA12_MFP_Pos)
3091 #define SYS_PA_H_MFP_PA13_MFP_Pos (20)
3092 #define SYS_PA_H_MFP_PA13_MFP_Msk (0x7ul << SYS_PA_H_MFP_PA13_MFP_Pos)
3094 #define SYS_PA_H_MFP_PA14_MFP_Pos (24)
3095 #define SYS_PA_H_MFP_PA14_MFP_Msk (0x7ul << SYS_PA_H_MFP_PA14_MFP_Pos)
3097 #define SYS_PA_H_MFP_PA15_MFP_Pos (28)
3098 #define SYS_PA_H_MFP_PA15_MFP_Msk (0x7ul << SYS_PA_H_MFP_PA15_MFP_Pos)
3100 #define SYS_PB_L_MFP_PB0_MFP_Pos (0)
3101 #define SYS_PB_L_MFP_PB0_MFP_Msk (0x7ul << SYS_PB_L_MFP_PB0_MFP_Pos)
3103 #define SYS_PB_L_MFP_PB1_MFP_Pos (4)
3104 #define SYS_PB_L_MFP_PB1_MFP_Msk (0x7ul << SYS_PB_L_MFP_PB1_MFP_Pos)
3106 #define SYS_PB_L_MFP_PB2_MFP_Pos (8)
3107 #define SYS_PB_L_MFP_PB2_MFP_Msk (0x7ul << SYS_PB_L_MFP_PB2_MFP_Pos)
3109 #define SYS_PB_L_MFP_PB3_MFP_Pos (12)
3110 #define SYS_PB_L_MFP_PB3_MFP_Msk (0x7ul << SYS_PB_L_MFP_PB3_MFP_Pos)
3112 #define SYS_PB_L_MFP_PB4_MFP_Pos (16)
3113 #define SYS_PB_L_MFP_PB4_MFP_Msk (0x7ul << SYS_PB_L_MFP_PB4_MFP_Pos)
3115 #define SYS_PB_L_MFP_PB5_MFP_Pos (20)
3116 #define SYS_PB_L_MFP_PB5_MFP_Msk (0x7ul << SYS_PB_L_MFP_PB5_MFP_Pos)
3118 #define SYS_PB_L_MFP_PB6_MFP_Pos (24)
3119 #define SYS_PB_L_MFP_PB6_MFP_Msk (0x7ul << SYS_PB_L_MFP_PB6_MFP_Pos)
3121 #define SYS_PB_L_MFP_PB7_MFP_Pos (28)
3122 #define SYS_PB_L_MFP_PB7_MFP_Msk (0x7ul << SYS_PB_L_MFP_PB7_MFP_Pos)
3124 #define SYS_PB_H_MFP_PB8_MFP_Pos (0)
3125 #define SYS_PB_H_MFP_PB8_MFP_Msk (0x7ul << SYS_PB_H_MFP_PB8_MFP_Pos)
3127 #define SYS_PB_H_MFP_PB9_MFP_Pos (4)
3128 #define SYS_PB_H_MFP_PB9_MFP_Msk (0x7ul << SYS_PB_H_MFP_PB9_MFP_Pos)
3130 #define SYS_PB_H_MFP_PB10_MFP_Pos (8)
3131 #define SYS_PB_H_MFP_PB10_MFP_Msk (0x7ul << SYS_PB_H_MFP_PB10_MFP_Pos)
3133 #define SYS_PB_H_MFP_PB11_MFP_Pos (12)
3134 #define SYS_PB_H_MFP_PB11_MFP_Msk (0x7ul << SYS_PB_H_MFP_PB11_MFP_Pos)
3136 #define SYS_PB_H_MFP_PB12_MFP_Pos (16)
3137 #define SYS_PB_H_MFP_PB12_MFP_Msk (0x7ul << SYS_PB_H_MFP_PB12_MFP_Pos)
3139 #define SYS_PB_H_MFP_PB13_MFP_Pos (20)
3140 #define SYS_PB_H_MFP_PB13_MFP_Msk (0x7ul << SYS_PB_H_MFP_PB13_MFP_Pos)
3142 #define SYS_PB_H_MFP_PB14_MFP_Pos (24)
3143 #define SYS_PB_H_MFP_PB14_MFP_Msk (0x7ul << SYS_PB_H_MFP_PB14_MFP_Pos)
3145 #define SYS_PB_H_MFP_PB15_MFP_Pos (28)
3146 #define SYS_PB_H_MFP_PB15_MFP_Msk (0x7ul << SYS_PB_H_MFP_PB15_MFP_Pos)
3148 #define SYS_PC_L_MFP_PC0_MFP_Pos (0)
3149 #define SYS_PC_L_MFP_PC0_MFP_Msk (0x7ul << SYS_PC_L_MFP_PC0_MFP_Pos)
3151 #define SYS_PC_L_MFP_PC1_MFP_Pos (4)
3152 #define SYS_PC_L_MFP_PC1_MFP_Msk (0x7ul << SYS_PC_L_MFP_PC1_MFP_Pos)
3154 #define SYS_PC_L_MFP_PC2_MFP_Pos (8)
3155 #define SYS_PC_L_MFP_PC2_MFP_Msk (0x7ul << SYS_PC_L_MFP_PC2_MFP_Pos)
3157 #define SYS_PC_L_MFP_PC3_MFP_Pos (12)
3158 #define SYS_PC_L_MFP_PC3_MFP_Msk (0x7ul << SYS_PC_L_MFP_PC3_MFP_Pos)
3160 #define SYS_PC_L_MFP_PC4_MFP_Pos (16)
3161 #define SYS_PC_L_MFP_PC4_MFP_Msk (0x7ul << SYS_PC_L_MFP_PC4_MFP_Pos)
3163 #define SYS_PC_L_MFP_PC5_MFP_Pos (20)
3164 #define SYS_PC_L_MFP_PC5_MFP_Msk (0x7ul << SYS_PC_L_MFP_PC5_MFP_Pos)
3166 #define SYS_PC_L_MFP_PC6_MFP_Pos (24)
3167 #define SYS_PC_L_MFP_PC6_MFP_Msk (0x7ul << SYS_PC_L_MFP_PC6_MFP_Pos)
3169 #define SYS_PC_L_MFP_PC7_MFP_Pos (28)
3170 #define SYS_PC_L_MFP_PC7_MFP_Msk (0x7ul << SYS_PC_L_MFP_PC7_MFP_Pos)
3172 #define SYS_PC_H_MFP_PC8_MFP_Pos (0)
3173 #define SYS_PC_H_MFP_PC8_MFP_Msk (0x7ul << SYS_PC_H_MFP_PC8_MFP_Pos)
3175 #define SYS_PC_H_MFP_PC9_MFP_Pos (4)
3176 #define SYS_PC_H_MFP_PC9_MFP_Msk (0x7ul << SYS_PC_H_MFP_PC9_MFP_Pos)
3178 #define SYS_PC_H_MFP_PC10_MFP_Pos (8)
3179 #define SYS_PC_H_MFP_PC10_MFP_Msk (0x7ul << SYS_PC_H_MFP_PC10_MFP_Pos)
3181 #define SYS_PC_H_MFP_PC11_MFP_Pos (12)
3182 #define SYS_PC_H_MFP_PC11_MFP_Msk (0x7ul << SYS_PC_H_MFP_PC11_MFP_Pos)
3184 #define SYS_PC_H_MFP_PC12_MFP_Pos (16)
3185 #define SYS_PC_H_MFP_PC12_MFP_Msk (0x7ul << SYS_PC_H_MFP_PC12_MFP_Pos)
3187 #define SYS_PC_H_MFP_PC13_MFP_Pos (20)
3188 #define SYS_PC_H_MFP_PC13_MFP_Msk (0x7ul << SYS_PC_H_MFP_PC13_MFP_Pos)
3190 #define SYS_PC_H_MFP_PC14_MFP_Pos (24)
3191 #define SYS_PC_H_MFP_PC14_MFP_Msk (0x7ul << SYS_PC_H_MFP_PC14_MFP_Pos)
3193 #define SYS_PC_H_MFP_PC15_MFP_Pos (28)
3194 #define SYS_PC_H_MFP_PC15_MFP_Msk (0x7ul << SYS_PC_H_MFP_PC15_MFP_Pos)
3196 #define SYS_PD_L_MFP_PD0_MFP_Pos (0)
3197 #define SYS_PD_L_MFP_PD0_MFP_Msk (0x7ul << SYS_PD_L_MFP_PD0_MFP_Pos)
3199 #define SYS_PD_L_MFP_PD1_MFP_Pos (4)
3200 #define SYS_PD_L_MFP_PD1_MFP_Msk (0x7ul << SYS_PD_L_MFP_PD1_MFP_Pos)
3202 #define SYS_PD_L_MFP_PD2_MFP_Pos (8)
3203 #define SYS_PD_L_MFP_PD2_MFP_Msk (0x7ul << SYS_PD_L_MFP_PD2_MFP_Pos)
3205 #define SYS_PD_L_MFP_PD3_MFP_Pos (12)
3206 #define SYS_PD_L_MFP_PD3_MFP_Msk (0x7ul << SYS_PD_L_MFP_PD3_MFP_Pos)
3208 #define SYS_PD_L_MFP_PD4_MFP_Pos (16)
3209 #define SYS_PD_L_MFP_PD4_MFP_Msk (0x7ul << SYS_PD_L_MFP_PD4_MFP_Pos)
3211 #define SYS_PD_L_MFP_PD5_MFP_Pos (20)
3212 #define SYS_PD_L_MFP_PD5_MFP_Msk (0x7ul << SYS_PD_L_MFP_PD5_MFP_Pos)
3214 #define SYS_PD_L_MFP_PD6_MFP_Pos (24)
3215 #define SYS_PD_L_MFP_PD6_MFP_Msk (0x7ul << SYS_PD_L_MFP_PD6_MFP_Pos)
3217 #define SYS_PD_L_MFP_PD7_MFP_Pos (28)
3218 #define SYS_PD_L_MFP_PD7_MFP_Msk (0x7ul << SYS_PD_L_MFP_PD7_MFP_Pos)
3220 #define SYS_PD_H_MFP_PD8_MFP_Pos (0)
3221 #define SYS_PD_H_MFP_PD8_MFP_Msk (0x7ul << SYS_PD_H_MFP_PD8_MFP_Pos)
3223 #define SYS_PD_H_MFP_PD9_MFP_Pos (4)
3224 #define SYS_PD_H_MFP_PD9_MFP_Msk (0x7ul << SYS_PD_H_MFP_PD9_MFP_Pos)
3226 #define SYS_PD_H_MFP_PD10_MFP_Pos (8)
3227 #define SYS_PD_H_MFP_PD10_MFP_Msk (0x7ul << SYS_PD_H_MFP_PD10_MFP_Pos)
3229 #define SYS_PD_H_MFP_PD11_MFP_Pos (12)
3230 #define SYS_PD_H_MFP_PD11_MFP_Msk (0x7ul << SYS_PD_H_MFP_PD11_MFP_Pos)
3232 #define SYS_PD_H_MFP_PD12_MFP_Pos (16)
3233 #define SYS_PD_H_MFP_PD12_MFP_Msk (0x7ul << SYS_PD_H_MFP_PD12_MFP_Pos)
3235 #define SYS_PD_H_MFP_PD13_MFP_Pos (20)
3236 #define SYS_PD_H_MFP_PD13_MFP_Msk (0x7ul << SYS_PD_H_MFP_PD13_MFP_Pos)
3238 #define SYS_PD_H_MFP_PD14_MFP_Pos (24)
3239 #define SYS_PD_H_MFP_PD14_MFP_Msk (0x7ul << SYS_PD_H_MFP_PD14_MFP_Pos)
3241 #define SYS_PD_H_MFP_PD15_MFP_Pos (28)
3242 #define SYS_PD_H_MFP_PD15_MFP_Msk (0x7ul << SYS_PD_H_MFP_PD15_MFP_Pos)
3244 #define SYS_PE_L_MFP_PE0_MFP_Pos (0)
3245 #define SYS_PE_L_MFP_PE0_MFP_Msk (0x7ul << SYS_PE_L_MFP_PE0_MFP_Pos)
3247 #define SYS_PE_L_MFP_PE1_MFP_Pos (4)
3248 #define SYS_PE_L_MFP_PE1_MFP_Msk (0x7ul << SYS_PE_L_MFP_PE1_MFP_Pos)
3250 #define SYS_PE_L_MFP_PE2_MFP_Pos (8)
3251 #define SYS_PE_L_MFP_PE2_MFP_Msk (0x7ul << SYS_PE_L_MFP_PE2_MFP_Pos)
3253 #define SYS_PE_L_MFP_PE3_MFP_Pos (12)
3254 #define SYS_PE_L_MFP_PE3_MFP_Msk (0x7ul << SYS_PE_L_MFP_PE3_MFP_Pos)
3256 #define SYS_PE_L_MFP_PE4_MFP_Pos (16)
3257 #define SYS_PE_L_MFP_PE4_MFP_Msk (0x7ul << SYS_PE_L_MFP_PE4_MFP_Pos)
3259 #define SYS_PE_L_MFP_PE5_MFP_Pos (20)
3260 #define SYS_PE_L_MFP_PE5_MFP_Msk (0x7ul << SYS_PE_L_MFP_PE5_MFP_Pos)
3262 #define SYS_PE_L_MFP_PE6_MFP_Pos (24)
3263 #define SYS_PE_L_MFP_PE6_MFP_Msk (0x7ul << SYS_PE_L_MFP_PE6_MFP_Pos)
3265 #define SYS_PE_L_MFP_PE7_MFP_Pos (28)
3266 #define SYS_PE_L_MFP_PE7_MFP_Msk (0x7ul << SYS_PE_L_MFP_PE7_MFP_Pos)
3268 #define SYS_PE_H_MFP_PE8_MFP_Pos (0)
3269 #define SYS_PE_H_MFP_PE8_MFP_Msk (0x7ul << SYS_PE_H_MFP_PE8_MFP_Pos)
3271 #define SYS_PE_H_MFP_PE9_MFP_Pos (4)
3272 #define SYS_PE_H_MFP_PE9_MFP_Msk (0x7ul << SYS_PE_H_MFP_PE9_MFP_Pos)
3274 #define SYS_PE_H_MFP_PE10_MFP_Pos (8)
3275 #define SYS_PE_H_MFP_PE10_MFP_Msk (0x7ul << SYS_PE_H_MFP_PE10_MFP_Pos)
3277 #define SYS_PE_H_MFP_PE11_MFP_Pos (12)
3278 #define SYS_PE_H_MFP_PE11_MFP_Msk (0x7ul << SYS_PE_H_MFP_PE11_MFP_Pos)
3280 #define SYS_PE_H_MFP_PE12_MFP_Pos (16)
3281 #define SYS_PE_H_MFP_PE12_MFP_Msk (0x7ul << SYS_PE_H_MFP_PE12_MFP_Pos)
3283 #define SYS_PE_H_MFP_PE13_MFP_Pos (20)
3284 #define SYS_PE_H_MFP_PE13_MFP_Msk (0x7ul << SYS_PE_H_MFP_PE13_MFP_Pos)
3286 #define SYS_PE_H_MFP_PE14_MFP_Pos (24)
3287 #define SYS_PE_H_MFP_PE14_MFP_Msk (0x7ul << SYS_PE_H_MFP_PE14_MFP_Pos)
3289 #define SYS_PE_H_MFP_PE15_MFP_Pos (28)
3290 #define SYS_PE_H_MFP_PE15_MFP_Msk (0x7ul << SYS_PE_H_MFP_PE15_MFP_Pos)
3292 #define SYS_PF_L_MFP_PF0_MFP_Pos (0)
3293 #define SYS_PF_L_MFP_PF0_MFP_Msk (0x7ul << SYS_PF_L_MFP_PF0_MFP_Pos)
3295 #define SYS_PF_L_MFP_PF1_MFP_Pos (4)
3296 #define SYS_PF_L_MFP_PF1_MFP_Msk (0x7ul << SYS_PF_L_MFP_PF1_MFP_Pos)
3298 #define SYS_PF_L_MFP_PF2_MFP_Pos (8)
3299 #define SYS_PF_L_MFP_PF2_MFP_Msk (0x7ul << SYS_PF_L_MFP_PF2_MFP_Pos)
3301 #define SYS_PF_L_MFP_PF3_MFP_Pos (12)
3302 #define SYS_PF_L_MFP_PF3_MFP_Msk (0x7ul << SYS_PF_L_MFP_PF3_MFP_Pos)
3304 #define SYS_PF_L_MFP_PF4_MFP_Pos (16)
3305 #define SYS_PF_L_MFP_PF4_MFP_Msk (0x7ul << SYS_PF_L_MFP_PF4_MFP_Pos)
3307 #define SYS_PF_L_MFP_PF5_MFP_Pos (20)
3308 #define SYS_PF_L_MFP_PF5_MFP_Msk (0x7ul << SYS_PF_L_MFP_PF5_MFP_Pos)
3310 #define SYS_PORCTL_POR_DIS_CODE_Pos (0)
3311 #define SYS_PORCTL_POR_DIS_CODE_Msk (0xfffful << SYS_PORCTL_POR_DIS_CODE_Pos)
3313 #define SYS_BODCTL_BOD17_EN_Pos (0)
3314 #define SYS_BODCTL_BOD17_EN_Msk (0x1ul << SYS_BODCTL_BOD17_EN_Pos)
3316 #define SYS_BODCTL_BOD20_EN_Pos (1)
3317 #define SYS_BODCTL_BOD20_EN_Msk (0x1ul << SYS_BODCTL_BOD20_EN_Pos)
3319 #define SYS_BODCTL_BOD25_EN_Pos (2)
3320 #define SYS_BODCTL_BOD25_EN_Msk (0x1ul << SYS_BODCTL_BOD25_EN_Pos)
3322 #define SYS_BODCTL_BOD17_RST_EN_Pos (4)
3323 #define SYS_BODCTL_BOD17_RST_EN_Msk (0x1ul << SYS_BODCTL_BOD17_RST_EN_Pos)
3325 #define SYS_BODCTL_BOD20_RST_EN_Pos (5)
3326 #define SYS_BODCTL_BOD20_RST_EN_Msk (0x1ul << SYS_BODCTL_BOD20_RST_EN_Pos)
3328 #define SYS_BODCTL_BOD25_RST_EN_Pos (6)
3329 #define SYS_BODCTL_BOD25_RST_EN_Msk (0x1ul << SYS_BODCTL_BOD25_RST_EN_Pos)
3331 #define SYS_BODCTL_BOD17_INT_EN_Pos (8)
3332 #define SYS_BODCTL_BOD17_INT_EN_Msk (0x1ul << SYS_BODCTL_BOD17_INT_EN_Pos)
3334 #define SYS_BODCTL_BOD20_INT_EN_Pos (9)
3335 #define SYS_BODCTL_BOD20_INT_EN_Msk (0x1ul << SYS_BODCTL_BOD20_INT_EN_Pos)
3337 #define SYS_BODCTL_BOD25_INT_EN_Pos (10)
3338 #define SYS_BODCTL_BOD25_INT_EN_Msk (0x1ul << SYS_BODCTL_BOD25_INT_EN_Pos)
3340 #define SYS_BODSTS_BOD_INT_Pos (0)
3341 #define SYS_BODSTS_BOD_INT_Msk (0x1ul << SYS_BODSTS_BOD_INT_Pos)
3343 #define SYS_BODSTS_BOD17_drop_Pos (1)
3344 #define SYS_BODSTS_BOD17_drop_Msk (0x1ul << SYS_BODSTS_BOD17_drop_Pos)
3346 #define SYS_BODSTS_BOD20_drop_Pos (2)
3347 #define SYS_BODSTS_BOD20_drop_Msk (0x1ul << SYS_BODSTS_BOD20_drop_Pos)
3349 #define SYS_BODSTS_BOD25_drop_Pos (3)
3350 #define SYS_BODSTS_BOD25_drop_Msk (0x1ul << SYS_BODSTS_BOD25_drop_Pos)
3352 #define SYS_BODSTS_BOD17_rise_Pos (4)
3353 #define SYS_BODSTS_BOD17_rise_Msk (0x1ul << SYS_BODSTS_BOD17_rise_Pos)
3355 #define SYS_BODSTS_BOD20_rise_Pos (5)
3356 #define SYS_BODSTS_BOD20_rise_Msk (0x1ul << SYS_BODSTS_BOD20_rise_Pos)
3358 #define SYS_BODSTS_BOD25_rise_Pos (6)
3359 #define SYS_BODSTS_BOD25_rise_Msk (0x1ul << SYS_BODSTS_BOD25_rise_Pos)
3361 #define SYS_VREFCTL_BGP_EN_Pos (0)
3362 #define SYS_VREFCTL_BGP_EN_Msk (0x1ul << SYS_VREFCTL_BGP_EN_Pos)
3364 #define SYS_VREFCTL_REG_EN_Pos (1)
3365 #define SYS_VREFCTL_REG_EN_Msk (0x1ul << SYS_VREFCTL_REG_EN_Pos)
3367 #define SYS_VREFCTL_SEL25_Pos (2)
3368 #define SYS_VREFCTL_SEL25_Msk (0x1ul << SYS_VREFCTL_SEL25_Pos)
3370 #define SYS_VREFCTL_EXT_MODE_Pos (3)
3371 #define SYS_VREFCTL_EXT_MODE_Msk (0x1ul << SYS_VREFCTL_EXT_MODE_Pos)
3373 #define SYS_IRCTRIMCTL_TRIM_SEL_Pos (0)
3374 #define SYS_IRCTRIMCTL_TRIM_SEL_Msk (0x3ul << SYS_IRCTRIMCTL_TRIM_SEL_Pos)
3376 #define SYS_IRCTRIMCTL_TRIM_LOOP_Pos (4)
3377 #define SYS_IRCTRIMCTL_TRIM_LOOP_Msk (0x3ul << SYS_IRCTRIMCTL_TRIM_LOOP_Pos)
3379 #define SYS_IRCTRIMCTL_TRIM_RETRY_CNT_Pos (6)
3380 #define SYS_IRCTRIMCTL_TRIM_RETRY_CNT_Msk (0x3ul << SYS_IRCTRIMCTL_TRIM_RETRY_CNT_Pos)
3382 #define SYS_IRCTRIMCTL_ERR_STOP_Pos (8)
3383 #define SYS_IRCTRIMCTL_ERR_STOP_Msk (0x1ul << SYS_IRCTRIMCTL_ERR_STOP_Pos)
3385 #define SYS_IRCTRIMIEN_TRIM_FAIL_IEN_Pos (1)
3386 #define SYS_IRCTRIMIEN_TRIM_FAIL_IEN_Msk (0x1ul << SYS_IRCTRIMIEN_TRIM_FAIL_IEN_Pos)
3388 #define SYS_IRCTRIMIEN_32K_ERR_IEN_Pos (2)
3389 #define SYS_IRCTRIMIEN_32K_ERR_IEN_Msk (0x1ul << SYS_IRCTRIMIEN_32K_ERR_IEN_Pos)
3391 #define SYS_IRCTRIMINT_FREQ_LOCK_Pos (0)
3392 #define SYS_IRCTRIMINT_FREQ_LOCK_Msk (0x1ul << SYS_IRCTRIMINT_FREQ_LOCK_Pos)
3394 #define SYS_IRCTRIMINT_TRIM_FAIL_INT_Pos (1)
3395 #define SYS_IRCTRIMINT_TRIM_FAIL_INT_Msk (0x1ul << SYS_IRCTRIMINT_TRIM_FAIL_INT_Pos)
3397 #define SYS_IRCTRIMINT_32K_ERR_INT_Pos (2)
3398 #define SYS_IRCTRIMINT_32K_ERR_INT_Msk (0x1ul << SYS_IRCTRIMINT_32K_ERR_INT_Pos)
3400 #define SYS_RegLockAddr_RegUnLock_Pos (0)
3401 #define SYS_RegLockAddr_RegUnLock_Msk (0x1ul << SYS_RegLockAddr_RegUnLock_Pos) /* SYS_CONST */
3404 /* end of SYS register group */
3405
3406
3407 /*---------------------- General Purpose Input/Output Controller -------------------------*/
3413 typedef struct
3414 {
3415
3416
3537 __IO uint32_t PMD;
3538
3552 __IO uint32_t OFFD;
3553
3567 __IO uint32_t DOUT;
3568
3586 __IO uint32_t DMASK;
3587
3599 __I uint32_t PIN;
3600
3618 __IO uint32_t DBEN;
3619
3639 __IO uint32_t IMD;
3640
3937 __IO uint32_t IER;
3938
3955 __IO uint32_t ISRC;
3956
3971 __IO uint32_t PUEN;
3972
3973 } GPIO_T;
3974
3975
3976 typedef struct
3977 {
4013 __IO uint32_t DBNCECON;
4014 } GP_DB_T;
4015
4021 #define GP_PMD_PMD0_Pos (0)
4022 #define GP_PMD_PMD0_Msk (0x3ul << GP_PMD_PMD0_Pos)
4024 #define GP_PMD_PMD1_Pos (2)
4025 #define GP_PMD_PMD1_Msk (0x3ul << GP_PMD_PMD1_Pos)
4027 #define GP_PMD_PMD2_Pos (4)
4028 #define GP_PMD_PMD2_Msk (0x3ul << GP_PMD_PMD2_Pos)
4030 #define GP_PMD_PMD3_Pos (6)
4031 #define GP_PMD_PMD3_Msk (0x3ul << GP_PMD_PMD3_Pos)
4033 #define GP_PMD_PMD4_Pos (8)
4034 #define GP_PMD_PMD4_Msk (0x3ul << GP_PMD_PMD4_Pos)
4036 #define GP_PMD_PMD5_Pos (10)
4037 #define GP_PMD_PMD5_Msk (0x3ul << GP_PMD_PMD5_Pos)
4039 #define GP_PMD_PMD6_Pos (12)
4040 #define GP_PMD_PMD6_Msk (0x3ul << GP_PMD_PMD6_Pos)
4042 #define GP_PMD_PMD7_Pos (14)
4043 #define GP_PMD_PMD7_Msk (0x3ul << GP_PMD_PMD7_Pos)
4045 #define GP_PMD_PMD8_Pos (16)
4046 #define GP_PMD_PMD8_Msk (0x3ul << GP_PMD_PMD8_Pos)
4048 #define GP_PMD_PMD9_Pos (18)
4049 #define GP_PMD_PMD9_Msk (0x3ul << GP_PMD_PMD9_Pos)
4051 #define GP_PMD_PMD10_Pos (20)
4052 #define GP_PMD_PMD10_Msk (0x3ul << GP_PMD_PMD10_Pos)
4054 #define GP_PMD_PMD11_Pos (22)
4055 #define GP_PMD_PMD11_Msk (0x3ul << GP_PMD_PMD11_Pos)
4057 #define GP_PMD_PMD12_Pos (24)
4058 #define GP_PMD_PMD12_Msk (0x3ul << GP_PMD_PMD12_Pos)
4060 #define GP_PMD_PMD13_Pos (26)
4061 #define GP_PMD_PMD13_Msk (0x3ul << GP_PMD_PMD13_Pos)
4063 #define GP_PMD_PMD14_Pos (28)
4064 #define GP_PMD_PMD14_Msk (0x3ul << GP_PMD_PMD14_Pos)
4066 #define GP_PMD_PMD15_Pos (30)
4067 #define GP_PMD_PMD15_Msk (0x3ul << GP_PMD_PMD15_Pos)
4069 #define GP_OFFD_OFFD_Pos (16)
4070 #define GP_OFFD_OFFD_Msk (0xfffful << GP_OFFD_OFFD_Pos)
4072 #define GP_DOUT_DOUT_Pos (0)
4073 #define GP_DOUT_DOUT_Msk (0xfffful << GP_DOUT_DOUT_Pos)
4075 #define GP_DMASK_DMASK_Pos (0)
4076 #define GP_DMASK_DMASK_Msk (0xfffful << GP_DMASK_DMASK_Pos)
4078 #define GP_PIN_PIN_Pos (0)
4079 #define GP_PIN_PIN_Msk (0xfffful << GP_PIN_PIN_Pos)
4081 #define GP_DBEN_DBEN_Pos (0)
4082 #define GP_DBEN_DBEN_Msk (0xfffful << GP_DBEN_DBEN_Pos)
4084 #define GP_IMD_IMD_Pos (0)
4085 #define GP_IMD_IMD_Msk (0xfffful << GP_IMD_IMD_Pos)
4087 #define GP_IER_FIER0_Pos (0)
4088 #define GP_IER_FIER0_Msk (0x1ul << GP_IER_FIER0_Pos)
4090 #define GP_IER_FIER1_Pos (1)
4091 #define GP_IER_FIER1_Msk (0x1ul << GP_IER_FIER1_Pos)
4093 #define GP_IER_FIER2_Pos (2)
4094 #define GP_IER_FIER2_Msk (0x1ul << GP_IER_FIER2_Pos)
4096 #define GP_IER_FIER3_Pos (3)
4097 #define GP_IER_FIER3_Msk (0x1ul << GP_IER_FIER3_Pos)
4099 #define GP_IER_FIER4_Pos (4)
4100 #define GP_IER_FIER4_Msk (0x1ul << GP_IER_FIER4_Pos)
4102 #define GP_IER_FIER5_Pos (5)
4103 #define GP_IER_FIER5_Msk (0x1ul << GP_IER_FIER5_Pos)
4105 #define GP_IER_FIER6_Pos (6)
4106 #define GP_IER_FIER6_Msk (0x1ul << GP_IER_FIER6_Pos)
4108 #define GP_IER_FIER7_Pos (7)
4109 #define GP_IER_FIER7_Msk (0x1ul << GP_IER_FIER7_Pos)
4111 #define GP_IER_FIER8_Pos (8)
4112 #define GP_IER_FIER8_Msk (0x1ul << GP_IER_FIER8_Pos)
4114 #define GP_IER_FIER9_Pos (9)
4115 #define GP_IER_FIER9_Msk (0x1ul << GP_IER_FIER9_Pos)
4117 #define GP_IER_FIER10_Pos (10)
4118 #define GP_IER_FIER10_Msk (0x1ul << GP_IER_FIER10_Pos)
4120 #define GP_IER_FIER11_Pos (11)
4121 #define GP_IER_FIER11_Msk (0x1ul << GP_IER_FIER11_Pos)
4123 #define GP_IER_FIER12_Pos (12)
4124 #define GP_IER_FIER12_Msk (0x1ul << GP_IER_FIER12_Pos)
4126 #define GP_IER_FIER13_Pos (13)
4127 #define GP_IER_FIER13_Msk (0x1ul << GP_IER_FIER13_Pos)
4129 #define GP_IER_FIER14_Pos (14)
4130 #define GP_IER_FIER14_Msk (0x1ul << GP_IER_FIER14_Pos)
4132 #define GP_IER_FIER15_Pos (15)
4133 #define GP_IER_FIER15_Msk (0x1ul << GP_IER_FIER15_Pos)
4135 #define GP_IER_RIER0_Pos (16)
4136 #define GP_IER_RIER0_Msk (0x1ul << GP_IER_RIER0_Pos)
4138 #define GP_IER_RIER1_Pos (17)
4139 #define GP_IER_RIER1_Msk (0x1ul << GP_IER_RIER1_Pos)
4141 #define GP_IER_RIER2_Pos (18)
4142 #define GP_IER_RIER2_Msk (0x1ul << GP_IER_RIER2_Pos)
4144 #define GP_IER_RIER3_Pos (19)
4145 #define GP_IER_RIER3_Msk (0x1ul << GP_IER_RIER3_Pos)
4147 #define GP_IER_RIER4_Pos (20)
4148 #define GP_IER_RIER4_Msk (0x1ul << GP_IER_RIER4_Pos)
4150 #define GP_IER_RIER5_Pos (21)
4151 #define GP_IER_RIER5_Msk (0x1ul << GP_IER_RIER5_Pos)
4153 #define GP_IER_RIER6_Pos (22)
4154 #define GP_IER_RIER6_Msk (0x1ul << GP_IER_RIER6_Pos)
4156 #define GP_IER_RIER7_Pos (23)
4157 #define GP_IER_RIER7_Msk (0x1ul << GP_IER_RIER7_Pos)
4159 #define GP_IER_RIER8_Pos (24)
4160 #define GP_IER_RIER8_Msk (0x1ul << GP_IER_RIER8_Pos)
4162 #define GP_IER_RIER9_Pos (25)
4163 #define GP_IER_RIER9_Msk (0x1ul << GP_IER_RIER9_Pos)
4165 #define GP_IER_RIER10_Pos (26)
4166 #define GP_IER_RIER10_Msk (0x1ul << GP_IER_RIER10_Pos)
4168 #define GP_IER_RIER11_Pos (27)
4169 #define GP_IER_RIER11_Msk (0x1ul << GP_IER_RIER11_Pos)
4171 #define GP_IER_RIER12_Pos (28)
4172 #define GP_IER_RIER12_Msk (0x1ul << GP_IER_RIER12_Pos)
4174 #define GP_IER_RIER13_Pos (29)
4175 #define GP_IER_RIER13_Msk (0x1ul << GP_IER_RIER13_Pos)
4177 #define GP_IER_RIER14_Pos (30)
4178 #define GP_IER_RIER14_Msk (0x1ul << GP_IER_RIER14_Pos)
4180 #define GP_IER_RIER15_Pos (31)
4181 #define GP_IER_RIER15_Msk (0x1ul << GP_IER_RIER15_Pos)
4183 #define GP_ISRC_ISRC_Pos (0)
4184 #define GP_ISRC_ISRC_Msk (0xfffful << GP_ISRC_ISRC_Pos)
4186 #define GP_PUEN_PUEN_Pos (0)
4187 #define GP_PUEN_PUEN_Msk (0xfffful << GP_PUEN_PUEN_Pos) /* GPIO_CONST */
4189
4194 #define GP_DBNCECON_DBCLKSEL_Pos (0)
4195 #define GP_DBNCECON_DBCLKSEL_Msk (0xful << GP_DBNCECON_DBCLKSEL_Pos)
4197 #define GP_DBNCECON_DBCLKSRC_Pos (4)
4198 #define GP_DBNCECON_DBCLKSRC_Msk (0x1ul << GP_DBNCECON_DBCLKSRC_Pos)
4200 #define GP_DBNCECON_DBCLK_ON_Pos (5)
4201 #define GP_DBNCECON_DBCLK_ON_Msk (0x1ul << GP_DBNCECON_DBCLK_ON_Pos) /* GP_DB_CONST */
4205 /* end of GP register group */
4206
4207
4208 /*---------------------- Inter-IC Bus Controller -------------------------*/
4214 typedef struct
4215 {
4216
4217
4253 __IO uint32_t CON;
4254
4269 __IO uint32_t INTSTS;
4270
4291 __I uint32_t STATUS;
4292
4304 __IO uint32_t DIV;
4305
4323 __IO uint32_t TOUT;
4324
4343 __IO uint32_t DATA;
4344
4364 __IO uint32_t SADDR0;
4365
4385 __IO uint32_t SADDR1;
4386 uint32_t RESERVE0[2];
4387
4388
4403 __IO uint32_t SAMASK0;
4404
4419 __IO uint32_t SAMASK1;
4420 uint32_t RESERVE1[4];
4421
4422
4434 __IO uint32_t WKUPCON;
4435
4448 __IO uint32_t WKUPSTS;
4449
4450 } I2C_T;
4451
4457 #define I2C_CON_IPEN_Pos (0)
4458 #define I2C_CON_IPEN_Msk (0x1ul << I2C_CON_IPEN_Pos)
4460 #define I2C_CON_ACK_Pos (1)
4461 #define I2C_CON_ACK_Msk (0x1ul << I2C_CON_ACK_Pos)
4463 #define I2C_CON_STOP_Pos (2)
4464 #define I2C_CON_STOP_Msk (0x1ul << I2C_CON_STOP_Pos)
4466 #define I2C_CON_START_Pos (3)
4467 #define I2C_CON_START_Msk (0x1ul << I2C_CON_START_Pos)
4469 #define I2C_CON_I2C_STS_Pos (4)
4470 #define I2C_CON_I2C_STS_Msk (0x1ul << I2C_CON_I2C_STS_Pos)
4472 #define I2C_CON_INTEN_Pos (7)
4473 #define I2C_CON_INTEN_Msk (0x1ul << I2C_CON_INTEN_Pos)
4475 #define I2C_INTSTS_INTSTS_Pos (0)
4476 #define I2C_INTSTS_INTSTS_Msk (0x1ul << I2C_INTSTS_INTSTS_Pos)
4478 #define I2C_INTSTS_TIF_Pos (1)
4479 #define I2C_INTSTS_TIF_Msk (0x1ul << I2C_INTSTS_TIF_Pos)
4481 #define I2C_STATUS_STATUS_Pos (0)
4482 #define I2C_STATUS_STATUS_Msk (0xfful << I2C_STATUS_STATUS_Pos)
4484 #define I2C_DIV_CLK_DIV_Pos (0)
4485 #define I2C_DIV_CLK_DIV_Msk (0xfful << I2C_DIV_CLK_DIV_Pos)
4487 #define I2C_TOUT_TOUTEN_Pos (0)
4488 #define I2C_TOUT_TOUTEN_Msk (0x1ul << I2C_TOUT_TOUTEN_Pos)
4490 #define I2C_TOUT_DIV4_Pos (1)
4491 #define I2C_TOUT_DIV4_Msk (0x1ul << I2C_TOUT_DIV4_Pos)
4493 #define I2C_DATA_DATA_Pos (0)
4494 #define I2C_DATA_DATA_Msk (0xfful << I2C_DATA_DATA_Pos)
4496 #define I2C_SADDR0_GCALL_Pos (0)
4497 #define I2C_SADDR0_GCALL_Msk (0x1ul << I2C_SADDR0_GCALL_Pos)
4499 #define I2C_SADDR0_SADDR_Pos (1)
4500 #define I2C_SADDR0_SADDR_Msk (0x7ful << I2C_SADDR0_SADDR_Pos)
4502 #define I2C_SADDR1_GCALL_Pos (0)
4503 #define I2C_SADDR1_GCALL_Msk (0x1ul << I2C_SADDR1_GCALL_Pos)
4505 #define I2C_SADDR1_SADDR_Pos (1)
4506 #define I2C_SADDR1_SADDR_Msk (0x7ful << I2C_SADDR1_SADDR_Pos)
4508 #define I2C_SAMASK0_SAMASK_Pos (1)
4509 #define I2C_SAMASK0_SAMASK_Msk (0x7ful << I2C_SAMASK0_SAMASK_Pos)
4511 #define I2C_SAMASK1_SAMASK_Pos (1)
4512 #define I2C_SAMASK1_SAMASK_Msk (0x7ful << I2C_SAMASK1_SAMASK_Pos)
4514 #define I2C_WKUPCON_WKUPEN_Pos (0)
4515 #define I2C_WKUPCON_WKUPEN_Msk (0x1ul << I2C_WKUPCON_WKUPEN_Pos)
4517 #define I2C_WKUPSTS_WKUPIF_Pos (0)
4518 #define I2C_WKUPSTS_WKUPIF_Msk (0x1ul << I2C_WKUPSTS_WKUPIF_Pos) /* I2C_CONST */
4521 /* end of I2C register group */
4522
4523
4524 /*---------------------- I2S Interface Controller -------------------------*/
4530 typedef struct
4531 {
4532
4533
4624 __IO uint32_t CTRL;
4625
4643 __IO uint32_t CLKDIV;
4644
4685 __IO uint32_t INTEN;
4686
4786 __IO uint32_t STATUS;
4787
4801 __O uint32_t TXFIFO;
4802
4816 __I uint32_t RXFIFO;
4817
4818 } I2S_T;
4819
4825 #define I2S_CTRL_I2SEN_Pos (0)
4826 #define I2S_CTRL_I2SEN_Msk (0x1ul << I2S_CTRL_I2SEN_Pos)
4828 #define I2S_CTRL_TXEN_Pos (1)
4829 #define I2S_CTRL_TXEN_Msk (0x1ul << I2S_CTRL_TXEN_Pos)
4831 #define I2S_CTRL_RXEN_Pos (2)
4832 #define I2S_CTRL_RXEN_Msk (0x1ul << I2S_CTRL_RXEN_Pos)
4834 #define I2S_CTRL_MUTE_Pos (3)
4835 #define I2S_CTRL_MUTE_Msk (0x1ul << I2S_CTRL_MUTE_Pos)
4837 #define I2S_CTRL_WORDWIDTH_Pos (4)
4838 #define I2S_CTRL_WORDWIDTH_Msk (0x3ul << I2S_CTRL_WORDWIDTH_Pos)
4840 #define I2S_CTRL_MONO_Pos (6)
4841 #define I2S_CTRL_MONO_Msk (0x1ul << I2S_CTRL_MONO_Pos)
4843 #define I2S_CTRL_FORMAT_Pos (7)
4844 #define I2S_CTRL_FORMAT_Msk (0x1ul << I2S_CTRL_FORMAT_Pos)
4846 #define I2S_CTRL_SLAVE_Pos (8)
4847 #define I2S_CTRL_SLAVE_Msk (0x1ul << I2S_CTRL_SLAVE_Pos)
4849 #define I2S_CTRL_TXTH_Pos (9)
4850 #define I2S_CTRL_TXTH_Msk (0x7ul << I2S_CTRL_TXTH_Pos)
4852 #define I2S_CTRL_RXTH_Pos (12)
4853 #define I2S_CTRL_RXTH_Msk (0x7ul << I2S_CTRL_RXTH_Pos)
4855 #define I2S_CTRL_MCLKEN_Pos (15)
4856 #define I2S_CTRL_MCLKEN_Msk (0x1ul << I2S_CTRL_MCLKEN_Pos)
4858 #define I2S_CTRL_RCHZCEN_Pos (16)
4859 #define I2S_CTRL_RCHZCEN_Msk (0x1ul << I2S_CTRL_RCHZCEN_Pos)
4861 #define I2S_CTRL_LCHZCEN_Pos (17)
4862 #define I2S_CTRL_LCHZCEN_Msk (0x1ul << I2S_CTRL_LCHZCEN_Pos)
4864 #define I2S_CTRL_CLR_TXFIFO_Pos (18)
4865 #define I2S_CTRL_CLR_TXFIFO_Msk (0x1ul << I2S_CTRL_CLR_TXFIFO_Pos)
4867 #define I2S_CTRL_CLR_RXFIFO_Pos (19)
4868 #define I2S_CTRL_CLR_RXFIFO_Msk (0x1ul << I2S_CTRL_CLR_RXFIFO_Pos)
4870 #define I2S_CTRL_TXDMA_Pos (20)
4871 #define I2S_CTRL_TXDMA_Msk (0x1ul << I2S_CTRL_TXDMA_Pos)
4873 #define I2S_CTRL_RXDMA_Pos (21)
4874 #define I2S_CTRL_RXDMA_Msk (0x1ul << I2S_CTRL_RXDMA_Pos)
4876 #define I2S_CTRL_RXLCH_Pos (23)
4877 #define I2S_CTRL_RXLCH_Msk (0x1ul << I2S_CTRL_RXLCH_Pos)
4879 #define I2S_CLKDIV_MCLK_DIV_Pos (0)
4880 #define I2S_CLKDIV_MCLK_DIV_Msk (0x7ul << I2S_CLKDIV_MCLK_DIV_Pos)
4882 #define I2S_CLKDIV_BCLK_DIV_Pos (8)
4883 #define I2S_CLKDIV_BCLK_DIV_Msk (0xfful << I2S_CLKDIV_BCLK_DIV_Pos)
4885 #define I2S_INTEN_RXUDFIE_Pos (0)
4886 #define I2S_INTEN_RXUDFIE_Msk (0x1ul << I2S_INTEN_RXUDFIE_Pos)
4888 #define I2S_INTEN_RXOVFIE_Pos (1)
4889 #define I2S_INTEN_RXOVFIE_Msk (0x1ul << I2S_INTEN_RXOVFIE_Pos)
4891 #define I2S_INTEN_RXTHIE_Pos (2)
4892 #define I2S_INTEN_RXTHIE_Msk (0x1ul << I2S_INTEN_RXTHIE_Pos)
4894 #define I2S_INTEN_TXUDFIE_Pos (8)
4895 #define I2S_INTEN_TXUDFIE_Msk (0x1ul << I2S_INTEN_TXUDFIE_Pos)
4897 #define I2S_INTEN_TXOVFIE_Pos (9)
4898 #define I2S_INTEN_TXOVFIE_Msk (0x1ul << I2S_INTEN_TXOVFIE_Pos)
4900 #define I2S_INTEN_TXTHIE_Pos (10)
4901 #define I2S_INTEN_TXTHIE_Msk (0x1ul << I2S_INTEN_TXTHIE_Pos)
4903 #define I2S_INTEN_RZCIE_Pos (11)
4904 #define I2S_INTEN_RZCIE_Msk (0x1ul << I2S_INTEN_RZCIE_Pos)
4906 #define I2S_INTEN_LZCIE_Pos (12)
4907 #define I2S_INTEN_LZCIE_Msk (0x1ul << I2S_INTEN_LZCIE_Pos)
4909 #define I2S_STATUS_I2SINT_Pos (0)
4910 #define I2S_STATUS_I2SINT_Msk (0x1ul << I2S_STATUS_I2SINT_Pos)
4912 #define I2S_STATUS_I2SRXINT_Pos (1)
4913 #define I2S_STATUS_I2SRXINT_Msk (0x1ul << I2S_STATUS_I2SRXINT_Pos)
4915 #define I2S_STATUS_I2STXINT_Pos (2)
4916 #define I2S_STATUS_I2STXINT_Msk (0x1ul << I2S_STATUS_I2STXINT_Pos)
4918 #define I2S_STATUS_RIGHT_Pos (3)
4919 #define I2S_STATUS_RIGHT_Msk (0x1ul << I2S_STATUS_RIGHT_Pos)
4921 #define I2S_STATUS_RXUDF_Pos (8)
4922 #define I2S_STATUS_RXUDF_Msk (0x1ul << I2S_STATUS_RXUDF_Pos)
4924 #define I2S_STATUS_RXOVF_Pos (9)
4925 #define I2S_STATUS_RXOVF_Msk (0x1ul << I2S_STATUS_RXOVF_Pos)
4927 #define I2S_STATUS_RXTHF_Pos (10)
4928 #define I2S_STATUS_RXTHF_Msk (0x1ul << I2S_STATUS_RXTHF_Pos)
4930 #define I2S_STATUS_RXFULL_Pos (11)
4931 #define I2S_STATUS_RXFULL_Msk (0x1ul << I2S_STATUS_RXFULL_Pos)
4933 #define I2S_STATUS_RXEMPTY_Pos (12)
4934 #define I2S_STATUS_RXEMPTY_Msk (0x1ul << I2S_STATUS_RXEMPTY_Pos)
4936 #define I2S_STATUS_TXUDF_Pos (16)
4937 #define I2S_STATUS_TXUDF_Msk (0x1ul << I2S_STATUS_TXUDF_Pos)
4939 #define I2S_STATUS_TXOVF_Pos (17)
4940 #define I2S_STATUS_TXOVF_Msk (0x1ul << I2S_STATUS_TXOVF_Pos)
4942 #define I2S_STATUS_TXTHF_Pos (18)
4943 #define I2S_STATUS_TXTHF_Msk (0x1ul << I2S_STATUS_TXTHF_Pos)
4945 #define I2S_STATUS_TXFULL_Pos (19)
4946 #define I2S_STATUS_TXFULL_Msk (0x1ul << I2S_STATUS_TXFULL_Pos)
4948 #define I2S_STATUS_TXEMPTY_Pos (20)
4949 #define I2S_STATUS_TXEMPTY_Msk (0x1ul << I2S_STATUS_TXEMPTY_Pos)
4951 #define I2S_STATUS_TXBUSY_Pos (21)
4952 #define I2S_STATUS_TXBUSY_Msk (0x1ul << I2S_STATUS_TXBUSY_Pos)
4954 #define I2S_STATUS_RZCF_Pos (22)
4955 #define I2S_STATUS_RZCF_Msk (0x1ul << I2S_STATUS_RZCF_Pos)
4957 #define I2S_STATUS_LZCF_Pos (23)
4958 #define I2S_STATUS_LZCF_Msk (0x1ul << I2S_STATUS_LZCF_Pos)
4960 #define I2S_STATUS_RX_LEVEL_Pos (24)
4961 #define I2S_STATUS_RX_LEVEL_Msk (0xful << I2S_STATUS_RX_LEVEL_Pos)
4963 #define I2S_STATUS_TX_LEVEL_Pos (28)
4964 #define I2S_STATUS_TX_LEVEL_Msk (0xful << I2S_STATUS_TX_LEVEL_Pos)
4966 #define I2S_TXFIFO_TXFIFO_Pos (0)
4967 #define I2S_TXFIFO_TXFIFO_Msk (0xfffffffful << I2S_TXFIFO_TXFIFO_Pos)
4969 #define I2S_RXFIFO_RXFIFO_Pos (0)
4970 #define I2S_RXFIFO_RXFIFO_Msk (0xfffffffful << I2S_RXFIFO_RXFIFO_Pos) /* I2S_CONST */
4973 /* end of I2S register group */
4974
4975
4976 /*---------------------- Interrupt Controller -------------------------*/
4982 typedef struct
4983 {
4984
4985
4996 __I uint32_t IRQSRC[32];
4997
4998
5009 __IO uint32_t NMI_SEL;
5010
5028 __IO uint32_t MCU_IRQ;
5029
5030 } INTR_T;
5031
5037 #define INTR_IRQSRC_INT_SRC_Pos (0)
5038 #define INTR_IRQSRC_INT_SRC_Msk (0xful << INTR_IRQ0SRC_INT_SRC_Pos)
5040 #define INTR_NMI_SEL_NMISEL_Pos (0)
5041 #define INTR_NMI_SEL_NMISEL_Msk (0x1ful << INTR_NMI_SEL_NMISEL_Pos)
5043 #define INTR_MCU_IRQ_MCU_IRQ_Pos (0)
5044 #define INTR_MCU_IRQ_MCU_IRQ_Msk (0xfffffffful << INTR_MCU_IRQ_MCU_IRQ_Pos) /* INTR_CONST */
5047 /* end of INTR register group */
5048
5049
5050 /*---------------------- LCD Controller -------------------------*/
5056 typedef struct
5057 {
5058
5059
5103 __IO uint32_t CTL;
5104
5147 __IO uint32_t DISPCTL;
5148
5165 __IO uint32_t MEM_0;
5166
5183 __IO uint32_t MEM_1;
5184
5201 __IO uint32_t MEM_2;
5202
5219 __IO uint32_t MEM_3;
5220
5237 __IO uint32_t MEM_4;
5238
5255 __IO uint32_t MEM_5;
5256
5273 __IO uint32_t MEM_6;
5274
5291 __IO uint32_t MEM_7;
5292
5309 __IO uint32_t MEM_8;
5310
5327 __IO uint32_t MEM_9;
5328
5350 __IO uint32_t FCR;
5351
5367 __IO uint32_t FCSTS;
5368
5369 } LCD_T;
5370
5376 #define LCD_CTL_EN_Pos (0)
5377 #define LCD_CTL_EN_Msk (0x1ul << LCD_CTL_EN_Pos)
5379 #define LCD_CTL_MUX_Pos (1)
5380 #define LCD_CTL_MUX_Msk (0x7ul << LCD_CTL_MUX_Pos)
5382 #define LCD_CTL_FREQ_Pos (4)
5383 #define LCD_CTL_FREQ_Msk (0x7ul << LCD_CTL_FREQ_Pos)
5385 #define LCD_CTL_BLINK_Pos (7)
5386 #define LCD_CTL_BLINK_Msk (0x1ul << LCD_CTL_BLINK_Pos)
5388 #define LCD_CTL_PDDISP_EN_Pos (8)
5389 #define LCD_CTL_PDDISP_EN_Msk (0x1ul << LCD_CTL_PDDISP_EN_Pos)
5391 #define LCD_CTL_PDINT_EN_Pos (9)
5392 #define LCD_CTL_PDINT_EN_Msk (0x1ul << LCD_CTL_PDINT_EN_Pos)
5394 #define LCD_DISPCTL_CPUMP_EN_Pos (0)
5395 #define LCD_DISPCTL_CPUMP_EN_Msk (0x1ul << LCD_DISPCTL_CPUMP_EN_Pos)
5397 #define LCD_DISPCTL_BIAS_SEL_Pos (1)
5398 #define LCD_DISPCTL_BIAS_SEL_Msk (0x3ul << LCD_DISPCTL_BIAS_SEL_Pos)
5400 #define LCD_DISPCTL_IBRL_EN_Pos (4)
5401 #define LCD_DISPCTL_IBRL_EN_Msk (0x1ul << LCD_DISPCTL_IBRL_EN_Pos)
5403 #define LCD_DISPCTL_BV_SEL_Pos (6)
5404 #define LCD_DISPCTL_BV_SEL_Msk (0x1ul << LCD_DISPCTL_BV_SEL_Pos)
5406 #define LCD_DISPCTL_CPUMP_VOL_SET_Pos (8)
5407 #define LCD_DISPCTL_CPUMP_VOL_SET_Msk (0x7ul << LCD_DISPCTL_CPUMP_VOL_SET_Pos)
5409 #define LCD_DISPCTL_CPUMP_FREQ_Pos (11)
5410 #define LCD_DISPCTL_CPUMP_FREQ_Msk (0x7ul << LCD_DISPCTL_CPUMP_FREQ_Pos)
5412 #define LCD_MEM_0_SEG_0_4x_Pos (0)
5413 #define LCD_MEM_0_SEG_0_4x_Msk (0x3ful << LCD_MEM_0_SEG_0_4x_Pos)
5415 #define LCD_MEM_0_SEG_1_4x_Pos (8)
5416 #define LCD_MEM_0_SEG_1_4x_Msk (0x7ful << LCD_MEM_0_SEG_1_4x_Pos)
5418 #define LCD_MEM_0_SEG_2_4x_Pos (16)
5419 #define LCD_MEM_0_SEG_2_4x_Msk (0x3ful << LCD_MEM_0_SEG_2_4x_Pos)
5421 #define LCD_MEM_0_SEG_3_4x_Pos (24)
5422 #define LCD_MEM_0_SEG_3_4x_Msk (0x3ful << LCD_MEM_0_SEG_3_4x_Pos)
5424 #define LCD_MEM_1_SEG_0_4x_Pos (0)
5425 #define LCD_MEM_1_SEG_0_4x_Msk (0x3ful << LCD_MEM_1_SEG_0_4x_Pos)
5427 #define LCD_MEM_1_SEG_1_4x_Pos (8)
5428 #define LCD_MEM_1_SEG_1_4x_Msk (0x7ful << LCD_MEM_1_SEG_1_4x_Pos)
5430 #define LCD_MEM_1_SEG_2_4x_Pos (16)
5431 #define LCD_MEM_1_SEG_2_4x_Msk (0x3ful << LCD_MEM_1_SEG_2_4x_Pos)
5433 #define LCD_MEM_1_SEG_3_4x_Pos (24)
5434 #define LCD_MEM_1_SEG_3_4x_Msk (0x3ful << LCD_MEM_1_SEG_3_4x_Pos)
5436 #define LCD_MEM_2_SEG_0_4x_Pos (0)
5437 #define LCD_MEM_2_SEG_0_4x_Msk (0x3ful << LCD_MEM_2_SEG_0_4x_Pos)
5439 #define LCD_MEM_2_SEG_1_4x_Pos (8)
5440 #define LCD_MEM_2_SEG_1_4x_Msk (0x7ful << LCD_MEM_2_SEG_1_4x_Pos)
5442 #define LCD_MEM_2_SEG_2_4x_Pos (16)
5443 #define LCD_MEM_2_SEG_2_4x_Msk (0x3ful << LCD_MEM_2_SEG_2_4x_Pos)
5445 #define LCD_MEM_2_SEG_3_4x_Pos (24)
5446 #define LCD_MEM_2_SEG_3_4x_Msk (0x3ful << LCD_MEM_2_SEG_3_4x_Pos)
5448 #define LCD_MEM_3_SEG_0_4x_Pos (0)
5449 #define LCD_MEM_3_SEG_0_4x_Msk (0x3ful << LCD_MEM_3_SEG_0_4x_Pos)
5451 #define LCD_MEM_3_SEG_1_4x_Pos (8)
5452 #define LCD_MEM_3_SEG_1_4x_Msk (0x7ful << LCD_MEM_3_SEG_1_4x_Pos)
5454 #define LCD_MEM_3_SEG_2_4x_Pos (16)
5455 #define LCD_MEM_3_SEG_2_4x_Msk (0x3ful << LCD_MEM_3_SEG_2_4x_Pos)
5457 #define LCD_MEM_3_SEG_3_4x_Pos (24)
5458 #define LCD_MEM_3_SEG_3_4x_Msk (0x3ful << LCD_MEM_3_SEG_3_4x_Pos)
5460 #define LCD_MEM_4_SEG_0_4x_Pos (0)
5461 #define LCD_MEM_4_SEG_0_4x_Msk (0x3ful << LCD_MEM_4_SEG_0_4x_Pos)
5463 #define LCD_MEM_4_SEG_1_4x_Pos (8)
5464 #define LCD_MEM_4_SEG_1_4x_Msk (0x7ful << LCD_MEM_4_SEG_1_4x_Pos)
5466 #define LCD_MEM_4_SEG_2_4x_Pos (16)
5467 #define LCD_MEM_4_SEG_2_4x_Msk (0x3ful << LCD_MEM_4_SEG_2_4x_Pos)
5469 #define LCD_MEM_4_SEG_3_4x_Pos (24)
5470 #define LCD_MEM_4_SEG_3_4x_Msk (0x3ful << LCD_MEM_4_SEG_3_4x_Pos)
5472 #define LCD_MEM_5_SEG_0_4x_Pos (0)
5473 #define LCD_MEM_5_SEG_0_4x_Msk (0x3ful << LCD_MEM_5_SEG_0_4x_Pos)
5475 #define LCD_MEM_5_SEG_1_4x_Pos (8)
5476 #define LCD_MEM_5_SEG_1_4x_Msk (0x7ful << LCD_MEM_5_SEG_1_4x_Pos)
5478 #define LCD_MEM_5_SEG_2_4x_Pos (16)
5479 #define LCD_MEM_5_SEG_2_4x_Msk (0x3ful << LCD_MEM_5_SEG_2_4x_Pos)
5481 #define LCD_MEM_5_SEG_3_4x_Pos (24)
5482 #define LCD_MEM_5_SEG_3_4x_Msk (0x3ful << LCD_MEM_5_SEG_3_4x_Pos)
5484 #define LCD_MEM_6_SEG_0_4x_Pos (0)
5485 #define LCD_MEM_6_SEG_0_4x_Msk (0x3ful << LCD_MEM_6_SEG_0_4x_Pos)
5487 #define LCD_MEM_6_SEG_1_4x_Pos (8)
5488 #define LCD_MEM_6_SEG_1_4x_Msk (0x7ful << LCD_MEM_6_SEG_1_4x_Pos)
5490 #define LCD_MEM_6_SEG_2_4x_Pos (16)
5491 #define LCD_MEM_6_SEG_2_4x_Msk (0x3ful << LCD_MEM_6_SEG_2_4x_Pos)
5493 #define LCD_MEM_6_SEG_3_4x_Pos (24)
5494 #define LCD_MEM_6_SEG_3_4x_Msk (0x3ful << LCD_MEM_6_SEG_3_4x_Pos)
5496 #define LCD_MEM_7_SEG_0_4x_Pos (0)
5497 #define LCD_MEM_7_SEG_0_4x_Msk (0x3ful << LCD_MEM_7_SEG_0_4x_Pos)
5499 #define LCD_MEM_7_SEG_1_4x_Pos (8)
5500 #define LCD_MEM_7_SEG_1_4x_Msk (0x7ful << LCD_MEM_7_SEG_1_4x_Pos)
5502 #define LCD_MEM_7_SEG_2_4x_Pos (16)
5503 #define LCD_MEM_7_SEG_2_4x_Msk (0x3ful << LCD_MEM_7_SEG_2_4x_Pos)
5505 #define LCD_MEM_7_SEG_3_4x_Pos (24)
5506 #define LCD_MEM_7_SEG_3_4x_Msk (0x3ful << LCD_MEM_7_SEG_3_4x_Pos)
5508 #define LCD_MEM_8_SEG_0_4x_Pos (0)
5509 #define LCD_MEM_8_SEG_0_4x_Msk (0x3ful << LCD_MEM_8_SEG_0_4x_Pos)
5511 #define LCD_MEM_8_SEG_1_4x_Pos (8)
5512 #define LCD_MEM_8_SEG_1_4x_Msk (0x7ful << LCD_MEM_8_SEG_1_4x_Pos)
5514 #define LCD_MEM_8_SEG_2_4x_Pos (16)
5515 #define LCD_MEM_8_SEG_2_4x_Msk (0x3ful << LCD_MEM_8_SEG_2_4x_Pos)
5517 #define LCD_MEM_8_SEG_3_4x_Pos (24)
5518 #define LCD_MEM_8_SEG_3_4x_Msk (0x3ful << LCD_MEM_8_SEG_3_4x_Pos)
5520 #define LCD_MEM_9_SEG_0_4x_Pos (0)
5521 #define LCD_MEM_9_SEG_0_4x_Msk (0x3ful << LCD_MEM_9_SEG_0_4x_Pos)
5523 #define LCD_MEM_9_SEG_1_4x_Pos (8)
5524 #define LCD_MEM_9_SEG_1_4x_Msk (0x7ful << LCD_MEM_9_SEG_1_4x_Pos)
5526 #define LCD_MEM_9_SEG_2_4x_Pos (16)
5527 #define LCD_MEM_9_SEG_2_4x_Msk (0x3ful << LCD_MEM_9_SEG_2_4x_Pos)
5529 #define LCD_MEM_9_SEG_3_4x_Pos (24)
5530 #define LCD_MEM_9_SEG_3_4x_Msk (0x3ful << LCD_MEM_9_SEG_3_4x_Pos)
5532 #define LCD_FCR_FCEN_Pos (0)
5533 #define LCD_FCR_FCEN_Msk (0x1ul << LCD_FCR_FCEN_Pos)
5535 #define LCD_FCR_FCINTEN_Pos (1)
5536 #define LCD_FCR_FCINTEN_Msk (0x1ul << LCD_FCR_FCINTEN_Pos)
5538 #define LCD_FCR_PRESCL_Pos (2)
5539 #define LCD_FCR_PRESCL_Msk (0x3ul << LCD_FCR_PRESCL_Pos)
5541 #define LCD_FCR_FCV_Pos (4)
5542 #define LCD_FCR_FCV_Msk (0x3ful << LCD_FCR_FCV_Pos)
5544 #define LCD_FCSTS_FCSTS_Pos (0)
5545 #define LCD_FCSTS_FCSTS_Msk (0x1ul << LCD_FCSTS_FCSTS_Pos)
5547 #define LCD_FCSTS_PDSTS_Pos (1)
5548 #define LCD_FCSTS_PDSTS_Msk (0x1ul << LCD_FCSTS_PDSTS_Pos) /* LCD_CONST */
5551 /* end of LCD register group */
5552
5553
5554 /*---------------------- Peripheral Direct Memory Access Controller -------------------------*/
5561 typedef struct
5562 {
5563
5564
5618 __IO uint32_t CTL;
5619
5631 __IO uint32_t DMASAR;
5632 uint32_t RESERVE0[1];
5633
5634
5645 __IO uint32_t DMABCR;
5646 uint32_t RESERVE1[1];
5647
5648
5659 __I uint32_t DMACSAR;
5660 uint32_t RESERVE2[1];
5661
5662
5674 __I uint32_t DMACBCR;
5675
5690 __IO uint32_t DMAIER;
5691
5713 __IO uint32_t DMAISR;
5714 uint32_t RESERVE3[22];
5715
5716
5730 __IO uint32_t WDATA;
5731
5742 __IO uint32_t SEED;
5743
5754 __I uint32_t CHECKSUM;
5755
5756 } DMA_CRC_T;
5757
5758
5759 typedef struct
5760 {
5761
5762
5795 __IO uint32_t GCRCSR;
5796
5843 __IO uint32_t DSSR0;
5844
5868 __IO uint32_t DSSR1;
5869
5902 __I uint32_t GCRISR;
5903
5904 } DMA_GCR_T;
5905
5906
5907 typedef struct
5908 {
5961 __IO uint32_t CSR;
5962
5974 __IO uint32_t SAR;
5975
5987 __IO uint32_t DAR;
5988
6000 __IO uint32_t BCR;
6001 uint32_t RESERVE0[1];
6002
6003
6014 __I uint32_t CSAR;
6015
6026 __I uint32_t CDAR;
6027
6039 __I uint32_t CBCR;
6040
6061 __IO uint32_t IER;
6062
6094 __IO uint32_t ISR;
6095
6109 __IO uint32_t TCR;
6110
6111 } PDMA_T;
6112
6113
6114
6115 typedef struct
6116 {
6117
6118
6148 __IO uint32_t CSR;
6149
6160 __IO uint32_t SAR;
6161
6172 __IO uint32_t DAR;
6173
6185 __IO uint32_t BCR;
6186 uint32_t RESERVE0[1];
6187
6188
6199 __I uint32_t CSAR;
6200
6211 __I uint32_t CDAR;
6212
6223 __I uint32_t CBCR;
6224
6239 __IO uint32_t IER;
6240
6261 __IO uint32_t ISR;
6262 uint32_t RESERVE1[1];
6263
6264
6277 __IO uint32_t SASOCR;
6278
6289 __IO uint32_t DASOCR;
6290
6291 } VDMA_T;
6292
6293
6299 #define DMA_CRC_CTL_CRCCEN_Pos (0)
6300 #define DMA_CRC_CTL_CRCCEN_Msk (0x1ul << DMA_CRC_CTL_CRCCEN_Pos)
6302 #define DMA_CRC_CTL_CRC_RST_Pos (1)
6303 #define DMA_CRC_CTL_CRC_RST_Msk (0x1ul << DMA_CRC_CTL_CRC_RST_Pos)
6305 #define DMA_CRC_CTL_TRIG_EN_Pos (23)
6306 #define DMA_CRC_CTL_TRIG_EN_Msk (0x1ul << DMA_CRC_CTL_TRIG_EN_Pos)
6308 #define DMA_CRC_CTL_WDATA_RVS_Pos (24)
6309 #define DMA_CRC_CTL_WDATA_RVS_Msk (0x1ul << DMA_CRC_CTL_WDATA_RVS_Pos)
6311 #define DMA_CRC_CTL_CHECKSUM_RVS_Pos (25)
6312 #define DMA_CRC_CTL_CHECKSUM_RVS_Msk (0x1ul << DMA_CRC_CTL_CHECKSUM_RVS_Pos)
6314 #define DMA_CRC_CTL_WDATA_COM_Pos (26)
6315 #define DMA_CRC_CTL_WDATA_COM_Msk (0x1ul << DMA_CRC_CTL_WDATA_COM_Pos)
6317 #define DMA_CRC_CTL_CHECKSUM_COM_Pos (27)
6318 #define DMA_CRC_CTL_CHECKSUM_COM_Msk (0x1ul << DMA_CRC_CTL_CHECKSUM_COM_Pos)
6320 #define DMA_CRC_CTL_CPU_WDLEN_Pos (28)
6321 #define DMA_CRC_CTL_CPU_WDLEN_Msk (0x3ul << DMA_CRC_CTL_CPU_WDLEN_Pos)
6323 #define DMA_CRC_CTL_CRC_MODE_Pos (30)
6324 #define DMA_CRC_CTL_CRC_MODE_Msk (0x3ul << DMA_CRC_CTL_CRC_MODE_Pos)
6326 #define DMA_CRC_DMASAR_CRC_DMASAR_Pos (0)
6327 #define DMA_CRC_DMASAR_CRC_DMASAR_Msk (0xfffffffful << DMA_CRC_DMASAR_CRC_DMASAR_Pos)
6329 #define DMA_CRC_DMABCR_CRC_DMABCR_Pos (0)
6330 #define DMA_CRC_DMABCR_CRC_DMABCR_Msk (0xfffful << DMA_CRC_DMABCR_CRC_DMABCR_Pos)
6332 #define DMA_CRC_DMACSAR_CRC_DMACSAR_Pos (0)
6333 #define DMA_CRC_DMACSAR_CRC_DMACSAR_Msk (0xfffffffful << DMA_CRC_DMACSAR_CRC_DMACSAR_Pos)
6335 #define DMA_CRC_DMACBCR_CRC_DMACBCR_Pos (0)
6336 #define DMA_CRC_DMACBCR_CRC_DMACBCR_Msk (0xfffful << DMA_CRC_DMACBCR_CRC_DMACBCR_Pos)
6338 #define DMA_CRC_DMAIER_TABORT_IE_Pos (0)
6339 #define DMA_CRC_DMAIER_TABORT_IE_Msk (0x1ul << DMA_CRC_DMAIER_TABORT_IE_Pos)
6341 #define DMA_CRC_DMAIER_BLKD_IE_Pos (1)
6342 #define DMA_CRC_DMAIER_BLKD_IE_Msk (0x1ul << DMA_CRC_DMAIER_BLKD_IE_Pos)
6344 #define DMA_CRC_DMAISR_TABORT_IF_Pos (0)
6345 #define DMA_CRC_DMAISR_TABORT_IF_Msk (0x1ul << DMA_CRC_DMAISR_TABORT_IF_Pos)
6347 #define DMA_CRC_DMAISR_BLKD_IF_Pos (1)
6348 #define DMA_CRC_DMAISR_BLKD_IF_Msk (0x1ul << DMA_CRC_DMAISR_BLKD_IF_Pos)
6350 #define DMA_CRC_WDATA_CRC_WDATA_Pos (0)
6351 #define DMA_CRC_WDATA_CRC_WDATA_Msk (0xfffffffful << DMA_CRC_WDATA_CRC_WDATA_Pos)
6353 #define DMA_CRC_SEED_CRC_SEED_Pos (0)
6354 #define DMA_CRC_SEED_CRC_SEED_Msk (0xfffffffful << DMA_CRC_SEED_CRC_SEED_Pos)
6356 #define DMA_CRC_CHECKSUM_CRC_CHECKSUM_Pos (0)
6357 #define DMA_CRC_CHECKSUM_CRC_CHECKSUM_Msk (0xfffffffful << DMA_CRC_CHECKSUM_CRC_CHECKSUM_Pos) /* DMA_CRC_CONST */
6360
6361
6367 #define DMA_GCR_GCRCSR_CLK0_EN_Pos (8)
6368 #define DMA_GCR_GCRCSR_CLK0_EN_Msk (0x1ul << DMA_GCR_GCRCSR_CLK0_EN_Pos)
6370 #define DMA_GCR_GCRCSR_CLK1_EN_Pos (9)
6371 #define DMA_GCR_GCRCSR_CLK1_EN_Msk (0x1ul << DMA_GCR_GCRCSR_CLK1_EN_Pos)
6373 #define DMA_GCR_GCRCSR_CLK2_EN_Pos (10)
6374 #define DMA_GCR_GCRCSR_CLK2_EN_Msk (0x1ul << DMA_GCR_GCRCSR_CLK2_EN_Pos)
6376 #define DMA_GCR_GCRCSR_CLK3_EN_Pos (11)
6377 #define DMA_GCR_GCRCSR_CLK3_EN_Msk (0x1ul << DMA_GCR_GCRCSR_CLK3_EN_Pos)
6379 #define DMA_GCR_GCRCSR_CLK4_EN_Pos (12)
6380 #define DMA_GCR_GCRCSR_CLK4_EN_Msk (0x1ul << DMA_GCR_GCRCSR_CLK4_EN_Pos)
6382 #define DMA_GCR_GCRCSR_CLK5_EN_Pos (13)
6383 #define DMA_GCR_GCRCSR_CLK5_EN_Msk (0x1ul << DMA_GCR_GCRCSR_CLK5_EN_Pos)
6385 #define DMA_GCR_GCRCSR_CLK6_EN_Pos (14)
6386 #define DMA_GCR_GCRCSR_CLK6_EN_Msk (0x1ul << DMA_GCR_GCRCSR_CLK6_EN_Pos)
6388 #define DMA_GCR_GCRCSR_CRC_CLK_EN_Pos (24)
6389 #define DMA_GCR_GCRCSR_CRC_CLK_EN_Msk (0x1ul << DMA_GCR_GCRCSR_CRC_CLK_EN_Pos)
6391 #define DMA_GCR_DSSR0_CH1_SEL_Pos (8)
6392 #define DMA_GCR_DSSR0_CH1_SEL_Msk (0x1ful << DMA_GCR_DSSR0_CH1_SEL_Pos)
6394 #define DMA_GCR_DSSR0_CH2_SEL_Pos (16)
6395 #define DMA_GCR_DSSR0_CH2_SEL_Msk (0x1ful << DMA_GCR_DSSR0_CH2_SEL_Pos)
6397 #define DMA_GCR_DSSR0_CH3_SEL_Pos (24)
6398 #define DMA_GCR_DSSR0_CH3_SEL_Msk (0x1ful << DMA_GCR_DSSR0_CH3_SEL_Pos)
6400 #define DMA_GCR_DSSR1_CH4_SEL_Pos (0)
6401 #define DMA_GCR_DSSR1_CH4_SEL_Msk (0x1ful << DMA_GCR_DSSR1_CH4_SEL_Pos)
6403 #define DMA_GCR_DSSR1_CH5_SEL_Pos (8)
6404 #define DMA_GCR_DSSR1_CH5_SEL_Msk (0x1ful << DMA_GCR_DSSR1_CH5_SEL_Pos)
6406 #define DMA_GCR_DSSR1_CH6_SEL_Pos (16)
6407 #define DMA_GCR_DSSR1_CH6_SEL_Msk (0x1ful << DMA_GCR_DSSR1_CH6_SEL_Pos)
6409 #define DMA_GCR_GCRISR_INTR0_Pos (0)
6410 #define DMA_GCR_GCRISR_INTR0_Msk (0x1ul << DMA_GCR_GCRISR_INTR0_Pos)
6412 #define DMA_GCR_GCRISR_INTR1_Pos (1)
6413 #define DMA_GCR_GCRISR_INTR1_Msk (0x1ul << DMA_GCR_GCRISR_INTR1_Pos)
6415 #define DMA_GCR_GCRISR_INTR2_Pos (2)
6416 #define DMA_GCR_GCRISR_INTR2_Msk (0x1ul << DMA_GCR_GCRISR_INTR2_Pos)
6418 #define DMA_GCR_GCRISR_INTR3_Pos (3)
6419 #define DMA_GCR_GCRISR_INTR3_Msk (0x1ul << DMA_GCR_GCRISR_INTR3_Pos)
6421 #define DMA_GCR_GCRISR_INTR4_Pos (4)
6422 #define DMA_GCR_GCRISR_INTR4_Msk (0x1ul << DMA_GCR_GCRISR_INTR4_Pos)
6424 #define DMA_GCR_GCRISR_INTR5_Pos (5)
6425 #define DMA_GCR_GCRISR_INTR5_Msk (0x1ul << DMA_GCR_GCRISR_INTR5_Pos)
6427 #define DMA_GCR_GCRISR_INTR6_Pos (6)
6428 #define DMA_GCR_GCRISR_INTR6_Msk (0x1ul << DMA_GCR_GCRISR_INTR6_Pos)
6430 #define DMA_GCR_GCRISR_CRC_INTR_Pos (16)
6431 #define DMA_GCR_GCRISR_CRC_INTR_Msk (0x1ul << DMA_GCR_GCRISR_CRC_INTR_Pos) /* DMA_GCR_CONST */
6434
6435
6441 #define PDMA_CSR_PDMACEN_Pos (0)
6442 #define PDMA_CSR_PDMACEN_Msk (0x1ul << PDMA_CSR_PDMACEN_Pos)
6444 #define PDMA_CSR_SW_RST_Pos (1)
6445 #define PDMA_CSR_SW_RST_Msk (0x1ul << PDMA_CSR_SW_RST_Pos)
6447 #define PDMA_CSR_MODE_SEL_Pos (2)
6448 #define PDMA_CSR_MODE_SEL_Msk (0x3ul << PDMA_CSR_MODE_SEL_Pos)
6450 #define PDMA_CSR_SAD_SEL_Pos (4)
6451 #define PDMA_CSR_SAD_SEL_Msk (0x3ul << PDMA_CSR_SAD_SEL_Pos)
6453 #define PDMA_CSR_DAD_SEL_Pos (6)
6454 #define PDMA_CSR_DAD_SEL_Msk (0x3ul << PDMA_CSR_DAD_SEL_Pos)
6456 #define PDMA_CSR_TO_EN_Pos (12)
6457 #define PDMA_CSR_TO_EN_Msk (0x1ul << PDMA_CSR_TO_EN_Pos)
6459 #define PDMA_CSR_APB_TWS_Pos (19)
6460 #define PDMA_CSR_APB_TWS_Msk (0x3ul << PDMA_CSR_APB_TWS_Pos)
6462 #define PDMA_CSR_TRIG_EN_Pos (23)
6463 #define PDMA_CSR_TRIG_EN_Msk (0x1ul << PDMA_CSR_TRIG_EN_Pos)
6465 #define PDMA_SAR_PDMA_SAR_Pos (0)
6466 #define PDMA_SAR_PDMA_SAR_Msk (0xfffffffful << PDMA_SAR_PDMA_SAR_Pos)
6468 #define PDMA_DAR_PDMA_DAR_Pos (0)
6469 #define PDMA_DAR_PDMA_DAR_Msk (0xfffffffful << PDMA_DAR_PDMA_DAR_Pos)
6471 #define PDMA_BCR_PDMA_BCR_Pos (0)
6472 #define PDMA_BCR_PDMA_BCR_Msk (0xfffful << PDMA_BCR_PDMA_BCR_Pos)
6474 #define PDMA_CSAR_PDMA_CSAR_Pos (0)
6475 #define PDMA_CSAR_PDMA_CSAR_Msk (0xfffffffful << PDMA_CSAR_PDMA_CSAR_Pos)
6477 #define PDMA_CDAR_PDMA_CDAR_Pos (0)
6478 #define PDMA_CDAR_PDMA_CDAR_Msk (0xfffffffful << PDMA_CDAR_PDMA_CDAR_Pos)
6480 #define PDMA_CBCR_PDMA_CBCR_Pos (0)
6481 #define PDMA_CBCR_PDMA_CBCR_Msk (0xfffffful << PDMA_CBCR_PDMA_CBCR_Pos)
6483 #define PDMA_IER_TABORT_IE_Pos (0)
6484 #define PDMA_IER_TABORT_IE_Msk (0x1ul << PDMA_IER_TABORT_IE_Pos)
6486 #define PDMA_IER_TD_IE_Pos (1)
6487 #define PDMA_IER_TD_IE_Msk (0x1ul << PDMA_IER_TD_IE_Pos)
6489 #define PDMA_IER_WRA_BCR_IE_Pos (2)
6490 #define PDMA_IER_WRA_BCR_IE_Msk (0xful << PDMA_IER_WRA_BCR_IE_Pos)
6492 #define PDMA_IER_TO_IE_Pos (6)
6493 #define PDMA_IER_TO_IE_Msk (0x1ul << PDMA_IER_TO_IE_Pos)
6495 #define PDMA_ISR_TABORT_IS_Pos (0)
6496 #define PDMA_ISR_TABORT_IS_Msk (0x1ul << PDMA_ISR_TABORT_IS_Pos)
6498 #define PDMA_ISR_TD_IS_Pos (1)
6499 #define PDMA_ISR_TD_IS_Msk (0x1ul << PDMA_ISR_TD_IS_Pos)
6501 #define PDMA_ISR_WRA_BCR_IS_Pos (2)
6502 #define PDMA_ISR_WRA_BCR_IS_Msk (0xful << PDMA_ISR_WRA_BCR_IS_Pos)
6504 #define PDMA_ISR_TO_IS_Pos (6)
6505 #define PDMA_ISR_TO_IS_Msk (0x1ul << PDMA_ISR_TO_IS_Pos)
6507 #define PDMA_TCR_PDMA_TCR_Pos (0)
6508 #define PDMA_TCR_PDMA_TCR_Msk (0xfffful << PDMA_TCR_PDMA_TCR_Pos) /* PDMA_CONST */
6511
6512
6518 #define VDMA_CSR_VDMACEN_Pos (0)
6519 #define VDMA_CSR_VDMACEN_Msk (0x1ul << VDMA_CSR_VDMACEN_Pos)
6521 #define VDMA_CSR_SW_RST_Pos (1)
6522 #define VDMA_CSR_SW_RST_Msk (0x1ul << VDMA_CSR_SW_RST_Pos)
6524 #define VDMA_CSR_STRIDE_EN_Pos (10)
6525 #define VDMA_CSR_STRIDE_EN_Msk (0x1ul << VDMA_CSR_STRIDE_EN_Pos)
6527 #define VDMA_CSR_DIR_SEL_Pos (11)
6528 #define VDMA_CSR_DIR_SEL_Msk (0x1ul << VDMA_CSR_DIR_SEL_Pos)
6530 #define VDMA_CSR_TRIG_EN_Pos (23)
6531 #define VDMA_CSR_TRIG_EN_Msk (0x1ul << VDMA_CSR_TRIG_EN_Pos)
6533 #define VDMA_SAR_VDMA_SAR_Pos (0)
6534 #define VDMA_SAR_VDMA_SAR_Msk (0xfffffffful << VDMA_SAR_VDMA_SAR_Pos)
6536 #define VDMA_DAR_VDMA_DAR_Pos (0)
6537 #define VDMA_DAR_VDMA_DAR_Msk (0xfffffffful << VDMA_DAR_VDMA_DAR_Pos)
6539 #define VDMA_BCR_VDMA_BCR_Pos (0)
6540 #define VDMA_BCR_VDMA_BCR_Msk (0xfffful << VDMA_BCR_VDMA_BCR_Pos)
6542 #define VDMA_CSAR_VDMA_CSAR_Pos (0)
6543 #define VDMA_CSAR_VDMA_CSAR_Msk (0xfffffffful << VDMA_CSAR_VDMA_CSAR_Pos)
6545 #define VDMA_CDAR_VDMA_CDAR_Pos (0)
6546 #define VDMA_CDAR_VDMA_CDAR_Msk (0xfffffffful << VDMA_CDAR_VDMA_CDAR_Pos)
6548 #define VDMA_CBCR_VDMA_CBCR_Pos (0)
6549 #define VDMA_CBCR_VDMA_CBCR_Msk (0xfffful << VDMA_CBCR_VDMA_CBCR_Pos)
6551 #define VDMA_IER_TABORT_IE_Pos (0)
6552 #define VDMA_IER_TABORT_IE_Msk (0x1ul << VDMA_IER_TABORT_IE_Pos)
6554 #define VDMA_IER_TD_IE_Pos (1)
6555 #define VDMA_IER_TD_IE_Msk (0x1ul << VDMA_IER_TD_IE_Pos)
6557 #define VDMA_ISR_TABORT_IS_Pos (0)
6558 #define VDMA_ISR_TABORT_IS_Msk (0x1ul << VDMA_ISR_TABORT_IS_Pos)
6560 #define VDMA_ISR_TD_IS_Pos (1)
6561 #define VDMA_ISR_TD_IS_Msk (0x1ul << VDMA_ISR_TD_IS_Pos)
6563 #define VDMA_SASOCR_SASTOBL_Pos (0)
6564 #define VDMA_SASOCR_SASTOBL_Msk (0xfffful << VDMA_SASOCR_SASTOBL_Pos)
6566 #define VDMA_SASOCR_STBC_Pos (16)
6567 #define VDMA_SASOCR_STBC_Msk (0xfffful << VDMA_SASOCR_STBC_Pos)
6569 #define VDMA_DASOCR_DASTOBL_Pos (0)
6570 #define VDMA_DASOCR_DASTOBL_Msk (0xfffful << VDMA_DASOCR_DASTOBL_Pos) /* VDMA_CONST */
6573 /* end of DMA register group */
6575
6576
6577 /*---------------------- Pulse Width Modulation Controller -------------------------*/
6583 typedef struct
6584 {
6585
6586
6607 __IO uint32_t PRES;
6608
6633 __IO uint32_t CLKSEL;
6634
6691 __IO uint32_t CTL;
6692
6713 __IO uint32_t INTEN;
6714
6751 __IO uint32_t INTSTS;
6752
6777 __IO uint32_t OE;
6778 uint32_t RESERVE0[1];
6779
6780
6809 __IO uint32_t DUTY0;
6810
6828 __I uint32_t DATA0;
6829 uint32_t RESERVE1[1];
6830
6831
6860 __IO uint32_t DUTY1;
6861
6879 __I uint32_t DATA1;
6880 uint32_t RESERVE2[1];
6881
6882
6911 __IO uint32_t DUTY2;
6912
6930 __I uint32_t DATA2;
6931 uint32_t RESERVE3[1];
6932
6933
6960 __IO uint32_t DUTY3;
6961
6979 __I uint32_t DATA3;
6980 uint32_t RESERVE4[3];
6981
6982
7085 __IO uint32_t CAPCTL;
7086
7127 __IO uint32_t CAPINTEN;
7128
7189 __IO uint32_t CAPINTSTS;
7190
7203 __I uint32_t CRL0;
7204
7217 __I uint32_t CFL0;
7218
7231 __I uint32_t CRL1;
7232
7245 __I uint32_t CFL1;
7246
7259 __I uint32_t CRL2;
7260
7273 __I uint32_t CFL2;
7274
7287 __I uint32_t CRL3;
7288
7301 __I uint32_t CFL3;
7302
7323 __I uint32_t PDMACH0;
7324
7345 __I uint32_t PDMACH2;
7346
7347 } PWM_T;
7348
7354 #define PWM_PRES_CP01_Pos (0)
7355 #define PWM_PRES_CP01_Msk (0xfful << PWM_PRES_CP01_Pos)
7357 #define PWM_PRES_CP23_Pos (8)
7358 #define PWM_PRES_CP23_Msk (0xfful << PWM_PRES_CP23_Pos)
7360 #define PWM_PRES_DZ01_Pos (16)
7361 #define PWM_PRES_DZ01_Msk (0xfful << PWM_PRES_DZ01_Pos)
7363 #define PWM_PRES_DZ23_Pos (24)
7364 #define PWM_PRES_DZ23_Msk (0xfful << PWM_PRES_DZ23_Pos)
7366 #define PWM_CLKSEL_CLKSEL0_Pos (0)
7367 #define PWM_CLKSEL_CLKSEL0_Msk (0x7ul << PWM_CLKSEL_CLKSEL0_Pos)
7369 #define PWM_CLKSEL_CLKSEL1_Pos (4)
7370 #define PWM_CLKSEL_CLKSEL1_Msk (0x7ul << PWM_CLKSEL_CLKSEL1_Pos)
7372 #define PWM_CLKSEL_CLKSEL2_Pos (8)
7373 #define PWM_CLKSEL_CLKSEL2_Msk (0x7ul << PWM_CLKSEL_CLKSEL2_Pos)
7375 #define PWM_CLKSEL_CLKSEL3_Pos (12)
7376 #define PWM_CLKSEL_CLKSEL3_Msk (0x7ul << PWM_CLKSEL_CLKSEL3_Pos)
7378 #define PWM_CTL_CH0EN_Pos (0)
7379 #define PWM_CTL_CH0EN_Msk (0x1ul << PWM_CTL_CH0EN_Pos)
7381 #define PWM_CTL_CH0INV_Pos (2)
7382 #define PWM_CTL_CH0INV_Msk (0x1ul << PWM_CTL_CH0INV_Pos)
7384 #define PWM_CTL_CH0MOD_Pos (3)
7385 #define PWM_CTL_CH0MOD_Msk (0x1ul << PWM_CTL_CH0MOD_Pos)
7387 #define PWM_CTL_DZEN01_Pos (4)
7388 #define PWM_CTL_DZEN01_Msk (0x1ul << PWM_CTL_DZEN01_Pos)
7390 #define PWM_CTL_DZEN23_Pos (5)
7391 #define PWM_CTL_DZEN23_Msk (0x1ul << PWM_CTL_DZEN23_Pos)
7393 #define PWM_CTL_CH1EN_Pos (8)
7394 #define PWM_CTL_CH1EN_Msk (0x1ul << PWM_CTL_CH1EN_Pos)
7396 #define PWM_CTL_CH1INV_Pos (10)
7397 #define PWM_CTL_CH1INV_Msk (0x1ul << PWM_CTL_CH1INV_Pos)
7399 #define PWM_CTL_CH1MOD_Pos (11)
7400 #define PWM_CTL_CH1MOD_Msk (0x1ul << PWM_CTL_CH1MOD_Pos)
7402 #define PWM_CTL_CH2EN_Pos (16)
7403 #define PWM_CTL_CH2EN_Msk (0x1ul << PWM_CTL_CH2EN_Pos)
7405 #define PWM_CTL_CH2INV_Pos (18)
7406 #define PWM_CTL_CH2INV_Msk (0x1ul << PWM_CTL_CH2INV_Pos)
7408 #define PWM_CTL_CH2MOD_Pos (19)
7409 #define PWM_CTL_CH2MOD_Msk (0x1ul << PWM_CTL_CH2MOD_Pos)
7411 #define PWM_CTL_CH3EN_Pos (24)
7412 #define PWM_CTL_CH3EN_Msk (0x1ul << PWM_CTL_CH3EN_Pos)
7414 #define PWM_CTL_CH3INV_Pos (26)
7415 #define PWM_CTL_CH3INV_Msk (0x1ul << PWM_CTL_CH3INV_Pos)
7417 #define PWM_CTL_CH3MOD_Pos (27)
7418 #define PWM_CTL_CH3MOD_Msk (0x1ul << PWM_CTL_CH3MOD_Pos)
7420 #define PWM_INTEN_TMIE0_Pos (0)
7421 #define PWM_INTEN_TMIE0_Msk (0x1ul << PWM_INTEN_TMIE0_Pos)
7423 #define PWM_INTEN_TMIE1_Pos (1)
7424 #define PWM_INTEN_TMIE1_Msk (0x1ul << PWM_INTEN_TMIE1_Pos)
7426 #define PWM_INTEN_TMIE2_Pos (2)
7427 #define PWM_INTEN_TMIE2_Msk (0x1ul << PWM_INTEN_TMIE2_Pos)
7429 #define PWM_INTEN_TMIE3_Pos (3)
7430 #define PWM_INTEN_TMIE3_Msk (0x1ul << PWM_INTEN_TMIE3_Pos)
7432 #define PWM_INTSTS_TMINT0_Pos (0)
7433 #define PWM_INTSTS_TMINT0_Msk (0x1ul << PWM_INTSTS_TMINT0_Pos)
7435 #define PWM_INTSTS_TMINT1_Pos (1)
7436 #define PWM_INTSTS_TMINT1_Msk (0x1ul << PWM_INTSTS_TMINT1_Pos)
7438 #define PWM_INTSTS_TMINT2_Pos (2)
7439 #define PWM_INTSTS_TMINT2_Msk (0x1ul << PWM_INTSTS_TMINT2_Pos)
7441 #define PWM_INTSTS_TMINT3_Pos (3)
7442 #define PWM_INTSTS_TMINT3_Msk (0x1ul << PWM_INTSTS_TMINT3_Pos)
7444 #define PWM_INTSTS_DUTY0SYNC_Pos (4)
7445 #define PWM_INTSTS_DUTY0SYNC_Msk (0x1ul << PWM_INTSTS_DUTY0SYNC_Pos)
7447 #define PWM_INTSTS_PRESSYNC_Pos (8)
7448 #define PWM_INTSTS_PRESSYNC_Msk (0x1ul << PWM_INTSTS_PRESSYNC_Pos)
7450 #define PWM_OE_CH0_OE_Pos (0)
7451 #define PWM_OE_CH0_OE_Msk (0x1ul << PWM_OE_CH0_OE_Pos)
7453 #define PWM_OE_CH1_OE_Pos (1)
7454 #define PWM_OE_CH1_OE_Msk (0x1ul << PWM_OE_CH1_OE_Pos)
7456 #define PWM_OE_CH2_OE_Pos (2)
7457 #define PWM_OE_CH2_OE_Msk (0x1ul << PWM_OE_CH2_OE_Pos)
7459 #define PWM_OE_CH3_OE_Pos (3)
7460 #define PWM_OE_CH3_OE_Msk (0x1ul << PWM_OE_CH3_OE_Pos)
7462 #define PWM_DUTY_CN_Pos (0)
7463 #define PWM_DUTY_CN_Msk (0xfffful << PWM_DUTY_CN_Pos)
7465 #define PWM_DUTY_CM_Pos (16)
7466 #define PWM_DUTY_CM_Msk (0xfffful << PWM_DUTY_CM_Pos)
7468 #define PWM_DATA0_PWMx_DATAy15_0_Pos (0)
7469 #define PWM_DATA0_PWMx_DATAy15_0_Msk (0xfffful << PWM_DATA0_PWMx_DATAy15_0_Pos)
7471 #define PWM_DATA0_PWMx_DATAy30_16_Pos (16)
7472 #define PWM_DATA0_PWMx_DATAy30_16_Msk (0x7ffful << PWM_DATA0_PWMx_DATAy30_16_Pos)
7474 #define PWM_DATA0_sync_Pos (31)
7475 #define PWM_DATA0_sync_Msk (0x1ul << PWM_DATA0_sync_Pos)
7477 #define PWM_DUTY1_CN_Pos (0)
7478 #define PWM_DUTY1_CN_Msk (0xfffful << PWM_DUTY1_CN_Pos)
7480 #define PWM_DUTY1_CM_Pos (16)
7481 #define PWM_DUTY1_CM_Msk (0xfffful << PWM_DUTY1_CM_Pos)
7483 #define PWM_DATA1_PWMx_DATAy15_0_Pos (0)
7484 #define PWM_DATA1_PWMx_DATAy15_0_Msk (0xfffful << PWM_DATA1_PWMx_DATAy15_0_Pos)
7486 #define PWM_DATA1_PWMx_DATAy30_16_Pos (16)
7487 #define PWM_DATA1_PWMx_DATAy30_16_Msk (0x7ffful << PWM_DATA1_PWMx_DATAy30_16_Pos)
7489 #define PWM_DATA1_sync_Pos (31)
7490 #define PWM_DATA1_sync_Msk (0x1ul << PWM_DATA1_sync_Pos)
7492 #define PWM_DUTY2_CN_Pos (0)
7493 #define PWM_DUTY2_CN_Msk (0xfffful << PWM_DUTY2_CN_Pos)
7495 #define PWM_DUTY2_CM_Pos (16)
7496 #define PWM_DUTY2_CM_Msk (0xfffful << PWM_DUTY2_CM_Pos)
7498 #define PWM_DATA2_PWMx_DATAy15_0_Pos (0)
7499 #define PWM_DATA2_PWMx_DATAy15_0_Msk (0xfffful << PWM_DATA2_PWMx_DATAy15_0_Pos)
7501 #define PWM_DATA2_PWMx_DATAy30_16_Pos (16)
7502 #define PWM_DATA2_PWMx_DATAy30_16_Msk (0x7ffful << PWM_DATA2_PWMx_DATAy30_16_Pos)
7504 #define PWM_DATA2_sync_Pos (31)
7505 #define PWM_DATA2_sync_Msk (0x1ul << PWM_DATA2_sync_Pos)
7507 #define PWM_DUTY3_CN_Pos (0)
7508 #define PWM_DUTY3_CN_Msk (0xfffful << PWM_DUTY3_CN_Pos)
7510 #define PWM_DUTY3_CM_Pos (16)
7511 #define PWM_DUTY3_CM_Msk (0xfffful << PWM_DUTY3_CM_Pos)
7513 #define PWM_DATA3_PWMx_DATAy15_0_Pos (0)
7514 #define PWM_DATA3_PWMx_DATAy15_0_Msk (0xfffful << PWM_DATA3_PWMx_DATAy15_0_Pos)
7516 #define PWM_DATA3_PWMx_DATAy30_16_Pos (16)
7517 #define PWM_DATA3_PWMx_DATAy30_16_Msk (0x7ffful << PWM_DATA3_PWMx_DATAy30_16_Pos)
7519 #define PWM_DATA3_sync_Pos (31)
7520 #define PWM_DATA3_sync_Msk (0x1ul << PWM_DATA3_sync_Pos)
7522 #define PWM_CAPCTL_INV0_Pos (0)
7523 #define PWM_CAPCTL_INV0_Msk (0x1ul << PWM_CAPCTL_INV0_Pos)
7525 #define PWM_CAPCTL_CAPCH0EN_Pos (1)
7526 #define PWM_CAPCTL_CAPCH0EN_Msk (0x1ul << PWM_CAPCTL_CAPCH0EN_Pos)
7528 #define PWM_CAPCTL_CAPCH0PADEN_Pos (2)
7529 #define PWM_CAPCTL_CAPCH0PADEN_Msk (0x1ul << PWM_CAPCTL_CAPCH0PADEN_Pos)
7531 #define PWM_CAPCTL_CH0PDMAEN_Pos (3)
7532 #define PWM_CAPCTL_CH0PDMAEN_Msk (0x1ul << PWM_CAPCTL_CH0PDMAEN_Pos)
7534 #define PWM_CAPCTL_PDMACAPMOD0_Pos (4)
7535 #define PWM_CAPCTL_PDMACAPMOD0_Msk (0x3ul << PWM_CAPCTL_PDMACAPMOD0_Pos)
7537 #define PWM_CAPCTL_CAPRELOADREN0_Pos (6)
7538 #define PWM_CAPCTL_CAPRELOADREN0_Msk (0x1ul << PWM_CAPCTL_CAPRELOADREN0_Pos)
7540 #define PWM_CAPCTL_CAPRELOADFEN0_Pos (7)
7541 #define PWM_CAPCTL_CAPRELOADFEN0_Msk (0x1ul << PWM_CAPCTL_CAPRELOADFEN0_Pos)
7543 #define PWM_CAPCTL_INV1_Pos (8)
7544 #define PWM_CAPCTL_INV1_Msk (0x1ul << PWM_CAPCTL_INV1_Pos)
7546 #define PWM_CAPCTL_CAPCH1EN_Pos (9)
7547 #define PWM_CAPCTL_CAPCH1EN_Msk (0x1ul << PWM_CAPCTL_CAPCH1EN_Pos)
7549 #define PWM_CAPCTL_CAPCH1PADEN_Pos (10)
7550 #define PWM_CAPCTL_CAPCH1PADEN_Msk (0x1ul << PWM_CAPCTL_CAPCH1PADEN_Pos)
7552 #define PWM_CAPCTL_CH0RFORDER_Pos (12)
7553 #define PWM_CAPCTL_CH0RFORDER_Msk (0x1ul << PWM_CAPCTL_CH0RFORDER_Pos)
7555 #define PWM_CAPCTL_CH01CASK_Pos (13)
7556 #define PWM_CAPCTL_CH01CASK_Msk (0x1ul << PWM_CAPCTL_CH01CASK_Pos)
7558 #define PWM_CAPCTL_CAPRELOADREN1_Pos (14)
7559 #define PWM_CAPCTL_CAPRELOADREN1_Msk (0x1ul << PWM_CAPCTL_CAPRELOADREN1_Pos)
7561 #define PWM_CAPCTL_CAPRELOADFEN1_Pos (15)
7562 #define PWM_CAPCTL_CAPRELOADFEN1_Msk (0x1ul << PWM_CAPCTL_CAPRELOADFEN1_Pos)
7564 #define PWM_CAPCTL_INV2_Pos (16)
7565 #define PWM_CAPCTL_INV2_Msk (0x1ul << PWM_CAPCTL_INV2_Pos)
7567 #define PWM_CAPCTL_CAPCH2EN_Pos (17)
7568 #define PWM_CAPCTL_CAPCH2EN_Msk (0x1ul << PWM_CAPCTL_CAPCH2EN_Pos)
7570 #define PWM_CAPCTL_CAPCH2PADEN_Pos (18)
7571 #define PWM_CAPCTL_CAPCH2PADEN_Msk (0x1ul << PWM_CAPCTL_CAPCH2PADEN_Pos)
7573 #define PWM_CAPCTL_CH2PDMAEN_Pos (19)
7574 #define PWM_CAPCTL_CH2PDMAEN_Msk (0x1ul << PWM_CAPCTL_CH2PDMAEN_Pos)
7576 #define PWM_CAPCTL_PDMACAPMOD2_Pos (20)
7577 #define PWM_CAPCTL_PDMACAPMOD2_Msk (0x3ul << PWM_CAPCTL_PDMACAPMOD2_Pos)
7579 #define PWM_CAPCTL_CAPRELOADREN2_Pos (22)
7580 #define PWM_CAPCTL_CAPRELOADREN2_Msk (0x1ul << PWM_CAPCTL_CAPRELOADREN2_Pos)
7582 #define PWM_CAPCTL_CAPRELOADFEN2_Pos (23)
7583 #define PWM_CAPCTL_CAPRELOADFEN2_Msk (0x1ul << PWM_CAPCTL_CAPRELOADFEN2_Pos)
7585 #define PWM_CAPCTL_INV3_Pos (24)
7586 #define PWM_CAPCTL_INV3_Msk (0x1ul << PWM_CAPCTL_INV3_Pos)
7588 #define PWM_CAPCTL_CAPCH3EN_Pos (25)
7589 #define PWM_CAPCTL_CAPCH3EN_Msk (0x1ul << PWM_CAPCTL_CAPCH3EN_Pos)
7591 #define PWM_CAPCTL_CAPCH3PADEN_Pos (26)
7592 #define PWM_CAPCTL_CAPCH3PADEN_Msk (0x1ul << PWM_CAPCTL_CAPCH3PADEN_Pos)
7594 #define PWM_CAPCTL_CH2RFORDER_Pos (28)
7595 #define PWM_CAPCTL_CH2RFORDER_Msk (0x1ul << PWM_CAPCTL_CH2RFORDER_Pos)
7597 #define PWM_CAPCTL_CH23CASK_Pos (29)
7598 #define PWM_CAPCTL_CH23CASK_Msk (0x1ul << PWM_CAPCTL_CH23CASK_Pos)
7600 #define PWM_CAPCTL_CAPRELOADREN3_Pos (30)
7601 #define PWM_CAPCTL_CAPRELOADREN3_Msk (0x1ul << PWM_CAPCTL_CAPRELOADREN3_Pos)
7603 #define PWM_CAPCTL_CAPRELOADFEN3_Pos (31)
7604 #define PWM_CAPCTL_CAPRELOADFEN3_Msk (0x1ul << PWM_CAPCTL_CAPRELOADFEN3_Pos)
7606 #define PWM_CAPINTEN_CRL_IE0_Pos (0)
7607 #define PWM_CAPINTEN_CRL_IE0_Msk (0x1ul << PWM_CAPINTEN_CRL_IE0_Pos)
7609 #define PWM_CAPINTEN_CFL_IE0_Pos (1)
7610 #define PWM_CAPINTEN_CFL_IE0_Msk (0x1ul << PWM_CAPINTEN_CFL_IE0_Pos)
7612 #define PWM_CAPINTEN_CRL_IE1_Pos (8)
7613 #define PWM_CAPINTEN_CRL_IE1_Msk (0x1ul << PWM_CAPINTEN_CRL_IE1_Pos)
7615 #define PWM_CAPINTEN_CFL_IE1_Pos (9)
7616 #define PWM_CAPINTEN_CFL_IE1_Msk (0x1ul << PWM_CAPINTEN_CFL_IE1_Pos)
7618 #define PWM_CAPINTEN_CRL_IE2_Pos (16)
7619 #define PWM_CAPINTEN_CRL_IE2_Msk (0x1ul << PWM_CAPINTEN_CRL_IE2_Pos)
7621 #define PWM_CAPINTEN_CFL_IE2_Pos (17)
7622 #define PWM_CAPINTEN_CFL_IE2_Msk (0x1ul << PWM_CAPINTEN_CFL_IE2_Pos)
7624 #define PWM_CAPINTEN_CRL_IE3_Pos (24)
7625 #define PWM_CAPINTEN_CRL_IE3_Msk (0x1ul << PWM_CAPINTEN_CRL_IE3_Pos)
7627 #define PWM_CAPINTEN_CFL_IE3_Pos (25)
7628 #define PWM_CAPINTEN_CFL_IE3_Msk (0x1ul << PWM_CAPINTEN_CFL_IE3_Pos)
7630 #define PWM_CAPINTSTS_CAPIF0_Pos (0)
7631 #define PWM_CAPINTSTS_CAPIF0_Msk (0x1ul << PWM_CAPINTSTS_CAPIF0_Pos)
7633 #define PWM_CAPINTSTS_CRLI0_Pos (1)
7634 #define PWM_CAPINTSTS_CRLI0_Msk (0x1ul << PWM_CAPINTSTS_CRLI0_Pos)
7636 #define PWM_CAPINTSTS_CFLRI0_Pos (2)
7637 #define PWM_CAPINTSTS_CFLRI0_Msk (0x1ul << PWM_CAPINTSTS_CFLRI0_Pos)
7639 #define PWM_CAPINTSTS_CAPOVR0_Pos (3)
7640 #define PWM_CAPINTSTS_CAPOVR0_Msk (0x1ul << PWM_CAPINTSTS_CAPOVR0_Pos)
7642 #define PWM_CAPINTSTS_CAPOVF0_Pos (4)
7643 #define PWM_CAPINTSTS_CAPOVF0_Msk (0x1ul << PWM_CAPINTSTS_CAPOVF0_Pos)
7645 #define PWM_CAPINTSTS_CAPIF1_Pos (8)
7646 #define PWM_CAPINTSTS_CAPIF1_Msk (0x1ul << PWM_CAPINTSTS_CAPIF1_Pos)
7648 #define PWM_CAPINTSTS_CRLI1_Pos (9)
7649 #define PWM_CAPINTSTS_CRLI1_Msk (0x1ul << PWM_CAPINTSTS_CRLI1_Pos)
7651 #define PWM_CAPINTSTS_CFLI1_Pos (10)
7652 #define PWM_CAPINTSTS_CFLI1_Msk (0x1ul << PWM_CAPINTSTS_CFLI1_Pos)
7654 #define PWM_CAPINTSTS_CAPOVR1_Pos (11)
7655 #define PWM_CAPINTSTS_CAPOVR1_Msk (0x1ul << PWM_CAPINTSTS_CAPOVR1_Pos)
7657 #define PWM_CAPINTSTS_CAPOVF1_Pos (12)
7658 #define PWM_CAPINTSTS_CAPOVF1_Msk (0x1ul << PWM_CAPINTSTS_CAPOVF1_Pos)
7660 #define PWM_CAPINTSTS_CAPIF2_Pos (16)
7661 #define PWM_CAPINTSTS_CAPIF2_Msk (0x1ul << PWM_CAPINTSTS_CAPIF2_Pos)
7663 #define PWM_CAPINTSTS_CRLI2_Pos (17)
7664 #define PWM_CAPINTSTS_CRLI2_Msk (0x1ul << PWM_CAPINTSTS_CRLI2_Pos)
7666 #define PWM_CAPINTSTS_CFLI2_Pos (18)
7667 #define PWM_CAPINTSTS_CFLI2_Msk (0x1ul << PWM_CAPINTSTS_CFLI2_Pos)
7669 #define PWM_CAPINTSTS_CAPOVR2_Pos (19)
7670 #define PWM_CAPINTSTS_CAPOVR2_Msk (0x1ul << PWM_CAPINTSTS_CAPOVR2_Pos)
7672 #define PWM_CAPINTSTS_CAPOVF2_Pos (20)
7673 #define PWM_CAPINTSTS_CAPOVF2_Msk (0x1ul << PWM_CAPINTSTS_CAPOVF2_Pos)
7675 #define PWM_CAPINTSTS_CAPIF3_Pos (24)
7676 #define PWM_CAPINTSTS_CAPIF3_Msk (0x1ul << PWM_CAPINTSTS_CAPIF3_Pos)
7678 #define PWM_CAPINTSTS_CRLI3_Pos (25)
7679 #define PWM_CAPINTSTS_CRLI3_Msk (0x1ul << PWM_CAPINTSTS_CRLI3_Pos)
7681 #define PWM_CAPINTSTS_CFLI3_Pos (26)
7682 #define PWM_CAPINTSTS_CFLI3_Msk (0x1ul << PWM_CAPINTSTS_CFLI3_Pos)
7684 #define PWM_CAPINTSTS_CAPOVR3_Pos (27)
7685 #define PWM_CAPINTSTS_CAPOVR3_Msk (0x1ul << PWM_CAPINTSTS_CAPOVR3_Pos)
7687 #define PWM_CAPINTSTS_CAPOVF3_Pos (28)
7688 #define PWM_CAPINTSTS_CAPOVF3_Msk (0x1ul << PWM_CAPINTSTS_CAPOVF3_Pos)
7690 #define PWM_CRL0_CRL15_0_Pos (0)
7691 #define PWM_CRL0_CRL15_0_Msk (0xfffful << PWM_CRL0_CRL15_0_Pos)
7693 #define PWM_CRL0_CRL31_16_Pos (16)
7694 #define PWM_CRL0_CRL31_16_Msk (0xfffful << PWM_CRL0_CRL31_16_Pos)
7696 #define PWM_CFL0_CFL15_0_Pos (0)
7697 #define PWM_CFL0_CFL15_0_Msk (0xfffful << PWM_CFL0_CFL15_0_Pos)
7699 #define PWM_CFL0_CFL31_16_Pos (16)
7700 #define PWM_CFL0_CFL31_16_Msk (0xfffful << PWM_CFL0_CFL31_16_Pos)
7702 #define PWM_CRL1_CRL15_0_Pos (0)
7703 #define PWM_CRL1_CRL15_0_Msk (0xfffful << PWM_CRL1_CRL15_0_Pos)
7705 #define PWM_CRL1_CRL31_16_Pos (16)
7706 #define PWM_CRL1_CRL31_16_Msk (0xfffful << PWM_CRL1_CRL31_16_Pos)
7708 #define PWM_CFL1_CFL15_0_Pos (0)
7709 #define PWM_CFL1_CFL15_0_Msk (0xfffful << PWM_CFL1_CFL15_0_Pos)
7711 #define PWM_CFL1_CFL31_16_Pos (16)
7712 #define PWM_CFL1_CFL31_16_Msk (0xfffful << PWM_CFL1_CFL31_16_Pos)
7714 #define PWM_CRL2_CRL15_0_Pos (0)
7715 #define PWM_CRL2_CRL15_0_Msk (0xfffful << PWM_CRL2_CRL15_0_Pos)
7717 #define PWM_CRL2_CRL31_16_Pos (16)
7718 #define PWM_CRL2_CRL31_16_Msk (0xfffful << PWM_CRL2_CRL31_16_Pos)
7720 #define PWM_CFL2_CFL15_0_Pos (0)
7721 #define PWM_CFL2_CFL15_0_Msk (0xfffful << PWM_CFL2_CFL15_0_Pos)
7723 #define PWM_CFL2_CFL31_16_Pos (16)
7724 #define PWM_CFL2_CFL31_16_Msk (0xfffful << PWM_CFL2_CFL31_16_Pos)
7726 #define PWM_CRL3_CRL15_0_Pos (0)
7727 #define PWM_CRL3_CRL15_0_Msk (0xfffful << PWM_CRL3_CRL15_0_Pos)
7729 #define PWM_CRL3_CRL31_16_Pos (16)
7730 #define PWM_CRL3_CRL31_16_Msk (0xfffful << PWM_CRL3_CRL31_16_Pos)
7732 #define PWM_CFL3_CFL15_0_Pos (0)
7733 #define PWM_CFL3_CFL15_0_Msk (0xfffful << PWM_CFL3_CFL15_0_Pos)
7735 #define PWM_CFL3_CFL31_16_Pos (16)
7736 #define PWM_CFL3_CFL31_16_Msk (0xfffful << PWM_CFL3_CFL31_16_Pos)
7738 #define PWM_PDMACH0_Captureddata7_0_Pos (0)
7739 #define PWM_PDMACH0_Captureddata7_0_Msk (0xfful << PWM_PDMACH0_Captureddata7_0_Pos)
7741 #define PWM_PDMACH0_Captureddata15_8_Pos (8)
7742 #define PWM_PDMACH0_Captureddata15_8_Msk (0xfful << PWM_PDMACH0_Captureddata15_8_Pos)
7744 #define PWM_PDMACH0_Captureddata23_16_Pos (16)
7745 #define PWM_PDMACH0_Captureddata23_16_Msk (0xfful << PWM_PDMACH0_Captureddata23_16_Pos)
7747 #define PWM_PDMACH0_Captureddata31_24_Pos (24)
7748 #define PWM_PDMACH0_Captureddata31_24_Msk (0xfful << PWM_PDMACH0_Captureddata31_24_Pos)
7750 #define PWM_PDMACH2_Captureddata7_0_Pos (0)
7751 #define PWM_PDMACH2_Captureddata7_0_Msk (0xfful << PWM_PDMACH2_Captureddata7_0_Pos)
7753 #define PWM_PDMACH2_Captureddata15_8_Pos (8)
7754 #define PWM_PDMACH2_Captureddata15_8_Msk (0xfful << PWM_PDMACH2_Captureddata15_8_Pos)
7756 #define PWM_PDMACH2_Captureddata23_16_Pos (16)
7757 #define PWM_PDMACH2_Captureddata23_16_Msk (0xfful << PWM_PDMACH2_Captureddata23_16_Pos)
7759 #define PWM_PDMACH2_Captureddata31_24_Pos (24)
7760 #define PWM_PDMACH2_Captureddata31_24_Msk (0xfful << PWM_PDMACH2_Captureddata31_24_Pos) /* PWM_CONST */
7763 /* end of PWM register group */
7764
7765
7766 /*---------------------- Real Time Clock Controller -------------------------*/
7772 typedef struct
7773 {
7774
7775
7792 __IO uint32_t INIR;
7793
7808 __IO uint32_t AER;
7809
7838 __IO uint32_t FCR;
7839
7854 __IO uint32_t TLR;
7855
7870 __IO uint32_t CLR;
7871
7884 __IO uint32_t TSSR;
7885
7902 __IO uint32_t DWR;
7903
7918 __IO uint32_t TAR;
7919
7934 __IO uint32_t CAR;
7935
7947 __I uint32_t LIR;
7948
7966 __IO uint32_t RIER;
7967
7994 __IO uint32_t RIIR;
7995
8020 __IO uint32_t TTR;
8021 uint32_t RESERVE0[2];
8022
8023
8049 __IO uint32_t SPRCTL;
8050
8062 __IO uint32_t SPR[20];
8063
8064 } RTC_T;
8065
8071 #define RTC_INIR_ACTIVE_Pos (0)
8072 #define RTC_INIR_ACTIVE_Msk (0x1ul << RTC_INIR_ACTIVE_Pos)
8074 #define RTC_INIR_INIR_Pos (0)
8075 #define RTC_INIR_INIR_Msk (0xfffffffful << RTC_INIR_INIR_Pos)
8077 #define RTC_AER_AER_Pos (0)
8078 #define RTC_AER_AER_Msk (0xfffful << RTC_AER_AER_Pos)
8080 #define RTC_AER_ENF_Pos (16)
8081 #define RTC_AER_ENF_Msk (0x1ul << RTC_AER_ENF_Pos)
8083 #define RTC_FCR_FRACTION_Pos (0)
8084 #define RTC_FCR_FRACTION_Msk (0x3ful << RTC_FCR_FRACTION_Pos)
8086 #define RTC_FCR_INTEGER_Pos (8)
8087 #define RTC_FCR_INTEGER_Msk (0xful << RTC_FCR_INTEGER_Pos)
8089 #define RTC_TLR_1SEC_Pos (0)
8090 #define RTC_TLR_1SEC_Msk (0xful << RTC_TLR_1SEC_Pos)
8092 #define RTC_TLR_10SEC_Pos (4)
8093 #define RTC_TLR_10SEC_Msk (0x7ul << RTC_TLR_10SEC_Pos)
8095 #define RTC_TLR_1MIN_Pos (8)
8096 #define RTC_TLR_1MIN_Msk (0xful << RTC_TLR_1MIN_Pos)
8098 #define RTC_TLR_10MIN_Pos (12)
8099 #define RTC_TLR_10MIN_Msk (0x7ul << RTC_TLR_10MIN_Pos)
8101 #define RTC_TLR_1HR_Pos (16)
8102 #define RTC_TLR_1HR_Msk (0xful << RTC_TLR_1HR_Pos)
8104 #define RTC_TLR_10HR_Pos (20)
8105 #define RTC_TLR_10HR_Msk (0x3ul << RTC_TLR_10HR_Pos)
8107 #define RTC_CLR_1DAY_Pos (0)
8108 #define RTC_CLR_1DAY_Msk (0xful << RTC_CLR_1DAY_Pos)
8110 #define RTC_CLR_10DAY_Pos (4)
8111 #define RTC_CLR_10DAY_Msk (0x3ul << RTC_CLR_10DAY_Pos)
8113 #define RTC_CLR_1MON_Pos (8)
8114 #define RTC_CLR_1MON_Msk (0xful << RTC_CLR_1MON_Pos)
8116 #define RTC_CLR_10MON_Pos (12)
8117 #define RTC_CLR_10MON_Msk (0x1ul << RTC_CLR_10MON_Pos)
8119 #define RTC_CLR_1YEAR_Pos (16)
8120 #define RTC_CLR_1YEAR_Msk (0xful << RTC_CLR_1YEAR_Pos)
8122 #define RTC_CLR_10YEAR_Pos (20)
8123 #define RTC_CLR_10YEAR_Msk (0xful << RTC_CLR_10YEAR_Pos)
8125 #define RTC_TSSR_24H_12H_Pos (0)
8126 #define RTC_TSSR_24H_12H_Msk (0x1ul << RTC_TSSR_24H_12H_Pos)
8128 #define RTC_DWR_DWR_Pos (0)
8129 #define RTC_DWR_DWR_Msk (0x7ul << RTC_DWR_DWR_Pos)
8131 #define RTC_TAR_1SEC_Pos (0)
8132 #define RTC_TAR_1SEC_Msk (0xful << RTC_TAR_1SEC_Pos)
8134 #define RTC_TAR_10SEC_Pos (4)
8135 #define RTC_TAR_10SEC_Msk (0x7ul << RTC_TAR_10SEC_Pos)
8137 #define RTC_TAR_1MIN_Pos (8)
8138 #define RTC_TAR_1MIN_Msk (0xful << RTC_TAR_1MIN_Pos)
8140 #define RTC_TAR_10MIN_Pos (12)
8141 #define RTC_TAR_10MIN_Msk (0x7ul << RTC_TAR_10MIN_Pos)
8143 #define RTC_TAR_1HR_Pos (16)
8144 #define RTC_TAR_1HR_Msk (0xful << RTC_TAR_1HR_Pos)
8146 #define RTC_TAR_10HR_Pos (20)
8147 #define RTC_TAR_10HR_Msk (0x3ul << RTC_TAR_10HR_Pos)
8149 #define RTC_CAR_1DAY_Pos (0)
8150 #define RTC_CAR_1DAY_Msk (0xful << RTC_CAR_1DAY_Pos)
8152 #define RTC_CAR_10DAY_Pos (4)
8153 #define RTC_CAR_10DAY_Msk (0x3ul << RTC_CAR_10DAY_Pos)
8155 #define RTC_CAR_1MON_Pos (8)
8156 #define RTC_CAR_1MON_Msk (0xful << RTC_CAR_1MON_Pos)
8158 #define RTC_CAR_10MON_Pos (12)
8159 #define RTC_CAR_10MON_Msk (0x1ul << RTC_CAR_10MON_Pos)
8161 #define RTC_CAR_1YEAR_Pos (16)
8162 #define RTC_CAR_1YEAR_Msk (0xful << RTC_CAR_1YEAR_Pos)
8164 #define RTC_CAR_10YEAR_Pos (20)
8165 #define RTC_CAR_10YEAR_Msk (0xful << RTC_CAR_10YEAR_Pos)
8167 #define RTC_LIR_LIR_Pos (0)
8168 #define RTC_LIR_LIR_Msk (0x1ul << RTC_LIR_LIR_Pos)
8170 #define RTC_RIER_AIER_Pos (0)
8171 #define RTC_RIER_AIER_Msk (0x1ul << RTC_RIER_AIER_Pos)
8173 #define RTC_RIER_TIER_Pos (1)
8174 #define RTC_RIER_TIER_Msk (0x1ul << RTC_RIER_TIER_Pos)
8176 #define RTC_RIER_SNOOPIER_Pos (2)
8177 #define RTC_RIER_SNOOPIER_Msk (0x1ul << RTC_RIER_SNOOPIER_Pos)
8179 #define RTC_RIIR_AIF_Pos (0)
8180 #define RTC_RIIR_AIF_Msk (0x1ul << RTC_RIIR_AIF_Pos)
8182 #define RTC_RIIR_TIF_Pos (1)
8183 #define RTC_RIIR_TIF_Msk (0x1ul << RTC_RIIR_TIF_Pos)
8185 #define RTC_RIIR_SNOOPIF_Pos (2)
8186 #define RTC_RIIR_SNOOPIF_Msk (0x1ul << RTC_RIIR_SNOOPIF_Pos)
8188 #define RTC_TTR_TTR_Pos (0)
8189 #define RTC_TTR_TTR_Msk (0x7ul << RTC_TTR_TTR_Pos)
8191 #define RTC_TTR_TWKE_Pos (3)
8192 #define RTC_TTR_TWKE_Msk (0x1ul << RTC_TTR_TWKE_Pos)
8194 #define RTC_SPRCTL_SNOOPEN_Pos (0)
8195 #define RTC_SPRCTL_SNOOPEN_Msk (0x1ul << RTC_SPRCTL_SNOOPEN_Pos)
8197 #define RTC_SPRCTL_SNOOPEDGE_Pos (1)
8198 #define RTC_SPRCTL_SNOOPEDGE_Msk (0x1ul << RTC_SPRCTL_SNOOPEDGE_Pos)
8200 #define RTC_SPRCTL_SPRRDY_Pos (7)
8201 #define RTC_SPRCTL_SPRRDY_Msk (0x1ul << RTC_SPRCTL_SPRRDY_Pos)
8203 #define RTC_SPR0_SPARE_Pos (0)
8204 #define RTC_SPR0_SPARE_Msk (0xfffffffful << RTC_SPR0_SPARE_Pos)
8206 #define RTC_SPR1_SPARE_Pos (0)
8207 #define RTC_SPR1_SPARE_Msk (0xfffffffful << RTC_SPR1_SPARE_Pos)
8209 #define RTC_SPR2_SPARE_Pos (0)
8210 #define RTC_SPR2_SPARE_Msk (0xfffffffful << RTC_SPR2_SPARE_Pos)
8212 #define RTC_SPR3_SPARE_Pos (0)
8213 #define RTC_SPR3_SPARE_Msk (0xfffffffful << RTC_SPR3_SPARE_Pos)
8215 #define RTC_SPR4_SPARE_Pos (0)
8216 #define RTC_SPR4_SPARE_Msk (0xfffffffful << RTC_SPR4_SPARE_Pos)
8218 #define RTC_SPR5_SPARE_Pos (0)
8219 #define RTC_SPR5_SPARE_Msk (0xfffffffful << RTC_SPR5_SPARE_Pos)
8221 #define RTC_SPR6_SPARE_Pos (0)
8222 #define RTC_SPR6_SPARE_Msk (0xfffffffful << RTC_SPR6_SPARE_Pos)
8224 #define RTC_SPR7_SPARE_Pos (0)
8225 #define RTC_SPR7_SPARE_Msk (0xfffffffful << RTC_SPR7_SPARE_Pos)
8227 #define RTC_SPR8_SPARE_Pos (0)
8228 #define RTC_SPR8_SPARE_Msk (0xfffffffful << RTC_SPR8_SPARE_Pos)
8230 #define RTC_SPR9_SPARE_Pos (0)
8231 #define RTC_SPR9_SPARE_Msk (0xfffffffful << RTC_SPR9_SPARE_Pos)
8233 #define RTC_SPR10_SPARE_Pos (0)
8234 #define RTC_SPR10_SPARE_Msk (0xfffffffful << RTC_SPR10_SPARE_Pos)
8236 #define RTC_SPR11_SPARE_Pos (0)
8237 #define RTC_SPR11_SPARE_Msk (0xfffffffful << RTC_SPR11_SPARE_Pos)
8239 #define RTC_SPR12_SPARE_Pos (0)
8240 #define RTC_SPR12_SPARE_Msk (0xfffffffful << RTC_SPR12_SPARE_Pos)
8242 #define RTC_SPR13_SPARE_Pos (0)
8243 #define RTC_SPR13_SPARE_Msk (0xfffffffful << RTC_SPR13_SPARE_Pos)
8245 #define RTC_SPR14_SPARE_Pos (0)
8246 #define RTC_SPR14_SPARE_Msk (0xfffffffful << RTC_SPR14_SPARE_Pos)
8248 #define RTC_SPR15_SPARE_Pos (0)
8249 #define RTC_SPR15_SPARE_Msk (0xfffffffful << RTC_SPR15_SPARE_Pos)
8251 #define RTC_SPR16_SPARE_Pos (0)
8252 #define RTC_SPR16_SPARE_Msk (0xfffffffful << RTC_SPR16_SPARE_Pos)
8254 #define RTC_SPR17_SPARE_Pos (0)
8255 #define RTC_SPR17_SPARE_Msk (0xfffffffful << RTC_SPR17_SPARE_Pos)
8257 #define RTC_SPR18_SPARE_Pos (0)
8258 #define RTC_SPR18_SPARE_Msk (0xfffffffful << RTC_SPR18_SPARE_Pos)
8260 #define RTC_SPR19_SPARE_Pos (0)
8261 #define RTC_SPR19_SPARE_Msk (0xfffffffful << RTC_SPR19_SPARE_Pos) /* RTC_CONST */
8264 /* end of RTC register group */
8265
8266
8267 /*---------------------- Smart Card Host Interface Controller -------------------------*/
8273 typedef struct
8274 {
8275
8276
8277 union
8278 {
8289 __I uint32_t RBR;
8300 __O uint32_t THR;
8301 };
8302
8388 __IO uint32_t CTL;
8389
8478 __IO uint32_t ALTCTL;
8479
8491 __IO uint32_t EGTR;
8492
8506 __IO uint32_t RFTMR;
8507
8526 __IO uint32_t ETUCR;
8527
8582 __IO uint32_t IER;
8583
8634 __IO uint32_t ISR;
8635
8709 __IO uint32_t TRSR;
8710
8785 __IO uint32_t PINCSR;
8786
8799 __IO uint32_t TMR0;
8800
8813 __IO uint32_t TMR1;
8814
8827 __IO uint32_t TMR2;
8828
8857 __IO uint32_t UACTL;
8858
8869 __I uint32_t TDRA;
8870
8883 __I uint32_t TDRB;
8884
8885 } SC_T;
8886
8892 #define SC_DAT_DAT_Pos (0)
8893 #define SC_DAT_DAT_Msk (0xfful << SC_DAT_DAT_Pos)
8895 #define SC_CTL_SC_CEN_Pos (0)
8896 #define SC_CTL_SC_CEN_Msk (0x1ul << SC_CTL_SC_CEN_Pos)
8898 #define SC_CTL_DIS_RX_Pos (1)
8899 #define SC_CTL_DIS_RX_Msk (0x1ul << SC_CTL_DIS_RX_Pos)
8901 #define SC_CTL_DIS_TX_Pos (2)
8902 #define SC_CTL_DIS_TX_Msk (0x1ul << SC_CTL_DIS_TX_Pos)
8904 #define SC_CTL_AUTO_CON_EN_Pos (3)
8905 #define SC_CTL_AUTO_CON_EN_Msk (0x1ul << SC_CTL_AUTO_CON_EN_Pos)
8907 #define SC_CTL_CON_SEL_Pos (4)
8908 #define SC_CTL_CON_SEL_Msk (0x3ul << SC_CTL_CON_SEL_Pos)
8910 #define SC_CTL_RX_FTRI_LEV_Pos (6)
8911 #define SC_CTL_RX_FTRI_LEV_Msk (0x3ul << SC_CTL_RX_FTRI_LEV_Pos)
8913 #define SC_CTL_BGT_Pos (8)
8914 #define SC_CTL_BGT_Msk (0x1ful << SC_CTL_BGT_Pos)
8916 #define SC_CTL_TMR_SEL_Pos (13)
8917 #define SC_CTL_TMR_SEL_Msk (0x3ul << SC_CTL_TMR_SEL_Pos)
8919 #define SC_CTL_SLEN_Pos (15)
8920 #define SC_CTL_SLEN_Msk (0x1ul << SC_CTL_SLEN_Pos)
8922 #define SC_CTL_RX_ERETRY_Pos (16)
8923 #define SC_CTL_RX_ERETRY_Msk (0x7ul << SC_CTL_RX_ERETRY_Pos)
8925 #define SC_CTL_RX_ERETRY_EN_Pos (19)
8926 #define SC_CTL_RX_ERETRY_EN_Msk (0x1ul << SC_CTL_RX_ERETRY_EN_Pos)
8928 #define SC_CTL_TX_ERETRY_Pos (20)
8929 #define SC_CTL_TX_ERETRY_Msk (0x7ul << SC_CTL_TX_ERETRY_Pos)
8931 #define SC_CTL_TX_ERETRY_EN_Pos (23)
8932 #define SC_CTL_TX_ERETRY_EN_Msk (0x1ul << SC_CTL_TX_ERETRY_EN_Pos)
8934 #define SC_CTL_CD_DEB_SEL_Pos (24)
8935 #define SC_CTL_CD_DEB_SEL_Msk (0x3ul << SC_CTL_CD_DEB_SEL_Pos)
8937 #define SC_ALTCTL_TX_RST_Pos (0)
8938 #define SC_ALTCTL_TX_RST_Msk (0x1ul << SC_ALTCTL_TX_RST_Pos)
8940 #define SC_ALTCTL_RX_RST_Pos (1)
8941 #define SC_ALTCTL_RX_RST_Msk (0x1ul << SC_ALTCTL_RX_RST_Pos)
8943 #define SC_ALTCTL_DACT_EN_Pos (2)
8944 #define SC_ALTCTL_DACT_EN_Msk (0x1ul << SC_ALTCTL_DACT_EN_Pos)
8946 #define SC_ALTCTL_ACT_EN_Pos (3)
8947 #define SC_ALTCTL_ACT_EN_Msk (0x1ul << SC_ALTCTL_ACT_EN_Pos)
8949 #define SC_ALTCTL_WARST_EN_Pos (4)
8950 #define SC_ALTCTL_WARST_EN_Msk (0x1ul << SC_ALTCTL_WARST_EN_Pos)
8952 #define SC_ALTCTL_TMR0_SEN_Pos (5)
8953 #define SC_ALTCTL_TMR0_SEN_Msk (0x1ul << SC_ALTCTL_TMR0_SEN_Pos)
8955 #define SC_ALTCTL_TMR1_SEN_Pos (6)
8956 #define SC_ALTCTL_TMR1_SEN_Msk (0x1ul << SC_ALTCTL_TMR1_SEN_Pos)
8958 #define SC_ALTCTL_TMR2_SEN_Pos (7)
8959 #define SC_ALTCTL_TMR2_SEN_Msk (0x1ul << SC_ALTCTL_TMR2_SEN_Pos)
8961 #define SC_ALTCTL_INIT_SEL_Pos (8)
8962 #define SC_ALTCTL_INIT_SEL_Msk (0x3ul << SC_ALTCTL_INIT_SEL_Pos)
8964 #define SC_ALTCTL_RX_BGT_EN_Pos (12)
8965 #define SC_ALTCTL_RX_BGT_EN_Msk (0x1ul << SC_ALTCTL_RX_BGT_EN_Pos)
8967 #define SC_ALTCTL_TMR0_ATV_Pos (13)
8968 #define SC_ALTCTL_TMR0_ATV_Msk (0x1ul << SC_ALTCTL_TMR0_ATV_Pos)
8970 #define SC_ALTCTL_TMR1_ATV_Pos (14)
8971 #define SC_ALTCTL_TMR1_ATV_Msk (0x1ul << SC_ALTCTL_TMR1_ATV_Pos)
8973 #define SC_ALTCTL_TMR2_ATV_Pos (15)
8974 #define SC_ALTCTL_TMR2_ATV_Msk (0x1ul << SC_ALTCTL_TMR2_ATV_Pos)
8976 #define SC_EGTR_EGT_Pos (0)
8977 #define SC_EGTR_EGT_Msk (0xfful << SC_EGTR_EGT_Pos)
8979 #define SC_RFTMR_RFTM_Pos (0)
8980 #define SC_RFTMR_RFTM_Msk (0x1fful << SC_RFTMR_RFTM_Pos)
8982 #define SC_ETUCR_ETU_RDIV_Pos (0)
8983 #define SC_ETUCR_ETU_RDIV_Msk (0xffful << SC_ETUCR_ETU_RDIV_Pos)
8985 #define SC_ETUCR_COMPEN_EN_Pos (15)
8986 #define SC_ETUCR_COMPEN_EN_Msk (0x1ul << SC_ETUCR_COMPEN_EN_Pos)
8988 #define SC_IER_RDA_IE_Pos (0)
8989 #define SC_IER_RDA_IE_Msk (0x1ul << SC_IER_RDA_IE_Pos)
8991 #define SC_IER_TBE_IE_Pos (1)
8992 #define SC_IER_TBE_IE_Msk (0x1ul << SC_IER_TBE_IE_Pos)
8994 #define SC_IER_TERR_IE_Pos (2)
8995 #define SC_IER_TERR_IE_Msk (0x1ul << SC_IER_TERR_IE_Pos)
8997 #define SC_IER_TMR0_IE_Pos (3)
8998 #define SC_IER_TMR0_IE_Msk (0x1ul << SC_IER_TMR0_IE_Pos)
9000 #define SC_IER_TMR1_IE_Pos (4)
9001 #define SC_IER_TMR1_IE_Msk (0x1ul << SC_IER_TMR1_IE_Pos)
9003 #define SC_IER_TMR2_IE_Pos (5)
9004 #define SC_IER_TMR2_IE_Msk (0x1ul << SC_IER_TMR2_IE_Pos)
9006 #define SC_IER_BGT_IE_Pos (6)
9007 #define SC_IER_BGT_IE_Msk (0x1ul << SC_IER_BGT_IE_Pos)
9009 #define SC_IER_CD_IE_Pos (7)
9010 #define SC_IER_CD_IE_Msk (0x1ul << SC_IER_CD_IE_Pos)
9012 #define SC_IER_INIT_IE_Pos (8)
9013 #define SC_IER_INIT_IE_Msk (0x1ul << SC_IER_INIT_IE_Pos)
9015 #define SC_IER_RTMR_IE_Pos (9)
9016 #define SC_IER_RTMR_IE_Msk (0x1ul << SC_IER_RTMR_IE_Pos)
9018 #define SC_IER_ACON_ERR_IE_Pos (10)
9019 #define SC_IER_ACON_ERR_IE_Msk (0x1ul << SC_IER_ACON_ERR_IE_Pos)
9021 #define SC_ISR_RDA_IS_Pos (0)
9022 #define SC_ISR_RDA_IS_Msk (0x1ul << SC_ISR_RDA_IS_Pos)
9024 #define SC_ISR_TBE_IS_Pos (1)
9025 #define SC_ISR_TBE_IS_Msk (0x1ul << SC_ISR_TBE_IS_Pos)
9027 #define SC_ISR_TERR_IS_Pos (2)
9028 #define SC_ISR_TERR_IS_Msk (0x1ul << SC_ISR_TERR_IS_Pos)
9030 #define SC_ISR_TMR0_IS_Pos (3)
9031 #define SC_ISR_TMR0_IS_Msk (0x1ul << SC_ISR_TMR0_IS_Pos)
9033 #define SC_ISR_TMR1_IS_Pos (4)
9034 #define SC_ISR_TMR1_IS_Msk (0x1ul << SC_ISR_TMR1_IS_Pos)
9036 #define SC_ISR_TMR2_IS_Pos (5)
9037 #define SC_ISR_TMR2_IS_Msk (0x1ul << SC_ISR_TMR2_IS_Pos)
9039 #define SC_ISR_BGT_IS_Pos (6)
9040 #define SC_ISR_BGT_IS_Msk (0x1ul << SC_ISR_BGT_IS_Pos)
9042 #define SC_ISR_CD_IS_Pos (7)
9043 #define SC_ISR_CD_IS_Msk (0x1ul << SC_ISR_CD_IS_Pos)
9045 #define SC_ISR_INIT_IS_Pos (8)
9046 #define SC_ISR_INIT_IS_Msk (0x1ul << SC_ISR_INIT_IS_Pos)
9048 #define SC_ISR_RTMR_IS_Pos (9)
9049 #define SC_ISR_RTMR_IS_Msk (0x1ul << SC_ISR_RTMR_IS_Pos)
9051 #define SC_ISR_ACON_ERR_IS_Pos (10)
9052 #define SC_ISR_ACON_ERR_IS_Msk (0x1ul << SC_ISR_ACON_ERR_IS_Pos)
9054 #define SC_TRSR_RX_OVER_F_Pos (0)
9055 #define SC_TRSR_RX_OVER_F_Msk (0x1ul << SC_TRSR_RX_OVER_F_Pos)
9057 #define SC_TRSR_RX_EMPTY_F_Pos (1)
9058 #define SC_TRSR_RX_EMPTY_F_Msk (0x1ul << SC_TRSR_RX_EMPTY_F_Pos)
9060 #define SC_TRSR_RX_FULL_F_Pos (2)
9061 #define SC_TRSR_RX_FULL_F_Msk (0x1ul << SC_TRSR_RX_FULL_F_Pos)
9063 #define SC_TRSR_RX_EPA_F_Pos (4)
9064 #define SC_TRSR_RX_EPA_F_Msk (0x1ul << SC_TRSR_RX_EPA_F_Pos)
9066 #define SC_TRSR_RX_EFR_F_Pos (5)
9067 #define SC_TRSR_RX_EFR_F_Msk (0x1ul << SC_TRSR_RX_EFR_F_Pos)
9069 #define SC_TRSR_RX_EBR_F_Pos (6)
9070 #define SC_TRSR_RX_EBR_F_Msk (0x1ul << SC_TRSR_RX_EBR_F_Pos)
9072 #define SC_TRSR_TX_OVER_F_Pos (8)
9073 #define SC_TRSR_TX_OVER_F_Msk (0x1ul << SC_TRSR_TX_OVER_F_Pos)
9075 #define SC_TRSR_TX_EMPTY_F_Pos (9)
9076 #define SC_TRSR_TX_EMPTY_F_Msk (0x1ul << SC_TRSR_TX_EMPTY_F_Pos)
9078 #define SC_TRSR_TX_FULL_F_Pos (10)
9079 #define SC_TRSR_TX_FULL_F_Msk (0x1ul << SC_TRSR_TX_FULL_F_Pos)
9081 #define SC_TRSR_RX_POINT_F_Pos (16)
9082 #define SC_TRSR_RX_POINT_F_Msk (0x7ul << SC_TRSR_RX_POINT_F_Pos)
9084 #define SC_TRSR_RX_REERR_Pos (21)
9085 #define SC_TRSR_RX_REERR_Msk (0x1ul << SC_TRSR_RX_REERR_Pos)
9087 #define SC_TRSR_RX_OVER_ERETRY_Pos (22)
9088 #define SC_TRSR_RX_OVER_ERETRY_Msk (0x1ul << SC_TRSR_RX_OVER_ERETRY_Pos)
9090 #define SC_TRSR_RX_ATV_Pos (23)
9091 #define SC_TRSR_RX_ATV_Msk (0x1ul << SC_TRSR_RX_ATV_Pos)
9093 #define SC_TRSR_TX_POINT_F_Pos (24)
9094 #define SC_TRSR_TX_POINT_F_Msk (0x7ul << SC_TRSR_TX_POINT_F_Pos)
9096 #define SC_TRSR_TX_REERR_Pos (29)
9097 #define SC_TRSR_TX_REERR_Msk (0x1ul << SC_TRSR_TX_REERR_Pos)
9099 #define SC_TRSR_TX_OVER_ERETRY_Pos (30)
9100 #define SC_TRSR_TX_OVER_ERETRY_Msk (0x1ul << SC_TRSR_TX_OVER_ERETRY_Pos)
9102 #define SC_TRSR_TX_ATV_Pos (31)
9103 #define SC_TRSR_TX_ATV_Msk (0x1ul << SC_TRSR_TX_ATV_Pos)
9105 #define SC_PINCSR_POW_EN_Pos (0)
9106 #define SC_PINCSR_POW_EN_Msk (0x1ul << SC_PINCSR_POW_EN_Pos)
9108 #define SC_PINCSR_SC_RST_Pos (1)
9109 #define SC_PINCSR_SC_RST_Msk (0x1ul << SC_PINCSR_SC_RST_Pos)
9111 #define SC_PINCSR_CD_REM_F_Pos (2)
9112 #define SC_PINCSR_CD_REM_F_Msk (0x1ul << SC_PINCSR_CD_REM_F_Pos)
9114 #define SC_PINCSR_CD_INS_F_Pos (3)
9115 #define SC_PINCSR_CD_INS_F_Msk (0x1ul << SC_PINCSR_CD_INS_F_Pos)
9117 #define SC_PINCSR_CD_PIN_ST_Pos (4)
9118 #define SC_PINCSR_CD_PIN_ST_Msk (0x1ul << SC_PINCSR_CD_PIN_ST_Pos)
9120 #define SC_PINCSR_CLK_KEEP_Pos (6)
9121 #define SC_PINCSR_CLK_KEEP_Msk (0x1ul << SC_PINCSR_CLK_KEEP_Pos)
9123 #define SC_PINCSR_ADAC_CD_EN_Pos (7)
9124 #define SC_PINCSR_ADAC_CD_EN_Msk (0x1ul << SC_PINCSR_ADAC_CD_EN_Pos)
9126 #define SC_PINCSR_SC_OEN_ST_Pos (8)
9127 #define SC_PINCSR_SC_OEN_ST_Msk (0x1ul << SC_PINCSR_SC_OEN_ST_Pos)
9129 #define SC_PINCSR_SC_DATA_O_Pos (9)
9130 #define SC_PINCSR_SC_DATA_O_Msk (0x1ul << SC_PINCSR_SC_DATA_O_Pos)
9132 #define SC_PINCSR_CD_LEV_Pos (10)
9133 #define SC_PINCSR_CD_LEV_Msk (0x1ul << SC_PINCSR_CD_LEV_Pos)
9135 #define SC_PINCSR_POW_INV_Pos (11)
9136 #define SC_PINCSR_POW_INV_Msk (0x1ul << SC_PINCSR_POW_INV_Pos)
9138 #define SC_PINCSR_SC_DATA_I_ST_Pos (16)
9139 #define SC_PINCSR_SC_DATA_I_ST_Msk (0x1ul << SC_PINCSR_SC_DATA_I_ST_Pos)
9141 #define SC_TMR0_CNT_Pos (0)
9142 #define SC_TMR0_CNT_Msk (0xfffffful << SC_TMR0_CNT_Pos)
9144 #define SC_TMR0_MODE_Pos (24)
9145 #define SC_TMR0_MODE_Msk (0xful << SC_TMR0_MODE_Pos)
9147 #define SC_TMR1_CNT_Pos (0)
9148 #define SC_TMR1_CNT_Msk (0xfful << SC_TMR1_CNT_Pos)
9150 #define SC_TMR1_MODE_Pos (24)
9151 #define SC_TMR1_MODE_Msk (0xful << SC_TMR1_MODE_Pos)
9153 #define SC_TMR2_CNT_Pos (0)
9154 #define SC_TMR2_CNT_Msk (0xfful << SC_TMR2_CNT_Pos)
9156 #define SC_TMR2_MODE_Pos (24)
9157 #define SC_TMR2_MODE_Msk (0xful << SC_TMR2_MODE_Pos)
9159 #define SC_UACTL_UA_MODE_EN_Pos (0)
9160 #define SC_UACTL_UA_MODE_EN_Msk (0x1ul << SC_UACTL_UA_MODE_EN_Pos)
9162 #define SC_UACTL_DATA_LEN_Pos (4)
9163 #define SC_UACTL_DATA_LEN_Msk (0x3ul << SC_UACTL_DATA_LEN_Pos)
9165 #define SC_UACTL_PBDIS_Pos (6)
9166 #define SC_UACTL_PBDIS_Msk (0x1ul << SC_UACTL_PBDIS_Pos)
9168 #define SC_UACTL_OPE_Pos (7)
9169 #define SC_UACTL_OPE_Msk (0x1ul << SC_UACTL_OPE_Pos)
9171 #define SC_TDRA_TDR0_Pos (0)
9172 #define SC_TDRA_TDR0_Msk (0xfffffful << SC_TDRA_TDR0_Pos)
9174 #define SC_TDRB_TDR1_Pos (0)
9175 #define SC_TDRB_TDR1_Msk (0xfful << SC_TDRB_TDR1_Pos)
9177 #define SC_TDRB_TDR2_Pos (8)
9178 #define SC_TDRB_TDR2_Msk (0xfful << SC_TDRB_TDR2_Pos) /* SC_CONST */
9181 /* end of SC register group */
9182
9183
9184 /*---------------------- Serial Peripheral Interface Controller -------------------------*/
9190 typedef struct
9191 {
9192
9193
9291 __IO uint32_t CTL;
9292
9346 __IO uint32_t STATUS;
9347
9364 __IO uint32_t CLKDIV;
9365
9417 __IO uint32_t SSR;
9418
9431 __I uint32_t RX0;
9432
9445 __I uint32_t RX1;
9446 uint32_t RESERVE0[2];
9447
9448
9463 __O uint32_t TX0;
9464
9479 __O uint32_t TX1;
9480 uint32_t RESERVE1[3];
9481
9482
9496 __IO uint32_t VARCLK;
9497
9526 __IO uint32_t DMA;
9527
9562 __IO uint32_t FFCTL;
9563 } SPI_T;
9564
9570 #define SPI_CTL_GO_BUSY_Pos (0)
9571 #define SPI_CTL_GO_BUSY_Msk (0x1ul << SPI_CTL_GO_BUSY_Pos)
9573 #define SPI_CTL_RX_NEG_Pos (1)
9574 #define SPI_CTL_RX_NEG_Msk (0x1ul << SPI_CTL_RX_NEG_Pos)
9576 #define SPI_CTL_TX_NEG_Pos (2)
9577 #define SPI_CTL_TX_NEG_Msk (0x1ul << SPI_CTL_TX_NEG_Pos)
9579 #define SPI_CTL_TX_BIT_LEN_Pos (3)
9580 #define SPI_CTL_TX_BIT_LEN_Msk (0x1ful << SPI_CTL_TX_BIT_LEN_Pos)
9582 #define SPI_CTL_LSB_Pos (10)
9583 #define SPI_CTL_LSB_Msk (0x1ul << SPI_CTL_LSB_Pos)
9585 #define SPI_CTL_CLKP_Pos (11)
9586 #define SPI_CTL_CLKP_Msk (0x1ul << SPI_CTL_CLKP_Pos)
9588 #define SPI_CTL_SP_CYCLE_Pos (12)
9589 #define SPI_CTL_SP_CYCLE_Msk (0xful << SPI_CTL_SP_CYCLE_Pos)
9591 #define SPI_CTL_INTEN_Pos (17)
9592 #define SPI_CTL_INTEN_Msk (0x1ul << SPI_CTL_INTEN_Pos)
9594 #define SPI_CTL_SLAVE_Pos (18)
9595 #define SPI_CTL_SLAVE_Msk (0x1ul << SPI_CTL_SLAVE_Pos)
9597 #define SPI_CTL_REORDER_Pos (19)
9598 #define SPI_CTL_REORDER_Msk (0x1ul << SPI_CTL_REORDER_Pos)
9600 #define SPI_CTL_FIFOM_Pos (21)
9601 #define SPI_CTL_FIFOM_Msk (0x1ul << SPI_CTL_FIFOM_Pos)
9603 #define SPI_CTL_TWOB_Pos (22)
9604 #define SPI_CTL_TWOB_Msk (0x1ul << SPI_CTL_TWOB_Pos)
9606 #define SPI_CTL_VARCLK_EN_Pos (23)
9607 #define SPI_CTL_VARCLK_EN_Msk (0x1ul << SPI_CTL_VARCLK_EN_Pos)
9609 #define SPI_CTL_DUAL_IO_DIR_Pos (28)
9610 #define SPI_CTL_DUAL_IO_DIR_Msk (0x1ul << SPI_CTL_DUAL_IO_DIR_Pos)
9612 #define SPI_CTL_DUAL_IO_EN_Pos (29)
9613 #define SPI_CTL_DUAL_IO_EN_Msk (0x1ul << SPI_CTL_DUAL_IO_EN_Pos)
9615 #define SPI_CTL_WKEUP_EN_Pos (31)
9616 #define SPI_CTL_WKEUP_EN_Msk (0x1ul << SPI_CTL_WKEUP_EN_Pos)
9618 #define SPI_STATUS_RX_EMPTY_Pos (0)
9619 #define SPI_STATUS_RX_EMPTY_Msk (0x1ul << SPI_STATUS_RX_EMPTY_Pos)
9621 #define SPI_STATUS_RX_FULL_Pos (1)
9622 #define SPI_STATUS_RX_FULL_Msk (0x1ul << SPI_STATUS_RX_FULL_Pos)
9624 #define SPI_STATUS_TX_EMPTY_Pos (2)
9625 #define SPI_STATUS_TX_EMPTY_Msk (0x1ul << SPI_STATUS_TX_EMPTY_Pos)
9627 #define SPI_STATUS_TX_FULL_Pos (3)
9628 #define SPI_STATUS_TX_FULL_Msk (0x1ul << SPI_STATUS_TX_FULL_Pos)
9630 #define SPI_STATUS_LTRIG_FLAG_Pos (4)
9631 #define SPI_STATUS_LTRIG_FLAG_Msk (0x1ul << SPI_STATUS_LTRIG_FLAG_Pos)
9633 #define SPI_STATUS_SLV_START_INTSTS_Pos (6)
9634 #define SPI_STATUS_SLV_START_INTSTS_Msk (0x1ul << SPI_STATUS_SLV_START_INTSTS_Pos)
9636 #define SPI_STATUS_INTSTS_Pos (7)
9637 #define SPI_STATUS_INTSTS_Msk (0x1ul << SPI_STATUS_INTSTS_Pos)
9639 #define SPI_STATUS_RXINT_STS_Pos (8)
9640 #define SPI_STATUS_RXINT_STS_Msk (0x1ul << SPI_STATUS_RXINT_STS_Pos)
9642 #define SPI_STATUS_RX_OVER_RUN_Pos (9)
9643 #define SPI_STATUS_RX_OVER_RUN_Msk (0x1ul << SPI_STATUS_RX_OVER_RUN_Pos)
9645 #define SPI_STATUS_TXINT_STS_Pos (10)
9646 #define SPI_STATUS_TXINT_STS_Msk (0x1ul << SPI_STATUS_TXINT_STS_Pos)
9648 #define SPI_STATUS_TIME_OUT_STS_Pos (12)
9649 #define SPI_STATUS_TIME_OUT_STS_Msk (0x1ul << SPI_STATUS_TIME_OUT_STS_Pos)
9651 #define SPI_STATUS_RX_FIFO_CNT_Pos (16)
9652 #define SPI_STATUS_RX_FIFO_CNT_Msk (0xful << SPI_STATUS_RX_FIFO_CNT_Pos)
9654 #define SPI_STATUS_TX_FIFO_CNT_Pos (20)
9655 #define SPI_STATUS_TX_FIFO_CNT_Msk (0xful << SPI_STATUS_TX_FIFO_CNT_Pos)
9657 #define SPI_CLKDIV_DIVIDER1_Pos (0)
9658 #define SPI_CLKDIV_DIVIDER1_Msk (0xfful << SPI_CLKDIV_DIVIDER1_Pos)
9660 #define SPI_CLKDIV_DIVIDER2_Pos (16)
9661 #define SPI_CLKDIV_DIVIDER2_Msk (0xfful << SPI_CLKDIV_DIVIDER2_Pos)
9663 #define SPI_SSR_SSR_Pos (0)
9664 #define SPI_SSR_SSR_Msk (0x3ul << SPI_SSR_SSR_Pos)
9666 #define SPI_SSR_SS_LVL_Pos (2)
9667 #define SPI_SSR_SS_LVL_Msk (0x1ul << SPI_SSR_SS_LVL_Pos)
9669 #define SPI_SSR_AUTOSS_Pos (3)
9670 #define SPI_SSR_AUTOSS_Msk (0x1ul << SPI_SSR_AUTOSS_Pos)
9672 #define SPI_SSR_SS_LTRIG_Pos (4)
9673 #define SPI_SSR_SS_LTRIG_Msk (0x1ul << SPI_SSR_SS_LTRIG_Pos)
9675 #define SPI_SSR_NOSLVSEL_Pos (5)
9676 #define SPI_SSR_NOSLVSEL_Msk (0x1ul << SPI_SSR_NOSLVSEL_Pos)
9678 #define SPI_SSR_SLV_ABORT_Pos (8)
9679 #define SPI_SSR_SLV_ABORT_Msk (0x1ul << SPI_SSR_SLV_ABORT_Pos)
9681 #define SPI_SSR_SSTA_INTEN_Pos (9)
9682 #define SPI_SSR_SSTA_INTEN_Msk (0x1ul << SPI_SSR_SSTA_INTEN_Pos)
9684 #define SPI_SSR_SS_INT_OPT_Pos (16)
9685 #define SPI_SSR_SS_INT_OPT_Msk (0x1ul << SPI_SSR_SS_INT_OPT_Pos)
9687 #define SPI_RX0_RDATA_Pos (0)
9688 #define SPI_RX0_RDATA_Msk (0xfffffffful << SPI_RX0_RDATA_Pos)
9690 #define SPI_RX1_RDATA_Pos (0)
9691 #define SPI_RX1_RDATA_Msk (0xfffffffful << SPI_RX1_RDATA_Pos)
9693 #define SPI_TX0_TDATA_Pos (0)
9694 #define SPI_TX0_TDATA_Msk (0xfffffffful << SPI_TX0_TDATA_Pos)
9696 #define SPI_TX1_TDATA_Pos (0)
9697 #define SPI_TX1_TDATA_Msk (0xfffffffful << SPI_TX1_TDATA_Pos)
9699 #define SPI_VARCLK_VARCLK_Pos (0)
9700 #define SPI_VARCLK_VARCLK_Msk (0xfffffffful << SPI_VARCLK_VARCLK_Pos)
9702 #define SPI_DMA_TX_DMA_EN_Pos (0)
9703 #define SPI_DMA_TX_DMA_EN_Msk (0x1ul << SPI_DMA_TX_DMA_EN_Pos)
9705 #define SPI_DMA_RX_DMA_EN_Pos (1)
9706 #define SPI_DMA_RX_DMA_EN_Msk (0x1ul << SPI_DMA_RX_DMA_EN_Pos)
9708 #define SPI_DMA_PDMA_RST_Pos (2)
9709 #define SPI_DMA_PDMA_RST_Msk (0x1ul << SPI_DMA_PDMA_RST_Pos)
9711 #define SPI_FFCTL_RX_CLR_Pos (0)
9712 #define SPI_FFCTL_RX_CLR_Msk (0x1ul << SPI_FFCTL_RX_CLR_Pos)
9714 #define SPI_FFCTL_TX_CLR_Pos (1)
9715 #define SPI_FFCTL_TX_CLR_Msk (0x1ul << SPI_FFCTL_TX_CLR_Pos)
9717 #define SPI_FFCTL_RX_INTEN_Pos (2)
9718 #define SPI_FFCTL_RX_INTEN_Msk (0x1ul << SPI_FFCTL_RX_INTEN_Pos)
9720 #define SPI_FFCTL_TX_INTEN_Pos (3)
9721 #define SPI_FFCTL_TX_INTEN_Msk (0x1ul << SPI_FFCTL_TX_INTEN_Pos)
9723 #define SPI_FFCTL_RXOVR_INTEN_Pos (4)
9724 #define SPI_FFCTL_RXOVR_INTEN_Msk (0x1ul << SPI_FFCTL_RXOVR_INTEN_Pos)
9726 #define SPI_FFCTL_TIMEOUT_EN_Pos (7)
9727 #define SPI_FFCTL_TIMEOUT_EN_Msk (0x1ul << SPI_FFCTL_TIMEOUT_EN_Pos)
9729 #define SPI_FFCTL_RX_THRESHOLD_Pos (24)
9730 #define SPI_FFCTL_RX_THRESHOLD_Msk (0x7ul << SPI_FFCTL_RX_THRESHOLD_Pos)
9732 #define SPI_FFCTL_TX_THRESHOLD_Pos (28)
9733 #define SPI_FFCTL_TX_THRESHOLD_Msk (0x7ul << SPI_FFCTL_TX_THRESHOLD_Pos) /* SPI_CONST */
9736 /* end of SPI register group */
9737
9738
9739 /*---------------------- Timer Controller -------------------------*/
9745 typedef struct
9746 {
9747
9748
9885 __IO uint32_t CTL;
9886
9898 __IO uint32_t PRECNT;
9899
9915 __IO uint32_t CMPR;
9916
9933 __IO uint32_t IER;
9934
9964 __IO uint32_t ISR;
9965
9976 __I uint32_t DR;
9977
9989 __I uint32_t TCAP;
9990 } TIMER_T;
9991
9992
9998 #define TIMER_CTL_TMR_EN_Pos (0)
9999 #define TIMER_CTL_TMR_EN_Msk (0x1ul << TIMER_CTL_TMR_EN_Pos)
10001 #define TIMER_CTL_SW_RST_Pos (1)
10002 #define TIMER_CTL_SW_RST_Msk (0x1ul << TIMER_CTL_SW_RST_Pos)
10004 #define TIMER_CTL_WAKE_EN_Pos (2)
10005 #define TIMER_CTL_WAKE_EN_Msk (0x1ul << TIMER_CTL_WAKE_EN_Pos)
10007 #define TIMER_CTL_DBGACK_EN_Pos (3)
10008 #define TIMER_CTL_DBGACK_EN_Msk (0x1ul << TIMER_CTL_DBGACK_EN_Pos)
10010 #define TIMER_CTL_MODE_SEL_Pos (4)
10011 #define TIMER_CTL_MODE_SEL_Msk (0x3ul << TIMER_CTL_MODE_SEL_Pos)
10013 #define TIMER_CTL_TMR_ACT_Pos (7)
10014 #define TIMER_CTL_TMR_ACT_Msk (0x1ul << TIMER_CTL_TMR_ACT_Pos)
10016 #define TIMER_CTL_ADC_TEEN_Pos (8)
10017 #define TIMER_CTL_ADC_TEEN_Msk (0x1ul << TIMER_CTL_ADC_TEEN_Pos)
10019 #define TIMER_CTL_DAC_TEEN_Pos (9)
10020 #define TIMER_CTL_DAC_TEEN_Msk (0x1ul << TIMER_CTL_DAC_TEEN_Pos)
10022 #define TIMER_CTL_PDMA_TEEN_Pos (10)
10023 #define TIMER_CTL_PDMA_TEEN_Msk (0x1ul << TIMER_CTL_PDMA_TEEN_Pos)
10025 #define TIMER_CTL_CAP_TRG_EN_Pos (11)
10026 #define TIMER_CTL_CAP_TRG_EN_Msk (0x1ul << TIMER_CTL_CAP_TRG_EN_Pos)
10028 #define TIMER_CTL_EVENT_EN_Pos (12)
10029 #define TIMER_CTL_EVENT_EN_Msk (0x1ul << TIMER_CTL_EVENT_EN_Pos)
10031 #define TIMER_CTL_EVENT_EDGE_Pos (13)
10032 #define TIMER_CTL_EVENT_EDGE_Msk (0x1ul << TIMER_CTL_EVENT_EDGE_Pos)
10034 #define TIMER_CTL_EVNT_DEB_EN_Pos (14)
10035 #define TIMER_CTL_EVNT_DEB_EN_Msk (0x1ul << TIMER_CTL_EVNT_DEB_EN_Pos)
10037 #define TIMER_CTL_TCAP_EN_Pos (16)
10038 #define TIMER_CTL_TCAP_EN_Msk (0x1ul << TIMER_CTL_TCAP_EN_Pos)
10040 #define TIMER_CTL_TCAP_MODE_Pos (17)
10041 #define TIMER_CTL_TCAP_MODE_Msk (0x1ul << TIMER_CTL_TCAP_MODE_Pos)
10043 #define TIMER_CTL_TCAP_EDGE_Pos (18)
10044 #define TIMER_CTL_TCAP_EDGE_Msk (0x3ul << TIMER_CTL_TCAP_EDGE_Pos)
10046 #define TIMER_CTL_TCAP_CNT_MODE_Pos (20)
10047 #define TIMER_CTL_TCAP_CNT_MODE_Msk (0x1ul << TIMER_CTL_TCAP_CNT_MODE_Pos)
10049 #define TIMER_CTL_TCAP_DEB_EN_Pos (22)
10050 #define TIMER_CTL_TCAP_DEB_EN_Msk (0x1ul << TIMER_CTL_TCAP_DEB_EN_Pos)
10052 #define TIMER_CTL_INTR_TRG_EN_Pos (24)
10053 #define TIMER_CTL_INTR_TRG_EN_Msk (0x1ul << TIMER_CTL_INTR_TRG_EN_Pos)
10055 #define TIMER_PRECNT_PRESCALE_CNT_Pos (0)
10056 #define TIMER_PRECNT_PRESCALE_CNT_Msk (0xfful << TIMER_PRECNT_PRESCALE_CNT_Pos)
10058 #define TIMER_CMPR_TMR_CMP_Pos (0)
10059 #define TIMER_CMPR_TMR_CMP_Msk (0xfffffful << TIMER_CMPR_TMR_CMP_Pos)
10061 #define TIMER_IER_TMR_IE_Pos (0)
10062 #define TIMER_IER_TMR_IE_Msk (0x1ul << TIMER_IER_TMR_IE_Pos)
10064 #define TIMER_IER_TCAP_IE_Pos (1)
10065 #define TIMER_IER_TCAP_IE_Msk (0x1ul << TIMER_IER_TCAP_IE_Pos)
10067 #define TIMER_ISR_TMR_IS_Pos (0)
10068 #define TIMER_ISR_TMR_IS_Msk (0x1ul << TIMER_ISR_TMR_IS_Pos)
10070 #define TIMER_ISR_TCAP_IS_Pos (1)
10071 #define TIMER_ISR_TCAP_IS_Msk (0x1ul << TIMER_ISR_TCAP_IS_Pos)
10073 #define TIMER_ISR_TMR_WAKE_STS_Pos (4)
10074 #define TIMER_ISR_TMR_WAKE_STS_Msk (0x1ul << TIMER_ISR_TMR_WAKE_STS_Pos)
10076 #define TIMER_ISR_NCAP_DET_STS_Pos (5)
10077 #define TIMER_ISR_NCAP_DET_STS_Msk (0x1ul << TIMER_ISR_NCAP_DET_STS_Pos)
10079 #define TIMER_DR_TDR_Pos (0)
10080 #define TIMER_DR_TDR_Msk (0xfffffful << TIMER_DR_TDR_Pos)
10082 #define TIMER_TCAP_CAP_Pos (0)
10083 #define TIMER_TCAP_CAP_Msk (0xfffffful << TIMER_TCAP_CAP_Pos) /* TMR_CONST */
10086
10087 /* end of TMR register group */
10089
10090
10091
10092 /*---------------------- Universal Asynchronous Receiver/Transmitter Controller -------------------------*/
10098 typedef struct
10099 {
10100
10101
10102 union
10103 {
10104
10115 __I uint32_t RBR;
10116
10117
10128 __O uint32_t THR;
10129 };
10130
10187 __IO uint32_t CTL;
10188
10233 __IO uint32_t TLCTL;
10234
10270 __IO uint32_t IER;
10271
10318 __IO uint32_t ISR;
10319
10370 __IO uint32_t TRSR;
10371
10421 __IO uint32_t FSR;
10422
10448 __IO uint32_t MCSR;
10449
10471 __IO uint32_t TMCTL;
10472
10487 __IO uint32_t BAUD;
10488 uint32_t RESERVE0[2];
10489
10490
10509 __IO uint32_t IRCR;
10510
10562 __IO uint32_t ALT_CTL;
10563
10577 __IO uint32_t FUN_SEL;
10578
10579 } UART_T;
10580
10586 #define UART_DAT_DAT_Pos (0)
10587 #define UART_DAT_DAT_Msk (0xfful << UART_DAT_DAT_Pos)
10589 #define UART_CTL_RX_RST_Pos (0)
10590 #define UART_CTL_RX_RST_Msk (0x1ul << UART_CTL_RX_RST_Pos)
10592 #define UART_CTL_TX_RST_Pos (1)
10593 #define UART_CTL_TX_RST_Msk (0x1ul << UART_CTL_TX_RST_Pos)
10595 #define UART_CTL_RX_DIS_Pos (2)
10596 #define UART_CTL_RX_DIS_Msk (0x1ul << UART_CTL_RX_DIS_Pos)
10598 #define UART_CTL_TX_DIS_Pos (3)
10599 #define UART_CTL_TX_DIS_Msk (0x1ul << UART_CTL_TX_DIS_Pos)
10601 #define UART_CTL_AUTO_RTS_EN_Pos (4)
10602 #define UART_CTL_AUTO_RTS_EN_Msk (0x1ul << UART_CTL_AUTO_RTS_EN_Pos)
10604 #define UART_CTL_AUTO_CTS_EN_Pos (5)
10605 #define UART_CTL_AUTO_CTS_EN_Msk (0x1ul << UART_CTL_AUTO_CTS_EN_Pos)
10607 #define UART_CTL_DMA_RX_EN_Pos (6)
10608 #define UART_CTL_DMA_RX_EN_Msk (0x1ul << UART_CTL_DMA_RX_EN_Pos)
10610 #define UART_CTL_DMA_TX_EN_Pos (7)
10611 #define UART_CTL_DMA_TX_EN_Msk (0x1ul << UART_CTL_DMA_TX_EN_Pos)
10613 #define UART_CTL_WAKE_CTS_EN_Pos (8)
10614 #define UART_CTL_WAKE_CTS_EN_Msk (0x1ul << UART_CTL_WAKE_CTS_EN_Pos)
10616 #define UART_CTL_WAKE_DATA_EN_Pos (9)
10617 #define UART_CTL_WAKE_DATA_EN_Msk (0x1ul << UART_CTL_WAKE_DATA_EN_Pos)
10619 #define UART_CTL_ABAUD_EN_Pos (12)
10620 #define UART_CTL_ABAUD_EN_Msk (0x1ul << UART_CTL_ABAUD_EN_Pos)
10622 #define UART_TLCTL_DATA_LEN_Pos (0)
10623 #define UART_TLCTL_DATA_LEN_Msk (0x3ul << UART_TLCTL_DATA_LEN_Pos)
10625 #define UART_TLCTL_NSB_Pos (2)
10626 #define UART_TLCTL_NSB_Msk (0x1ul << UART_TLCTL_NSB_Pos)
10628 #define UART_TLCTL_PBE_Pos (3)
10629 #define UART_TLCTL_PBE_Msk (0x1ul << UART_TLCTL_PBE_Pos)
10631 #define UART_TLCTL_EPE_Pos (4)
10632 #define UART_TLCTL_EPE_Msk (0x1ul << UART_TLCTL_EPE_Pos)
10634 #define UART_TLCTL_SPE_Pos (5)
10635 #define UART_TLCTL_SPE_Msk (0x1ul << UART_TLCTL_SPE_Pos)
10637 #define UART_TLCTL_BCB_Pos (6)
10638 #define UART_TLCTL_BCB_Msk (0x1ul << UART_TLCTL_BCB_Pos)
10640 #define UART_TLCTL_RFITL_Pos (8)
10641 #define UART_TLCTL_RFITL_Msk (0x3ul << UART_TLCTL_RFITL_Pos)
10643 #define UART_TLCTL_RTS_TRI_LEV_Pos (12)
10644 #define UART_TLCTL_RTS_TRI_LEV_Msk (0x3ul << UART_TLCTL_RTS_TRI_LEV_Pos)
10646 #define UART_IER_RDA_IE_Pos (0)
10647 #define UART_IER_RDA_IE_Msk (0x1ul << UART_IER_RDA_IE_Pos)
10649 #define UART_IER_THRE_IE_Pos (1)
10650 #define UART_IER_THRE_IE_Msk (0x1ul << UART_IER_THRE_IE_Pos)
10652 #define UART_IER_RLS_IE_Pos (2)
10653 #define UART_IER_RLS_IE_Msk (0x1ul << UART_IER_RLS_IE_Pos)
10655 #define UART_IER_MODEM_IE_Pos (3)
10656 #define UART_IER_MODEM_IE_Msk (0x1ul << UART_IER_MODEM_IE_Pos)
10658 #define UART_IER_RTO_IE_Pos (4)
10659 #define UART_IER_RTO_IE_Msk (0x1ul << UART_IER_RTO_IE_Pos)
10661 #define UART_IER_BUF_ERR_IE_Pos (5)
10662 #define UART_IER_BUF_ERR_IE_Msk (0x1ul << UART_IER_BUF_ERR_IE_Pos)
10664 #define UART_IER_WAKE_IE_Pos (6)
10665 #define UART_IER_WAKE_IE_Msk (0x1ul << UART_IER_WAKE_IE_Pos)
10667 #define UART_IER_ABAUD_IE_Pos (7)
10668 #define UART_IER_ABAUD_IE_Msk (0x1ul << UART_IER_ABAUD_IE_Pos)
10670 #define UART_IER_LIN_IE_Pos (8)
10671 #define UART_IER_LIN_IE_Msk (0x1ul << UART_IER_LIN_IE_Pos)
10673 #define UART_ISR_RDA_IS_Pos (0)
10674 #define UART_ISR_RDA_IS_Msk (0x1ul << UART_ISR_RDA_IS_Pos)
10676 #define UART_ISR_THRE_IS_Pos (1)
10677 #define UART_ISR_THRE_IS_Msk (0x1ul << UART_ISR_THRE_IS_Pos)
10679 #define UART_ISR_RLS_IS_Pos (2)
10680 #define UART_ISR_RLS_IS_Msk (0x1ul << UART_ISR_RLS_IS_Pos)
10682 #define UART_ISR_MODEM_IS_Pos (3)
10683 #define UART_ISR_MODEM_IS_Msk (0x1ul << UART_ISR_MODEM_IS_Pos)
10685 #define UART_ISR_RTO_IS_Pos (4)
10686 #define UART_ISR_RTO_IS_Msk (0x1ul << UART_ISR_RTO_IS_Pos)
10688 #define UART_ISR_BUF_ERR_IS_Pos (5)
10689 #define UART_ISR_BUF_ERR_IS_Msk (0x1ul << UART_ISR_BUF_ERR_IS_Pos)
10691 #define UART_ISR_WAKE_IS_Pos (6)
10692 #define UART_ISR_WAKE_IS_Msk (0x1ul << UART_ISR_WAKE_IS_Pos)
10694 #define UART_ISR_ABAUD_IS_Pos (7)
10695 #define UART_ISR_ABAUD_IS_Msk (0x1ul << UART_ISR_ABAUD_IS_Pos)
10697 #define UART_ISR_LIN_IS_Pos (8)
10698 #define UART_ISR_LIN_IS_Msk (0x1ul << UART_ISR_LIN_IS_Pos)
10700 #define UART_TRSR_RS485_ADDET_F_Pos (0)
10701 #define UART_TRSR_RS485_ADDET_F_Msk (0x1ul << UART_TRSR_RS485_ADDET_F_Pos)
10703 #define UART_TRSR_ABAUD_F_Pos (1)
10704 #define UART_TRSR_ABAUD_F_Msk (0x1ul << UART_TRSR_ABAUD_F_Pos)
10706 #define UART_TRSR_ABAUD_TOUT_F_Pos (2)
10707 #define UART_TRSR_ABAUD_TOUT_F_Msk (0x1ul << UART_TRSR_ABAUD_TOUT_F_Pos)
10709 #define UART_TRSR_LIN_TX_F_Pos (3)
10710 #define UART_TRSR_LIN_TX_F_Msk (0x1ul << UART_TRSR_LIN_TX_F_Pos)
10712 #define UART_TRSR_LIN_RX_F_Pos (4)
10713 #define UART_TRSR_LIN_RX_F_Msk (0x1ul << UART_TRSR_LIN_RX_F_Pos)
10715 #define UART_TRSR_BIT_ERR_F_Pos (5)
10716 #define UART_TRSR_BIT_ERR_F_Msk (0x1ul << UART_TRSR_BIT_ERR_F_Pos)
10718 #define UART_TRSR_LIN_RX_SYNC_ERR_F_Pos (8)
10719 #define UART_TRSR_LIN_RX_SYNC_ERR_F_Msk (0x1ul << UART_TRSR_LIN_RX_SYNC_ERR_F_Pos)
10721 #define UART_FSR_RX_OVER_F_Pos (0)
10722 #define UART_FSR_RX_OVER_F_Msk (0x1ul << UART_FSR_RX_OVER_F_Pos)
10724 #define UART_FSR_RX_EMPTY_F_Pos (1)
10725 #define UART_FSR_RX_EMPTY_F_Msk (0x1ul << UART_FSR_RX_EMPTY_F_Pos)
10727 #define UART_FSR_RX_FULL_F_Pos (2)
10728 #define UART_FSR_RX_FULL_F_Msk (0x1ul << UART_FSR_RX_FULL_F_Pos)
10730 #define UART_FSR_PE_F_Pos (4)
10731 #define UART_FSR_PE_F_Msk (0x1ul << UART_FSR_PE_F_Pos)
10733 #define UART_FSR_FE_F_Pos (5)
10734 #define UART_FSR_FE_F_Msk (0x1ul << UART_FSR_FE_F_Pos)
10736 #define UART_FSR_BI_F_Pos (6)
10737 #define UART_FSR_BI_F_Msk (0x1ul << UART_FSR_BI_F_Pos)
10739 #define UART_FSR_TX_OVER_F_Pos (8)
10740 #define UART_FSR_TX_OVER_F_Msk (0x1ul << UART_FSR_TX_OVER_F_Pos)
10742 #define UART_FSR_TX_EMPTY_F_Pos (9)
10743 #define UART_FSR_TX_EMPTY_F_Msk (0x1ul << UART_FSR_TX_EMPTY_F_Pos)
10745 #define UART_FSR_TX_FULL_F_Pos (10)
10746 #define UART_FSR_TX_FULL_F_Msk (0x1ul << UART_FSR_TX_FULL_F_Pos)
10748 #define UART_FSR_TE_F_Pos (11)
10749 #define UART_FSR_TE_F_Msk (0x1ul << UART_FSR_TE_F_Pos)
10751 #define UART_FSR_RX_POINTER_F_Pos (16)
10752 #define UART_FSR_RX_POINTER_F_Msk (0x1ful << UART_FSR_RX_POINTER_F_Pos)
10754 #define UART_FSR_TX_POINTER_F_Pos (24)
10755 #define UART_FSR_TX_POINTER_F_Msk (0x1ful << UART_FSR_TX_POINTER_F_Pos)
10757 #define UART_MCSR_LEV_RTS_Pos (0)
10758 #define UART_MCSR_LEV_RTS_Msk (0x1ul << UART_MCSR_LEV_RTS_Pos)
10760 #define UART_MCSR_RTS_ST_Pos (1)
10761 #define UART_MCSR_RTS_ST_Msk (0x1ul << UART_MCSR_RTS_ST_Pos)
10763 #define UART_MCSR_LEV_CTS_Pos (16)
10764 #define UART_MCSR_LEV_CTS_Msk (0x1ul << UART_MCSR_LEV_CTS_Pos)
10766 #define UART_MCSR_CTS_ST_Pos (17)
10767 #define UART_MCSR_CTS_ST_Msk (0x1ul << UART_MCSR_CTS_ST_Pos)
10769 #define UART_MCSR_DCT_F_Pos (18)
10770 #define UART_MCSR_DCT_F_Msk (0x1ul << UART_MCSR_DCT_F_Pos)
10772 #define UART_TMCTL_TOIC_Pos (0)
10773 #define UART_TMCTL_TOIC_Msk (0x1fful << UART_TMCTL_TOIC_Pos)
10775 #define UART_TMCTL_DLY_Pos (16)
10776 #define UART_TMCTL_DLY_Msk (0xfful << UART_TMCTL_DLY_Pos)
10778 #define UART_BAUD_BRD_Pos (0)
10779 #define UART_BAUD_BRD_Msk (0xfffful << UART_BAUD_BRD_Pos)
10781 #define UART_BAUD_DIV_16_EN_Pos (31)
10782 #define UART_BAUD_DIV_16_EN_Msk (0x1ul << UART_BAUD_DIV_16_EN_Pos)
10784 #define UART_IRCR_TX_SELECT_Pos (1)
10785 #define UART_IRCR_TX_SELECT_Msk (0x1ul << UART_IRCR_TX_SELECT_Pos)
10787 #define UART_IRCR_INV_TX_Pos (5)
10788 #define UART_IRCR_INV_TX_Msk (0x1ul << UART_IRCR_INV_TX_Pos)
10790 #define UART_IRCR_INV_RX_Pos (6)
10791 #define UART_IRCR_INV_RX_Msk (0x1ul << UART_IRCR_INV_RX_Pos)
10793 #define UART_ALT_CTL_LIN_TX_BCNT_Pos (0)
10794 #define UART_ALT_CTL_LIN_TX_BCNT_Msk (0x7ul << UART_ALT_CTL_LIN_TX_BCNT_Pos)
10796 #define UART_ALT_CTL_LIN_HEAD_SEL_Pos (4)
10797 #define UART_ALT_CTL_LIN_HEAD_SEL_Msk (0x3ul << UART_ALT_CTL_LIN_HEAD_SEL_Pos)
10799 #define UART_ALT_CTL_LIN_RX_EN_Pos (6)
10800 #define UART_ALT_CTL_LIN_RX_EN_Msk (0x1ul << UART_ALT_CTL_LIN_RX_EN_Pos)
10802 #define UART_ALT_CTL_LIN_TX_EN_Pos (7)
10803 #define UART_ALT_CTL_LIN_TX_EN_Msk (0x1ul << UART_ALT_CTL_LIN_TX_EN_Pos)
10805 #define UART_ALT_CTL_Bit_ERR_EN_Pos (8)
10806 #define UART_ALT_CTL_Bit_ERR_EN_Msk (0x1ul << UART_ALT_CTL_Bit_ERR_EN_Pos)
10808 #define UART_ALT_CTL_RS485_NMM_Pos (16)
10809 #define UART_ALT_CTL_RS485_NMM_Msk (0x1ul << UART_ALT_CTL_RS485_NMM_Pos)
10811 #define UART_ALT_CTL_RS485_AAD_Pos (17)
10812 #define UART_ALT_CTL_RS485_AAD_Msk (0x1ul << UART_ALT_CTL_RS485_AAD_Pos)
10814 #define UART_ALT_CTL_RS485_AUD_Pos (18)
10815 #define UART_ALT_CTL_RS485_AUD_Msk (0x1ul << UART_ALT_CTL_RS485_AUD_Pos)
10817 #define UART_ALT_CTL_RS485_ADD_EN_Pos (19)
10818 #define UART_ALT_CTL_RS485_ADD_EN_Msk (0x1ul << UART_ALT_CTL_RS485_ADD_EN_Pos)
10820 #define UART_ALT_CTL_ADDR_PID_MATCH_Pos (24)
10821 #define UART_ALT_CTL_ADDR_PID_MATCH_Msk (0xfful << UART_ALT_CTL_ADDR_PID_MATCH_Pos)
10823 #define UART_FUN_SEL_FUN_SEL_Pos (0)
10824 #define UART_FUN_SEL_FUN_SEL_Msk (0x3ul << UART_FUN_SEL_FUN_SEL_Pos) /* UART_CONST */
10827 /* end of UART register group */
10828
10829
10830 /*---------------------- USB Device Controller -------------------------*/
10839 typedef struct
10840 {
10841
10842
10853 __IO uint32_t BUFSEG;
10854
10873 __IO uint32_t MXPLD;
10874
10910 __IO uint32_t CFG;
10911 uint32_t RESERVE;
10912
10913 } USBD_EP_T;
10914
10915 typedef struct
10916 {
10917
10918
10950 __IO uint32_t CTL;
10951
10971 __I uint32_t BUSSTS;
10972
10993 __IO uint32_t INTEN;
10994
11046 __IO uint32_t INTSTS;
11047
11057 __IO uint32_t FADDR;
11058
11094 __I uint32_t EPSTS;
11095
11107 __IO uint32_t BUFSEG;
11108
11123 __I uint32_t EPSTS2;
11124
11125
11126 USBD_EP_T EP[8];
11127
11128 uint32_t RESERVE0;
11129
11153 __IO uint32_t PDMA;
11154
11155 } USBD_T;
11156
11162 #define USBD_CTL_USB_EN_Pos (0)
11163 #define USBD_CTL_USB_EN_Msk (0x1ul << USBD_CTL_USB_EN_Pos)
11165 #define USBD_CTL_PHY_EN_Pos (1)
11166 #define USBD_CTL_PHY_EN_Msk (0x1ul << USBD_CTL_PHY_EN_Pos)
11168 #define USBD_CTL_PWRDB_Pos (2)
11169 #define USBD_CTL_PWRDB_Msk (0x1ul << USBD_CTL_PWRDB_Pos)
11171 #define USBD_CTL_DPPU_EN_Pos (3)
11172 #define USBD_CTL_DPPU_EN_Msk (0x1ul << USBD_CTL_DPPU_EN_Pos)
11174 #define USBD_CTL_DRVSE0_Pos (4)
11175 #define USBD_CTL_DRVSE0_Msk (0x1ul << USBD_CTL_DRVSE0_Pos)
11177 #define USBD_CTL_RWAKEUP_Pos (8)
11178 #define USBD_CTL_RWAKEUP_Msk (0x1ul << USBD_CTL_RWAKEUP_Pos)
11180 #define USBD_CTL_WAKEUP_EN_Pos (9)
11181 #define USBD_CTL_WAKEUP_EN_Msk (0x1ul << USBD_CTL_WAKEUP_EN_Pos)
11183 #define USBD_BUSSTS_USBRST_Pos (0)
11184 #define USBD_BUSSTS_USBRST_Msk (0x1ul << USBD_BUSSTS_USBRST_Pos)
11186 #define USBD_BUSSTS_SUSPEND_Pos (1)
11187 #define USBD_BUSSTS_SUSPEND_Msk (0x1ul << USBD_BUSSTS_SUSPEND_Pos)
11189 #define USBD_BUSSTS_RESUME_Pos (2)
11190 #define USBD_BUSSTS_RESUME_Msk (0x1ul << USBD_BUSSTS_RESUME_Pos)
11192 #define USBD_BUSSTS_TIMEOUT_Pos (3)
11193 #define USBD_BUSSTS_TIMEOUT_Msk (0x1ul << USBD_BUSSTS_TIMEOUT_Pos)
11195 #define USBD_BUSSTS_FLDET_Pos (4)
11196 #define USBD_BUSSTS_FLDET_Msk (0x1ul << USBD_BUSSTS_FLDET_Pos)
11198 #define USBD_INTEN_BUSEVT_IE_Pos (0)
11199 #define USBD_INTEN_BUSEVT_IE_Msk (0x1ul << USBD_INTEN_BUSEVT_IE_Pos)
11201 #define USBD_INTEN_USBEVT_IE_Pos (1)
11202 #define USBD_INTEN_USBEVT_IE_Msk (0x1ul << USBD_INTEN_USBEVT_IE_Pos)
11204 #define USBD_INTEN_FLDET_IE_Pos (2)
11205 #define USBD_INTEN_FLDET_IE_Msk (0x1ul << USBD_INTEN_FLDET_IE_Pos)
11207 #define USBD_INTEN_WAKEUP_IE_Pos (3)
11208 #define USBD_INTEN_WAKEUP_IE_Msk (0x1ul << USBD_INTEN_WAKEUP_IE_Pos)
11210 #define USBD_INTSTS_BUS_STS_Pos (0)
11211 #define USBD_INTSTS_BUS_STS_Msk (0x1ul << USBD_INTSTS_BUS_STS_Pos)
11213 #define USBD_INTSTS_USB_STS_Pos (1)
11214 #define USBD_INTSTS_USB_STS_Msk (0x1ul << USBD_INTSTS_USB_STS_Pos)
11216 #define USBD_INTSTS_FLD_STS_Pos (2)
11217 #define USBD_INTSTS_FLD_STS_Msk (0x1ul << USBD_INTSTS_FLD_STS_Pos)
11219 #define USBD_INTSTS_WKEUP_STS_Pos (3)
11220 #define USBD_INTSTS_WKEUP_STS_Msk (0x1ul << USBD_INTSTS_WKEUP_STS_Pos)
11222 #define USBD_INTSTS_EPEVT0_Pos (16)
11223 #define USBD_INTSTS_EPEVT0_Msk (0x1ul << USBD_INTSTS_EPEVT0_Pos)
11225 #define USBD_INTSTS_EPEVT1_Pos (17)
11226 #define USBD_INTSTS_EPEVT1_Msk (0x1ul << USBD_INTSTS_EPEVT1_Pos)
11228 #define USBD_INTSTS_EPEVT2_Pos (18)
11229 #define USBD_INTSTS_EPEVT2_Msk (0x1ul << USBD_INTSTS_EPEVT2_Pos)
11231 #define USBD_INTSTS_EPEVT3_Pos (19)
11232 #define USBD_INTSTS_EPEVT3_Msk (0x1ul << USBD_INTSTS_EPEVT3_Pos)
11234 #define USBD_INTSTS_EPEVT4_Pos (20)
11235 #define USBD_INTSTS_EPEVT4_Msk (0x1ul << USBD_INTSTS_EPEVT4_Pos)
11237 #define USBD_INTSTS_EPEVT5_Pos (21)
11238 #define USBD_INTSTS_EPEVT5_Msk (0x1ul << USBD_INTSTS_EPEVT5_Pos)
11240 #define USBD_INTSTS_EPEVT6_Pos (22)
11241 #define USBD_INTSTS_EPEVT6_Msk (0x1ul << USBD_INTSTS_EPEVT6_Pos)
11243 #define USBD_INTSTS_EPEVT7_Pos (23)
11244 #define USBD_INTSTS_EPEVT7_Msk (0x1ul << USBD_INTSTS_EPEVT7_Pos)
11246 #define USBD_INTSTS_SETUP_Pos (31)
11247 #define USBD_INTSTS_SETUP_Msk (0x1ul << USBD_INTSTS_SETUP_Pos)
11249 #define USBD_FADDR_FADDR_Pos (0)
11250 #define USBD_FADDR_FADDR_Msk (0x7ful << USBD_FADDR_FADDR_Pos)
11252 #define USBD_EPSTS_OVERRUN_Pos (7)
11253 #define USBD_EPSTS_OVERRUN_Msk (0x1ul << USBD_EPSTS_OVERRUN_Pos)
11255 #define USBD_EPSTS_EPSTS0_Pos (8)
11256 #define USBD_EPSTS_EPSTS0_Msk (0xful << USBD_EPSTS_EPSTS0_Pos)
11258 #define USBD_EPSTS_EPSTS1_Pos (12)
11259 #define USBD_EPSTS_EPSTS1_Msk (0xful << USBD_EPSTS_EPSTS1_Pos)
11261 #define USBD_EPSTS_EPSTS2_Pos (16)
11262 #define USBD_EPSTS_EPSTS2_Msk (0xful << USBD_EPSTS_EPSTS2_Pos)
11264 #define USBD_EPSTS_EPSTS3_Pos (20)
11265 #define USBD_EPSTS_EPSTS3_Msk (0xful << USBD_EPSTS_EPSTS3_Pos)
11267 #define USBD_EPSTS_EPSTS4_Pos (24)
11268 #define USBD_EPSTS_EPSTS4_Msk (0xful << USBD_EPSTS_EPSTS4_Pos)
11270 #define USBD_EPSTS_EPSTS5_Pos (28)
11271 #define USBD_EPSTS_EPSTS5_Msk (0xful << USBD_EPSTS_EPSTS5_Pos)
11273 #define USBD_BUFSEG_BUFSEG_Pos (3)
11274 #define USBD_BUFSEG_BUFSEG_Msk (0x3ful << USBD_BUFSEG_BUFSEG_Pos)
11276 #define USBD_EPSTS2_EPSTS6_Pos (0)
11277 #define USBD_EPSTS2_EPSTS6_Msk (0x7ul << USBD_EPSTS2_EPSTS6_Pos)
11279 #define USBD_EPSTS2_EPSTS7_Pos (4)
11280 #define USBD_EPSTS2_EPSTS7_Msk (0x7ul << USBD_EPSTS2_EPSTS7_Pos)
11282 #define USBD_BUFSEG_BUFSEG_Pos (3)
11283 #define USBD_BUFSEG_BUFSEG_Msk (0x3ful << USBD_BUFSEG_BUFSEG_Pos)
11285 #define USBD_MXPLD_MXPLD_Pos (0)
11286 #define USBD_MXPLD_MXPLD_Msk (0x1fful << USBD_MXPLD_MXPLD_Pos)
11288 #define USBD_CFG_EP_NUM_Pos (0)
11289 #define USBD_CFG_EP_NUM_Msk (0xful << USBD_CFG_EP_NUM_Pos)
11291 #define USBD_CFG_ISOCH_Pos (4)
11292 #define USBD_CFG_ISOCH_Msk (0x1ul << USBD_CFG_ISOCH_Pos)
11294 #define USBD_CFG_EPMODE_Pos (5)
11295 #define USBD_CFG_EPMODE_Msk (0x3ul << USBD_CFG_EPMODE_Pos)
11297 #define USBD_CFG_DSQ_SYNC_Pos (7)
11298 #define USBD_CFG_DSQ_SYNC_Msk (0x1ul << USBD_CFG_DSQ_SYNC_Pos)
11300 #define USBD_CFG_CSTALL_Pos (8)
11301 #define USBD_CFG_CSTALL_Msk (0x1ul << USBD_CFG_CSTALL_Pos)
11303 #define USBD_CFG_SSTALL_Pos (9)
11304 #define USBD_CFG_SSTALL_Msk (0x1ul << USBD_CFG_SSTALL_Pos)
11306 #define USBD_CFG_CLRRDY_Pos (15)
11307 #define USBD_CFG_CLRRDY_Msk (0x1ul << USBD_CFG_CLRRDY_Pos)
11309 #define USBD_PDMA_PDMA_RW_Pos (0)
11310 #define USBD_PDMA_PDMA_RW_Msk (0x1ul << USBD_PDMA_PDMA_RW_Pos)
11312 #define USBD_PDMA_PDMA_TRG_Pos (1)
11313 #define USBD_PDMA_PDMA_TRG_Msk (0x1ul << USBD_PDMA_PDMA_TRG_Pos)
11315 #define USBD_PDMA_BYTEM_Pos (2)
11316 #define USBD_PDMA_BYTEM_Msk (0x1ul << USBD_PDMA_BYTEM_Pos)
11318 #define USBD_PDMA_PDMA_RST_Pos (3)
11319 #define USBD_PDMA_PDMA_RST_Msk (0x1ul << USBD_PDMA_PDMA_RST_Pos) /* USBD_CONST */
11322 /* end of USBD register group */
11323
11324
11325 /*---------------------- Watch Dog Timer Controller -------------------------*/
11331 typedef struct
11332 {
11333
11334
11375 __IO uint32_t CTL;
11376
11388 __IO uint32_t IER;
11389
11419 __IO uint32_t ISR;
11420
11421 } WDT_T;
11422
11428 #define WDT_CTL_WTR_Pos (0)
11429 #define WDT_CTL_WTR_Msk (0x1ul << WDT_CTL_WTR_Pos)
11431 #define WDT_CTL_WTRE_Pos (1)
11432 #define WDT_CTL_WTRE_Msk (0x1ul << WDT_CTL_WTRE_Pos)
11434 #define WDT_CTL_WTWKE_Pos (2)
11435 #define WDT_CTL_WTWKE_Msk (0x1ul << WDT_CTL_WTWKE_Pos)
11437 #define WDT_CTL_WTE_Pos (3)
11438 #define WDT_CTL_WTE_Msk (0x1ul << WDT_CTL_WTE_Pos)
11440 #define WDT_CTL_WTIS_Pos (4)
11441 #define WDT_CTL_WTIS_Msk (0x7ul << WDT_CTL_WTIS_Pos)
11443 #define WDT_CTL_WTRDSEL_Pos (8)
11444 #define WDT_CTL_WTRDSEL_Msk (0x3ul << WDT_CTL_WTRDSEL_Pos)
11446 #define WDT_IER_IE_Pos (0)
11447 #define WDT_IER_IE_Msk (0x1ul << WDT_IER_IE_Pos)
11449 #define WDT_ISR_IS_Pos (0)
11450 #define WDT_ISR_IS_Msk (0x1ul << WDT_ISR_IS_Pos)
11452 #define WDT_ISR_RST_IS_Pos (1)
11453 #define WDT_ISR_RST_IS_Msk (0x1ul << WDT_ISR_RST_IS_Pos)
11455 #define WDT_ISR_WAKE_IS_Pos (2)
11456 #define WDT_ISR_WAKE_IS_Msk (0x1ul << WDT_ISR_WAKE_IS_Pos) /* WDT_CONST */
11459 /* end of WDT register group */
11460
11461
11462 /*---------------------- Window Watchdog Timer -------------------------*/
11468 typedef struct
11469 {
11470
11471
11484 __O uint32_t RLD;
11485
11508 __IO uint32_t CR;
11509
11522 __IO uint32_t IER;
11523
11538 __IO uint32_t STS;
11539
11550 __I uint32_t VAL;
11551
11552 } WWDT_T;
11553
11559 #define WWDT_RLD_WWDTRLD_Pos (0)
11560 #define WWDT_RLD_WWDTRLD_Msk (0xfffffffful << WWDT_RLD_RLD_Pos)
11562 #define WWDT_CR_WWDTEN_Pos (0)
11563 #define WWDT_CR_WWDTEN_Msk (0x1ul << WWDT_CR_WWDTEN_Pos)
11565 #define WWDT_CR_PERIODSEL_Pos (8)
11566 #define WWDT_CR_PERIODSEL_Msk (0xful << WWDT_CR_PERIODSEL_Pos)
11568 #define WWDT_CR_WINCMP_Pos (16)
11569 #define WWDT_CR_WINCMP_Msk (0x3ful << WWDT_CR_WINCMP_Pos)
11571 #define WWDT_CR_DBGEN_Pos (31)
11572 #define WWDT_CR_DBGEN_Msk (0x1ul << WWDT_CR_DBGEN_Pos)
11574 #define WWDT_IER_WWDTIE_Pos (0)
11575 #define WWDT_IER_WWDTIE_Msk (0x1ul << WWDT_IER_WWDTIE_Pos)
11577 #define WWDT_STS_IF_Pos (0)
11578 #define WWDT_STS_IF_Msk (0x1ul << WWDT_STS_IF_Pos)
11580 #define WWDT_STS_RF_Pos (1)
11581 #define WWDT_STS_RF_Msk (0x1ul << WWDT_STS_RF_Pos)
11583 #define WWDT_VAL_WWDTVAL_Pos (0)
11584 #define WWDT_VAL_WWDTVAL_Msk (0x3ful << WWDT_VAL_WWDTVAL_Pos) /* WWDT_CONST */
11587 /* end of WWDT register group */
11588
11589
11590
11591
11592 #if defined ( __CC_ARM )
11593 #pragma no_anon_unions
11594 #endif
11595
11601 #define FLASH_BASE ((uint32_t)0x00000000)
11602 #define SRAM_BASE ((uint32_t)0x20000000)
11603 #define APB1PERIPH_BASE ((uint32_t)0x40000000)
11604 #define APB2PERIPH_BASE ((uint32_t)0x40100000)
11605 #define AHBPERIPH_BASE ((uint32_t)0x50000000)
11606
11607
11609 #define WDT_BASE (APB1PERIPH_BASE + 0x04000)
11610 #define WWDT_BASE (APB1PERIPH_BASE + 0x04100)
11611 #define RTC_BASE (APB1PERIPH_BASE + 0x08000)
11612 #define TIMER0_BASE (APB1PERIPH_BASE + 0x10000)
11613 #define TIMER1_BASE (APB1PERIPH_BASE + 0x10100)
11614 #define I2C0_BASE (APB1PERIPH_BASE + 0x20000)
11615 #define SPI0_BASE (APB1PERIPH_BASE + 0x30000)
11616 #define PWM0_BASE (APB1PERIPH_BASE + 0x40000)
11617 #define UART0_BASE (APB1PERIPH_BASE + 0x50000)
11618 #define DAC_BASE (APB1PERIPH_BASE + 0xA0000)
11619 #define LCD_BASE (APB1PERIPH_BASE + 0xB0000)
11620 #define SPI2_BASE (APB1PERIPH_BASE + 0xD0000)
11621 #define ADC_BASE (APB1PERIPH_BASE + 0xE0000)
11622
11623 #define TIMER2_BASE (APB2PERIPH_BASE + 0x10000)
11624 #define TIMER3_BASE (APB2PERIPH_BASE + 0x10100)
11625 #define SHADOW_BASE (APB1PERIPH_BASE + 0x10200)
11626 #define I2C1_BASE (APB2PERIPH_BASE + 0x20000)
11627 #define SPI1_BASE (APB2PERIPH_BASE + 0x30000)
11628 #define PWM1_BASE (APB2PERIPH_BASE + 0x40000)
11629 #define UART1_BASE (APB2PERIPH_BASE + 0x50000)
11630 #define USBD_BASE (APB1PERIPH_BASE + 0x60000)
11631 #define SC0_BASE (APB2PERIPH_BASE + 0x90000)
11632 #define I2S_BASE (APB2PERIPH_BASE + 0xA0000)
11633 #define SC1_BASE (APB2PERIPH_BASE + 0xB0000)
11634 #define SC2_BASE (APB2PERIPH_BASE + 0xC0000)
11635
11636 #define SYS_BASE (AHBPERIPH_BASE + 0x00000)
11637 #define CLK_BASE (AHBPERIPH_BASE + 0x00200)
11638 #define INT_BASE (AHBPERIPH_BASE + 0x00300)
11639 #define GPIOA_BASE (AHBPERIPH_BASE + 0x04000)
11640 #define GPIOB_BASE (AHBPERIPH_BASE + 0x04040)
11641 #define GPIOC_BASE (AHBPERIPH_BASE + 0x04080)
11642 #define GPIOD_BASE (AHBPERIPH_BASE + 0x040C0)
11643 #define GPIOE_BASE (AHBPERIPH_BASE + 0x04100)
11644 #define GPIOF_BASE (AHBPERIPH_BASE + 0x04140)
11645 #define GPIODBNCE_BASE (AHBPERIPH_BASE + 0x04180)
11646 #define GPIO_PIN_DATA_BASE (AHBPERIPH_BASE + 0x04200)
11647 #define VDMA_BASE (AHBPERIPH_BASE + 0x08000)
11648 #define PDMA1_BASE (AHBPERIPH_BASE + 0x08100)
11649 #define PDMA2_BASE (AHBPERIPH_BASE + 0x08200)
11650 #define PDMA3_BASE (AHBPERIPH_BASE + 0x08300)
11651 #define PDMA4_BASE (AHBPERIPH_BASE + 0x08400)
11652 #define PDMA5_BASE (AHBPERIPH_BASE + 0x08500)
11653 #define PDMA6_BASE (AHBPERIPH_BASE + 0x08600)
11654 #define PDMACRC_BASE (AHBPERIPH_BASE + 0x08E00)
11655 #define PDMAGCR_BASE (AHBPERIPH_BASE + 0x08F00)
11656 #define FMC_BASE (AHBPERIPH_BASE + 0x0C000)
11657 #define EBI_BASE (AHBPERIPH_BASE + 0x10000)
11658
11659 /* end of group NANO100_PERIPHERAL_MEM_MAP */
11660
11661
11666 #define WDT ((WDT_T *) WDT_BASE)
11667 #define WWDT ((WWDT_T *) WWDT_BASE)
11668 #define RTC ((RTC_T *) RTC_BASE)
11669 #define TIMER0 ((TIMER_T *) TIMER0_BASE)
11670 #define TIMER1 ((TIMER_T *) TIMER1_BASE)
11671 #define TIMER2 ((TIMER_T *) TIMER2_BASE)
11672 #define TIMER3 ((TIMER_T *) TIMER3_BASE)
11673 #define SHADOW ((SHADOW_T *) SHADOW_BASE)
11674 #define I2C0 ((I2C_T *) I2C0_BASE)
11675 #define I2C1 ((I2C_T *) I2C1_BASE)
11676 #define SPI0 ((SPI_T *) SPI0_BASE)
11677 #define SPI1 ((SPI_T *) SPI1_BASE)
11678 #define SPI2 ((SPI_T *) SPI2_BASE)
11679 #define PWM0 ((PWM_T *) PWM0_BASE)
11680 #define PWM1 ((PWM_T *) PWM1_BASE)
11681 #define UART0 ((UART_T *) UART0_BASE)
11682 #define UART1 ((UART_T *) UART1_BASE)
11683 #define LCD ((LCD_T *) LCD_BASE)
11684 #define ADC ((ADC_T *) ADC_BASE)
11685 #define SC0 ((SC_T *) SC0_BASE)
11686 #define SC1 ((SC_T *) SC1_BASE)
11687 #define SC2 ((SC_T *) SC2_BASE)
11688 #define USBD ((USBD_T *) USBD_BASE)
11689 #define I2S ((I2S_T *) I2S_BASE)
11690 #define DAC ((DAC_T *) DAC_BASE)
11691
11692 #define SYS ((SYS_T *) SYS_BASE)
11693 #define CLK ((CLK_T *) CLK_BASE)
11694 #define INTR ((INTR_T *) INT_BASE)
11695 #define PA ((GPIO_T *) GPIOA_BASE)
11696 #define PB ((GPIO_T *) GPIOB_BASE)
11697 #define PC ((GPIO_T *) GPIOC_BASE)
11698 #define PD ((GPIO_T *) GPIOD_BASE)
11699 #define PE ((GPIO_T *) GPIOE_BASE)
11700 #define PF ((GPIO_T *) GPIOF_BASE)
11701 #define GPIO ((GP_DB_T *) GPIODBNCE_BASE)
11702 #define VDMA ((VDMA_T *) VDMA_BASE)
11703 #define PDMA1 ((PDMA_T *) PDMA1_BASE)
11704 #define PDMA2 ((PDMA_T *) PDMA2_BASE)
11705 #define PDMA3 ((PDMA_T *) PDMA3_BASE)
11706 #define PDMA4 ((PDMA_T *) PDMA4_BASE)
11707 #define PDMA5 ((PDMA_T *) PDMA5_BASE)
11708 #define PDMA6 ((PDMA_T *) PDMA6_BASE)
11709 #define PDMACRC ((DMA_CRC_T *) PDMACRC_BASE)
11710 #define PDMAGCR ((DMA_GCR_T *) PDMAGCR_BASE)
11711 #define FMC ((FMC_T *) FMC_BASE)
11712 #define EBI ((EBI_T *) EBI_BASE)
11713
11714 /* end of group NANO100_PERIPHERAL_DECLARATION */
11715 /* end of group NANO100_Peripherals */
11717
11723 typedef volatile unsigned char vu8;
11724 typedef volatile unsigned short vu16;
11725 typedef volatile unsigned long vu32;
11726
11732 #define M8(addr) (*((vu8 *) (addr)))
11733
11740 #define M16(addr) (*((vu16 *) (addr)))
11741
11748 #define M32(addr) (*((vu32 *) (addr)))
11749
11757 #define outpw(port,value) *((volatile unsigned int *)(port)) = value
11758
11765 #define inpw(port) (*((volatile unsigned int *)(port)))
11766
11774 #define outps(port,value) *((volatile unsigned short *)(port)) = value
11775
11782 #define inps(port) (*((volatile unsigned short *)(port)))
11783
11790 #define outpb(port,value) *((volatile unsigned char *)(port)) = value
11791
11797 #define inpb(port) (*((volatile unsigned char *)(port)))
11798
11806 #define outp32(port,value) *((volatile unsigned int *)(port)) = value
11807
11814 #define inp32(port) (*((volatile unsigned int *)(port)))
11815
11823 #define outp16(port,value) *((volatile unsigned short *)(port)) = value
11824
11831 #define inp16(port) (*((volatile unsigned short *)(port)))
11832
11839 #define outp8(port,value) *((volatile unsigned char *)(port)) = value
11840
11846 #define inp8(port) (*((volatile unsigned char *)(port)))
11847 /* end of group NANO100_IO_ROUTINE */
11849
11850 /******************************************************************************/
11851 /* Legacy Constants */
11852 /******************************************************************************/
11858 #ifndef NULL
11859 #define NULL (0)
11860 #endif
11861
11862 #define TRUE (1)
11863 #define FALSE (0)
11864
11865 #define ENABLE (1)
11866 #define DISABLE (0)
11867
11868 /* Define one bit mask */
11869 #define BIT0 (0x00000001)
11870 #define BIT1 (0x00000002)
11871 #define BIT2 (0x00000004)
11872 #define BIT3 (0x00000008)
11873 #define BIT4 (0x00000010)
11874 #define BIT5 (0x00000020)
11875 #define BIT6 (0x00000040)
11876 #define BIT7 (0x00000080)
11877 #define BIT8 (0x00000100)
11878 #define BIT9 (0x00000200)
11879 #define BIT10 (0x00000400)
11880 #define BIT11 (0x00000800)
11881 #define BIT12 (0x00001000)
11882 #define BIT13 (0x00002000)
11883 #define BIT14 (0x00004000)
11884 #define BIT15 (0x00008000)
11885 #define BIT16 (0x00010000)
11886 #define BIT17 (0x00020000)
11887 #define BIT18 (0x00040000)
11888 #define BIT19 (0x00080000)
11889 #define BIT20 (0x00100000)
11890 #define BIT21 (0x00200000)
11891 #define BIT22 (0x00400000)
11892 #define BIT23 (0x00800000)
11893 #define BIT24 (0x01000000)
11894 #define BIT25 (0x02000000)
11895 #define BIT26 (0x04000000)
11896 #define BIT27 (0x08000000)
11897 #define BIT28 (0x10000000)
11898 #define BIT29 (0x20000000)
11899 #define BIT30 (0x40000000)
11900 #define BIT31 (0x80000000)
11901
11902 /* Byte Mask Definitions */
11903 #define BYTE0_Msk (0x000000FF)
11904 #define BYTE1_Msk (0x0000FF00)
11905 #define BYTE2_Msk (0x00FF0000)
11906 #define BYTE3_Msk (0xFF000000)
11907
11908 #define GET_BYTE0(u32Param) ((u32Param & BYTE0_Msk) )
11909 #define GET_BYTE1(u32Param) ((u32Param & BYTE1_Msk) >> 8)
11910 #define GET_BYTE2(u32Param) ((u32Param & BYTE2_Msk) >> 16)
11911 #define GET_BYTE3(u32Param) ((u32Param & BYTE3_Msk) >> 24)
11913 /* end of group NANO100_legacy_Constants */
11914 /* end of group NANO100_Definitions */
11916
11917 #ifdef __cplusplus
11918 }
11919 #endif
11920
11921
11922 /******************************************************************************/
11923 /* Peripheral header files */
11924 /******************************************************************************/
11925 #include "sys.h"
11926 #include "clk.h"
11927 #include "adc.h"
11928 #include "dac.h"
11929 #include "fmc.h"
11930 #include "ebi.h"
11931 #include "gpio.h"
11932 #include "i2c.h"
11933 #include "crc.h"
11934 #include "pdma.h"
11935 #include "pwm.h"
11936 #include "rtc.h"
11937 #include "sc.h"
11938 #include "scuart.h"
11939 #include "spi.h"
11940 #include "timer.h"
11941 #include "uart.h"
11942 #include "usbd.h"
11943 #include "wdt.h"
11944 #include "wwdt.h"
11945 #include "i2s.h"
11946 #include "lcd.h"
11947
11948 #endif // __NANO100SERIES_H__
11949
11950 /*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
11951
WDT_T::IER
__IO uint32_t IER
Definition: Nano100Series.h:11388
PDMA_T::DAR
__IO uint32_t DAR
Definition: Nano100Series.h:5987
SYS_T::IRCTRIMCTL
__IO uint32_t IRCTRIMCTL
Definition: Nano100Series.h:2879
SC2_IRQn
Definition: Nano100Series.h:110
ADC_T::SMPLCNT1
__IO uint32_t SMPLCNT1
Definition: Nano100Series.h:570
RTC_T::TLR
__IO uint32_t TLR
Definition: Nano100Series.h:7854
RTC_T
Definition: Nano100Series.h:7772
DMA_CRC_T
Definition: Nano100Series.h:5561
rtc.h
Nano100 series RTC driver header file.
I2C0_IRQn
Definition: Nano100Series.h:108
UART_T::ALT_CTL
__IO uint32_t ALT_CTL
Definition: Nano100Series.h:10562
VDMA_T::DAR
__IO uint32_t DAR
Definition: Nano100Series.h:6172
uart.h
Nano100 Series uart control header file.
RTC_T::RIER
__IO uint32_t RIER
Definition: Nano100Series.h:7966
GPIO_T
Definition: Nano100Series.h:3413
PWM_T::CRL3
__I uint32_t CRL3
Definition: Nano100Series.h:7287
PDMA_T::CSR
__IO uint32_t CSR
Definition: Nano100Series.h:5961
UART_T::FUN_SEL
__IO uint32_t FUN_SEL
Definition: Nano100Series.h:10577
SVCall_IRQn
Definition: Nano100Series.h:85
pwm.h
NANO100 series PWM driver header file.
LCD_T::CTL
__IO uint32_t CTL
Definition: Nano100Series.h:5103
I2S_T::CTRL
__IO uint32_t CTRL
Definition: Nano100Series.h:4624
SC_T::ETUCR
__IO uint32_t ETUCR
Definition: Nano100Series.h:8526
CLK_T::CLKSEL2
__IO uint32_t CLKSEL2
Definition: Nano100Series.h:1069
WWDT_T::STS
__IO uint32_t STS
Definition: Nano100Series.h:11538
SC_T
Definition: Nano100Series.h:8273
PWM_T::DUTY1
__IO uint32_t DUTY1
Definition: Nano100Series.h:6860
DAC_T::DATA1
__IO uint32_t DATA1
Definition: Nano100Series.h:1582
GPDEF_IRQn
Definition: Nano100Series.h:95
INTR_T::MCU_IRQ
__IO uint32_t MCU_IRQ
Definition: Nano100Series.h:5028
ADC_IRQn
Definition: Nano100Series.h:118
PDWU_IRQn
Definition: Nano100Series.h:117
FMC_T::ISPCMD
__IO uint32_t ISPCMD
Definition: Nano100Series.h:1874
vu8
volatile unsigned char vu8
Define 8-bit unsigned volatile data type.
Definition: Nano100Series.h:11723
RTC_T::INIR
__IO uint32_t INIR
Definition: Nano100Series.h:7792
VDMA_T
Definition: Nano100Series.h:6115
RTC_T::CAR
__IO uint32_t CAR
Definition: Nano100Series.h:7934
wwdt.h
Nano100 series WWDT driver header file.
ADC_T::SMPLCNT0
__IO uint32_t SMPLCNT0
Definition: Nano100Series.h:550
SPI_T::SSR
__IO uint32_t SSR
Definition: Nano100Series.h:9417
FMC_T::ISPDAT
__IO uint32_t ISPDAT
Definition: Nano100Series.h:1858
RTC_T::RIIR
__IO uint32_t RIIR
Definition: Nano100Series.h:7994
GPIO_T::DMASK
__IO uint32_t DMASK
Definition: Nano100Series.h:3586
LCD_T::MEM_5
__IO uint32_t MEM_5
Definition: Nano100Series.h:5255
FMC_T::DFBADR
__I uint32_t DFBADR
Definition: Nano100Series.h:1902
PWM_T::CRL1
__I uint32_t CRL1
Definition: Nano100Series.h:7231
SC_T::TMR1
__IO uint32_t TMR1
Definition: Nano100Series.h:8813
SC_T::ALTCTL
__IO uint32_t ALTCTL
Definition: Nano100Series.h:8478
LCD_T::MEM_3
__IO uint32_t MEM_3
Definition: Nano100Series.h:5219
CLK_T::CLKDIV1
__IO uint32_t CLKDIV1
Definition: Nano100Series.h:1105
SYS_T::PD_H_MFP
__IO uint32_t PD_H_MFP
Definition: Nano100Series.h:2600
gpio.h
Nano100 series GPIO driver header file.
SYS_T::IRCTRIMIEN
__IO uint32_t IRCTRIMIEN
Definition: Nano100Series.h:2899
GPIO_T::DBEN
__IO uint32_t DBEN
Definition: Nano100Series.h:3618
PWM_T::INTEN
__IO uint32_t INTEN
Definition: Nano100Series.h:6713
CLK_T::APBCLK
__IO uint32_t APBCLK
Definition: Nano100Series.h:908
I2C_T
Definition: Nano100Series.h:4214
UART_T::FSR
__IO uint32_t FSR
Definition: Nano100Series.h:10421
PDMA_T::ISR
__IO uint32_t ISR
Definition: Nano100Series.h:6094
TIMER_T::DR
__I uint32_t DR
Definition: Nano100Series.h:9976
INTR_T
Definition: Nano100Series.h:4982
IRQn_Type
enum IRQn IRQn_Type
UART_T::TRSR
__IO uint32_t TRSR
Definition: Nano100Series.h:10370
PWM_T::CAPINTSTS
__IO uint32_t CAPINTSTS
Definition: Nano100Series.h:7189
USBD_EP_T
USBD endpoints register.
Definition: Nano100Series.h:10839
I2C_T::WKUPCON
__IO uint32_t WKUPCON
Definition: Nano100Series.h:4434
DMA_CRC_T::DMASAR
__IO uint32_t DMASAR
Definition: Nano100Series.h:5631
PWM_T::CRL2
__I uint32_t CRL2
Definition: Nano100Series.h:7259
UART_T::IER
__IO uint32_t IER
Definition: Nano100Series.h:10270
SC_T::TRSR
__IO uint32_t TRSR
Definition: Nano100Series.h:8709
DMA_CRC_T::DMAIER
__IO uint32_t DMAIER
Definition: Nano100Series.h:5690
PWM_T::CFL2
__I uint32_t CFL2
Definition: Nano100Series.h:7273
DMA_GCR_T::DSSR0
__IO uint32_t DSSR0
Definition: Nano100Series.h:5843
VDMA_T::DASOCR
__IO uint32_t DASOCR
Definition: Nano100Series.h:6289
sys.h
Nano100 Series system control header file.
I2C_T::WKUPSTS
__IO uint32_t WKUPSTS
Definition: Nano100Series.h:4448
ADC_T::CALWORD
__IO uint32_t CALWORD
Definition: Nano100Series.h:513
PWM_T::DUTY3
__IO uint32_t DUTY3
Definition: Nano100Series.h:6960
DMA_CRC_T::SEED
__IO uint32_t SEED
Definition: Nano100Series.h:5742
VDMA_T::SASOCR
__IO uint32_t SASOCR
Definition: Nano100Series.h:6277
DMA_GCR_T
Definition: Nano100Series.h:5759
I2S_T::STATUS
__IO uint32_t STATUS
Definition: Nano100Series.h:4786
CLK_T
Definition: Nano100Series.h:714
SPI_T::STATUS
__IO uint32_t STATUS
Definition: Nano100Series.h:9346
SPI_T::DMA
__IO uint32_t DMA
Definition: Nano100Series.h:9526
FMC_T::ISPADR
__IO uint32_t ISPADR
Definition: Nano100Series.h:1845
USBD_T::PDMA
__IO uint32_t PDMA
Definition: Nano100Series.h:11153
PWM_T::OE
__IO uint32_t OE
Definition: Nano100Series.h:6777
VDMA_T::CDAR
__I uint32_t CDAR
Definition: Nano100Series.h:6211
DMA_CRC_T::WDATA
__IO uint32_t WDATA
Definition: Nano100Series.h:5730
UART_T::RBR
__I uint32_t RBR
Definition: Nano100Series.h:10115
USBD_EP_T::CFG
__IO uint32_t CFG
Definition: Nano100Series.h:10910
PDMA_IRQn
Definition: Nano100Series.h:115
VDMA_T::BCR
__IO uint32_t BCR
Definition: Nano100Series.h:6185
PWM_T::PRES
__IO uint32_t PRES
Definition: Nano100Series.h:6607
GPIO_T::OFFD
__IO uint32_t OFFD
Definition: Nano100Series.h:3552
RTC_T::FCR
__IO uint32_t FCR
Definition: Nano100Series.h:7838
PWM_T::DATA3
__I uint32_t DATA3
Definition: Nano100Series.h:6979
crc.h
Nano100 series CRC driver header file.
USBD_T::RESERVE0
uint32_t RESERVE0
Definition: Nano100Series.h:11128
I2C_T::STATUS
__I uint32_t STATUS
Definition: Nano100Series.h:4291
UART_T::ISR
__IO uint32_t ISR
Definition: Nano100Series.h:10318
SYS_T::RST_SRC
__IO uint32_t RST_SRC
Definition: Nano100Series.h:2042
pdma.h
Nano100 series PDMA driver header file.
PDMA_T
Definition: Nano100Series.h:5907
SC_T::EGTR
__IO uint32_t EGTR
Definition: Nano100Series.h:8491
DMA_CRC_T::DMACSAR
__I uint32_t DMACSAR
Definition: Nano100Series.h:5659
GPABC_IRQn
Definition: Nano100Series.h:94
DAC_T
Definition: Nano100Series.h:1477
sc.h
Nano100 series Smartcard (SC) driver header file.
SYS_T::PDID
__I uint32_t PDID
Definition: Nano100Series.h:2008
timer.h
Nano100 series TIMER driver header file.
UART_T::TMCTL
__IO uint32_t TMCTL
Definition: Nano100Series.h:10471
adc.h
NANO100 series ADC driver header file.
DMA_GCR_T::GCRCSR
__IO uint32_t GCRCSR
Definition: Nano100Series.h:5795
LCD_T::MEM_1
__IO uint32_t MEM_1
Definition: Nano100Series.h:5183
TIMER_T::IER
__IO uint32_t IER
Definition: Nano100Series.h:9933
USBD_T::BUSSTS
__I uint32_t BUSSTS
Definition: Nano100Series.h:10971
LCD_T::FCSTS
__IO uint32_t FCSTS
Definition: Nano100Series.h:5367
SPI_T
Definition: Nano100Series.h:9190
PWM_T::CFL1
__I uint32_t CFL1
Definition: Nano100Series.h:7245
I2S_T::TXFIFO
__O uint32_t TXFIFO
Definition: Nano100Series.h:4801
PWM_T::DUTY2
__IO uint32_t DUTY2
Definition: Nano100Series.h:6911
DAC_IRQn
Definition: Nano100Series.h:119
LCD_T::MEM_2
__IO uint32_t MEM_2
Definition: Nano100Series.h:5201
DMA_CRC_T::CHECKSUM
__I uint32_t CHECKSUM
Definition: Nano100Series.h:5754
SPI0_IRQn
Definition: Nano100Series.h:104
wdt.h
Nano100 series WDT driver header file.
SYS_T::BODSTS
__IO uint32_t BODSTS
Definition: Nano100Series.h:2806
WWDT_T::IER
__IO uint32_t IER
Definition: Nano100Series.h:11522
WDT_IRQn
Definition: Nano100Series.h:91
PWM_T::CFL3
__I uint32_t CFL3
Definition: Nano100Series.h:7301
GPIO_T::ISRC
__IO uint32_t ISRC
Definition: Nano100Series.h:3955
TMR2_IRQn
Definition: Nano100Series.h:100
spi.h
NANO100 series SPI driver header file.
ADC_T::CALCTL
__IO uint32_t CALCTL
Definition: Nano100Series.h:499
PDMA_T::IER
__IO uint32_t IER
Definition: Nano100Series.h:6061
UART_T::CTL
__IO uint32_t CTL
Definition: Nano100Series.h:10187
SPI_T::TX0
__O uint32_t TX0
Definition: Nano100Series.h:9463
VDMA_T::CBCR
__I uint32_t CBCR
Definition: Nano100Series.h:6223
TIMER_T::ISR
__IO uint32_t ISR
Definition: Nano100Series.h:9964
SYS_T
Definition: Nano100Series.h:1993
INTR_T::NMI_SEL
__IO uint32_t NMI_SEL
Definition: Nano100Series.h:5009
PWM_T::PDMACH0
__I uint32_t PDMACH0
Definition: Nano100Series.h:7323
EBI_T
Definition: Nano100Series.h:1678
I2S_T::INTEN
__IO uint32_t INTEN
Definition: Nano100Series.h:4685
DMA_CRC_T::DMABCR
__IO uint32_t DMABCR
Definition: Nano100Series.h:5645
LCD_T::MEM_0
__IO uint32_t MEM_0
Definition: Nano100Series.h:5165
DMA_GCR_T::GCRISR
__I uint32_t GCRISR
Definition: Nano100Series.h:5902
LCD_T::MEM_4
__IO uint32_t MEM_4
Definition: Nano100Series.h:5237
vu32
volatile unsigned long vu32
Define 32-bit unsigned volatile data type.
Definition: Nano100Series.h:11725
SysTick_IRQn
Definition: Nano100Series.h:87
SC_T::ISR
__IO uint32_t ISR
Definition: Nano100Series.h:8634
EINT1_IRQn
Definition: Nano100Series.h:93
BOD_IRQn
Definition: Nano100Series.h:90
WDT_T::CTL
__IO uint32_t CTL
Definition: Nano100Series.h:11375
PendSV_IRQn
Definition: Nano100Series.h:86
I2C1_IRQn
Definition: Nano100Series.h:109
DAC_T::STS1
__IO uint32_t STS1
Definition: Nano100Series.h:1603
RTC_T::CLR
__IO uint32_t CLR
Definition: Nano100Series.h:7870
RTC_T::TAR
__IO uint32_t TAR
Definition: Nano100Series.h:7918
scuart.h
SPI2_IRQn
Definition: Nano100Series.h:106
CLK_T::CLKSTATUS
__I uint32_t CLKSTATUS
Definition: Nano100Series.h:937
I2C_T::INTSTS
__IO uint32_t INTSTS
Definition: Nano100Series.h:4269
WDT_T
Definition: Nano100Series.h:11331
ADC_T::CR
__IO uint32_t CR
Definition: Nano100Series.h:267
PWM_T::CFL0
__I uint32_t CFL0
Definition: Nano100Series.h:7217
LCD_T::DISPCTL
__IO uint32_t DISPCTL
Definition: Nano100Series.h:5147
WWDT_T
Definition: Nano100Series.h:11468
FMC_T::ISPCON
__IO uint32_t ISPCON
Definition: Nano100Series.h:1832
GPIO_T::IMD
__IO uint32_t IMD
Definition: Nano100Series.h:3639
PDMA_T::CBCR
__I uint32_t CBCR
Definition: Nano100Series.h:6039
RTC_T::DWR
__IO uint32_t DWR
Definition: Nano100Series.h:7902
LCD_T::MEM_8
__IO uint32_t MEM_8
Definition: Nano100Series.h:5309
PWM_T::CRL0
__I uint32_t CRL0
Definition: Nano100Series.h:7203
RTC_T::SPRCTL
__IO uint32_t SPRCTL
Definition: Nano100Series.h:8049
ADC_T::PWRCTL
__IO uint32_t PWRCTL
Definition: Nano100Series.h:475
vu16
volatile unsigned short vu16
Define 16-bit unsigned volatile data type.
Definition: Nano100Series.h:11724
fmc.h
Nano100B Series Flash Memory Controller Driver Header File.
DAC_T::COMCTL
__IO uint32_t COMCTL
Definition: Nano100Series.h:1626
I2C_T::SAMASK1
__IO uint32_t SAMASK1
Definition: Nano100Series.h:4419
SPI_T::CTL
__IO uint32_t CTL
Definition: Nano100Series.h:9291
DMA_CRC_T::CTL
__IO uint32_t CTL
Definition: Nano100Series.h:5618
TMR3_IRQn
Definition: Nano100Series.h:101
DMA_CRC_T::DMACBCR
__I uint32_t DMACBCR
Definition: Nano100Series.h:5674
SYS_T::PE_L_MFP
__IO uint32_t PE_L_MFP
Definition: Nano100Series.h:2635
DMA_GCR_T::DSSR1
__IO uint32_t DSSR1
Definition: Nano100Series.h:5868
PDMA_T::CDAR
__I uint32_t CDAR
Definition: Nano100Series.h:6026
UART_T::MCSR
__IO uint32_t MCSR
Definition: Nano100Series.h:10448
USBD_T::CTL
__IO uint32_t CTL
Definition: Nano100Series.h:10950
SPI_T::RX0
__I uint32_t RX0
Definition: Nano100Series.h:9431
FMC_T::ISPTRG
__IO uint32_t ISPTRG
Definition: Nano100Series.h:1888
USBD_T::INTEN
__IO uint32_t INTEN
Definition: Nano100Series.h:10993
SYS_T::PE_H_MFP
__IO uint32_t PE_H_MFP
Definition: Nano100Series.h:2669
EINT0_IRQn
Definition: Nano100Series.h:92
I2C_T::SADDR0
__IO uint32_t SADDR0
Definition: Nano100Series.h:4364
clk.h
Nano100 series CLK driver header file.
GPIO_T::PMD
__IO uint32_t PMD
Definition: Nano100Series.h:3537
I2S_T
Definition: Nano100Series.h:4530
RTC_T::TSSR
__IO uint32_t TSSR
Definition: Nano100Series.h:7884
CLK_T::MCLKO
__IO uint32_t MCLKO
Definition: Nano100Series.h:1189
SC_T::TDRA
__I uint32_t TDRA
Definition: Nano100Series.h:8869
ADC_T::CMPR1
__IO uint32_t CMPR1
Definition: Nano100Series.h:394
TMR0_IRQn
Definition: Nano100Series.h:98
IRQn
IRQn
Definition: Nano100Series.h:79
i2s.h
Nano100 series I2S driver header file.
USBD_EP_T::MXPLD
__IO uint32_t MXPLD
Definition: Nano100Series.h:10873
VDMA_T::CSAR
__I uint32_t CSAR
Definition: Nano100Series.h:6199
DMA_CRC_T::DMAISR
__IO uint32_t DMAISR
Definition: Nano100Series.h:5713
WWDT_T::CR
__IO uint32_t CR
Definition: Nano100Series.h:11508
USBD_IRQn
Definition: Nano100Series.h:113
SYS_T::PC_L_MFP
__IO uint32_t PC_L_MFP
Definition: Nano100Series.h:2462
GPIO_T::DOUT
__IO uint32_t DOUT
Definition: Nano100Series.h:3567
UART_T::TLCTL
__IO uint32_t TLCTL
Definition: Nano100Series.h:10233
EBI_T::EBICON
__IO uint32_t EBICON
Definition: Nano100Series.h:1718
PWM_T::DATA0
__I uint32_t DATA0
Definition: Nano100Series.h:6828
RTC_T::LIR
__I uint32_t LIR
Definition: Nano100Series.h:7947
RTC_T::TTR
__IO uint32_t TTR
Definition: Nano100Series.h:8020
SYS_T::IPRST_CTL2
__IO uint32_t IPRST_CTL2
Definition: Nano100Series.h:2156
lcd.h
Nano100 series I2C driver header file.
HIRC_IRQn
Definition: Nano100Series.h:107
DAC_T::DATA0
__IO uint32_t DATA0
Definition: Nano100Series.h:1519
WWDT_T::RLD
__O uint32_t RLD
Definition: Nano100Series.h:11484
system_Nano100Series.h
Nano100 series system clock definition file.
I2C_T::DIV
__IO uint32_t DIV
Definition: Nano100Series.h:4304
SC_T::TMR0
__IO uint32_t TMR0
Definition: Nano100Series.h:8799
SYS_T::BODCTL
__IO uint32_t BODCTL
Definition: Nano100Series.h:2774
RTC_IRQn
Definition: Nano100Series.h:120
FMC_T::ISPSTA
__IO uint32_t ISPSTA
Definition: Nano100Series.h:1926
SC_T::TDRB
__I uint32_t TDRB
Definition: Nano100Series.h:8883
SYS_T::PF_L_MFP
__IO uint32_t PF_L_MFP
Definition: Nano100Series.h:2700
ADC_T
Definition: Nano100Series.h:164
HardFault_IRQn
Definition: Nano100Series.h:84
DAC_T::STS0
__IO uint32_t STS0
Definition: Nano100Series.h:1540
SC1_IRQn
Definition: Nano100Series.h:112
SC0_IRQn
Definition: Nano100Series.h:111
SC_T::RBR
__I uint32_t RBR
Definition: Nano100Series.h:8289
UART1_IRQn
Definition: Nano100Series.h:103
EBI_T::EXTIME
__IO uint32_t EXTIME
Definition: Nano100Series.h:1743
DAC_T::CTL0
__IO uint32_t CTL0
Definition: Nano100Series.h:1508
SYS_T::PB_L_MFP
__IO uint32_t PB_L_MFP
Definition: Nano100Series.h:2348
DAC_T::CTL1
__IO uint32_t CTL1
Definition: Nano100Series.h:1571
PWM1_IRQn
Definition: Nano100Series.h:97
I2S_IRQn
Definition: Nano100Series.h:116
SYS_T::PB_H_MFP
__IO uint32_t PB_H_MFP
Definition: Nano100Series.h:2407
SYS_T::IRCTRIMINT
__IO uint32_t IRCTRIMINT
Definition: Nano100Series.h:2926
USBD_EP_T::RESERVE
uint32_t RESERVE
Definition: Nano100Series.h:10911
dac.h
NANO100 series DAC driver header file.
ADC_T::SR
__IO uint32_t SR
Definition: Nano100Series.h:437
SC_T::TMR2
__IO uint32_t TMR2
Definition: Nano100Series.h:8827
SYS_T::PA_L_MFP
__IO uint32_t PA_L_MFP
Definition: Nano100Series.h:2231
I2S_T::RXFIFO
__I uint32_t RXFIFO
Definition: Nano100Series.h:4816
SPI_T::RX1
__I uint32_t RX1
Definition: Nano100Series.h:9445
VDMA_T::CSR
__IO uint32_t CSR
Definition: Nano100Series.h:6148
TIMER_T::TCAP
__I uint32_t TCAP
Definition: Nano100Series.h:9989
FMC_T
Definition: Nano100Series.h:1792
SYS_T::PD_L_MFP
__IO uint32_t PD_L_MFP
Definition: Nano100Series.h:2566
LCD_IRQn
Definition: Nano100Series.h:114
USBD_T
Definition: Nano100Series.h:10915
CLK_T::CLKSEL0
__IO uint32_t CLKSEL0
Definition: Nano100Series.h:959
PDMA_T::CSAR
__I uint32_t CSAR
Definition: Nano100Series.h:6014
LCD_T::MEM_9
__IO uint32_t MEM_9
Definition: Nano100Series.h:5327
PDMA_T::BCR
__IO uint32_t BCR
Definition: Nano100Series.h:6000
TIMER_T::CMPR
__IO uint32_t CMPR
Definition: Nano100Series.h:9915
PDMA_T::TCR
__IO uint32_t TCR
Definition: Nano100Series.h:6109
PWM_T::CAPCTL
__IO uint32_t CAPCTL
Definition: Nano100Series.h:7085
SC_T::RFTMR
__IO uint32_t RFTMR
Definition: Nano100Series.h:8506
VDMA_T::SAR
__IO uint32_t SAR
Definition: Nano100Series.h:6160
SPI1_IRQn
Definition: Nano100Series.h:105
SYS_T::PA_H_MFP
__IO uint32_t PA_H_MFP
Definition: Nano100Series.h:2292
PWM_T::PDMACH2
__I uint32_t PDMACH2
Definition: Nano100Series.h:7345
TIMER_T
Definition: Nano100Series.h:9745
I2S_T::CLKDIV
__IO uint32_t CLKDIV
Definition: Nano100Series.h:4643
PWM_T::DATA2
__I uint32_t DATA2
Definition: Nano100Series.h:6930
SYS_T::IPRST_CTL1
__IO uint32_t IPRST_CTL1
Definition: Nano100Series.h:2080
SYS_T::PC_H_MFP
__IO uint32_t PC_H_MFP
Definition: Nano100Series.h:2513
I2C_T::DATA
__IO uint32_t DATA
Definition: Nano100Series.h:4343
I2C_T::TOUT
__IO uint32_t TOUT
Definition: Nano100Series.h:4323
TIMER_T::PRECNT
__IO uint32_t PRECNT
Definition: Nano100Series.h:9898
VDMA_T::ISR
__IO uint32_t ISR
Definition: Nano100Series.h:6261
RTC_T::AER
__IO uint32_t AER
Definition: Nano100Series.h:7808
LCD_T::MEM_7
__IO uint32_t MEM_7
Definition: Nano100Series.h:5291
ebi.h
Nano100 Series Flash Memory Controller Driver Header File.
CLK_T::CLKSEL1
__IO uint32_t CLKSEL1
Definition: Nano100Series.h:1008
SYS_T::RegLockAddr
__IO uint32_t RegLockAddr
Definition: Nano100Series.h:2941
WWDT_T::VAL
__I uint32_t VAL
Definition: Nano100Series.h:11550
GPIO_T::IER
__IO uint32_t IER
Definition: Nano100Series.h:3937
LCD_T::FCR
__IO uint32_t FCR
Definition: Nano100Series.h:5350
PWM_T::DATA1
__I uint32_t DATA1
Definition: Nano100Series.h:6879
UART0_IRQn
Definition: Nano100Series.h:102
PWM_T::CTL
__IO uint32_t CTL
Definition: Nano100Series.h:6691
PWM_T::CLKSEL
__IO uint32_t CLKSEL
Definition: Nano100Series.h:6633
PDMA_T::SAR
__IO uint32_t SAR
Definition: Nano100Series.h:5974
SC_T::THR
__O uint32_t THR
Definition: Nano100Series.h:8300
GPIO_T::PUEN
__IO uint32_t PUEN
Definition: Nano100Series.h:3971
GP_DB_T::DBNCECON
__IO uint32_t DBNCECON
Definition: Nano100Series.h:4013
SPI_T::VARCLK
__IO uint32_t VARCLK
Definition: Nano100Series.h:9496
PWM_T::DUTY0
__IO uint32_t DUTY0
Definition: Nano100Series.h:6809
UART_T
Definition: Nano100Series.h:10098
UART_T::IRCR
__IO uint32_t IRCR
Definition: Nano100Series.h:10509
LCD_T::MEM_6
__IO uint32_t MEM_6
Definition: Nano100Series.h:5273
USBD_EP_T::BUFSEG
__IO uint32_t BUFSEG
Definition: Nano100Series.h:10853
ADC_T::PDMA
__I uint32_t PDMA
Definition: Nano100Series.h:452
SPI_T::CLKDIV
__IO uint32_t CLKDIV
Definition: Nano100Series.h:9364
CLK_T::PLLCTL
__IO uint32_t PLLCTL
Definition: Nano100Series.h:1129
USBD_T::EPSTS2
__I uint32_t EPSTS2
Definition: Nano100Series.h:11123
I2C_T::SAMASK0
__IO uint32_t SAMASK0
Definition: Nano100Series.h:4403
CLK_T::AHBCLK
__IO uint32_t AHBCLK
Definition: Nano100Series.h:817
CLK_T::WK_INTSTS
__IO uint32_t WK_INTSTS
Definition: Nano100Series.h:1203
GP_DB_T
Definition: Nano100Series.h:3976
SC_T::PINCSR
__IO uint32_t PINCSR
Definition: Nano100Series.h:8785
SPI_T::FFCTL
__IO uint32_t FFCTL
Definition: Nano100Series.h:9562
CLK_T::PWRCTL
__IO uint32_t PWRCTL
Definition: Nano100Series.h:789
USBD_T::EPSTS
__I uint32_t EPSTS
Definition: Nano100Series.h:11094
SC_T::CTL
__IO uint32_t CTL
Definition: Nano100Series.h:8388
LCD_T
Definition: Nano100Series.h:5056
CLK_T::CLKDIV0
__IO uint32_t CLKDIV0
Definition: Nano100Series.h:1091
UART_T::THR
__O uint32_t THR
Definition: Nano100Series.h:10128
TMR1_IRQn
Definition: Nano100Series.h:99
USBD_T::INTSTS
__IO uint32_t INTSTS
Definition: Nano100Series.h:11046
CLK_T::FRQDIV
__IO uint32_t FRQDIV
Definition: Nano100Series.h:1146
TIMER_T::CTL
__IO uint32_t CTL
Definition: Nano100Series.h:9885
I2C_T::SADDR1
__IO uint32_t SADDR1
Definition: Nano100Series.h:4385
PWM_T::CAPINTEN
__IO uint32_t CAPINTEN
Definition: Nano100Series.h:7127
SYS_T::Int_VREFCTL
__IO uint32_t Int_VREFCTL
Definition: Nano100Series.h:2838
SC_T::IER
__IO uint32_t IER
Definition: Nano100Series.h:8582
ADC_T::CMPR0
__IO uint32_t CMPR0
Definition: Nano100Series.h:363
NonMaskableInt_IRQn
Definition: Nano100Series.h:83
PWM_T::INTSTS
__IO uint32_t INTSTS
Definition: Nano100Series.h:6751
SPI_T::TX1
__O uint32_t TX1
Definition: Nano100Series.h:9479
ADC_T::CHEN
__IO uint32_t CHEN
Definition: Nano100Series.h:332
WDT_T::ISR
__IO uint32_t ISR
Definition: Nano100Series.h:11419
VDMA_T::IER
__IO uint32_t IER
Definition: Nano100Series.h:6239
SYS_T::TEMPCTL
__IO uint32_t TEMPCTL
Definition: Nano100Series.h:2171
PWM0_IRQn
Definition: Nano100Series.h:96
USBD_T::BUFSEG
__IO uint32_t BUFSEG
Definition: Nano100Series.h:11107
USBD_T::FADDR
__IO uint32_t FADDR
Definition: Nano100Series.h:11057
SYS_T::PORCTL
__IO uint32_t PORCTL
Definition: Nano100Series.h:2716
GPIO_T::PIN
__I uint32_t PIN
Definition: Nano100Series.h:3599
UART_T::BAUD
__IO uint32_t BAUD
Definition: Nano100Series.h:10487
usbd.h
NANO100 series USB driver header file.
I2C_T::CON
__IO uint32_t CON
Definition: Nano100Series.h:4253
i2c.h
Nano100 series I2C driver header file.
SC_T::UACTL
__IO uint32_t UACTL
Definition: Nano100Series.h:8857
PWM_T
Definition: Nano100Series.h:6583