Nano100BN Series BSP  V3.03.002
The Board Support Package for Nano100BN Series
Data Fields
ADC_T Struct Reference

#include <Nano100Series.h>

Data Fields

__I uint32_t RESULT [18]
 
__IO uint32_t CR
 
__IO uint32_t CHEN
 
__IO uint32_t CMPR0
 
__IO uint32_t CMPR1
 
__IO uint32_t SR
 
uint32_t RESERVE0 [1]
 
__I uint32_t PDMA
 
__IO uint32_t PWRCTL
 
__IO uint32_t CALCTL
 
__IO uint32_t CALWORD
 
__IO uint32_t SMPLCNT0
 
__IO uint32_t SMPLCNT1
 

Detailed Description

@addtogroup ADC Analog to Digital Converter(ADC)
Memory Mapped Structure for ADC Controller

Definition at line 164 of file Nano100Series.h.

Field Documentation

◆ CALCTL

__IO uint32_t ADC_T::CALCTL

CALCTL

Offset: 0x68 ADC Calibration Control Register

Bits Field Descriptions
[0] CALEN Calibration Function Enable
Enable this bit to turn on the calibration function block.
0 = Disable
1 = Enabled.
[1] CALSTART Calibration Functional Block Start
0 = Stops calibration functional block.
1 = Starts calibration functional block.
Note: This bit is set by SW and clear by HW; don't write 1 to this bit while CALEN = 0.
[2] CALDONE Calibrate Functional Block Complete
0 = Not yet.
1 = Selected functional block complete.
[3] CALSEL Select Calibration Functional Block
0 = Load calibration functional block.
1 = Calibration functional block.

Definition at line 499 of file Nano100Series.h.

◆ CALWORD

__IO uint32_t ADC_T::CALWORD

CALWORD

Offset: 0x6C A/D calibration load word register

Bits Field Descriptions
[6:0] CALWORD Calibration Word Register
Write to this register with the previous calibration word before load calibration action
Read this register after calibration done
Note: The calibration block contains two parts "CALIBRATION" and "LOAD CALIBRATION"; if the calibration block is config as "CALIBRATION"; then this register represent the result of calibration when calibration is completed; if config as "LOAD CALIBRATION" ; config this register before loading calibration action, after loading calibration complete, the loaded calibration word will apply to the ADC;while in loading calibration function the loaded value will not be equal to the original CALWORD until calibration is done.

Definition at line 513 of file Nano100Series.h.

◆ CHEN

__IO uint32_t ADC_T::CHEN

CHEN

Offset: 0x4C A/D Channel Enable Register

Bits Field Descriptions
[0] CHEN0 Analog Input Channel 0 Enable (Convert Input Voltage From PA.0 )
0 = Disabled.
1 = Enabled.
If more than one channel in single mode is enabled by software, the least channel is converted and other enabled channels will be ignored.
[1] CHEN1 Analog Input Channel 1 Enable(Convert Input Voltage From PA.1 )
0 = Disabled.
1 = Enabled.
[2] CHEN2 Analog Input Channel 2 Enable (Convert Input Voltage From PA.2 )
0 = Disabled.
1 = Enabled.
[3] CHEN3 Analog Input Channel 3 Enable(Convert Input Voltage From PA.3 )
0 = Disabled.
1 = Enabled.
[4] CHEN4 Analog Input Channel 4 Enable (Convert Input Voltage From PA.4 )
0 = Disabled.
1 = Enabled.
[5] CHEN5 Analog Input Channel 5 Enable (Convert Input Voltage From PA.5 )
0 = Disabled.
1 = Enabled.
[6] CHEN6 Analog Input Channel 6 Enable (Convert Input Voltage From PA.6 )
0 = Disabled.
1 = Enabled.
[7] CHEN7 Analog Input Channel 7 Enable (Convert Input Voltage From PA.7 )
0 = Disabled.
1 = Enabled.
[8] CHEN8 Analog Input Channel 8 Enable For DAC0 (Convert Input Voltage From PD.0 )
0 = Disabled.
1 = Enabled.
[9] CHEN9 Analog Input Channel 9 Enable For DAC1 (Convert Input Voltage From PD.1 )
0 = Disabled.
1 = Enabled.
[10] CHEN10 Analog Input Channel 10 Enable (Convert Input Voltage From PD.2 )
0 = Disabled.
1 = Enabled.
[11] CHEN11 Analog Input Channel 11 Enable(Convert Input Voltage From PD.3 )
0 = Disabled.
1 = Enabled.
[12] CHEN12 Analog Input Channel 12 Enable (Convert DAC0 Output Voltage)
0 = Disabled.
1 = Enabled.
[13] CHEN13 Analog Input Channel 13 Enable (Convert DAC1 Output Voltage)
0 = Disabled.
1 = Enabled.
[14] CHEN14 Analog Input Channel 14 Enable (Convert VTEMP)
0 = Disabled.
1 = Enabled.
[15] CHEN15 Analog Input Channel 15 Enable (Convert Int_VREF)
0 = Disabled.
1 = Enabled.
[16] CHEN16 Analog Input Channel 16 Enable (Convert AVDD)
0 = Disabled.
1 = Enabled.
[17] CHEN17 Analog Input Channel 17 Enable (Convert AVSS)
0 = Disabled.
1 = Enabled.

Definition at line 332 of file Nano100Series.h.

◆ CMPR0

__IO uint32_t ADC_T::CMPR0

CMPR0

Offset: 0x50 A/D Compare Register 0

Bits Field Descriptions
[0] CMPEN Compare Enable
0 = Compare Disabled.
1 = Compare Enabled.
Set this bit to 1 to enable compare CMPD[11:0] with specified channel conversion result when converted data is loaded into ADC_RESULTx register.
When this bit is set to 1, and CMPMATCNT is 0, the CMPF will be set once the match is hit
[1] CMPIE Compare Interrupt Enable
0 = Compare function interrupt Disabled.
1 = Compare function interrupt Enabled.
If the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT, CMPF bit will be asserted, in the meanwhile, if CMPIE is set to 1, a compare interrupt request is generated.
[2] CMPCOND Compare Condition
0 = Set the compare condition as that when a 12-bit A/D conversion result is less than the 12-bit CMPD (ADCMPRx[27:16]), the internal match counter will increase one.
1 = Set the compare condition as that when a 12-bit A/D conversion result is greater or equal to the 12-bit CMPD (ADCMPRx[27:16]), the internal match counter will increase by one.
Note: When the internal counter reaches the value to (CMPMATCNT +1), the CMPF bit will be set.
[7:3] CMPCH Compare Channel Selection
This field selects the channel whose conversion result is selected to be compared.
[11:8] CMPMATCNT Compare Match Count
When the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND[2], the internal match counter will increase 1.
When the internal counter reaches the value to (CMPMATCNT +1), the CMPF bit will be set.
[27:16] CMPD Comparison Data
The 12 bits data is used to compare with conversion result of specified channel.
Software can use it to monitor the external analog input pin voltage variation in scan mode without imposing a load on software.

Definition at line 363 of file Nano100Series.h.

◆ CMPR1

__IO uint32_t ADC_T::CMPR1

CMPR1

Offset: 0x54 A/D Compare Register 1

Bits Field Descriptions
[0] CMPEN Compare Enable
0 = Compare Disabled.
1 = Compare Enabled.
Set this bit to 1 to enable compare CMPD[11:0] with specified channel conversion result when converted data is loaded into ADC_RESULTx register.
When this bit is set to 1, and CMPMATCNT is 0, the CMPF will be set once the match is hit
[1] CMPIE Compare Interrupt Enable
0 = Compare function interrupt Disabled.
1 = Compare function interrupt Enabled.
If the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT, CMPF bit will be asserted, in the meanwhile, if CMPIE is set to 1, a compare interrupt request is generated.
[2] CMPCOND Compare Condition
0 = Set the compare condition as that when a 12-bit A/D conversion result is less than the 12-bit CMPD (ADCMPRx[27:16]), the internal match counter will increase one.
1 = Set the compare condition as that when a 12-bit A/D conversion result is greater or equal to the 12-bit CMPD (ADCMPRx[27:16]), the internal match counter will increase by one.
Note: When the internal counter reaches the value to (CMPMATCNT +1), the CMPF bit will be set.
[7:3] CMPCH Compare Channel Selection
This field selects the channel whose conversion result is selected to be compared.
[11:8] CMPMATCNT Compare Match Count
When the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND[2], the internal match counter will increase 1.
When the internal counter reaches the value to (CMPMATCNT +1), the CMPF bit will be set.
[27:16] CMPD Comparison Data
The 12 bits data is used to compare with conversion result of specified channel.
Software can use it to monitor the external analog input pin voltage variation in scan mode without imposing a load on software.

Definition at line 394 of file Nano100Series.h.

◆ CR

__IO uint32_t ADC_T::CR

CR

Offset: 0x48 A/D Control Register

Bits Field Descriptions
[0] ADEN A/D Converter Enable
0 = Disabled.
1 = Enabled.
Before starting A/D conversion, this bit should be set to 1.
Clear it to 0 to disable A/D converter analog circuit power consumption.
[1] ADIE A/D Interrupt Enable
0 = A/D interrupt function Disabled.
1 = A/D interrupt function Enabled.
A/D conversion end interrupt request is generated if ADIE bit is set to 1.
[3:2] ADMD A/D Converter Operation Mode
00 = Single conversion
01 = Reserved
10 = Single-cycle scan
11 = Continuous scan
[5:4] TRGS Hardware Trigger Source
This field must keep 00
Software should disable TRGE and ADST before change TRGS.
In hardware trigger mode, the ADST bit is set by the external trigger from STADC, However software has the highest priority to set or cleared ADST bit at any time.
[7:6] TRGCOND External Trigger Condition
These two bits decide external pin STADC trigger event is level or edge.
The signal must be kept at stable state at least 8 PCLKs for level trigger and 4 PCLKs at high and low state.
00 = Low level
01 = High level
10 = Falling edge
11 = Rising edge
[8] TRGE External Trigger Enable
Enable or disable triggering of A/D conversion by external STADC pin.
0 = Disabled.
1 = Enabled.
[9] PTEN PDMA Transfer Enable
0 = PDMA data transfer Disabled.
1 = PDMA data transfer in ADC_RESULT 0~17 Enabled.
When A/D conversion is completed, the converted data is loaded into ADC_RESULT 0~10, software can enable this bit to generate a PDMA data transfer request.
When PTEN=1, software must set ADIE=0 to disable interrupt.
PDMA can access ADC_RESULT 0-17 registers by block or single transfer mode.
[10] DIFF Differential Mode Selection
0 = ADC is operated in single-ended mode.
1 = ADC is operated in differential mode.
The A/D analog input ADC_CH0/ADC_CH1 consists of a differential pair.
So as ADC_CH2/ADC_CH3, ADC_CH4/ADC_CH5, ADC_CH6/ADC_CH7, ADC_CH8/ADC_CH9 and ADC_CH10/ADC_CH11.
The even channel defines as plus analog input voltage (Vplus) and the odd channel defines as minus analog input voltage (Vminus).
Differential input voltage (Vdiff) = Vplus - Vminus, where Vplus is the analog input; Vminus is the inverted analog input.
In differential input mode, only the even number of the two corresponding channels needs to be enabled in CHEN (ADCHER[11:0]).
The conversion result will be placed to the corresponding data register of the enabled channel.
Note: Calibration should calibrated each time when switching between single-ended and differential mode
[11] ADST A/D Conversion Start
0 = Conversion stopped and A/D converter enter idle state.
1 = Conversion starts.
ADST bit can be set to 1 from two sources: software write and external pin STADC.
ADST is cleared to 0 by hardware automatically at the end of single mode and single-cycle scan mode on specified channels.
In continuous scan mode, A/D conversion is continuously performed sequentially unless software writes 0 to this bit or chip reset.
Note: After ADC conversion done, SW needs to wait at least one ADC clock before to set this bit high again.
[13:12] TMSEL Select A/D Enable Time-Out Source
00 = TMR0
01 = TMR1
10 = TMR2
11 = TMR3
[15] TMTRGMOD Timer Event Trigger ADC Conversion
0 = This function Disabled.
1 = ADC Enabled by TIMER OUT event. Setting TMSEL to select timer event from timer0~3
[17:16] REFSEL Reference Voltage Source Selection
00 = Reserved
01 = Select Int_VREF as reference voltage
10 = Select VREF as reference voltage
11 = Reserved
[19:18] RESSEL Resolution Selection
00 = 6 bits
01 = 8 bits
10 = 10 bits
11 = 12 bits
[31:24] TMPDMACNT PDMA Count
When each timer event occur PDMA will transfer TMPDMACNT +1 ADC result in the amount of this register setting
Note: The total amount of PDMA transferring data should be set in PDMA byte count register.
When PDMA finish is set, ADC will not be enabled and start transfer even though the timer event occurred.

Definition at line 267 of file Nano100Series.h.

◆ PDMA

__I uint32_t ADC_T::PDMA

PDMA

Offset: 0x60 A/D PDMA current transfer data Register

Bits Field Descriptions
[11:0] AD_PDMA ADC PDMA Current Transfer Data Register
When PDMA transferring, read this register can monitor current PDMA transfer data.
This is a read only register.

Definition at line 452 of file Nano100Series.h.

◆ PWRCTL

__IO uint32_t ADC_T::PWRCTL

PWRCTL

Offset: 0x64 ADC Power Management Register

Bits Field Descriptions
[0] PWUPRDY ADC Power-Up Sequence Completed And Ready For Conversion
0 = ADC is not ready for conversion; may be in power down state or in the progress of power up.
1 = ADC is ready for conversion.
[1] PWDCALEN Power Up Calibration Function Enable
1 = Power up with calibration.
0 = Power up without calibration.
Note: This bit work together with CALFBKSEL set 1
[3:2] PWDMOD Power-Down Mode
00 = Power down
01 = Reserved
10 = Standby mode
11 = Reserved
Note: Different PWDMOD has different power down/up sequence, in order to avoid ADC powering up with wrong sequence; user must keep PWMOD consistent each time in powe down and power up

Definition at line 475 of file Nano100Series.h.

◆ RESERVE0

uint32_t ADC_T::RESERVE0[1]

Definition at line 438 of file Nano100Series.h.

◆ RESULT

__I uint32_t ADC_T::RESULT[18]

RESULT0, RESULT1.. RESULT17

Offset: 0x00 ~0x44 A/D Data Register 0~17

Bits Field Descriptions
[11:0] RSLT A/D Conversion Result
This field contains 12 bits conversion results.
[16] VALID Data Valid Flag
It is a mirror of VALID bit in ADC_RESULTx
[17] OVERRUN Over Run Flag
It is a mirror to OVERRUN bit in ADC_RESULTx

Definition at line 182 of file Nano100Series.h.

◆ SMPLCNT0

__IO uint32_t ADC_T::SMPLCNT0

SMPLCNT0

Offset: 0x70 ADC Channel Sampling Time Counter Register Group 0

Bits Field Descriptions
[3:0] CH0SAMPCNT Channel 0 Sampling Counter
0000 = 0 ADC clock
0001 = 1 ADC clock
0010 = 2 ADC clocks
0011 = 4 ADC clocks
0100 = 8 ADC clocks
0101 = 16 ADC clocks
0110 = 32 ADC clocks
0111 = 64 ADC clocks
1000 = 128 ADC clocks
1001 = 256 ADC clocks
1010 = 512 ADC clocks
Others = 1024 ADC clocks
[7:4] CH1SAMPCNT Channel 1 Sampling Counter
The same as Channel 0 sampling counter table.
[11:8] CH2SAMPCNT Channel 2 Sampling Counter
The same as Channel 0 sampling counter table.
[15:12] CH3SAMPCNT Channel 3 Sampling Counter
The same as Channel 0 sampling counter table.
[19:16] CH4SAMPCNT Channel 4 Sampling Counter
The same as Channel 0 sampling counter table.
[23:20] CH5SAMPCNT Channel 5 Sampling Counter
The same as Channel 0 sampling counter table.
[27:24] CH6SAMPCNT Channel 6 Sampling Counter
The same as Channel 0 sampling counter table.
[31:28] CH7SAMPCNT Channel 7 Sampling Counter
The same as Channel 0 sampling counter table.

Definition at line 550 of file Nano100Series.h.

◆ SMPLCNT1

__IO uint32_t ADC_T::SMPLCNT1

SMPLCNT1

Offset: 0x74 ADC Channel Sampling Time Counter Register Group 1

Bits Field Descriptions
[3:0] CH8SAMPCNT Channel 8 Sampling Counter
The same as Channel 0 sampling counter table.
[7:4] CH9SAMPCNT Channel 9 Sampling Counter
The same as Channel 0 sampling counter table.
[11:8] CH10SAMPCNT Channel 10 Sampling Counter
The same as Channel 0 sampling counter table.
[15:12] CH11SAMPCNT Channel 11 Sampling Counter
The same as Channel 0 sampling counter table.
[19:16] INTCHSAMPCNT Internal Channel (VTEMP, AVDD, AVSS, Int_VREF, DAC0, DAC1) Sampling Counter
The same as Channel 0 sampling counter table.

Definition at line 570 of file Nano100Series.h.

◆ SR

__IO uint32_t ADC_T::SR

SR

Offset: 0x58 A/D Status Register

Bits Field Descriptions
[0] ADF A/D Conversion End Flag
A status flag that indicates the end of A/D conversion.
ADF is set to 1 at these two conditions:
When A/D conversion ends in single mode
When A/D conversion ends on all specified channels in scan mode.
This flag can be cleared by writing 1 to it.
[1] CMPF0 Compare Flag
When the selected channel A/D conversion result meets setting condition in ADCMPR0 then this bit is set to 1.
And it is cleared by writing 1 to self.
0 = Conversion result in ADC_RESULTx does not meet ADCMPR0setting.
1 = Conversion result in ADC_RESULTx meets ADCMPR0setting.
This flag can be cleared by writing 1 to it.
Note: When this flag is set, the matching counter will be reset to 0,and continue to count when user write 1 to clear CMPF0
[2] CMPF1 Compare Flag
When the selected channel A/D conversion result meets setting condition in ADCMPR1 then this bit is set to 1.
And it is cleared by writing 1 to self.
0 = Conversion result in ADC_RESULTx does not meet ADCMPR1 setting.
1 = Conversion result in ADC_RESULTx meets ADCMPR1 setting.
This flag can be cleared by writing 1 to it.
Note: when this flag is set, the matching counter will be reset to 0,and continue to count when user write 1 to clear CMPF1
[3] BUSY BUSY/IDLE
0 = A/D converter is in idle state.
1 = A/D converter is busy at conversion.
This bit is a mirror of ADST bit in ADCR. That is to say if ADST = 1,then BUSY is 1 and vice versa.
It is read only.
[8:4] CHANNEL Current Conversion Channel
This filed reflects current conversion channel when BUSY=1.
When BUSY=0, it shows the next channel to be converted.
It is read only.
[16] INITRDY ADC Power-Up Sequence Completed
0 = ADC not powered up after system reset.
1 = ADC has been powered up since the last system reset.
Note: This bit will be set after system reset occurred and automatically cleared by power-up event.

Definition at line 437 of file Nano100Series.h.


The documentation for this struct was generated from the following file: