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Nano100BN Series BSP
V3.03.002
The Board Support Package for Nano100BN Series
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Macros | |
| #define | FREQ_128MHZ 128000000 |
| #define | FREQ_120MHZ 120000000 |
| #define | FREQ_48MHZ 48000000 |
| #define | FREQ_42MHZ 42000000 |
| #define | FREQ_32MHZ 32000000 |
| #define | FREQ_24MHZ 24000000 |
| #define | FREQ_12MHZ 12000000 |
| #define | CLK_PWRCTL_HXT_EN (0x1UL<<CLK_PWRCTL_HXT_EN_Pos) |
| #define | CLK_PWRCTL_LXT_EN (0x1UL<<CLK_PWRCTL_LXT_EN_Pos) |
| #define | CLK_PWRCTL_HIRC_EN (0x1UL<<CLK_PWRCTL_HIRC_EN_Pos) |
| #define | CLK_PWRCTL_LIRC_EN (0x1UL<<CLK_PWRCTL_LIRC_EN_Pos) |
| #define | CLK_PWRCTL_DELY_EN (0x1UL<<CLK_PWRCTL_WK_DLY_Pos) |
| #define | CLK_PWRCTL_WAKEINT_EN (0x1UL<<CLK_PWRCTL_PD_WK_IE_Pos) |
| #define | CLK_PWRCTL_PWRDOWN_EN (0x1UL<<CLK_PWRCTL_PD_EN_Pos) |
| #define | CLK_PWRCTL_HXT_SELXT (0x1UL<<CLK_PWRCTL_HXT_SELXT_Pos) |
| #define | CLK_PWRCTL_HXT_GAIN (0x1UL<<CLK_PWRCTL_HXT_GAIN_Pos) |
| #define | CLK_PWRCTL_LXT_SCNT (0x1UL<<CLK_PWRCTL_LXT_SCNT_Pos) |
| #define | CLK_AHBCLK_GPIO_EN (0x1UL<<CLK_AHBCLK_GPIO_EN_Pos) |
| #define | CLK_AHBCLK_DMA_EN (0x1UL<<CLK_AHBCLK_DMA_EN_Pos) |
| #define | CLK_AHBCLK_ISP_EN (0x1UL<<CLK_AHBCLK_ISP_EN_Pos) |
| #define | CLK_AHBCLK_EBI_EN (0x1UL<<CLK_AHBCLK_EBI_EN_Pos) |
| #define | CLK_AHBCLK_SRAM_EN (0x1UL<<CLK_AHBCLK_SRAM_EN_Pos) |
| #define | CLK_AHBCLK_TICK_EN (0x1UL<<CLK_AHBCLK_TICK_EN_Pos) |
| #define | CLK_APBCLK_WDT_EN (0x1UL<<CLK_APBCLK_WDT_EN_Pos) |
| #define | CLK_APBCLK_RTC_EN (0x1UL<<CLK_APBCLK_RTC_EN_Pos) |
| #define | CLK_APBCLK_TMR0_EN (0x1UL<<CLK_APBCLK_TMR0_EN_Pos) |
| #define | CLK_APBCLK_TMR1_EN (0x1UL<<CLK_APBCLK_TMR1_EN_Pos) |
| #define | CLK_APBCLK_TMR2_EN (0x1UL<<CLK_APBCLK_TMR2_EN_Pos) |
| #define | CLK_APBCLK_TMR3_EN (0x1UL<<CLK_APBCLK_TMR3_EN_Pos) |
| #define | CLK_APBCLK_FDIV_EN (0x1UL<<CLK_APBCLK_FDIV_EN_Pos) |
| #define | CLK_APBCLK_SC2_EN (0x1UL<<CLK_APBCLK_SC2_EN_Pos) |
| #define | CLK_APBCLK_I2C0_EN (0x1UL<<CLK_APBCLK_I2C0_EN_Pos) |
| #define | CLK_APBCLK_I2C1_EN (0x1UL<<CLK_APBCLK_I2C1_EN_Pos) |
| #define | CLK_APBCLK_SPI0_EN (0x1UL<<CLK_APBCLK_SPI0_EN_Pos) |
| #define | CLK_APBCLK_SPI1_EN (0x1UL<<CLK_APBCLK_SPI1_EN_Pos) |
| #define | CLK_APBCLK_SPI2_EN (0x1UL<<CLK_APBCLK_SPI2_EN_Pos) |
| #define | CLK_APBCLK_UART0_EN (0x1UL<<CLK_APBCLK_UART0_EN_Pos) |
| #define | CLK_APBCLK_UART1_EN (0x1UL<<CLK_APBCLK_UART1_EN_Pos) |
| #define | CLK_APBCLK_PWM0_CH01_EN (0x1UL<<CLK_APBCLK_PWM0_CH01_EN_Pos) |
| #define | CLK_APBCLK_PWM0_CH23_EN (0x1UL<<CLK_APBCLK_PWM0_CH23_EN_Pos) |
| #define | CLK_APBCLK_PWM1_CH01_EN (0x1UL<<CLK_APBCLK_PWM1_CH01_EN_Pos) |
| #define | CLK_APBCLK_PWM1_CH23_EN (0x1UL<<CLK_APBCLK_PWM1_CH23_EN_Pos) |
| #define | CLK_APBCLK_DAC_EN (0x1UL<<CLK_APBCLK_DAC_EN_Pos) |
| #define | CLK_APBCLK_LCD_EN (0x1UL<<CLK_APBCLK_LCD_EN_Pos) |
| #define | CLK_APBCLK_USBD_EN (0x1UL<<CLK_APBCLK_USBD_EN_Pos) |
| #define | CLK_APBCLK_ADC_EN (0x1UL<<CLK_APBCLK_ADC_EN_Pos) |
| #define | CLK_APBCLK_I2S_EN (0x1UL<<CLK_APBCLK_I2S_EN_Pos) |
| #define | CLK_APBCLK_SC0_EN (0x1UL<<CLK_APBCLK_SC0_EN_Pos) |
| #define | CLK_APBCLK_SC1_EN (0x1UL<<CLK_APBCLK_SC1_EN_Pos) |
| #define | CLK_CLKSTATUS_HXT_STB (0x1UL<<CLK_CLKSTATUS_HXT_STB_Pos) |
| #define | CLK_CLKSTATUS_LXT_STB (0x1UL<<CLK_CLKSTATUS_LXT_STB_Pos) |
| #define | CLK_CLKSTATUS_PLL_STB (0x1UL<<CLK_CLKSTATUS_PLL_STB_Pos) |
| #define | CLK_CLKSTATUS_LIRC_STB (0x1UL<<CLK_CLKSTATUS_LIRC_STB_Pos) |
| #define | CLK_CLKSTATUS_HIRC_STB (0x1UL<<CLK_CLKSTATUS_HIRC_STB_Pos) |
| #define | CLK_CLKSTATUS_CLK_SW_FAIL (0x1UL<<CLK_CLKSTATUS_CLK_SW_FAIL_Pos) |
| #define | CLK_CLKSEL0_HCLK_S_HXT (0UL<<CLK_CLKSEL0_HCLK_S_Pos) |
| #define | CLK_CLKSEL0_HCLK_S_LXT (1UL<<CLK_CLKSEL0_HCLK_S_Pos) |
| #define | CLK_CLKSEL0_HCLK_S_PLL (2UL<<CLK_CLKSEL0_HCLK_S_Pos) |
| #define | CLK_CLKSEL0_HCLK_S_LIRC (3UL<<CLK_CLKSEL0_HCLK_S_Pos) |
| #define | CLK_CLKSEL0_HCLK_S_HIRC (7UL<<CLK_CLKSEL0_HCLK_S_Pos) |
| #define | CLK_CLKSEL1_LCD_S_LXT (0x0UL<<CLK_CLKSEL1_LCD_S_Pos) |
| #define | CLK_CLKSEL1_TMR1_S_HXT (0x0UL<<CLK_CLKSEL1_TMR1_S_Pos) |
| #define | CLK_CLKSEL1_TMR1_S_LXT (0x1UL<<CLK_CLKSEL1_TMR1_S_Pos) |
| #define | CLK_CLKSEL1_TMR1_S_LIRC (0x2UL<<CLK_CLKSEL1_TMR1_S_Pos) |
| #define | CLK_CLKSEL1_TMR1_S_EXT (0x3UL<<CLK_CLKSEL1_TMR1_S_Pos) |
| #define | CLK_CLKSEL1_TMR1_S_HIRC (0x4UL<<CLK_CLKSEL1_TMR1_S_Pos) |
| #define | CLK_CLKSEL1_TMR0_S_HXT (0x0UL<<CLK_CLKSEL1_TMR0_S_Pos) |
| #define | CLK_CLKSEL1_TMR0_S_LXT (0x1UL<<CLK_CLKSEL1_TMR0_S_Pos) |
| #define | CLK_CLKSEL1_TMR0_S_LIRC (0x2UL<<CLK_CLKSEL1_TMR0_S_Pos) |
| #define | CLK_CLKSEL1_TMR0_S_EXT (0x3UL<<CLK_CLKSEL1_TMR0_S_Pos) |
| #define | CLK_CLKSEL1_TMR0_S_HIRC (0x4UL<<CLK_CLKSEL1_TMR0_S_Pos) |
| #define | CLK_CLKSEL1_PWM0_CH01_S_HXT (0x0UL<<CLK_CLKSEL1_PWM0_CH01_S_Pos) |
| #define | CLK_CLKSEL1_PWM0_CH01_S_LXT (0x1UL<<CLK_CLKSEL1_PWM0_CH01_S_Pos) |
| #define | CLK_CLKSEL1_PWM0_CH01_S_HCLK (0x2UL<<CLK_CLKSEL1_PWM0_CH01_S_Pos) |
| #define | CLK_CLKSEL1_PWM0_CH01_S_HIRC (0x3UL<<CLK_CLKSEL1_PWM0_CH01_S_Pos) |
| #define | CLK_CLKSEL1_PWM0_CH23_S_HXT (0x0UL<<CLK_CLKSEL1_PWM0_CH23_S_Pos) |
| #define | CLK_CLKSEL1_PWM0_CH23_S_LXT (0x1UL<<CLK_CLKSEL1_PWM0_CH23_S_Pos) |
| #define | CLK_CLKSEL1_PWM0_CH23_S_HCLK (0x2UL<<CLK_CLKSEL1_PWM0_CH23_S_Pos) |
| #define | CLK_CLKSEL1_PWM0_CH23_S_HIRC (0x3UL<<CLK_CLKSEL1_PWM0_CH23_S_Pos) |
| #define | CLK_CLKSEL1_ADC_S_HXT (0x0UL<<CLK_CLKSEL1_ADC_S_Pos) |
| #define | CLK_CLKSEL1_ADC_S_LXT (0x1UL<<CLK_CLKSEL1_ADC_S_Pos) |
| #define | CLK_CLKSEL1_ADC_S_PLL (0x2UL<<CLK_CLKSEL1_ADC_S_Pos) |
| #define | CLK_CLKSEL1_ADC_S_HIRC (0x3UL<<CLK_CLKSEL1_ADC_S_Pos) |
| #define | CLK_CLKSEL1_UART_S_HXT (0x0UL<<CLK_CLKSEL1_UART_S_Pos) |
| #define | CLK_CLKSEL1_UART_S_LXT (0x1UL<<CLK_CLKSEL1_UART_S_Pos) |
| #define | CLK_CLKSEL1_UART_S_PLL (0x2UL<<CLK_CLKSEL1_UART_S_Pos) |
| #define | CLK_CLKSEL1_UART_S_HIRC (0x3UL<<CLK_CLKSEL1_UART_S_Pos) |
| #define | CLK_CLKSEL2_SPI2_S_PLL (0x0UL<<CLK_CLKSEL2_SPI2_S_Pos) |
| #define | CLK_CLKSEL2_SPI2_S_HCLK (0x1UL<<CLK_CLKSEL2_SPI2_S_Pos) |
| #define | CLK_CLKSEL2_SPI1_S_PLL (0x0UL<<CLK_CLKSEL2_SPI1_S_Pos) |
| #define | CLK_CLKSEL2_SPI1_S_HCLK (0x1UL<<CLK_CLKSEL2_SPI1_S_Pos) |
| #define | CLK_CLKSEL2_SPI0_S_PLL (0x0UL<<CLK_CLKSEL2_SPI0_S_Pos) |
| #define | CLK_CLKSEL2_SPI0_S_HCLK (0x1UL<<CLK_CLKSEL2_SPI0_S_Pos) |
| #define | CLK_CLKSEL2_SC_S_HXT (0x0UL<<CLK_CLKSEL2_SC_S_Pos) |
| #define | CLK_CLKSEL2_SC_S_PLL (0x1UL<<CLK_CLKSEL2_SC_S_Pos) |
| #define | CLK_CLKSEL2_SC_S_HIRC (0x2UL<<CLK_CLKSEL2_SC_S_Pos) |
| #define | CLK_CLKSEL2_I2S_S_HXT (0x0UL<<CLK_CLKSEL2_I2S_S_Pos) |
| #define | CLK_CLKSEL2_I2S_S_PLL (0x1UL<<CLK_CLKSEL2_I2S_S_Pos) |
| #define | CLK_CLKSEL2_I2S_S_HIRC (0x2UL<<CLK_CLKSEL2_I2S_S_Pos) |
| #define | CLK_CLKSEL2_TMR3_S_HXT (0x0UL<<CLK_CLKSEL2_TMR3_S_Pos) |
| #define | CLK_CLKSEL2_TMR3_S_LXT (0x1UL<<CLK_CLKSEL2_TMR3_S_Pos) |
| #define | CLK_CLKSEL2_TMR3_S_LIRC (0x2UL<<CLK_CLKSEL2_TMR3_S_Pos) |
| #define | CLK_CLKSEL2_TMR3_S_EXT (0x3UL<<CLK_CLKSEL2_TMR3_S_Pos) |
| #define | CLK_CLKSEL2_TMR3_S_HIRC (0x4UL<<CLK_CLKSEL2_TMR3_S_Pos) |
| #define | CLK_CLKSEL2_TMR2_S_HXT (0x0UL<<CLK_CLKSEL2_TMR2_S_Pos) |
| #define | CLK_CLKSEL2_TMR2_S_LXT (0x1UL<<CLK_CLKSEL2_TMR2_S_Pos) |
| #define | CLK_CLKSEL2_TMR2_S_LIRC (0x2UL<<CLK_CLKSEL2_TMR2_S_Pos) |
| #define | CLK_CLKSEL2_TMR2_S_EXT (0x3UL<<CLK_CLKSEL2_TMR2_S_Pos) |
| #define | CLK_CLKSEL2_TMR2_S_HIRC (0x4UL<<CLK_CLKSEL2_TMR2_S_Pos) |
| #define | CLK_CLKSEL2_PWM1_CH01_S_HXT (0x0UL<<CLK_CLKSEL2_PWM1_CH01_S_Pos) |
| #define | CLK_CLKSEL2_PWM1_CH01_S_LXT (0x1UL<<CLK_CLKSEL2_PWM1_CH01_S_Pos) |
| #define | CLK_CLKSEL2_PWM1_CH01_S_HCLK (0x2UL<<CLK_CLKSEL2_PWM1_CH01_S_Pos) |
| #define | CLK_CLKSEL2_PWM1_CH01_S_HIRC (0x3UL<<CLK_CLKSEL2_PWM1_CH01_S_Pos) |
| #define | CLK_CLKSEL2_PWM1_CH23_S_HXT (0x0UL<<CLK_CLKSEL2_PWM1_CH23_S_Pos) |
| #define | CLK_CLKSEL2_PWM1_CH23_S_LXT (0x1UL<<CLK_CLKSEL2_PWM1_CH23_S_Pos) |
| #define | CLK_CLKSEL2_PWM1_CH23_S_HCLK (0x2UL<<CLK_CLKSEL2_PWM1_CH23_S_Pos) |
| #define | CLK_CLKSEL2_PWM1_CH23_S_HIRC (0x3UL<<CLK_CLKSEL2_PWM1_CH23_S_Pos) |
| #define | CLK_CLKSEL2_FRQDIV_S_HXT (0x0UL<<CLK_CLKSEL2_FRQDIV_S_Pos) |
| #define | CLK_CLKSEL2_FRQDIV_S_LXT (0x1UL<<CLK_CLKSEL2_FRQDIV_S_Pos) |
| #define | CLK_CLKSEL2_FRQDIV_S_HCLK (0x2UL<<CLK_CLKSEL2_FRQDIV_S_Pos) |
| #define | CLK_CLKSEL2_FRQDIV_S_HIRC (0x3UL<<CLK_CLKSEL2_FRQDIV_S_Pos) |
| #define | CLK_HCLK_CLK_DIVIDER(x) (((x-1)<< CLK_CLKDIV0_HCLK_N_Pos) & CLK_CLKDIV0_HCLK_N_Msk) |
| #define | CLK_USB_CLK_DIVIDER(x) (((x-1)<< CLK_CLKDIV0_USB_N_Pos) & CLK_CLKDIV0_USB_N_Msk) |
| #define | CLK_UART_CLK_DIVIDER(x) (((x-1)<< CLK_CLKDIV0_UART_N_Pos) & CLK_CLKDIV0_UART_N_Msk) |
| #define | CLK_ADC_CLK_DIVIDER(x) (((x-1)<< CLK_CLKDIV0_ADC_N_Pos) & CLK_CLKDIV0_ADC_N_Msk) |
| #define | CLK_SC0_CLK_DIVIDER(x) (((x-1)<< CLK_CLKDIV0_SC0_N_Pos) & CLK_CLKDIV0_SC0_N_Msk) |
| #define | CLK_I2S_CLK_DIVIDER(x) (((x-1)<< CLK_CLKDIV0_I2S_N_Pos) & CLK_CLKDIV0_I2S_N_Msk) |
| #define | CLK_SC2_CLK_DIVIDER(x) (((x-1)<< CLK_CLKDIV1_SC2_N_Pos ) & CLK_CLKDIV1_SC2_N_Msk) |
| #define | CLK_SC1_CLK_DIVIDER(x) (((x-1)<< CLK_CLKDIV1_SC1_N_Pos ) & CLK_CLKDIV1_SC1_N_Msk) |
| #define | CLK_CLKSEL0_STCLKSEL_HCLK (1) |
| #define | CLK_CLKSEL0_STCLKSEL_HCLK_DIV8 (2) |
| #define | CLK_PLLCTL_OUT_DV (0x1UL<<CLK_PLLCTL_OUT_DV_Pos) |
| #define | CLK_PLLCTL_PD (0x1UL<<CLK_PLLCTL_PD_Pos) |
| #define | CLK_PLLCTL_PLL_SRC_HIRC (0x1UL<<CLK_PLLCTL_PLL_SRC_Pos) |
| #define | CLK_PLLCTL_PLL_SRC_HXT (0x0UL<<CLK_PLLCTL_PLL_SRC_Pos) |
| #define | CLK_PLLCTL_NR_2 0x000 |
| #define | CLK_PLLCTL_NR_4 0x100 |
| #define | CLK_PLLCTL_NR_8 0x200 |
| #define | CLK_PLLCTL_NR_16 0x300 |
| #define | CLK_PLLCON_NF(x) ((x)-32) |
| #define | CLK_PLLCON_NO_1 0x0000UL |
| #define | CLK_PLLCON_NO_2 0x1000UL |
| #define | CLK_PLLCTL_120MHz_HIRC (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLLCON_NO_1 | CLK_PLLCTL_NR_4 | CLK_PLLCON_NF(40) ) |
| #define | CLK_PLLCTL_96MHz_HIRC (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLLCON_NO_1 | CLK_PLLCTL_NR_8 | CLK_PLLCON_NF(64) ) |
| #define | CLK_PLLCTL_48MHz_HIRC (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLLCON_NO_1 | CLK_PLLCTL_NR_16| CLK_PLLCON_NF(64) ) |
| #define | CLK_PLLCTL_84MHz_HIRC (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLLCON_NO_1 | CLK_PLLCTL_NR_8 | CLK_PLLCON_NF(56) ) |
| #define | CLK_PLLCTL_42MHz_HIRC (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLLCON_NO_1 | CLK_PLLCTL_NR_16| CLK_PLLCON_NF(56) ) |
| #define | CLK_FRQDIV_EN (0x1UL<<CLK_FRQDIV_FDIV_EN_Pos) |
| #define | CLK_WK_INTSTS_IS (0x1UL<<CLK_WK_INTSTS_PD_WK_IS_Pos) |
| #define | CLK_MCLKO_MCLK_SEL_ISP_CLK (0x00<<CLK_MCLKO_MCLK_SEL_Pos) |
| #define | CLK_MCLKO_MCLK_SEL_HIRC (0x01<<CLK_MCLKO_MCLK_SEL_Pos) |
| #define | CLK_MCLKO_MCLK_SEL_HXT (0x02<<CLK_MCLKO_MCLK_SEL_Pos) |
| #define | CLK_MCLKO_MCLK_SEL_LXT (0x03<<CLK_MCLKO_MCLK_SEL_Pos) |
| #define | CLK_MCLKO_MCLK_SEL_LIRC (0x04<<CLK_MCLKO_MCLK_SEL_Pos) |
| #define | CLK_MCLKO_MCLK_SEL_PLLO (0x05<<CLK_MCLKO_MCLK_SEL_Pos) |
| #define | CLK_MCLKO_MCLK_SEL_PLLI (0x06<<CLK_MCLKO_MCLK_SEL_Pos) |
| #define | CLK_MCLKO_MCLK_SEL_SYSTICK (0x07<<CLK_MCLKO_MCLK_SEL_Pos) |
| #define | CLK_MCLKO_MCLK_SEL_HCLK (0x08<<CLK_MCLKO_MCLK_SEL_Pos) |
| #define | CLK_MCLKO_MCLK_SEL_PCLK (0x0A<<CLK_MCLKO_MCLK_SEL_Pos) |
| #define | CLK_MCLKO_MCLK_SEL_TMR0 (0x20<<CLK_MCLKO_MCLK_SEL_Pos) |
| #define | CLK_MCLKO_MCLK_SEL_TMR1 (0x21<<CLK_MCLKO_MCLK_SEL_Pos) |
| #define | CLK_MCLKO_MCLK_SEL_UART0 (0x22<<CLK_MCLKO_MCLK_SEL_Pos) |
| #define | CLK_MCLKO_MCLK_SEL_USB (0x23<<CLK_MCLKO_MCLK_SEL_Pos) |
| #define | CLK_MCLKO_MCLK_SEL_ADC (0x24<<CLK_MCLKO_MCLK_SEL_Pos) |
| #define | CLK_MCLKO_MCLK_SEL_WDT (0x25<<CLK_MCLKO_MCLK_SEL_Pos) |
| #define | CLK_MCLKO_MCLK_SEL_PWM0CH01 (0x26<<CLK_MCLKO_MCLK_SEL_Pos) |
| #define | CLK_MCLKO_MCLK_SEL_PWM0CH23 (0x27<<CLK_MCLKO_MCLK_SEL_Pos) |
| #define | CLK_MCLKO_MCLK_SEL_LCD (0x29<<CLK_MCLKO_MCLK_SEL_Pos) |
| #define | CLK_MCLKO_MCLK_SEL_TMR2 (0x38<<CLK_MCLKO_MCLK_SEL_Pos) |
| #define | CLK_MCLKO_MCLK_SEL_TMR3 (0x39<<CLK_MCLKO_MCLK_SEL_Pos) |
| #define | CLK_MCLKO_MCLK_SEL_UART1 (0x3A<<CLK_MCLKO_MCLK_SEL_Pos) |
| #define | CLK_MCLKO_MCLK_SEL_PWM1CH01 (0x3B<<CLK_MCLKO_MCLK_SEL_Pos) |
| #define | CLK_MCLKO_MCLK_SEL_PWM1CH23 (0x3C<<CLK_MCLKO_MCLK_SEL_Pos) |
| #define | CLK_MCLKO_MCLK_SEL_I2S (0x3D<<CLK_MCLKO_MCLK_SEL_Pos) |
| #define | CLK_MCLKO_MCLK_SEL_SC0 (0x3E<<CLK_MCLKO_MCLK_SEL_Pos) |
| #define | CLK_MCLKO_MCLK_SEL_SC1 (0x3F<<CLK_MCLKO_MCLK_SEL_Pos) |
| #define | MODULE_APBCLK(x) ((x >>31) & 0x1) |
| #define | MODULE_CLKSEL(x) ((x >>29) & 0x3) |
| #define | MODULE_CLKSEL_Msk(x) ((x >>25) & 0xf) |
| #define | MODULE_CLKSEL_Pos(x) ((x >>20) & 0x1f) |
| #define | MODULE_CLKDIV(x) ((x >>18) & 0x3) |
| #define | MODULE_CLKDIV_Msk(x) ((x >>10) & 0xff) |
| #define | MODULE_CLKDIV_Pos(x) ((x >>5 ) & 0x1f) |
| #define | MODULE_IP_EN_Pos(x) ((x >>0 ) & 0x1f) |
| #define | MODULE_NoMsk 0x0 |
| #define | NA MODULE_NoMsk |
| #define | MODULE_APBCLK_ENC(x) (((x) & 0x01) << 31) |
| #define | MODULE_CLKSEL_ENC(x) (((x) & 0x03) << 29) |
| #define | MODULE_CLKSEL_Msk_ENC(x) (((x) & 0x0f) << 25) |
| #define | MODULE_CLKSEL_Pos_ENC(x) (((x) & 0x1f) << 20) |
| #define | MODULE_CLKDIV_ENC(x) (((x) & 0x03) << 18) |
| #define | MODULE_CLKDIV_Msk_ENC(x) (((x) & 0xff) << 10) |
| #define | MODULE_CLKDIV_Pos_ENC(x) (((x) & 0x1f) << 5) |
| #define | MODULE_IP_EN_Pos_ENC(x) (((x) & 0x1f) << 0) |
| #define | TICK_MODULE ((0UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(1<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_TICK_EN_Pos ) |
| #define | SRAM_MODULE ((0UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(1<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_SRAM_EN_Pos ) |
| #define | EBI_MODULE ((0UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(1<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_EBI_EN_Pos ) |
| #define | ISP_MODULE ((0UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(1<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_ISP_EN_Pos ) |
| #define | DMA_MODULE ((0UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_DMA_EN_Pos ) |
| #define | GPIO_MODULE ((0UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_GPIO_EN_Pos ) |
| #define | SC2_MODULE ((1UL<<31)|(2<<29)|(3<<25) |(18<<20)|(1<<18)|(0xF<<10) |( 4<<5)|CLK_APBCLK_SC2_EN_Pos ) |
| #define | SC1_MODULE ((1UL<<31)|(2<<29)|(3<<25) |(18<<20)|(1<<18)|(0xF<<10) |( 0<<5)|CLK_APBCLK_SC1_EN_Pos ) |
| #define | SC0_MODULE ((1UL<<31)|(2<<29)|(3<<25) |(18<<20)|(0<<18)|(0xF<<10) |(28<<5)|CLK_APBCLK_SC0_EN_Pos ) |
| #define | I2S_MODULE ((1UL<<31)|(2<<29)|(3<<25) |(16<<20)|(0<<18)|(0xF<<10) |(12<<5)|CLK_APBCLK_I2S_EN_Pos ) |
| #define | ADC_MODULE ((1UL<<31)|(1<<29)|(3<<25) |( 2<<20)|(0<<18)|(0xFF<<10) |(16<<5)|CLK_APBCLK_ADC_EN_Pos ) |
| #define | USBD_MODULE ((1UL<<31)|(1<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(0xF<<10) |( 4<<5)|CLK_APBCLK_USBD_EN_Pos ) |
| #define | PWM1_CH23_MODULE ((1UL<<31)|(2<<29)|(3<<25) |( 6<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_PWM1_CH23_EN_Pos) |
| #define | PWM1_CH01_MODULE ((1UL<<31)|(2<<29)|(3<<25) |( 4<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_PWM1_CH01_EN_Pos) |
| #define | PWM0_CH23_MODULE ((1UL<<31)|(1<<29)|(3<<25) |( 6<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_PWM0_CH23_EN_Pos) |
| #define | PWM0_CH01_MODULE ((1UL<<31)|(1<<29)|(3<<25) |( 4<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_PWM0_CH01_EN_Pos) |
| #define | UART1_MODULE ((1UL<<31)|(1<<29)|(3<<25) |( 0<<20)|(0<<18)|(0xF<<10) |( 8<<5)|CLK_APBCLK_UART1_EN_Pos ) |
| #define | UART0_MODULE ((1UL<<31)|(1<<29)|(3<<25) |( 0<<20)|(0<<18)|(0xF<<10) |( 8<<5)|CLK_APBCLK_UART0_EN_Pos ) |
| #define | SPI2_MODULE ((1UL<<31)|(2<<29)|(1<<25) |(22<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_SPI2_EN_Pos ) |
| #define | SPI1_MODULE ((1UL<<31)|(2<<29)|(1<<25) |(21<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_SPI1_EN_Pos ) |
| #define | SPI0_MODULE ((1UL<<31)|(2<<29)|(1<<25) |(20<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_SPI0_EN_Pos ) |
| #define | I2C1_MODULE ((1UL<<31)|(0<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_I2C1_EN_Pos ) |
| #define | I2C0_MODULE ((1UL<<31)|(0<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_I2C0_EN_Pos ) |
| #define | FDIV_MODULE ((1UL<<31)|(2<<29)|(3<<25) |( 2<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_FDIV_EN_Pos ) |
| #define | TMR3_MODULE ((1UL<<31)|(2<<29)|(7<<25) |(12<<20)|(1<<18)|(0xF<<10) |(20<<5)|CLK_APBCLK_TMR3_EN_Pos ) |
| #define | TMR2_MODULE ((1UL<<31)|(2<<29)|(7<<25) |( 8<<20)|(1<<18)|(0xF<<10) |(16<<5)|CLK_APBCLK_TMR2_EN_Pos ) |
| #define | TMR1_MODULE ((1UL<<31)|(1<<29)|(7<<25) |(12<<20)|(1<<18)|(0xF<<10) |(12<<5)|CLK_APBCLK_TMR1_EN_Pos ) |
| #define | TMR0_MODULE ((1UL<<31)|(1<<29)|(7<<25) |( 8<<20)|(1<<18)|(0xF<<10) |( 8<<5)|CLK_APBCLK_TMR0_EN_Pos ) |
| #define | RTC_MODULE ((1UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_RTC_EN_Pos ) |
| #define | WDT_MODULE ((1UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_WDT_EN_Pos ) |
| #define | LCD_MODULE ((1UL<<31)|(1<<29)|(1<<25) |(18<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_LCD_EN_Pos ) |
| #define | DAC_MODULE ((1UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_DAC_EN_Pos ) |
| #define ADC_MODULE ((1UL<<31)|(1<<29)|(3<<25) |( 2<<20)|(0<<18)|(0xFF<<10) |(16<<5)|CLK_APBCLK_ADC_EN_Pos ) |
| #define CLK_ADC_CLK_DIVIDER | ( | x | ) | (((x-1)<< CLK_CLKDIV0_ADC_N_Pos) & CLK_CLKDIV0_ADC_N_Msk) |
| #define CLK_AHBCLK_DMA_EN (0x1UL<<CLK_AHBCLK_DMA_EN_Pos) |
| #define CLK_AHBCLK_EBI_EN (0x1UL<<CLK_AHBCLK_EBI_EN_Pos) |
| #define CLK_AHBCLK_GPIO_EN (0x1UL<<CLK_AHBCLK_GPIO_EN_Pos) |
| #define CLK_AHBCLK_ISP_EN (0x1UL<<CLK_AHBCLK_ISP_EN_Pos) |
| #define CLK_AHBCLK_SRAM_EN (0x1UL<<CLK_AHBCLK_SRAM_EN_Pos) |
| #define CLK_AHBCLK_TICK_EN (0x1UL<<CLK_AHBCLK_TICK_EN_Pos) |
| #define CLK_APBCLK_ADC_EN (0x1UL<<CLK_APBCLK_ADC_EN_Pos) |
| #define CLK_APBCLK_DAC_EN (0x1UL<<CLK_APBCLK_DAC_EN_Pos) |
| #define CLK_APBCLK_FDIV_EN (0x1UL<<CLK_APBCLK_FDIV_EN_Pos) |
| #define CLK_APBCLK_I2C0_EN (0x1UL<<CLK_APBCLK_I2C0_EN_Pos) |
| #define CLK_APBCLK_I2C1_EN (0x1UL<<CLK_APBCLK_I2C1_EN_Pos) |
| #define CLK_APBCLK_I2S_EN (0x1UL<<CLK_APBCLK_I2S_EN_Pos) |
| #define CLK_APBCLK_LCD_EN (0x1UL<<CLK_APBCLK_LCD_EN_Pos) |
| #define CLK_APBCLK_PWM0_CH01_EN (0x1UL<<CLK_APBCLK_PWM0_CH01_EN_Pos) |
| #define CLK_APBCLK_PWM0_CH23_EN (0x1UL<<CLK_APBCLK_PWM0_CH23_EN_Pos) |
| #define CLK_APBCLK_PWM1_CH01_EN (0x1UL<<CLK_APBCLK_PWM1_CH01_EN_Pos) |
| #define CLK_APBCLK_PWM1_CH23_EN (0x1UL<<CLK_APBCLK_PWM1_CH23_EN_Pos) |
| #define CLK_APBCLK_RTC_EN (0x1UL<<CLK_APBCLK_RTC_EN_Pos) |
| #define CLK_APBCLK_SC0_EN (0x1UL<<CLK_APBCLK_SC0_EN_Pos) |
| #define CLK_APBCLK_SC1_EN (0x1UL<<CLK_APBCLK_SC1_EN_Pos) |
| #define CLK_APBCLK_SC2_EN (0x1UL<<CLK_APBCLK_SC2_EN_Pos) |
| #define CLK_APBCLK_SPI0_EN (0x1UL<<CLK_APBCLK_SPI0_EN_Pos) |
| #define CLK_APBCLK_SPI1_EN (0x1UL<<CLK_APBCLK_SPI1_EN_Pos) |
| #define CLK_APBCLK_SPI2_EN (0x1UL<<CLK_APBCLK_SPI2_EN_Pos) |
| #define CLK_APBCLK_TMR0_EN (0x1UL<<CLK_APBCLK_TMR0_EN_Pos) |
| #define CLK_APBCLK_TMR1_EN (0x1UL<<CLK_APBCLK_TMR1_EN_Pos) |
| #define CLK_APBCLK_TMR2_EN (0x1UL<<CLK_APBCLK_TMR2_EN_Pos) |
| #define CLK_APBCLK_TMR3_EN (0x1UL<<CLK_APBCLK_TMR3_EN_Pos) |
| #define CLK_APBCLK_UART0_EN (0x1UL<<CLK_APBCLK_UART0_EN_Pos) |
| #define CLK_APBCLK_UART1_EN (0x1UL<<CLK_APBCLK_UART1_EN_Pos) |
| #define CLK_APBCLK_USBD_EN (0x1UL<<CLK_APBCLK_USBD_EN_Pos) |
| #define CLK_APBCLK_WDT_EN (0x1UL<<CLK_APBCLK_WDT_EN_Pos) |
| #define CLK_CLKSEL0_HCLK_S_HIRC (7UL<<CLK_CLKSEL0_HCLK_S_Pos) |
| #define CLK_CLKSEL0_HCLK_S_HXT (0UL<<CLK_CLKSEL0_HCLK_S_Pos) |
| #define CLK_CLKSEL0_HCLK_S_LIRC (3UL<<CLK_CLKSEL0_HCLK_S_Pos) |
| #define CLK_CLKSEL0_HCLK_S_LXT (1UL<<CLK_CLKSEL0_HCLK_S_Pos) |
| #define CLK_CLKSEL0_HCLK_S_PLL (2UL<<CLK_CLKSEL0_HCLK_S_Pos) |
| #define CLK_CLKSEL0_STCLKSEL_HCLK (1) |
| #define CLK_CLKSEL0_STCLKSEL_HCLK_DIV8 (2) |
| #define CLK_CLKSEL1_ADC_S_HIRC (0x3UL<<CLK_CLKSEL1_ADC_S_Pos) |
| #define CLK_CLKSEL1_ADC_S_HXT (0x0UL<<CLK_CLKSEL1_ADC_S_Pos) |
| #define CLK_CLKSEL1_ADC_S_LXT (0x1UL<<CLK_CLKSEL1_ADC_S_Pos) |
| #define CLK_CLKSEL1_ADC_S_PLL (0x2UL<<CLK_CLKSEL1_ADC_S_Pos) |
| #define CLK_CLKSEL1_LCD_S_LXT (0x0UL<<CLK_CLKSEL1_LCD_S_Pos) |
| #define CLK_CLKSEL1_PWM0_CH01_S_HCLK (0x2UL<<CLK_CLKSEL1_PWM0_CH01_S_Pos) |
| #define CLK_CLKSEL1_PWM0_CH01_S_HIRC (0x3UL<<CLK_CLKSEL1_PWM0_CH01_S_Pos) |
| #define CLK_CLKSEL1_PWM0_CH01_S_HXT (0x0UL<<CLK_CLKSEL1_PWM0_CH01_S_Pos) |
| #define CLK_CLKSEL1_PWM0_CH01_S_LXT (0x1UL<<CLK_CLKSEL1_PWM0_CH01_S_Pos) |
| #define CLK_CLKSEL1_PWM0_CH23_S_HCLK (0x2UL<<CLK_CLKSEL1_PWM0_CH23_S_Pos) |
| #define CLK_CLKSEL1_PWM0_CH23_S_HIRC (0x3UL<<CLK_CLKSEL1_PWM0_CH23_S_Pos) |
| #define CLK_CLKSEL1_PWM0_CH23_S_HXT (0x0UL<<CLK_CLKSEL1_PWM0_CH23_S_Pos) |
| #define CLK_CLKSEL1_PWM0_CH23_S_LXT (0x1UL<<CLK_CLKSEL1_PWM0_CH23_S_Pos) |
| #define CLK_CLKSEL1_TMR0_S_EXT (0x3UL<<CLK_CLKSEL1_TMR0_S_Pos) |
| #define CLK_CLKSEL1_TMR0_S_HIRC (0x4UL<<CLK_CLKSEL1_TMR0_S_Pos) |
| #define CLK_CLKSEL1_TMR0_S_HXT (0x0UL<<CLK_CLKSEL1_TMR0_S_Pos) |
| #define CLK_CLKSEL1_TMR0_S_LIRC (0x2UL<<CLK_CLKSEL1_TMR0_S_Pos) |
| #define CLK_CLKSEL1_TMR0_S_LXT (0x1UL<<CLK_CLKSEL1_TMR0_S_Pos) |
| #define CLK_CLKSEL1_TMR1_S_EXT (0x3UL<<CLK_CLKSEL1_TMR1_S_Pos) |
| #define CLK_CLKSEL1_TMR1_S_HIRC (0x4UL<<CLK_CLKSEL1_TMR1_S_Pos) |
| #define CLK_CLKSEL1_TMR1_S_HXT (0x0UL<<CLK_CLKSEL1_TMR1_S_Pos) |
| #define CLK_CLKSEL1_TMR1_S_LIRC (0x2UL<<CLK_CLKSEL1_TMR1_S_Pos) |
| #define CLK_CLKSEL1_TMR1_S_LXT (0x1UL<<CLK_CLKSEL1_TMR1_S_Pos) |
| #define CLK_CLKSEL1_UART_S_HIRC (0x3UL<<CLK_CLKSEL1_UART_S_Pos) |
| #define CLK_CLKSEL1_UART_S_HXT (0x0UL<<CLK_CLKSEL1_UART_S_Pos) |
| #define CLK_CLKSEL1_UART_S_LXT (0x1UL<<CLK_CLKSEL1_UART_S_Pos) |
| #define CLK_CLKSEL1_UART_S_PLL (0x2UL<<CLK_CLKSEL1_UART_S_Pos) |
| #define CLK_CLKSEL2_FRQDIV_S_HCLK (0x2UL<<CLK_CLKSEL2_FRQDIV_S_Pos) |
| #define CLK_CLKSEL2_FRQDIV_S_HIRC (0x3UL<<CLK_CLKSEL2_FRQDIV_S_Pos) |
| #define CLK_CLKSEL2_FRQDIV_S_HXT (0x0UL<<CLK_CLKSEL2_FRQDIV_S_Pos) |
| #define CLK_CLKSEL2_FRQDIV_S_LXT (0x1UL<<CLK_CLKSEL2_FRQDIV_S_Pos) |
| #define CLK_CLKSEL2_I2S_S_HIRC (0x2UL<<CLK_CLKSEL2_I2S_S_Pos) |
| #define CLK_CLKSEL2_I2S_S_HXT (0x0UL<<CLK_CLKSEL2_I2S_S_Pos) |
| #define CLK_CLKSEL2_I2S_S_PLL (0x1UL<<CLK_CLKSEL2_I2S_S_Pos) |
| #define CLK_CLKSEL2_PWM1_CH01_S_HCLK (0x2UL<<CLK_CLKSEL2_PWM1_CH01_S_Pos) |
| #define CLK_CLKSEL2_PWM1_CH01_S_HIRC (0x3UL<<CLK_CLKSEL2_PWM1_CH01_S_Pos) |
| #define CLK_CLKSEL2_PWM1_CH01_S_HXT (0x0UL<<CLK_CLKSEL2_PWM1_CH01_S_Pos) |
| #define CLK_CLKSEL2_PWM1_CH01_S_LXT (0x1UL<<CLK_CLKSEL2_PWM1_CH01_S_Pos) |
| #define CLK_CLKSEL2_PWM1_CH23_S_HCLK (0x2UL<<CLK_CLKSEL2_PWM1_CH23_S_Pos) |
| #define CLK_CLKSEL2_PWM1_CH23_S_HIRC (0x3UL<<CLK_CLKSEL2_PWM1_CH23_S_Pos) |
| #define CLK_CLKSEL2_PWM1_CH23_S_HXT (0x0UL<<CLK_CLKSEL2_PWM1_CH23_S_Pos) |
| #define CLK_CLKSEL2_PWM1_CH23_S_LXT (0x1UL<<CLK_CLKSEL2_PWM1_CH23_S_Pos) |
| #define CLK_CLKSEL2_SC_S_HIRC (0x2UL<<CLK_CLKSEL2_SC_S_Pos) |
| #define CLK_CLKSEL2_SC_S_HXT (0x0UL<<CLK_CLKSEL2_SC_S_Pos) |
| #define CLK_CLKSEL2_SC_S_PLL (0x1UL<<CLK_CLKSEL2_SC_S_Pos) |
| #define CLK_CLKSEL2_SPI0_S_HCLK (0x1UL<<CLK_CLKSEL2_SPI0_S_Pos) |
| #define CLK_CLKSEL2_SPI0_S_PLL (0x0UL<<CLK_CLKSEL2_SPI0_S_Pos) |
| #define CLK_CLKSEL2_SPI1_S_HCLK (0x1UL<<CLK_CLKSEL2_SPI1_S_Pos) |
| #define CLK_CLKSEL2_SPI1_S_PLL (0x0UL<<CLK_CLKSEL2_SPI1_S_Pos) |
| #define CLK_CLKSEL2_SPI2_S_HCLK (0x1UL<<CLK_CLKSEL2_SPI2_S_Pos) |
| #define CLK_CLKSEL2_SPI2_S_PLL (0x0UL<<CLK_CLKSEL2_SPI2_S_Pos) |
| #define CLK_CLKSEL2_TMR2_S_EXT (0x3UL<<CLK_CLKSEL2_TMR2_S_Pos) |
| #define CLK_CLKSEL2_TMR2_S_HIRC (0x4UL<<CLK_CLKSEL2_TMR2_S_Pos) |
| #define CLK_CLKSEL2_TMR2_S_HXT (0x0UL<<CLK_CLKSEL2_TMR2_S_Pos) |
| #define CLK_CLKSEL2_TMR2_S_LIRC (0x2UL<<CLK_CLKSEL2_TMR2_S_Pos) |
| #define CLK_CLKSEL2_TMR2_S_LXT (0x1UL<<CLK_CLKSEL2_TMR2_S_Pos) |
| #define CLK_CLKSEL2_TMR3_S_EXT (0x3UL<<CLK_CLKSEL2_TMR3_S_Pos) |
| #define CLK_CLKSEL2_TMR3_S_HIRC (0x4UL<<CLK_CLKSEL2_TMR3_S_Pos) |
| #define CLK_CLKSEL2_TMR3_S_HXT (0x0UL<<CLK_CLKSEL2_TMR3_S_Pos) |
| #define CLK_CLKSEL2_TMR3_S_LIRC (0x2UL<<CLK_CLKSEL2_TMR3_S_Pos) |
| #define CLK_CLKSEL2_TMR3_S_LXT (0x1UL<<CLK_CLKSEL2_TMR3_S_Pos) |
| #define CLK_CLKSTATUS_CLK_SW_FAIL (0x1UL<<CLK_CLKSTATUS_CLK_SW_FAIL_Pos) |
| #define CLK_CLKSTATUS_HIRC_STB (0x1UL<<CLK_CLKSTATUS_HIRC_STB_Pos) |
| #define CLK_CLKSTATUS_HXT_STB (0x1UL<<CLK_CLKSTATUS_HXT_STB_Pos) |
| #define CLK_CLKSTATUS_LIRC_STB (0x1UL<<CLK_CLKSTATUS_LIRC_STB_Pos) |
| #define CLK_CLKSTATUS_LXT_STB (0x1UL<<CLK_CLKSTATUS_LXT_STB_Pos) |
| #define CLK_CLKSTATUS_PLL_STB (0x1UL<<CLK_CLKSTATUS_PLL_STB_Pos) |
| #define CLK_FRQDIV_EN (0x1UL<<CLK_FRQDIV_FDIV_EN_Pos) |
| #define CLK_HCLK_CLK_DIVIDER | ( | x | ) | (((x-1)<< CLK_CLKDIV0_HCLK_N_Pos) & CLK_CLKDIV0_HCLK_N_Msk) |
| #define CLK_I2S_CLK_DIVIDER | ( | x | ) | (((x-1)<< CLK_CLKDIV0_I2S_N_Pos) & CLK_CLKDIV0_I2S_N_Msk) |
| #define CLK_MCLKO_MCLK_SEL_ADC (0x24<<CLK_MCLKO_MCLK_SEL_Pos) |
| #define CLK_MCLKO_MCLK_SEL_HCLK (0x08<<CLK_MCLKO_MCLK_SEL_Pos) |
| #define CLK_MCLKO_MCLK_SEL_HIRC (0x01<<CLK_MCLKO_MCLK_SEL_Pos) |
| #define CLK_MCLKO_MCLK_SEL_HXT (0x02<<CLK_MCLKO_MCLK_SEL_Pos) |
| #define CLK_MCLKO_MCLK_SEL_I2S (0x3D<<CLK_MCLKO_MCLK_SEL_Pos) |
| #define CLK_MCLKO_MCLK_SEL_ISP_CLK (0x00<<CLK_MCLKO_MCLK_SEL_Pos) |
| #define CLK_MCLKO_MCLK_SEL_LCD (0x29<<CLK_MCLKO_MCLK_SEL_Pos) |
| #define CLK_MCLKO_MCLK_SEL_LIRC (0x04<<CLK_MCLKO_MCLK_SEL_Pos) |
| #define CLK_MCLKO_MCLK_SEL_LXT (0x03<<CLK_MCLKO_MCLK_SEL_Pos) |
| #define CLK_MCLKO_MCLK_SEL_PCLK (0x0A<<CLK_MCLKO_MCLK_SEL_Pos) |
| #define CLK_MCLKO_MCLK_SEL_PLLI (0x06<<CLK_MCLKO_MCLK_SEL_Pos) |
| #define CLK_MCLKO_MCLK_SEL_PLLO (0x05<<CLK_MCLKO_MCLK_SEL_Pos) |
| #define CLK_MCLKO_MCLK_SEL_PWM0CH01 (0x26<<CLK_MCLKO_MCLK_SEL_Pos) |
| #define CLK_MCLKO_MCLK_SEL_PWM0CH23 (0x27<<CLK_MCLKO_MCLK_SEL_Pos) |
| #define CLK_MCLKO_MCLK_SEL_PWM1CH01 (0x3B<<CLK_MCLKO_MCLK_SEL_Pos) |
| #define CLK_MCLKO_MCLK_SEL_PWM1CH23 (0x3C<<CLK_MCLKO_MCLK_SEL_Pos) |
| #define CLK_MCLKO_MCLK_SEL_SC0 (0x3E<<CLK_MCLKO_MCLK_SEL_Pos) |
| #define CLK_MCLKO_MCLK_SEL_SC1 (0x3F<<CLK_MCLKO_MCLK_SEL_Pos) |
| #define CLK_MCLKO_MCLK_SEL_SYSTICK (0x07<<CLK_MCLKO_MCLK_SEL_Pos) |
| #define CLK_MCLKO_MCLK_SEL_TMR0 (0x20<<CLK_MCLKO_MCLK_SEL_Pos) |
| #define CLK_MCLKO_MCLK_SEL_TMR1 (0x21<<CLK_MCLKO_MCLK_SEL_Pos) |
| #define CLK_MCLKO_MCLK_SEL_TMR2 (0x38<<CLK_MCLKO_MCLK_SEL_Pos) |
| #define CLK_MCLKO_MCLK_SEL_TMR3 (0x39<<CLK_MCLKO_MCLK_SEL_Pos) |
| #define CLK_MCLKO_MCLK_SEL_UART0 (0x22<<CLK_MCLKO_MCLK_SEL_Pos) |
| #define CLK_MCLKO_MCLK_SEL_UART1 (0x3A<<CLK_MCLKO_MCLK_SEL_Pos) |
| #define CLK_MCLKO_MCLK_SEL_USB (0x23<<CLK_MCLKO_MCLK_SEL_Pos) |
| #define CLK_MCLKO_MCLK_SEL_WDT (0x25<<CLK_MCLKO_MCLK_SEL_Pos) |
| #define CLK_PLLCON_NF | ( | x | ) | ((x)-32) |
| #define CLK_PLLCTL_120MHz_HIRC (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLLCON_NO_1 | CLK_PLLCTL_NR_4 | CLK_PLLCON_NF(40) ) |
| #define CLK_PLLCTL_42MHz_HIRC (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLLCON_NO_1 | CLK_PLLCTL_NR_16| CLK_PLLCON_NF(56) ) |
| #define CLK_PLLCTL_48MHz_HIRC (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLLCON_NO_1 | CLK_PLLCTL_NR_16| CLK_PLLCON_NF(64) ) |
| #define CLK_PLLCTL_84MHz_HIRC (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLLCON_NO_1 | CLK_PLLCTL_NR_8 | CLK_PLLCON_NF(56) ) |
| #define CLK_PLLCTL_96MHz_HIRC (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLLCON_NO_1 | CLK_PLLCTL_NR_8 | CLK_PLLCON_NF(64) ) |
| #define CLK_PLLCTL_OUT_DV (0x1UL<<CLK_PLLCTL_OUT_DV_Pos) |
| #define CLK_PLLCTL_PD (0x1UL<<CLK_PLLCTL_PD_Pos) |
| #define CLK_PLLCTL_PLL_SRC_HIRC (0x1UL<<CLK_PLLCTL_PLL_SRC_Pos) |
| #define CLK_PLLCTL_PLL_SRC_HXT (0x0UL<<CLK_PLLCTL_PLL_SRC_Pos) |
| #define CLK_PWRCTL_DELY_EN (0x1UL<<CLK_PWRCTL_WK_DLY_Pos) |
| #define CLK_PWRCTL_HIRC_EN (0x1UL<<CLK_PWRCTL_HIRC_EN_Pos) |
| #define CLK_PWRCTL_HXT_EN (0x1UL<<CLK_PWRCTL_HXT_EN_Pos) |
| #define CLK_PWRCTL_HXT_GAIN (0x1UL<<CLK_PWRCTL_HXT_GAIN_Pos) |
| #define CLK_PWRCTL_HXT_SELXT (0x1UL<<CLK_PWRCTL_HXT_SELXT_Pos) |
| #define CLK_PWRCTL_LIRC_EN (0x1UL<<CLK_PWRCTL_LIRC_EN_Pos) |
| #define CLK_PWRCTL_LXT_EN (0x1UL<<CLK_PWRCTL_LXT_EN_Pos) |
| #define CLK_PWRCTL_LXT_SCNT (0x1UL<<CLK_PWRCTL_LXT_SCNT_Pos) |
| #define CLK_PWRCTL_PWRDOWN_EN (0x1UL<<CLK_PWRCTL_PD_EN_Pos) |
| #define CLK_PWRCTL_WAKEINT_EN (0x1UL<<CLK_PWRCTL_PD_WK_IE_Pos) |
| #define CLK_SC0_CLK_DIVIDER | ( | x | ) | (((x-1)<< CLK_CLKDIV0_SC0_N_Pos) & CLK_CLKDIV0_SC0_N_Msk) |
| #define CLK_SC1_CLK_DIVIDER | ( | x | ) | (((x-1)<< CLK_CLKDIV1_SC1_N_Pos ) & CLK_CLKDIV1_SC1_N_Msk) |
| #define CLK_SC2_CLK_DIVIDER | ( | x | ) | (((x-1)<< CLK_CLKDIV1_SC2_N_Pos ) & CLK_CLKDIV1_SC2_N_Msk) |
| #define CLK_UART_CLK_DIVIDER | ( | x | ) | (((x-1)<< CLK_CLKDIV0_UART_N_Pos) & CLK_CLKDIV0_UART_N_Msk) |
| #define CLK_USB_CLK_DIVIDER | ( | x | ) | (((x-1)<< CLK_CLKDIV0_USB_N_Pos) & CLK_CLKDIV0_USB_N_Msk) |
| #define CLK_WK_INTSTS_IS (0x1UL<<CLK_WK_INTSTS_PD_WK_IS_Pos) |
| #define DAC_MODULE ((1UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_DAC_EN_Pos ) |
| #define DMA_MODULE ((0UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_DMA_EN_Pos ) |
| #define EBI_MODULE ((0UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(1<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_EBI_EN_Pos ) |
| #define FDIV_MODULE ((1UL<<31)|(2<<29)|(3<<25) |( 2<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_FDIV_EN_Pos ) |
| #define GPIO_MODULE ((0UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_GPIO_EN_Pos ) |
| #define I2C0_MODULE ((1UL<<31)|(0<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_I2C0_EN_Pos ) |
| #define I2C1_MODULE ((1UL<<31)|(0<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_I2C1_EN_Pos ) |
| #define I2S_MODULE ((1UL<<31)|(2<<29)|(3<<25) |(16<<20)|(0<<18)|(0xF<<10) |(12<<5)|CLK_APBCLK_I2S_EN_Pos ) |
| #define ISP_MODULE ((0UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(1<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_ISP_EN_Pos ) |
| #define LCD_MODULE ((1UL<<31)|(1<<29)|(1<<25) |(18<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_LCD_EN_Pos ) |
| #define MODULE_APBCLK | ( | x | ) | ((x >>31) & 0x1) |
| #define MODULE_APBCLK_ENC | ( | x | ) | (((x) & 0x01) << 31) |
| #define MODULE_CLKDIV | ( | x | ) | ((x >>18) & 0x3) |
| #define MODULE_CLKDIV_ENC | ( | x | ) | (((x) & 0x03) << 18) |
| #define MODULE_CLKDIV_Msk | ( | x | ) | ((x >>10) & 0xff) |
| #define MODULE_CLKDIV_Msk_ENC | ( | x | ) | (((x) & 0xff) << 10) |
| #define MODULE_CLKDIV_Pos | ( | x | ) | ((x >>5 ) & 0x1f) |
| #define MODULE_CLKDIV_Pos_ENC | ( | x | ) | (((x) & 0x1f) << 5) |
| #define MODULE_CLKSEL | ( | x | ) | ((x >>29) & 0x3) |
| #define MODULE_CLKSEL_ENC | ( | x | ) | (((x) & 0x03) << 29) |
| #define MODULE_CLKSEL_Msk | ( | x | ) | ((x >>25) & 0xf) |
| #define MODULE_CLKSEL_Msk_ENC | ( | x | ) | (((x) & 0x0f) << 25) |
| #define MODULE_CLKSEL_Pos | ( | x | ) | ((x >>20) & 0x1f) |
| #define MODULE_CLKSEL_Pos_ENC | ( | x | ) | (((x) & 0x1f) << 20) |
| #define MODULE_IP_EN_Pos | ( | x | ) | ((x >>0 ) & 0x1f) |
| #define MODULE_IP_EN_Pos_ENC | ( | x | ) | (((x) & 0x1f) << 0) |
| #define NA MODULE_NoMsk |
| #define PWM0_CH01_MODULE ((1UL<<31)|(1<<29)|(3<<25) |( 4<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_PWM0_CH01_EN_Pos) |
| #define PWM0_CH23_MODULE ((1UL<<31)|(1<<29)|(3<<25) |( 6<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_PWM0_CH23_EN_Pos) |
| #define PWM1_CH01_MODULE ((1UL<<31)|(2<<29)|(3<<25) |( 4<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_PWM1_CH01_EN_Pos) |
| #define PWM1_CH23_MODULE ((1UL<<31)|(2<<29)|(3<<25) |( 6<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_PWM1_CH23_EN_Pos) |
| #define RTC_MODULE ((1UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_RTC_EN_Pos ) |
| #define SC0_MODULE ((1UL<<31)|(2<<29)|(3<<25) |(18<<20)|(0<<18)|(0xF<<10) |(28<<5)|CLK_APBCLK_SC0_EN_Pos ) |
| #define SC1_MODULE ((1UL<<31)|(2<<29)|(3<<25) |(18<<20)|(1<<18)|(0xF<<10) |( 0<<5)|CLK_APBCLK_SC1_EN_Pos ) |
| #define SC2_MODULE ((1UL<<31)|(2<<29)|(3<<25) |(18<<20)|(1<<18)|(0xF<<10) |( 4<<5)|CLK_APBCLK_SC2_EN_Pos ) |
| #define SPI0_MODULE ((1UL<<31)|(2<<29)|(1<<25) |(20<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_SPI0_EN_Pos ) |
| #define SPI1_MODULE ((1UL<<31)|(2<<29)|(1<<25) |(21<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_SPI1_EN_Pos ) |
| #define SPI2_MODULE ((1UL<<31)|(2<<29)|(1<<25) |(22<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_SPI2_EN_Pos ) |
| #define SRAM_MODULE ((0UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(1<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_SRAM_EN_Pos ) |
| #define TICK_MODULE ((0UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(1<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_TICK_EN_Pos ) |
| #define TMR0_MODULE ((1UL<<31)|(1<<29)|(7<<25) |( 8<<20)|(1<<18)|(0xF<<10) |( 8<<5)|CLK_APBCLK_TMR0_EN_Pos ) |
| #define TMR1_MODULE ((1UL<<31)|(1<<29)|(7<<25) |(12<<20)|(1<<18)|(0xF<<10) |(12<<5)|CLK_APBCLK_TMR1_EN_Pos ) |
| #define TMR2_MODULE ((1UL<<31)|(2<<29)|(7<<25) |( 8<<20)|(1<<18)|(0xF<<10) |(16<<5)|CLK_APBCLK_TMR2_EN_Pos ) |
| #define TMR3_MODULE ((1UL<<31)|(2<<29)|(7<<25) |(12<<20)|(1<<18)|(0xF<<10) |(20<<5)|CLK_APBCLK_TMR3_EN_Pos ) |
| #define UART0_MODULE ((1UL<<31)|(1<<29)|(3<<25) |( 0<<20)|(0<<18)|(0xF<<10) |( 8<<5)|CLK_APBCLK_UART0_EN_Pos ) |
| #define UART1_MODULE ((1UL<<31)|(1<<29)|(3<<25) |( 0<<20)|(0<<18)|(0xF<<10) |( 8<<5)|CLK_APBCLK_UART1_EN_Pos ) |
| #define USBD_MODULE ((1UL<<31)|(1<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(0xF<<10) |( 4<<5)|CLK_APBCLK_USBD_EN_Pos ) |
1.8.15