![]() |
Nano100BN Series BSP
V3.03.002
The Board Support Package for Nano100BN Series
|
Macros | |
| #define | ADC_CH_0_MASK (1UL << 0) |
| #define | ADC_CH_1_MASK (1UL << 1) |
| #define | ADC_CH_2_MASK (1UL << 2) |
| #define | ADC_CH_3_MASK (1UL << 3) |
| #define | ADC_CH_4_MASK (1UL << 4) |
| #define | ADC_CH_5_MASK (1UL << 5) |
| #define | ADC_CH_6_MASK (1UL << 6) |
| #define | ADC_CH_7_MASK (1UL << 7) |
| #define | ADC_CH_8_MASK (1UL << 8) |
| #define | ADC_CH_9_MASK (1UL << 9) |
| #define | ADC_CH_10_MASK (1UL << 10) |
| #define | ADC_CH_11_MASK (1UL << 11) |
| #define | ADC_CH_12_MASK (1UL << 12) |
| #define | ADC_CH_13_MASK (1UL << 13) |
| #define | ADC_CH_14_MASK (1UL << 14) |
| #define | ADC_CH_15_MASK (1UL << 15) |
| #define | ADC_CH_16_MASK (1UL << 16) |
| #define | ADC_CH_17_MASK (1UL << 17) |
| #define | ADC_CHEN_Msk (0x3FFFF) |
| #define | ADC_PDMADATA_AD_PDMA_Msk (0xFFF) |
| #define | ADC_CMP_LESS_THAN (0UL) |
| #define | ADC_CMP_GREATER_OR_EQUAL_TO (ADC_CMPR_CMPCOND_Msk) |
| #define | ADC_TRIGGER_BY_EXT_PIN (0UL) |
| #define | ADC_LOW_LEVEL_TRIGGER (0UL << ADC_CR_TRGCOND_Pos) |
| #define | ADC_HIGH_LEVEL_TRIGGER (1UL << ADC_CR_TRGCOND_Pos) |
| #define | ADC_FALLING_EDGE_TRIGGER (2UL << ADC_CR_TRGCOND_Pos) |
| #define | ADC_RISING_EDGE_TRIGGER (3UL << ADC_CR_TRGCOND_Pos) |
| #define | ADC_ADF_INT (ADC_SR_ADF_Msk) |
| #define | ADC_CMP0_INT (ADC_SR_CMPF0_Msk) |
| #define | ADC_CMP1_INT (ADC_SR_CMPF1_Msk) |
| #define | ADC_INPUT_MODE_SINGLE_END (0UL << ADC_CR_DIFF_Pos) |
| #define | ADC_INPUT_MODE_DIFFERENTIAL (1UL << ADC_CR_DIFF_Pos) |
| #define | ADC_OPERATION_MODE_SINGLE (0UL << ADC_CR_ADMD_Pos) |
| #define | ADC_OPERATION_MODE_SINGLE_CYCLE (2UL << ADC_CR_ADMD_Pos) |
| #define | ADC_OPERATION_MODE_CONTINUOUS (3UL << ADC_CR_ADMD_Pos) |
| #define | ADC_DMODE_OUT_FORMAT_UNSIGNED (0UL << ADC_CR_DIFF_Pos) |
| #define | ADC_DMODE_OUT_FORMAT_2COMPLEMENT (1UL << ADC_CR_DIFF_Pos) |
| #define | ADC_RESSEL_6_BIT (0UL << ADC_CR_RESSEL_Pos) |
| #define | ADC_RESSEL_8_BIT (1UL << ADC_CR_RESSEL_Pos) |
| #define | ADC_RESSEL_10_BIT (2UL << ADC_CR_RESSEL_Pos) |
| #define | ADC_RESSEL_12_BIT (3UL << ADC_CR_RESSEL_Pos) |
| #define | ADC_REFSEL_POWER (0UL << ADC_CR_REFSEL_Pos) |
| #define | ADC_REFSEL_INT_VREF (1UL << ADC_CR_REFSEL_Pos) |
| #define | ADC_REFSEL_VREF (2UL << ADC_CR_REFSEL_Pos) |
| #define ADC_ADF_INT (ADC_SR_ADF_Msk) |
| #define ADC_CMP0_INT (ADC_SR_CMPF0_Msk) |
| #define ADC_CMP1_INT (ADC_SR_CMPF1_Msk) |
| #define ADC_CMP_GREATER_OR_EQUAL_TO (ADC_CMPR_CMPCOND_Msk) |
| #define ADC_CMP_LESS_THAN (0UL) |
| #define ADC_DMODE_OUT_FORMAT_2COMPLEMENT (1UL << ADC_CR_DIFF_Pos) |
| #define ADC_DMODE_OUT_FORMAT_UNSIGNED (0UL << ADC_CR_DIFF_Pos) |
| #define ADC_FALLING_EDGE_TRIGGER (2UL << ADC_CR_TRGCOND_Pos) |
| #define ADC_HIGH_LEVEL_TRIGGER (1UL << ADC_CR_TRGCOND_Pos) |
| #define ADC_INPUT_MODE_DIFFERENTIAL (1UL << ADC_CR_DIFF_Pos) |
| #define ADC_INPUT_MODE_SINGLE_END (0UL << ADC_CR_DIFF_Pos) |
| #define ADC_LOW_LEVEL_TRIGGER (0UL << ADC_CR_TRGCOND_Pos) |
| #define ADC_OPERATION_MODE_CONTINUOUS (3UL << ADC_CR_ADMD_Pos) |
| #define ADC_OPERATION_MODE_SINGLE (0UL << ADC_CR_ADMD_Pos) |
| #define ADC_OPERATION_MODE_SINGLE_CYCLE (2UL << ADC_CR_ADMD_Pos) |
| #define ADC_PDMADATA_AD_PDMA_Msk (0xFFF) |
| #define ADC_REFSEL_INT_VREF (1UL << ADC_CR_REFSEL_Pos) |
| #define ADC_REFSEL_POWER (0UL << ADC_CR_REFSEL_Pos) |
| #define ADC_REFSEL_VREF (2UL << ADC_CR_REFSEL_Pos) |
| #define ADC_RESSEL_10_BIT (2UL << ADC_CR_RESSEL_Pos) |
| #define ADC_RESSEL_12_BIT (3UL << ADC_CR_RESSEL_Pos) |
| #define ADC_RESSEL_6_BIT (0UL << ADC_CR_RESSEL_Pos) |
| #define ADC_RESSEL_8_BIT (1UL << ADC_CR_RESSEL_Pos) |
| #define ADC_RISING_EDGE_TRIGGER (3UL << ADC_CR_TRGCOND_Pos) |
1.8.15