| Nano100BN Series BSP V3.03.002 The Board Support Package for Nano100BN Series

Data Fields
I2C_T Struct Reference

`#include <Nano100Series.h>`

## Data Fields
__IO uint32_t | CON
__IO uint32_t | INTSTS
__I uint32_t | STATUS
__IO uint32_t | DIV
__IO uint32_t | TOUT
__IO uint32_t | DATA
__IO uint32_t | SADDR0
__IO uint32_t | SADDR1
uint32_t | RESERVE0 [2]
__IO uint32_t | SAMASK0
__IO uint32_t | SAMASK1
uint32_t | RESERVE1 [4]
__IO uint32_t | WKUPCON
__IO uint32_t | WKUPSTS

## Detailed Description

    @addtogroup I2C Inter-IC Bus Controller(I2C)
    Memory Mapped Structure for I2C Controller

Definition at line 4214 of file Nano100Series.h.

## Field Documentation

## ◆ CON

__IO uint32_t I2C_T::CON

# CON

## Offset: 0x00 I2C Control Register

Bits | Field | Descriptions
--- | --- | ---
[0] | IPEN | I2C Function Enable
|  | When this bit is set to 1, the I2C serial function is enabled.
|  | 0 = I2C function Disabled.
|  | 1 = I2C function Enabled.
[1] | ACK | Assert Acknowledge Control Bit
|  | 0 =: When this bit is set to 0 prior to address or data received, a Not acknowledged (high level to SDA) will be returned during the acknowledge clock pulse.
|  | 1 = When this bit is set to 1 prior to address or data received, an acknowledged will be returned during the acknowledge clock pulse on the SCL line when.
|  | a. A slave is acknowledging the address sent from master
|  | b. The receiver devices are acknowledging the data sent by transmitter.
[2] | STOP | I2C STOP Control Bit
|  | In Master mode, set this bit to 1 to transmit a STOP condition to bus then the controller will check the bus condition if a STOP condition is detected and this bit will be cleared by hardware automatically.
|  | In Slave mode, set this bit to 1 to reset the controller to the defined "not addressed" Slave mode.
|  | This means it is NO LONGER in the slave receiver mode to receive data from the master transmit device.
|  | 0 = Will be cleared by hardware automatically if a STOP condition is detected.
|  | 1 = Sends a STOP condition to bus in Master mode or reset the controller to "not addressed" in Slave mode.
[3] | START | I2C START Command
|  | Setting this bit to 1 to enter Master mode, the device sends a START or repeat START condition to bus when the bus is free and it will be cleared to 0 after the START command is active and the STATUS has been updated.
|  | 0 = After START or repeat START is active.
|  | 1 = Sends a START or repeat START condition to bus.
[4] | I2C_STS | I2C Status
|  | When a new state is present in the I2CSTATUS register, this bit will be set automatically, and if the INTEN bit is set, the I2C interrupt is requested.
|  | It must be cleared by software by writing one to this bit and the I2C protocol function will go ahead until the STOP is active or the IPEN is disabled.
|  | 0 = I2C's Status disabled and the I2C protocol function will go ahead.
|  | 1 = I2C's Status active.
[7] | INTEN | Interrupt Enable
|  | 0 = I2C interrupt Disabled.
|  | 1 = I2C interrupt Enabled.

Definition at line 4253 of file Nano100Series.h.

## ◆ DATA

__IO uint32_t I2C_T::DATA

# DATA

## Offset: 0x14 I2C DATA Register

Bits | Field | Descriptions
--- | --- | ---
[7:0] | DATA | I2C Data Register
|  | The DATA contains a byte of serial data to be transmitted or a byte which has just been received.
|  | The user can read from or write to this 8-bit I2CDATA register directly while it is not in the process of shifting a byte.
|  | This occurs when the serial interrupt flag is set.
|  | Data in DATA remains stable as long as I2C_STS bit is set.
|  | While data is being shifted out, data on the bus is simultaneously being shifted in; The DATA always contains the last data byte present on the bus.
|  | Thus, in the event of arbitration lost, the transition from master transmitter to slave receiver is made with the correct data in DATA.
|  | DATA and the acknowledge bit form a 9-bit shift register, the acknowledge bit is controlled by the device hardware and cannot be accessed by the user.
|  | Serial data is shifted through the acknowledge bit into DATA on the rising edges of serial clock pulses on the SCL line.
|  | When a byte has been shifted into DATA, the serial data is available in DATA, and the acknowledge bit (ACK or NACK) is returned by the control logic during the ninth clock pulse.

Definition at line 4343 of file Nano100Series.h.

## ◆ DIV

__IO uint32_t I2C_T::DIV

# DIV

## Offset: 0x0C I2C clock divided Register

Bits | Field | Descriptions
--- | --- | ---
[7:0] | CLK_DIV | I2C Clock Divider Control Register
|  | The I2C clock rate bits: Data Baud Rate of I2C = PCLK /( 4 x ( CLK_DIV + 1)).
|  | Note: the minimum value of CLK_DIV is 4.

Definition at line 4304 of file Nano100Series.h.

## ◆ INTSTS

__IO uint32_t I2C_T::INTSTS

# INTSTS

## Offset: 0x04 I2C Interrupt Status Register

Bits | Field | Descriptions
--- | --- | ---
[0] | INTSTS | I2C STATUS's Interrupt Status
|  | When a new state is present in the I2CSTATUS register, this bit will be set automatically, and if INTEN bit is set, the I2C interrupt is requested.
|  | Software can write 1 to cleat this bit.
[1] | TIF | Time-Out Status
|  | 0 = No Time-out flag. Software can cleat this flag.
|  | 1 = Time-Out flag active and it is set by hardware. It can interrupt CPU when INTEN bit is set.

Definition at line 4269 of file Nano100Series.h.

## ◆ RESERVE0

uint32_t I2C_T::RESERVE0[2]

Definition at line 4386 of file Nano100Series.h.

## ◆ RESERVE1

uint32_t I2C_T::RESERVE1[4]

Definition at line 4420 of file Nano100Series.h.

## ◆ SADDR0

__IO uint32_t I2C_T::SADDR0

# SADDR0

## Offset: 0x18 I2C Slave address Register0

Bits | Field | Descriptions
--- | --- | ---
[0] | GCALL | General Call Function
|  | The I2C controller supports the "General Call" function.
|  | If the GCALL bit is set, the controller will respond to General Call address (00H).
|  | When GCALL bit is set, the controller is in Slave mode, it can receive the general call address by 00H after Master send general call address to the I2C bus, then it will follow status of GCALL mode.
|  | If it is in Master mode, the ACK bit must be cleared when it will send general call address of 00H to I2C bus.
|  | 0 = General Call Function Disabled.
|  | 1 = General Call Function Enabled.
[7:1] | SADDR | I2C Salve Address Register
|  | The content of this register is irrelevant when the device is in Master mode.
|  | In the Slave mode, the seven most significant bits must be loaded with the device's own address.
|  | The device will react if either of the address is matched.

Definition at line 4364 of file Nano100Series.h.

## ◆ SADDR1

__IO uint32_t I2C_T::SADDR1

# SADDR1

## Offset: 0x1C I2C Slave address Register1

Bits | Field | Descriptions
--- | --- | ---
[0] | GCALL | General Call Function
|  | The I2C controller supports the "General Call" function.
|  | If the GCALL bit is set, the controller will respond to General Call address (00H).
|  | When GCALL bit is set, the controller is in Slave mode, it can receive the general call address by 00H after Master send general call address to the I2C bus, then it will follow status of GCALL mode.
|  | If it is in Master mode, the ACK bit must be cleared when it will send general call address of 00H to I2C bus.
|  | 0 = General Call Function Disabled.
|  | 1 = General Call Function Enabled.
[7:1] | SADDR | I2C Salve Address Register
|  | The content of this register is irrelevant when the device is in Master mode.
|  | In the Slave mode, the seven most significant bits must be loaded with the device's own address.
|  | The device will react if either of the address is matched.

Definition at line 4385 of file Nano100Series.h.

## ◆ SAMASK0

__IO uint32_t I2C_T::SAMASK0

# SAMASK0

## Offset: 0x28 I2C Slave address Mask Register0

Bits | Field | Descriptions
--- | --- | ---
[7:1] | SAMASK | I2C Slave Address Mask Register
|  | 0 = Mask disable (the received corresponding register bit should be exact the same as address register.).
|  | 1 = Mask enable (the received corresponding address bit is don't care.).
|  | I2C bus controllers support multiple address recognition with two address mask registers.
|  | When the bit in the address mask register is set to b'1, it means the received corresponding address bit is don't-care.
|  | If the bit is set to b'0, that means the received corresponding register bit should be exact the same as address register.

Definition at line 4403 of file Nano100Series.h.

## ◆ SAMASK1

__IO uint32_t I2C_T::SAMASK1

# SAMASK1

## Offset: 0x2C I2C Slave address Mask Register1

Bits | Field | Descriptions
--- | --- | ---
[7:1] | SAMASK | I2C Slave Address Mask Register
|  | 0 = Mask disable (the received corresponding register bit should be exact the same as address register.).
|  | 1 = Mask enable (the received corresponding address bit is don't care.).
|  | I2C bus controllers support multiple address recognition with two address mask registers.
|  | When the bit in the address mask register is set to b'1, it means the received corresponding address bit is don't-care.
|  | If the bit is set to b'0, that means the received corresponding register bit should be exact the same as address register.

Definition at line 4419 of file Nano100Series.h.

## ◆ STATUS

__I uint32_t I2C_T::STATUS

# STATUS

## Offset: 0x08 I2C Status Register

Bits | Field | Descriptions
--- | --- | ---
[7:0] | STATUS | I2C Status Register
|  | This is a read only register.
|  | The three least significant bits are always 0.
|  | The five most significant bits contain the status code.
|  | When each of these states is entered, a status interrupt and I2C_STS are requested (I2C_STS = 1 and STAINTSTS = 1).
|  | A valid status code is present in STATUS one machine cycle after I2C_STS is set by hardware and is still present one machine cycle after I2C_STS has been reset by software.
|  | In addition, states 00H stands for a 'Bus Error'.
|  | A 'Bus Error' occurs when a START or STOP condition is present at an illegal position in the formation frame.
|  | Example of illegal position: a data byte or an acknowledge bit is present during the serial transfer of an address byte.
|  | To recover I2C from bus error, STOP should be set and I2C_STS should be cleared to enter not addressed Slave mode.
|  | Then clear STOP to release the bus and to wait new communication.
|  | I2C bus can not recognize stop condition during this action when bus error occurs.

Definition at line 4291 of file Nano100Series.h.

## ◆ TOUT

__IO uint32_t I2C_T::TOUT

# TOUT

## Offset: 0x10 I2C Time-out control Register

Bits | Field | Descriptions
--- | --- | ---
[0] | TOUTEN | Time-Out Counter Enable/Disable
|  | 0 = Disabled.
|  | 1 = Enabled.
|  | When set this bit to enable, the 14 bits time-out counter will start counting when STAINTSTS is cleared.
|  | Setting flag STAINTSTS to high or the falling edge of I2C clock or stop signal will reset counter and re-start up counting after STAINTSTS is cleared.
[1] | DIV4 | Time-Out Counter Input Clock Divider By 4
|  | 0 = Disabled.
|  | 1 = Enabled.
|  | When this bit is set enabled, the Time-Out period is prolonging 4 times.

Definition at line 4323 of file Nano100Series.h.

## ◆ WKUPCON

__IO uint32_t I2C_T::WKUPCON

# WKUPCON

## Offset: 0x40 I2C Wake-up Control Register

Bits | Field | Descriptions
--- | --- | ---
[0] | WKUPEN | I2C Wake-Up Function Enable
|  | 0 = I2C wake-up function Disabled.
|  | 1 = I2C wake-up function Enabled.

Definition at line 4434 of file Nano100Series.h.

## ◆ WKUPSTS

__IO uint32_t I2C_T::WKUPSTS

# WKUPSTS

## Offset: 0x44 I2C Wake-up Status Register

Bits | Field | Descriptions
--- | --- | ---
[0] | WKUPIF | Wake-Up Interrupt Flag
|  | 0 = Wake-up flag inactive.
|  | 1 = Wake-up flag active.
|  | Software can write 1 to clear this flag

Definition at line 4448 of file Nano100Series.h.

The documentation for this struct was generated from the following file:

- C:/Users/yachen/workzone/bsp/nano100bbsp/Library/Device/Nuvoton/Nano100Series/Include/Nano100Series.h