| Nano100BN Series BSP V3.03.002 The Board Support Package for Nano100BN Series

spi.c
Go to the documentation of this file.
1 /****************************************************************************/
13 #include "Nano100Series.h"
14
47 uint32_t SPI_Open(SPI_T *spi,
48 uint32_t u32MasterSlave,
49 uint32_t u32SPIMode,
50 uint32_t u32DataWidth,
51 uint32_t u32BusClock)
52 {
53 if(u32DataWidth == 32)
54 u32DataWidth = 0;
55
56 spi->CTL = u32MasterSlave | (u32DataWidth << SPI_CTL_TX_BIT_LEN_Pos) | (u32SPIMode);
57
58 return ( SPI_SetBusClock(spi, u32BusClock) );
59 }
60
66 void SPI_Close(SPI_T *spi)
67 {
68 /* Reset SPI */
69 if(spi == SPI0)
70 {
71 SYS->IPRST_CTL2 |= SYS_IPRST_CTL2_SPI0_RST_Msk;
72 SYS->IPRST_CTL2 &= ~SYS_IPRST_CTL2_SPI0_RST_Msk;
73 }
74 else if(spi == SPI1)
75 {
76 SYS->IPRST_CTL2 |= SYS_IPRST_CTL2_SPI1_RST_Msk;
77 SYS->IPRST_CTL2 &= ~SYS_IPRST_CTL2_SPI1_RST_Msk;
78 }
79 else
80 {
81 SYS->IPRST_CTL2 |= SYS_IPRST_CTL2_SPI2_RST_Msk;
82 SYS->IPRST_CTL2 &= ~SYS_IPRST_CTL2_SPI2_RST_Msk;
83 }
84 }
85
91 void SPI_ClearRxFIFO(SPI_T *spi)
92 {
93 spi->FFCTL |= SPI_FFCTL_RX_CLR_Msk;
94 }
95
101 void SPI_ClearTxFIFO(SPI_T *spi)
102 {
103 spi->FFCTL |= SPI_FFCTL_TX_CLR_Msk;
104 }
105
111 void SPI_DisableAutoSS(SPI_T *spi)
112 {
113 spi->SSR &= ~SPI_SSR_AUTOSS_Msk;
114 }
115
127 void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel)
128 {
129 spi->SSR = (spi->SSR & ~(SPI_SSR_SS_LVL_Msk | SPI_SSR_SSR_Msk)) | (u32SSPinMask | u32ActiveLevel) | SPI_SSR_AUTOSS_Msk;
130 }
131
138 uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock)
139 {
140 uint32_t u32ClkSrc, u32Div = 0;
141
142 if(spi == SPI0)
143 {
144 if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0_S_Msk) == CLK_CLKSEL2_SPI0_S_HCLK)
145 u32ClkSrc = CLK_GetHCLKFreq();
146 else
147 u32ClkSrc = CLK_GetPLLClockFreq();
148 }
149 else if(spi == SPI1)
150 {
151 if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1_S_Msk) == CLK_CLKSEL2_SPI1_S_HCLK)
152 u32ClkSrc = CLK_GetHCLKFreq();
153 else
154 u32ClkSrc = CLK_GetPLLClockFreq();
155 }
156 else
157 {
158 if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2_S_Msk) == CLK_CLKSEL2_SPI2_S_HCLK)
159 u32ClkSrc = CLK_GetHCLKFreq();
160 else
161 u32ClkSrc = CLK_GetPLLClockFreq();
162 }
163
164 if(u32BusClock > u32ClkSrc)
165 u32BusClock = u32ClkSrc;
166
167 if(u32BusClock != 0 )
168 {
169 u32Div = (u32ClkSrc / u32BusClock) - 1;
170 if(u32Div > SPI_CLKDIV_DIVIDER1_Msk)
171 u32Div = SPI_CLKDIV_DIVIDER1_Msk;
172 }
173 else
174 u32Div = 0;
175
176 spi->CLKDIV = (spi->CLKDIV & ~SPI_CLKDIV_DIVIDER1_Msk) | u32Div;
177
178 return ( u32ClkSrc / (u32Div+1) );
179 }
180
188 void SPI_EnableFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold)
189 {
190 spi->FFCTL = (spi->FFCTL & ~(SPI_FFCTL_TX_THRESHOLD_Msk | SPI_FFCTL_RX_THRESHOLD_Msk) |
191 (u32TxThreshold << SPI_FFCTL_TX_THRESHOLD_Pos) |
192 (u32RxThreshold << SPI_FFCTL_RX_THRESHOLD_Pos));
193
194 spi->CTL |= SPI_CTL_FIFOM_Msk;
195 }
196
202 void SPI_DisableFIFO(SPI_T *spi)
203 {
204 spi->CTL &= ~SPI_CTL_FIFOM_Msk;
205 }
206
212 uint32_t SPI_GetBusClock(SPI_T *spi)
213 {
214 uint32_t u32Div;
215 uint32_t u32ClkSrc;
216
217 if(spi == SPI0)
218 {
219 if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0_S_Msk) == CLK_CLKSEL2_SPI0_S_HCLK)
220 u32ClkSrc = CLK_GetHCLKFreq();
221 else
222 u32ClkSrc = CLK_GetPLLClockFreq();
223 }
224 else if(spi == SPI1)
225 {
226 if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1_S_Msk) == CLK_CLKSEL2_SPI1_S_HCLK)
227 u32ClkSrc = CLK_GetHCLKFreq();
228 else
229 u32ClkSrc = CLK_GetPLLClockFreq();
230 }
231 else
232 {
233 if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2_S_Msk) == CLK_CLKSEL2_SPI2_S_HCLK)
234 u32ClkSrc = CLK_GetHCLKFreq();
235 else
236 u32ClkSrc = CLK_GetPLLClockFreq();
237 }
238
239 u32Div = spi->CLKDIV & SPI_CLKDIV_DIVIDER1_Msk;
240 return (u32ClkSrc / (u32Div + 1));
241 }
242
257 void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask)
258 {
259 if((u32Mask & SPI_IE_MASK) == SPI_IE_MASK)
260 spi->CTL |= SPI_CTL_INTEN_Msk;
261
262 if((u32Mask & SPI_SSTA_INTEN_MASK) == SPI_SSTA_INTEN_MASK)
263 spi->SSR |= SPI_SSR_SSTA_INTEN_Msk;
264
265 if((u32Mask & SPI_FIFO_TX_INTEN_MASK) == SPI_FIFO_TX_INTEN_MASK)
266 spi->FFCTL |= SPI_FFCTL_TX_INTEN_Msk;
267
268 if((u32Mask & SPI_FIFO_RX_INTEN_MASK) == SPI_FIFO_RX_INTEN_MASK)
269 spi->FFCTL |= SPI_FFCTL_RX_INTEN_Msk;
270
271 if((u32Mask & SPI_FIFO_RXOVR_INTEN_MASK) == SPI_FIFO_RXOVR_INTEN_MASK)
272 spi->FFCTL |= SPI_FFCTL_RXOVR_INTEN_Msk;
273
274 if((u32Mask & SPI_FIFO_TIMEOUT_INTEN_MASK) == SPI_FIFO_TIMEOUT_INTEN_MASK)
275 spi->FFCTL |= SPI_FFCTL_TIMEOUT_EN_Msk;
276 }
277
292 void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask)
293 {
294 if((u32Mask & SPI_IE_MASK) == SPI_IE_MASK)
295 spi->CTL &= ~SPI_CTL_INTEN_Msk;
296
297 if((u32Mask & SPI_SSTA_INTEN_MASK) == SPI_SSTA_INTEN_MASK)
298 spi->SSR &= ~SPI_SSR_SSTA_INTEN_Msk;
299
300 if((u32Mask & SPI_FIFO_TX_INTEN_MASK) == SPI_FIFO_TX_INTEN_MASK)
301 spi->FFCTL &= ~SPI_FFCTL_TX_INTEN_Msk;
302
303 if((u32Mask & SPI_FIFO_RX_INTEN_MASK) == SPI_FIFO_RX_INTEN_MASK)
304 spi->FFCTL &= ~SPI_FFCTL_RX_INTEN_Msk;
305
306 if((u32Mask & SPI_FIFO_RXOVR_INTEN_MASK) == SPI_FIFO_RXOVR_INTEN_MASK)
307 spi->FFCTL &= ~SPI_FFCTL_RXOVR_INTEN_Msk;
308
309 if((u32Mask & SPI_FIFO_TIMEOUT_INTEN_MASK) == SPI_FIFO_TIMEOUT_INTEN_MASK)
310 spi->FFCTL &= ~SPI_FFCTL_TIMEOUT_EN_Msk;
311 }
312
318 void SPI_EnableWakeup(SPI_T *spi)
319 {
320 spi->CTL |= SPI_CTL_WKEUP_EN_Msk;
321 }
322
328 void SPI_DisableWakeup(SPI_T *spi)
329 {
330 spi->CTL &= ~SPI_CTL_WKEUP_EN_Msk;
331 }
332 /* end of group NANO100_SPI_EXPORTED_FUNCTIONS */
334 /* end of group NANO100_SPI_Driver */
336 /* end of group NANO100_Device_Driver */
338
339 /*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
SPI_CTL_INTEN_Msk
#define SPI_CTL_INTEN_Msk
Definition: Nano100Series.h:9592
SPI_SSTA_INTEN_MASK
#define SPI_SSTA_INTEN_MASK
Definition: spi.h:51
SPI_DisableAutoSS
void SPI_DisableAutoSS(SPI_T *spi)
Disable the automatic slave select function.
Definition: spi.c:111
SPI_CTL_TX_BIT_LEN_Pos
#define SPI_CTL_TX_BIT_LEN_Pos
Definition: Nano100Series.h:9579
SPI_FFCTL_TX_THRESHOLD_Msk
#define SPI_FFCTL_TX_THRESHOLD_Msk
Definition: Nano100Series.h:9733
SPI_SetBusClock
uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock)
Set the SPI bus clock. Only available in Master mode.
Definition: spi.c:138
SPI_CTL_FIFOM_Msk
#define SPI_CTL_FIFOM_Msk
Definition: Nano100Series.h:9601
SPI_SSR_SS_LVL_Msk
#define SPI_SSR_SS_LVL_Msk
Definition: Nano100Series.h:9667
SPI_T::SSR
__IO uint32_t SSR
Definition: Nano100Series.h:9417
SPI0
#define SPI0
Pointer to SPI0 register structure.
Definition: Nano100Series.h:11676
CLK
#define CLK
Pointer to CLK register structure.
Definition: Nano100Series.h:11693
CLK_GetHCLKFreq
uint32_t CLK_GetHCLKFreq(void)
This function get HCLK frequency. The frequency unit is Hz.
Definition: clk.c:119
SPI1
#define SPI1
Pointer to SPI1 register structure.
Definition: Nano100Series.h:11677
SPI_FFCTL_TX_CLR_Msk
#define SPI_FFCTL_TX_CLR_Msk
Definition: Nano100Series.h:9715
SPI_EnableInt
void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask)
Enable FIFO related interrupts specified by u32Mask parameter.
Definition: spi.c:257
SPI_FFCTL_RXOVR_INTEN_Msk
#define SPI_FFCTL_RXOVR_INTEN_Msk
Definition: Nano100Series.h:9724
Nano100Series.h
Nano100 series peripheral access layer header file. This file contains all the peripheral register's ...
SPI_ClearRxFIFO
void SPI_ClearRxFIFO(SPI_T *spi)
Clear Rx FIFO buffer.
Definition: spi.c:91
CLK_GetPLLClockFreq
uint32_t CLK_GetPLLClockFreq(void)
This function get PLL frequency. The frequency unit is Hz.
Definition: clk.c:142
SPI_T
Definition: Nano100Series.h:9190
SPI_FIFO_RX_INTEN_MASK
#define SPI_FIFO_RX_INTEN_MASK
Definition: spi.h:53
CLK_CLKSEL2_SPI1_S_Msk
#define CLK_CLKSEL2_SPI1_S_Msk
Definition: Nano100Series.h:1408
SYS_IPRST_CTL2_SPI0_RST_Msk
#define SYS_IPRST_CTL2_SPI0_RST_Msk
Definition: Nano100Series.h:3008
SPI_FFCTL_TX_INTEN_Msk
#define SPI_FFCTL_TX_INTEN_Msk
Definition: Nano100Series.h:9721
CLK_CLKSEL2_SPI1_S_HCLK
#define CLK_CLKSEL2_SPI1_S_HCLK
Definition: clk.h:147
SPI_Close
void SPI_Close(SPI_T *spi)
Reset SPI module and disable SPI peripheral clock.
Definition: spi.c:66
SPI_T::CTL
__IO uint32_t CTL
Definition: Nano100Series.h:9291
SPI_CLKDIV_DIVIDER1_Msk
#define SPI_CLKDIV_DIVIDER1_Msk
Definition: Nano100Series.h:9658
SPI_FFCTL_RX_INTEN_Msk
#define SPI_FFCTL_RX_INTEN_Msk
Definition: Nano100Series.h:9718
SPI_FFCTL_TIMEOUT_EN_Msk
#define SPI_FFCTL_TIMEOUT_EN_Msk
Definition: Nano100Series.h:9727
CLK_CLKSEL2_SPI0_S_HCLK
#define CLK_CLKSEL2_SPI0_S_HCLK
Definition: clk.h:150
SPI_DisableInt
void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask)
Disable FIFO related interrupts specified by u32Mask parameter.
Definition: spi.c:292
SPI_GetBusClock
uint32_t SPI_GetBusClock(SPI_T *spi)
Get the actual frequency of SPI bus clock. Only available in Master mode.
Definition: spi.c:212
SYS_IPRST_CTL2_SPI1_RST_Msk
#define SYS_IPRST_CTL2_SPI1_RST_Msk
Definition: Nano100Series.h:3011
SPI_DisableFIFO
void SPI_DisableFIFO(SPI_T *spi)
Disable FIFO mode.
Definition: spi.c:202
SPI_ClearTxFIFO
void SPI_ClearTxFIFO(SPI_T *spi)
Clear Tx FIFO buffer.
Definition: spi.c:101
SPI_FIFO_TIMEOUT_INTEN_MASK
#define SPI_FIFO_TIMEOUT_INTEN_MASK
Definition: spi.h:55
SPI_DisableWakeup
void SPI_DisableWakeup(SPI_T *spi)
Disable wake-up function.
Definition: spi.c:328
SPI_IE_MASK
#define SPI_IE_MASK
Definition: spi.h:50
SPI_FFCTL_RX_THRESHOLD_Msk
#define SPI_FFCTL_RX_THRESHOLD_Msk
Definition: Nano100Series.h:9730
SPI_EnableAutoSS
void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel)
Enable the automatic slave select function. Only available in Master mode.
Definition: spi.c:127
CLK_CLKSEL2_SPI0_S_Msk
#define CLK_CLKSEL2_SPI0_S_Msk
Definition: Nano100Series.h:1405
SPI_Open
uint32_t SPI_Open(SPI_T *spi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock)
This function make SPI module be ready to transfer. By default, the SPI transfer sequence is MSB firs...
Definition: spi.c:47
SPI_FIFO_RXOVR_INTEN_MASK
#define SPI_FIFO_RXOVR_INTEN_MASK
Definition: spi.h:54
SPI_SSR_AUTOSS_Msk
#define SPI_SSR_AUTOSS_Msk
Definition: Nano100Series.h:9670
SPI_FFCTL_TX_THRESHOLD_Pos
#define SPI_FFCTL_TX_THRESHOLD_Pos
Definition: Nano100Series.h:9732
SPI_T::CLKDIV
__IO uint32_t CLKDIV
Definition: Nano100Series.h:9364
SPI_SSR_SSR_Msk
#define SPI_SSR_SSR_Msk
Definition: Nano100Series.h:9664
SPI_T::FFCTL
__IO uint32_t FFCTL
Definition: Nano100Series.h:9562
SPI_SSR_SSTA_INTEN_Msk
#define SPI_SSR_SSTA_INTEN_Msk
Definition: Nano100Series.h:9682
SPI_EnableWakeup
void SPI_EnableWakeup(SPI_T *spi)
Enable wake-up function.
Definition: spi.c:318
SPI_FFCTL_RX_CLR_Msk
#define SPI_FFCTL_RX_CLR_Msk
Definition: Nano100Series.h:9712
SPI_FFCTL_RX_THRESHOLD_Pos
#define SPI_FFCTL_RX_THRESHOLD_Pos
Definition: Nano100Series.h:9729
CLK_CLKSEL2_SPI2_S_Msk
#define CLK_CLKSEL2_SPI2_S_Msk
Definition: Nano100Series.h:1411
SPI_EnableFIFO
void SPI_EnableFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold)
Enable FIFO mode with user-specified Tx FIFO threshold and Rx FIFO threshold configurations.
Definition: spi.c:188
SYS_IPRST_CTL2_SPI2_RST_Msk
#define SYS_IPRST_CTL2_SPI2_RST_Msk
Definition: Nano100Series.h:3014
SPI_CTL_WKEUP_EN_Msk
#define SPI_CTL_WKEUP_EN_Msk
Definition: Nano100Series.h:9616
SPI_FIFO_TX_INTEN_MASK
#define SPI_FIFO_TX_INTEN_MASK
Definition: spi.h:52
CLK_CLKSEL2_SPI2_S_HCLK
#define CLK_CLKSEL2_SPI2_S_HCLK
Definition: clk.h:144
SYS
#define SYS
Pointer to SYS register structure.
Definition: Nano100Series.h:11692