Nano100BN Series BSP  V3.03.002
The Board Support Package for Nano100BN Series
Data Fields
RTC_T Struct Reference

#include <Nano100Series.h>

Data Fields

__IO uint32_t INIR
 
__IO uint32_t AER
 
__IO uint32_t FCR
 
__IO uint32_t TLR
 
__IO uint32_t CLR
 
__IO uint32_t TSSR
 
__IO uint32_t DWR
 
__IO uint32_t TAR
 
__IO uint32_t CAR
 
__I uint32_t LIR
 
__IO uint32_t RIER
 
__IO uint32_t RIIR
 
__IO uint32_t TTR
 
uint32_t RESERVE0 [2]
 
__IO uint32_t SPRCTL
 
__IO uint32_t SPR [20]
 

Detailed Description

@addtogroup RTC Real Time Clock Controller(RTC)
Memory Mapped Structure for RTC Controller

Definition at line 7772 of file Nano100Series.h.

Field Documentation

◆ AER

__IO uint32_t RTC_T::AER

AER

Offset: 0x04 RTC Access Enable Register

Bits Field Descriptions
[15:0] AER RTC Register Access Enable Password (Write Only)
Enable RTC access after write 0xA965. Otherwise disable RTC access.
[16] ENF RTC Register Access Enable Flag (Read Only)
1 = RTC register read/write Enabled.
0 = RTC register read/write Disabled.
This bit will be set after AER[15:0] register is load a 0xA965, and be cleared automatically 512 RTC clocks or AER[15:0] is not 0xA965.

Definition at line 7808 of file Nano100Series.h.

◆ CAR

__IO uint32_t RTC_T::CAR

CAR

Offset: 0x20 Calendar Alarm Register

Bits Field Descriptions
[3:0] 1DAY 1 Day Calendar Digit of Alarm Setting (0~9)
[5:4] 10DAY 10 Day Calendar Digit of Alarm Setting (0~3)
[11:8] 1MON 1 Month Calendar Digit of Alarm Setting (0~9)
[12] 10MON 10 Month Calendar Digit of Alarm Setting (0~1)
[19:16] 1YEAR 1 Year Calendar Digit of Alarm Setting (0~9)
[23:20] 10YEAR 10 Year Calendar Digit of Alarm Setting (0~9)

Definition at line 7934 of file Nano100Series.h.

◆ CLR

__IO uint32_t RTC_T::CLR

CLR

Offset: 0x10 Calendar Loading Register

Bits Field Descriptions
[3:0] 1DAY 1 Day Calendar Digit (0~9)
[5:4] 10DAY 10 Day Calendar Digit (0~3)
[11:8] 1MON 1 Month Calendar Digit (0~9)
[12] 10MON 10 Month Calendar Digit (0~1)
[19:16] 1YEAR 1 Year Calendar Digit (0~9)
[23:20] 10YEAR 10 Year Calendar Digit (0~9)

Definition at line 7870 of file Nano100Series.h.

◆ DWR

__IO uint32_t RTC_T::DWR

DWR

Offset: 0x18 Day of the Week Register

Bits Field Descriptions
[2:0] DWR Day Of The Week Register
000 = Sunday.
001 = Monday.
010 = Tuesday.
011 = Wednesday.
100 = Thursday.
101 = Friday.
110 = Saturday.

Definition at line 7902 of file Nano100Series.h.

◆ FCR

__IO uint32_t RTC_T::FCR

FCR

Offset: 0x08 RTC Frequency Compensation Register

Bits Field Descriptions
[5:0] FRACTION Fraction Part
Formula = (fraction part of detected value) x 64.
Note: Digit in FCR must be expressed as hexadecimal number.
[11:8] INTEGER Integer Part
0000 = 32761.
0001 = 32762.
0010 = 32763.
0011 = 32764.
0100 = 32765.
0101 = 32766.
0110 = 32767.
0111 = 32768.
1000 = 32769.
1001 = 32770.
1010 = 32771.
1011 = 32772.
1100 = 32773.
1101 = 32774.
1110 = 32775.
1111 = 32776.

Definition at line 7838 of file Nano100Series.h.

◆ INIR

__IO uint32_t RTC_T::INIR

INIR

Offset: 0x00 RTC Initiation Register

Bits Field Descriptions
[0] ACTIVE RTC Active Status (Read Only)
0 = RTC is at reset state.
1 = RTC is at normal active state.
[31:1] INIR RTC Initiation (Write Only)
When RTC block is powered on, RTC is at reset state.
User has to write a number (0x a5eb1357) to INIR to make RTC leaving reset state.
Once the INIR is written as 0xa5eb1357, the RTC will be in un-reset state permanently.
The INIR is a write-only field and read value will be always "0".

Definition at line 7792 of file Nano100Series.h.

◆ LIR

__I uint32_t RTC_T::LIR

LIR

Offset: 0x24 Leap Year Indicator Register

Bits Field Descriptions
[0] LIR Leap Year Indication REGISTER (Read Only)
0 = This year is not a leap year.
1 = This year is leap year.

Definition at line 7947 of file Nano100Series.h.

◆ RESERVE0

uint32_t RTC_T::RESERVE0[2]

Definition at line 8021 of file Nano100Series.h.

◆ RIER

__IO uint32_t RTC_T::RIER

RIER

Offset: 0x28 RTC Interrupt Enable Register

Bits Field Descriptions
[0] AIER Alarm Interrupt Enable
0 = RTC Alarm Interrupt is disabled.
1 = RTC Alarm Interrupt is enabled.
[1] TIER Time Tick Interrupt And Wake-Up By Tick Enable
0 = RTC Time Tick Interrupt is disabled.
1 = RTC Time Tick Interrupt is enabled.
[2] SNOOPIER Snooper Pin Event Detection Interrupt Enable
0 = Snooper Pin Event Detection Interrupt is disabled.
1 = Snooper Pin Event Detection Interrupt is enabled.

Definition at line 7966 of file Nano100Series.h.

◆ RIIR

__IO uint32_t RTC_T::RIIR

RIIR

Offset: 0x2C RTC Interrupt Indication Register

Bits Field Descriptions
[0] AIS RTC Alarm Interrupt Status
RTC unit will set AIS to high once the RTC real time counters TLR and CLR reach the alarm setting time registers TAR and CAR.
When this bit is set and AIER is also high, RTC will generate an interrupt to CPU.
This bit is cleared by writing "1" to it through software.
0 = RCT Alarm Interrupt condition never occurred.
1 = RTC Alarm Interrupt is requested if RIER.AIER=1.
[1] TIS RTC Time Tick Interrupt Status
RTC unit will set TIF to high periodically in the period selected by TTR[2:0].
When this bit is set and TIER is also high, RTC will generate an interrupt to CPU.
This bit is cleared by writing "1" to it through software.
0 = RCT Time Tick Interrupt condition never occurred.
1 = RTC Time Tick Interrupt is requested.
[2] SNOOPIF Snooper Pin Event Detection Interrupt Flag
When SNOOPEN is high and an event defined by SNOOPEDGE detected in snooper pin, this flag will be set.
While this bit is set and SNOOPIER is also high, RTC will generate an interrupt to CPU.
Write "1" to clear this bit to "0".
0 = Snooper pin event defined by SNOOPEDGE never detected.
1 = Snooper pin event defined by SNOOPEDGE detected.

Definition at line 7994 of file Nano100Series.h.

◆ SPR

__IO uint32_t RTC_T::SPR[20]

SPR0 ~ 19

Offset: 0x40 ~ 0x8C RTC Spare Register 0 ~ 19

Bits Field Descriptions
[31:0] SPARE SPARE
This field is used to store back-up information defined by software.
This field will be cleared by hardware automatically once a snooper pin event is detected.

Definition at line 8062 of file Nano100Series.h.

◆ SPRCTL

__IO uint32_t RTC_T::SPRCTL

SPRCTL

Offset: 0x3C RTC Spare Functional Control Register

Bits Field Descriptions
[0] SNOOPEN Snooper Pin Event Detection Enable
This bit enables the snooper pin event detection.
When this bit is set high and an event defined by SNOOPEDGE detected, the 20 spare registers will be cleared to "0" by hardware automatically.
And, the SNOOPIF will also be set.
In addition, RTC will also generate wake-up event to wake system up.
0 = Snooper pin event detection function Disabled.
1 = Snooper pin event detection function Enabled.
[1] SNOOPEDGE Snooper Active Edge Selection
This bit defines which edge of snooper pin will generate a snooper pin detected event to clear the 20 spare registers.
0 = Rising edge of snooper pin generates snooper pin detected event.
1 = Falling edge of snooper pin generates snooper pin detected event.
[7] SPRRDY SPR Register Ready
This bit indicates if the registers SPR0 ~ SPR19 are ready to read.
After CPU writing registers SPR0 ~ SPR19, polling this bit to check if SP0 ~ SPR19 are updated done is necessary.
This it is read only and any write to this bit won't take any effect.
0 = SPR0 ~ SPR19 updating is in progress.
1 = SPR0 ~ SPR19 are updated done and ready to read.

Definition at line 8049 of file Nano100Series.h.

◆ TAR

__IO uint32_t RTC_T::TAR

TAR

Offset: 0x1C Time Alarm Register

Bits Field Descriptions
[3:0] 1SEC 1 Sec Time Digit of Alarm Setting (0~9)
[6:4] 10SEC 10 Sec Time Digit of Alarm Setting (0~5)
[11:8] 1MIN 1 Min Time Digit of Alarm Setting (0~9)
[14:12] 10MIN 10 Min Time Digit of Alarm Setting (0~5)
[19:16] 1HR 1 Hour Time Digit of Alarm Setting (0~9)
[21:20] 10HR 10 Hour Time Digit of Alarm Setting (0~2)

Definition at line 7918 of file Nano100Series.h.

◆ TLR

__IO uint32_t RTC_T::TLR

TLR

Offset: 0x0C Time Loading Register

Bits Field Descriptions
[3:0] 1SEC 1 Sec Time Digit (0~9)
[6:4] 10SEC 10 Sec Time Digit (0~5)
[11:8] 1MIN 1 Min Time Digit (0~9)
[14:12] 10MIN 10 Min Time Digit (0~5)
[19:16] 1HR 1 Hour Time Digit (0~9)
[21:20] 10HR 10 Hour Time Digit (0~2)

Definition at line 7854 of file Nano100Series.h.

◆ TSSR

__IO uint32_t RTC_T::TSSR

TSSR

Offset: 0x14 Time Scale Selection Register

Bits Field Descriptions
[0] 24hr_12hr 24-Hour / 12-Hour Mode Selection
It indicates that TLR and TAR are in 24-hour mode or 12-hour mode
0 = select 12-hour time scale with AM and PM indication.
1 = select 24-hour time scale.

Definition at line 7884 of file Nano100Series.h.

◆ TTR

__IO uint32_t RTC_T::TTR

TTR

Offset: 0x30 RTC Time Tick Register

Bits Field Descriptions
[2:0] TTR Time Tick Register
The RTC time tick period for Periodic Time Tick Interrupt request.
000 = 1 tick/second.
001 = 1/2 tick/second.
010 = 1/4 tick/second.
011 = 1/8 tick/second.
100 = 1/16 tick/second.
101 = 1/32 tick/second.
110 = 1/64 tick/second.
111 = 1/128 tick/second.
Note: This register can be read back after the RTC is active by AER.
[3] TWKE RTC Timer Wake-Up CPU Function Enable Bit
If TWKE is set before CPU enters power-down mode, when a RTC Time Tick, CPU will be wakened up by RTC unit.
0 = Time Tick wake-up CPU function Disabled.
1 = Wake-up function Enabled so that CPU can be waken up from Power-down mode by Time Tick.
Note: Tick timer setting follows the TTR description.

Definition at line 8020 of file Nano100Series.h.


The documentation for this struct was generated from the following file: