Nano100BN Series BSP  V3.03.002
The Board Support Package for Nano100BN Series
NuEdu-Basic01_SPI_Flash.c
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1 /**************************************************************************/
12 #include <stdio.h>
13 #include "Nano100Series.h"
15 
28 /*---------------------------------------------------------------------------------------------------------*/
30 /* Definitons */
31 /*---------------------------------------------------------------------------------------------------------*/
32 #define SPI_FLASH_PORT SPI0
33 
43 void Open_SPI_Flash(void)
44 {
45 
46  /* Init GPIO for SPI Flash Port, set PE1, PE2, PE3 and PE4 for SPI0 */
49 
50  /* Enable SPI0 IP clock */
51  CLK->APBCLK |= CLK_APBCLK_SPI0_EN_Msk;
52 
53  /* Configure SPI_FLASH_PORT as a master, MSB first, clock idle low, TX at falling-edge, RX at rising-edge and 32-bit transaction */
55 
56  /* Disable the automatic hardware slave select function. Select the SS pin and configure as low-active. */
57  SPI_FLASH_PORT->SSR = (SPI_FLASH_PORT->SSR & ~SPI_SSR_SSR_Msk);
58 
59  /* Set SPI clock rate = HCLK / (20+1) = 42MHz / 21 = 2MHz */
60  SPI_FLASH_PORT->CLKDIV = (SPI_FLASH_PORT->CLKDIV & ~SPI_CLKDIV_DIVIDER1_Msk) | (0x14 << SPI_CLKDIV_DIVIDER1_Pos);
61 
62 }
63 
71 unsigned int SpiFlash_ReadMidDid(void)
72 {
73  unsigned int au32SourceData;
74  unsigned int au32DestinationData;
75 
76  // configure transaction length as 8 bits
77  SPI_FLASH_PORT->CTL = (SPI_FLASH_PORT->CTL & ~SPI_CTL_TX_BIT_LEN_Msk) | (0x08 << SPI_CTL_TX_BIT_LEN_Pos);
78 
79  // /CS: active
80  SPI_FLASH_PORT->SSR = (SPI_FLASH_PORT->SSR & ~SPI_SSR_SSR_Msk) | 0x1;
81 
82  // send Command: 0x90, Read Manufacturer/Device ID
83  au32SourceData = 0x90;
84  SPI_FLASH_PORT->TX0 = au32SourceData;
85  SPI_FLASH_PORT->CTL |= SPI_CTL_GO_BUSY_Msk;
86 
87  // wait
88  while (SPI_FLASH_PORT->CTL & SPI_CTL_GO_BUSY_Msk) {}
89 
90  // configure transaction length as 24 bits
91  SPI_FLASH_PORT->CTL = (SPI_FLASH_PORT->CTL & ~SPI_CTL_TX_BIT_LEN_Msk) | (0x18 << SPI_CTL_TX_BIT_LEN_Pos);
92 
93  // send 24-bit '0', dummy
94  au32SourceData = 0x0;
95  SPI_FLASH_PORT->TX0 = au32SourceData;
96  SPI_FLASH_PORT->CTL |= SPI_CTL_GO_BUSY_Msk;
97 
98  // wait
99  while (SPI_FLASH_PORT->CTL & SPI_CTL_GO_BUSY_Msk) {}
100 
101  // configure transaction length as 16 bits
102  SPI_FLASH_PORT->CTL = (SPI_FLASH_PORT->CTL & ~SPI_CTL_TX_BIT_LEN_Msk) | (0x10 << SPI_CTL_TX_BIT_LEN_Pos);
103 
104  // receive
105  au32SourceData = 0x0;
106  SPI_FLASH_PORT->TX0 = au32SourceData;
107  SPI_FLASH_PORT->CTL |= SPI_CTL_GO_BUSY_Msk;
108 
109  // wait
110  while (SPI_FLASH_PORT->CTL & SPI_CTL_GO_BUSY_Msk) {}
111 
112  // /CS: de-active
113  SPI_FLASH_PORT->SSR = (SPI_FLASH_PORT->SSR & ~SPI_SSR_SSR_Msk);
114 
115  // dump Rx register
116  au32DestinationData = SPI_FLASH_PORT->RX0;
117 
118  return (au32DestinationData & 0xffff);
119 
120 }
121 
128 {
129  unsigned int au32SourceData;
130 
131  // configure transaction length as 8 bits
132  SPI_FLASH_PORT->CTL = (SPI_FLASH_PORT->CTL & ~SPI_CTL_TX_BIT_LEN_Msk) | (0x08 << SPI_CTL_TX_BIT_LEN_Pos);
133 
134  // /CS: active
135  SPI_FLASH_PORT->SSR = (SPI_FLASH_PORT->SSR & ~SPI_SSR_SSR_Msk) | 0x1;
136 
137  // send Command: 0x06, Write enable
138  au32SourceData = 0x06;
139  SPI_FLASH_PORT->TX0 = au32SourceData;
140  SPI_FLASH_PORT->CTL |= SPI_CTL_GO_BUSY_Msk;
141 
142  // wait
143  while (SPI_FLASH_PORT->CTL & SPI_CTL_GO_BUSY_Msk) {}
144 
145  // /CS: de-active
146  SPI_FLASH_PORT->SSR = (SPI_FLASH_PORT->SSR & ~SPI_SSR_SSR_Msk);
147 
148  // /CS: active
149  SPI_FLASH_PORT->SSR = (SPI_FLASH_PORT->SSR & ~SPI_SSR_SSR_Msk) | 0x1;
150 
151  // send Command: 0xC7, Chip Erase
152  au32SourceData = 0xc7;
153  SPI_FLASH_PORT->TX0 = au32SourceData;
154  SPI_FLASH_PORT->CTL |= SPI_CTL_GO_BUSY_Msk;
155 
156  // wait
157  while (SPI_FLASH_PORT->CTL & SPI_CTL_GO_BUSY_Msk) {}
158 
159  // /CS: de-active
160  SPI_FLASH_PORT->SSR = (SPI_FLASH_PORT->SSR & ~SPI_SSR_SSR_Msk);
161 
162 }
163 
169 unsigned int SpiFlash_ReadStatusReg1(void)
170 {
171  unsigned int au32SourceData;
172  unsigned int au32DestinationData;
173 
174  // configure transaction length as 16 bits
175  SPI_FLASH_PORT->CTL = (SPI_FLASH_PORT->CTL & ~SPI_CTL_TX_BIT_LEN_Msk) | (0x10 << SPI_CTL_TX_BIT_LEN_Pos);
176 
177  // /CS: active
178  SPI_FLASH_PORT->SSR = (SPI_FLASH_PORT->SSR & ~SPI_SSR_SSR_Msk) | 0x1;
179 
180  // send Command: 0x05, Read status register 1
181  au32SourceData = 0x0500;
182  SPI_FLASH_PORT->TX0 = au32SourceData;
183  SPI_FLASH_PORT->CTL |= SPI_CTL_GO_BUSY_Msk;
184 
185  // wait
186  while (SPI_FLASH_PORT->CTL & SPI_CTL_GO_BUSY_Msk) {}
187 
188  // /CS: de-active
189  SPI_FLASH_PORT->SSR = (SPI_FLASH_PORT->SSR & ~SPI_SSR_SSR_Msk);
190 
191  // dump Rx register
192  au32DestinationData = SPI_FLASH_PORT->RX0;
193 
194  return (au32DestinationData & 0xFF);
195 
196 }
197 
203 unsigned int SpiFlash_ReadStatusReg2(void)
204 {
205  unsigned int au32SourceData;
206  unsigned int au32DestinationData;
207 
208  // configure transaction length as 16 bits
209  SPI_FLASH_PORT->CTL = (SPI_FLASH_PORT->CTL & ~SPI_CTL_TX_BIT_LEN_Msk) | (0x10 << SPI_CTL_TX_BIT_LEN_Pos);
210 
211  // /CS: active
212  SPI_FLASH_PORT->SSR = (SPI_FLASH_PORT->SSR & ~SPI_SSR_SSR_Msk) | 0x1;
213 
214  // send Command: 0x35, Read status register 2
215  au32SourceData = 0x3500;
216  SPI_FLASH_PORT->TX0 = au32SourceData;
217  SPI_FLASH_PORT->CTL |= SPI_CTL_GO_BUSY_Msk;
218 
219  // wait
220  while (SPI_FLASH_PORT->CTL & SPI_CTL_GO_BUSY_Msk) {}
221 
222  // /CS: de-active
223  SPI_FLASH_PORT->SSR = (SPI_FLASH_PORT->SSR & ~SPI_SSR_SSR_Msk);
224 
225  // dump Rx register
226  au32DestinationData = SPI_FLASH_PORT->RX0;
227 
228  return (au32DestinationData & 0xFF);
229 
230 }
231 
238 {
239  unsigned int ReturnValue;
240 
241  do
242  {
243  ReturnValue = SpiFlash_ReadStatusReg1();
244  ReturnValue = ReturnValue & 1;
245  }
246  while(ReturnValue!=0); // check the BUSY bit
247 
248 }
249 
261 void SpiFlash_PageProgram(unsigned char *DataBuffer, unsigned int StartAddress, unsigned int ByteCount)
262 {
263  unsigned int au32SourceData;
264  unsigned int Counter;
265 
266  // configure transaction length as 8 bits
267  SPI_FLASH_PORT->CTL = (SPI_FLASH_PORT->CTL & ~SPI_CTL_TX_BIT_LEN_Msk) | (0x08 << SPI_CTL_TX_BIT_LEN_Pos);
268 
269  // /CS: active
270  SPI_FLASH_PORT->SSR = (SPI_FLASH_PORT->SSR & ~SPI_SSR_SSR_Msk) | 0x1;
271 
272  // send Command: 0x06, Write enable
273  au32SourceData = 0x06;
274  SPI_FLASH_PORT->TX0 = au32SourceData;
275  SPI_FLASH_PORT->CTL |= SPI_CTL_GO_BUSY_Msk;
276 
277  // wait
278  while (SPI_FLASH_PORT->CTL & SPI_CTL_GO_BUSY_Msk) {}
279 
280  // /CS: de-active
281  SPI_FLASH_PORT->SSR = (SPI_FLASH_PORT->SSR & ~SPI_SSR_SSR_Msk);
282 
283  // /CS: active
284  SPI_FLASH_PORT->SSR = (SPI_FLASH_PORT->SSR & ~SPI_SSR_SSR_Msk) | 0x1;
285 
286  // send Command: 0x02, Page program
287  au32SourceData = 0x02;
288  SPI_FLASH_PORT->TX0 = au32SourceData;
289  SPI_FLASH_PORT->CTL |= SPI_CTL_GO_BUSY_Msk;
290 
291  // wait
292  while (SPI_FLASH_PORT->CTL & SPI_CTL_GO_BUSY_Msk) {}
293 
294  // configure transaction length as 24 bits
295  SPI_FLASH_PORT->CTL = (SPI_FLASH_PORT->CTL & ~SPI_CTL_TX_BIT_LEN_Msk) | (0x18 << SPI_CTL_TX_BIT_LEN_Pos);
296 
297  // send 24-bit start address
298  au32SourceData = StartAddress;
299  SPI_FLASH_PORT->TX0 = au32SourceData;
300  SPI_FLASH_PORT->CTL |= SPI_CTL_GO_BUSY_Msk;
301 
302  // wait
303  while (SPI_FLASH_PORT->CTL & SPI_CTL_GO_BUSY_Msk) {}
304 
305  // configure transaction length as 8 bits
306  SPI_FLASH_PORT->CTL = (SPI_FLASH_PORT->CTL & ~SPI_CTL_TX_BIT_LEN_Msk) | (0x08 << SPI_CTL_TX_BIT_LEN_Pos);
307 
308  for(Counter=0; Counter<ByteCount; Counter++)
309  {
310  // send data to program
311  au32SourceData = DataBuffer[Counter];
312  SPI_FLASH_PORT->TX0 = au32SourceData;
313  SPI_FLASH_PORT->CTL |= SPI_CTL_GO_BUSY_Msk;
314 
315  // wait
316  while (SPI_FLASH_PORT->CTL & SPI_CTL_GO_BUSY_Msk) {}
317  }
318 
319  // /CS: de-active
320  SPI_FLASH_PORT->SSR = (SPI_FLASH_PORT->SSR & ~SPI_SSR_SSR_Msk);
321 
322 }
323 
335 void SpiFlash_ReadData(unsigned char *DataBuffer, unsigned int StartAddress, unsigned int ByteCount)
336 {
337  unsigned int au32SourceData;
338  unsigned int au32DestinationData;
339  unsigned int Counter;
340 
341  // configure transaction length as 8 bits
342  SPI_FLASH_PORT->CTL = (SPI_FLASH_PORT->CTL & ~SPI_CTL_TX_BIT_LEN_Msk) | (0x08 << SPI_CTL_TX_BIT_LEN_Pos);
343 
344  // /CS: active
345  SPI_FLASH_PORT->SSR = (SPI_FLASH_PORT->SSR & ~SPI_SSR_SSR_Msk) | 0x1;
346 
347  // send Command: 0x03, Read data
348  au32SourceData = 0x03;
349  SPI_FLASH_PORT->TX0 = au32SourceData;
350  SPI_FLASH_PORT->CTL |= SPI_CTL_GO_BUSY_Msk;
351 
352  // wait
353  while (SPI_FLASH_PORT->CTL & SPI_CTL_GO_BUSY_Msk) {}
354 
355  // configure transaction length as 24 bits
356  SPI_FLASH_PORT->CTL = (SPI_FLASH_PORT->CTL & ~SPI_CTL_TX_BIT_LEN_Msk) | (0x18 << SPI_CTL_TX_BIT_LEN_Pos);
357 
358  // send 24-bit start address
359  au32SourceData = StartAddress;
360  SPI_FLASH_PORT->TX0 = au32SourceData;
361  SPI_FLASH_PORT->CTL |= SPI_CTL_GO_BUSY_Msk;
362 
363  // wait
364  while (SPI_FLASH_PORT->CTL & SPI_CTL_GO_BUSY_Msk) {}
365 
366  // configure transaction length as 8 bits
367  SPI_FLASH_PORT->CTL = (SPI_FLASH_PORT->CTL & ~SPI_CTL_TX_BIT_LEN_Msk) | (0x08 << SPI_CTL_TX_BIT_LEN_Pos);
368 
369  for(Counter=0; Counter<ByteCount; Counter++)
370  {
371  // receive
372  au32SourceData = 0x0;
373  SPI_FLASH_PORT->TX0 = au32SourceData;
374  SPI_FLASH_PORT->CTL |= SPI_CTL_GO_BUSY_Msk;
375 
376  // wait
377  while (SPI_FLASH_PORT->CTL & SPI_CTL_GO_BUSY_Msk) {}
378 
379  // dump Rx register
380  au32DestinationData = SPI_FLASH_PORT->RX0;
381  DataBuffer[Counter] = (unsigned char) au32DestinationData;
382  }
383 
384  // /CS: de-active
385  SPI_FLASH_PORT->SSR = (SPI_FLASH_PORT->SSR & ~SPI_SSR_SSR_Msk);
386 
387 }
388 
389  /* end of group Nano130_Basic01_FUNCTIONS */
391  /* end of group NuEdu-SDK-Nano130_Basic01 */
393  /* end of group NANO100_Library */
395 
396 /*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
#define SPI_CTL_TX_BIT_LEN_Pos
#define SPI_CTL_SLAVE_Msk
#define CLK
Pointer to CLK register structure.
#define SPI_CTL_RX_NEG_Msk
#define SPI_CTL_TX_NEG_Msk
#define SPI_CTL_GO_BUSY_Msk
Nano100 series peripheral access layer header file. This file contains all the peripheral register's ...
void SpiFlash_ChipErase(void)
This function do the chip erasing to SPI Flash device.
#define SYS_PE_L_MFP_PE4_MFP_SPI0_MOSI0
Definition: sys.h:498
void SpiFlash_ReadData(unsigned char *DataBuffer, unsigned int StartAddress, unsigned int ByteCount)
This function do the data reading from SPI Flash device.
#define SPI_CLKDIV_DIVIDER1_Msk
#define SPI_CLKDIV_DIVIDER1_Pos
unsigned int SpiFlash_ReadStatusReg2(void)
Read back the Status Register 2 from SPI Flash device.
NuEdu-Basic01 SPI Flash driver header file for NuEdu-SDK-Nano130.
void SpiFlash_PageProgram(unsigned char *DataBuffer, unsigned int StartAddress, unsigned int ByteCount)
This function do the page programming to SPI Flash device.
void SpiFlash_WaitReady(void)
Waiting for the BUSY bit of SPI Flash that be cleared to 0.
#define SPI_CTL_TX_BIT_LEN_Msk
#define SPI_CTL_LSB_Msk
unsigned int SpiFlash_ReadMidDid(void)
Read back the Manufacturer ID and Device ID from SPI Flash device.
#define SPI_SSR_SSR_Msk
void Open_SPI_Flash(void)
Open GPIO port for SPI interface and configure this SPI controller as Master, MSB first,...
#define SYS_PE_L_MFP_PE1_MFP_SPI0_SS0
Definition: sys.h:508
#define CLK_APBCLK_SPI0_EN_Msk
#define SPI_CTL_CLKP_Msk
#define SYS_PE_L_MFP_PE3_MFP_SPI0_MISO0
Definition: sys.h:501
#define SYS_PE_L_MFP_PE2_MFP_SPI0_SCLK
Definition: sys.h:504
unsigned int SpiFlash_ReadStatusReg1(void)
Read back the Status Register 1 from SPI Flash device.
#define SYS
Pointer to SYS register structure.