| Nano100BN Series BSP V3.03.002 The Board Support Package for Nano100BN Series

pdma.c
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1 /**************************************************************************/
12 #include "Nano100Series.h"
13
14
15
38 void PDMA_Open(uint32_t u32Mask)
39 {
40 PDMAGCR->GCRCSR |= (u32Mask << 8);
41 }
42
52 void PDMA_Close(void)
53 {
54 PDMAGCR->GCRCSR = 0;
55 }
56
68 void PDMA_SetTransferCnt(uint32_t u32Ch, uint32_t u32Width, uint32_t u32TransCount)
69 {
70 PDMA_T *pdma;
71 pdma = (PDMA_T *)((uint32_t) PDMA1_BASE + (0x100 * (u32Ch-1)));
72 pdma->CSR = (pdma->CSR & ~PDMA_CSR_APB_TWS_Msk) | u32Width;
73 switch (u32Width)
74 {
75 case PDMA_WIDTH_32:
76 pdma->BCR = (u32TransCount << 2);
77 break;
78
79 case PDMA_WIDTH_8:
80 pdma->BCR = u32TransCount;
81 break;
82
83 case PDMA_WIDTH_16:
84 pdma->BCR = (u32TransCount << 1);
85 break;
86
87 default:
88 ;
89 }
90 }
91
105 void PDMA_SetTransferAddr(uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl)
106 {
107 PDMA_T *pdma;
108 pdma = (PDMA_T *)((uint32_t) PDMA1_BASE + (0x100 * (u32Ch-1)));
109
110 pdma->SAR = u32SrcAddr;
111 pdma->DAR = u32DstAddr;
112 pdma->CSR = (pdma->CSR & ~(PDMA_CSR_SAD_SEL_Msk|PDMA_CSR_DAD_SEL_Msk)) | (u32SrcCtrl | u32DstCtrl);
113 }
114
133 void PDMA_SetTransferMode(uint32_t u32Ch, uint32_t u32Peripheral, uint32_t u32ScatterEn, uint32_t u32DescAddr)
134 {
135 PDMA_T *pdma;
136 pdma = (PDMA_T *)((uint32_t) PDMA1_BASE + (0x100 * (u32Ch-1)));
137
138 switch (u32Ch)
139 {
140 case 1:
141 PDMAGCR->DSSR0 = (PDMAGCR->DSSR0 & ~DMA_GCR_DSSR0_CH1_SEL_Msk) | (u32Peripheral << DMA_GCR_DSSR0_CH1_SEL_Pos);
142 break;
143 case 2:
144 PDMAGCR->DSSR0 = (PDMAGCR->DSSR0 & ~DMA_GCR_DSSR0_CH2_SEL_Msk) | (u32Peripheral << DMA_GCR_DSSR0_CH2_SEL_Pos);
145 break;
146 case 3:
147 PDMAGCR->DSSR0 = (PDMAGCR->DSSR0 & ~DMA_GCR_DSSR0_CH3_SEL_Msk) | (u32Peripheral << DMA_GCR_DSSR0_CH3_SEL_Pos);
148 break;
149 case 4:
150 PDMAGCR->DSSR1 = (PDMAGCR->DSSR1 & ~DMA_GCR_DSSR1_CH4_SEL_Msk) | u32Peripheral;
151 break;
152 default:
153 ;
154 }
155 if (u32Peripheral == PDMA_MEM)
156 pdma->CSR &= ~PDMA_CSR_MODE_SEL_Msk;
157 else if (u32Peripheral & 0x10)
158 pdma->CSR = (pdma->CSR & ~PDMA_CSR_MODE_SEL_Msk) | 0x4; /* IP to memory */
159 else
160 pdma->CSR = (pdma->CSR & ~PDMA_CSR_MODE_SEL_Msk) | 0x8; /* memory to IP */
161 }
162
174 void PDMA_SetTimeOut(uint32_t u32Ch, uint32_t u32OnOff, uint32_t u32TimeOutCnt)
175 {
176 PDMA_T *pdma;
177 pdma = (PDMA_T *)((uint32_t) PDMA1_BASE + (0x100 * (u32Ch-1)));
178
179 pdma->TCR = (pdma->TCR & ~PDMA_TCR_PDMA_TCR_Msk) | u32TimeOutCnt;
180 pdma->CSR = (pdma->CSR & ~PDMA_CSR_TO_EN_Msk) | (u32OnOff << PDMA_CSR_TO_EN_Pos);
181
182 }
183
193 void PDMA_Trigger(uint32_t u32Ch)
194 {
195 PDMA_T *pdma;
196 pdma = (PDMA_T *)((uint32_t) PDMA1_BASE + (0x100 * (u32Ch-1)));
197
198 pdma->CSR |= (PDMA_CSR_TRIG_EN_Msk | PDMA_CSR_PDMACEN_Msk);
199 }
200
211 void PDMA_EnableInt(uint32_t u32Ch, uint32_t u32Mask)
212 {
213 PDMA_T *pdma;
214 pdma = (PDMA_T *)((uint32_t) PDMA1_BASE + (0x100 * (u32Ch-1)));
215
216 pdma->IER |= u32Mask;
217 }
218
229 void PDMA_DisableInt(uint32_t u32Ch, uint32_t u32Mask)
230 {
231 PDMA_T *pdma;
232 pdma = (PDMA_T *)((uint32_t) PDMA1_BASE + (0x100 * (u32Ch-1)));
233
234 pdma->IER &= ~u32Mask;
235 }
236
237 /* end of group NANO100_PDMA_EXPORTED_FUNCTIONS */
239 /* end of group NANO100_PDMA_Driver */
241 /* end of group NANO100_Device_Driver */
243
244 /*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
PDMA_T::DAR
__IO uint32_t DAR
Definition: Nano100Series.h:5987
PDMA_Trigger
void PDMA_Trigger(uint32_t u32Ch)
Trigger PDMA.
Definition: pdma.c:193
PDMA_TCR_PDMA_TCR_Msk
#define PDMA_TCR_PDMA_TCR_Msk
Definition: Nano100Series.h:6508
PDMA_CSR_DAD_SEL_Msk
#define PDMA_CSR_DAD_SEL_Msk
Definition: Nano100Series.h:6454
PDMA_CSR_PDMACEN_Msk
#define PDMA_CSR_PDMACEN_Msk
Definition: Nano100Series.h:6442
PDMA_T::CSR
__IO uint32_t CSR
Definition: Nano100Series.h:5961
DMA_GCR_DSSR0_CH2_SEL_Msk
#define DMA_GCR_DSSR0_CH2_SEL_Msk
Definition: Nano100Series.h:6395
PDMA_DisableInt
void PDMA_DisableInt(uint32_t u32Ch, uint32_t u32Mask)
Disable Interrupt.
Definition: pdma.c:229
PDMA_EnableInt
void PDMA_EnableInt(uint32_t u32Ch, uint32_t u32Mask)
Enable Interrupt.
Definition: pdma.c:211
DMA_GCR_DSSR1_CH4_SEL_Msk
#define DMA_GCR_DSSR1_CH4_SEL_Msk
Definition: Nano100Series.h:6401
PDMA_SetTransferAddr
void PDMA_SetTransferAddr(uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl)
Set PDMA Transfer Address.
Definition: pdma.c:105
Nano100Series.h
Nano100 series peripheral access layer header file. This file contains all the peripheral register's ...
PDMA_T
Definition: Nano100Series.h:5907
PDMA_SetTransferMode
void PDMA_SetTransferMode(uint32_t u32Ch, uint32_t u32Periphral, uint32_t u32ScatterEn, uint32_t u32DescAddr)
Set PDMA Transfer Mode.
Definition: pdma.c:133
PDMA_CSR_TO_EN_Pos
#define PDMA_CSR_TO_EN_Pos
Definition: Nano100Series.h:6456
PDMA_CSR_APB_TWS_Msk
#define PDMA_CSR_APB_TWS_Msk
Definition: Nano100Series.h:6460
PDMA_T::IER
__IO uint32_t IER
Definition: Nano100Series.h:6061
PDMA_WIDTH_16
#define PDMA_WIDTH_16
Definition: pdma.h:37
PDMA_Open
void PDMA_Open(uint32_t u32Mask)
PDMA Open.
Definition: pdma.c:38
PDMA_SetTimeOut
void PDMA_SetTimeOut(uint32_t u32Ch, uint32_t u32OnOff, uint32_t u32TimeOutCnt)
Set PDMA Timeout.
Definition: pdma.c:174
PDMA_CSR_TRIG_EN_Msk
#define PDMA_CSR_TRIG_EN_Msk
Definition: Nano100Series.h:6463
DMA_GCR_DSSR0_CH1_SEL_Pos
#define DMA_GCR_DSSR0_CH1_SEL_Pos
Definition: Nano100Series.h:6391
PDMA_MEM
#define PDMA_MEM
Definition: pdma.h:79
PDMA_CSR_TO_EN_Msk
#define PDMA_CSR_TO_EN_Msk
Definition: Nano100Series.h:6457
DMA_GCR_DSSR0_CH3_SEL_Pos
#define DMA_GCR_DSSR0_CH3_SEL_Pos
Definition: Nano100Series.h:6397
PDMA_T::BCR
__IO uint32_t BCR
Definition: Nano100Series.h:6000
PDMA_T::TCR
__IO uint32_t TCR
Definition: Nano100Series.h:6109
PDMA_SetTransferCnt
void PDMA_SetTransferCnt(uint32_t u32Ch, uint32_t u32Width, uint32_t u32TransCount)
Set PDMA Transfer Count.
Definition: pdma.c:68
DMA_GCR_DSSR0_CH2_SEL_Pos
#define DMA_GCR_DSSR0_CH2_SEL_Pos
Definition: Nano100Series.h:6394
PDMA_WIDTH_32
#define PDMA_WIDTH_32
Definition: pdma.h:38
PDMA_Close
void PDMA_Close(void)
PDMA Close.
Definition: pdma.c:52
DMA_GCR_DSSR0_CH3_SEL_Msk
#define DMA_GCR_DSSR0_CH3_SEL_Msk
Definition: Nano100Series.h:6398
PDMA_CSR_SAD_SEL_Msk
#define PDMA_CSR_SAD_SEL_Msk
Definition: Nano100Series.h:6451
PDMA_T::SAR
__IO uint32_t SAR
Definition: Nano100Series.h:5974
PDMA_CSR_MODE_SEL_Msk
#define PDMA_CSR_MODE_SEL_Msk
Definition: Nano100Series.h:6448
PDMAGCR
#define PDMAGCR
Pointer to PDMA global control register structure.
Definition: Nano100Series.h:11710
DMA_GCR_DSSR0_CH1_SEL_Msk
#define DMA_GCR_DSSR0_CH1_SEL_Msk
Definition: Nano100Series.h:6392
PDMA1_BASE
#define PDMA1_BASE
PDMA1 register base address.
Definition: Nano100Series.h:11648
PDMA_WIDTH_8
#define PDMA_WIDTH_8
Definition: pdma.h:36