| Nano100BN Series BSP V3.03.002 The Board Support Package for Nano100BN Series

Data Fields
DMA_GCR_T Struct Reference

`#include <Nano100Series.h>`

## Data Fields
__IO uint32_t | GCRCSR
__IO uint32_t | DSSR0
__IO uint32_t | DSSR1
__I uint32_t | GCRISR

## Detailed Description

Definition at line 5759 of file Nano100Series.h.

## Field Documentation

## ◆ DSSR0

__IO uint32_t DMA_GCR_T::DSSR0

# DSSR0

## Offset: 0x04 DMA Service Selection Control Register 0

Bits | Field | Descriptions
--- | --- | ---
[12:8] | CH1_SEL | Channel 1 Selection
|  | This filed defines which peripheral is connected to PDMA channel 1.
|  | Software can configure the peripheral by setting CH1_SEL.
|  | 00000 = Connect to SPI0_TX.
|  | 00001 = Connect to SPI1_TX.
|  | 00010 = Connect to UART0_TX.
|  | 00011 = Connect to UART1_TX.
|  | 00100 = Connect to USB_TX.
|  | 00101 = Connect to I2S_TX.
|  | 00110 = Connect to DAC0_TX.
|  | 00111 = Connect to DAC1_TX.
|  | 01000 = Connect to SPI2_TX.
|  | 01001 = Connect to TMR0.
|  | 01010 = Connect to TMR1.
|  | 01011 = Connect to TMR2.
|  | 01100 = Connect to TMR3.
|  | 10000 = Connect to SPI0_RX.
|  | 10001 = Connect to SPI1_RX.
|  | 10010 = Connect to UART0_RX.
|  | 10011 = Connect to UART1_RX.
|  | 10100 = Connect to USB_RX.
|  | 10101 = Connect to I2S_RX.
|  | 10110 = Connect to ADC.
|  | 11000 = Connect to SPI2_RX.
|  | 11001 = Connect to PWM0_CH0.
|  | 11010 = Connect to PWM0_CH2.
|  | 11011 = Connect to PWM1_CH0.
|  | 11100 = Connect to PWM1_CH2.
[20:16] | CH2_SEL | Channel 2 Selection
|  | This filed defines which peripheral is connected to PDMA channel 2.
|  | Software can configure the peripheral setting by CH2_SEL.
|  | The channel configuration is the same as CH1_SEL field.
|  | Please refer to the explanation of CH1_SEL.
[28:24] | CH3_SEL | Channel 3 Selection
|  | This filed defines which peripheral is connected to PDMA channel 3.
|  | Software can configure the peripheral setting by CH3_SEL.
|  | The channel configuration is the same as CH1_SEL field.
|  | Please refer to the explanation of CH1_SEL.

Definition at line 5843 of file Nano100Series.h.

## ◆ DSSR1

__IO uint32_t DMA_GCR_T::DSSR1

# DSSR1

## Offset: 0x08 DMA Service Selection Control Register 1

Bits | Field | Descriptions
--- | --- | ---
[4:0] | CH4_SEL | Channel 4 Selection
|  | This filed defines which peripheral is connected to PDMA channel 4.
|  | Software can configure the peripheral by setting CH4_SEL.
|  | The channel configuration is the same as CH1_SEL field.
|  | Please refer to the explanation of CH1_SEL.
[12:8] | CH5_SEL | Channel 5 Selection
|  | This filed defines which peripheral is connected to PDMA channel 5.
|  | Software can configure the peripheral setting by CH5_SEL.
|  | The channel configuration is the same as CH1_SEL field.
|  | Please refer to the explanation of CH1_SEL.
[20:16] | CH6_SEL | Channel 6 Selection
|  | This filed defines which peripheral is connected to PDMA channel 6.
|  | Software can configure the peripheral setting by CH6_SEL.
|  | The channel configuration is the same as CH1_SEL field.
|  | Please refer to the explanation of CH1_SEL.

Definition at line 5868 of file Nano100Series.h.

## ◆ GCRCSR

__IO uint32_t DMA_GCR_T::GCRCSR

# GCRCSR

## Offset: 0x00 DMA Global Control and Status Register

Bits | Field | Descriptions
--- | --- | ---
[8] | CLK0_EN | DMA Controller Channel 0 Clock Enable Control
|  | 0 = Disabled.
|  | 1 = Enabled.
[9] | CLK1_EN | DMA Controller Channel 1 Clock Enable Control
|  | 0 = Disabled.
|  | 1 = Enabled.
[10] | CLK2_EN | DMA Controller Channel 2 Clock Enable Control
|  | 0 = Disabled.
|  | 1 = Enabled.
[11] | CLK3_EN | DMA Controller Channel 3 Clock Enable Control
|  | 0 = Disabled.
|  | 1 = Enabled.
[12] | CLK4_EN | DMA Controller Channel 4 Clock Enable Control
|  | 0 = Disabled.
|  | 1 = Enabled.
[13] | CLK5_EN | DMA Controller Channel 5 Clock Enable Control
|  | 0 = Disabled.
|  | 1 = Enabled.
[14] | CLK6_EN | DMA Controller Channel 6 Clock Enable Control
|  | 0 = Disabled.
|  | 1 = Enabled.
[24] | CRC_CLK_EN | CRC Controller Clock Enable Control
|  | 0 = Disabled.
|  | 1 = Enabled.

Definition at line 5795 of file Nano100Series.h.

## ◆ GCRISR

__I uint32_t DMA_GCR_T::GCRISR

# GCRISR

## Offset: 0x0C DMA Global Interrupt Status Register

Bits | Field | Descriptions
--- | --- | ---
[0] | INTR0 | Interrupt Pin Status Of Channel 0 (Read Only)
|  | This bit is the Interrupt pin status of DMA channel0.
|  | Note: This bit is read only
[1] | INTR1 | Interrupt Pin Status Of Channel 1 (Read Only)
|  | This bit is the Interrupt pin status of DMA channel1.
|  | Note: This bit is read only
[2] | INTR2 | Interrupt Pin Status Of Channel 2 (Read Only)
|  | This bit is the Interrupt pin status of DMA channel2.
|  | Note: This bit is read only
[3] | INTR3 | Interrupt Pin Status Of Channel 3 (Read Only)
|  | This bit is the Interrupt pin status of DMA channel3.
|  | Note: This bit is read only
[4] | INTR4 | Interrupt Pin Status Of Channel 4 (Read Only)
|  | This bit is the Interrupt pin status of DMA channel4.
|  | Note: This bit is read only
[5] | INTR5 | Interrupt Pin Status Of Channel 5 (Read Only)
|  | This bit is the Interrupt pin status of DMA channel4.
|  | Note: This bit is read only
[6] | INTR6 | Interrupt Pin Status Of Channel 6 (Read Only)
|  | This bit is the Interrupt pin status of DMA channel4.
|  | Note: This bit is read only
[16] | CRC_INTR | Interrupt Pin Status Of CRC Controller
|  | This bit is the Interrupt status of CRC controller
|  | Note: This bit is read only

Definition at line 5902 of file Nano100Series.h.

The documentation for this struct was generated from the following file:

- C:/Users/yachen/workzone/bsp/nano100bbsp/Library/Device/Nuvoton/Nano100Series/Include/Nano100Series.h