| Nano102_112 Series BSP V3.03.002 The Board Support Package for Nano102_112 Series

adc.c
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1 /**************************************************************************/
12 #include "Nano1X2Series.h"
13
41 void ADC_Open(ADC_T *adc,
42 uint32_t u32InputMode,
43 uint32_t u32OpMode,
44 uint32_t u32ChMask)
45 {
46
47 ADC->CR = (ADC->CR & ~ADC_CR_DIFF_Msk) | u32InputMode;
48 ADC->CR = (ADC->CR & ~ADC_CR_ADMD_Msk) | u32OpMode;
49 ADC->CR = (ADC->CR & ~ADC_CR_REFSEL_Msk);
50 ADC->CHEN = u32ChMask;
51 return;
52 }
53
59 void ADC_Close(ADC_T *adc)
60 {
61 SYS->IPRST_CTL2 |= SYS_IPRST_CTL2_ADC_RST_Msk;
62 SYS->IPRST_CTL2 &= ~SYS_IPRST_CTL2_ADC_RST_Msk;
63 return;
64
65 }
66
81 void ADC_EnableHWTrigger(ADC_T *adc,
82 uint32_t u32Source,
83 uint32_t u32Param)
84 {
85 ADC->CR &= ~(ADC_CR_TRGS_Msk | ADC_CR_TRGCOND_Msk | ADC_CR_TRGE_Msk);
86 if(u32Source == ADC_TRIGGER_BY_EXT_PIN)
87 {
88 ADC->CR |= u32Source | u32Param | ADC_CR_TRGE_Msk;
89 }
90 else
91 {
92 ADC->CR |= u32Source | ADC_CR_TRGE_Msk;
93 }
94
95 return;
96 }
97
103 void ADC_DisableHWTrigger(ADC_T *adc)
104 {
105 ADC->CR &= ~(ADC_CR_TRGS_Msk | ADC_CR_TRGCOND_Msk | ADC_CR_TRGE_Msk);
106 return;
107 }
108
116 void ADC_EnableTimerTrigger(ADC_T *adc,
117 uint32_t u32Source,
118 uint32_t u32PDMACnt)
119 {
120 ADC->CR &= ~(ADC_CR_TMPDMACNT_Msk | ADC_CR_TMSEL_Msk);
121 ADC->CR |= (u32PDMACnt << ADC_CR_TMPDMACNT_Pos) | (u32Source << ADC_CR_TMSEL_Pos) | ADC_CR_TMTRGMOD_Msk;
122
123 return;
124 }
125
131 void ADC_DisableTimerTrigger(ADC_T *adc)
132 {
133 ADC->CR &= ~ADC_CR_TMTRGMOD_Msk;
134
135 return;
136 }
137
145 void ADC_SetExtraSampleTime(ADC_T *adc,
146 uint32_t u32ChNum,
147 uint32_t u32SampleTime)
148 {
149
150 if (u32ChNum < 8)
151 ADC->SMPLCNT0 = (ADC->SMPLCNT0 & ~(ADC_SMPLCNT0_CH0SAMPCNT_Msk << (u32ChNum * 4))) | (u32SampleTime << (u32ChNum * 4));
152 else
153 ADC->SMPLCNT1 = (ADC->SMPLCNT1 & ~ADC_SMPLCNT1_INTCHSAMPCNT_Msk) | (u32SampleTime << ADC_SMPLCNT1_INTCHSAMPCNT_Pos);
154 }
155
167 void ADC_EnableInt(ADC_T *adc, uint32_t u32Mask)
168 {
169 if(u32Mask & ADC_ADF_INT)
170 ADC->CR |= ADC_CR_ADIE_Msk;
171 if(u32Mask & ADC_CMP0_INT)
172 ADC->CMPR0 |= ADC_CMPR_CMPIE_Msk;
173 if(u32Mask & ADC_CMP1_INT)
174 ADC->CMPR1 |= ADC_CMPR_CMPIE_Msk;
175
176 return;
177 }
178
190 void ADC_DisableInt(ADC_T *adc, uint32_t u32Mask)
191 {
192 if(u32Mask & ADC_ADF_INT)
193 ADC->CR &= ~ADC_CR_ADIE_Msk;
194 if(u32Mask & ADC_CMP0_INT)
195 ADC->CMPR0 &= ~ADC_CMPR_CMPIE_Msk;
196 if(u32Mask & ADC_CMP1_INT)
197 ADC->CMPR1 &= ~ADC_CMPR_CMPIE_Msk;
198
199 return;
200 }
201
202
203 /* end of group NANO1X2_ADC_EXPORTED_FUNCTIONS */
205 /* end of group NANO1X2_ADC_Driver */
207 /* end of group NANO1X2_Device_Driver */
209
210 /*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
ADC_EnableHWTrigger
void ADC_EnableHWTrigger(ADC_T *adc, uint32_t u32Source, uint32_t u32Param)
Configure the hardware trigger condition and enable hardware trigger.
Definition: adc.c:81
ADC_EnableTimerTrigger
void ADC_EnableTimerTrigger(ADC_T *adc, uint32_t u32Source, uint32_t u32PDMACnt)
Config and enable timer trigger.
Definition: adc.c:116
SYS_IPRST_CTL2_ADC_RST_Msk
#define SYS_IPRST_CTL2_ADC_RST_Msk
Definition: Nano1X2Series.h:3693
ADC_CR_TMTRGMOD_Msk
#define ADC_CR_TMTRGMOD_Msk
Definition: Nano1X2Series.h:807
ADC_EnableInt
void ADC_EnableInt(ADC_T *adc, uint32_t u32Mask)
Enable the interrupt(s) selected by u32Mask parameter.
Definition: adc.c:167
ADC_CR_TRGS_Msk
#define ADC_CR_TRGS_Msk
Definition: Nano1X2Series.h:786
ADC_CR_TMPDMACNT_Msk
#define ADC_CR_TMPDMACNT_Msk
Definition: Nano1X2Series.h:816
ADC_DisableInt
void ADC_DisableInt(ADC_T *adc, uint32_t u32Mask)
Disable the interrupt(s) selected by u32Mask parameter.
Definition: adc.c:190
ADC_TRIGGER_BY_EXT_PIN
#define ADC_TRIGGER_BY_EXT_PIN
Definition: adc.h:49
ADC_SMPLCNT1_INTCHSAMPCNT_Msk
#define ADC_SMPLCNT1_INTCHSAMPCNT_Msk
Definition: Nano1X2Series.h:891
ADC_Close
void ADC_Close(ADC_T *adc)
Disable ADC module.
Definition: adc.c:59
ADC_Open
void ADC_Open(ADC_T *adc, uint32_t u32InputMode, uint32_t u32OpMode, uint32_t u32ChMask)
This API configures ADC module to be ready for convert the input from selected channel.
Definition: adc.c:41
ADC_CMP0_INT
#define ADC_CMP0_INT
Definition: adc.h:56
ADC_CR_TMSEL_Pos
#define ADC_CR_TMSEL_Pos
Definition: Nano1X2Series.h:803
Nano1X2Series.h
Nano102/112 peripheral access layer header file. This file contains all the peripheral register's def...
ADC_CR_ADMD_Msk
#define ADC_CR_ADMD_Msk
Definition: Nano1X2Series.h:783
ADC_DisableTimerTrigger
void ADC_DisableTimerTrigger(ADC_T *adc)
Disable timer trigger ADC function.
Definition: adc.c:131
ADC_CR_DIFF_Msk
#define ADC_CR_DIFF_Msk
Definition: Nano1X2Series.h:798
ADC_SMPLCNT1_INTCHSAMPCNT_Pos
#define ADC_SMPLCNT1_INTCHSAMPCNT_Pos
Definition: Nano1X2Series.h:890
ADC_ADF_INT
#define ADC_ADF_INT
Definition: adc.h:55
ADC_SMPLCNT0_CH0SAMPCNT_Msk
#define ADC_SMPLCNT0_CH0SAMPCNT_Msk
Definition: Nano1X2Series.h:885
ADC_DisableHWTrigger
void ADC_DisableHWTrigger(ADC_T *adc)
Disable hardware trigger ADC function.
Definition: adc.c:103
ADC_T
Definition: Nano1X2Series.h:378
ADC_CR_TRGCOND_Msk
#define ADC_CR_TRGCOND_Msk
Definition: Nano1X2Series.h:789
ADC
#define ADC
Pointer to ADC register structure.
Definition: Nano1X2Series.h:10645
ADC_CR_TMPDMACNT_Pos
#define ADC_CR_TMPDMACNT_Pos
Definition: Nano1X2Series.h:815
ADC_CR_ADIE_Msk
#define ADC_CR_ADIE_Msk
Definition: Nano1X2Series.h:780
ADC_CMP1_INT
#define ADC_CMP1_INT
Definition: adc.h:57
ADC_CR_TRGE_Msk
#define ADC_CR_TRGE_Msk
Definition: Nano1X2Series.h:792
SYS
#define SYS
Pointer to SYS register structure.
Definition: Nano1X2Series.h:10650
ADC_CR_TMSEL_Msk
#define ADC_CR_TMSEL_Msk
Definition: Nano1X2Series.h:804
ADC_CR_REFSEL_Msk
#define ADC_CR_REFSEL_Msk
Definition: Nano1X2Series.h:810
ADC_CMPR_CMPIE_Msk
#define ADC_CMPR_CMPIE_Msk
Definition: Nano1X2Series.h:825
ADC_SetExtraSampleTime
void ADC_SetExtraSampleTime(ADC_T *adc, uint32_t u32ChNum, uint32_t u32SampleTime)
Configure the hardware trigger condition and enable hardware trigger.
Definition: adc.c:145