| Nano102_112 Series BSP V3.03.002 The Board Support Package for Nano102_112 Series

pdma.c
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1 /**************************************************************************/
12 #include "Nano1X2Series.h"
13
14
15
38 void PDMA_Open(uint32_t u32Mask)
39 {
40 PDMAGCR->GCRCSR |= (u32Mask << 8);
41 }
42
52 void PDMA_Close(void)
53 {
54 PDMAGCR->GCRCSR = 0;
55 }
56
68 void PDMA_SetTransferCnt(uint32_t u32Ch, uint32_t u32Width, uint32_t u32TransCount)
69 {
70 PDMA_T *pdma;
71 pdma = (PDMA_T *)((uint32_t) PDMA0_BASE + (0x100 * u32Ch));
72 pdma->CSR = (pdma->CSR & ~PDMA_CSR_APB_TWS_Msk) | u32Width;
73 switch (u32Width)
74 {
75 case PDMA_WIDTH_32:
76 pdma->BCR = (u32TransCount << 2);
77 break;
78
79 case PDMA_WIDTH_8:
80 pdma->BCR = u32TransCount;
81 break;
82
83 case PDMA_WIDTH_16:
84 pdma->BCR = (u32TransCount << 1);
85 break;
86
87 default:
88 ;
89 }
90 }
91
105 void PDMA_SetTransferAddr(uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl)
106 {
107 PDMA_T *pdma;
108 pdma = (PDMA_T *)((uint32_t) PDMA0_BASE + (0x100 * u32Ch));
109
110 pdma->SAR = u32SrcAddr;
111 pdma->DAR = u32DstAddr;
112 pdma->CSR = (pdma->CSR & ~(PDMA_CSR_SAD_SEL_Msk|PDMA_CSR_DAD_SEL_Msk)) | (u32SrcCtrl | u32DstCtrl);
113 }
114
131 void PDMA_SetTransferMode(uint32_t u32Ch, uint32_t u32Peripheral, uint32_t u32ScatterEn, uint32_t u32DescAddr)
132 {
133 PDMA_T *pdma;
134 pdma = (PDMA_T *)((uint32_t) PDMA0_BASE + (0x100 * u32Ch));
135
136 switch (u32Ch)
137 {
138 case 1:
139 PDMAGCR->DSSR0 = (PDMAGCR->DSSR0 & ~DMA_GCR_DSSR0_CH1_SEL_Msk) | (u32Peripheral << DMA_GCR_DSSR0_CH1_SEL_Pos);
140 break;
141 case 2:
142 PDMAGCR->DSSR0 = (PDMAGCR->DSSR0 & ~DMA_GCR_DSSR0_CH2_SEL_Msk) | (u32Peripheral << DMA_GCR_DSSR0_CH2_SEL_Pos);
143 break;
144 case 3:
145 PDMAGCR->DSSR0 = (PDMAGCR->DSSR0 & ~DMA_GCR_DSSR0_CH3_SEL_Msk) | (u32Peripheral << DMA_GCR_DSSR0_CH3_SEL_Pos);
146 break;
147 case 4:
148 PDMAGCR->DSSR1 = (PDMAGCR->DSSR1 & ~DMA_GCR_DSSR1_CH4_SEL_Msk) | u32Peripheral;
149 break;
150 default:
151 ;
152 }
153 if (u32Peripheral == PDMA_MEM)
154 pdma->CSR &= ~PDMA_CSR_MODE_SEL_Msk;
155 else if (u32Peripheral & 0x10)
156 pdma->CSR = (pdma->CSR & ~PDMA_CSR_MODE_SEL_Msk) | 0x4; /* IP to memory */
157 else
158 pdma->CSR = (pdma->CSR & ~PDMA_CSR_MODE_SEL_Msk) | 0x8; /* memory to IP */
159 }
160
172 void PDMA_SetTimeOut(uint32_t u32Ch, uint32_t u32OnOff, uint32_t u32TimeOutCnt)
173 {
174 PDMA_T *pdma;
175 pdma = (PDMA_T *)((uint32_t) PDMA0_BASE + (0x100 * u32Ch));
176
177 pdma->TCR = (pdma->TCR & ~PDMA_TCR_PDMA_TCR_Msk) | u32TimeOutCnt;
178 pdma->CSR = (pdma->CSR & ~PDMA_CSR_TO_EN_Msk) | (u32OnOff << PDMA_CSR_TO_EN_Pos);
179
180 }
181
191 void PDMA_Trigger(uint32_t u32Ch)
192 {
193 PDMA_T *pdma;
194 pdma = (PDMA_T *)((uint32_t) PDMA0_BASE + (0x100 * u32Ch));
195
196 pdma->CSR |= (PDMA_CSR_TRIG_EN_Msk | PDMA_CSR_PDMACEN_Msk);
197 }
198
209 void PDMA_EnableInt(uint32_t u32Ch, uint32_t u32Mask)
210 {
211 PDMA_T *pdma;
212 pdma = (PDMA_T *)((uint32_t) PDMA0_BASE + (0x100 * u32Ch));
213
214 pdma->IER |= u32Mask;
215 }
216
227 void PDMA_DisableInt(uint32_t u32Ch, uint32_t u32Mask)
228 {
229 PDMA_T *pdma;
230 pdma = (PDMA_T *)((uint32_t) PDMA0_BASE + (0x100 * u32Ch));
231
232 pdma->IER &= ~u32Mask;
233 }
234
235 /* end of group NANO1X2_PDMA_EXPORTED_FUNCTIONS */
237 /* end of group NANO1X2_PDMA_Driver */
239 /* end of group NANO1X2_Device_Driver */
241
242 /*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
PDMA_T::DAR
__IO uint32_t DAR
Definition: Nano1X2Series.h:2140
PDMA_T::CSR
__IO uint32_t CSR
Definition: Nano1X2Series.h:2114
PDMA_WIDTH_32
#define PDMA_WIDTH_32
Definition: pdma.h:38
DMA_GCR_DSSR0_CH1_SEL_Msk
#define DMA_GCR_DSSR0_CH1_SEL_Msk
Definition: Nano1X2Series.h:2355
PDMA_MEM
#define PDMA_MEM
Definition: pdma.h:69
PDMA_CSR_APB_TWS_Msk
#define PDMA_CSR_APB_TWS_Msk
Definition: Nano1X2Series.h:2407
PDMA_CSR_TO_EN_Pos
#define PDMA_CSR_TO_EN_Pos
Definition: Nano1X2Series.h:2403
PDMA_CSR_TO_EN_Msk
#define PDMA_CSR_TO_EN_Msk
Definition: Nano1X2Series.h:2404
PDMA_TCR_PDMA_TCR_Msk
#define PDMA_TCR_PDMA_TCR_Msk
Definition: Nano1X2Series.h:2455
DMA_GCR_DSSR0_CH2_SEL_Pos
#define DMA_GCR_DSSR0_CH2_SEL_Pos
Definition: Nano1X2Series.h:2357
PDMA_WIDTH_16
#define PDMA_WIDTH_16
Definition: pdma.h:37
PDMA_T
Definition: Nano1X2Series.h:2060
PDMA_CSR_TRIG_EN_Msk
#define PDMA_CSR_TRIG_EN_Msk
Definition: Nano1X2Series.h:2410
DMA_GCR_DSSR0_CH1_SEL_Pos
#define DMA_GCR_DSSR0_CH1_SEL_Pos
Definition: Nano1X2Series.h:2354
PDMA_T::IER
__IO uint32_t IER
Definition: Nano1X2Series.h:2214
PDMA_CSR_DAD_SEL_Msk
#define PDMA_CSR_DAD_SEL_Msk
Definition: Nano1X2Series.h:2401
PDMA_EnableInt
void PDMA_EnableInt(uint32_t u32Ch, uint32_t u32Mask)
Enable Interrupt.
Definition: pdma.c:209
PDMAGCR
#define PDMAGCR
Pointer to PDMA global control register structure.
Definition: Nano1X2Series.h:10664
Nano1X2Series.h
Nano102/112 peripheral access layer header file. This file contains all the peripheral register's def...
DMA_GCR_DSSR0_CH2_SEL_Msk
#define DMA_GCR_DSSR0_CH2_SEL_Msk
Definition: Nano1X2Series.h:2358
PDMA_Trigger
void PDMA_Trigger(uint32_t u32Ch)
Trigger PDMA.
Definition: pdma.c:191
PDMA_Close
void PDMA_Close(void)
PDMA Close.
Definition: pdma.c:52
PDMA_Open
void PDMA_Open(uint32_t u32Mask)
PDMA Open.
Definition: pdma.c:38
DMA_GCR_DSSR0_CH3_SEL_Pos
#define DMA_GCR_DSSR0_CH3_SEL_Pos
Definition: Nano1X2Series.h:2360
PDMA0_BASE
#define PDMA0_BASE
PDMA0 register base address.
Definition: Nano1X2Series.h:10614
PDMA_CSR_PDMACEN_Msk
#define PDMA_CSR_PDMACEN_Msk
Definition: Nano1X2Series.h:2389
DMA_GCR_DSSR0_CH3_SEL_Msk
#define DMA_GCR_DSSR0_CH3_SEL_Msk
Definition: Nano1X2Series.h:2361
DMA_GCR_DSSR1_CH4_SEL_Msk
#define DMA_GCR_DSSR1_CH4_SEL_Msk
Definition: Nano1X2Series.h:2364
PDMA_CSR_MODE_SEL_Msk
#define PDMA_CSR_MODE_SEL_Msk
Definition: Nano1X2Series.h:2395
PDMA_T::BCR
__IO uint32_t BCR
Definition: Nano1X2Series.h:2153
PDMA_T::TCR
__IO uint32_t TCR
Definition: Nano1X2Series.h:2262
PDMA_SetTransferAddr
void PDMA_SetTransferAddr(uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl)
Set PDMA Transfer Address.
Definition: pdma.c:105
PDMA_SetTransferMode
void PDMA_SetTransferMode(uint32_t u32Ch, uint32_t u32Periphral, uint32_t u32ScatterEn, uint32_t u32DescAddr)
Set PDMA Transfer Mode.
Definition: pdma.c:131
PDMA_SetTransferCnt
void PDMA_SetTransferCnt(uint32_t u32Ch, uint32_t u32Width, uint32_t u32TransCount)
Set PDMA Transfer Count.
Definition: pdma.c:68
PDMA_CSR_SAD_SEL_Msk
#define PDMA_CSR_SAD_SEL_Msk
Definition: Nano1X2Series.h:2398
PDMA_WIDTH_8
#define PDMA_WIDTH_8
Definition: pdma.h:36
PDMA_T::SAR
__IO uint32_t SAR
Definition: Nano1X2Series.h:2127
PDMA_DisableInt
void PDMA_DisableInt(uint32_t u32Ch, uint32_t u32Mask)
Disable Interrupt.
Definition: pdma.c:227
PDMA_SetTimeOut
void PDMA_SetTimeOut(uint32_t u32Ch, uint32_t u32OnOff, uint32_t u32TimeOutCnt)
Set PDMA Timeout.
Definition: pdma.c:172