| Nano102_112 Series BSP V3.03.002 The Board Support Package for Nano102_112 Series

Data Fields
TIMER_T Struct Reference

`#include <Nano1X2Series.h>`

## Data Fields
__IO uint32_t | CTL
__IO uint32_t | PRECNT
__IO uint32_t | CMPR
__IO uint32_t | IER
__IO uint32_t | ISR
__IO uint32_t | DR
__I uint32_t | TCAP
uint32_t | RESERVE0 [1]
__IO uint32_t | ECTL

## Detailed Description

    @addtogroup TIMER Timer Controller(TIMER)
    Memory Mapped Structure for TMR Controller

Definition at line 9027 of file Nano1X2Series.h.

## Field Documentation

## ◆ CMPR

__IO uint32_t TIMER_T::CMPR

# CMPR

## Offset: 0x08 Timer x Compare Register

Bits | Field | Descriptions
--- | --- | ---
[23:0] | TMR_CMP | Timer Compared Value
|  | TMR_CMP is a 24-bit compared register.
|  | When the internal 24-bit up-counter counts and its value is equal to TMR_CMP value, a Timer Interrupt is requested if the timer interrupt is enabled with TMR_EN (TMRx_CTL [0]) is enabled.
|  | The TMR_CMP value defines the timer counting cycle time.
|  | Time-out period = (Period of timer clock input) * (8-bit PRESCALE_CNT + 1) * (24-bit TMR_CMP).
|  | Note1: Never write 0x0 or 0x1 in TMR_CMP, or the core will run into unknown state.
|  | Note2: No matter TMR_EN (TMRx_CTL [0]) is 0 or 1, whenever software write a new value into this register, TIMER will restart counting using this new value and abort previous count.

Definition at line 9208 of file Nano1X2Series.h.

## ◆ CTL

__IO uint32_t TIMER_T::CTL

# CTL

## Offset: 0x00 Timer x Control Register

Bits | Field | Descriptions
--- | --- | ---
[0] | TMR_EN | Timer Counter Enable Control
|  | 0 = Stops/Suspends counting.
|  | 1 = Starts counting.
|  | Note1: Set TMR_EN to 1 enables 24-bit counter keeps up counting from the last stop counting value.
|  | Note2: This bit is auto-cleared by hardware in one-shot mode (MODE_SEL (TMRx_CTL[5:4]) = 00) once the value of 24-bit up counter equals the TMRx_CMPR.
[1] | SW_RST | Software Reset
|  | Set this bit will reset the timer counter, pre-scale counter and also force TMR_EN (TMRx_CTL [0]) to 0.
|  | 0 = No effect.
|  | 1 = Reset Timer's pre-scale counter, internal 24-bit up-counter and TMR_EN (TMRx_CTL [0]) bit.
|  | Note: This bit will be auto cleared and takes at least 3 TMRx_CLK clock cycles.
[2] | WAKE_EN | Wake-Up Enable Control
|  | When WAKE_EN is set and the TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) is set, the timer controller will generate a wake-up trigger event to CPU.
|  | 0 = Wake-up trigger event Disabled.
|  | 1 = Wake-up trigger event Enabled.
[3] | DBGACK_EN | ICE Debug Mode Acknowledge Ineffective Enable Control
|  | 0 = ICE debug mode acknowledgement effects TIMER counting and TIMER counter will be held while ICE debug mode acknowledged.
|  | 1 = ICE debug mode acknowledgement is ineffective and TIMER counter will keep going no matter ICE debug mode acknowledged or not.
[5:4] | MODE_SEL | Timer Operating Mode Select
|  | 00 = The timer is operating in the one-shot mode.
|  | In this mode, the associated interrupt signal is generated (if TMR_IER [TMR_IE] is enabled) once the value of 24-bit up counter equals the TMRx_CMPR.
|  | And TMR_CTL [TMR_EN] is automatically cleared by hardware.
|  | 01 = The timer is operating in the periodic mode.
|  | In this mode, the associated interrupt signal is generated periodically (if TMR_IER [TMR_IE] is enabled) while the value of 24-bit up counter equals the TMRx_CMPR.
|  | After that, the 24-bit counter will be reset and starts counting from zero again.
|  | 10 = The timer is operating in the periodic mode with output toggling.
|  | In this mode, the associated interrupt signal is generated periodically (if TMR_IER [TMR_IE] is enabled) while the value of 24-bit up counter equals the TMRx_CMPR.
|  | After that, the 24-bit counter will be reset and starts counting from zero again.
|  | At the same time, timer controller will also toggle the output pin TMRx_TOG_OUT to its inverse level (from low to high or from high to low).
|  | Note: The default level of TMRx_TOG_OUT after reset is low.
|  | 11 = The timer is operating in continuous counting mode.
|  | In this mode, the associated interrupt signal is generated when TMR_DR = TMR_CMPR (if TMR_IER [TMR_IE] is enabled).
|  | However, the 24-bit up-counter counts continuously without reset.
[6] | ACMP_EN_TMR | ACMP Trigger Timer Enable Control
|  | This bit high enables the functionality that when ACMP0 is in sigma-delta mode, it could enable Timer.
|  | 0 = ACMP0 trigger timer functionality disabled.
|  | 1 = ACMP0 trigger timer functionality enabled.
[7] | TMR_ACT | Timer Active Status Bit (Read Only)
|  | This bit indicates the timer counter status of timer.
|  | 0 = Timer is not active.
|  | 1 = Timer is in active.
[8] | ADC_TEEN | Timer Trigger ADC Enable Control
|  | This bit controls if TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) could trigger ADC.
|  | When ADC_TEEN is set, TMR_IS (TMRx_ISR[0]) is set and the CAP_TRG_EN (TMRx_CTL[11]) is low, the timer controller will generate an internal trigger event to ADC controller.
|  | When ADC_TEEN is set, TCAP_IS (TMRx_ISR[1]) is set and the CAP_TRG_EN (TMRx_CTL[11]) is high, the timer controller will generate an internal trigger event to ADC controller.
|  | 0 = TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) trigger ADC Disabled.
|  | 1 = TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) trigger ADC Enabled.
[10] | PDMA_TEEN | Timer Trigger PDMA Enable Control
|  | This bit controls if TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) could trigger PDMA.
|  | When PDMA_TEEN is set, TMR_IS (TMRx_ISR[0]) is set and the CAP_TRG_EN (TMRx_CTL[11]) is low, the timer controller will generate an internal trigger event to PDMA controller.
|  | When PDMA_TEEN is set, TCAP_IS (TMRx_ISR[1]) is set and the CAP_TRG_EN (TMRx_CTL[11]) is high, the timer controller will generate an internal trigger event to PDMA controller.
|  | 0 = TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) trigger PDMA Disabled.
|  | 1 = TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) trigger PDMA Enabled.
[11] | CAP_TRG_EN | TCAP_IS Trigger Mode Enable
|  | This bit controls if the TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) is used to trigger PDMA and ADC while TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) is set.
|  | If this bit is low and TMR_IS (TMRx_ISR[0]) is set, timer will generate an internal trigger event to PDMA or ADC while related trigger enable bit (PDMA_TEEN (TMRx_CTL[10]) or ADC_TEEN (TMRx_CTL[8])) is set.
|  | If this bit is set high and TCAP_IS (TMRx_ISR[0]) is set, timer will generate an internal trigger event to PDMA or ADC while related trigger enable bit (PDMA_TEEN (TMRx_CTL[10]) or ADC_TEEN (TMRx_CTL[8])) is set.
|  | 0 = TMR_IS (TMRx_ISR[0]) is used to trigger PDMA and ADC.
|  | 1 = TCAP_IS (TMRx_ISR[1]) is used to trigger PDMA and ADC.
[12] | EVENT_EN | Event Counting Mode Enable Control
|  | When EVENT_EN is set, the increase of 24-bit up-counting timer is controlled by external event pin.
|  | While the transition of external event pin matches the definition of EVENT_EDGE (TMRx_CTL[13]), the 24-bit up-counting timer increases by 1.
|  | Or, the 24-bit up-counting timer will keep its value unchanged.
|  | 0 = Timer counting is not controlled by external event pin.
|  | 1 = Timer counting is controlled by external event pin.
[13] | EVENT_EDGE | Event Counting Mode Edge Selection
|  | This bit indicates which edge of external event pin enabling the timer to increase 1.
|  | 0 = A falling edge of external event enabling the timer to increase 1.
|  | 1 = A rising edge of external event enabling the timer to increase 1.
[14] | EVNT_DEB_EN | External Event De-Bounce Enable Control
|  | When EVNT_DEB_EN is set, the external event pin de-bounce circuit will be enabled to eliminate the bouncing of the signal.
|  | In de-bounce circuit the external event pin will be sampled 4 times by TMRx_CLK.
|  | 0 = De-bounce circuit Disabled.
|  | 1 = De-bounce circuit Enabled.
|  | Note: When EVENT_EN (TMRx_CTL[12]) is enabled, enable this bit is recommended.
|  | And, while EVENT_EN (TMRx_CTL[12]) is disabled, disable this bit is recommended to save power consumption.
[16] | TCAP_EN | TC Pin Functional Enable Control
|  | This bit controls if the transition on TC pin could be used as timer counter reset function or timer capture function.
|  | 0 = The transition on TC pin is ignored.
|  | 1 = The transition on TC pin will result in the capture or reset of 24-bit timer counter.
|  | Note: For TMRx_CTL, if INTR_TRG_EN (TMRx_CTL[24]) is set, the TCAP_EN will be forced to low and the TC pin transition is ignored (where x = 0 or 2).
|  | Note: For TMRx+1_CTL, if INTR_TRG_EN (TMRx_CTL[24]) is set, the TCAP_EN will be forced to high (where x = 0 or 2).
[17] | TCAP_MODE | TC Pin Function Mode Selection
|  | This bit indicates if the transition on TC pin is used as timer counter reset function or timer capture function.
|  | 0 = The transition on TC pin is used as timer capture function.
|  | 1 = The transition on TC pin is used as timer counter reset function.
|  | Note: For TMRx+1_CTL, if INTR_TRG_EN (TMRx_CTL[24]) is set, the TCAP_MODE will be forced to low (where x = 0 or 2).
[19:18] | TCAP_EDGE | TC Pin Edge Detect Selection
|  | This field defines that active transition of Tcapture pin is for timer counter reset function or for timer capture function.
|  | For timer counter reset function and free-counting mode of timer capture function, the configurations are:
|  | 00 = A falling edge (1 to 0 transition) on Tcapture pin is an active transition.
|  | 01 = A rising edge (0 to 1 transition) on Tcapture pin is an active transition.
|  | 10 = Both falling edge (1 to 0 transition) and rising edge (0 to 1 transition) on Tcapture pin are active transitions.
|  | 11 = Both falling edge (1 to 0 transition) and rising edge (0 to 1 transition) on Tcapture pin are active transitions.
|  | For trigger-counting mode of timer capture function, the configurations are:
|  | 00 = 1st falling edge on Tcapture pin triggers 24-bit timer to start counting, while 2nd falling edge triggers 24-bit timer to stop counting.
|  | 01 = 1st rising edge on Tcapture pin triggers 24-bit timer to start counting, while 2nd rising edge triggers 24-bit timer to stop counting.
|  | 10 = Falling edge on Tcapture pin triggers 24-bit timer to start counting, while rising edge triggers 24-bit timer to stop counting.
|  | 11 = Rising edge on Tcapture pin triggers 24-bit timer to start counting, while falling edge triggers 24-bit timer to stop counting.
|  | Note: For TMRx+1_CTL, if INTR_TRG_EN is set, the TCAP_EDGE will be forced to 11.
[20] | TCAP_CNT_MOD | Timer Capture Counting Mode Selection
|  | This bit indicates the behavior of 24-bit up-counting timer while TCAP_EN (TMRx_CTL[16]) is set to high.
|  | If this bit is 0, the free-counting mode, the behavior of 24-bit up-counting timer is defined by MODE_SEL (TMRx_CTL[5:4]) field.
|  | When TCAP_EN (TMRx_CTL[16]) is set, TCAP_MODE (TMRx_CTL[17]) is 0, and the transition of TC pin matches the TCAP_EDGE (TMRx_CTL[19:18]) setting, the value of 24-bit up-counting timer will be saved into register TMRx_TCAP.
|  | If this bit is 1, Trigger-counting mode, 24-bit up-counting timer will be not counting and keep its value at 0.
|  | When TCAP_EN (TMRx_CTL[16]) is set, TCAP_MODE (TMRx_CTL[17]) is 0, and once the transition of external pin matches the 1st transition of TCAP_EDGE (TMRx_CTL[19:18]) setting, the 24-bit up-counting timer will start counting.
|  | And then if the transition of external pin matches the 2nd transition of TCAP_EDGE (TMRx_CTL[19:18]) setting, the 24-bit up-counting timer will stop counting.
|  | And its value will be saved into register TMRx_TCAP.
|  | 0 = Capture with free-counting timer mode.
|  | 1 = Capture with trigger-counting timer mode.
|  | Note: For TMRx+1_CTL, if INTR_TRG_EN (TMRx_CTL[24]) is set, the TCAP_CNT_MOD will be forced to high, the capture with Trigger-counting Timer mode (where x = 0 or 2).
[22] | TCAP_DEB_EN | TC Pin De-Bounce Enable Control
|  | When CAP_DEB_EN (TMRx_CTL[22]) is set, the TC pin de-bounce circuit will be enabled to eliminate the bouncing of the signal.
|  | In de-bounce circuit the TC pin signal will be sampled 4 times by TMRx_CLK.
|  | 0 = De-bounce circuit Disabled.
|  | 1 = De-bounce circuit Enabled.
|  | Note: When TCAP_EN (TMRx_CTL[16]) is enabled, enable this bit is recommended.
|  | And, while TCAP_EN (TMRx_CTL[16]) is disabled, disable this bit is recommended to save power consumption.
|  | Note: When CAP_SRC (TMRx_ECTL[16]) is high, the capture signal is from internal of chip and the de-bounce circuit would not take effect no matter this bit is high or low.
|  | Note: For Timer 1 and 3, when INTR_TRG_EN (TMRx_CTL[24]) is high, the capture signal is from internal of chip and the de-bounce circuit would not take effect no matter this bit is high or low.
[24] | INTR_TRG_EN | Inter-Timer Trigger Function Enable Control
|  | This bit controls if Inter-timer Trigger function is enabled.
|  | If Inter-timer Trigger function is enabled, the TMRx will be in counter mode and counting with external Clock Source or event.
|  | In addition, TMRx+1 will be in trigger-counting mode of capture function.
|  | 0 = Inter-timer trigger function Disabled.
|  | 1 = Inter-timer trigger function Enabled.
|  | Note: For TMRx+1_CTL, this bit is ignored and the read back value is always 0.
[25] | INTR_TRG_MODE | Inter-Timer Trigger Mode Selection
|  | This bit controls the timer operation mode when inter-timer trigger function is enabled.
|  | When this bit is low, the TMRx will be in counter mode and counting with external Clock Source or event.
|  | In addition, TMRx+1 will be in trigger-counting mode of capture function.
|  | In this mode, TMRx_CMPR control when inter-timer trigger function terminated.
|  | When this bit is high, the TMRx will be in counter mode and counting with external Clock Source or event.
|  | In addition, TMRx+1 will be in trigger-counting mode of capture function.
|  | In this mode, TMRx+1_CMPR control when inter-timer trigger function terminated.
|  | In this mode, TMRx would ignore some incoming event based on the EVNT_DROP_CNT (TMRx_ECTL[31:24]).
|  | And once the TMRx+1 counter value equal or large than TMRx+1_CMPR, TMRx would terminate the operation when next incoming event received.
|  | 0 = Inter-Timer Trigger function wouldn't ignore any incoming event.
|  | 1 = Inter-Timer Trigger function would ignore incoming event based on the EVNT_DROP_CNT (TMRx_ECTL[31:24]).
|  | Note: For TMRx+1_CTL, this bit is ignored and the read back value is always 0.

Definition at line 9178 of file Nano1X2Series.h.

## ◆ DR

__IO uint32_t TIMER_T::DR

# DR

## Offset: 0x14 Timer 0 Data Register

Bits | Field | Descriptions
--- | --- | ---
[23:0] | TDR | Timer Data Register (Read)
|  | User can read this register for internal 24-bit timer up-counter value.
|  | Counter Reset (Write)
|  | User can write any value to this register to reset internal 24-bit timer up-counter and 8-bit pre-scale counter.
|  | This reset operation wouldn't affect any other timer control registers and circuit.
|  | After reset completed, the 24-bit timer up-counter and 8-bit pre-scale counter restart the counting based on the TMRx_CTL register setting.
[31] | RSTACT | Reset Active
|  | This bit indicates if the counter reset operation active.
|  | When user write this register, timer starts to reset its internal 24-bit timer up-counter and 8-bit pre-scale counter to 0.
|  | In the same time, timer set this flag to 1 to indicate the counter reset operation is in progress.
|  | Once the counter reset operation done, timer clear this bit to 0 automatically.
|  | 0 = Reset operation done.
|  | 1 = Reset operation triggered by writing TMR_DR is in progress.
|  | Note: This bit is read only. Write operation wouldn't take any effect.

Definition at line 9287 of file Nano1X2Series.h.

## ◆ ECTL

__IO uint32_t TIMER_T::ECTL

# ECTL

## Offset: 0x20 Timer x Extended Control Register

Bits | Field | Descriptions
--- | --- | ---
[0] | EVNT_GEN_EN | Event Generator Function Enable Control
|  | When this bit is high, timer would generate a high pulse event out when it increases the 24-bit up counter and the polarity of signal defined by EVNT_GEN_SRC (TMRx_ECTL[12]) is same as the polarity defined by EVNT_GEN_POL (TMRx_ECTL[1]).
|  | 0 = Event generator function disabled.
|  | 1 = Event generator function enabled.
[1] | EVNT_GEN_POL | Event Generator Reference Input Source Polarity Selection
|  | When this bit is low and EVNT_GEN_EN (TMRx_ECTL[0]) is high, timer would generate a high pulse event out when it increases the 24-bit up counter and the polarity of signal defined by EVNT_GEN_SRC (TMRx_ECTL[12]) is low.
|  | When this bit is high and EVNT_GEN_EN (TMRx_ECTL[0]) is high, timer would generate a low pulse event pulse out when it increases the 24-bit up counter and the polarity of signal defined by EVNT_GEN_SRC (TMRx_ECTL[12]) is high.
|  | This bit only affects timer's operation when EVNT_GEN_EN (TMRx_ECTL[0]) is high.
|  | 0 = Timer generates a high pulse event out when it increase the 24-bit up counter and the polarity of signal defined by EVNT_GEN_SRC (TMRx_ECTL[12]) is low.
|  | 1 = Timer generates a high pulse event out when it increase the 24-bit up counter and the polarity of signal defined by EVNT_GEN_SRC (TMRx_ECTL[12]) is high.
[8] | EVNT_CNT_SRC | Event Counting Source Selection
|  | This bit defines the TMRx+1 event counting source is from external event pin TMx+1 or internal signal from TMRx's event generator output (where x = 0 or 2).
|  | 0 = The event counting source is from external event pin.
|  | 1 = The event counting source is from TMRx's event generator output.
|  | Note: This bit is only available in TMRx+1 (where x = 0 or 2).
[12] | EVNT_GEN_SRC | Event Generator Reference Input Source Selection
|  | This bit defines the event generator function controlled by external event pin or internal event signals from ACMP0.
|  | 0 = The event generator reference source is from external event pin.
|  | 1 = The event generator reference source is from ACMP0.
|  | Note: This bit is only available in TMRx (where x = 0 or 2).
[16] | CAP_SRC | Capture Function Source Selection
|  | This bit defines timer counter reset function or timer capture function controlled by transition of TC pin or transition of internal signals from other functional blocks of this chip.
|  | 0 = Transition of TC pin selected.
|  | 1 = Transition of internal signals from ACMP0.
|  | Note: When this bit is high, the EVNT_DEB_EN (TMRx_CTL[14]) would not take effect.
[31:24] | EVNT_DROP_CNT | Event Drop Count
|  | This field indicates timer to drop how many events after inter-timer trigger function enable.
|  | For example, if user writes 0x7 to this field, timer would drop 7 first incoming events and starts the inter-timer trigger operation when it get 8th event.
|  | This field would affect timer's operation only when inter-timer trigger function enabled (INTR_TRG_EN (TMRx_CTL[24]) = 1) and ITNR_TRG_MODE (TMRx_CTL[25]) = 1.

Definition at line 9343 of file Nano1X2Series.h.

## ◆ IER

__IO uint32_t TIMER_T::IER

# IER

## Offset: 0x0C Timer x Interrupt Enable Register

Bits | Field | Descriptions
--- | --- | ---
[0] | TMR_IE | Timer Interrupt Enable Control
|  | 0 = Timer Interrupt Disabled.
|  | 1 = Timer Interrupt Enabled.
|  | Note: If timer interrupt is enabled, the timer asserts its interrupt signal when the associated counter is equal to TMR_CMPR.
[1] | TCAP_IE | Timer Capture Function Interrupt Enable Control
|  | 0 = Timer External Pin Function Interrupt Disabled.
|  | 1 = Timer External Pin Function Interrupt Enabled.
|  | Note: If timer external pin function interrupt is enabled, the timer asserts its interrupt signal when the TCAP_EN (TMRx_CTL[16]) is set and the transition of external pin matches the TCAP_EDGE (TMRx_CTL[19:18]) setting

Definition at line 9226 of file Nano1X2Series.h.

## ◆ ISR

__IO uint32_t TIMER_T::ISR

# ISR

## Offset: 0x10 Timer x Interrupt Status Register

Bits | Field | Descriptions
--- | --- | ---
[0] | TMR_IS | Timer Interrupt Status
|  | This bit indicates the interrupt status of Timer.
|  | This bit is set by hardware when the up counting value of internal 24-bit counter matches the timer compared value (TMR_CMPR).
|  | Write 1 to clear this bit to 0.
|  | If this bit is active and TMR_IE (TMRx_IER[0]) is enabled, Timer will trigger an interrupt to CPU.
[1] | TCAP_IS | Timer Capture Function Interrupt Status
|  | This bit indicates the external pin function interrupt status of Timer.
|  | This bit is set by hardware when TCAP_EN (TMRx_CTL[16]) is set high, and the transition of external pin matches the TCAP_EDGE (TMRx_CTL[19:18]) setting.
|  | Write 1 to clear this bit to 0.
|  | If this bit is active and TCAP_IE (TMRx_IER[1]) is enabled, Timer will trigger an interrupt to CPU.
[4] | TMR_WAKE_STS | Timer Wake-Up Status
|  | If timer causes CPU wakes up from power-down mode, this bit will be set to high.
|  | It must be cleared by software with a write 1 to this bit.
|  | 0 = Timer does not cause system wake-up.
|  | 1 = Wakes system up from power-down mode by Timer timeout.
[5] | NCAP_DET_STS | New Capture Detected Status
|  | This status is to indicate there is a new incoming capture event detected before CPU clearing the TCAP_IS (TMRx_ISR[1]) status.
|  | If the above condition occurred, the Timer will keep register TMRx_TCAP unchanged and drop the new capture value.
|  | Write 1 to clear this bit to 0.
|  | 0 = New incoming capture event didn't detect before CPU clearing TCAP_IS (TMRx_ISR[1]) status.
|  | 1 = New incoming capture event detected before CPU clearing TCAP_IS (TMRx_ISR[1]) status.
[6] | TCAP_IS_FEDGE | TC Pin Edge Detect Is Falling
|  | This flag indicates the edge detected in TC pin is rising edge or falling edge.
|  | Timer only updates this flag when it updates the Timer Capture Data (TMR_TCAP[23:0]) value.
|  | When a new incoming capture event detected before CPU clearing the TCAP_IS (TMRx_ISR[1]) status, Timer will keep this bit unchanged.
|  | 0 = TC pin edge detected is rising edge.
|  | 1 = TC pin edge detected is falling edge.

Definition at line 9263 of file Nano1X2Series.h.

## ◆ PRECNT

__IO uint32_t TIMER_T::PRECNT

# PRECNT

## Offset: 0x04 Timer x Pre-Scale Counter Register

Bits | Field | Descriptions
--- | --- | ---
[7:0] | PRESCALE_CNT | Pre-Scale Counter
|  | Clock input is divided by PRESCALE_CNT + 1 before it is fed to the counter.
|  | If PRESCALE_CNT =0, then there is no scaling.

Definition at line 9191 of file Nano1X2Series.h.

## ◆ RESERVE0

uint32_t TIMER_T::RESERVE0[1]

Definition at line 9303 of file Nano1X2Series.h.

## ◆ TCAP

__I uint32_t TIMER_T::TCAP

# TCAP

## Offset: 0x18 Timer x Capture Data Register

Bits | Field | Descriptions
--- | --- | ---
[23:0] | CAP | Timer Capture Data Register
|  | When TCAP_EN (TMRx_CTL[16]) is set, TCAP_MODE (TMRx_CTL[17]) is 0, TCAP_CNT_MOD (TMRx_CTL[20]) is 0, and the transition of external pin matches the TCAP_EDGE (TMRx_CTL[19:18]) setting, the value of 24-bit up-counting timer will be saved into register TMRx_TCAP.
|  | When TCAP_EN (TMRx_CTL[16]) is set, TCAP_MODE (TMRx_CTL[17]) is 0, TCAP_CNT_MOD (TMRx_CTL[20]) is 1, and the transition of external pin matches the 2nd transition of TCAP_EDGE (TMRx_CTL[19:18]) setting, the value of 24-bit up-counting timer will be saved into register TMRx_TCAP.
|  | User can read this register to get the counter value.
|  | When a new incoming capture event detected before CPU clearing the TCAP_IS (TMRxISR[1]) status, Timer will keep this filed value unchanged and drop the new capture value.

Definition at line 9302 of file Nano1X2Series.h.

The documentation for this struct was generated from the following file:

- Device/Nuvoton/Nano1X2Series/Include/Nano1X2Series.h