| Nano102_112 Series BSP V3.03.002 The Board Support Package for Nano102_112 Series

Macros
CLK Exported Constants
NANO102/112 Device Driver » CLK Driver

## Macros
#define | FREQ_32MHZ 32000000
#define | FREQ_16MHZ 16000000
#define | CLK_PWRCTL_HXT_EN ((uint32_t)0x00000001)
#define | CLK_PWRCTL_LXT_EN ((uint32_t)0x00000002)
#define | CLK_PWRCTL_HIRC_EN ((uint32_t)0x00000004)
#define | CLK_PWRCTL_LIRC_EN ((uint32_t)0x00000008)
#define | CLK_PWRCTL_DELY_EN ((uint32_t)0x00000010)
#define | CLK_PWRCTL_WAKEINT_EN ((uint32_t)0x00000020)
#define | CLK_PWRCTL_PWRDOWN_EN ((uint32_t)0x00000040)
#define | CLK_PWRCTL_HXT_SELXT ((uint32_t)0x00000100)
#define | CLK_PWRCTL_HXT_GAIN_8M ((uint32_t)0x00000000)
#define | CLK_PWRCTL_HXT_GAIN_8M_12M ((uint32_t)0x00000400)
#define | CLK_PWRCTL_HXT_GAIN_12M_16M ((uint32_t)0x00000800)
#define | CLK_PWRCTL_HXT_GAIN_16M ((uint32_t)0x00000C00)
#define | CLK_AHBCLK_GPIO_EN ((uint32_t)0x00000001)
#define | CLK_AHBCLK_DMA_EN ((uint32_t)0x00000002)
#define | CLK_AHBCLK_ISP_EN ((uint32_t)0x00000004)
#define | CLK_AHBCLK_EBI_EN ((uint32_t)0x00000008)
#define | CLK_AHBCLK_SRAM_EN ((uint32_t)0x00000010)
#define | CLK_AHBCLK_TICK_EN ((uint32_t)0x00000020)
#define | CLK_APBCLK_WDT_EN ((uint32_t)0x00000001)
#define | CLK_APBCLK_RTC_EN ((uint32_t)0x00000002)
#define | CLK_APBCLK_TMR0_EN ((uint32_t)0x00000004)
#define | CLK_APBCLK_TMR1_EN ((uint32_t)0x00000008)
#define | CLK_APBCLK_TMR2_EN ((uint32_t)0x00000010)
#define | CLK_APBCLK_TMR3_EN ((uint32_t)0x00000020)
#define | CLK_APBCLK_FDIV_EN ((uint32_t)0x00000040)
#define | CLK_APBCLK_SC2_EN ((uint32_t)0x00000080)
#define | CLK_APBCLK_I2C0_EN ((uint32_t)0x00000100)
#define | CLK_APBCLK_I2C1_EN ((uint32_t)0x00000200)
#define | CLK_APBCLK_SPI0_EN ((uint32_t)0x00001000)
#define | CLK_APBCLK_SPI1_EN ((uint32_t)0x00002000)
#define | CLK_APBCLK_SPI2_EN ((uint32_t)0x00004000)
#define | CLK_APBCLK_UART0_EN ((uint32_t)0x00010000)
#define | CLK_APBCLK_UART1_EN ((uint32_t)0x00020000)
#define | CLK_APBCLK_PWM0_CH01_EN ((uint32_t)0x00100000)
#define | CLK_APBCLK_PWM0_CH23_EN ((uint32_t)0x00200000)
#define | CLK_APBCLK_DAC_EN ((uint32_t)0x02000000)
#define | CLK_APBCLK_LCD_EN ((uint32_t)0x04000000)
#define | CLK_APBCLK_USBD_EN ((uint32_t)0x08000000)
#define | CLK_APBCLK_ADC_EN ((uint32_t)0x10000000)
#define | CLK_APBCLK_I2S_EN ((uint32_t)0x20000000)
#define | CLK_APBCLK_SC0_EN ((uint32_t)0x40000000)
#define | CLK_APBCLK_SC1_EN ((uint32_t)0x80000000)
#define | CLK_CLKSTATUS_HXT_STB ((uint32_t)0x00000001)
#define | CLK_CLKSTATUS_LXT_STB ((uint32_t)0x00000002)
#define | CLK_CLKSTATUS_PLL_STB ((uint32_t)0x00000004)
#define | CLK_CLKSTATUS_LIRC_STB ((uint32_t)0x00000008)
#define | CLK_CLKSTATUS_HIRC_STB ((uint32_t)0x00000010)
#define | CLK_CLKSTATUS_CLK_SW_FAIL ((uint32_t)0x00000080)
#define | CLK_PLLCTL_PD ((uint32_t)0x00010000)
#define | CLK_PLLCTL_PLL_SRC_HXT ((uint32_t)(0x00000000))
#define | CLK_PLLCTL_PLL_SRC_HIRC ((uint32_t)(0x00020000))
#define | CLK_PLL_SRC_N(x) (((x)-1)<<8)
#define | CLK_PLL_MLP(x) ((x)<<0)
#define | CLK_PLLCTL_32MHz_HIRC (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLL_SRC_N(12) | CLK_PLL_MLP(32))
#define | CLK_PLLCTL_28MHz_HIRC (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLL_SRC_N(12) | CLK_PLL_MLP(28))
#define | CLK_PLLCTL_24MHz_HIRC (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLL_SRC_N(12) | CLK_PLL_MLP(24))
#define | CLK_PLLCTL_22MHz_HIRC (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLL_SRC_N(12) | CLK_PLL_MLP(22))
#define | CLK_PLLCTL_16MHz_HIRC (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLL_SRC_N(12) | CLK_PLL_MLP(16))
#define | CLK_CLKSEL0_HCLK_S_HXT (0UL<<CLK_CLKSEL0_HCLK_S_Pos)
#define | CLK_CLKSEL0_HCLK_S_LXT (1UL<<CLK_CLKSEL0_HCLK_S_Pos)
#define | CLK_CLKSEL0_HCLK_S_PLL (2UL<<CLK_CLKSEL0_HCLK_S_Pos)
#define | CLK_CLKSEL0_HCLK_S_LIRC (3UL<<CLK_CLKSEL0_HCLK_S_Pos)
#define | CLK_CLKSEL0_HCLK_S_HIRC (7UL<<CLK_CLKSEL0_HCLK_S_Pos)
#define | CLK_CLKSEL1_ADC_S_HXT (0x0UL<<CLK_CLKSEL1_ADC_S_Pos)
#define | CLK_CLKSEL1_ADC_S_LXT (0x1UL<<CLK_CLKSEL1_ADC_S_Pos)
#define | CLK_CLKSEL1_ADC_S_PLL (0x2UL<<CLK_CLKSEL1_ADC_S_Pos)
#define | CLK_CLKSEL1_ADC_S_HIRC (0x3UL<<CLK_CLKSEL1_ADC_S_Pos)
#define | CLK_CLKSEL1_ADC_S_HCLK (0x4UL<<CLK_CLKSEL1_ADC_S_Pos)
#define | CLK_CLKSEL1_LCD_S_LXT (0x0UL<<CLK_CLKSEL1_LCD_S_Pos)
#define | CLK_CLKSEL1_TMR1_S_HXT (0x0UL<<CLK_CLKSEL1_TMR1_S_Pos)
#define | CLK_CLKSEL1_TMR1_S_LXT (0x1UL<<CLK_CLKSEL1_TMR1_S_Pos)
#define | CLK_CLKSEL1_TMR1_S_LIRC (0x2UL<<CLK_CLKSEL1_TMR1_S_Pos)
#define | CLK_CLKSEL1_TMR1_S_EXT (0x3UL<<CLK_CLKSEL1_TMR1_S_Pos)
#define | CLK_CLKSEL1_TMR1_S_HIRC (0x4UL<<CLK_CLKSEL1_TMR1_S_Pos)
#define | CLK_CLKSEL1_TMR1_S_HCLK (0x5UL<<CLK_CLKSEL1_TMR1_S_Pos)
#define | CLK_CLKSEL1_TMR0_S_HXT (0x0UL<<CLK_CLKSEL1_TMR0_S_Pos)
#define | CLK_CLKSEL1_TMR0_S_LXT (0x1UL<<CLK_CLKSEL1_TMR0_S_Pos)
#define | CLK_CLKSEL1_TMR0_S_LIRC (0x2UL<<CLK_CLKSEL1_TMR0_S_Pos)
#define | CLK_CLKSEL1_TMR0_S_EXT (0x3UL<<CLK_CLKSEL1_TMR0_S_Pos)
#define | CLK_CLKSEL1_TMR0_S_HIRC (0x4UL<<CLK_CLKSEL1_TMR0_S_Pos)
#define | CLK_CLKSEL1_TMR0_S_HCLK (0x5UL<<CLK_CLKSEL1_TMR0_S_Pos)
#define | CLK_CLKSEL1_PWM0_CH01_S_HXT (0x0UL<<CLK_CLKSEL1_PWM0_CH01_S_Pos)
#define | CLK_CLKSEL1_PWM0_CH01_S_LXT (0x1UL<<CLK_CLKSEL1_PWM0_CH01_S_Pos)
#define | CLK_CLKSEL1_PWM0_CH01_S_HCLK (0x2UL<<CLK_CLKSEL1_PWM0_CH01_S_Pos)
#define | CLK_CLKSEL1_PWM0_CH01_S_HIRC (0x3UL<<CLK_CLKSEL1_PWM0_CH01_S_Pos)
#define | CLK_CLKSEL1_PWM0_CH23_S_HXT (0x0UL<<CLK_CLKSEL1_PWM0_CH23_S_Pos)
#define | CLK_CLKSEL1_PWM0_CH23_S_LXT (0x1UL<<CLK_CLKSEL1_PWM0_CH23_S_Pos)
#define | CLK_CLKSEL1_PWM0_CH23_S_HCLK (0x2UL<<CLK_CLKSEL1_PWM0_CH23_S_Pos)
#define | CLK_CLKSEL1_PWM0_CH23_S_HIRC (0x3UL<<CLK_CLKSEL1_PWM0_CH23_S_Pos)
#define | CLK_CLKSEL1_UART_S_HXT (0x0UL<<CLK_CLKSEL1_UART_S_Pos)
#define | CLK_CLKSEL1_UART_S_LXT (0x1UL<<CLK_CLKSEL1_UART_S_Pos)
#define | CLK_CLKSEL1_UART_S_PLL (0x2UL<<CLK_CLKSEL1_UART_S_Pos)
#define | CLK_CLKSEL1_UART_S_HIRC (0x3UL<<CLK_CLKSEL1_UART_S_Pos)
#define | CLK_CLKSEL2_SPI1_S_PLL (0x0UL<<CLK_CLKSEL2_SPI1_S_Pos)
#define | CLK_CLKSEL2_SPI1_S_HCLK (0x1UL<<CLK_CLKSEL2_SPI1_S_Pos)
#define | CLK_CLKSEL2_SPI0_S_PLL (0x0UL<<CLK_CLKSEL2_SPI0_S_Pos)
#define | CLK_CLKSEL2_SPI0_S_HCLK (0x1UL<<CLK_CLKSEL2_SPI0_S_Pos)
#define | CLK_CLKSEL2_SC_S_HXT (0x0UL<<CLK_CLKSEL2_SC_S_Pos)
#define | CLK_CLKSEL2_SC_S_PLL (0x1UL<<CLK_CLKSEL2_SC_S_Pos)
#define | CLK_CLKSEL2_SC_S_HIRC (0x2UL<<CLK_CLKSEL2_SC_S_Pos)
#define | CLK_CLKSEL2_SC_S_HCLK (0x3UL<<CLK_CLKSEL2_SC_S_Pos)
#define | CLK_CLKSEL2_TMR2_S_HXT (0x0UL<<CLK_CLKSEL2_TMR2_S_Pos)
#define | CLK_CLKSEL2_TMR2_S_LXT (0x1UL<<CLK_CLKSEL2_TMR2_S_Pos)
#define | CLK_CLKSEL2_TMR2_S_LIRC (0x2UL<<CLK_CLKSEL2_TMR2_S_Pos)
#define | CLK_CLKSEL2_TMR2_S_EXT (0x3UL<<CLK_CLKSEL2_TMR2_S_Pos)
#define | CLK_CLKSEL2_TMR2_S_HIRC (0x4UL<<CLK_CLKSEL2_TMR2_S_Pos)
#define | CLK_CLKSEL2_TMR2_S_HCLK (0x5UL<<CLK_CLKSEL2_TMR2_S_Pos)
#define | CLK_CLKSEL2_TMR3_S_HXT (0x0UL<<CLK_CLKSEL2_TMR3_S_Pos)
#define | CLK_CLKSEL2_TMR3_S_LXT (0x1UL<<CLK_CLKSEL2_TMR3_S_Pos)
#define | CLK_CLKSEL2_TMR3_S_LIRC (0x2UL<<CLK_CLKSEL2_TMR3_S_Pos)
#define | CLK_CLKSEL2_TMR3_S_EXT (0x3UL<<CLK_CLKSEL2_TMR3_S_Pos)
#define | CLK_CLKSEL2_TMR3_S_HIRC (0x4UL<<CLK_CLKSEL2_TMR3_S_Pos)
#define | CLK_CLKSEL2_TMR3_S_HCLK (0x5UL<<CLK_CLKSEL2_TMR3_S_Pos)
#define | CLK_CLKSEL2_FRQDIV0_S_HXT (0x0UL<<CLK_CLKSEL2_FRQDIV0_S_Pos)
#define | CLK_CLKSEL2_FRQDIV0_S_LXT (0x1UL<<CLK_CLKSEL2_FRQDIV0_S_Pos)
#define | CLK_CLKSEL2_FRQDIV0_S_HCLK (0x2UL<<CLK_CLKSEL2_FRQDIV0_S_Pos)
#define | CLK_CLKSEL2_FRQDIV0_S_HIRC (0x3UL<<CLK_CLKSEL2_FRQDIV0_S_Pos)
#define | CLK_CLKSEL2_FRQDIV_S_HXT CLK_CLKSEL2_FRQDIV0_S_HXT
#define | CLK_CLKSEL2_FRQDIV_S_LXT CLK_CLKSEL2_FRQDIV0_S_LXT
#define | CLK_CLKSEL2_FRQDIV_S_HCLK CLK_CLKSEL2_FRQDIV0_S_HCLK
#define | CLK_CLKSEL2_FRQDIV_S_HIRC CLK_CLKSEL2_FRQDIV0_S_HIRC
#define | CLK_CLKSEL2_FRQDIV1_S_HXT (0x0UL<<CLK_CLKSEL2_FRQDIV1_S_Pos)
#define | CLK_CLKSEL2_FRQDIV1_S_LXT (0x1UL<<CLK_CLKSEL2_FRQDIV1_S_Pos)
#define | CLK_CLKSEL2_FRQDIV1_S_HCLK (0x2UL<<CLK_CLKSEL2_FRQDIV1_S_Pos)
#define | CLK_CLKSEL2_FRQDIV1_S_HIRC (0x3UL<<CLK_CLKSEL2_FRQDIV1_S_Pos)
#define | CLK_HCLK_CLK_DIVIDER(x) (((x-1)<< CLK_CLKDIV0_HCLK_N_Pos) & CLK_CLKDIV0_HCLK_N_Msk)
#define | CLK_UART_CLK_DIVIDER(x) (((x-1)<< CLK_CLKDIV0_UART_N_Pos) & CLK_CLKDIV0_UART_N_Msk)
#define | CLK_ADC_CLK_DIVIDER(x) (((x-1)<< CLK_CLKDIV0_ADC_N_Pos) & CLK_CLKDIV0_ADC_N_Msk)
#define | CLK_SC0_CLK_DIVIDER(x) (((x-1)<< CLK_CLKDIV0_SC0_N_Pos) & CLK_CLKDIV0_SC0_N_Msk)
#define | CLK_SC1_CLK_DIVIDER(x) (((x-1)<< CLK_CLKDIV1_SC1_N_Pos ) & CLK_CLKDIV1_SC1_N_Msk)
#define | CLK_TMR3_CLK_DIVIDER(x) (((x-1)<< CLK_CLKDIV1_TMR3_N_Pos) & CLK_CLKDIV1_TMR3_N_Msk)
#define | CLK_TMR2_CLK_DIVIDER(x) (((x-1)<< CLK_CLKDIV1_TMR2_N_Pos) & CLK_CLKDIV1_TMR2_N_Msk)
#define | CLK_TMR1_CLK_DIVIDER(x) (((x-1)<< CLK_CLKDIV1_TMR1_N_Pos) & CLK_CLKDIV1_TMR1_N_Msk)
#define | CLK_TMR0_CLK_DIVIDER(x) (((x-1)<< CLK_CLKDIV1_TMR0_N_Pos) & CLK_CLKDIV1_TMR0_N_Msk)
#define | CLK_CLKSEL0_STCLKSEL_HCLK (1)
#define | CLK_CLKSEL0_STCLKSEL_HCLK_DIV8 (2)
#define | CLK_FRQDIV_EN ((uint32_t)0x00000010)
#define | CLK_WK_INTSTS_IS ((uint32_t)0x00000001)
#define | MODULE_APBCLK(x) ((x >>31) & 0x1)
#define | MODULE_CLKSEL(x) ((x >>29) & 0x3)
#define | MODULE_CLKSEL_Msk(x) ((x >>25) & 0xf)
#define | MODULE_CLKSEL_Pos(x) ((x >>20) & 0x1f)
#define | MODULE_CLKDIV(x) ((x >>18) & 0x3)
#define | MODULE_CLKDIV_Msk(x) ((x >>10) & 0xff)
#define | MODULE_CLKDIV_Pos(x) ((x >>5 ) & 0x1f)
#define | MODULE_IP_EN_Pos(x) ((x >>0 ) & 0x1f)
#define | MODULE_NoMsk 0x0
#define | NA MODULE_NoMsk
#define | MODULE_APBCLK_ENC(x) (((x) & 0x01) << 31)
#define | MODULE_CLKSEL_ENC(x) (((x) & 0x03) << 29)
#define | MODULE_CLKSEL_Msk_ENC(x) (((x) & 0x0f) << 25)
#define | MODULE_CLKSEL_Pos_ENC(x) (((x) & 0x1f) << 20)
#define | MODULE_CLKDIV_ENC(x) (((x) & 0x03) << 18)
#define | MODULE_CLKDIV_Msk_ENC(x) (((x) & 0xff) << 10)
#define | MODULE_CLKDIV_Pos_ENC(x) (((x) & 0x1f) << 5)
#define | MODULE_IP_EN_Pos_ENC(x) (((x) & 0x1f) << 0)
#define | TICK_MODULE ((0UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(1<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_TICK_EN_Pos )
#define | SRAM_MODULE ((0UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(1<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_SRAM_EN_Pos )
#define | EBI_MODULE ((0UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(1<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_EBI_EN_Pos )
#define | ISP_MODULE ((0UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(1<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_ISP_EN_Pos )
#define | DMA_MODULE ((0UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_DMA_EN_Pos )
#define | GPIO_MODULE ((0UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_GPIO_EN_Pos )
#define | SC1_MODULE ((1UL<<31)|(2<<29)|(3<<25) |(18<<20)|(1<<18)|(0xF<<10) |( 0<<5)|CLK_APBCLK_SC1_EN_Pos )
#define | SC0_MODULE ((1UL<<31)|(2<<29)|(3<<25) |(18<<20)|(0<<18)|(0xF<<10) |(28<<5)|CLK_APBCLK_SC0_EN_Pos )
#define | ADC_MODULE ((1UL<<31)|(1<<29)|(7<<25) |(19<<20)|(0<<18)|(0xFF<<10) |(16<<5)|CLK_APBCLK_ADC_EN_Pos )
#define | LCD_MODULE ((1UL<<31)|(1<<29)|(1<<25) |(18<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_LCD_EN_Pos )
#define | PWM0_CH23_MODULE ((1UL<<31)|(1<<29)|(3<<25) |( 6<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_PWM0_CH23_EN_Pos)
#define | PWM0_CH01_MODULE ((1UL<<31)|(1<<29)|(3<<25) |( 4<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_PWM0_CH01_EN_Pos)
#define | UART1_MODULE ((1UL<<31)|(1<<29)|(3<<25) |( 0<<20)|(0<<18)|(0xF<<10) |( 8<<5)|CLK_APBCLK_UART1_EN_Pos )
#define | UART0_MODULE ((1UL<<31)|(1<<29)|(3<<25) |( 0<<20)|(0<<18)|(0xF<<10) |( 8<<5)|CLK_APBCLK_UART0_EN_Pos )
#define | SPI1_MODULE ((1UL<<31)|(2<<29)|(1<<25) |(21<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_SPI1_EN_Pos )
#define | SPI0_MODULE ((1UL<<31)|(2<<29)|(1<<25) |(20<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_SPI0_EN_Pos )
#define | ACMP_MODULE ((1UL<<31)|(0<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_ACMP_EN_Pos )
#define | I2C1_MODULE ((1UL<<31)|(0<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_I2C1_EN_Pos )
#define | I2C0_MODULE ((1UL<<31)|(0<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_I2C0_EN_Pos )
#define | FDIV1_MODULE ((1UL<<31)|(2<<29)|(3<<25) |( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_FDIV1_EN_Pos )
#define | FDIV0_MODULE ((1UL<<31)|(2<<29)|(3<<25) |( 2<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_FDIV0_EN_Pos )
#define | TMR3_MODULE ((1UL<<31)|(2<<29)|(7<<25) |(12<<20)|(1<<18)|(0xF<<10) |(20<<5)|CLK_APBCLK_TMR3_EN_Pos )
#define | TMR2_MODULE ((1UL<<31)|(2<<29)|(7<<25) |( 8<<20)|(1<<18)|(0xF<<10) |(16<<5)|CLK_APBCLK_TMR2_EN_Pos )
#define | TMR1_MODULE ((1UL<<31)|(1<<29)|(7<<25) |(12<<20)|(1<<18)|(0xF<<10) |(12<<5)|CLK_APBCLK_TMR1_EN_Pos )
#define | TMR0_MODULE ((1UL<<31)|(1<<29)|(7<<25) |( 8<<20)|(1<<18)|(0xF<<10) |( 8<<5)|CLK_APBCLK_TMR0_EN_Pos )
#define | RTC_MODULE ((1UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_RTC_EN_Pos )
#define | WDT_MODULE ((1UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_WDT_EN_Pos )
#define | FDIV_MODULE FDIV0_MODULE

## Detailed Description

## Macro Definition Documentation

## ◆ ACMP_MODULE

#define ACMP_MODULE ((1UL<<31)|(0<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_ACMP_EN_Pos )

ACMP Module

Definition at line 274 of file clk.h.

## ◆ ADC_MODULE

#define ADC_MODULE ((1UL<<31)|(1<<29)|(7<<25) |(19<<20)|(0<<18)|(0xFF<<10) |(16<<5)|CLK_APBCLK_ADC_EN_Pos )

ADC Module

Definition at line 266 of file clk.h.

## ◆ CLK_ADC_CLK_DIVIDER

#define CLK_ADC_CLK_DIVIDER | ( |  | x | ) | (((x-1)<< CLK_CLKDIV0_ADC_N_Pos) & CLK_CLKDIV0_ADC_N_Msk)

CLKDIV0 Setting for ADC clock divider. It could be 1~256

Definition at line 211 of file clk.h.

## ◆ CLK_AHBCLK_DMA_EN

#define CLK_AHBCLK_DMA_EN ((uint32_t)0x00000002)

DMA clock enable

Definition at line 56 of file clk.h.

## ◆ CLK_AHBCLK_EBI_EN

#define CLK_AHBCLK_EBI_EN ((uint32_t)0x00000008)

EBI clock enable

Definition at line 58 of file clk.h.

## ◆ CLK_AHBCLK_GPIO_EN

#define CLK_AHBCLK_GPIO_EN ((uint32_t)0x00000001)

GPIO clock enable

Definition at line 55 of file clk.h.

## ◆ CLK_AHBCLK_ISP_EN

#define CLK_AHBCLK_ISP_EN ((uint32_t)0x00000004)

Flash ISP controller clock enable

Definition at line 57 of file clk.h.

## ◆ CLK_AHBCLK_SRAM_EN

#define CLK_AHBCLK_SRAM_EN ((uint32_t)0x00000010)

SRAM Controller Clock Enable

Definition at line 59 of file clk.h.

## ◆ CLK_AHBCLK_TICK_EN

#define CLK_AHBCLK_TICK_EN ((uint32_t)0x00000020)

System Tick Clock Enable

Definition at line 60 of file clk.h.

## ◆ CLK_APBCLK_ADC_EN

#define CLK_APBCLK_ADC_EN ((uint32_t)0x10000000)

ADC clock enable

Definition at line 83 of file clk.h.

## ◆ CLK_APBCLK_DAC_EN

#define CLK_APBCLK_DAC_EN ((uint32_t)0x02000000)

DAC Clock Enable Control

Definition at line 80 of file clk.h.

## ◆ CLK_APBCLK_FDIV_EN

#define CLK_APBCLK_FDIV_EN ((uint32_t)0x00000040)

Frequency Divider Output clock enable

Definition at line 69 of file clk.h.

## ◆ CLK_APBCLK_I2C0_EN

#define CLK_APBCLK_I2C0_EN ((uint32_t)0x00000100)

I2C 0 clock enable

Definition at line 71 of file clk.h.

## ◆ CLK_APBCLK_I2C1_EN

#define CLK_APBCLK_I2C1_EN ((uint32_t)0x00000200)

I2C 1 clock enable

Definition at line 72 of file clk.h.

## ◆ CLK_APBCLK_I2S_EN

#define CLK_APBCLK_I2S_EN ((uint32_t)0x20000000)

I2S clock enable

Definition at line 84 of file clk.h.

## ◆ CLK_APBCLK_LCD_EN

#define CLK_APBCLK_LCD_EN ((uint32_t)0x04000000)

LCD controller Clock Enable Control

Definition at line 81 of file clk.h.

## ◆ CLK_APBCLK_PWM0_CH01_EN

#define CLK_APBCLK_PWM0_CH01_EN ((uint32_t)0x00100000)

PWM0 Channel 0 and Channel 1 Clock Enable Control

Definition at line 78 of file clk.h.

## ◆ CLK_APBCLK_PWM0_CH23_EN

#define CLK_APBCLK_PWM0_CH23_EN ((uint32_t)0x00200000)

PWM0 Channel 2 and Channel 3 Clock Enable Control

Definition at line 79 of file clk.h.

## ◆ CLK_APBCLK_RTC_EN

#define CLK_APBCLK_RTC_EN ((uint32_t)0x00000002)

RTC clock enable

Definition at line 64 of file clk.h.

## ◆ CLK_APBCLK_SC0_EN

#define CLK_APBCLK_SC0_EN ((uint32_t)0x40000000)

SmartCard 0 Clock Enable Control

Definition at line 85 of file clk.h.

## ◆ CLK_APBCLK_SC1_EN

#define CLK_APBCLK_SC1_EN ((uint32_t)0x80000000)

SmartCard 1 Clock Enable Control

Definition at line 86 of file clk.h.

## ◆ CLK_APBCLK_SC2_EN

#define CLK_APBCLK_SC2_EN ((uint32_t)0x00000080)

SmartCard 2 Clock Enable Control

Definition at line 70 of file clk.h.

## ◆ CLK_APBCLK_SPI0_EN

#define CLK_APBCLK_SPI0_EN ((uint32_t)0x00001000)

SPI 0 clock enable

Definition at line 73 of file clk.h.

## ◆ CLK_APBCLK_SPI1_EN

#define CLK_APBCLK_SPI1_EN ((uint32_t)0x00002000)

SPI 1 clock enable

Definition at line 74 of file clk.h.

## ◆ CLK_APBCLK_SPI2_EN

#define CLK_APBCLK_SPI2_EN ((uint32_t)0x00004000)

SPI 2 clock enable

Definition at line 75 of file clk.h.

## ◆ CLK_APBCLK_TMR0_EN

#define CLK_APBCLK_TMR0_EN ((uint32_t)0x00000004)

Timer 0 clock enable

Definition at line 65 of file clk.h.

## ◆ CLK_APBCLK_TMR1_EN

#define CLK_APBCLK_TMR1_EN ((uint32_t)0x00000008)

Timer 1 clock enable

Definition at line 66 of file clk.h.

## ◆ CLK_APBCLK_TMR2_EN

#define CLK_APBCLK_TMR2_EN ((uint32_t)0x00000010)

Timer 2 clock enable

Definition at line 67 of file clk.h.

## ◆ CLK_APBCLK_TMR3_EN

#define CLK_APBCLK_TMR3_EN ((uint32_t)0x00000020)

Timer 3 clock enable

Definition at line 68 of file clk.h.

## ◆ CLK_APBCLK_UART0_EN

#define CLK_APBCLK_UART0_EN ((uint32_t)0x00010000)

UART 0 clock enable

Definition at line 76 of file clk.h.

## ◆ CLK_APBCLK_UART1_EN

#define CLK_APBCLK_UART1_EN ((uint32_t)0x00020000)

UART 1 clock enable

Definition at line 77 of file clk.h.

## ◆ CLK_APBCLK_USBD_EN

#define CLK_APBCLK_USBD_EN ((uint32_t)0x08000000)

USB device clock enable

Definition at line 82 of file clk.h.

## ◆ CLK_APBCLK_WDT_EN

#define CLK_APBCLK_WDT_EN ((uint32_t)0x00000001)

Watchdog clock enable

Definition at line 63 of file clk.h.

## ◆ CLK_CLKSEL0_HCLK_S_HIRC

#define CLK_CLKSEL0_HCLK_S_HIRC (7UL<<CLK_CLKSEL0_HCLK_S_Pos)

Select HCLK clock source from high speed oscillator

Definition at line 126 of file clk.h.

## ◆ CLK_CLKSEL0_HCLK_S_HXT

#define CLK_CLKSEL0_HCLK_S_HXT (0UL<<CLK_CLKSEL0_HCLK_S_Pos)

Select HCLK clock source from high speed crystal

Definition at line 122 of file clk.h.

## ◆ CLK_CLKSEL0_HCLK_S_LIRC

#define CLK_CLKSEL0_HCLK_S_LIRC (3UL<<CLK_CLKSEL0_HCLK_S_Pos)

Select HCLK clock source from low speed oscillator

Definition at line 125 of file clk.h.

## ◆ CLK_CLKSEL0_HCLK_S_LXT

#define CLK_CLKSEL0_HCLK_S_LXT (1UL<<CLK_CLKSEL0_HCLK_S_Pos)

Select HCLK clock source from low speed crystal

Definition at line 123 of file clk.h.

## ◆ CLK_CLKSEL0_HCLK_S_PLL

#define CLK_CLKSEL0_HCLK_S_PLL (2UL<<CLK_CLKSEL0_HCLK_S_Pos)

Select HCLK clock source from PLL

Definition at line 124 of file clk.h.

## ◆ CLK_CLKSEL0_STCLKSEL_HCLK

#define CLK_CLKSEL0_STCLKSEL_HCLK (1)

Setting systick clock source as external HCLK

Definition at line 222 of file clk.h.

## ◆ CLK_CLKSEL0_STCLKSEL_HCLK_DIV8

#define CLK_CLKSEL0_STCLKSEL_HCLK_DIV8 (2)

Setting systick clock source as external HCLK/8

Definition at line 223 of file clk.h.

## ◆ CLK_CLKSEL1_ADC_S_HCLK

#define CLK_CLKSEL1_ADC_S_HCLK (0x4UL<<CLK_CLKSEL1_ADC_S_Pos)

Select ADC clock source from HCLK

Definition at line 133 of file clk.h.

## ◆ CLK_CLKSEL1_ADC_S_HIRC

#define CLK_CLKSEL1_ADC_S_HIRC (0x3UL<<CLK_CLKSEL1_ADC_S_Pos)

Select ADC clock source from high speed oscillator

Definition at line 132 of file clk.h.

## ◆ CLK_CLKSEL1_ADC_S_HXT

#define CLK_CLKSEL1_ADC_S_HXT (0x0UL<<CLK_CLKSEL1_ADC_S_Pos)

Select ADC clock source from high speed crystal

Definition at line 129 of file clk.h.

## ◆ CLK_CLKSEL1_ADC_S_LXT

#define CLK_CLKSEL1_ADC_S_LXT (0x1UL<<CLK_CLKSEL1_ADC_S_Pos)

Select ADC clock source from low speed crystal

Definition at line 130 of file clk.h.

## ◆ CLK_CLKSEL1_ADC_S_PLL

#define CLK_CLKSEL1_ADC_S_PLL (0x2UL<<CLK_CLKSEL1_ADC_S_Pos)

Select ADC clock source from PLL

Definition at line 131 of file clk.h.

## ◆ CLK_CLKSEL1_LCD_S_LXT

#define CLK_CLKSEL1_LCD_S_LXT (0x0UL<<CLK_CLKSEL1_LCD_S_Pos)

Select LCD clock source from low speed crystal

Definition at line 135 of file clk.h.

## ◆ CLK_CLKSEL1_PWM0_CH01_S_HCLK

#define CLK_CLKSEL1_PWM0_CH01_S_HCLK (0x2UL<<CLK_CLKSEL1_PWM0_CH01_S_Pos)

Select PWM0_CH01 clock source from HCLK

Definition at line 153 of file clk.h.

## ◆ CLK_CLKSEL1_PWM0_CH01_S_HIRC

#define CLK_CLKSEL1_PWM0_CH01_S_HIRC (0x3UL<<CLK_CLKSEL1_PWM0_CH01_S_Pos)

Select PWM0_CH01 clock source from high speed oscillator

Definition at line 154 of file clk.h.

## ◆ CLK_CLKSEL1_PWM0_CH01_S_HXT

#define CLK_CLKSEL1_PWM0_CH01_S_HXT (0x0UL<<CLK_CLKSEL1_PWM0_CH01_S_Pos)

Select PWM0_CH01 clock source from high speed crystal

Definition at line 151 of file clk.h.

## ◆ CLK_CLKSEL1_PWM0_CH01_S_LXT

#define CLK_CLKSEL1_PWM0_CH01_S_LXT (0x1UL<<CLK_CLKSEL1_PWM0_CH01_S_Pos)

Select PWM0_CH01 clock source from low speed crystal

Definition at line 152 of file clk.h.

## ◆ CLK_CLKSEL1_PWM0_CH23_S_HCLK

#define CLK_CLKSEL1_PWM0_CH23_S_HCLK (0x2UL<<CLK_CLKSEL1_PWM0_CH23_S_Pos)

Select PWM0_CH23 clock source from HCLK

Definition at line 158 of file clk.h.

## ◆ CLK_CLKSEL1_PWM0_CH23_S_HIRC

#define CLK_CLKSEL1_PWM0_CH23_S_HIRC (0x3UL<<CLK_CLKSEL1_PWM0_CH23_S_Pos)

Select PWM0_CH23 clock source from high speed oscillator

Definition at line 159 of file clk.h.

## ◆ CLK_CLKSEL1_PWM0_CH23_S_HXT

#define CLK_CLKSEL1_PWM0_CH23_S_HXT (0x0UL<<CLK_CLKSEL1_PWM0_CH23_S_Pos)

Select PWM0_CH23 clock source from high speed crystal

Definition at line 156 of file clk.h.

## ◆ CLK_CLKSEL1_PWM0_CH23_S_LXT

#define CLK_CLKSEL1_PWM0_CH23_S_LXT (0x1UL<<CLK_CLKSEL1_PWM0_CH23_S_Pos)

Select PWM0_CH23 clock source from low speed crystal

Definition at line 157 of file clk.h.

## ◆ CLK_CLKSEL1_TMR0_S_EXT

#define CLK_CLKSEL1_TMR0_S_EXT (0x3UL<<CLK_CLKSEL1_TMR0_S_Pos)

Select TMR0 clock source from external trigger

Definition at line 147 of file clk.h.

## ◆ CLK_CLKSEL1_TMR0_S_HCLK

#define CLK_CLKSEL1_TMR0_S_HCLK (0x5UL<<CLK_CLKSEL1_TMR0_S_Pos)

Select TMR0 clock source from HCLK

Definition at line 149 of file clk.h.

## ◆ CLK_CLKSEL1_TMR0_S_HIRC

#define CLK_CLKSEL1_TMR0_S_HIRC (0x4UL<<CLK_CLKSEL1_TMR0_S_Pos)

Select TMR0 clock source from high speed oscillator

Definition at line 148 of file clk.h.

## ◆ CLK_CLKSEL1_TMR0_S_HXT

#define CLK_CLKSEL1_TMR0_S_HXT (0x0UL<<CLK_CLKSEL1_TMR0_S_Pos)

Select TMR0 clock source from high speed crystal

Definition at line 144 of file clk.h.

## ◆ CLK_CLKSEL1_TMR0_S_LIRC

#define CLK_CLKSEL1_TMR0_S_LIRC (0x2UL<<CLK_CLKSEL1_TMR0_S_Pos)

Select TMR0 clock source from low speed oscillator

Definition at line 146 of file clk.h.

## ◆ CLK_CLKSEL1_TMR0_S_LXT

#define CLK_CLKSEL1_TMR0_S_LXT (0x1UL<<CLK_CLKSEL1_TMR0_S_Pos)

Select TMR0 clock source from low speed crystal

Definition at line 145 of file clk.h.

## ◆ CLK_CLKSEL1_TMR1_S_EXT

#define CLK_CLKSEL1_TMR1_S_EXT (0x3UL<<CLK_CLKSEL1_TMR1_S_Pos)

Select TMR1 clock source from external trigger

Definition at line 140 of file clk.h.

## ◆ CLK_CLKSEL1_TMR1_S_HCLK

#define CLK_CLKSEL1_TMR1_S_HCLK (0x5UL<<CLK_CLKSEL1_TMR1_S_Pos)

Select TMR1 clock source from HCLK

Definition at line 142 of file clk.h.

## ◆ CLK_CLKSEL1_TMR1_S_HIRC

#define CLK_CLKSEL1_TMR1_S_HIRC (0x4UL<<CLK_CLKSEL1_TMR1_S_Pos)

Select TMR1 clock source from high speed oscillator

Definition at line 141 of file clk.h.

## ◆ CLK_CLKSEL1_TMR1_S_HXT

#define CLK_CLKSEL1_TMR1_S_HXT (0x0UL<<CLK_CLKSEL1_TMR1_S_Pos)

Select TMR1 clock source from high speed crystal

Definition at line 137 of file clk.h.

## ◆ CLK_CLKSEL1_TMR1_S_LIRC

#define CLK_CLKSEL1_TMR1_S_LIRC (0x2UL<<CLK_CLKSEL1_TMR1_S_Pos)

Select TMR1 clock source from low speed oscillator

Definition at line 139 of file clk.h.

## ◆ CLK_CLKSEL1_TMR1_S_LXT

#define CLK_CLKSEL1_TMR1_S_LXT (0x1UL<<CLK_CLKSEL1_TMR1_S_Pos)

Select TMR1 clock source from low speed crystal

Definition at line 138 of file clk.h.

## ◆ CLK_CLKSEL1_UART_S_HIRC

#define CLK_CLKSEL1_UART_S_HIRC (0x3UL<<CLK_CLKSEL1_UART_S_Pos)

Select UART clock source from high speed oscillator

Definition at line 164 of file clk.h.

## ◆ CLK_CLKSEL1_UART_S_HXT

#define CLK_CLKSEL1_UART_S_HXT (0x0UL<<CLK_CLKSEL1_UART_S_Pos)

Select UART clock source from high speed crystal

Definition at line 161 of file clk.h.

## ◆ CLK_CLKSEL1_UART_S_LXT

#define CLK_CLKSEL1_UART_S_LXT (0x1UL<<CLK_CLKSEL1_UART_S_Pos)

Select UART clock source from low speed crystal

Definition at line 162 of file clk.h.

## ◆ CLK_CLKSEL1_UART_S_PLL

#define CLK_CLKSEL1_UART_S_PLL (0x2UL<<CLK_CLKSEL1_UART_S_Pos)

Select UART clock source from PLL

Definition at line 163 of file clk.h.

## ◆ CLK_CLKSEL2_FRQDIV0_S_HCLK

#define CLK_CLKSEL2_FRQDIV0_S_HCLK (0x2UL<<CLK_CLKSEL2_FRQDIV0_S_Pos)

Select FRQDIV0 clock source from HCLK

Definition at line 195 of file clk.h.

## ◆ CLK_CLKSEL2_FRQDIV0_S_HIRC

#define CLK_CLKSEL2_FRQDIV0_S_HIRC (0x3UL<<CLK_CLKSEL2_FRQDIV0_S_Pos)

Select FRQDIV0 clock source from high speed oscillator

Definition at line 196 of file clk.h.

## ◆ CLK_CLKSEL2_FRQDIV0_S_HXT

#define CLK_CLKSEL2_FRQDIV0_S_HXT (0x0UL<<CLK_CLKSEL2_FRQDIV0_S_Pos)

Select FRQDIV0 clock source from high speed crystal

Definition at line 193 of file clk.h.

## ◆ CLK_CLKSEL2_FRQDIV0_S_LXT

#define CLK_CLKSEL2_FRQDIV0_S_LXT (0x1UL<<CLK_CLKSEL2_FRQDIV0_S_Pos)

Select FRQDIV0 clock source from low speed crystal

Definition at line 194 of file clk.h.

## ◆ CLK_CLKSEL2_FRQDIV1_S_HCLK

#define CLK_CLKSEL2_FRQDIV1_S_HCLK (0x2UL<<CLK_CLKSEL2_FRQDIV1_S_Pos)

Select FRQDIV1 clock source from HCLK

Definition at line 205 of file clk.h.

## ◆ CLK_CLKSEL2_FRQDIV1_S_HIRC

#define CLK_CLKSEL2_FRQDIV1_S_HIRC (0x3UL<<CLK_CLKSEL2_FRQDIV1_S_Pos)

Select FRQDIV1 clock source from high speed oscillator

Definition at line 206 of file clk.h.

## ◆ CLK_CLKSEL2_FRQDIV1_S_HXT

#define CLK_CLKSEL2_FRQDIV1_S_HXT (0x0UL<<CLK_CLKSEL2_FRQDIV1_S_Pos)

Select FRQDIV1 clock source from high speed crystal

Definition at line 203 of file clk.h.

## ◆ CLK_CLKSEL2_FRQDIV1_S_LXT

#define CLK_CLKSEL2_FRQDIV1_S_LXT (0x1UL<<CLK_CLKSEL2_FRQDIV1_S_Pos)

Select FRQDIV1 clock source from low speed crystal

Definition at line 204 of file clk.h.

## ◆ CLK_CLKSEL2_FRQDIV_S_HCLK

#define CLK_CLKSEL2_FRQDIV_S_HCLK CLK_CLKSEL2_FRQDIV0_S_HCLK

Select FRQDIV0 clock source from HCLK

Definition at line 200 of file clk.h.

## ◆ CLK_CLKSEL2_FRQDIV_S_HIRC

#define CLK_CLKSEL2_FRQDIV_S_HIRC CLK_CLKSEL2_FRQDIV0_S_HIRC

Select FRQDIV0 clock source from high speed oscillator

Definition at line 201 of file clk.h.

## ◆ CLK_CLKSEL2_FRQDIV_S_HXT

#define CLK_CLKSEL2_FRQDIV_S_HXT CLK_CLKSEL2_FRQDIV0_S_HXT

Select FRQDIV0 clock source from high speed crystal

Definition at line 198 of file clk.h.

## ◆ CLK_CLKSEL2_FRQDIV_S_LXT

#define CLK_CLKSEL2_FRQDIV_S_LXT CLK_CLKSEL2_FRQDIV0_S_LXT

Select FRQDIV0 clock source from low speed crystal

Definition at line 199 of file clk.h.

## ◆ CLK_CLKSEL2_SC_S_HCLK

#define CLK_CLKSEL2_SC_S_HCLK (0x3UL<<CLK_CLKSEL2_SC_S_Pos)

Select SC clock source from HCLK

Definition at line 176 of file clk.h.

## ◆ CLK_CLKSEL2_SC_S_HIRC

#define CLK_CLKSEL2_SC_S_HIRC (0x2UL<<CLK_CLKSEL2_SC_S_Pos)

Select SC clock source from high speed oscillator

Definition at line 175 of file clk.h.

## ◆ CLK_CLKSEL2_SC_S_HXT

#define CLK_CLKSEL2_SC_S_HXT (0x0UL<<CLK_CLKSEL2_SC_S_Pos)

Select SC clock source from high speed crystal

Definition at line 173 of file clk.h.

## ◆ CLK_CLKSEL2_SC_S_PLL

#define CLK_CLKSEL2_SC_S_PLL (0x1UL<<CLK_CLKSEL2_SC_S_Pos)

Select SC clock source from PLL

Definition at line 174 of file clk.h.

## ◆ CLK_CLKSEL2_SPI0_S_HCLK

#define CLK_CLKSEL2_SPI0_S_HCLK (0x1UL<<CLK_CLKSEL2_SPI0_S_Pos)

Select SPI 0 clock source from HCLK

Definition at line 171 of file clk.h.

## ◆ CLK_CLKSEL2_SPI0_S_PLL

#define CLK_CLKSEL2_SPI0_S_PLL (0x0UL<<CLK_CLKSEL2_SPI0_S_Pos)

Select SPI 0 clock source from PLL

Definition at line 170 of file clk.h.

## ◆ CLK_CLKSEL2_SPI1_S_HCLK

#define CLK_CLKSEL2_SPI1_S_HCLK (0x1UL<<CLK_CLKSEL2_SPI1_S_Pos)

Select SPI 1 clock source from HCLK

Definition at line 168 of file clk.h.

## ◆ CLK_CLKSEL2_SPI1_S_PLL

#define CLK_CLKSEL2_SPI1_S_PLL (0x0UL<<CLK_CLKSEL2_SPI1_S_Pos)

Select SPI 1 clock source from PLL

Definition at line 167 of file clk.h.

## ◆ CLK_CLKSEL2_TMR2_S_EXT

#define CLK_CLKSEL2_TMR2_S_EXT (0x3UL<<CLK_CLKSEL2_TMR2_S_Pos)

Select TMR2 clock source from external trigger

Definition at line 181 of file clk.h.

## ◆ CLK_CLKSEL2_TMR2_S_HCLK

#define CLK_CLKSEL2_TMR2_S_HCLK (0x5UL<<CLK_CLKSEL2_TMR2_S_Pos)

Select TMR2 clock source from HCLK

Definition at line 183 of file clk.h.

## ◆ CLK_CLKSEL2_TMR2_S_HIRC

#define CLK_CLKSEL2_TMR2_S_HIRC (0x4UL<<CLK_CLKSEL2_TMR2_S_Pos)

Select TMR2 clock source from high speed oscillator

Definition at line 182 of file clk.h.

## ◆ CLK_CLKSEL2_TMR2_S_HXT

#define CLK_CLKSEL2_TMR2_S_HXT (0x0UL<<CLK_CLKSEL2_TMR2_S_Pos)

Select TMR2 clock source from high speed crystal

Definition at line 178 of file clk.h.

## ◆ CLK_CLKSEL2_TMR2_S_LIRC

#define CLK_CLKSEL2_TMR2_S_LIRC (0x2UL<<CLK_CLKSEL2_TMR2_S_Pos)

Select TMR2 clock source from low speed oscillator

Definition at line 180 of file clk.h.

## ◆ CLK_CLKSEL2_TMR2_S_LXT

#define CLK_CLKSEL2_TMR2_S_LXT (0x1UL<<CLK_CLKSEL2_TMR2_S_Pos)

Select TMR2 clock source from low speed crystal

Definition at line 179 of file clk.h.

## ◆ CLK_CLKSEL2_TMR3_S_EXT

#define CLK_CLKSEL2_TMR3_S_EXT (0x3UL<<CLK_CLKSEL2_TMR3_S_Pos)

Select TMR3 clock source from external trigger

Definition at line 188 of file clk.h.

## ◆ CLK_CLKSEL2_TMR3_S_HCLK

#define CLK_CLKSEL2_TMR3_S_HCLK (0x5UL<<CLK_CLKSEL2_TMR3_S_Pos)

Select TMR3 clock source from HCLK

Definition at line 190 of file clk.h.

## ◆ CLK_CLKSEL2_TMR3_S_HIRC

#define CLK_CLKSEL2_TMR3_S_HIRC (0x4UL<<CLK_CLKSEL2_TMR3_S_Pos)

Select TMR3 clock source from high speed oscillator

Definition at line 189 of file clk.h.

## ◆ CLK_CLKSEL2_TMR3_S_HXT

#define CLK_CLKSEL2_TMR3_S_HXT (0x0UL<<CLK_CLKSEL2_TMR3_S_Pos)

Select TMR3 clock source from high speed crystal

Definition at line 185 of file clk.h.

## ◆ CLK_CLKSEL2_TMR3_S_LIRC

#define CLK_CLKSEL2_TMR3_S_LIRC (0x2UL<<CLK_CLKSEL2_TMR3_S_Pos)

Select TMR3 clock source from low speed oscillator

Definition at line 187 of file clk.h.

## ◆ CLK_CLKSEL2_TMR3_S_LXT

#define CLK_CLKSEL2_TMR3_S_LXT (0x1UL<<CLK_CLKSEL2_TMR3_S_Pos)

Select TMR3 clock source from low speed crystal

Definition at line 186 of file clk.h.

## ◆ CLK_CLKSTATUS_CLK_SW_FAIL

#define CLK_CLKSTATUS_CLK_SW_FAIL ((uint32_t)0x00000080)

Clock switch fail flag

Definition at line 94 of file clk.h.

## ◆ CLK_CLKSTATUS_HIRC_STB

#define CLK_CLKSTATUS_HIRC_STB ((uint32_t)0x00000010)

Internal high speed oscillator clock source stable flag

Definition at line 93 of file clk.h.

## ◆ CLK_CLKSTATUS_HXT_STB

#define CLK_CLKSTATUS_HXT_STB ((uint32_t)0x00000001)

External high speed crystal clock source stable flag

Definition at line 89 of file clk.h.

## ◆ CLK_CLKSTATUS_LIRC_STB

#define CLK_CLKSTATUS_LIRC_STB ((uint32_t)0x00000008)

Internal low speed oscillator clock source stable flag

Definition at line 92 of file clk.h.

## ◆ CLK_CLKSTATUS_LXT_STB

#define CLK_CLKSTATUS_LXT_STB ((uint32_t)0x00000002)

External low speed crystal clock source stable flag

Definition at line 90 of file clk.h.

## ◆ CLK_CLKSTATUS_PLL_STB

#define CLK_CLKSTATUS_PLL_STB ((uint32_t)0x00000004)

Internal PLL clock source stable flag

Definition at line 91 of file clk.h.

## ◆ CLK_FRQDIV_EN

#define CLK_FRQDIV_EN ((uint32_t)0x00000010)

Frequency divider enable bit

Definition at line 226 of file clk.h.

## ◆ CLK_HCLK_CLK_DIVIDER

#define CLK_HCLK_CLK_DIVIDER | ( |  | x | ) | (((x-1)<< CLK_CLKDIV0_HCLK_N_Pos) & CLK_CLKDIV0_HCLK_N_Msk)

CLKDIV0 Setting for HCLK clock divider. It could be 1~16

Definition at line 209 of file clk.h.

## ◆ CLK_PLL_MLP

#define CLK_PLL_MLP | ( |  | x | ) | ((x)<<0)

PLL Multiple

Definition at line 102 of file clk.h.

## ◆ CLK_PLL_SRC_N

#define CLK_PLL_SRC_N | ( |  | x | ) | (((x)-1)<<8)

PLL Input Source Divider

Definition at line 101 of file clk.h.

## ◆ CLK_PLLCTL_16MHz_HIRC

#define CLK_PLLCTL_16MHz_HIRC (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLL_SRC_N(12) | CLK_PLL_MLP(16))

Predefined PLLCTL setting for 16MHz PLL output with 12MHz IRC

Definition at line 116 of file clk.h.

## ◆ CLK_PLLCTL_22MHz_HIRC

#define CLK_PLLCTL_22MHz_HIRC (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLL_SRC_N(12) | CLK_PLL_MLP(22))

Predefined PLLCTL setting for 22MHz PLL output with 12MHz IRC

Definition at line 115 of file clk.h.

## ◆ CLK_PLLCTL_24MHz_HIRC

#define CLK_PLLCTL_24MHz_HIRC (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLL_SRC_N(12) | CLK_PLL_MLP(24))

Predefined PLLCTL setting for 24MHz PLL output with 12MHz IRC

Definition at line 114 of file clk.h.

## ◆ CLK_PLLCTL_28MHz_HIRC

#define CLK_PLLCTL_28MHz_HIRC (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLL_SRC_N(12) | CLK_PLL_MLP(28))

Predefined PLLCTL setting for 28MHz PLL output with 12MHz IRC

Definition at line 113 of file clk.h.

## ◆ CLK_PLLCTL_32MHz_HIRC

#define CLK_PLLCTL_32MHz_HIRC (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLL_SRC_N(12) | CLK_PLL_MLP(32))

Predefined PLLCTL setting for 32MHz PLL output with 12MHz IRC

Definition at line 112 of file clk.h.

## ◆ CLK_PLLCTL_PD

#define CLK_PLLCTL_PD ((uint32_t)0x00010000)

PLL Power down mode

Definition at line 97 of file clk.h.

## ◆ CLK_PLLCTL_PLL_SRC_HIRC

#define CLK_PLLCTL_PLL_SRC_HIRC ((uint32_t)(0x00020000))

For PLL clock source is HIRC

Definition at line 99 of file clk.h.

## ◆ CLK_PLLCTL_PLL_SRC_HXT

#define CLK_PLLCTL_PLL_SRC_HXT ((uint32_t)(0x00000000))

For PLL clock source is HXT

Definition at line 98 of file clk.h.

## ◆ CLK_PWRCTL_DELY_EN

#define CLK_PWRCTL_DELY_EN ((uint32_t)0x00000010)

Enable the wake-up delay counter

Definition at line 42 of file clk.h.

## ◆ CLK_PWRCTL_HIRC_EN

#define CLK_PWRCTL_HIRC_EN ((uint32_t)0x00000004)

Enable internal high speed oscillator

Definition at line 40 of file clk.h.

## ◆ CLK_PWRCTL_HXT_EN

#define CLK_PWRCTL_HXT_EN ((uint32_t)0x00000001)

Enable high speed crystal

Definition at line 38 of file clk.h.

## ◆ CLK_PWRCTL_HXT_GAIN_12M_16M

#define CLK_PWRCTL_HXT_GAIN_12M_16M ((uint32_t)0x00000800)

High frequency crystal Gain control is from 12 MHz to 16 MHz

Definition at line 49 of file clk.h.

## ◆ CLK_PWRCTL_HXT_GAIN_16M

#define CLK_PWRCTL_HXT_GAIN_16M ((uint32_t)0x00000C00)

High frequency crystal Gain control is higher than 16 MHz

Definition at line 50 of file clk.h.

## ◆ CLK_PWRCTL_HXT_GAIN_8M

#define CLK_PWRCTL_HXT_GAIN_8M ((uint32_t)0x00000000)

High frequency crystal Gain control is lower than from 8 MHz

Definition at line 47 of file clk.h.

## ◆ CLK_PWRCTL_HXT_GAIN_8M_12M

#define CLK_PWRCTL_HXT_GAIN_8M_12M ((uint32_t)0x00000400)

High frequency crystal Gain control is from 8 MHz to 12 MHz

Definition at line 48 of file clk.h.

## ◆ CLK_PWRCTL_HXT_SELXT

#define CLK_PWRCTL_HXT_SELXT ((uint32_t)0x00000100)

High frequency crystal loop back path Enabled

Definition at line 45 of file clk.h.

## ◆ CLK_PWRCTL_LIRC_EN

#define CLK_PWRCTL_LIRC_EN ((uint32_t)0x00000008)

Enable internal low speed oscillator

Definition at line 41 of file clk.h.

## ◆ CLK_PWRCTL_LXT_EN

#define CLK_PWRCTL_LXT_EN ((uint32_t)0x00000002)

Enable low speed crystal

Definition at line 39 of file clk.h.

## ◆ CLK_PWRCTL_PWRDOWN_EN

#define CLK_PWRCTL_PWRDOWN_EN ((uint32_t)0x00000040)

Power down enable bit

Definition at line 44 of file clk.h.

## ◆ CLK_PWRCTL_WAKEINT_EN

#define CLK_PWRCTL_WAKEINT_EN ((uint32_t)0x00000020)

Enable the wake-up interrupt

Definition at line 43 of file clk.h.

## ◆ CLK_SC0_CLK_DIVIDER

#define CLK_SC0_CLK_DIVIDER | ( |  | x | ) | (((x-1)<< CLK_CLKDIV0_SC0_N_Pos) & CLK_CLKDIV0_SC0_N_Msk)

CLKDIV0 Setting for SmartCard0 clock divider. It could be 1~16

Definition at line 212 of file clk.h.

## ◆ CLK_SC1_CLK_DIVIDER

#define CLK_SC1_CLK_DIVIDER | ( |  | x | ) | (((x-1)<< CLK_CLKDIV1_SC1_N_Pos ) & CLK_CLKDIV1_SC1_N_Msk)

CLKDIV1 Setting for SmartCard1 clock divider. It could be 1~16

Definition at line 215 of file clk.h.

## ◆ CLK_TMR0_CLK_DIVIDER

#define CLK_TMR0_CLK_DIVIDER | ( |  | x | ) | (((x-1)<< CLK_CLKDIV1_TMR0_N_Pos) & CLK_CLKDIV1_TMR0_N_Msk)

CLKDIV1 Setting for Timer0 clock divider. It could be 1~16

Definition at line 219 of file clk.h.

## ◆ CLK_TMR1_CLK_DIVIDER

#define CLK_TMR1_CLK_DIVIDER | ( |  | x | ) | (((x-1)<< CLK_CLKDIV1_TMR1_N_Pos) & CLK_CLKDIV1_TMR1_N_Msk)

CLKDIV1 Setting for Timer1 clock divider. It could be 1~16

Definition at line 218 of file clk.h.

## ◆ CLK_TMR2_CLK_DIVIDER

#define CLK_TMR2_CLK_DIVIDER | ( |  | x | ) | (((x-1)<< CLK_CLKDIV1_TMR2_N_Pos) & CLK_CLKDIV1_TMR2_N_Msk)

CLKDIV1 Setting for Timer2 clock divider. It could be 1~16

Definition at line 217 of file clk.h.

## ◆ CLK_TMR3_CLK_DIVIDER

#define CLK_TMR3_CLK_DIVIDER | ( |  | x | ) | (((x-1)<< CLK_CLKDIV1_TMR3_N_Pos) & CLK_CLKDIV1_TMR3_N_Msk)

CLKDIV1 Setting for Timer3 clock divider. It could be 1~16

Definition at line 216 of file clk.h.

## ◆ CLK_UART_CLK_DIVIDER

#define CLK_UART_CLK_DIVIDER | ( |  | x | ) | (((x-1)<< CLK_CLKDIV0_UART_N_Pos) & CLK_CLKDIV0_UART_N_Msk)

CLKDIV0 Setting for UART clock divider. It could be 1~16

Definition at line 210 of file clk.h.

## ◆ CLK_WK_INTSTS_IS

#define CLK_WK_INTSTS_IS ((uint32_t)0x00000001)

Wake-up Interrupt Status in chip Power-down Mode

Definition at line 229 of file clk.h.

## ◆ DMA_MODULE

#define DMA_MODULE ((0UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_DMA_EN_Pos )

DMA Module

Definition at line 261 of file clk.h.

## ◆ EBI_MODULE

#define EBI_MODULE ((0UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(1<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_EBI_EN_Pos )

EBI Module

Definition at line 259 of file clk.h.

## ◆ FDIV0_MODULE

#define FDIV0_MODULE ((1UL<<31)|(2<<29)|(3<<25) |( 2<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_FDIV0_EN_Pos )

Frequency Divider0 Output Module

Definition at line 278 of file clk.h.

## ◆ FDIV1_MODULE

#define FDIV1_MODULE ((1UL<<31)|(2<<29)|(3<<25) |( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_FDIV1_EN_Pos )

Frequency Divider1 Output Module

Definition at line 277 of file clk.h.

## ◆ FDIV_MODULE

#define FDIV_MODULE FDIV0_MODULE

Frequency Divider Output Module

Definition at line 286 of file clk.h.

## ◆ FREQ_16MHZ

#define FREQ_16MHZ 16000000

Definition at line 35 of file clk.h.

## ◆ FREQ_32MHZ

#define FREQ_32MHZ 32000000

Definition at line 34 of file clk.h.

## ◆ GPIO_MODULE

#define GPIO_MODULE ((0UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_GPIO_EN_Pos )

GPIO Module

Definition at line 262 of file clk.h.

## ◆ I2C0_MODULE

#define I2C0_MODULE ((1UL<<31)|(0<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_I2C0_EN_Pos )

I2C0 Module

Definition at line 276 of file clk.h.

## ◆ I2C1_MODULE

#define I2C1_MODULE ((1UL<<31)|(0<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_I2C1_EN_Pos )

I2C1 Module

Definition at line 275 of file clk.h.

## ◆ ISP_MODULE

#define ISP_MODULE ((0UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(1<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_ISP_EN_Pos )

ISP Module

Definition at line 260 of file clk.h.

## ◆ LCD_MODULE

#define LCD_MODULE ((1UL<<31)|(1<<29)|(1<<25) |(18<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_LCD_EN_Pos )

LCD Module

Definition at line 267 of file clk.h.

## ◆ MODULE_APBCLK

#define MODULE_APBCLK | ( |  | x | ) | ((x >>31) & 0x1)

Calculate APBCLK offset on MODULE index

Definition at line 235 of file clk.h.

## ◆ MODULE_APBCLK_ENC

#define MODULE_APBCLK_ENC | ( |  | x | ) | (((x) & 0x01) << 31)

MODULE index, 0x0:AHBCLK, 0x1:APBCLK

Definition at line 246 of file clk.h.

## ◆ MODULE_CLKDIV

#define MODULE_CLKDIV | ( |  | x | ) | ((x >>18) & 0x3)

Calculate APBCLK CLKDIV on MODULE index

Definition at line 239 of file clk.h.

## ◆ MODULE_CLKDIV_ENC

#define MODULE_CLKDIV_ENC | ( |  | x | ) | (((x) & 0x03) << 18)

APBCLK CLKDIV on MODULE index, 0x0:CLKDIV

Definition at line 250 of file clk.h.

## ◆ MODULE_CLKDIV_Msk

#define MODULE_CLKDIV_Msk | ( |  | x | ) | ((x >>10) & 0xff)

Calculate CLKDIV mask offset on MODULE index

Definition at line 240 of file clk.h.

## ◆ MODULE_CLKDIV_Msk_ENC

#define MODULE_CLKDIV_Msk_ENC | ( |  | x | ) | (((x) & 0xff) << 10)

CLKDIV mask offset on MODULE index

Definition at line 251 of file clk.h.

## ◆ MODULE_CLKDIV_Pos

#define MODULE_CLKDIV_Pos | ( |  | x | ) | ((x >>5 ) & 0x1f)

Calculate CLKDIV position offset on MODULE index

Definition at line 241 of file clk.h.

## ◆ MODULE_CLKDIV_Pos_ENC

#define MODULE_CLKDIV_Pos_ENC | ( |  | x | ) | (((x) & 0x1f) << 5)

CLKDIV position offset on MODULE index

Definition at line 252 of file clk.h.

## ◆ MODULE_CLKSEL

#define MODULE_CLKSEL | ( |  | x | ) | ((x >>29) & 0x3)

Calculate CLKSEL offset on MODULE index

Definition at line 236 of file clk.h.

## ◆ MODULE_CLKSEL_ENC

#define MODULE_CLKSEL_ENC | ( |  | x | ) | (((x) & 0x03) << 29)

CLKSEL offset on MODULE index, 0x0:CLKSEL0, 0x1:CLKSEL1 0x3 CLKSEL2

Definition at line 247 of file clk.h.

## ◆ MODULE_CLKSEL_Msk

#define MODULE_CLKSEL_Msk | ( |  | x | ) | ((x >>25) & 0xf)

Calculate CLKSEL mask offset on MODULE index

Definition at line 237 of file clk.h.

## ◆ MODULE_CLKSEL_Msk_ENC

#define MODULE_CLKSEL_Msk_ENC | ( |  | x | ) | (((x) & 0x0f) << 25)

CLKSEL mask offset on MODULE index

Definition at line 248 of file clk.h.

## ◆ MODULE_CLKSEL_Pos

#define MODULE_CLKSEL_Pos | ( |  | x | ) | ((x >>20) & 0x1f)

Calculate CLKSEL position offset on MODULE index

Definition at line 238 of file clk.h.

## ◆ MODULE_CLKSEL_Pos_ENC

#define MODULE_CLKSEL_Pos_ENC | ( |  | x | ) | (((x) & 0x1f) << 20)

CLKSEL position offset on MODULE index

Definition at line 249 of file clk.h.

## ◆ MODULE_IP_EN_Pos

#define MODULE_IP_EN_Pos | ( |  | x | ) | ((x >>0 ) & 0x1f)

Calculate APBCLK offset on MODULE index

Definition at line 242 of file clk.h.

## ◆ MODULE_IP_EN_Pos_ENC

#define MODULE_IP_EN_Pos_ENC | ( |  | x | ) | (((x) & 0x1f) << 0)

APBCLK offset on MODULE index

Definition at line 253 of file clk.h.

## ◆ MODULE_NoMsk

#define MODULE_NoMsk 0x0

Not mask on MODULE index

Definition at line 243 of file clk.h.

## ◆ NA

#define NA MODULE_NoMsk

Not Available

Definition at line 244 of file clk.h.

## ◆ PWM0_CH01_MODULE

#define PWM0_CH01_MODULE ((1UL<<31)|(1<<29)|(3<<25) |( 4<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_PWM0_CH01_EN_Pos)

PWM0 Channel0 and Channel1 Module

Definition at line 269 of file clk.h.

## ◆ PWM0_CH23_MODULE

#define PWM0_CH23_MODULE ((1UL<<31)|(1<<29)|(3<<25) |( 6<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_PWM0_CH23_EN_Pos)

PWM0 Channel2 and Channel3 Module

Definition at line 268 of file clk.h.

## ◆ RTC_MODULE

#define RTC_MODULE ((1UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_RTC_EN_Pos )

Real-Time-Clock Module

Definition at line 283 of file clk.h.

## ◆ SC0_MODULE

#define SC0_MODULE ((1UL<<31)|(2<<29)|(3<<25) |(18<<20)|(0<<18)|(0xF<<10) |(28<<5)|CLK_APBCLK_SC0_EN_Pos )

SmartCard0 Module

Definition at line 265 of file clk.h.

## ◆ SC1_MODULE

#define SC1_MODULE ((1UL<<31)|(2<<29)|(3<<25) |(18<<20)|(1<<18)|(0xF<<10) |( 0<<5)|CLK_APBCLK_SC1_EN_Pos )

SmartCard1 Module

Definition at line 264 of file clk.h.

## ◆ SPI0_MODULE

#define SPI0_MODULE ((1UL<<31)|(2<<29)|(1<<25) |(20<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_SPI0_EN_Pos )

SPI0 Module

Definition at line 273 of file clk.h.

## ◆ SPI1_MODULE

#define SPI1_MODULE ((1UL<<31)|(2<<29)|(1<<25) |(21<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_SPI1_EN_Pos )

SPI1 Module

Definition at line 272 of file clk.h.

## ◆ SRAM_MODULE

#define SRAM_MODULE ((0UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(1<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_SRAM_EN_Pos )

SRAM Module

Definition at line 258 of file clk.h.

## ◆ TICK_MODULE

#define TICK_MODULE ((0UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(1<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_TICK_EN_Pos )

TICK Module

Definition at line 257 of file clk.h.

## ◆ TMR0_MODULE

#define TMR0_MODULE ((1UL<<31)|(1<<29)|(7<<25) |( 8<<20)|(1<<18)|(0xF<<10) |( 8<<5)|CLK_APBCLK_TMR0_EN_Pos )

Timer0 Module

Definition at line 282 of file clk.h.

## ◆ TMR1_MODULE

#define TMR1_MODULE ((1UL<<31)|(1<<29)|(7<<25) |(12<<20)|(1<<18)|(0xF<<10) |(12<<5)|CLK_APBCLK_TMR1_EN_Pos )

Timer1 Module

Definition at line 281 of file clk.h.

## ◆ TMR2_MODULE

#define TMR2_MODULE ((1UL<<31)|(2<<29)|(7<<25) |( 8<<20)|(1<<18)|(0xF<<10) |(16<<5)|CLK_APBCLK_TMR2_EN_Pos )

Timer2 Module

Definition at line 280 of file clk.h.

## ◆ TMR3_MODULE

#define TMR3_MODULE ((1UL<<31)|(2<<29)|(7<<25) |(12<<20)|(1<<18)|(0xF<<10) |(20<<5)|CLK_APBCLK_TMR3_EN_Pos )

Timer3 Module

Definition at line 279 of file clk.h.

## ◆ UART0_MODULE

#define UART0_MODULE ((1UL<<31)|(1<<29)|(3<<25) |( 0<<20)|(0<<18)|(0xF<<10) |( 8<<5)|CLK_APBCLK_UART0_EN_Pos )

UART0 Module

Definition at line 271 of file clk.h.

## ◆ UART1_MODULE

#define UART1_MODULE ((1UL<<31)|(1<<29)|(3<<25) |( 0<<20)|(0<<18)|(0xF<<10) |( 8<<5)|CLK_APBCLK_UART1_EN_Pos )

UART1 Module

Definition at line 270 of file clk.h.

## ◆ WDT_MODULE

#define WDT_MODULE ((1UL<<31)|(3<<29)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK_WDT_EN_Pos )

Watchdog Timer Module

Definition at line 284 of file clk.h.