| Nano102_112 Series BSP V3.03.002 The Board Support Package for Nano102_112 Series

Data Fields
I2C_T Struct Reference

`#include <Nano1X2Series.h>`

## Data Fields
__IO uint32_t | CON
__IO uint32_t | INTSTS
__I uint32_t | STATUS
__IO uint32_t | DIV
__IO uint32_t | TOUT
__IO uint32_t | DATA
__IO uint32_t | SADDR0
__IO uint32_t | SADDR1
uint32_t | RESERVE0 [2]
__IO uint32_t | SAMASK0
__IO uint32_t | SAMASK1
uint32_t | RESERVE1 [4]
__IO uint32_t | CON2
__IO uint32_t | STATUS2

## Detailed Description

    @addtogroup I2C Inter-IC Bus Controller(I2C)
    Memory Mapped Structure for I2C Controller

Definition at line 4890 of file Nano1X2Series.h.

## Field Documentation

## ◆ CON

__IO uint32_t I2C_T::CON

# CON

## Offset: 0x00 I2C Control Register

Bits | Field | Descriptions
--- | --- | ---
[0] | IPEN | I2C Function Enable Control
|  | 0 = I2C function Disabled.
|  | 1 = I2C function Enabled.
[1] | ACK | Assert Acknowledge Control Bit
|  | 0 = When this bit is set to 0 prior to address or data received, a Not acknowledged (high level to SDA) will be returned during the acknowledge clock pulse.
|  | 1 = When this bit is set to 1 prior to address or data received, an acknowledged will be returned during the acknowledge clock pulse on the SCL line when:
|  | (a): A slave is acknowledging the address sent from master.
|  | (b): The receiver devices are acknowledging the data sent by transmitter.
[2] | STOP | I2C STOP Control Bit
|  | In Master mode, set this bit to 1 to transmit a STOP condition to bus then the controller will check the bus condition if a STOP condition is detected and this bit will be cleared by hardware automatically.
|  | In Slave mode, set this bit to 1 to reset the controller to the defined "not addressed" Slave mode.
|  | This means it is NO LONGER in the slave receiver mode to receive data from the master transmit device.
|  | 0 = Will be cleared by hardware automatically if a STOP condition is detected.
|  | 1 = Sends a STOP condition to bus in Master mode or reset the controller to "not addressed" in Slave mode.
[3] | START | I2C START Command
|  | Setting this bit to 1 to enter Master mode, the device sends a START or repeat START condition to bus when the bus is free and it will be cleared to 0 after the START command is active and the STATUS has been updated.
|  | 0 = After START or repeat START is active.
|  | 1 = Sends a START or repeat START condition to bus.
[4] | I2C_STS | I2C Status
|  | When a new state is present in the I2CSTATUS register, if the INTEN bit is set, the I2C interrupt is requested.
|  | It must write one by software to this bit after the I2CINTSTS[0] is set to 1 and the I2C protocol function will go ahead until the STOP is active or the IPEN is disabled.
|  | 0 = I2C's Status disabled and the I2C protocol function will go ahead.
|  | 1 = I2C's Status active.
[7] | INTEN | Interrupt Enable Control
|  | 0 = I2C interrupt Disabled.
|  | 1 = I2C interrupt Enabled.

Definition at line 4928 of file Nano1X2Series.h.

## ◆ CON2

__IO uint32_t I2C_T::CON2

# CON2

## Offset: 0x40 I2C Control Register 2

Bits | Field | Descriptions
--- | --- | ---
[0] | WKUPEN | I2C Wake-Up Function Enable Control
|  | 0 = I2C wake-up function Disabled.
|  | 1 = I2C wake-up function Enabled.
[1] | OVER_INTEN | I2C OVER RUN Interrupt Control Bit
|  | 0 = Overrun event interrupt Disabled.
|  | 1 = Send a interrupt to system when the TWOFF bit is enabled and there is over run event in received fifo.
[2] | UNDER_INTEN | I2C UNDER RUN Interrupt Control Bit
|  | 0 = Under run event interrupt Disabled.
|  | 1 = Send a interrupt to system when the TWOFF bit is enabled and there is under run event happened in transmitted fifo.
[4] | TWOFF_EN | TWO LEVEL FIFO Enable Control
|  | 0 = Disabled.
|  | 1 = Enabled.
[5] | NOSTRETCH | NO STRETCH The I2C BUS
|  | 0 = The I2C SCL bus is stretched by hardware if the INTSTS (I2CINTSTS[0]) is not cleared in master mode.
|  | 1 = The I2C SCL bus is not stretched by hardware if the INTSTS is not cleared in master mode.

Definition at line 5093 of file Nano1X2Series.h.

## ◆ DATA

__IO uint32_t I2C_T::DATA

# DATA

## Offset: 0x14 I2C DATA Register

Bits | Field | Descriptions
--- | --- | ---
[7:0] | DATA | I2C Data Bits
|  | The DATA contains a byte of serial data to be transmitted or a byte which has just been received.

Definition at line 5004 of file Nano1X2Series.h.

## ◆ DIV

__IO uint32_t I2C_T::DIV

# DIV

## Offset: 0x0C I2C clock divided Register

Bits | Field | Descriptions
--- | --- | ---
[7:0] | CLK_DIV | I2C Clock Divided Bits
|  | The I2C clock rate bits: Data Baud Rate of I2C = PCLK /( 4 x ( CLK_DIV + 1)).
|  | Note: the minimum value of CLK_DIV is 4.

Definition at line 4973 of file Nano1X2Series.h.

## ◆ INTSTS

__IO uint32_t I2C_T::INTSTS

# INTSTS

## Offset: 0x04 I2C Interrupt Status Register

Bits | Field | Descriptions
--- | --- | ---
[0] | INTSTS | I2C STATUS's Interrupt Status
|  | 0 = No bus event occurred.
|  | 1 = New state is presented in the I2CSTATUS. Software can write 1 to cleat this bit.
[1] | TIF | Time-Out Status
|  | 0 = No Time-out flag. Software can cleat this flag.
|  | 1 = Time-Out flag active and it is set by hardware. It can interrupt CPU when INTEN bit is set.
[7] | WAKEUP_ACK_DONE | Wakeup Address Frame Acknowledge Bit Done
|  | 0 = The ACK bit cycle of address match frame isn't done.
|  | 1 = The ACK bit cycle of address match frame is done in power-down.

Definition at line 4947 of file Nano1X2Series.h.

## ◆ RESERVE0

uint32_t I2C_T::RESERVE0[2]

Definition at line 5039 of file Nano1X2Series.h.

## ◆ RESERVE1

uint32_t I2C_T::RESERVE1[4]

Definition at line 5067 of file Nano1X2Series.h.

## ◆ SADDR0

__IO uint32_t I2C_T::SADDR0

# SADDR0

## Offset: 0x18 I2C Slave address Register0

Bits | Field | Descriptions
--- | --- | ---
[0] | GCALL | General Call Function
|  | 0 = General Call Function Disabled.
|  | 1 = General Call Function Enabled.
[7:1] | SADDR | I2C Salve Address Bits
|  | The content of this register is irrelevant when the device is in Master mode.
|  | In the Slave mode, the seven most significant bits must be loaded with the device's own address.
|  | The device will react if either of the address is matched.

Definition at line 5021 of file Nano1X2Series.h.

## ◆ SADDR1

__IO uint32_t I2C_T::SADDR1

# SADDR1

## Offset: 0x1C I2C Slave address Register1

Bits | Field | Descriptions
--- | --- | ---
[0] | GCALL | General Call Function
|  | 0 = General Call Function Disabled.
|  | 1 = General Call Function Enabled.
[7:1] | SADDR | I2C Salve Address Bits
|  | The content of this register is irrelevant when the device is in Master mode.
|  | In the Slave mode, the seven most significant bits must be loaded with the device's own address.
|  | The device will react if either of the address is matched.

Definition at line 5038 of file Nano1X2Series.h.

## ◆ SAMASK0

__IO uint32_t I2C_T::SAMASK0

# SAMASK0

## Offset: 0x28 I2C Slave address Mask Register0

Bits | Field | Descriptions
--- | --- | ---
[7:1] | SAMASK | I2C Slave Address Mask Bits
|  | 0 = Mask disable (the received corresponding register bit should be exact the same as address register).
|  | 1 = Mask enable (the received corresponding address bit is don't care).

Definition at line 5053 of file Nano1X2Series.h.

## ◆ SAMASK1

__IO uint32_t I2C_T::SAMASK1

# SAMASK1

## Offset: 0x2C I2C Slave address Mask Register1

Bits | Field | Descriptions
--- | --- | ---
[7:1] | SAMASK | I2C Slave Address Mask Bits
|  | 0 = Mask disable (the received corresponding register bit should be exact the same as address register).
|  | 1 = Mask enable (the received corresponding address bit is don't care).

Definition at line 5066 of file Nano1X2Series.h.

## ◆ STATUS

__I uint32_t I2C_T::STATUS

# STATUS

## Offset: 0x08 I2C Status Register

Bits | Field | Descriptions
--- | --- | ---
[7:0] | STATUS | I2C Status Bits (Read Only)
|  | Indicates the current status code of the bus information.
|  | The detail information about the status is described in the sections of I2C protocol register and operation mode.

Definition at line 4960 of file Nano1X2Series.h.

## ◆ STATUS2

__IO uint32_t I2C_T::STATUS2

# STATUS2

## Offset: 0x44 I2C Status Register 2

Bits | Field | Descriptions
--- | --- | ---
[0] | WKUPIF | Wake-Up Interrupt Flag
|  | 0 = Wake-up flag inactive.
|  | 1 = Wake-up flag active.
|  | Software can write 1 to clear this flag
[1] | OVERUN | I2C OVER RUN Status Bit
|  | 0 = The received FIFO is not over run when the TWOFF_EN = 1.
|  | 1 = The received FIFO is over run when the TWOFF_EN = 1.
[2] | UNDERUN | I2C UNDER RUN Status Bit
|  | 0 = The transmitted FIFO is not under run when the TWOFF_EN = 1.
|  | 1 = The transmitted FIFO is under run when the TWOFF_EN = 1.
[3] | WR_STATUS | I2C Read/Write Status Bit In Address Wakeup Frame
|  | 0 = Write command be record on the address match wakeup frame.
|  | 1 = Read command be record on the address match wakeup frame.
[4] | FULL | I2C TWO LEVEL FIFO FULL
|  | 0 = TX FIFO no full when the TWOFF_EN = 1.
|  | 1 = TX FIFO full when the TWOFF_EN = 1.
[5] | EMPTY | I2C TWO LEVEL FIFO EMPTY
|  | 0 = RX FIFO no empty when the TWOFF_EN = 1.
|  | 1 = RX FIFO empty when the TWOFF_EN = 1.
[6] | BUS_FREE | Bus Free Status
|  | The bus status in the controller.
|  | 0 = I2C's "Start" condition is detected on the bus.
|  | 1 = Bus free and it is released by "STOP" condition or the controller is disabled.

Definition at line 5126 of file Nano1X2Series.h.

## ◆ TOUT

__IO uint32_t I2C_T::TOUT

# TOUT

## Offset: 0x10 I2C Time-out control Register

Bits | Field | Descriptions
--- | --- | ---
[0] | TOUTEN | Time-Out Counter Enable/Disable Control
|  | 0 = Disabled.
|  | 1 = Enabled.
|  | When set this bit to enable, the 14 bits time-out counter will start counting when INTSTS (I2CINTSTS[0]) is cleared.
|  | Setting flag STAINTSTS to high or the falling edge of I2C clock or stop signal will reset counter and re-start up counting after INTSTS is cleared.
[1] | DIV4 | Time-Out Counter Input Clock Divider By 4
|  | 0 = Disabled.
|  | 1 = Enabled.
|  | When Enabled, the time-out period is extended 4 times.

Definition at line 4992 of file Nano1X2Series.h.

The documentation for this struct was generated from the following file:

- Device/Nuvoton/Nano1X2Series/Include/Nano1X2Series.h