| Nano102_112 Series BSP V3.03.002 The Board Support Package for Nano102_112 Series

Data Fields
ACMP_T Struct Reference
NANO102/112 Definitions » NANO102/112 Peripherals

`#include <Nano1X2Series.h>`

## Data Fields
__IO uint32_t | CR [2]
__IO uint32_t | SR
__IO uint32_t | RVCR
__IO uint32_t | MODCR0

## Detailed Description

    @addtogroup ACMP Analog Comparator Controller(ACMP)
    Memory Mapped Structure for ACMP Controller

Definition at line 156 of file Nano1X2Series.h.

## Field Documentation

## ◆ CR

__IO uint32_t ACMP_T::CR[2]

# CR0/1

## Offset: 0x00,0x04 Analog Comparator 0/1 Control Register

Bits | Field | Descriptions
--- | --- | ---
[0] | ACMPEN | Comparator ACMP0/1 Enable Control
|  | 0 = Disabled.
|  | 1 = Enabled.
|  | Note: Comparator output needs to wait 10 us stable time after ACMPEN(ACMP0EN/ACMP1EN) is set.
[1] | ACMPIE | Comparator ACMP Interrupt Enable Control
|  | 0 = ACMP interrupt function Disabled.
|  | 1 = ACMP interrupt function Enabled.
|  | Note: Interrupt generated if ACMPIE(ACMP0IE/ACMP1IE) bit is set to "1" after ACMP0/1 output changed.
[2] | ACMP_HYSEN | Comparator ACMP0/1 Hysteresis Enable Control
|  | 0 = ACMP0 Hysteresis function Disabled.
|  | 1 = ACMP0 Hysteresis function Enabled. The typical range is 20mV.
[5:4] | CN | Comparator ACMP0/1 Negative Input Selection
|  | 00 = The comparator reference pin ACMP0/1_N is selected as the negative comparator input.
|  | 01 = The internal comparator reference voltage (CRV) is selected as the negative comparator input.
|  | 10 = The internal reference voltage (Int_VREF) is selected as the negative comparator input.
|  | 11 = The AGND is selected as the negative comparator input.
[16] | ACMP0_EX | Comparator ACMP0 Swap
|  | 0 = No swap to the comparator inputs and output.
|  | 1 = Swap the comparator inputs with ACMP0_Px and ACMP0_N, and invert the polarity of comparator 0 output.
|  | Note: This bit swaps the comparator inputs and inverts the comparator output.
[19] | ACOMP0_PN_AutoEx | Comparator Analog ACMP0_Px & ACMP0_N Input Swap Function Automatically
|  | This bit is only for sigma-delta ADC mode use.
|  | 0 = Disabled to swap comparator ACMP0 input function, ACMP0_Px and ACMP0_N, automatically.
|  | 1 = Enabled to swap comparator ACMP0 input function, ACMP0_Px and ACMP0_N, automatically.
[20] | ACMP0_FILTER | Comparator ACMP0 Output Filter
|  | 0 = Comparator ACMP0 output is not filtered by internal RC filter.
|  | 1 = Comparator ACMP0 output is filtered by internal RC filter.
[21] | CPO0_SEL | Comparator ACMP0 Output To Timer Path Selection
|  | 0 = Comparator ACMP0 output to Timer is through internal path.
|  | 1 = Comparator ACMP0 output to Timer is through external pin (through PF.4).
[30:29] | CPP0SEL | Comparator ACMP0 Positive Input Selection
|  | 00 = Input from PA.4.
|  | 01 = Input from PA.3.
|  | 10 = Input from PA.2.
|  | 11 = Input from PA.1.
[31] | ACMP_WKEUP_EN | Comparator ACMP0/1 Wake-Up Enable Control
|  | 0 = Wake-up function Disabled.
|  | 1 = Wake-up function Enabled when the system enters Power-down mode.

Definition at line 206 of file Nano1X2Series.h.

## ◆ MODCR0

__IO uint32_t ACMP_T::MODCR0

# MODCR0

## Offset: 0x10 Analog Comparator 0 Mode Control Register

Bits | Field | Descriptions
--- | --- | ---
[1:0] | MOD_SEL | Comparator Mode Selection
|  | 00 = Normal Comparator Mode.
|  | 01 = Sigma-Delta ADC Mode.
|  | 10 = Single Slope ADC Mode.
|  | 11 = Reserved.
[2] | TMR_SEL | Analog Comparator 0 Co-Operation Timer Selection
|  | 0 = Select TIMER0 as co-operation Timer.
|  | 1 = Select TIMER2 as co-operation Timer.
[3] | TMR_TRI_LV | Timer Trigger Level
|  | This bit is for Sigma-Delta ADC Mode.
|  | 0 = Comparator Output Low to High to Enable Timer.
|  | 1 = Comparator Output High to Low to Enable Timer.
[6:4] | CH_DIS_PIN_SEL | Charge Or Discharge Pin Selection
|  | 000 = PA.1.
|  | 001 = PA.2.
|  | 010 = PA.3.
|  | 011 = PA.4.
|  | 100 = PA.5.
|  | 101 = PA.6.
|  | 110 = PA.14.
|  | 111 = PF.5.
[7] | CH_DIS_FUN_SEL | Charge Or Discharge Pin Function Option
|  | This bit is for Single Slope ADC Mode only.
|  | 0 = Drive low on charge pin to dis-charge capacitor and drive high on charge pin to charge capacitor.
|  | 1 = Drive high on charge pin to dis-charge capacitor and drive low on charge pin to charge capacitor.
[8] | START | Start ADC Mode
|  | 0 = Stop Sigma-Delta ADC Mode or Single Slope ADC Mode.
|  | 1 = Start Sigma-Delta ADC Mode or Single Slope ADC Mode.

Definition at line 287 of file Nano1X2Series.h.

## ◆ RVCR

__IO uint32_t ACMP_T::RVCR

# RVCR

## Offset: 0x0C Analog Comparator Reference Voltage Control Register

Bits | Field | Descriptions
--- | --- | ---
[3:0] | CRVS | Comparator Reference Voltage Setting
|  | Comparator reference voltage = VIN * (1/6+CRVS[3:0]/24). VIN = AVDD or Int_VREF.
[4] | CRV_EN | CRV Enable Control
|  | 0 = CRV Disabled.
|  | 1 = CRV Enabled.
[5] | CRVSRC_SEL | CRV Source Selection
|  | 0 = From AVDD.
|  | 1 = From Int_VREF.

Definition at line 249 of file Nano1X2Series.h.

## ◆ SR

__IO uint32_t ACMP_T::SR

# SR

## Offset: 0x08 Analog Comparator Status Register

Bits | Field | Descriptions
--- | --- | ---
[0] | ACMPF0 | Comparator ACMP0 Flag
|  | This bit is set by hardware whenever the comparator 0 output changes state.
|  | This will generate an interrupt if ACMP0IE set.
|  | Note: Write "1" to clear this bit to 0.
[1] | ACMPF1 | Comparator ACMP1 Flag
|  | This bit is set by hardware whenever the comparator 1 output changes state.
|  | This will generate an interrupt if ACMP1IE set.
|  | Note: Write "1" to clear this bit to 0.
[2] | CO0 | Comparator ACMP0 Output
|  | Synchronized to the PCLK to allow reading by software.
|  | Cleared when the comparator is disabled (ACMP0EN = 0).
[3] | CO1 | Comparator ACMP1 Output
|  | Synchronized to the PCLK to allow reading by software.
|  | Cleared when the comparator is disabled (ACMP1EN = 0).

Definition at line 231 of file Nano1X2Series.h.

The documentation for this struct was generated from the following file:

- Device/Nuvoton/Nano1X2Series/Include/Nano1X2Series.h