| Nano103 BSP V3.01.002 The Board Support Package for Nano103 Series

pwm.c
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1 /**************************************************************************/
12 #include "Nano103.h"
13
37 uint32_t PWM_ConfigCaptureChannel(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge)
38 {
39 uint32_t u32Src;
40 uint32_t u32PWMClockSrc;
41 uint32_t u32NearestUnitTimeNsec;
42 uint16_t u16Prescale = 1, u16CNR = 0xFFFF;
43
44 u32Src = CLK->CLKSEL1 & CLK_CLKSEL1_PWM0SEL_Msk;
45
46 if(u32Src == 0)
47 {
48 //clock source is from PLL clock
49 u32PWMClockSrc = CLK_GetPLLClockFreq();
50 }
51 else
52 {
53 //clock source is from PCLK
54 SystemCoreClockUpdate();
55 u32PWMClockSrc = SystemCoreClock;
56 }
57
58 u32PWMClockSrc /= 1000;
59 for(u16Prescale = 1; u16Prescale <= 0x1000; u16Prescale++)
60 {
61 u32NearestUnitTimeNsec = (1000000 * u16Prescale) / u32PWMClockSrc;
62 if(u32NearestUnitTimeNsec < u32UnitTimeNsec)
63 {
64 if(u16Prescale == 0x1000) //limit to the maximum unit time(nano second)
65 break;
66 if(!((1000000 * (u16Prescale + 1) > (u32NearestUnitTimeNsec * u32PWMClockSrc))))
67 break;
68 continue;
69 }
70 break;
71 }
72
73 // convert to real register value
74 // every two channels share a prescaler
75 PWM_SET_PRESCALER(pwm, u32ChannelNum, --u16Prescale);
76
77 // set PWM to down count type(edge aligned)
78 (pwm)->CTL1 = ((pwm)->CTL1 & ~(PWM_CTL1_CNTTYPE0_Msk << ((u32ChannelNum >> 1) << 2))) | (1UL << ((u32ChannelNum >> 1) << 2));
79
80 PWM_SET_CNR(pwm, u32ChannelNum, u16CNR);
81
82 return (u32NearestUnitTimeNsec);
83 }
84
96 uint32_t PWM_ConfigOutputChannel(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle)
97 {
98 uint32_t u32Src;
99 uint32_t u32PWMClockSrc;
100 uint32_t i;
101 uint16_t u16Prescale = 1, u16CNR = 0xFFFF;
102
103 u32Src = CLK->CLKSEL1 & CLK_CLKSEL1_PWM0SEL_Msk;
104
105 if(u32Src == 0)
106 {
107 //clock source is from PLL clock
108 u32PWMClockSrc = CLK_GetPLLClockFreq();
109 }
110 else
111 {
112 //clock source is from PCLK
113 SystemCoreClockUpdate();
114 u32PWMClockSrc = SystemCoreClock;
115 }
116
117 for(u16Prescale = 1; u16Prescale < 0xFFF; u16Prescale++) //prescale could be 0~0xFFF
118 {
119 i = (u32PWMClockSrc / u32Frequency) / u16Prescale;
120 // If target value is larger than CNR, need to use a larger prescaler
121 if(i > (0x10000))
122 continue;
123
124 u16CNR = i;
125 break;
126 }
127 // Store return value here 'cos we're gonna change u16Prescale & u16CNR to the real value to fill into register
128 i = u32PWMClockSrc / (u16Prescale * u16CNR);
129
130 // convert to real register value
131 // every two channels share a prescaler
132 PWM_SET_PRESCALER(pwm, u32ChannelNum, --u16Prescale);
133 // set PWM to down count type(edge aligned)
134 (pwm)->CTL1 = ((pwm)->CTL1 & ~(PWM_CTL1_CNTTYPE0_Msk << ((u32ChannelNum >> 1) << 2))) | (1UL << ((u32ChannelNum >> 1) << 2));
135
136 PWM_SET_CNR(pwm, u32ChannelNum, --u16CNR);
137 if(u32DutyCycle)
138 {
139 PWM_SET_CMR(pwm, u32ChannelNum, u32DutyCycle * (u16CNR + 1) / 100 - 1);
140 (pwm)->WGCTL0 &= ~((PWM_WGCTL0_PRDPCTL0_Msk | PWM_WGCTL0_ZPCTL0_Msk) << (u32ChannelNum * 2));
141 (pwm)->WGCTL0 |= (PWM_OUTPUT_LOW << (u32ChannelNum * 2 + PWM_WGCTL0_PRDPCTLn_Pos));
142 (pwm)->WGCTL1 &= ~((PWM_WGCTL1_CMPDCTL0_Msk | PWM_WGCTL1_CMPUCTL0_Msk) << (u32ChannelNum * 2));
143 (pwm)->WGCTL1 |= (PWM_OUTPUT_HIGH << (u32ChannelNum * 2 + PWM_WGCTL1_CMPDCTLn_Pos));
144 }
145 else
146 {
147 PWM_SET_CMR(pwm, u32ChannelNum, 0);
148 (pwm)->WGCTL0 &= ~((PWM_WGCTL0_PRDPCTL0_Msk | PWM_WGCTL0_ZPCTL0_Msk) << (u32ChannelNum * 2));
149 (pwm)->WGCTL0 |= (PWM_OUTPUT_LOW << (u32ChannelNum * 2 + PWM_WGCTL0_ZPCTLn_Pos));
150 (pwm)->WGCTL1 &= ~((PWM_WGCTL1_CMPDCTL0_Msk | PWM_WGCTL1_CMPUCTL0_Msk) << (u32ChannelNum * 2));
151 (pwm)->WGCTL1 |= (PWM_OUTPUT_HIGH << (u32ChannelNum * 2 + PWM_WGCTL1_CMPDCTLn_Pos));
152 }
153
154 return(i);
155 }
156
166 void PWM_Start(PWM_T *pwm, uint32_t u32ChannelMask)
167 {
168 uint32_t i;
169 for(i = 0; i < PWM_CHANNEL_NUM; i ++)
170 {
171 if(u32ChannelMask & (1 << i))
172 {
173 (pwm)->CNTEN |= (1UL << ((i >> 1) << 1));
174 }
175 }
176 }
177
187 void PWM_Stop(PWM_T *pwm, uint32_t u32ChannelMask)
188 {
189 uint32_t i;
190 for(i = 0; i < PWM_CHANNEL_NUM; i ++)
191 {
192 if(u32ChannelMask & (1 << i))
193 {
194 (pwm)->PERIOD[((i >> 1) << 1)] = 0;
195 }
196 }
197 }
198
208 void PWM_ForceStop(PWM_T *pwm, uint32_t u32ChannelMask)
209 {
210 uint32_t i;
211 for(i = 0; i < PWM_CHANNEL_NUM; i ++)
212 {
213 if(u32ChannelMask & (1 << i))
214 {
215 (pwm)->CNTEN &= ~(1UL << ((i >> 1) << 1));
216 }
217 }
218 }
219
236 void PWM_EnableADCTrigger(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition)
237 {
238 if(u32ChannelNum < 4)
239 {
240 (pwm)->ADCTS0 &= ~((PWM_ADCTS0_TRGSEL0_Msk) << (u32ChannelNum * 8));
241 (pwm)->ADCTS0 |= ((PWM_ADCTS0_TRGEN0_Msk | u32Condition) << (u32ChannelNum * 8));
242 }
243 else
244 {
245 (pwm)->ADCTS1 &= ~((PWM_ADCTS1_TRGSEL4_Msk) << ((u32ChannelNum - 4) * 8));
246 (pwm)->ADCTS1 |= ((PWM_ADCTS1_TRGEN4_Msk | u32Condition) << ((u32ChannelNum - 4) * 8));
247 }
248 }
249
258 void PWM_DisableADCTrigger(PWM_T *pwm, uint32_t u32ChannelNum)
259 {
260 if(u32ChannelNum < 4)
261 {
262 (pwm)->ADCTS0 &= ~(PWM_ADCTS0_TRGEN0_Msk << (u32ChannelNum * 8));
263 }
264 else
265 {
266 (pwm)->ADCTS1 &= ~(PWM_ADCTS1_TRGEN4_Msk << ((u32ChannelNum - 4) * 8));
267 }
268 }
269
279 void PWM_ClearADCTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition)
280 {
281 (pwm)->STATUS = ((1 << PWM_STATUS_ADCTRGn_Pos) << u32ChannelNum);
282 }
283
293 uint32_t PWM_GetADCTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum)
294 {
295 return (((pwm)->STATUS & ((1 << PWM_STATUS_ADCTRGn_Pos) << u32ChannelNum)) ? 1 : 0);
296 }
297
318 void PWM_EnableFaultBrake(PWM_T *pwm, uint32_t u32ChannelMask, uint32_t u32LevelMask, uint32_t u32BrakeSource)
319 {
320 uint32_t i;
321
322 SYS_UnlockReg();
323
324 for(i = 0; i < PWM_CHANNEL_NUM; i ++)
325 {
326 if(u32ChannelMask & (1 << i))
327 {
328 if((u32BrakeSource == PWM_FB_LEVEL_SYS_COR) || (u32BrakeSource == PWM_FB_EDGE_SYS_BOD) || \
329 (u32BrakeSource == PWM_FB_EDGE_SYS_COR) || (u32BrakeSource == PWM_FB_LEVEL_SYS_BOD))
330 {
331 *(__IO uint32_t *)(&((pwm)->BRKCTL0_1) + (i >> 1)) |= (u32BrakeSource & (PWM_BRKCTL0_1_SYSEEN_Msk | PWM_BRKCTL0_1_SYSLEN_Msk));
332 (pwm)->FAILBRK |= (u32BrakeSource & 0xF);
333 }
334 else
335 {
336 *(__IO uint32_t *)(&((pwm)->BRKCTL0_1) + (i >> 1)) |= u32BrakeSource;
337 }
338 }
339
340 if(u32LevelMask & (1 << i))
341 {
342 if(i % 2 == 0)
343 {
344 //set brake action as high level for even channel
345 *(__IO uint32_t *)(&((pwm)->BRKCTL0_1) + (i >> 1)) &= ~PWM_BRKCTL0_1_BRKAEVEN_Msk;
346 *(__IO uint32_t *)(&((pwm)->BRKCTL0_1) + (i >> 1)) |= ((3UL) << PWM_BRKCTL0_1_BRKAEVEN_Pos);
347 }
348 else
349 {
350 //set brake action as high level for odd channel
351 *(__IO uint32_t *)(&((pwm)->BRKCTL0_1) + (i >> 1)) &= ~PWM_BRKCTL0_1_BRKAODD_Msk;
352 *(__IO uint32_t *)(&((pwm)->BRKCTL0_1) + (i >> 1)) |= ((3UL) << PWM_BRKCTL0_1_BRKAODD_Pos);
353 }
354 }
355 else
356 {
357 if(i % 2 == 0)
358 {
359 //set brake action as low level for even channel
360 *(__IO uint32_t *)(&((pwm)->BRKCTL0_1) + (i >> 1)) &= ~PWM_BRKCTL0_1_BRKAEVEN_Msk;
361 *(__IO uint32_t *)(&((pwm)->BRKCTL0_1) + (i >> 1)) |= ((2UL) << PWM_BRKCTL0_1_BRKAEVEN_Pos);
362 }
363 else
364 {
365 //set brake action as low level for odd channel
366 *(__IO uint32_t *)(&((pwm)->BRKCTL0_1) + (i >> 1)) &= ~PWM_BRKCTL0_1_BRKAODD_Msk;
367 *(__IO uint32_t *)(&((pwm)->BRKCTL0_1) + (i >> 1)) |= ((2UL) << PWM_BRKCTL0_1_BRKAODD_Pos);
368 }
369 }
370 }
371
372 SYS_LockReg();
373 }
374
384 void PWM_EnableCapture(PWM_T *pwm, uint32_t u32ChannelMask)
385 {
386 (pwm)->CAPINEN |= u32ChannelMask;
387 (pwm)->CAPCTL |= u32ChannelMask;
388 }
389
399 void PWM_DisableCapture(PWM_T *pwm, uint32_t u32ChannelMask)
400 {
401 (pwm)->CAPINEN &= ~u32ChannelMask;
402 (pwm)->CAPCTL &= ~u32ChannelMask;
403 }
404
414 void PWM_EnableOutput(PWM_T *pwm, uint32_t u32ChannelMask)
415 {
416 (pwm)->POEN |= u32ChannelMask;
417 }
418
428 void PWM_DisableOutput(PWM_T *pwm, uint32_t u32ChannelMask)
429 {
430 (pwm)->POEN &= ~u32ChannelMask;
431 }
432
444 void PWM_EnableDeadZone(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Duration)
445 {
446 // every two channels share the same setting
447 *(__IO uint32_t *)(&((pwm)->DTCTL0_1) + (u32ChannelNum >> 1)) &= ~PWM_DTCTL0_1_DTCNT_Msk;
448 *(__IO uint32_t *)(&((pwm)->DTCTL0_1) + (u32ChannelNum >> 1)) |= PWM_DTCTL0_1_DTEN_Msk | u32Duration;
449 }
450
460 void PWM_DisableDeadZone(PWM_T *pwm, uint32_t u32ChannelNum)
461 {
462 // every two channels shares the same setting
463 *(__IO uint32_t *)(&((pwm)->DTCTL0_1) + (u32ChannelNum >> 1)) &= ~PWM_DTCTL0_1_DTEN_Msk;
464 }
465
477 void PWM_EnableCaptureInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge)
478 {
479 (pwm)->CAPIEN |= (u32Edge << u32ChannelNum);
480 }
481
493 void PWM_DisableCaptureInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge)
494 {
495 (pwm)->CAPIEN &= ~(u32Edge << u32ChannelNum);
496 }
497
509 void PWM_ClearCaptureIntFlag(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge)
510 {
511 (pwm)->CAPIF = (u32Edge << u32ChannelNum);
512 }
513
525 uint32_t PWM_GetCaptureIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
526 {
527 return (((((pwm)->CAPIF & (PWM_CAPTURE_INT_FALLING_LATCH << u32ChannelNum)) ? 1 : 0) << 1) | \
528 (((pwm)->CAPIF & (PWM_CAPTURE_INT_RISING_LATCH << u32ChannelNum)) ? 1 : 0));
529 }
541 void PWM_EnableDutyInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType)
542 {
543 (pwm)->INTEN0 |= (u32IntDutyType << u32ChannelNum);
544 }
545
554 void PWM_DisableDutyInt(PWM_T *pwm, uint32_t u32ChannelNum)
555 {
556 (pwm)->INTEN0 &= ~((PWM_DUTY_INT_DOWN_COUNT_MATCH_CMP | PWM_DUTY_INT_UP_COUNT_MATCH_CMP) << u32ChannelNum);
557 }
558
567 void PWM_ClearDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
568 {
569 (pwm)->INTSTS0 = ((1 << PWM_INTSTS0_CMPUIFn_Pos) | (1 << PWM_INTSTS0_CMPDIFn_Pos)) << u32ChannelNum;
570 }
571
582 uint32_t PWM_GetDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
583 {
584 return ((((pwm)->INTSTS0 & (((1 << PWM_INTSTS0_CMPDIFn_Pos) | (1 << PWM_INTSTS0_CMPUIFn_Pos)) << u32ChannelNum))) ? 1 : 0);
585 }
586
598 void PWM_EnableLoadMode(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32LoadMode)
599 {
600 (pwm)->CTL0 |= (u32LoadMode << u32ChannelNum);
601 }
602
614 void PWM_DisableLoadMode(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32LoadMode)
615 {
616 (pwm)->CTL0 &= ~(u32LoadMode << u32ChannelNum);
617 }
618
630 void PWM_EnableFaultBrakeInt(PWM_T *pwm, uint32_t u32BrakeSource)
631 {
632 SYS_UnlockReg();
633 (pwm)->INTEN1 |= (0x7 << u32BrakeSource);
634 SYS_LockReg();
635 }
636
648 void PWM_DisableFaultBrakeInt(PWM_T *pwm, uint32_t u32BrakeSource)
649 {
650 SYS_UnlockReg();
651 (pwm)->INTEN1 &= ~(0x7 << u32BrakeSource);
652 SYS_LockReg();
653 }
654
665 void PWM_ClearFaultBrakeIntFlag(PWM_T *pwm, uint32_t u32BrakeSource)
666 {
667 SYS_UnlockReg();
668 (pwm)->INTSTS1 = (0x3f << u32BrakeSource);
669 SYS_LockReg();
670 }
671
683 uint32_t PWM_GetFaultBrakeIntFlag(PWM_T *pwm, uint32_t u32BrakeSource)
684 {
685 return (((pwm)->INTSTS1 & (0x3f << u32BrakeSource)) ? 1 : 0);
686 }
687
697 void PWM_EnablePeriodInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType)
698 {
699 (pwm)->INTEN0 |= (PWM_INTEN0_PIEN0_Msk << ((u32ChannelNum >> 1) << 1));
700 }
701
710 void PWM_DisablePeriodInt(PWM_T *pwm, uint32_t u32ChannelNum)
711 {
712 (pwm)->INTEN0 &= ~(PWM_INTEN0_PIEN0_Msk << ((u32ChannelNum >> 1) << 1));
713 }
714
723 void PWM_ClearPeriodIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
724 {
725 (pwm)->INTSTS0 = (PWM_INTSTS0_PIF0_Msk << ((u32ChannelNum >> 1) << 1));
726 }
727
738 uint32_t PWM_GetPeriodIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
739 {
740 return (((pwm)->INTSTS0 & (PWM_INTSTS0_PIF0_Msk << ((u32ChannelNum >> 1) << 1))) ? 1 : 0);
741 }
742
751 void PWM_EnableZeroInt(PWM_T *pwm, uint32_t u32ChannelNum)
752 {
753 (pwm)->INTEN0 |= (PWM_INTEN0_ZIEN0_Msk << ((u32ChannelNum >> 1) << 1));
754 }
755
764 void PWM_DisableZeroInt(PWM_T *pwm, uint32_t u32ChannelNum)
765 {
766 (pwm)->INTEN0 &= ~(PWM_INTEN0_ZIEN0_Msk << ((u32ChannelNum >> 1) << 1));
767 }
768
777 void PWM_ClearZeroIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
778 {
779 (pwm)->INTSTS0 = (PWM_INTSTS0_ZIF0_Msk << ((u32ChannelNum >> 1) << 1));
780 }
781
792 uint32_t PWM_GetZeroIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
793 {
794 return (((pwm)->INTSTS0 & (PWM_INTSTS0_ZIF0_Msk << ((u32ChannelNum >> 1) << 1))) ? 1 : 0);
795 }
796
812 void PWM_SetClockSource(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel)
813 {
814 (pwm)->CLKSRC = ((pwm)->CLKSRC & ~(PWM_CLKSRC_ECLKSRC0_Msk << ((u32ChannelNum >> 1) * PWM_CLKSRC_ECLKSRC2_Pos))) | \
815 (u32ClkSrcSel << ((u32ChannelNum >> 1) * PWM_CLKSRC_ECLKSRC2_Pos));
816 }
817
836 void PWM_EnableBrakeNoiseFilter(PWM_T *pwm, uint32_t u32BrakePinNum, uint32_t u32ClkCnt, uint32_t u32ClkDivSel)
837 {
838 (pwm)->BNF = ((pwm)->BNF & ~((PWM_BNF_BRK0FCNT_Msk | PWM_BNF_BRK0FCS_Msk) << (u32BrakePinNum * PWM_BNF_BRK1FEN_Pos))) | \
839 (((u32ClkCnt << PWM_BNF_BRK0FCNT_Pos) | (u32ClkDivSel << PWM_BNF_BRK0FCS_Pos) | PWM_BNF_BRK0FEN_Msk) << (u32BrakePinNum * PWM_BNF_BRK1FEN_Pos));
840 }
841
850 void PWM_DisableBrakeNoiseFilter(PWM_T *pwm, uint32_t u32BrakePinNum)
851 {
852 (pwm)->BNF &= ~(PWM_BNF_BRK0FEN_Msk << (u32BrakePinNum * PWM_BNF_BRK1FEN_Pos));
853 }
854
863 void PWM_EnableBrakePinInverse(PWM_T *pwm, uint32_t u32BrakePinNum)
864 {
865 (pwm)->BNF |= (PWM_BNF_BRK0PINV_Msk << (u32BrakePinNum * PWM_BNF_BRK1FEN_Pos));
866 }
867
876 void PWM_DisableBrakePinInverse(PWM_T *pwm, uint32_t u32BrakePinNum)
877 {
878 (pwm)->BNF &= ~(PWM_BNF_BRK0PINV_Msk << (u32BrakePinNum * PWM_BNF_BRK1FEN_Pos));
879 }
880
890 void PWM_SetBrakePinSource(PWM_T *pwm, uint32_t u32BrakePinNum, uint32_t u32SelAnotherModule)
891 {
892 (pwm)->BNF = ((pwm)->BNF & ~(PWM_BNF_BK0SRC_Msk << (u32BrakePinNum * 8))) | (u32SelAnotherModule << (PWM_BNF_BK0SRC_Pos + u32BrakePinNum * 8));
893 }
894
905 uint32_t PWM_GetWrapAroundFlag(PWM_T *pwm, uint32_t u32ChannelNum)
906 {
907 return (((pwm)->STATUS & (PWM_STATUS_CNTMAX0_Msk << ((u32ChannelNum >> 1) << 1))) ? 1 : 0);
908 }
909
918 void PWM_ClearWrapAroundFlag(PWM_T *pwm, uint32_t u32ChannelNum)
919 {
920 (pwm)->STATUS = (PWM_STATUS_CNTMAX0_Msk << ((u32ChannelNum >> 1) << 1));
921 }
922
923 /* end of group NANO103_PWM_EXPORTED_FUNCTIONS */
925 /* end of group NANO103_PWM_Driver */
927 /* end of group NANO103_Device_Driver */
929
930 /*** (C) COPYRIGHT 2015 Nuvoton Technology Corp. ***/
PWM_EnableLoadMode
void PWM_EnableLoadMode(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32LoadMode)
Enable load mode of selected channel.
Definition: pwm.c:598
PWM_ClearADCTriggerFlag
void PWM_ClearADCTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition)
Clear selected channel trigger ADC flag.
Definition: pwm.c:279
PWM_GetFaultBrakeIntFlag
uint32_t PWM_GetFaultBrakeIntFlag(PWM_T *pwm, uint32_t u32BrakeSource)
This function get fault brake interrupt flag of selected source.
Definition: pwm.c:683
PWM_WGCTL0_ZPCTLn_Pos
#define PWM_WGCTL0_ZPCTLn_Pos
Definition: Nano103.h:17024
PWM_EnableADCTrigger
void PWM_EnableADCTrigger(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition)
Enable selected channel to trigger ADC.
Definition: pwm.c:236
PWM_GetZeroIntFlag
uint32_t PWM_GetZeroIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
Get zero interrupt of selected channel.
Definition: pwm.c:792
PWM_BNF_BRK0PINV_Msk
#define PWM_BNF_BRK0PINV_Msk
Definition: Nano103.h:17052
PWM_WGCTL0_PRDPCTLn_Pos
#define PWM_WGCTL0_PRDPCTLn_Pos
Definition: Nano103.h:17027
PWM_WGCTL1_CMPUCTL0_Msk
#define PWM_WGCTL1_CMPUCTL0_Msk
Definition: pwm.h:66
PWM_DisableZeroInt
void PWM_DisableZeroInt(PWM_T *pwm, uint32_t u32ChannelNum)
Disable zero interrupt of selected channel.
Definition: pwm.c:764
PWM_SetClockSource
void PWM_SetClockSource(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel)
Set PWM clock source.
Definition: pwm.c:812
PWM_GetPeriodIntFlag
uint32_t PWM_GetPeriodIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
Get period interrupt of selected channel.
Definition: pwm.c:738
PWM_SET_CNR
#define PWM_SET_CNR(pwm, u32ChannelNum, u32CNR)
This macro set the period of the selected channel.
Definition: pwm.h:246
SYS_UnlockReg
__STATIC_INLINE void SYS_UnlockReg(void)
Disable register write-protection function.
Definition: sys.h:615
SYS_LockReg
__STATIC_INLINE void SYS_LockReg(void)
Enable register write-protection function.
Definition: sys.h:632
PWM_ADCTS1_TRGEN4_Msk
#define PWM_ADCTS1_TRGEN4_Msk
Definition: Nano103.h:17328
PWM_CAPTURE_INT_RISING_LATCH
#define PWM_CAPTURE_INT_RISING_LATCH
Definition: pwm.h:99
PWM_STATUS_ADCTRGn_Pos
#define PWM_STATUS_ADCTRGn_Pos
Definition: Nano103.h:17345
PWM_EnablePeriodInt
void PWM_EnablePeriodInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType)
Enable period interrupt of selected channel.
Definition: pwm.c:697
PWM_EnableDutyInt
void PWM_EnableDutyInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType)
Enable duty interrupt of selected channel.
Definition: pwm.c:541
PWM_INTEN0_PIEN0_Msk
#define PWM_INTEN0_PIEN0_Msk
Definition: Nano103.h:17172
CLK_CLKSEL1_PWM0SEL_Msk
#define CLK_CLKSEL1_PWM0SEL_Msk
Definition: Nano103.h:5080
PWM_DTCTL0_1_DTEN_Msk
#define PWM_DTCTL0_1_DTEN_Msk
Definition: Nano103.h:16995
PWM_EnableBrakePinInverse
void PWM_EnableBrakePinInverse(PWM_T *pwm, uint32_t u32BrakePinNum)
Enable PWM brake pin inverse function.
Definition: pwm.c:863
PWM_BRKCTL0_1_BRKAODD_Msk
#define PWM_BRKCTL0_1_BRKAODD_Msk
Definition: Nano103.h:17100
PWM_ClearCaptureIntFlag
void PWM_ClearCaptureIntFlag(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge)
Clear capture interrupt of selected channel.
Definition: pwm.c:509
PWM_INTEN0_ZIEN0_Msk
#define PWM_INTEN0_ZIEN0_Msk
Definition: Nano103.h:17163
PWM_DTCTL0_1_DTCNT_Msk
#define PWM_DTCTL0_1_DTCNT_Msk
Definition: Nano103.h:16992
PWM_DUTY_INT_UP_COUNT_MATCH_CMP
#define PWM_DUTY_INT_UP_COUNT_MATCH_CMP
Definition: pwm.h:108
PWM_BRKCTL0_1_SYSLEN_Msk
#define PWM_BRKCTL0_1_SYSLEN_Msk
Definition: Nano103.h:17094
PWM_CLKSRC_ECLKSRC0_Msk
#define PWM_CLKSRC_ECLKSRC0_Msk
Definition: Nano103.h:16950
PWM_OUTPUT_HIGH
#define PWM_OUTPUT_HIGH
Definition: pwm.h:58
PWM_FB_EDGE_SYS_BOD
#define PWM_FB_EDGE_SYS_BOD
Definition: pwm.h:85
PWM_BRKCTL0_1_BRKAODD_Pos
#define PWM_BRKCTL0_1_BRKAODD_Pos
Definition: Nano103.h:17099
SystemCoreClock
uint32_t SystemCoreClock
Definition: system_Nano103.c:20
PWM_BRKCTL0_1_BRKAEVEN_Msk
#define PWM_BRKCTL0_1_BRKAEVEN_Msk
Definition: Nano103.h:17097
PWM_CHANNEL_NUM
#define PWM_CHANNEL_NUM
Definition: pwm.h:32
PWM_BRKCTL0_1_SYSEEN_Msk
#define PWM_BRKCTL0_1_SYSEEN_Msk
Definition: Nano103.h:17085
PWM_Stop
void PWM_Stop(PWM_T *pwm, uint32_t u32ChannelMask)
Stop PWM module.
Definition: pwm.c:187
PWM_ClearWrapAroundFlag
void PWM_ClearWrapAroundFlag(PWM_T *pwm, uint32_t u32ChannelNum)
Clear the time-base counter reached its maximum value flag of selected channel.
Definition: pwm.c:918
PWM_ADCTS0_TRGEN0_Msk
#define PWM_ADCTS0_TRGEN0_Msk
Definition: Nano103.h:17304
PWM_SET_PRESCALER
#define PWM_SET_PRESCALER(pwm, u32ChannelNum, u32Prescaler)
This macro set the prescaler of the selected channel.
Definition: pwm.h:221
PWM_DisableDeadZone
void PWM_DisableDeadZone(PWM_T *pwm, uint32_t u32ChannelNum)
Disable Dead zone of selected channel.
Definition: pwm.c:460
PWM_EnableOutput
void PWM_EnableOutput(PWM_T *pwm, uint32_t u32ChannelMask)
Enables PWM output generation of selected channel(s)
Definition: pwm.c:414
PWM_EnableCaptureInt
void PWM_EnableCaptureInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge)
Enable capture interrupt of selected channel.
Definition: pwm.c:477
PWM_GetADCTriggerFlag
uint32_t PWM_GetADCTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum)
Get selected channel trigger ADC flag.
Definition: pwm.c:293
PWM_CLKSRC_ECLKSRC2_Pos
#define PWM_CLKSRC_ECLKSRC2_Pos
Definition: Nano103.h:16952
PWM_DUTY_INT_DOWN_COUNT_MATCH_CMP
#define PWM_DUTY_INT_DOWN_COUNT_MATCH_CMP
Definition: pwm.h:107
PWM_DisableCaptureInt
void PWM_DisableCaptureInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge)
Disable capture interrupt of selected channel.
Definition: pwm.c:493
PWM_WGCTL1_CMPDCTL0_Msk
#define PWM_WGCTL1_CMPDCTL0_Msk
Definition: pwm.h:67
PWM_FB_LEVEL_SYS_COR
#define PWM_FB_LEVEL_SYS_COR
Definition: pwm.h:91
PWM_DisableOutput
void PWM_DisableOutput(PWM_T *pwm, uint32_t u32ChannelMask)
Disables PWM output generation of selected channel(s)
Definition: pwm.c:428
PWM_STATUS_CNTMAX0_Msk
#define PWM_STATUS_CNTMAX0_Msk
Definition: Nano103.h:17337
PWM_ForceStop
void PWM_ForceStop(PWM_T *pwm, uint32_t u32ChannelMask)
Stop PWM generation immediately by clear channel enable bit.
Definition: pwm.c:208
PWM_BNF_BK0SRC_Msk
#define PWM_BNF_BK0SRC_Msk
Definition: Nano103.h:17067
PWM_EnableFaultBrake
void PWM_EnableFaultBrake(PWM_T *pwm, uint32_t u32ChannelMask, uint32_t u32LevelMask, uint32_t u32BrakeSource)
This function enable fault brake of selected channel(s)
Definition: pwm.c:318
CLK_GetPLLClockFreq
uint32_t CLK_GetPLLClockFreq(void)
This function get PLL frequency. The frequency unit is Hz.
Definition: clk.c:176
PWM_BNF_BK0SRC_Pos
#define PWM_BNF_BK0SRC_Pos
Definition: Nano103.h:17066
PWM_ClearDutyIntFlag
void PWM_ClearDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
Clear duty interrupt flag of selected channel.
Definition: pwm.c:567
PWM_BRKCTL0_1_BRKAEVEN_Pos
#define PWM_BRKCTL0_1_BRKAEVEN_Pos
Definition: Nano103.h:17096
PWM_BNF_BRK0FCS_Pos
#define PWM_BNF_BRK0FCS_Pos
Definition: Nano103.h:17045
PWM_FB_EDGE_SYS_COR
#define PWM_FB_EDGE_SYS_COR
Definition: pwm.h:86
PWM_Start
void PWM_Start(PWM_T *pwm, uint32_t u32ChannelMask)
Start PWM module.
Definition: pwm.c:166
PWM_ClearZeroIntFlag
void PWM_ClearZeroIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
Clear zero interrupt of selected channel.
Definition: pwm.c:777
PWM_INTSTS0_PIF0_Msk
#define PWM_INTSTS0_PIF0_Msk
Definition: Nano103.h:17214
PWM_WGCTL0_PRDPCTL0_Msk
#define PWM_WGCTL0_PRDPCTL0_Msk
Definition: pwm.h:65
PWM_BNF_BRK0FCNT_Msk
#define PWM_BNF_BRK0FCNT_Msk
Definition: Nano103.h:17049
PWM_DisableLoadMode
void PWM_DisableLoadMode(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32LoadMode)
Disable load mode of selected channel.
Definition: pwm.c:614
PWM_GetWrapAroundFlag
uint32_t PWM_GetWrapAroundFlag(PWM_T *pwm, uint32_t u32ChannelNum)
Get the time-base counter reached its maximum value flag of selected channel.
Definition: pwm.c:905
PWM_GetCaptureIntFlag
uint32_t PWM_GetCaptureIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
Get capture interrupt of selected channel.
Definition: pwm.c:525
PWM_DisableADCTrigger
void PWM_DisableADCTrigger(PWM_T *pwm, uint32_t u32ChannelNum)
Disable selected channel to trigger ADC.
Definition: pwm.c:258
PWM_BNF_BRK0FCNT_Pos
#define PWM_BNF_BRK0FCNT_Pos
Definition: Nano103.h:17048
PWM_OUTPUT_LOW
#define PWM_OUTPUT_LOW
Definition: pwm.h:57
PWM_INTSTS0_CMPDIFn_Pos
#define PWM_INTSTS0_CMPDIFn_Pos
Definition: Nano103.h:17225
PWM_WGCTL0_ZPCTL0_Msk
#define PWM_WGCTL0_ZPCTL0_Msk
Definition: pwm.h:64
Nano103.h
NANO103 peripheral access layer header file. This file contains all the peripheral register's definit...
PWM_DisableFaultBrakeInt
void PWM_DisableFaultBrakeInt(PWM_T *pwm, uint32_t u32BrakeSource)
This function disable fault brake interrupt.
Definition: pwm.c:648
SystemCoreClockUpdate
void SystemCoreClockUpdate(void)
Updates the SystemCoreClock with current core Clock retrieved from CPU registers.
Definition: system_Nano103.c:134
PWM_ConfigOutputChannel
uint32_t PWM_ConfigOutputChannel(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle)
This function Configure PWM generator and get the nearest frequency in edge aligned auto-reload mode.
Definition: pwm.c:96
PWM_BNF_BRK0FCS_Msk
#define PWM_BNF_BRK0FCS_Msk
Definition: Nano103.h:17046
PWM_BNF_BRK0FEN_Msk
#define PWM_BNF_BRK0FEN_Msk
Definition: Nano103.h:17043
PWM_EnableFaultBrakeInt
void PWM_EnableFaultBrakeInt(PWM_T *pwm, uint32_t u32BrakeSource)
This function enable fault brake interrupt.
Definition: pwm.c:630
PWM_EnableDeadZone
void PWM_EnableDeadZone(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Duration)
Enable Dead zone of selected channel.
Definition: pwm.c:444
PWM_SET_CMR
#define PWM_SET_CMR(pwm, u32ChannelNum, u32CMR)
This macro set the comparator of the selected channel.
Definition: pwm.h:233
PWM_INTSTS0_CMPUIFn_Pos
#define PWM_INTSTS0_CMPUIFn_Pos
Definition: Nano103.h:17222
PWM_CAPTURE_INT_FALLING_LATCH
#define PWM_CAPTURE_INT_FALLING_LATCH
Definition: pwm.h:100
PWM_ConfigCaptureChannel
uint32_t PWM_ConfigCaptureChannel(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge)
Configure PWM capture and get the nearest unit time.
Definition: pwm.c:37
PWM_FB_LEVEL_SYS_BOD
#define PWM_FB_LEVEL_SYS_BOD
Definition: pwm.h:90
PWM_SetBrakePinSource
void PWM_SetBrakePinSource(PWM_T *pwm, uint32_t u32BrakePinNum, uint32_t u32SelAnotherModule)
Set PWM brake pin source.
Definition: pwm.c:890
PWM_ClearFaultBrakeIntFlag
void PWM_ClearFaultBrakeIntFlag(PWM_T *pwm, uint32_t u32BrakeSource)
This function clear fault brake interrupt of selected source.
Definition: pwm.c:665
CLK
#define CLK
Pointer to CLK register structure.
Definition: Nano103.h:24884
PWM_EnableCapture
void PWM_EnableCapture(PWM_T *pwm, uint32_t u32ChannelMask)
Enable capture of selected channel(s)
Definition: pwm.c:384
PWM_CTL1_CNTTYPE0_Msk
#define PWM_CTL1_CNTTYPE0_Msk
Definition: Nano103.h:16938
PWM_ADCTS1_TRGSEL4_Msk
#define PWM_ADCTS1_TRGSEL4_Msk
Definition: Nano103.h:17325
PWM_GetDutyIntFlag
uint32_t PWM_GetDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
Get duty interrupt flag of selected channel.
Definition: pwm.c:582
PWM_EnableBrakeNoiseFilter
void PWM_EnableBrakeNoiseFilter(PWM_T *pwm, uint32_t u32BrakePinNum, uint32_t u32ClkCnt, uint32_t u32ClkDivSel)
Enable PWM brake noise filter function.
Definition: pwm.c:836
PWM_EnableZeroInt
void PWM_EnableZeroInt(PWM_T *pwm, uint32_t u32ChannelNum)
Enable zero interrupt of selected channel.
Definition: pwm.c:751
PWM_WGCTL1_CMPDCTLn_Pos
#define PWM_WGCTL1_CMPDCTLn_Pos
Definition: Nano103.h:17033
PWM_BNF_BRK1FEN_Pos
#define PWM_BNF_BRK1FEN_Pos
Definition: Nano103.h:17054
PWM_ADCTS0_TRGSEL0_Msk
#define PWM_ADCTS0_TRGSEL0_Msk
Definition: Nano103.h:17301
PWM_DisableBrakePinInverse
void PWM_DisableBrakePinInverse(PWM_T *pwm, uint32_t u32BrakePinNum)
Disable PWM brake pin inverse function.
Definition: pwm.c:876
PWM_DisableDutyInt
void PWM_DisableDutyInt(PWM_T *pwm, uint32_t u32ChannelNum)
Disable duty interrupt of selected channel.
Definition: pwm.c:554
PWM_INTSTS0_ZIF0_Msk
#define PWM_INTSTS0_ZIF0_Msk
Definition: Nano103.h:17205
PWM_DisableBrakeNoiseFilter
void PWM_DisableBrakeNoiseFilter(PWM_T *pwm, uint32_t u32BrakePinNum)
Disable PWM brake noise filter function.
Definition: pwm.c:850
PWM_DisableCapture
void PWM_DisableCapture(PWM_T *pwm, uint32_t u32ChannelMask)
Disable capture of selected channel(s)
Definition: pwm.c:399
PWM_DisablePeriodInt
void PWM_DisablePeriodInt(PWM_T *pwm, uint32_t u32ChannelNum)
Disable period interrupt of selected channel.
Definition: pwm.c:710
PWM_ClearPeriodIntFlag
void PWM_ClearPeriodIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
Clear period interrupt of selected channel.
Definition: pwm.c:723
PWM_T
Definition: Nano103.h:14357