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Nano103 BSP
V3.01.002
The Board Support Package for Nano103 Series
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NANO103 Series system control header file. More...
Go to the source code of this file.
Macros | |
| #define | CHIP_RST ((0x0<<24) | SYS_IPRST1_CHIPRST_Pos ) |
| #define | CPU_RST ((0x0<<24) | SYS_IPRST1_CPURST_Pos ) |
| #define | DMA_RST ((0x0<<24) | SYS_IPRST1_PDMARST_Pos ) |
| #define | SC1_RST ((0x4<<24) | SYS_IPRST2_SC1RST_Pos ) |
| #define | SC0_RST ((0x4<<24) | SYS_IPRST2_SC0RST_Pos ) |
| #define | ADC_RST ((0x4<<24) | SYS_IPRST2_ADCRST_Pos ) |
| #define | ACMP0_RST ((0x4<<24) | SYS_IPRST2_ACMP0RST_Pos ) |
| #define | PWM0_RST ((0x4<<24) | SYS_IPRST2_PWM0RST_Pos ) |
| #define | UART1_RST ((0x4<<24) | SYS_IPRST2_UART1RST_Pos ) |
| #define | UART0_RST ((0x4<<24) | SYS_IPRST2_UART0RST_Pos ) |
| #define | SPI3_RST ((0x4<<24) | SYS_IPRST2_SPI3RST_Pos ) |
| #define | SPI2_RST ((0x4<<24) | SYS_IPRST2_SPI2RST_Pos ) |
| #define | SPI1_RST ((0x4<<24) | SYS_IPRST2_SPI1RST_Pos ) |
| #define | SPI0_RST ((0x4<<24) | SYS_IPRST2_SPI0RST_Pos ) |
| #define | I2C1_RST ((0x4<<24) | SYS_IPRST2_I2C1RST_Pos ) |
| #define | I2C0_RST ((0x4<<24) | SYS_IPRST2_I2C0RST_Pos ) |
| #define | TMR3_RST ((0x4<<24) | SYS_IPRST2_TMR3RST_Pos ) |
| #define | TMR2_RST ((0x4<<24) | SYS_IPRST2_TMR2RST_Pos ) |
| #define | TMR1_RST ((0x4<<24) | SYS_IPRST2_TMR1RST_Pos ) |
| #define | TMR0_RST ((0x4<<24) | SYS_IPRST2_TMR0RST_Pos ) |
| #define | GPIO_RST ((0x4<<24) | SYS_IPRST2_GPIORST_Pos ) |
| #define | SYS_BODCTL_BOD_RST_EN (1UL<<SYS_BODCTL_BODREN_Pos) |
| #define | SYS_BODCTL_BOD_INTERRUPT_EN (1UL<<SYS_BODCTL_BODIE_Pos) |
| #define | SYS_BODCTL_BODVL_1_7V (0UL<<SYS_BODCTL_BODVL_Pos) |
| #define | SYS_BODCTL_BODVL_1_8V (1UL<<SYS_BODCTL_BODVL_Pos) |
| #define | SYS_BODCTL_BODVL_1_9V (2UL<<SYS_BODCTL_BODVL_Pos) |
| #define | SYS_BODCTL_BODVL_2_0V (3UL<<SYS_BODCTL_BODVL_Pos) |
| #define | SYS_BODCTL_BODVL_2_1V (4UL<<SYS_BODCTL_BODVL_Pos) |
| #define | SYS_BODCTL_BODVL_2_2V (5UL<<SYS_BODCTL_BODVL_Pos) |
| #define | SYS_BODCTL_BODVL_2_3V (6UL<<SYS_BODCTL_BODVL_Pos) |
| #define | SYS_BODCTL_BODVL_2_4V (7UL<<SYS_BODCTL_BODVL_Pos) |
| #define | SYS_BODCTL_BODVL_2_5V (8UL<<SYS_BODCTL_BODVL_Pos) |
| #define | SYS_BODCTL_BODVL_2_6V (9UL<<SYS_BODCTL_BODVL_Pos) |
| #define | SYS_BODCTL_BODVL_2_7V (0xAUL<<SYS_BODCTL_BODVL_Pos) |
| #define | SYS_BODCTL_BODVL_2_8V (0xBUL<<SYS_BODCTL_BODVL_Pos) |
| #define | SYS_BODCTL_BODVL_2_9V (0xCUL<<SYS_BODCTL_BODVL_Pos) |
| #define | SYS_BODCTL_BODVL_3_0V (0xDUL<<SYS_BODCTL_BODVL_Pos) |
| #define | SYS_BODCTL_BODVL_3_1V (0xEUL<<SYS_BODCTL_BODVL_Pos) |
| #define | SYS_BODCTL_LPBOD_RST_EN (1UL<<SYS_BODCTL_LPBODREN_Pos) |
| #define | SYS_BODCTL_LPBOD_INTERRUPT_EN (1UL<<SYS_BODCTL_LPBODIE_Pos) |
| #define | SYS_BODCTL_LPBODVL_2_0V (0UL<<SYS_BODCTL_LPBODVL_Pos) |
| #define | SYS_BODCTL_LPBODVL_2_5V (1UL<<SYS_BODCTL_LPBODVL_Pos) |
| #define | SYS_IVREFCTL_BGP_EN ((uint32_t)0x00000001) |
| #define | SYS_IVREFCTL_REG_EN ((uint32_t)0x00000002) |
| #define | SYS_IVREFCTL_SEL25 ((uint32_t)0x00000008) |
| #define | SYS_IVREFCTL_SEL18 ((uint32_t)0x00000004) |
| #define | SYS_IVREFCTL_SEL15 ((uint32_t)0x00000000) |
| #define | SYS_IVREFCTL_EXTMODE ((uint32_t)0x00000010) |
| #define | SYS_LDOCTL_LDO_LEVEL12 ((uint32_t)0x00000000) |
| #define | SYS_LDOCTL_LDO_LEVEL16 ((uint32_t)0x00000004) |
| #define | SYS_LDOCTL_LDO_LEVEL18 ((uint32_t)0x00000008) |
| #define | SYS_IRC0TCTL_TRIM_11_0592M ((uint32_t)0x00000001) |
| #define | SYS_IRC0TCTL_TRIM_12M ((uint32_t)0x00000002) |
| #define | SYS_IRC0TCTL_TRIM_12_288M ((uint32_t)0x00000003) |
| #define | SYS_IRC0TCTL_TRIM_16M ((uint32_t)0x00000004) |
| #define | SYS_IRC1TCTL_TRIM_36M ((uint32_t)0x00000002) |
| #define | SYS_MIRCTCTL_TRIM_4M ((uint32_t)0x00000002) |
| #define | SYS_IRCTCTL_LOOP_4CLK ((uint32_t)0x00000000) |
| #define | SYS_IRCTCTL_LOOP_8CLK ((uint32_t)0x00000010) |
| #define | SYS_IRCTCTL_LOOP_16CLK ((uint32_t)0x00000020) |
| #define | SYS_IRCTCTL_LOOP_32CLK ((uint32_t)0x00000030) |
| #define | SYS_IRCTCTL_RETRY_64 ((uint32_t)0x00000000) |
| #define | SYS_IRCTCTL_RETRY_128 ((uint32_t)0x00000040) |
| #define | SYS_IRCTCTL_RETRY_256 ((uint32_t)0x00000080) |
| #define | SYS_IRCTCTL_RETRY_512 ((uint32_t)0x000000C0) |
| #define | SYS_IRCTCTL_CLKERR_STOP ((uint32_t)0x00000100) |
| #define | SYS_IRCTIEN_DISABLE ((uint32_t)0x00000000) |
| #define | SYS_IRCTIEN_FAIL_EN ((uint32_t)0x00000002) |
| #define | SYS_IRCTIEN_32KERR_EN ((uint32_t)0x00000004) |
| #define | SYS_IRCTISTS_FREQLOCK ((uint32_t)0x00000001) |
| #define | SYS_IRCTISTS_FAIL_INT ((uint32_t)0x00000002) |
| #define | SYS_IRCTISTS_32KERR_INT ((uint32_t)0x00000004) |
| #define | SYS_GPA_MFPL_PA0MFP_GPIO (0x00UL<<SYS_GPA_MFPL_PA0MFP_Pos) |
| #define | SYS_GPA_MFPL_PA0MFP_ADC_CH0 (0x01UL<<SYS_GPA_MFPL_PA0MFP_Pos) |
| #define | SYS_GPA_MFPL_PA0MFP_ACMP0_P (0x02UL<<SYS_GPA_MFPL_PA0MFP_Pos) |
| #define | SYS_GPA_MFPL_PA0MFP_TM2_EXT (0x03UL<<SYS_GPA_MFPL_PA0MFP_Pos) |
| #define | SYS_GPA_MFPL_PA0MFP_PWM0_CH2 (0x05UL<<SYS_GPA_MFPL_PA0MFP_Pos) |
| #define | SYS_GPA_MFPL_PA0MFP_SPI3_MOSI1 (0x06UL<<SYS_GPA_MFPL_PA0MFP_Pos) |
| #define | SYS_GPA_MFPL_PA1MFP_GPIO (0x00UL<<SYS_GPA_MFPL_PA1MFP_Pos) |
| #define | SYS_GPA_MFPL_PA1MFP_ADC_CH1 (0x01UL<<SYS_GPA_MFPL_PA1MFP_Pos) |
| #define | SYS_GPA_MFPL_PA1MFP_ACMP0_N (0x02UL<<SYS_GPA_MFPL_PA1MFP_Pos) |
| #define | SYS_GPA_MFPL_PA1MFP_SPI3_MISO1 (0x06UL<<SYS_GPA_MFPL_PA1MFP_Pos) |
| #define | SYS_GPA_MFPL_PA2MFP_GPIO (0x00UL<<SYS_GPA_MFPL_PA2MFP_Pos) |
| #define | SYS_GPA_MFPL_PA2MFP_ADC_CH2 (0x01UL<<SYS_GPA_MFPL_PA2MFP_Pos) |
| #define | SYS_GPA_MFPL_PA2MFP_UART1_RXD (0x05UL<<SYS_GPA_MFPL_PA2MFP_Pos) |
| #define | SYS_GPA_MFPL_PA3MFP_GPIO (0x00UL<<SYS_GPA_MFPL_PA3MFP_Pos) |
| #define | SYS_GPA_MFPL_PA3MFP_ADC_CH3 (0x01UL<<SYS_GPA_MFPL_PA3MFP_Pos) |
| #define | SYS_GPA_MFPL_PA3MFP_UART1_TXD (0x05UL<<SYS_GPA_MFPL_PA3MFP_Pos) |
| #define | SYS_GPA_MFPL_PA3MFP_SPI3_MOSI0 (0x06UL<<SYS_GPA_MFPL_PA3MFP_Pos) |
| #define | SYS_GPA_MFPL_PA4MFP_GPIO (0x00UL<<SYS_GPA_MFPL_PA4MFP_Pos) |
| #define | SYS_GPA_MFPL_PA4MFP_ADC_CH4 (0x01UL<<SYS_GPA_MFPL_PA4MFP_Pos) |
| #define | SYS_GPA_MFPL_PA4MFP_I2C0_SDA (0x05UL<<SYS_GPA_MFPL_PA4MFP_Pos) |
| #define | SYS_GPA_MFPL_PA4MFP_SPI3_MISO0 (0x06UL<<SYS_GPA_MFPL_PA4MFP_Pos) |
| #define | SYS_GPA_MFPL_PA5MFP_GPIO (0x00UL<<SYS_GPA_MFPL_PA5MFP_Pos) |
| #define | SYS_GPA_MFPL_PA5MFP_ADC_CH5 (0x01UL<<SYS_GPA_MFPL_PA5MFP_Pos) |
| #define | SYS_GPA_MFPL_PA5MFP_I2C0_SCL (0x05UL<<SYS_GPA_MFPL_PA5MFP_Pos) |
| #define | SYS_GPA_MFPL_PA5MFP_SPI3_CLK (0x06UL<<SYS_GPA_MFPL_PA5MFP_Pos) |
| #define | SYS_GPA_MFPL_PA6MFP_GPIO (0x00UL<<SYS_GPA_MFPL_PA6MFP_Pos) |
| #define | SYS_GPA_MFPL_PA6MFP_ADC_CH6 (0x01UL<<SYS_GPA_MFPL_PA6MFP_Pos) |
| #define | SYS_GPA_MFPL_PA6MFP_ACMP0_O (0x02UL<<SYS_GPA_MFPL_PA6MFP_Pos) |
| #define | SYS_GPA_MFPL_PA6MFP_TM3_EXT (0x03UL<<SYS_GPA_MFPL_PA6MFP_Pos) |
| #define | SYS_GPA_MFPL_PA6MFP_TM3_CNT (0x04UL<<SYS_GPA_MFPL_PA6MFP_Pos) |
| #define | SYS_GPA_MFPL_PA6MFP_PWM0_CH3 (0x05UL<<SYS_GPA_MFPL_PA6MFP_Pos) |
| #define | SYS_GPA_MFPL_PA6MFP_SPI3_SS0 (0x06UL<<SYS_GPA_MFPL_PA6MFP_Pos) |
| #define | SYS_GPA_MFPL_PA6MFP_TM3_OUT (0x07UL<<SYS_GPA_MFPL_PA6MFP_Pos) |
| #define | SYS_GPA_MFPH_PA8MFP_GPIO (0x00UL<<SYS_GPA_MFPH_PA8MFP_Pos) |
| #define | SYS_GPA_MFPH_PA8MFP_I2C0_SDA (0x01UL<<SYS_GPA_MFPH_PA8MFP_Pos) |
| #define | SYS_GPA_MFPH_PA8MFP_TM0_CNT (0x02UL<<SYS_GPA_MFPH_PA8MFP_Pos) |
| #define | SYS_GPA_MFPH_PA8MFP_SC0_CLK (0x03UL<<SYS_GPA_MFPH_PA8MFP_Pos) |
| #define | SYS_GPA_MFPH_PA8MFP_SPI2_SS0 (0x04UL<<SYS_GPA_MFPH_PA8MFP_Pos) |
| #define | SYS_GPA_MFPH_PA8MFP_TM0_OUT (0x05UL<<SYS_GPA_MFPH_PA8MFP_Pos) |
| #define | SYS_GPA_MFPH_PA8MFP_UART1_nCTS (0x06UL<<SYS_GPA_MFPH_PA8MFP_Pos) |
| #define | SYS_GPA_MFPH_PA9MFP_GPIO (0x00UL<<SYS_GPA_MFPH_PA9MFP_Pos) |
| #define | SYS_GPA_MFPH_PA9MFP_I2C0_SCL (0x01UL<<SYS_GPA_MFPH_PA9MFP_Pos) |
| #define | SYS_GPA_MFPH_PA9MFP_TM1_CNT (0x02UL<<SYS_GPA_MFPH_PA9MFP_Pos) |
| #define | SYS_GPA_MFPH_PA9MFP_SC0_DAT (0x03UL<<SYS_GPA_MFPH_PA9MFP_Pos) |
| #define | SYS_GPA_MFPH_PA9MFP_SPI2_CLK (0x04UL<<SYS_GPA_MFPH_PA9MFP_Pos) |
| #define | SYS_GPA_MFPH_PA9MFP_TM1_OUT (0x05UL<<SYS_GPA_MFPH_PA9MFP_Pos) |
| #define | SYS_GPA_MFPH_PA9MFP_UART1_nRTS (0x06UL<<SYS_GPA_MFPH_PA9MFP_Pos) |
| #define | SYS_GPA_MFPH_PA9MFP_SNOOPER (0x07UL<<SYS_GPA_MFPH_PA9MFP_Pos) |
| #define | SYS_GPA_MFPH_PA10MFP_GPIO (0x00UL<<SYS_GPA_MFPH_PA10MFP_Pos) |
| #define | SYS_GPA_MFPH_PA10MFP_I2C1_SDA (0x01UL<<SYS_GPA_MFPH_PA10MFP_Pos) |
| #define | SYS_GPA_MFPH_PA10MFP_TM2_CNT (0x02UL<<SYS_GPA_MFPH_PA10MFP_Pos) |
| #define | SYS_GPA_MFPH_PA10MFP_SC0_PWR (0x03UL<<SYS_GPA_MFPH_PA10MFP_Pos) |
| #define | SYS_GPA_MFPH_PA10MFP_SPI2_MISO0 (0x04UL<<SYS_GPA_MFPH_PA10MFP_Pos) |
| #define | SYS_GPA_MFPH_PA10MFP_TM2_OUT (0x05UL<<SYS_GPA_MFPH_PA10MFP_Pos) |
| #define | SYS_GPA_MFPH_PA11MFP_GPIO (0x00UL<<SYS_GPA_MFPH_PA11MFP_Pos) |
| #define | SYS_GPA_MFPH_PA11MFP_I2C1_SCL (0x01UL<<SYS_GPA_MFPH_PA11MFP_Pos) |
| #define | SYS_GPA_MFPH_PA11MFP_TM3_CNT (0x02UL<<SYS_GPA_MFPH_PA11MFP_Pos) |
| #define | SYS_GPA_MFPH_PA11MFP_SC0_RST (0x03UL<<SYS_GPA_MFPH_PA11MFP_Pos) |
| #define | SYS_GPA_MFPH_PA11MFP_SPI2_MOSI0 (0x04UL<<SYS_GPA_MFPH_PA11MFP_Pos) |
| #define | SYS_GPA_MFPH_PA11MFP_TM3_OUT (0x05UL<<SYS_GPA_MFPH_PA11MFP_Pos) |
| #define | SYS_GPA_MFPH_PA12MFP_GPIO (0x00UL<<SYS_GPA_MFPH_PA12MFP_Pos) |
| #define | SYS_GPA_MFPH_PA12MFP_PWM0_CH0 (0x01UL<<SYS_GPA_MFPH_PA12MFP_Pos) |
| #define | SYS_GPA_MFPH_PA12MFP_TM0_EXT (0x03UL<<SYS_GPA_MFPH_PA12MFP_Pos) |
| #define | SYS_GPA_MFPH_PA12MFP_I2C0_SDA (0x05UL<<SYS_GPA_MFPH_PA12MFP_Pos) |
| #define | SYS_GPA_MFPH_PA13MFP_GPIO (0x00UL<<SYS_GPA_MFPH_PA13MFP_Pos) |
| #define | SYS_GPA_MFPH_PA13MFP_PWM0_CH1 (0x01UL<<SYS_GPA_MFPH_PA13MFP_Pos) |
| #define | SYS_GPA_MFPH_PA13MFP_TM1_EXT (0x03UL<<SYS_GPA_MFPH_PA13MFP_Pos) |
| #define | SYS_GPA_MFPH_PA13MFP_I2C0_SCL (0x05UL<<SYS_GPA_MFPH_PA13MFP_Pos) |
| #define | SYS_GPA_MFPH_PA14MFP_GPIO (0x00UL<<SYS_GPA_MFPH_PA14MFP_Pos) |
| #define | SYS_GPA_MFPH_PA14MFP_PWM0_CH2 (0x01UL<<SYS_GPA_MFPH_PA14MFP_Pos) |
| #define | SYS_GPA_MFPH_PA14MFP_I2C1_SDA (0x02UL<<SYS_GPA_MFPH_PA14MFP_Pos) |
| #define | SYS_GPA_MFPH_PA14MFP_TM2_EXT (0x03UL<<SYS_GPA_MFPH_PA14MFP_Pos) |
| #define | SYS_GPA_MFPH_PA14MFP_TM2_CNT (0x05UL<<SYS_GPA_MFPH_PA14MFP_Pos) |
| #define | SYS_GPA_MFPH_PA14MFP_UART0_RXD (0x06UL<<SYS_GPA_MFPH_PA14MFP_Pos) |
| #define | SYS_GPA_MFPH_PA14MFP_TM2_OUT (0x07UL<<SYS_GPA_MFPH_PA14MFP_Pos) |
| #define | SYS_GPA_MFPH_PA15MFP_GPIO (0x00UL<<SYS_GPA_MFPH_PA15MFP_Pos) |
| #define | SYS_GPA_MFPH_PA15MFP_PWM0_CH3 (0x01UL<<SYS_GPA_MFPH_PA15MFP_Pos) |
| #define | SYS_GPA_MFPH_PA15MFP_I2C1_SCL (0x02UL<<SYS_GPA_MFPH_PA15MFP_Pos) |
| #define | SYS_GPA_MFPH_PA15MFP_TM3_EXT (0x03UL<<SYS_GPA_MFPH_PA15MFP_Pos) |
| #define | SYS_GPA_MFPH_PA15MFP_SC0_PWR (0x04UL<<SYS_GPA_MFPH_PA15MFP_Pos) |
| #define | SYS_GPA_MFPH_PA15MFP_TM3_CNT (0x05UL<<SYS_GPA_MFPH_PA15MFP_Pos) |
| #define | SYS_GPA_MFPH_PA15MFP_UART0_TXD (0x06UL<<SYS_GPA_MFPH_PA15MFP_Pos) |
| #define | SYS_GPA_MFPH_PA15MFP_TM3_OUT (0x07UL<<SYS_GPA_MFPH_PA15MFP_Pos) |
| #define | SYS_GPB_MFPL_PB0MFP_GPIO (0x00UL<<SYS_GPB_MFPL_PB0MFP_Pos) |
| #define | SYS_GPB_MFPL_PB0MFP_UART0_RXD (0x01UL<<SYS_GPB_MFPL_PB0MFP_Pos) |
| #define | SYS_GPB_MFPL_PB0MFP_SPI1_MOSI0 (0x03UL<<SYS_GPB_MFPL_PB0MFP_Pos) |
| #define | SYS_GPB_MFPL_PB1MFP_GPIO (0x00UL<<SYS_GPB_MFPL_PB1MFP_Pos) |
| #define | SYS_GPB_MFPL_PB1MFP_UART0_TXD (0x01UL<<SYS_GPB_MFPL_PB1MFP_Pos) |
| #define | SYS_GPB_MFPL_PB1MFP_SPI1_MISO0 (0x03UL<<SYS_GPB_MFPL_PB1MFP_Pos) |
| #define | SYS_GPB_MFPL_PB2MFP_GPIO (0x00UL<<SYS_GPB_MFPL_PB2MFP_Pos) |
| #define | SYS_GPB_MFPL_PB2MFP_UART0_nRTS (0x01UL<<SYS_GPB_MFPL_PB2MFP_Pos) |
| #define | SYS_GPB_MFPL_PB2MFP_SPI1_CLK (0x03UL<<SYS_GPB_MFPL_PB2MFP_Pos) |
| #define | SYS_GPB_MFPL_PB2MFP_CLKO (0x04UL<<SYS_GPB_MFPL_PB2MFP_Pos) |
| #define | SYS_GPB_MFPL_PB3MFP_GPIO (0x00UL<<SYS_GPB_MFPL_PB3MFP_Pos) |
| #define | SYS_GPB_MFPL_PB3MFP_UART0_nCTS (0x01UL<<SYS_GPB_MFPL_PB3MFP_Pos) |
| #define | SYS_GPB_MFPL_PB3MFP_SPI1_SS0 (0x03UL<<SYS_GPB_MFPL_PB3MFP_Pos) |
| #define | SYS_GPB_MFPL_PB3MFP_SC1_CD (0x04UL<<SYS_GPB_MFPL_PB3MFP_Pos) |
| #define | SYS_GPB_MFPL_PB4MFP_GPIO (0x00UL<<SYS_GPB_MFPL_PB4MFP_Pos) |
| #define | SYS_GPB_MFPL_PB4MFP_UART1_RXD (0x01UL<<SYS_GPB_MFPL_PB4MFP_Pos) |
| #define | SYS_GPB_MFPL_PB4MFP_SC0_CD (0x03UL<<SYS_GPB_MFPL_PB4MFP_Pos) |
| #define | SYS_GPB_MFPL_PB4MFP_SPI2_SS0 (0x04UL<<SYS_GPB_MFPL_PB4MFP_Pos) |
| #define | SYS_GPB_MFPL_PB4MFP_RTC_HZ (0x06UL<<SYS_GPB_MFPL_PB4MFP_Pos) |
| #define | SYS_GPB_MFPL_PB5MFP_GPIO (0x00UL<<SYS_GPB_MFPL_PB5MFP_Pos) |
| #define | SYS_GPB_MFPL_PB5MFP_UART1_TXD (0x01UL<<SYS_GPB_MFPL_PB5MFP_Pos) |
| #define | SYS_GPB_MFPL_PB5MFP_SC0_RST (0x03UL<<SYS_GPB_MFPL_PB5MFP_Pos) |
| #define | SYS_GPB_MFPL_PB5MFP_SPI2_CLK (0x04UL<<SYS_GPB_MFPL_PB5MFP_Pos) |
| #define | SYS_GPB_MFPL_PB6MFP_GPIO (0x00UL<<SYS_GPB_MFPL_PB6MFP_Pos) |
| #define | SYS_GPB_MFPL_PB6MFP_UART1_nRTS (0x01UL<<SYS_GPB_MFPL_PB6MFP_Pos) |
| #define | SYS_GPB_MFPL_PB6MFP_SPI2_MISO0 (0x04UL<<SYS_GPB_MFPL_PB6MFP_Pos) |
| #define | SYS_GPB_MFPL_PB7MFP_GPIO (0x00UL<<SYS_GPB_MFPL_PB7MFP_Pos) |
| #define | SYS_GPB_MFPL_PB7MFP_UART1_nCTS (0x01UL<<SYS_GPB_MFPL_PB7MFP_Pos) |
| #define | SYS_GPB_MFPL_PB7MFP_SPI2_MOSI0 (0x04UL<<SYS_GPB_MFPL_PB7MFP_Pos) |
| #define | SYS_GPB_MFPH_PB8MFP_GPIO (0x00UL<<SYS_GPB_MFPH_PB8MFP_Pos) |
| #define | SYS_GPB_MFPH_PB8MFP_STADC (0x01UL<<SYS_GPB_MFPH_PB8MFP_Pos) |
| #define | SYS_GPB_MFPH_PB8MFP_TM0_CNT (0x02UL<<SYS_GPB_MFPH_PB8MFP_Pos) |
| #define | SYS_GPB_MFPH_PB8MFP_INT0 (0x03UL<<SYS_GPB_MFPH_PB8MFP_Pos) |
| #define | SYS_GPB_MFPH_PB8MFP_TM0_OUT (0x04UL<<SYS_GPB_MFPH_PB8MFP_Pos) |
| #define | SYS_GPB_MFPH_PB8MFP_SNOOPER (0x07UL<<SYS_GPB_MFPH_PB8MFP_Pos) |
| #define | SYS_GPB_MFPH_PB9MFP_GPIO (0x00UL<<SYS_GPB_MFPH_PB9MFP_Pos) |
| #define | SYS_GPB_MFPH_PB9MFP_SPI1_SS1 (0x01UL<<SYS_GPB_MFPH_PB9MFP_Pos) |
| #define | SYS_GPB_MFPH_PB9MFP_TM1_CNT (0x02UL<<SYS_GPB_MFPH_PB9MFP_Pos) |
| #define | SYS_GPB_MFPH_PB9MFP_TM1_OUT (0x04UL<<SYS_GPB_MFPH_PB9MFP_Pos) |
| #define | SYS_GPB_MFPH_PB9MFP_INT0 (0x05UL<<SYS_GPB_MFPH_PB9MFP_Pos) |
| #define | SYS_GPB_MFPH_PB10MFP_GPIO (0x00UL<<SYS_GPB_MFPH_PB10MFP_Pos) |
| #define | SYS_GPB_MFPH_PB10MFP_SPI0_MOSI0 (0x01UL<<SYS_GPB_MFPH_PB10MFP_Pos) |
| #define | SYS_GPB_MFPH_PB10MFP_TM2_CNT (0x02UL<<SYS_GPB_MFPH_PB10MFP_Pos) |
| #define | SYS_GPB_MFPH_PB10MFP_TM2_OUT (0x04UL<<SYS_GPB_MFPH_PB10MFP_Pos) |
| #define | SYS_GPB_MFPH_PB10MFP_SPI0_SS1 (0x05UL<<SYS_GPB_MFPH_PB10MFP_Pos) |
| #define | SYS_GPB_MFPH_PB11MFP_GPIO (0x00UL<<SYS_GPB_MFPH_PB11MFP_Pos) |
| #define | SYS_GPB_MFPH_PB11MFP_PWM0_CH4 (0x01UL<<SYS_GPB_MFPH_PB11MFP_Pos) |
| #define | SYS_GPB_MFPH_PB11MFP_TM3_CNT (0x02UL<<SYS_GPB_MFPH_PB11MFP_Pos) |
| #define | SYS_GPB_MFPH_PB11MFP_TM3_OUT (0x04UL<<SYS_GPB_MFPH_PB11MFP_Pos) |
| #define | SYS_GPB_MFPH_PB11MFP_SPI0_MISO0 (0x05UL<<SYS_GPB_MFPH_PB11MFP_Pos) |
| #define | SYS_GPB_MFPH_PB13MFP_GPIO (0x00UL<<SYS_GPB_MFPH_PB13MFP_Pos) |
| #define | SYS_GPB_MFPH_PB13MFP_SPI2_MISO1 (0x03UL<<SYS_GPB_MFPH_PB13MFP_Pos) |
| #define | SYS_GPB_MFPH_PB13MFP_SNOOPER (0x07UL<<SYS_GPB_MFPH_PB13MFP_Pos) |
| #define | SYS_GPB_MFPH_PB14MFP_GPIO (0x00UL<<SYS_GPB_MFPH_PB14MFP_Pos) |
| #define | SYS_GPB_MFPH_PB14MFP_INT0 (0x01UL<<SYS_GPB_MFPH_PB14MFP_Pos) |
| #define | SYS_GPB_MFPH_PB14MFP_SPI2_MOSI1 (0x03UL<<SYS_GPB_MFPH_PB14MFP_Pos) |
| #define | SYS_GPB_MFPH_PB14MFP_SPI2_SS1 (0x04UL<<SYS_GPB_MFPH_PB14MFP_Pos) |
| #define | SYS_GPB_MFPH_PB15MFP_GPIO (0x00UL<<SYS_GPB_MFPH_PB15MFP_Pos) |
| #define | SYS_GPB_MFPH_PB15MFP_INT1 (0x01UL<<SYS_GPB_MFPH_PB15MFP_Pos) |
| #define | SYS_GPB_MFPH_PB15MFP_SNOOPER (0x03UL<<SYS_GPB_MFPH_PB15MFP_Pos) |
| #define | SYS_GPB_MFPH_PB15MFP_SC1_CD (0x04UL<<SYS_GPB_MFPH_PB15MFP_Pos) |
| #define | SYS_GPC_MFPL_PC0MFP_GPIO (0x00UL<<SYS_GPC_MFPL_PC0MFP_Pos) |
| #define | SYS_GPC_MFPL_PC0MFP_SPI0_SS0 (0x01UL<<SYS_GPC_MFPL_PC0MFP_Pos) |
| #define | SYS_GPC_MFPL_PC0MFP_SC1_CLK (0x04UL<<SYS_GPC_MFPL_PC0MFP_Pos) |
| #define | SYS_GPC_MFPL_PC0MFP_PWM0_BRAKE1 (0x05UL<<SYS_GPC_MFPL_PC0MFP_Pos) |
| #define | SYS_GPC_MFPL_PC1MFP_GPIO (0x00UL<<SYS_GPC_MFPL_PC1MFP_Pos) |
| #define | SYS_GPC_MFPL_PC1MFP_SPI0_CLK (0x01UL<<SYS_GPC_MFPL_PC1MFP_Pos) |
| #define | SYS_GPC_MFPL_PC1MFP_SC1_DAT (0x04UL<<SYS_GPC_MFPL_PC1MFP_Pos) |
| #define | SYS_GPC_MFPL_PC1MFP_PWM0_BRAKE0 (0x05UL<<SYS_GPC_MFPL_PC1MFP_Pos) |
| #define | SYS_GPC_MFPL_PC2MFP_GPIO (0x00UL<<SYS_GPC_MFPL_PC2MFP_Pos) |
| #define | SYS_GPC_MFPL_PC2MFP_SPI0_MISO0 (0x01UL<<SYS_GPC_MFPL_PC2MFP_Pos) |
| #define | SYS_GPC_MFPL_PC2MFP_SC1_PWR (0x04UL<<SYS_GPC_MFPL_PC2MFP_Pos) |
| #define | SYS_GPC_MFPL_PC2MFP_PWM0_BRAKE1 (0x05UL<<SYS_GPC_MFPL_PC2MFP_Pos) |
| #define | SYS_GPC_MFPL_PC3MFP_GPIO (0x00UL<<SYS_GPC_MFPL_PC3MFP_Pos) |
| #define | SYS_GPC_MFPL_PC3MFP_SPI0_MOSI0 (0x01UL<<SYS_GPC_MFPL_PC3MFP_Pos) |
| #define | SYS_GPC_MFPL_PC3MFP_SC1_RST (0x04UL<<SYS_GPC_MFPL_PC3MFP_Pos) |
| #define | SYS_GPC_MFPL_PC3MFP_PWM0_BRAKE0 (0x05UL<<SYS_GPC_MFPL_PC3MFP_Pos) |
| #define | SYS_GPC_MFPL_PC6MFP_GPIO (0x00UL<<SYS_GPC_MFPL_PC6MFP_Pos) |
| #define | SYS_GPC_MFPL_PC6MFP_UART1_RXD (0x01UL<<SYS_GPC_MFPL_PC6MFP_Pos) |
| #define | SYS_GPC_MFPL_PC6MFP_TM0_EXT (0x03UL<<SYS_GPC_MFPL_PC6MFP_Pos) |
| #define | SYS_GPC_MFPL_PC6MFP_SC1_CD (0x04UL<<SYS_GPC_MFPL_PC6MFP_Pos) |
| #define | SYS_GPC_MFPL_PC6MFP_PWM0_CH0 (0x05UL<<SYS_GPC_MFPL_PC6MFP_Pos) |
| #define | SYS_GPC_MFPL_PC7MFP_GPIO (0x00UL<<SYS_GPC_MFPL_PC7MFP_Pos) |
| #define | SYS_GPC_MFPL_PC7MFP_UART1_TXD (0x01UL<<SYS_GPC_MFPL_PC7MFP_Pos) |
| #define | SYS_GPC_MFPL_PC7MFP_ADC_CH7 (0x02UL<<SYS_GPC_MFPL_PC7MFP_Pos) |
| #define | SYS_GPC_MFPL_PC7MFP_TM1_EXT (0x03UL<<SYS_GPC_MFPL_PC7MFP_Pos) |
| #define | SYS_GPC_MFPL_PC7MFP_PWM0_CH1 (0x05UL<<SYS_GPC_MFPL_PC7MFP_Pos) |
| #define | SYS_GPC_MFPH_PC8MFP_GPIO (0x00UL<<SYS_GPC_MFPH_PC8MFP_Pos) |
| #define | SYS_GPC_MFPH_PC8MFP_SPI1_SS0 (0x01UL<<SYS_GPC_MFPH_PC8MFP_Pos) |
| #define | SYS_GPC_MFPH_PC8MFP_I2C1_SDA (0x05UL<<SYS_GPC_MFPH_PC8MFP_Pos) |
| #define | SYS_GPC_MFPH_PC9MFP_GPIO (0x00UL<<SYS_GPC_MFPH_PC9MFP_Pos) |
| #define | SYS_GPC_MFPH_PC9MFP_SPI1_CLK (0x01UL<<SYS_GPC_MFPH_PC9MFP_Pos) |
| #define | SYS_GPC_MFPH_PC9MFP_I2C1_SCL (0x05UL<<SYS_GPC_MFPH_PC9MFP_Pos) |
| #define | SYS_GPC_MFPH_PC10MFP_GPIO (0x00UL<<SYS_GPC_MFPH_PC10MFP_Pos) |
| #define | SYS_GPC_MFPH_PC10MFP_SPI1_MISO0 (0x01UL<<SYS_GPC_MFPH_PC10MFP_Pos) |
| #define | SYS_GPC_MFPH_PC10MFP_UART1_RXD (0x05UL<<SYS_GPC_MFPH_PC10MFP_Pos) |
| #define | SYS_GPC_MFPH_PC11MFP_GPIO (0x00UL<<SYS_GPC_MFPH_PC11MFP_Pos) |
| #define | SYS_GPC_MFPH_PC11MFP_SPI1_MOSI0 (0x01UL<<SYS_GPC_MFPH_PC11MFP_Pos) |
| #define | SYS_GPC_MFPH_PC11MFP_UART1_TXD (0x05UL<<SYS_GPC_MFPH_PC11MFP_Pos) |
| #define | SYS_GPC_MFPH_PC14MFP_GPIO (0x00UL<<SYS_GPC_MFPH_PC14MFP_Pos) |
| #define | SYS_GPC_MFPH_PC14MFP_UART1_nCTS (0x01UL<<SYS_GPC_MFPH_PC14MFP_Pos) |
| #define | SYS_GPC_MFPH_PC15MFP_GPIO (0x00UL<<SYS_GPC_MFPH_PC15MFP_Pos) |
| #define | SYS_GPC_MFPH_PC15MFP_UART1_nRTS (0x01UL<<SYS_GPC_MFPH_PC15MFP_Pos) |
| #define | SYS_GPC_MFPH_PC15MFP_TM0_EXT (0x03UL<<SYS_GPC_MFPH_PC15MFP_Pos) |
| #define | SYS_GPD_MFPL_PD6MFP_GPIO (0x00UL<<SYS_GPD_MFPL_PD6MFP_Pos) |
| #define | SYS_GPD_MFPL_PD6MFP_SPI1_MOSI1 (0x03UL<<SYS_GPD_MFPL_PD6MFP_Pos) |
| #define | SYS_GPD_MFPL_PD6MFP_SC1_RST (0x04UL<<SYS_GPD_MFPL_PD6MFP_Pos) |
| #define | SYS_GPD_MFPL_PD7MFP_GPIO (0x00UL<<SYS_GPD_MFPL_PD7MFP_Pos) |
| #define | SYS_GPD_MFPL_PD7MFP_SPI1_MISO1 (0x03UL<<SYS_GPD_MFPL_PD7MFP_Pos) |
| #define | SYS_GPD_MFPL_PD7MFP_SC1_PWR (0x04UL<<SYS_GPD_MFPL_PD7MFP_Pos) |
| #define | SYS_GPD_MFPH_PD14MFP_GPIO (0x00UL<<SYS_GPD_MFPH_PD14MFP_Pos) |
| #define | SYS_GPD_MFPH_PD14MFP_SPI0_MOSI1 (0x01UL<<SYS_GPD_MFPH_PD14MFP_Pos) |
| #define | SYS_GPD_MFPH_PD14MFP_SC1_DAT (0x04UL<<SYS_GPD_MFPH_PD14MFP_Pos) |
| #define | SYS_GPD_MFPH_PD15MFP_GPIO (0x00UL<<SYS_GPD_MFPH_PD15MFP_Pos) |
| #define | SYS_GPD_MFPH_PD15MFP_SPI0_MISO1 (0x01UL<<SYS_GPD_MFPH_PD15MFP_Pos) |
| #define | SYS_GPD_MFPH_PD15MFP_SC1_CLK (0x04UL<<SYS_GPD_MFPH_PD15MFP_Pos) |
| #define | SYS_GPE_MFPL_PE5MFP_GPIO (0x00UL<<SYS_GPE_MFPL_PE5MFP_Pos) |
| #define | SYS_GPE_MFPL_PE5MFP_PWM0_CH5 (0x01UL<<SYS_GPE_MFPL_PE5MFP_Pos) |
| #define | SYS_GPE_MFPL_PE5MFP_RTC_HZ (0x06UL<<SYS_GPE_MFPL_PE5MFP_Pos) |
| #define | SYS_GPF_MFPL_PF0MFP_GPIO (0x00UL<<SYS_GPF_MFPL_PF0MFP_Pos) |
| #define | SYS_GPF_MFPL_PF0MFP_INT0 (0x05UL<<SYS_GPF_MFPL_PF0MFP_Pos) |
| #define | SYS_GPF_MFPL_PF0MFP_ICE_DAT (0x07UL<<SYS_GPF_MFPL_PF0MFP_Pos) |
| #define | SYS_GPF_MFPL_PF1MFP_GPIO (0x00UL<<SYS_GPF_MFPL_PF1MFP_Pos) |
| #define | SYS_GPF_MFPL_PF1MFP_CLKO (0x04UL<<SYS_GPF_MFPL_PF1MFP_Pos) |
| #define | SYS_GPF_MFPL_PF1MFP_INT1 (0x05UL<<SYS_GPF_MFPL_PF1MFP_Pos) |
| #define | SYS_GPF_MFPL_PF1MFP_ICE_CLK (0x07UL<<SYS_GPF_MFPL_PF1MFP_Pos) |
| #define | SYS_GPF_MFPL_PF2MFP_GPIO (0x00UL<<SYS_GPF_MFPL_PF2MFP_Pos) |
| #define | SYS_GPF_MFPL_PF2MFP_XT1_OUT (0x07UL<<SYS_GPF_MFPL_PF2MFP_Pos) |
| #define | SYS_GPF_MFPL_PF3MFP_GPIO (0x00UL<<SYS_GPF_MFPL_PF3MFP_Pos) |
| #define | SYS_GPF_MFPL_PF3MFP_XT1_IN (0x07UL<<SYS_GPF_MFPL_PF3MFP_Pos) |
| #define | SYS_GPF_MFPL_PF6MFP_GPIO (0x00UL<<SYS_GPF_MFPL_PF6MFP_Pos) |
| #define | SYS_GPF_MFPL_PF6MFP_I2C1_SDA (0x01UL<<SYS_GPF_MFPL_PF6MFP_Pos) |
| #define | SYS_GPF_MFPL_PF6MFP_X32_OUT (0x07UL<<SYS_GPF_MFPL_PF6MFP_Pos) |
| #define | SYS_GPF_MFPL_PF7MFP_GPIO (0x00UL<<SYS_GPF_MFPL_PF7MFP_Pos) |
| #define | SYS_GPF_MFPL_PF7MFP_I2C1_SCL (0x01UL<<SYS_GPF_MFPL_PF7MFP_Pos) |
| #define | SYS_GPF_MFPL_PF7MFP_SC0_CD (0x03UL<<SYS_GPF_MFPL_PF7MFP_Pos) |
| #define | SYS_GPF_MFPL_PF7MFP_X32_IN (0x07UL<<SYS_GPF_MFPL_PF7MFP_Pos) |
| #define | SYS_CLEAR_BOD_INT_FLAG() (SYS->BODCTL |= SYS_BODCTL_BODIF_Msk) |
| Clear Brown-out detector interrupt flag. More... | |
| #define | SYS_GET_BOD_INT_FLAG() (SYS->BODCTL & SYS_BODCTL_BODIF_Msk) |
| Get Brown-out detector interrupt flag. More... | |
| #define | SYS_ENABLE_BOD() (SYS->BODCTL |= SYS_BODCTL_BODEN_Msk) |
| Enable Brown-out detector function. More... | |
| #define | SYS_DISABLE_BOD() (SYS->BODCTL &= ~SYS_BODCTL_BODEN_Msk) |
| Disable Brown-out detector function. More... | |
| #define | SYS_ENABLE_LPBOD() (SYS->BODCTL |= SYS_BODCTL_LPBODEN_Msk) |
| Enable Low Power Brown-out detector function. More... | |
| #define | SYS_DISABLE_LPBOD() (SYS->BODCTL &= ~SYS_BODCTL_LPBODEN_Msk) |
| Disable Low Power Brown-out detector function. More... | |
| #define | SYS_GET_BOD_OUTPUT() (SYS->BODCTL & SYS_BODCTL_BODOUT_Msk) |
| Get Brown-out detector status. More... | |
| #define | SYS_DISABLE_BOD_RST() (SYS->BODCTL &= ~SYS_BODCTL_BODREN_Msk) |
| Disable Brown-out detector reset function. More... | |
| #define | SYS_ENABLE_BOD_RST() (SYS->BODCTL |= SYS_BODCTL_BODREN_Msk) |
| Enable Brown-out detector reset function. More... | |
| #define | SYS_DISABLE_LPBOD_RST() (SYS->BODCTL &= ~SYS_BODCTL_LPBODREN_Msk) |
| Disable Low Power Brown-out detector reset function. More... | |
| #define | SYS_ENABLE_LPBOD_RST() (SYS->BODCTL |= SYS_BODCTL_LPBODREN_Msk) |
| Enable Low Power Brown-out detector reset function. More... | |
| #define | SYS_SET_BOD_LEVEL(u32Level) (SYS->BODCTL = (SYS->BODCTL & ~SYS_BODCTL_BODVL_Msk) | (u32Level)) |
| Set Brown-out detector voltage level. More... | |
| #define | SYS_IS_BOD_RST() (SYS->RSTSTS & SYS_RSTSTS_BODRF_Msk) |
| Get reset source is from Brown-out detector reset. More... | |
| #define | SYS_IS_LVR_RST() (SYS->RSTSTS & SYS_RSTSTS_LVRF_Msk) |
| Get reset source is from Low-voltage reset. More... | |
| #define | SYS_IS_CPU_RST() (SYS->RSTSTS & SYS_RSTSTS_CPURF_Msk) |
| Get reset source is from CPU reset. More... | |
| #define | SYS_IS_LOCKUP_RST() (SYS->RSTSTS & SYS_RSTSTS_LOCKRF_Msk) |
| Get reset source is from Cortex-M0 lockup event. More... | |
| #define | SYS_IS_POR_RST() (SYS->RSTSTS & SYS_RSTSTS_PORF_Msk) |
| Get reset source is from Power-on Reset. More... | |
| #define | SYS_IS_RSTPIN_RST() (SYS->RSTSTS & SYS_RSTSTS_PINRF_Msk) |
| Get reset source is from reset pin reset. More... | |
| #define | SYS_IS_SYSTEM_RST() (SYS->RSTSTS & SYS_RSTSTS_SYSRF_Msk) |
| Get reset source is from system reset. More... | |
| #define | SYS_IS_WDT_RST() (SYS->RSTSTS & SYS_RSTSTS_WDTRF_Msk) |
| Get reset source is from window watch dog reset. More... | |
| #define | SYS_DISABLE_LVR() (SYS->BODCTL &= ~SYS_BODCTL_LVREN_Msk) |
| Disable Low-Voltage-Reset function. More... | |
| #define | SYS_ENABLE_LVR() (SYS->BODCTL |= SYS_BODCTL_LVREN_Msk) |
| Enable Low-Voltage-Reset function. More... | |
| #define | SYS_DISABLE_POR() do{SYS->PORCTL = 0x5AA5;SYS->MISCCTL = SYS_MISCCTL_POR33DIS_Msk | SYS_MISCCTL_POR18DIS_Msk;}while(0) |
| Disable Power-on Reset function. More... | |
| #define | SYS_ENABLE_POR() do{SYS->PORCTL = 0;SYS->MISCCTL = 0;}while(0) |
| Enable Power-on Reset function. More... | |
| #define | SYS_CLEAR_RST_SOURCE(u32RstSrc) (SYS->RSTSTS |= u32RstSrc) |
| Clear reset source flag. More... | |
| #define | SYS_GET_IRC0TRIM_INT_FLAG() (SYS->IRC0TISTS) |
| Get HIRC0 trim status. More... | |
| #define | SYS_CLEAR_IRC0TRIM_INT_FLAG(u32IRCTrimFlg) (SYS->IRC0TISTS = u32IRCTrimFlg) |
| Clear HIRC0 trim flag. More... | |
| #define | SYS_GET_IRC1TRIM_INT_FLAG() (SYS->IRC1TISTS) |
| Get HIRC1 trim status. More... | |
| #define | SYS_CLEAR_IRC1TRIM_INT_FLAG(u32IRCTrimFlg) (SYS->IRC1TISTS = u32IRCTrimFlg) |
| Clear HIRC1 trim flag. More... | |
| #define | SYS_GET_MIRCTRIM_INT_FLAG() (SYS->MIRCTISTS) |
| Get MIRC trim status. More... | |
| #define | SYS_CLEAR_MIRCTRIM_INT_FLAG(u32IRCTrimFlg) (SYS->MIRCTISTS = u32IRCTrimFlg) |
| Clear MIRC trim flag. More... | |
Functions | |
| __STATIC_INLINE void | SYS_UnlockReg (void) |
| Disable register write-protection function. More... | |
| __STATIC_INLINE void | SYS_LockReg (void) |
| Enable register write-protection function. More... | |
| void | SYS_ClearResetSrc (uint32_t u32Src) |
| Clear reset source. More... | |
| uint32_t | SYS_GetBODStatus (void) |
| Get Brown-out detector output status. More... | |
| uint32_t | SYS_GetResetSrc (void) |
| This function get the system reset source register value. More... | |
| uint32_t | SYS_IsRegLocked (void) |
| This function check register write-protection bit setting. More... | |
| uint32_t | SYS_ReadPDID (void) |
| This function get product ID. More... | |
| void | SYS_ResetChip (void) |
| This function reset chip. More... | |
| void | SYS_ResetCPU (void) |
| This function reset CPU. More... | |
| void | SYS_ResetModule (uint32_t u32ModuleIndex) |
| This function reset selected modules. More... | |
| void | SYS_EnableBOD (int32_t i32Mode, uint32_t u32BODLevel) |
| This function configure Normal BOD function. Configure BOD reset or interrupt mode and set Brown-out voltage level. Enable Brown-out function. More... | |
| void | SYS_DisableBOD (void) |
| This function disable Normal BOD function. More... | |
| void | SYS_EnableLPBOD (int32_t i32Mode, uint32_t u32BODLevel) |
| This function configure Low Power BOD function only valid in Power Down mode. Configure Low Power BOD reset or interrupt mode and set Low Power Brown-out voltage level. Enable Low Power Brown-out function. More... | |
| void | SYS_DisableLPBOD (void) |
| This function disable Low Power BOD function. More... | |
| void | SYS_EnableHIRC0Trim (uint32_t u32TrimSel, uint32_t u32TrimEnInt) |
| This function enable HIRC0 trim function. More... | |
| void | SYS_DisableHIRC0Trim (void) |
| This function disable HIRC0 trim function. More... | |
| void | SYS_EnableHIRC1Trim (uint32_t u32TrimSel, uint32_t u32TrimEnInt) |
| This function enable HIRC1 trim function. More... | |
| void | SYS_DisableHIRC1Trim (void) |
| This function disable HIRC1 trim function. More... | |
| void | SYS_EnableMIRCTrim (uint32_t u32TrimSel, uint32_t u32TrimEnInt) |
| This function enable MIRC trim function. More... | |
| void | SYS_DisableMIRCTrim (void) |
| This function disable HIRC0 trim function. More... | |
NANO103 Series system control header file.
Definition in file sys.h.
1.8.15