| Nano103 BSP V3.01.002 The Board Support Package for Nano103 Series

Data Fields
WDT_T Struct Reference

`#include <Nano103.h>`

## Data Fields
__IO uint32_t | CTL
__IO uint32_t | INTEN
__IO uint32_t | STATUS

## Detailed Description

    @addtogroup WDT Watch Dog Timer Controller(WDT)
    Memory Mapped Structure for WDT Controller

Definition at line 17454 of file Nano103.h.

## Field Documentation

## ◆ CTL

WDT_T::CTL

[0x0000] Watchdog Timer Control Register

CTL

Offset: 0x00 Watchdog Timer Control Register

Bits | Field | Descriptions
[0] | WTR | Clear Watchdog Timer (Write Protect) Please refer to open lock sequence to program it. Setting this bit will clear the Watchdog timer. 0 = No effect. 1 = Reset the contents of the Watchdog timer. Note: This bit will be auto cleared after 1 PCLK clock cycle.
[1] | WTRE | Watchdog Timer Reset Function Enable Bit (Write Protect) Please refer to open lock sequence to program it. Setting this bit will enable the Watchdog timer reset function. 0 = Watchdog timer reset function Disabled. 1 = Watchdog timer reset function Enabled.
[2] | WTWKE | Watchdog Timer Wake-up Function Enable Bit (Write Protect) Please refer to open lock sequence to program it. 0 = Watchdog timer Wake-up CPU function Disabled. 1 = Wake-up function Enabled so that Watchdog timer time-out can wake up CPU from Power-down mode.
[3] | WTE | Watchdog Timer Enable Bit (Write Protect) Please refer to open lock sequence to program it. 0 = Watchdog timer Disabled (this action will reset the internal counter). 1 = Watchdog timer Enabled.
[6:4] | WTIS | Watchdog Timer Interval Selection (Write Protect) Please refer to open lock sequence to program it. The three bits select the time-out interval for the Watchdog timer. This count is free running counter. Please refer to Table 6.11-1.
[9:8] | WTRDSEL | Watchdog Timer Reset Delay Selection When watchdog timeout happened, software has a time named watchdog reset delay period to clear watchdog timer to prevent watchdog reset happened Software can select a suitable value of watchdog reset delay period for different watchdog timeout period. 00 = Watchdog reset delay period is 1026 watchdog clock. 01 = Watchdog reset delay period is 130 watchdog clock. 10 = Watchdog reset delay period is 18 watchdog clock. 11 = Watchdog reset delay period is 3 watchdog clock. Note: This bit will be reset if watchdog reset happened
[31] | DBGEN | WDT Debug Mode Enable Control (Write Protect) 0 = WDT stopped counting if system is in Debug mode. 1 = WDT still counted even system is in Debug mode.

Definition at line 17627 of file Nano103.h.

## ◆ INTEN

WDT_T::INTEN

[0x0004] Watchdog Timer Interrupt Enable Register

INTEN

Offset: 0x04 Watchdog Timer Interrupt Enable Register

Bits | Field | Descriptions
[0] | WDT_IE | Watchdog Timer Time-out Interrupt Enable Bit 0 = Watchdog timer time-out interrupt Disabled. 1 = Watchdog timer time-out interrupt Enabled.

Definition at line 17628 of file Nano103.h.

## ◆ STATUS

WDT_T::STATUS

[0x0008] Watchdog Timer Interrupt Status Register

STATUS

Offset: 0x08 Watchdog Timer Status Register

Bits | Field | Descriptions
[0] | WDT_IS | Watchdog Timer Time-out Interrupt Status If the Watchdog timer time-out interrupt is enabled, then the hardware will set this bit to indicate that the Watchdog timer time-out interrupt has occurred If the Watchdog timer time-out interrupt is not enabled, then this bit indicates that a time-out period has elapsed. 0 = Watchdog timer time-out interrupt did not occur. 1 = Watchdog timer time-out interrupt occurred. Note: This bit is read only, but can be cleared by writing 1 to it.
[1] | WDT_RST_IS | Watchdog Timer Reset Status When the Watchdog timer initiates a reset, the hardware will set this bit This flag can be read by software to determine the source of reset Software is responsible to clear it manually by writing 1 to it If WTRE is disabled, then the Watchdog timer has no effect on this bit. 0 = Watchdog timer reset did not occur. 1 = Watchdog timer reset occurred. Note: This bit is read only, but can be cleared by writing 1 to it.
[2] | WDT_WAKE_IS | Watchdog Timer Wake-up Status If Watchdog timer causes system to wake up from Power-down mode, this bit will be set to 1 It must be cleared by software with a write 1 to this bit. 0 = Watchdog timer does not cause system wake-up. 1 = Wake system up from Power-down mode by Watchdog time-out. Note1: When system in Power-down mode and watchdog time-out, hardware will set WDT_WAKE_IS and WDT_IS. Note2: After one engine clock, this bit can be cleared by writing 1 to it

Definition at line 17629 of file Nano103.h.

The documentation for this struct was generated from the following file:

- C:/Users/yachen/workzone/bsp/nano103bsp/Library/Device/Nuvoton/Nano103/Include/Nano103.h