| Nano103 BSP V3.01.002 The Board Support Package for Nano103 Series

Macros
CLK Exported Constants
NANO103 Device Driver » CLK Driver

## Macros
#define | FREQ_36MHZ 36000000
#define | FREQ_16MHZ 16000000
#define | CLK_PWRCTL_HXT_EN ((uint32_t)0x00000001)
#define | CLK_PWRCTL_LXT_EN ((uint32_t)0x00000002)
#define | CLK_PWRCTL_HIRC0_EN ((uint32_t)0x00000004)
#define | CLK_PWRCTL_LIRC_EN ((uint32_t)0x00000008)
#define | CLK_PWRCTL_DELY_EN ((uint32_t)0x00000010)
#define | CLK_PWRCTL_WAKEINT_EN ((uint32_t)0x00000020)
#define | CLK_PWRCTL_PWRDOWN_EN ((uint32_t)0x00000040)
#define | CLK_PWRCTL_HXT_HXTSLTYP ((uint32_t)0x00000100)
#define | CLK_PWRCTL_HIRC1_EN ((uint32_t)0x01000000)
#define | CLK_PWRCTL_MIRC_EN ((uint32_t)0x02000000)
#define | CLK_PWRCTL_HXT_SELXT ((uint32_t)0x00000100)
#define | CLK_PWRCTL_HXT_GAIN_4M ((uint32_t)0x00000000)
#define | CLK_PWRCTL_HXT_GAIN_4M_8M ((uint32_t)0x00000400)
#define | CLK_PWRCTL_HXT_GAIN_8M_12M ((uint32_t)0x00000800)
#define | CLK_PWRCTL_HXT_GAIN_12M_16M ((uint32_t)0x00000C00)
#define | CLK_PWRCTL_HXT_GAIN_16M_24M ((uint32_t)0x00001000)
#define | CLK_PWRCTL_HXT_GAIN_24M_32M ((uint32_t)0x00001400)
#define | CLK_PWRCTL_HXT_GAIN_32M_36M ((uint32_t)0x00001800)
#define | CLK_PWRCTL_HXT_GAIN_36M ((uint32_t)0x00001C00)
#define | CLK_AHBCLK_GPIO_EN ((uint32_t)0x00000001)
#define | CLK_AHBCLK_DMA_EN ((uint32_t)0x00000002)
#define | CLK_AHBCLK_ISP_EN ((uint32_t)0x00000004)
#define | CLK_AHBCLK_SRAM_EN ((uint32_t)0x00000010)
#define | CLK_AHBCLK_TICK_EN ((uint32_t)0x00000020)
#define | CLK_APBCLK_WDT_EN ((uint32_t)0x00000001)
#define | CLK_APBCLK_RTC_EN ((uint32_t)0x00000002)
#define | CLK_APBCLK_TMR0_EN ((uint32_t)0x00000004)
#define | CLK_APBCLK_TMR1_EN ((uint32_t)0x00000008)
#define | CLK_APBCLK_TMR2_EN ((uint32_t)0x00000010)
#define | CLK_APBCLK_TMR3_EN ((uint32_t)0x00000020)
#define | CLK_APBCLK_CLKOC_EN ((uint32_t)0x00000040)
#define | CLK_APBCLK_I2C0_EN ((uint32_t)0x00000100)
#define | CLK_APBCLK_I2C1_EN ((uint32_t)0x00000200)
#define | CLK_APBCLK_ACMP0_EN ((uint32_t)0x00000800)
#define | CLK_APBCLK_SPI0_EN ((uint32_t)0x00001000)
#define | CLK_APBCLK_SPI1_EN ((uint32_t)0x00002000)
#define | CLK_APBCLK_SPI2_EN ((uint32_t)0x00004000)
#define | CLK_APBCLK_SPI3_EN ((uint32_t)0x00008000)
#define | CLK_APBCLK_UART0_EN ((uint32_t)0x00010000)
#define | CLK_APBCLK_UART1_EN ((uint32_t)0x00020000)
#define | CLK_APBCLK_PWM0_EN ((uint32_t)0x00100000)
#define | CLK_APBCLK_ADC_EN ((uint32_t)0x10000000)
#define | CLK_APBCLK_SC0_EN ((uint32_t)0x40000000)
#define | CLK_APBCLK_SC1_EN ((uint32_t)0x80000000)
#define | CLK_CLKSTATUS_HXT_STB ((uint32_t)0x00000001)
#define | CLK_CLKSTATUS_LXT_STB ((uint32_t)0x00000002)
#define | CLK_CLKSTATUS_PLL_STB ((uint32_t)0x00000004)
#define | CLK_CLKSTATUS_LIRC_STB ((uint32_t)0x00000008)
#define | CLK_CLKSTATUS_HIRC0_STB ((uint32_t)0x00000010)
#define | CLK_CLKSTATUS_HIRC1_STB ((uint32_t)0x00000020)
#define | CLK_CLKSTATUS_MIRC_STB ((uint32_t)0x00000040)
#define | CLK_CLKSTATUS_CLK_SW_FAIL ((uint32_t)0x00000080)
#define | CLK_PLLCTL_PD ((uint32_t)0x00010000)
#define | CLK_PLLCTL_PLL_SRC_HXT ((uint32_t)(0x00000000))
#define | CLK_PLLCTL_PLL_SRC_HIRC ((uint32_t)(0x00020000))
#define | CLK_PLLCTL_PLL_SRC_MIRC ((uint32_t)(0x00040000))
#define | CLK_PLL_SRC_N(x) (((x)-1)<<8)
#define | CLK_PLL_MLP(x) ((x)<<0)
#define | CLK_PLLCTL_36MHz_HIRC0 (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLL_SRC_N(12) | CLK_PLL_MLP(36))
#define | CLK_PLLCTL_32MHz_HIRC0 (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLL_SRC_N(12) | CLK_PLL_MLP(32))
#define | CLK_PLLCTL_28MHz_HIRC0 (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLL_SRC_N(12) | CLK_PLL_MLP(28))
#define | CLK_PLLCTL_24MHz_HIRC0 (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLL_SRC_N(12) | CLK_PLL_MLP(24))
#define | CLK_PLLCTL_22MHz_HIRC0 (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLL_SRC_N(12) | CLK_PLL_MLP(22))
#define | CLK_PLLCTL_16MHz_HIRC0 (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLL_SRC_N(12) | CLK_PLL_MLP(16))
#define | CLK_PLLCTL_36MHz_HIRC1 (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLL_SRC_N(36) | CLK_PLL_MLP(36))
#define | CLK_PLLCTL_32MHz_HIRC1 (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLL_SRC_N(36) | CLK_PLL_MLP(32))
#define | CLK_PLLCTL_28MHz_HIRC1 (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLL_SRC_N(36) | CLK_PLL_MLP(28))
#define | CLK_PLLCTL_24MHz_HIRC1 (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLL_SRC_N(36) | CLK_PLL_MLP(24))
#define | CLK_PLLCTL_22MHz_HIRC1 (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLL_SRC_N(36) | CLK_PLL_MLP(22))
#define | CLK_PLLCTL_16MHz_HIRC1 (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLL_SRC_N(36) | CLK_PLL_MLP(16))
#define | CLK_PLLCTL_36MHz_MIRC (CLK_PLLCTL_PLL_SRC_MIRC | CLK_PLL_SRC_N(4) | CLK_PLL_MLP(36))
#define | CLK_PLLCTL_32MHz_MIRC (CLK_PLLCTL_PLL_SRC_MIRC | CLK_PLL_SRC_N(4) | CLK_PLL_MLP(32))
#define | CLK_PLLCTL_28MHz_MIRC (CLK_PLLCTL_PLL_SRC_MIRC | CLK_PLL_SRC_N(4) | CLK_PLL_MLP(28))
#define | CLK_PLLCTL_24MHz_MIRC (CLK_PLLCTL_PLL_SRC_MIRC | CLK_PLL_SRC_N(4) | CLK_PLL_MLP(24))
#define | CLK_PLLCTL_22MHz_MIRC (CLK_PLLCTL_PLL_SRC_MIRC | CLK_PLL_SRC_N(4) | CLK_PLL_MLP(22))
#define | CLK_PLLCTL_16MHz_MIRC (CLK_PLLCTL_PLL_SRC_MIRC | CLK_PLL_SRC_N(4) | CLK_PLL_MLP(16))
#define | CLK_CLKSEL0_HCLKSEL_HXT (0x0UL<<CLK_CLKSEL0_HCLKSEL_Pos)
#define | CLK_CLKSEL0_HCLKSEL_LXT (0x1UL<<CLK_CLKSEL0_HCLKSEL_Pos)
#define | CLK_CLKSEL0_HCLKSEL_PLL (0x2UL<<CLK_CLKSEL0_HCLKSEL_Pos)
#define | CLK_CLKSEL0_HCLKSEL_LIRC (0x3UL<<CLK_CLKSEL0_HCLKSEL_Pos)
#define | CLK_CLKSEL0_HCLKSEL_HIRC (0x4UL<<CLK_CLKSEL0_HCLKSEL_Pos)
#define | CLK_CLKSEL0_HCLKSEL_HIRC0 (0x4UL<<CLK_CLKSEL0_HCLKSEL_Pos)
#define | CLK_CLKSEL0_HCLKSEL_HIRC1 (0xCUL<<CLK_CLKSEL0_HCLKSEL_Pos)
#define | CLK_CLKSEL0_HCLKSEL_MIRC (0x5UL<<CLK_CLKSEL0_HCLKSEL_Pos)
#define | CLK_CLKSEL0_ISPSEL_HIRC (0x0UL<<CLK_CLKSEL0_ISPSEL_Pos)
#define | CLK_CLKSEL0_ISPSEL_MIRC (0x1UL<<CLK_CLKSEL0_ISPSEL_Pos)
#define | CLK_CLKSEL1_UART0SEL_HXT (0x0UL<<CLK_CLKSEL1_UART0SEL_Pos)
#define | CLK_CLKSEL1_UART0SEL_LXT (0x1UL<<CLK_CLKSEL1_UART0SEL_Pos)
#define | CLK_CLKSEL1_UART0SEL_PLL (0x2UL<<CLK_CLKSEL1_UART0SEL_Pos)
#define | CLK_CLKSEL1_UART0SEL_HIRC (0x3UL<<CLK_CLKSEL1_UART0SEL_Pos)
#define | CLK_CLKSEL1_UART0SEL_MIRC (0x4UL<<CLK_CLKSEL1_UART0SEL_Pos)
#define | CLK_CLKSEL1_PWM0SEL_PLL (0x0UL<<CLK_CLKSEL1_PWM0SEL_Pos)
#define | CLK_CLKSEL1_PWM0SEL_PCLK0 (0x1UL<<CLK_CLKSEL1_PWM0SEL_Pos)
#define | CLK_CLKSEL1_TMR0SEL_HXT (0x0UL<<CLK_CLKSEL1_TMR0SEL_Pos)
#define | CLK_CLKSEL1_TMR0SEL_LXT (0x1UL<<CLK_CLKSEL1_TMR0SEL_Pos)
#define | CLK_CLKSEL1_TMR0SEL_LIRC (0x2UL<<CLK_CLKSEL1_TMR0SEL_Pos)
#define | CLK_CLKSEL1_TMR0SEL_HIRC (0x4UL<<CLK_CLKSEL1_TMR0SEL_Pos)
#define | CLK_CLKSEL1_TMR0SEL_MIRC (0x5UL<<CLK_CLKSEL1_TMR0SEL_Pos)
#define | CLK_CLKSEL1_TMR0SEL_EXT (0x3UL<<CLK_CLKSEL1_TMR0SEL_Pos)
#define | CLK_CLKSEL1_TMR0SEL_HCLK (0x6UL<<CLK_CLKSEL1_TMR0SEL_Pos)
#define | CLK_CLKSEL1_TMR1SEL_HXT (0x0UL<<CLK_CLKSEL1_TMR1SEL_Pos)
#define | CLK_CLKSEL1_TMR1SEL_LXT (0x1UL<<CLK_CLKSEL1_TMR1SEL_Pos)
#define | CLK_CLKSEL1_TMR1SEL_LIRC (0x2UL<<CLK_CLKSEL1_TMR1SEL_Pos)
#define | CLK_CLKSEL1_TMR1SEL_HIRC (0x4UL<<CLK_CLKSEL1_TMR1SEL_Pos)
#define | CLK_CLKSEL1_TMR1SEL_MIRC (0x5UL<<CLK_CLKSEL1_TMR1SEL_Pos)
#define | CLK_CLKSEL1_TMR1SEL_EXT (0x3UL<<CLK_CLKSEL1_TMR1SEL_Pos)
#define | CLK_CLKSEL1_TMR1SEL_HCLK (0x6UL<<CLK_CLKSEL1_TMR1SEL_Pos)
#define | CLK_CLKSEL1_ADCSEL_HXT (0x0UL<<CLK_CLKSEL1_ADCSEL_Pos)
#define | CLK_CLKSEL1_ADCSEL_LXT (0x1UL<<CLK_CLKSEL1_ADCSEL_Pos)
#define | CLK_CLKSEL1_ADCSEL_PLL (0x2UL<<CLK_CLKSEL1_ADCSEL_Pos)
#define | CLK_CLKSEL1_ADCSEL_HIRC (0x3UL<<CLK_CLKSEL1_ADCSEL_Pos)
#define | CLK_CLKSEL1_ADCSEL_MIRC (0x4UL<<CLK_CLKSEL1_ADCSEL_Pos)
#define | CLK_CLKSEL1_ADCSEL_HCLK (0x5UL<<CLK_CLKSEL1_ADCSEL_Pos)
#define | CLK_CLKSEL1_SPI0SEL_HXT (0x2UL<<CLK_CLKSEL1_SPI0SEL_Pos)
#define | CLK_CLKSEL1_SPI0SEL_PLL (0x0UL<<CLK_CLKSEL1_SPI0SEL_Pos)
#define | CLK_CLKSEL1_SPI0SEL_HIRC (0x3UL<<CLK_CLKSEL1_SPI0SEL_Pos)
#define | CLK_CLKSEL1_SPI0SEL_HCLK (0x1UL<<CLK_CLKSEL1_SPI0SEL_Pos)
#define | CLK_CLKSEL1_SPI2SEL_HXT (0x2UL<<CLK_CLKSEL1_SPI2SEL_Pos)
#define | CLK_CLKSEL1_SPI2SEL_PLL (0x0UL<<CLK_CLKSEL1_SPI2SEL_Pos)
#define | CLK_CLKSEL1_SPI2SEL_HIRC (0x3UL<<CLK_CLKSEL1_SPI2SEL_Pos)
#define | CLK_CLKSEL1_SPI2SEL_HCLK (0x1UL<<CLK_CLKSEL1_SPI2SEL_Pos)
#define | CLK_CLKSEL1_WDTSEL_LXT (0x1UL<<CLK_CLKSEL1_WDTSEL_Pos)
#define | CLK_CLKSEL1_WDTSEL_LIRC (0x3UL<<CLK_CLKSEL1_WDTSEL_Pos)
#define | CLK_CLKSEL1_WDTSEL_HCLKDIV2048 (0x2UL<<CLK_CLKSEL1_WDTSEL_Pos)
#define | CLK_CLKSEL1_WWDTSEL_LIRC (0x3UL<<CLK_CLKSEL1_WWDTSEL_Pos)
#define | CLK_CLKSEL1_WWDTSEL_HCLKDIV2048 (0x2UL<<CLK_CLKSEL1_WWDTSEL_Pos)
#define | CLK_CLKSEL2_UART1SEL_HXT (0x0UL<<CLK_CLKSEL2_UART1SEL_Pos)
#define | CLK_CLKSEL2_UART1SEL_LXT (0x1UL<<CLK_CLKSEL2_UART1SEL_Pos)
#define | CLK_CLKSEL2_UART1SEL_PLL (0x2UL<<CLK_CLKSEL2_UART1SEL_Pos)
#define | CLK_CLKSEL2_UART1SEL_HIRC (0x3UL<<CLK_CLKSEL2_UART1SEL_Pos)
#define | CLK_CLKSEL2_UART1SEL_MIRC (0x4UL<<CLK_CLKSEL2_UART1SEL_Pos)
#define | CLK_CLKSEL2_CLKOSEL_HXT (0x0UL<<CLK_CLKSEL2_CLKOSEL_Pos)
#define | CLK_CLKSEL2_CLKOSEL_LXT (0x1UL<<CLK_CLKSEL2_CLKOSEL_Pos)
#define | CLK_CLKSEL2_CLKOSEL_HCLK (0x2UL<<CLK_CLKSEL2_CLKOSEL_Pos)
#define | CLK_CLKSEL2_CLKOSEL_HIRC (0x3UL<<CLK_CLKSEL2_CLKOSEL_Pos)
#define | CLK_CLKSEL2_CLKOSEL_MIRC (0x4UL<<CLK_CLKSEL2_CLKOSEL_Pos)
#define | CLK_CLKSEL2_TMR2SEL_HXT (0x0UL<<CLK_CLKSEL2_TMR2SEL_Pos)
#define | CLK_CLKSEL2_TMR2SEL_LXT (0x1UL<<CLK_CLKSEL2_TMR2SEL_Pos)
#define | CLK_CLKSEL2_TMR2SEL_LIRC (0x2UL<<CLK_CLKSEL2_TMR2SEL_Pos)
#define | CLK_CLKSEL2_TMR2SEL_HIRC (0x4UL<<CLK_CLKSEL2_TMR2SEL_Pos)
#define | CLK_CLKSEL2_TMR2SEL_MIRC (0x5UL<<CLK_CLKSEL2_TMR2SEL_Pos)
#define | CLK_CLKSEL2_TMR2SEL_EXT (0x3UL<<CLK_CLKSEL2_TMR2SEL_Pos)
#define | CLK_CLKSEL2_TMR2SEL_HCLK (0x6UL<<CLK_CLKSEL2_TMR2SEL_Pos)
#define | CLK_CLKSEL2_TMR3SEL_HXT (0x0UL<<CLK_CLKSEL2_TMR3SEL_Pos)
#define | CLK_CLKSEL2_TMR3SEL_LXT (0x1UL<<CLK_CLKSEL2_TMR3SEL_Pos)
#define | CLK_CLKSEL2_TMR3SEL_LIRC (0x2UL<<CLK_CLKSEL2_TMR3SEL_Pos)
#define | CLK_CLKSEL2_TMR3SEL_HIRC (0x4UL<<CLK_CLKSEL2_TMR3SEL_Pos)
#define | CLK_CLKSEL2_TMR3SEL_MIRC (0x5UL<<CLK_CLKSEL2_TMR3SEL_Pos)
#define | CLK_CLKSEL2_TMR3SEL_EXT (0x3UL<<CLK_CLKSEL2_TMR3SEL_Pos)
#define | CLK_CLKSEL2_TMR3SEL_HCLK (0x6UL<<CLK_CLKSEL2_TMR3SEL_Pos)
#define | CLK_CLKSEL2_SC0SEL_HXT (0x0UL<<CLK_CLKSEL2_SC0SEL_Pos)
#define | CLK_CLKSEL2_SC0SEL_PLL (0x1UL<<CLK_CLKSEL2_SC0SEL_Pos)
#define | CLK_CLKSEL2_SC0SEL_HIRC (0x2UL<<CLK_CLKSEL2_SC0SEL_Pos)
#define | CLK_CLKSEL2_SC0SEL_MIRC (0x3UL<<CLK_CLKSEL2_SC0SEL_Pos)
#define | CLK_CLKSEL2_SC0SEL_HCLK (0x4UL<<CLK_CLKSEL2_SC0SEL_Pos)
#define | CLK_CLKSEL2_SC1SEL_HXT (0x0UL<<CLK_CLKSEL2_SC1SEL_Pos)
#define | CLK_CLKSEL2_SC1SEL_PLL (0x1UL<<CLK_CLKSEL2_SC1SEL_Pos)
#define | CLK_CLKSEL2_SC1SEL_HIRC (0x2UL<<CLK_CLKSEL2_SC1SEL_Pos)
#define | CLK_CLKSEL2_SC1SEL_MIRC (0x3UL<<CLK_CLKSEL2_SC1SEL_Pos)
#define | CLK_CLKSEL2_SC1SEL_HCLK (0x4UL<<CLK_CLKSEL2_SC1SEL_Pos)
#define | CLK_CLKSEL2_SPI1SEL_HXT (0x2UL<<CLK_CLKSEL2_SPI1SEL_Pos)
#define | CLK_CLKSEL2_SPI1SEL_PLL (0x0UL<<CLK_CLKSEL2_SPI1SEL_Pos)
#define | CLK_CLKSEL2_SPI1SEL_HIRC (0x3UL<<CLK_CLKSEL2_SPI1SEL_Pos)
#define | CLK_CLKSEL2_SPI1SEL_HCLK (0x1UL<<CLK_CLKSEL2_SPI1SEL_Pos)
#define | CLK_CLKSEL2_SPI3SEL_HXT (0x2UL<<CLK_CLKSEL2_SPI3SEL_Pos)
#define | CLK_CLKSEL2_SPI3SEL_PLL (0x0UL<<CLK_CLKSEL2_SPI3SEL_Pos)
#define | CLK_CLKSEL2_SPI3SEL_HIRC (0x3UL<<CLK_CLKSEL2_SPI3SEL_Pos)
#define | CLK_CLKSEL2_SPI3SEL_HCLK (0x1UL<<CLK_CLKSEL2_SPI3SEL_Pos)
#define | CLK_APB0DIV_HCLK (0x0UL<<CLK_APBDIV_APB0DIV_Pos)
#define | CLK_APB0DIV_1_2HCLK (0x1UL<<CLK_APBDIV_APB0DIV_Pos)
#define | CLK_APB0DIV_1_4HCLK (0x2UL<<CLK_APBDIV_APB0DIV_Pos)
#define | CLK_APB0DIV_1_8HCLK (0x3UL<<CLK_APBDIV_APB0DIV_Pos)
#define | CLK_APB0DIV_1_16HCLK (0x4UL<<CLK_APBDIV_APB0DIV_Pos)
#define | CLK_APB1DIV_HCLK (0x0UL<<CLK_APBDIV_APB1DIV_Pos)
#define | CLK_APB1DIV_1_2HCLK (0x1UL<<CLK_APBDIV_APB1DIV_Pos)
#define | CLK_APB1DIV_1_4HCLK (0x2UL<<CLK_APBDIV_APB1DIV_Pos)
#define | CLK_APB1DIV_1_8HCLK (0x3UL<<CLK_APBDIV_APB1DIV_Pos)
#define | CLK_APB1DIV_1_16HCLK (0x4UL<<CLK_APBDIV_APB1DIV_Pos)
#define | CLK_HCLK_CLK_DIVIDER(x) ((((uint32_t)x-1)<<CLK_CLKDIV0_HCLKDIV_Pos) & CLK_CLKDIV0_HCLKDIV_Msk) /* CLKDIV0 Setting for HCLK clock divider. It could be 1~16*/
#define | CLK_UART0_CLK_DIVIDER(x) ((((uint32_t)x-1)<<CLK_CLKDIV0_UART0DIV_Pos)& CLK_CLKDIV0_UART0DIV_Msk) /* CLKDIV0 Setting for UART0 clock divider. It could be 1~16*/
#define | CLK_TMR0_CLK_DIVIDER(x) ((((uint32_t)x-1)<<CLK_CLKDIV1_TMR0DIV_Pos) & CLK_CLKDIV1_TMR0DIV_Msk) /* CLKDIV1 Setting for TMR0 clock divider. It could be 1~16*/
#define | CLK_TMR1_CLK_DIVIDER(x) ((((uint32_t)x-1)<<CLK_CLKDIV1_TMR1DIV_Pos) & CLK_CLKDIV1_TMR1DIV_Msk) /* CLKDIV1 Setting for TMR1 clock divider. It could be 1~16*/
#define | CLK_ADC_CLK_DIVIDER(x) ((((uint32_t)x-1)<<CLK_CLKDIV0_ADCDIV_Pos) & CLK_CLKDIV0_ADCDIV_Msk) /* CLKDIV0 Setting for ADC clock divider. It could be 1~256*/
#define | CLK_UART1_CLK_DIVIDER(x) ((((uint32_t)x-1)<<CLK_CLKDIV0_UART1DIV_Pos)& CLK_CLKDIV0_UART1DIV_Msk) /* CLKDIV0 Setting for UART1 clock divider. It could be 1~16*/
#define | CLK_TMR2_CLK_DIVIDER(x) ((((uint32_t)x-1)<<CLK_CLKDIV1_TMR2DIV_Pos) & CLK_CLKDIV1_TMR2DIV_Msk) /* CLKDIV1 Setting for TMR2 clock divider. It could be 1~16*/
#define | CLK_TMR3_CLK_DIVIDER(x) ((((uint32_t)x-1)<<CLK_CLKDIV1_TMR3DIV_Pos) & CLK_CLKDIV1_TMR3DIV_Msk) /* CLKDIV1 Setting for TMR3 clock divider. It could be 1~16*/
#define | CLK_SC0_CLK_DIVIDER(x) ((((uint32_t)x-1)<<CLK_CLKDIV0_SC0DIV_Pos) & CLK_CLKDIV0_SC0DIV_Msk) /* CLKDIV0 Setting for SC0 clock divider. It could be 1~16*/
#define | CLK_SC1_CLK_DIVIDER(x) ((((uint32_t)x-1)<<CLK_CLKDIV1_SC1DIV_Pos) & CLK_CLKDIV1_SC1DIV_Msk) /* CLKDIV1 Setting for SC1 clock divider. It could be 1~16*/
#define | CLK_CLKSEL0_STCLKSEL_HCLK (1)
#define | CLK_CLKSEL0_STCLKSEL_HCLK_DIV8 (2)
#define | CLK_CLKO_EN ((uint32_t)0x00000010)
#define | CLK_WK_INTSTS_IS ((uint32_t)0x00000001)
#define | MODULE_APBCLK(x) ((x >>31) & 0x1)
#define | MODULE_CLKSEL(x) ((x >>29) & 0x3)
#define | MODULE_CLKSEL_Msk(x) ((x >>25) & 0xf)
#define | MODULE_CLKSEL_Pos(x) ((x >>20) & 0x1f)
#define | MODULE_CLKDIV(x) ((x >>18) & 0x3)
#define | MODULE_CLKDIV_Msk(x) ((x >>10) & 0xff)
#define | MODULE_CLKDIV_Pos(x) ((x >>5 ) & 0x1f)
#define | MODULE_IP_EN_Pos(x) ((x >>0 ) & 0x1f)
#define | MODULE_NoMsk 0x0
#define | NA MODULE_NoMsk
#define | MODULE_APBCLK_ENC(x) (((x) & 0x01) << 31)
#define | MODULE_CLKSEL_ENC(x) (((x) & 0x03) << 29)
#define | MODULE_CLKSEL_Msk_ENC(x) (((x) & 0x0f) << 25)
#define | MODULE_CLKSEL_Pos_ENC(x) (((x) & 0x1f) << 20)
#define | MODULE_CLKDIV_ENC(x) (((x) & 0x03) << 18)
#define | MODULE_CLKDIV_Msk_ENC(x) (((x) & 0xff) << 10)
#define | MODULE_CLKDIV_Pos_ENC(x) (((x) & 0x1f) << 5)
#define | MODULE_IP_EN_Pos_ENC(x) (((x) & 0x1f) << 0)
#define | GPIO_MODULE
#define | PDMA_MODULE
#define | ISP_MODULE
#define | SRAM_MODULE
#define | STC_MODULE
#define | WDT_MODULE
#define | WWDT_MODULE
#define | RTC_MODULE
#define | TMR0_MODULE
#define | TMR1_MODULE
#define | TMR2_MODULE
#define | TMR3_MODULE
#define | CLKO_MODULE
#define | I2C0_MODULE
#define | I2C1_MODULE
#define | ACMP0_MODULE
#define | SPI0_MODULE
#define | SPI1_MODULE
#define | SPI2_MODULE
#define | SPI3_MODULE
#define | UART0_MODULE
#define | UART1_MODULE
#define | PWM0_MODULE
#define | ADC_MODULE
#define | SC0_MODULE
#define | SC1_MODULE

## Detailed Description

## Macro Definition Documentation

## ◆ ACMP0_MODULE

#define ACMP0_MODULE

ACMP0 Module

Definition at line 309 of file clk.h.

## ◆ ADC_MODULE

#define ADC_MODULE

ADC Module

Definition at line 317 of file clk.h.

## ◆ CLK_ADC_CLK_DIVIDER

#define CLK_ADC_CLK_DIVIDER | ( |  | x | ) | ((((uint32_t)x-1)<<CLK_CLKDIV0_ADCDIV_Pos) & CLK_CLKDIV0_ADCDIV_Msk) /* CLKDIV0 Setting for ADC clock divider. It could be 1~256*/

Definition at line 250 of file clk.h.

## ◆ CLK_AHBCLK_DMA_EN

#define CLK_AHBCLK_DMA_EN ((uint32_t)0x00000002)

DMA clock enable

Definition at line 61 of file clk.h.

## ◆ CLK_AHBCLK_GPIO_EN

#define CLK_AHBCLK_GPIO_EN ((uint32_t)0x00000001)

GPIO clock enable

Definition at line 60 of file clk.h.

## ◆ CLK_AHBCLK_ISP_EN

#define CLK_AHBCLK_ISP_EN ((uint32_t)0x00000004)

Flash ISP controller clock enable

Definition at line 62 of file clk.h.

## ◆ CLK_AHBCLK_SRAM_EN

#define CLK_AHBCLK_SRAM_EN ((uint32_t)0x00000010)

SRAM Controller Clock Enable

Definition at line 63 of file clk.h.

## ◆ CLK_AHBCLK_TICK_EN

#define CLK_AHBCLK_TICK_EN ((uint32_t)0x00000020)

System Tick Clock Enable

Definition at line 64 of file clk.h.

## ◆ CLK_APB0DIV_1_16HCLK

#define CLK_APB0DIV_1_16HCLK (0x4UL<<CLK_APBDIV_APB0DIV_Pos)

Select PCLK0 clock source from 1/16HCLK

Definition at line 238 of file clk.h.

## ◆ CLK_APB0DIV_1_2HCLK

#define CLK_APB0DIV_1_2HCLK (0x1UL<<CLK_APBDIV_APB0DIV_Pos)

Select PCLK0 clock source from 1/2HCLK

Definition at line 235 of file clk.h.

## ◆ CLK_APB0DIV_1_4HCLK

#define CLK_APB0DIV_1_4HCLK (0x2UL<<CLK_APBDIV_APB0DIV_Pos)

Select PCLK0 clock source from 1/4HCLK

Definition at line 236 of file clk.h.

## ◆ CLK_APB0DIV_1_8HCLK

#define CLK_APB0DIV_1_8HCLK (0x3UL<<CLK_APBDIV_APB0DIV_Pos)

Select PCLK0 clock source from 1/8HCLK

Definition at line 237 of file clk.h.

## ◆ CLK_APB0DIV_HCLK

#define CLK_APB0DIV_HCLK (0x0UL<<CLK_APBDIV_APB0DIV_Pos)

Select PCLK0 clock source from HCLK

Definition at line 234 of file clk.h.

## ◆ CLK_APB1DIV_1_16HCLK

#define CLK_APB1DIV_1_16HCLK (0x4UL<<CLK_APBDIV_APB1DIV_Pos)

Select PCLK1 clock source from 1/16HCLK

Definition at line 243 of file clk.h.

## ◆ CLK_APB1DIV_1_2HCLK

#define CLK_APB1DIV_1_2HCLK (0x1UL<<CLK_APBDIV_APB1DIV_Pos)

Select PCLK1 clock source from 1/2HCLK

Definition at line 240 of file clk.h.

## ◆ CLK_APB1DIV_1_4HCLK

#define CLK_APB1DIV_1_4HCLK (0x2UL<<CLK_APBDIV_APB1DIV_Pos)

Select PCLK1 clock source from 1/4HCLK

Definition at line 241 of file clk.h.

## ◆ CLK_APB1DIV_1_8HCLK

#define CLK_APB1DIV_1_8HCLK (0x3UL<<CLK_APBDIV_APB1DIV_Pos)

Select PCLK1 clock source from 1/8HCLK

Definition at line 242 of file clk.h.

## ◆ CLK_APB1DIV_HCLK

#define CLK_APB1DIV_HCLK (0x0UL<<CLK_APBDIV_APB1DIV_Pos)

Select PCLK1 clock source from HCLK

Definition at line 239 of file clk.h.

## ◆ CLK_APBCLK_ACMP0_EN

#define CLK_APBCLK_ACMP0_EN ((uint32_t)0x00000800)

ACMP0 clock Enable Control

Definition at line 76 of file clk.h.

## ◆ CLK_APBCLK_ADC_EN

#define CLK_APBCLK_ADC_EN ((uint32_t)0x10000000)

ADC clock enable

Definition at line 84 of file clk.h.

## ◆ CLK_APBCLK_CLKOC_EN

#define CLK_APBCLK_CLKOC_EN ((uint32_t)0x00000040)

Frequency Divider Output clock enable

Definition at line 73 of file clk.h.

## ◆ CLK_APBCLK_I2C0_EN

#define CLK_APBCLK_I2C0_EN ((uint32_t)0x00000100)

I2C 0 clock enable

Definition at line 74 of file clk.h.

## ◆ CLK_APBCLK_I2C1_EN

#define CLK_APBCLK_I2C1_EN ((uint32_t)0x00000200)

I2C 1 clock enable

Definition at line 75 of file clk.h.

## ◆ CLK_APBCLK_PWM0_EN

#define CLK_APBCLK_PWM0_EN ((uint32_t)0x00100000)

PWM0 clock Enable Control

Definition at line 83 of file clk.h.

## ◆ CLK_APBCLK_RTC_EN

#define CLK_APBCLK_RTC_EN ((uint32_t)0x00000002)

RTC clock enable

Definition at line 68 of file clk.h.

## ◆ CLK_APBCLK_SC0_EN

#define CLK_APBCLK_SC0_EN ((uint32_t)0x40000000)

SmartCard 0 Clock Enable Control

Definition at line 85 of file clk.h.

## ◆ CLK_APBCLK_SC1_EN

#define CLK_APBCLK_SC1_EN ((uint32_t)0x80000000)

SmartCard 1 Clock Enable Control

Definition at line 86 of file clk.h.

## ◆ CLK_APBCLK_SPI0_EN

#define CLK_APBCLK_SPI0_EN ((uint32_t)0x00001000)

SPI 0 clock enable

Definition at line 77 of file clk.h.

## ◆ CLK_APBCLK_SPI1_EN

#define CLK_APBCLK_SPI1_EN ((uint32_t)0x00002000)

SPI 1 clock enable

Definition at line 78 of file clk.h.

## ◆ CLK_APBCLK_SPI2_EN

#define CLK_APBCLK_SPI2_EN ((uint32_t)0x00004000)

SPI 2 clock enable

Definition at line 79 of file clk.h.

## ◆ CLK_APBCLK_SPI3_EN

#define CLK_APBCLK_SPI3_EN ((uint32_t)0x00008000)

SPI 3 clock enable

Definition at line 80 of file clk.h.

## ◆ CLK_APBCLK_TMR0_EN

#define CLK_APBCLK_TMR0_EN ((uint32_t)0x00000004)

Timer 0 clock enable

Definition at line 69 of file clk.h.

## ◆ CLK_APBCLK_TMR1_EN

#define CLK_APBCLK_TMR1_EN ((uint32_t)0x00000008)

Timer 1 clock enable

Definition at line 70 of file clk.h.

## ◆ CLK_APBCLK_TMR2_EN

#define CLK_APBCLK_TMR2_EN ((uint32_t)0x00000010)

Timer 2 clock enable

Definition at line 71 of file clk.h.

## ◆ CLK_APBCLK_TMR3_EN

#define CLK_APBCLK_TMR3_EN ((uint32_t)0x00000020)

Timer 3 clock enable

Definition at line 72 of file clk.h.

## ◆ CLK_APBCLK_UART0_EN

#define CLK_APBCLK_UART0_EN ((uint32_t)0x00010000)

UART 0 clock enable

Definition at line 81 of file clk.h.

## ◆ CLK_APBCLK_UART1_EN

#define CLK_APBCLK_UART1_EN ((uint32_t)0x00020000)

UART 1 clock enable

Definition at line 82 of file clk.h.

## ◆ CLK_APBCLK_WDT_EN

#define CLK_APBCLK_WDT_EN ((uint32_t)0x00000001)

Watchdog clock enable

Definition at line 67 of file clk.h.

## ◆ CLK_CLKO_EN

#define CLK_CLKO_EN ((uint32_t)0x00000010)

Frequency divider enable bit

Definition at line 262 of file clk.h.

## ◆ CLK_CLKSEL0_HCLKSEL_HIRC

#define CLK_CLKSEL0_HCLKSEL_HIRC (0x4UL<<CLK_CLKSEL0_HCLKSEL_Pos)

Select HCLK clock source from high speed oscillator

Definition at line 142 of file clk.h.

## ◆ CLK_CLKSEL0_HCLKSEL_HIRC0

#define CLK_CLKSEL0_HCLKSEL_HIRC0 (0x4UL<<CLK_CLKSEL0_HCLKSEL_Pos)

Select HCLK clock source from high speed oscillator

Definition at line 143 of file clk.h.

## ◆ CLK_CLKSEL0_HCLKSEL_HIRC1

#define CLK_CLKSEL0_HCLKSEL_HIRC1 (0xCUL<<CLK_CLKSEL0_HCLKSEL_Pos)

Select HCLK clock source from high speed oscillator

Definition at line 144 of file clk.h.

## ◆ CLK_CLKSEL0_HCLKSEL_HXT

#define CLK_CLKSEL0_HCLKSEL_HXT (0x0UL<<CLK_CLKSEL0_HCLKSEL_Pos)

Select HCLK clock source from high speed crystal

Definition at line 138 of file clk.h.

## ◆ CLK_CLKSEL0_HCLKSEL_LIRC

#define CLK_CLKSEL0_HCLKSEL_LIRC (0x3UL<<CLK_CLKSEL0_HCLKSEL_Pos)

Select HCLK clock source from low speed oscillator

Definition at line 141 of file clk.h.

## ◆ CLK_CLKSEL0_HCLKSEL_LXT

#define CLK_CLKSEL0_HCLKSEL_LXT (0x1UL<<CLK_CLKSEL0_HCLKSEL_Pos)

Select HCLK clock source from low speed crystal

Definition at line 139 of file clk.h.

## ◆ CLK_CLKSEL0_HCLKSEL_MIRC

#define CLK_CLKSEL0_HCLKSEL_MIRC (0x5UL<<CLK_CLKSEL0_HCLKSEL_Pos)

Select HCLK clock source from medium speed oscillator

Definition at line 145 of file clk.h.

## ◆ CLK_CLKSEL0_HCLKSEL_PLL

#define CLK_CLKSEL0_HCLKSEL_PLL (0x2UL<<CLK_CLKSEL0_HCLKSEL_Pos)

Select HCLK clock source from PLL

Definition at line 140 of file clk.h.

## ◆ CLK_CLKSEL0_ISPSEL_HIRC

#define CLK_CLKSEL0_ISPSEL_HIRC (0x0UL<<CLK_CLKSEL0_ISPSEL_Pos)

Select ISP clock source from high speed oscillator

Definition at line 146 of file clk.h.

## ◆ CLK_CLKSEL0_ISPSEL_MIRC

#define CLK_CLKSEL0_ISPSEL_MIRC (0x1UL<<CLK_CLKSEL0_ISPSEL_Pos)

Select ISP clock source from medium speed oscillator

Definition at line 147 of file clk.h.

## ◆ CLK_CLKSEL0_STCLKSEL_HCLK

#define CLK_CLKSEL0_STCLKSEL_HCLK (1)

Setting systick clock source as external HCLK

Definition at line 258 of file clk.h.

## ◆ CLK_CLKSEL0_STCLKSEL_HCLK_DIV8

#define CLK_CLKSEL0_STCLKSEL_HCLK_DIV8 (2)

Setting systick clock source as external HCLK/8

Definition at line 259 of file clk.h.

## ◆ CLK_CLKSEL1_ADCSEL_HCLK

#define CLK_CLKSEL1_ADCSEL_HCLK (0x5UL<<CLK_CLKSEL1_ADCSEL_Pos)

Select ADC clock source from HCLK

Definition at line 175 of file clk.h.

## ◆ CLK_CLKSEL1_ADCSEL_HIRC

#define CLK_CLKSEL1_ADCSEL_HIRC (0x3UL<<CLK_CLKSEL1_ADCSEL_Pos)

Select ADC clock source from high speed oscillator

Definition at line 173 of file clk.h.

## ◆ CLK_CLKSEL1_ADCSEL_HXT

#define CLK_CLKSEL1_ADCSEL_HXT (0x0UL<<CLK_CLKSEL1_ADCSEL_Pos)

Select ADC clock source from high speed crystal

Definition at line 170 of file clk.h.

## ◆ CLK_CLKSEL1_ADCSEL_LXT

#define CLK_CLKSEL1_ADCSEL_LXT (0x1UL<<CLK_CLKSEL1_ADCSEL_Pos)

Select ADC clock source from low speed crystal

Definition at line 171 of file clk.h.

## ◆ CLK_CLKSEL1_ADCSEL_MIRC

#define CLK_CLKSEL1_ADCSEL_MIRC (0x4UL<<CLK_CLKSEL1_ADCSEL_Pos)

Select ADC clock source from medium speed oscillator

Definition at line 174 of file clk.h.

## ◆ CLK_CLKSEL1_ADCSEL_PLL

#define CLK_CLKSEL1_ADCSEL_PLL (0x2UL<<CLK_CLKSEL1_ADCSEL_Pos)

Select ADC clock source from PLL

Definition at line 172 of file clk.h.

## ◆ CLK_CLKSEL1_PWM0SEL_PCLK0

#define CLK_CLKSEL1_PWM0SEL_PCLK0 (0x1UL<<CLK_CLKSEL1_PWM0SEL_Pos)

Select PWM0 clock source from PCLK0

Definition at line 155 of file clk.h.

## ◆ CLK_CLKSEL1_PWM0SEL_PLL

#define CLK_CLKSEL1_PWM0SEL_PLL (0x0UL<<CLK_CLKSEL1_PWM0SEL_Pos)

Select PWM0 clock source from PLL

Definition at line 154 of file clk.h.

## ◆ CLK_CLKSEL1_SPI0SEL_HCLK

#define CLK_CLKSEL1_SPI0SEL_HCLK (0x1UL<<CLK_CLKSEL1_SPI0SEL_Pos)

Select SPI0 clock source from HCLK

Definition at line 179 of file clk.h.

## ◆ CLK_CLKSEL1_SPI0SEL_HIRC

#define CLK_CLKSEL1_SPI0SEL_HIRC (0x3UL<<CLK_CLKSEL1_SPI0SEL_Pos)

Select SPI0 clock source from high speed oscillator

Definition at line 178 of file clk.h.

## ◆ CLK_CLKSEL1_SPI0SEL_HXT

#define CLK_CLKSEL1_SPI0SEL_HXT (0x2UL<<CLK_CLKSEL1_SPI0SEL_Pos)

Select SPI0 clock source from high speed crystal

Definition at line 176 of file clk.h.

## ◆ CLK_CLKSEL1_SPI0SEL_PLL

#define CLK_CLKSEL1_SPI0SEL_PLL (0x0UL<<CLK_CLKSEL1_SPI0SEL_Pos)

Select SPI0 clock source from PLL

Definition at line 177 of file clk.h.

## ◆ CLK_CLKSEL1_SPI2SEL_HCLK

#define CLK_CLKSEL1_SPI2SEL_HCLK (0x1UL<<CLK_CLKSEL1_SPI2SEL_Pos)

Select SPI2 clock source from HCLK

Definition at line 183 of file clk.h.

## ◆ CLK_CLKSEL1_SPI2SEL_HIRC

#define CLK_CLKSEL1_SPI2SEL_HIRC (0x3UL<<CLK_CLKSEL1_SPI2SEL_Pos)

Select SPI2 clock source from high speed oscillator

Definition at line 182 of file clk.h.

## ◆ CLK_CLKSEL1_SPI2SEL_HXT

#define CLK_CLKSEL1_SPI2SEL_HXT (0x2UL<<CLK_CLKSEL1_SPI2SEL_Pos)

Select SPI2 clock source from high speed crystal

Definition at line 180 of file clk.h.

## ◆ CLK_CLKSEL1_SPI2SEL_PLL

#define CLK_CLKSEL1_SPI2SEL_PLL (0x0UL<<CLK_CLKSEL1_SPI2SEL_Pos)

Select SPI2 clock source from PLL

Definition at line 181 of file clk.h.

## ◆ CLK_CLKSEL1_TMR0SEL_EXT

#define CLK_CLKSEL1_TMR0SEL_EXT (0x3UL<<CLK_CLKSEL1_TMR0SEL_Pos)

Select TMR0 clock source from external trigger

Definition at line 161 of file clk.h.

## ◆ CLK_CLKSEL1_TMR0SEL_HCLK

#define CLK_CLKSEL1_TMR0SEL_HCLK (0x6UL<<CLK_CLKSEL1_TMR0SEL_Pos)

Select TMR0 clock source from HCLK

Definition at line 162 of file clk.h.

## ◆ CLK_CLKSEL1_TMR0SEL_HIRC

#define CLK_CLKSEL1_TMR0SEL_HIRC (0x4UL<<CLK_CLKSEL1_TMR0SEL_Pos)

Select TMR0 clock source from high speed oscillator

Definition at line 159 of file clk.h.

## ◆ CLK_CLKSEL1_TMR0SEL_HXT

#define CLK_CLKSEL1_TMR0SEL_HXT (0x0UL<<CLK_CLKSEL1_TMR0SEL_Pos)

Select TMR0 clock source from high speed crystal

Definition at line 156 of file clk.h.

## ◆ CLK_CLKSEL1_TMR0SEL_LIRC

#define CLK_CLKSEL1_TMR0SEL_LIRC (0x2UL<<CLK_CLKSEL1_TMR0SEL_Pos)

Select TMR0 clock source from low speed oscillator

Definition at line 158 of file clk.h.

## ◆ CLK_CLKSEL1_TMR0SEL_LXT

#define CLK_CLKSEL1_TMR0SEL_LXT (0x1UL<<CLK_CLKSEL1_TMR0SEL_Pos)

Select TMR0 clock source from low speed crystal

Definition at line 157 of file clk.h.

## ◆ CLK_CLKSEL1_TMR0SEL_MIRC

#define CLK_CLKSEL1_TMR0SEL_MIRC (0x5UL<<CLK_CLKSEL1_TMR0SEL_Pos)

Select TMR0 clock source from medium speed oscillator

Definition at line 160 of file clk.h.

## ◆ CLK_CLKSEL1_TMR1SEL_EXT

#define CLK_CLKSEL1_TMR1SEL_EXT (0x3UL<<CLK_CLKSEL1_TMR1SEL_Pos)

Select TMR1 clock source from external trigger

Definition at line 168 of file clk.h.

## ◆ CLK_CLKSEL1_TMR1SEL_HCLK

#define CLK_CLKSEL1_TMR1SEL_HCLK (0x6UL<<CLK_CLKSEL1_TMR1SEL_Pos)

Select TMR1 clock source from HCLK

Definition at line 169 of file clk.h.

## ◆ CLK_CLKSEL1_TMR1SEL_HIRC

#define CLK_CLKSEL1_TMR1SEL_HIRC (0x4UL<<CLK_CLKSEL1_TMR1SEL_Pos)

Select TMR1 clock source from high speed oscillator

Definition at line 166 of file clk.h.

## ◆ CLK_CLKSEL1_TMR1SEL_HXT

#define CLK_CLKSEL1_TMR1SEL_HXT (0x0UL<<CLK_CLKSEL1_TMR1SEL_Pos)

Select TMR1 clock source from high speed crystal

Definition at line 163 of file clk.h.

## ◆ CLK_CLKSEL1_TMR1SEL_LIRC

#define CLK_CLKSEL1_TMR1SEL_LIRC (0x2UL<<CLK_CLKSEL1_TMR1SEL_Pos)

Select TMR1 clock source from low speed oscillator

Definition at line 165 of file clk.h.

## ◆ CLK_CLKSEL1_TMR1SEL_LXT

#define CLK_CLKSEL1_TMR1SEL_LXT (0x1UL<<CLK_CLKSEL1_TMR1SEL_Pos)

Select TMR1 clock source from low speed crystal

Definition at line 164 of file clk.h.

## ◆ CLK_CLKSEL1_TMR1SEL_MIRC

#define CLK_CLKSEL1_TMR1SEL_MIRC (0x5UL<<CLK_CLKSEL1_TMR1SEL_Pos)

Select TMR1 clock source from medium speed oscillator

Definition at line 167 of file clk.h.

## ◆ CLK_CLKSEL1_UART0SEL_HIRC

#define CLK_CLKSEL1_UART0SEL_HIRC (0x3UL<<CLK_CLKSEL1_UART0SEL_Pos)

Select UART0 clock source from high speed oscillator

Definition at line 152 of file clk.h.

## ◆ CLK_CLKSEL1_UART0SEL_HXT

#define CLK_CLKSEL1_UART0SEL_HXT (0x0UL<<CLK_CLKSEL1_UART0SEL_Pos)

Select UART0 clock source from high speed crystal

Definition at line 149 of file clk.h.

## ◆ CLK_CLKSEL1_UART0SEL_LXT

#define CLK_CLKSEL1_UART0SEL_LXT (0x1UL<<CLK_CLKSEL1_UART0SEL_Pos)

Select UART0 clock source from low speed crystal

Definition at line 150 of file clk.h.

## ◆ CLK_CLKSEL1_UART0SEL_MIRC

#define CLK_CLKSEL1_UART0SEL_MIRC (0x4UL<<CLK_CLKSEL1_UART0SEL_Pos)

Select UART0 clock source from medium speed oscillator

Definition at line 153 of file clk.h.

## ◆ CLK_CLKSEL1_UART0SEL_PLL

#define CLK_CLKSEL1_UART0SEL_PLL (0x2UL<<CLK_CLKSEL1_UART0SEL_Pos)

Select UART0 clock source from PLL

Definition at line 151 of file clk.h.

## ◆ CLK_CLKSEL1_WDTSEL_HCLKDIV2048

#define CLK_CLKSEL1_WDTSEL_HCLKDIV2048 (0x2UL<<CLK_CLKSEL1_WDTSEL_Pos)

Select WDT clock source from HCLK/2048

Definition at line 186 of file clk.h.

## ◆ CLK_CLKSEL1_WDTSEL_LIRC

#define CLK_CLKSEL1_WDTSEL_LIRC (0x3UL<<CLK_CLKSEL1_WDTSEL_Pos)

Select WDT clock source from low speed oscillator

Definition at line 185 of file clk.h.

## ◆ CLK_CLKSEL1_WDTSEL_LXT

#define CLK_CLKSEL1_WDTSEL_LXT (0x1UL<<CLK_CLKSEL1_WDTSEL_Pos)

Select WDT clock source from low speed crystal

Definition at line 184 of file clk.h.

## ◆ CLK_CLKSEL1_WWDTSEL_HCLKDIV2048

#define CLK_CLKSEL1_WWDTSEL_HCLKDIV2048 (0x2UL<<CLK_CLKSEL1_WWDTSEL_Pos)

Select WWDT clock source from HCLK/2048

Definition at line 188 of file clk.h.

## ◆ CLK_CLKSEL1_WWDTSEL_LIRC

#define CLK_CLKSEL1_WWDTSEL_LIRC (0x3UL<<CLK_CLKSEL1_WWDTSEL_Pos)

Select WWDT clock source from low speed oscillator

Definition at line 187 of file clk.h.

## ◆ CLK_CLKSEL2_CLKOSEL_HCLK

#define CLK_CLKSEL2_CLKOSEL_HCLK (0x2UL<<CLK_CLKSEL2_CLKOSEL_Pos)

Select CLKO clock source from HCLK

Definition at line 197 of file clk.h.

## ◆ CLK_CLKSEL2_CLKOSEL_HIRC

#define CLK_CLKSEL2_CLKOSEL_HIRC (0x3UL<<CLK_CLKSEL2_CLKOSEL_Pos)

Select CLKO clock source from high speed oscillator

Definition at line 198 of file clk.h.

## ◆ CLK_CLKSEL2_CLKOSEL_HXT

#define CLK_CLKSEL2_CLKOSEL_HXT (0x0UL<<CLK_CLKSEL2_CLKOSEL_Pos)

Select CLKO clock source from high speed crystal

Definition at line 195 of file clk.h.

## ◆ CLK_CLKSEL2_CLKOSEL_LXT

#define CLK_CLKSEL2_CLKOSEL_LXT (0x1UL<<CLK_CLKSEL2_CLKOSEL_Pos)

Select CLKO clock source from low speed crystal

Definition at line 196 of file clk.h.

## ◆ CLK_CLKSEL2_CLKOSEL_MIRC

#define CLK_CLKSEL2_CLKOSEL_MIRC (0x4UL<<CLK_CLKSEL2_CLKOSEL_Pos)

Select CLKO clock source from medium speed oscillator

Definition at line 199 of file clk.h.

## ◆ CLK_CLKSEL2_SC0SEL_HCLK

#define CLK_CLKSEL2_SC0SEL_HCLK (0x4UL<<CLK_CLKSEL2_SC0SEL_Pos)

Select SC0 clock source from HCLK

Definition at line 218 of file clk.h.

## ◆ CLK_CLKSEL2_SC0SEL_HIRC

#define CLK_CLKSEL2_SC0SEL_HIRC (0x2UL<<CLK_CLKSEL2_SC0SEL_Pos)

Select SC0 clock source from high speed oscillator

Definition at line 216 of file clk.h.

## ◆ CLK_CLKSEL2_SC0SEL_HXT

#define CLK_CLKSEL2_SC0SEL_HXT (0x0UL<<CLK_CLKSEL2_SC0SEL_Pos)

Select SC0 clock source from high speed crystal

Definition at line 214 of file clk.h.

## ◆ CLK_CLKSEL2_SC0SEL_MIRC

#define CLK_CLKSEL2_SC0SEL_MIRC (0x3UL<<CLK_CLKSEL2_SC0SEL_Pos)

Select SC0 clock source from medium speed oscillator

Definition at line 217 of file clk.h.

## ◆ CLK_CLKSEL2_SC0SEL_PLL

#define CLK_CLKSEL2_SC0SEL_PLL (0x1UL<<CLK_CLKSEL2_SC0SEL_Pos)

Select SC0 clock source from PLL

Definition at line 215 of file clk.h.

## ◆ CLK_CLKSEL2_SC1SEL_HCLK

#define CLK_CLKSEL2_SC1SEL_HCLK (0x4UL<<CLK_CLKSEL2_SC1SEL_Pos)

Select SC1 clock source from HCLK

Definition at line 223 of file clk.h.

## ◆ CLK_CLKSEL2_SC1SEL_HIRC

#define CLK_CLKSEL2_SC1SEL_HIRC (0x2UL<<CLK_CLKSEL2_SC1SEL_Pos)

Select SC1 clock source from high speed oscillator

Definition at line 221 of file clk.h.

## ◆ CLK_CLKSEL2_SC1SEL_HXT

#define CLK_CLKSEL2_SC1SEL_HXT (0x0UL<<CLK_CLKSEL2_SC1SEL_Pos)

Select SC1 clock source from high speed crystal

Definition at line 219 of file clk.h.

## ◆ CLK_CLKSEL2_SC1SEL_MIRC

#define CLK_CLKSEL2_SC1SEL_MIRC (0x3UL<<CLK_CLKSEL2_SC1SEL_Pos)

Select SC1 clock source from medium speed oscillator

Definition at line 222 of file clk.h.

## ◆ CLK_CLKSEL2_SC1SEL_PLL

#define CLK_CLKSEL2_SC1SEL_PLL (0x1UL<<CLK_CLKSEL2_SC1SEL_Pos)

Select SC1 clock source from PLL

Definition at line 220 of file clk.h.

## ◆ CLK_CLKSEL2_SPI1SEL_HCLK

#define CLK_CLKSEL2_SPI1SEL_HCLK (0x1UL<<CLK_CLKSEL2_SPI1SEL_Pos)

Select SPI1 clock source from HCLK

Definition at line 227 of file clk.h.

## ◆ CLK_CLKSEL2_SPI1SEL_HIRC

#define CLK_CLKSEL2_SPI1SEL_HIRC (0x3UL<<CLK_CLKSEL2_SPI1SEL_Pos)

Select SPI1 clock source from high speed oscillator

Definition at line 226 of file clk.h.

## ◆ CLK_CLKSEL2_SPI1SEL_HXT

#define CLK_CLKSEL2_SPI1SEL_HXT (0x2UL<<CLK_CLKSEL2_SPI1SEL_Pos)

Select SPI1 clock source from high speed crystal

Definition at line 224 of file clk.h.

## ◆ CLK_CLKSEL2_SPI1SEL_PLL

#define CLK_CLKSEL2_SPI1SEL_PLL (0x0UL<<CLK_CLKSEL2_SPI1SEL_Pos)

Select SPI1 clock source from PLL

Definition at line 225 of file clk.h.

## ◆ CLK_CLKSEL2_SPI3SEL_HCLK

#define CLK_CLKSEL2_SPI3SEL_HCLK (0x1UL<<CLK_CLKSEL2_SPI3SEL_Pos)

Select SPI3 clock source from HCLK

Definition at line 231 of file clk.h.

## ◆ CLK_CLKSEL2_SPI3SEL_HIRC

#define CLK_CLKSEL2_SPI3SEL_HIRC (0x3UL<<CLK_CLKSEL2_SPI3SEL_Pos)

Select SPI3 clock source from high speed oscillator

Definition at line 230 of file clk.h.

## ◆ CLK_CLKSEL2_SPI3SEL_HXT

#define CLK_CLKSEL2_SPI3SEL_HXT (0x2UL<<CLK_CLKSEL2_SPI3SEL_Pos)

Select SPI3 clock source from high speed crystal

Definition at line 228 of file clk.h.

## ◆ CLK_CLKSEL2_SPI3SEL_PLL

#define CLK_CLKSEL2_SPI3SEL_PLL (0x0UL<<CLK_CLKSEL2_SPI3SEL_Pos)

Select SPI3 clock source from PLL

Definition at line 229 of file clk.h.

## ◆ CLK_CLKSEL2_TMR2SEL_EXT

#define CLK_CLKSEL2_TMR2SEL_EXT (0x3UL<<CLK_CLKSEL2_TMR2SEL_Pos)

Select TMR2 clock source from external trigger

Definition at line 205 of file clk.h.

## ◆ CLK_CLKSEL2_TMR2SEL_HCLK

#define CLK_CLKSEL2_TMR2SEL_HCLK (0x6UL<<CLK_CLKSEL2_TMR2SEL_Pos)

Select TMR2 clock source from HCLK

Definition at line 206 of file clk.h.

## ◆ CLK_CLKSEL2_TMR2SEL_HIRC

#define CLK_CLKSEL2_TMR2SEL_HIRC (0x4UL<<CLK_CLKSEL2_TMR2SEL_Pos)

Select TMR2 clock source from high speed oscillator

Definition at line 203 of file clk.h.

## ◆ CLK_CLKSEL2_TMR2SEL_HXT

#define CLK_CLKSEL2_TMR2SEL_HXT (0x0UL<<CLK_CLKSEL2_TMR2SEL_Pos)

Select TMR2 clock source from high speed crystal

Definition at line 200 of file clk.h.

## ◆ CLK_CLKSEL2_TMR2SEL_LIRC

#define CLK_CLKSEL2_TMR2SEL_LIRC (0x2UL<<CLK_CLKSEL2_TMR2SEL_Pos)

Select TMR2 clock source from low speed oscillator

Definition at line 202 of file clk.h.

## ◆ CLK_CLKSEL2_TMR2SEL_LXT

#define CLK_CLKSEL2_TMR2SEL_LXT (0x1UL<<CLK_CLKSEL2_TMR2SEL_Pos)

Select TMR2 clock source from low speed crystal

Definition at line 201 of file clk.h.

## ◆ CLK_CLKSEL2_TMR2SEL_MIRC

#define CLK_CLKSEL2_TMR2SEL_MIRC (0x5UL<<CLK_CLKSEL2_TMR2SEL_Pos)

Select TMR2 clock source from medium speed oscillator

Definition at line 204 of file clk.h.

## ◆ CLK_CLKSEL2_TMR3SEL_EXT

#define CLK_CLKSEL2_TMR3SEL_EXT (0x3UL<<CLK_CLKSEL2_TMR3SEL_Pos)

Select TMR3 clock source from external trigger

Definition at line 212 of file clk.h.

## ◆ CLK_CLKSEL2_TMR3SEL_HCLK

#define CLK_CLKSEL2_TMR3SEL_HCLK (0x6UL<<CLK_CLKSEL2_TMR3SEL_Pos)

Select TMR3 clock source from HCLK

Definition at line 213 of file clk.h.

## ◆ CLK_CLKSEL2_TMR3SEL_HIRC

#define CLK_CLKSEL2_TMR3SEL_HIRC (0x4UL<<CLK_CLKSEL2_TMR3SEL_Pos)

Select TMR3 clock source from high speed oscillator

Definition at line 210 of file clk.h.

## ◆ CLK_CLKSEL2_TMR3SEL_HXT

#define CLK_CLKSEL2_TMR3SEL_HXT (0x0UL<<CLK_CLKSEL2_TMR3SEL_Pos)

Select TMR3 clock source from high speed crystal

Definition at line 207 of file clk.h.

## ◆ CLK_CLKSEL2_TMR3SEL_LIRC

#define CLK_CLKSEL2_TMR3SEL_LIRC (0x2UL<<CLK_CLKSEL2_TMR3SEL_Pos)

Select TMR3 clock source from low speed oscillator

Definition at line 209 of file clk.h.

## ◆ CLK_CLKSEL2_TMR3SEL_LXT

#define CLK_CLKSEL2_TMR3SEL_LXT (0x1UL<<CLK_CLKSEL2_TMR3SEL_Pos)

Select TMR3 clock source from low speed crystal

Definition at line 208 of file clk.h.

## ◆ CLK_CLKSEL2_TMR3SEL_MIRC

#define CLK_CLKSEL2_TMR3SEL_MIRC (0x5UL<<CLK_CLKSEL2_TMR3SEL_Pos)

Select TMR3 clock source from medium speed oscillator

Definition at line 211 of file clk.h.

## ◆ CLK_CLKSEL2_UART1SEL_HIRC

#define CLK_CLKSEL2_UART1SEL_HIRC (0x3UL<<CLK_CLKSEL2_UART1SEL_Pos)

Select UART1 clock source from high speed oscillator

Definition at line 193 of file clk.h.

## ◆ CLK_CLKSEL2_UART1SEL_HXT

#define CLK_CLKSEL2_UART1SEL_HXT (0x0UL<<CLK_CLKSEL2_UART1SEL_Pos)

Select UART1 clock source from high speed crystal

Definition at line 190 of file clk.h.

## ◆ CLK_CLKSEL2_UART1SEL_LXT

#define CLK_CLKSEL2_UART1SEL_LXT (0x1UL<<CLK_CLKSEL2_UART1SEL_Pos)

Select UART1 clock source from low speed crystal

Definition at line 191 of file clk.h.

## ◆ CLK_CLKSEL2_UART1SEL_MIRC

#define CLK_CLKSEL2_UART1SEL_MIRC (0x4UL<<CLK_CLKSEL2_UART1SEL_Pos)

Select UART1 clock source from medium speed oscillator

Definition at line 194 of file clk.h.

## ◆ CLK_CLKSEL2_UART1SEL_PLL

#define CLK_CLKSEL2_UART1SEL_PLL (0x2UL<<CLK_CLKSEL2_UART1SEL_Pos)

Select UART1 clock source from PLL

Definition at line 192 of file clk.h.

## ◆ CLK_CLKSTATUS_CLK_SW_FAIL

#define CLK_CLKSTATUS_CLK_SW_FAIL ((uint32_t)0x00000080)

Clock switch fail flag

Definition at line 96 of file clk.h.

## ◆ CLK_CLKSTATUS_HIRC0_STB

#define CLK_CLKSTATUS_HIRC0_STB ((uint32_t)0x00000010)

Internal high speed oscillator 0 clock source stable flag

Definition at line 93 of file clk.h.

## ◆ CLK_CLKSTATUS_HIRC1_STB

#define CLK_CLKSTATUS_HIRC1_STB ((uint32_t)0x00000020)

Internal high speed oscillator 1 clock source stable flag

Definition at line 94 of file clk.h.

## ◆ CLK_CLKSTATUS_HXT_STB

#define CLK_CLKSTATUS_HXT_STB ((uint32_t)0x00000001)

External high speed crystal clock source stable flag

Definition at line 89 of file clk.h.

## ◆ CLK_CLKSTATUS_LIRC_STB

#define CLK_CLKSTATUS_LIRC_STB ((uint32_t)0x00000008)

Internal low speed oscillator clock source stable flag

Definition at line 92 of file clk.h.

## ◆ CLK_CLKSTATUS_LXT_STB

#define CLK_CLKSTATUS_LXT_STB ((uint32_t)0x00000002)

External low speed crystal clock source stable flag

Definition at line 90 of file clk.h.

## ◆ CLK_CLKSTATUS_MIRC_STB

#define CLK_CLKSTATUS_MIRC_STB ((uint32_t)0x00000040)

Internal medium speed oscillator clock source stable flag

Definition at line 95 of file clk.h.

## ◆ CLK_CLKSTATUS_PLL_STB

#define CLK_CLKSTATUS_PLL_STB ((uint32_t)0x00000004)

Internal PLL clock source stable flag

Definition at line 91 of file clk.h.

## ◆ CLK_HCLK_CLK_DIVIDER

#define CLK_HCLK_CLK_DIVIDER | ( |  | x | ) | ((((uint32_t)x-1)<<CLK_CLKDIV0_HCLKDIV_Pos) & CLK_CLKDIV0_HCLKDIV_Msk) /* CLKDIV0 Setting for HCLK clock divider. It could be 1~16*/

Definition at line 246 of file clk.h.

## ◆ CLK_PLL_MLP

#define CLK_PLL_MLP | ( |  | x | ) | ((x)<<0)

PLL Multiple

Definition at line 105 of file clk.h.

## ◆ CLK_PLL_SRC_N

#define CLK_PLL_SRC_N | ( |  | x | ) | (((x)-1)<<8)

PLL Input Source Divider

Definition at line 104 of file clk.h.

## ◆ CLK_PLLCTL_16MHz_HIRC0

#define CLK_PLLCTL_16MHz_HIRC0 (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLL_SRC_N(12) | CLK_PLL_MLP(16))

Predefined PLLCTL setting for 16MHz PLL output with 12MHz HIRC0

Definition at line 121 of file clk.h.

## ◆ CLK_PLLCTL_16MHz_HIRC1

#define CLK_PLLCTL_16MHz_HIRC1 (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLL_SRC_N(36) | CLK_PLL_MLP(16))

Predefined PLLCTL setting for 16MHz PLL output with 36MHz HIRC1

Definition at line 128 of file clk.h.

## ◆ CLK_PLLCTL_16MHz_MIRC

#define CLK_PLLCTL_16MHz_MIRC (CLK_PLLCTL_PLL_SRC_MIRC | CLK_PLL_SRC_N(4) | CLK_PLL_MLP(16))

Predefined PLLCTL setting for 16MHz PLL output with 4MHz MIRC

Definition at line 135 of file clk.h.

## ◆ CLK_PLLCTL_22MHz_HIRC0

#define CLK_PLLCTL_22MHz_HIRC0 (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLL_SRC_N(12) | CLK_PLL_MLP(22))

Predefined PLLCTL setting for 22MHz PLL output with 12MHz HIRC0

Definition at line 120 of file clk.h.

## ◆ CLK_PLLCTL_22MHz_HIRC1

#define CLK_PLLCTL_22MHz_HIRC1 (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLL_SRC_N(36) | CLK_PLL_MLP(22))

Predefined PLLCTL setting for 22MHz PLL output with 36MHz HIRC1

Definition at line 127 of file clk.h.

## ◆ CLK_PLLCTL_22MHz_MIRC

#define CLK_PLLCTL_22MHz_MIRC (CLK_PLLCTL_PLL_SRC_MIRC | CLK_PLL_SRC_N(4) | CLK_PLL_MLP(22))

Predefined PLLCTL setting for 22MHz PLL output with 4MHz MIRC

Definition at line 134 of file clk.h.

## ◆ CLK_PLLCTL_24MHz_HIRC0

#define CLK_PLLCTL_24MHz_HIRC0 (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLL_SRC_N(12) | CLK_PLL_MLP(24))

Predefined PLLCTL setting for 24MHz PLL output with 12MHz HIRC0

Definition at line 119 of file clk.h.

## ◆ CLK_PLLCTL_24MHz_HIRC1

#define CLK_PLLCTL_24MHz_HIRC1 (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLL_SRC_N(36) | CLK_PLL_MLP(24))

Predefined PLLCTL setting for 24MHz PLL output with 36MHz HIRC1

Definition at line 126 of file clk.h.

## ◆ CLK_PLLCTL_24MHz_MIRC

#define CLK_PLLCTL_24MHz_MIRC (CLK_PLLCTL_PLL_SRC_MIRC | CLK_PLL_SRC_N(4) | CLK_PLL_MLP(24))

Predefined PLLCTL setting for 24MHz PLL output with 4MHz MIRC

Definition at line 133 of file clk.h.

## ◆ CLK_PLLCTL_28MHz_HIRC0

#define CLK_PLLCTL_28MHz_HIRC0 (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLL_SRC_N(12) | CLK_PLL_MLP(28))

Predefined PLLCTL setting for 28MHz PLL output with 12MHz HIRC0

Definition at line 118 of file clk.h.

## ◆ CLK_PLLCTL_28MHz_HIRC1

#define CLK_PLLCTL_28MHz_HIRC1 (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLL_SRC_N(36) | CLK_PLL_MLP(28))

Predefined PLLCTL setting for 28MHz PLL output with 36MHz HIRC1

Definition at line 125 of file clk.h.

## ◆ CLK_PLLCTL_28MHz_MIRC

#define CLK_PLLCTL_28MHz_MIRC (CLK_PLLCTL_PLL_SRC_MIRC | CLK_PLL_SRC_N(4) | CLK_PLL_MLP(28))

Predefined PLLCTL setting for 28MHz PLL output with 4MHz MIRC

Definition at line 132 of file clk.h.

## ◆ CLK_PLLCTL_32MHz_HIRC0

#define CLK_PLLCTL_32MHz_HIRC0 (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLL_SRC_N(12) | CLK_PLL_MLP(32))

Predefined PLLCTL setting for 32MHz PLL output with 12MHz HIRC0

Definition at line 117 of file clk.h.

## ◆ CLK_PLLCTL_32MHz_HIRC1

#define CLK_PLLCTL_32MHz_HIRC1 (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLL_SRC_N(36) | CLK_PLL_MLP(32))

Predefined PLLCTL setting for 32MHz PLL output with 36MHz HIRC1

Definition at line 124 of file clk.h.

## ◆ CLK_PLLCTL_32MHz_MIRC

#define CLK_PLLCTL_32MHz_MIRC (CLK_PLLCTL_PLL_SRC_MIRC | CLK_PLL_SRC_N(4) | CLK_PLL_MLP(32))

Predefined PLLCTL setting for 32MHz PLL output with 4MHz MIRC

Definition at line 131 of file clk.h.

## ◆ CLK_PLLCTL_36MHz_HIRC0

#define CLK_PLLCTL_36MHz_HIRC0 (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLL_SRC_N(12) | CLK_PLL_MLP(36))

Predefined PLLCTL setting for 36MHz PLL output with 12MHz HIRC0

Definition at line 116 of file clk.h.

## ◆ CLK_PLLCTL_36MHz_HIRC1

#define CLK_PLLCTL_36MHz_HIRC1 (CLK_PLLCTL_PLL_SRC_HIRC | CLK_PLL_SRC_N(36) | CLK_PLL_MLP(36))

Predefined PLLCTL setting for 36MHz PLL output with 36MHz HIRC1

Definition at line 123 of file clk.h.

## ◆ CLK_PLLCTL_36MHz_MIRC

#define CLK_PLLCTL_36MHz_MIRC (CLK_PLLCTL_PLL_SRC_MIRC | CLK_PLL_SRC_N(4) | CLK_PLL_MLP(36))

Predefined PLLCTL setting for 36MHz PLL output with 4MHz MIRC

Definition at line 130 of file clk.h.

## ◆ CLK_PLLCTL_PD

#define CLK_PLLCTL_PD ((uint32_t)0x00010000)

PLL Power down mode

Definition at line 99 of file clk.h.

## ◆ CLK_PLLCTL_PLL_SRC_HIRC

#define CLK_PLLCTL_PLL_SRC_HIRC ((uint32_t)(0x00020000))

For PLL clock source is HIRC

Definition at line 101 of file clk.h.

## ◆ CLK_PLLCTL_PLL_SRC_HXT

#define CLK_PLLCTL_PLL_SRC_HXT ((uint32_t)(0x00000000))

For PLL clock source is HXT

Definition at line 100 of file clk.h.

## ◆ CLK_PLLCTL_PLL_SRC_MIRC

#define CLK_PLLCTL_PLL_SRC_MIRC ((uint32_t)(0x00040000))

For PLL clock source is MIRC

Definition at line 102 of file clk.h.

## ◆ CLK_PWRCTL_DELY_EN

#define CLK_PWRCTL_DELY_EN ((uint32_t)0x00000010)

Enable the wake-up delay counter

Definition at line 42 of file clk.h.

## ◆ CLK_PWRCTL_HIRC0_EN

#define CLK_PWRCTL_HIRC0_EN ((uint32_t)0x00000004)

Enable internal high speed oscillator 0

Definition at line 40 of file clk.h.

## ◆ CLK_PWRCTL_HIRC1_EN

#define CLK_PWRCTL_HIRC1_EN ((uint32_t)0x01000000)

Enable internal high speed oscillator 1

Definition at line 46 of file clk.h.

## ◆ CLK_PWRCTL_HXT_EN

#define CLK_PWRCTL_HXT_EN ((uint32_t)0x00000001)

Enable high speed crystal

Definition at line 38 of file clk.h.

## ◆ CLK_PWRCTL_HXT_GAIN_12M_16M

#define CLK_PWRCTL_HXT_GAIN_12M_16M ((uint32_t)0x00000C00)

High frequency crystal Gain control is from 12 MHz to 16 MHz

Definition at line 53 of file clk.h.

## ◆ CLK_PWRCTL_HXT_GAIN_16M_24M

#define CLK_PWRCTL_HXT_GAIN_16M_24M ((uint32_t)0x00001000)

High frequency crystal Gain control is from 16 MHz to 24 MHz

Definition at line 54 of file clk.h.

## ◆ CLK_PWRCTL_HXT_GAIN_24M_32M

#define CLK_PWRCTL_HXT_GAIN_24M_32M ((uint32_t)0x00001400)

High frequency crystal Gain control is from 24 MHz to 32 MHz

Definition at line 55 of file clk.h.

## ◆ CLK_PWRCTL_HXT_GAIN_32M_36M

#define CLK_PWRCTL_HXT_GAIN_32M_36M ((uint32_t)0x00001800)

High frequency crystal Gain control is from 32 MHz to 36 MHz

Definition at line 56 of file clk.h.

## ◆ CLK_PWRCTL_HXT_GAIN_36M

#define CLK_PWRCTL_HXT_GAIN_36M ((uint32_t)0x00001C00)

High frequency crystal Gain control is higher than 36 MHz

Definition at line 57 of file clk.h.

## ◆ CLK_PWRCTL_HXT_GAIN_4M

#define CLK_PWRCTL_HXT_GAIN_4M ((uint32_t)0x00000000)

High frequency crystal Gain control is lower than from 4 MHz

Definition at line 50 of file clk.h.

## ◆ CLK_PWRCTL_HXT_GAIN_4M_8M

#define CLK_PWRCTL_HXT_GAIN_4M_8M ((uint32_t)0x00000400)

High frequency crystal Gain control is from 4 MHz to 8 MHz

Definition at line 51 of file clk.h.

## ◆ CLK_PWRCTL_HXT_GAIN_8M_12M

#define CLK_PWRCTL_HXT_GAIN_8M_12M ((uint32_t)0x00000800)

High frequency crystal Gain control is from 8 MHz to 12 MHz

Definition at line 52 of file clk.h.

## ◆ CLK_PWRCTL_HXT_HXTSLTYP

#define CLK_PWRCTL_HXT_HXTSLTYP ((uint32_t)0x00000100)

High frequency crystal loop back path Enabled

Definition at line 45 of file clk.h.

## ◆ CLK_PWRCTL_HXT_SELXT

#define CLK_PWRCTL_HXT_SELXT ((uint32_t)0x00000100)

High frequency crystal loop back path Enabled

Definition at line 48 of file clk.h.

## ◆ CLK_PWRCTL_LIRC_EN

#define CLK_PWRCTL_LIRC_EN ((uint32_t)0x00000008)

Enable internal low speed oscillator

Definition at line 41 of file clk.h.

## ◆ CLK_PWRCTL_LXT_EN

#define CLK_PWRCTL_LXT_EN ((uint32_t)0x00000002)

Enable low speed crystal

Definition at line 39 of file clk.h.

## ◆ CLK_PWRCTL_MIRC_EN

#define CLK_PWRCTL_MIRC_EN ((uint32_t)0x02000000)

Enable internal medium speed oscillator

Definition at line 47 of file clk.h.

## ◆ CLK_PWRCTL_PWRDOWN_EN

#define CLK_PWRCTL_PWRDOWN_EN ((uint32_t)0x00000040)

Power down enable bit

Definition at line 44 of file clk.h.

## ◆ CLK_PWRCTL_WAKEINT_EN

#define CLK_PWRCTL_WAKEINT_EN ((uint32_t)0x00000020)

Enable the wake-up interrupt

Definition at line 43 of file clk.h.

## ◆ CLK_SC0_CLK_DIVIDER

#define CLK_SC0_CLK_DIVIDER | ( |  | x | ) | ((((uint32_t)x-1)<<CLK_CLKDIV0_SC0DIV_Pos) & CLK_CLKDIV0_SC0DIV_Msk) /* CLKDIV0 Setting for SC0 clock divider. It could be 1~16*/

Definition at line 254 of file clk.h.

## ◆ CLK_SC1_CLK_DIVIDER

#define CLK_SC1_CLK_DIVIDER | ( |  | x | ) | ((((uint32_t)x-1)<<CLK_CLKDIV1_SC1DIV_Pos) & CLK_CLKDIV1_SC1DIV_Msk) /* CLKDIV1 Setting for SC1 clock divider. It could be 1~16*/

Definition at line 255 of file clk.h.

## ◆ CLK_TMR0_CLK_DIVIDER

#define CLK_TMR0_CLK_DIVIDER | ( |  | x | ) | ((((uint32_t)x-1)<<CLK_CLKDIV1_TMR0DIV_Pos) & CLK_CLKDIV1_TMR0DIV_Msk) /* CLKDIV1 Setting for TMR0 clock divider. It could be 1~16*/

Definition at line 248 of file clk.h.

## ◆ CLK_TMR1_CLK_DIVIDER

#define CLK_TMR1_CLK_DIVIDER | ( |  | x | ) | ((((uint32_t)x-1)<<CLK_CLKDIV1_TMR1DIV_Pos) & CLK_CLKDIV1_TMR1DIV_Msk) /* CLKDIV1 Setting for TMR1 clock divider. It could be 1~16*/

Definition at line 249 of file clk.h.

## ◆ CLK_TMR2_CLK_DIVIDER

#define CLK_TMR2_CLK_DIVIDER | ( |  | x | ) | ((((uint32_t)x-1)<<CLK_CLKDIV1_TMR2DIV_Pos) & CLK_CLKDIV1_TMR2DIV_Msk) /* CLKDIV1 Setting for TMR2 clock divider. It could be 1~16*/

Definition at line 252 of file clk.h.

## ◆ CLK_TMR3_CLK_DIVIDER

#define CLK_TMR3_CLK_DIVIDER | ( |  | x | ) | ((((uint32_t)x-1)<<CLK_CLKDIV1_TMR3DIV_Pos) & CLK_CLKDIV1_TMR3DIV_Msk) /* CLKDIV1 Setting for TMR3 clock divider. It could be 1~16*/

Definition at line 253 of file clk.h.

## ◆ CLK_UART0_CLK_DIVIDER

#define CLK_UART0_CLK_DIVIDER | ( |  | x | ) | ((((uint32_t)x-1)<<CLK_CLKDIV0_UART0DIV_Pos)& CLK_CLKDIV0_UART0DIV_Msk) /* CLKDIV0 Setting for UART0 clock divider. It could be 1~16*/

Definition at line 247 of file clk.h.

## ◆ CLK_UART1_CLK_DIVIDER

#define CLK_UART1_CLK_DIVIDER | ( |  | x | ) | ((((uint32_t)x-1)<<CLK_CLKDIV0_UART1DIV_Pos)& CLK_CLKDIV0_UART1DIV_Msk) /* CLKDIV0 Setting for UART1 clock divider. It could be 1~16*/

Definition at line 251 of file clk.h.

## ◆ CLK_WK_INTSTS_IS

#define CLK_WK_INTSTS_IS ((uint32_t)0x00000001)

Wake-up Interrupt Status in chip Power-down Mode

Definition at line 265 of file clk.h.

## ◆ CLKO_MODULE

#define CLKO_MODULE

CLKO Module

Definition at line 306 of file clk.h.

## ◆ FREQ_16MHZ

#define FREQ_16MHZ 16000000

Definition at line 35 of file clk.h.

## ◆ FREQ_36MHZ

#define FREQ_36MHZ 36000000

Definition at line 34 of file clk.h.

## ◆ GPIO_MODULE

#define GPIO_MODULE

GPIO Module

Definition at line 294 of file clk.h.

## ◆ I2C0_MODULE

#define I2C0_MODULE

I2C0 Module

Definition at line 307 of file clk.h.

## ◆ I2C1_MODULE

#define I2C1_MODULE

I2C1 Module

Definition at line 308 of file clk.h.

## ◆ ISP_MODULE

#define ISP_MODULE

ISP Module

Definition at line 296 of file clk.h.

## ◆ MODULE_APBCLK

#define MODULE_APBCLK | ( |  | x | ) | ((x >>31) & 0x1)

Calculate APBCLK offset on MODULE index

Definition at line 271 of file clk.h.

## ◆ MODULE_APBCLK_ENC

#define MODULE_APBCLK_ENC | ( |  | x | ) | (((x) & 0x01) << 31)

MODULE index, 0x0:AHBCLK, 0x1:APBCLK

Definition at line 282 of file clk.h.

## ◆ MODULE_CLKDIV

#define MODULE_CLKDIV | ( |  | x | ) | ((x >>18) & 0x3)

Calculate APBCLK CLKDIV on MODULE index

Definition at line 275 of file clk.h.

## ◆ MODULE_CLKDIV_ENC

#define MODULE_CLKDIV_ENC | ( |  | x | ) | (((x) & 0x03) << 18)

APBCLK CLKDIV on MODULE index, 0x0:CLKDIV

Definition at line 286 of file clk.h.

## ◆ MODULE_CLKDIV_Msk

#define MODULE_CLKDIV_Msk | ( |  | x | ) | ((x >>10) & 0xff)

Calculate CLKDIV mask offset on MODULE index

Definition at line 276 of file clk.h.

## ◆ MODULE_CLKDIV_Msk_ENC

#define MODULE_CLKDIV_Msk_ENC | ( |  | x | ) | (((x) & 0xff) << 10)

CLKDIV mask offset on MODULE index

Definition at line 287 of file clk.h.

## ◆ MODULE_CLKDIV_Pos

#define MODULE_CLKDIV_Pos | ( |  | x | ) | ((x >>5 ) & 0x1f)

Calculate CLKDIV position offset on MODULE index

Definition at line 277 of file clk.h.

## ◆ MODULE_CLKDIV_Pos_ENC

#define MODULE_CLKDIV_Pos_ENC | ( |  | x | ) | (((x) & 0x1f) << 5)

CLKDIV position offset on MODULE index

Definition at line 288 of file clk.h.

## ◆ MODULE_CLKSEL

#define MODULE_CLKSEL | ( |  | x | ) | ((x >>29) & 0x3)

Calculate CLKSEL offset on MODULE index

Definition at line 272 of file clk.h.

## ◆ MODULE_CLKSEL_ENC

#define MODULE_CLKSEL_ENC | ( |  | x | ) | (((x) & 0x03) << 29)

CLKSEL offset on MODULE index, 0x0:CLKSEL0, 0x1:CLKSEL1 0x3 CLKSEL2

Definition at line 283 of file clk.h.

## ◆ MODULE_CLKSEL_Msk

#define MODULE_CLKSEL_Msk | ( |  | x | ) | ((x >>25) & 0xf)

Calculate CLKSEL mask offset on MODULE index

Definition at line 273 of file clk.h.

## ◆ MODULE_CLKSEL_Msk_ENC

#define MODULE_CLKSEL_Msk_ENC | ( |  | x | ) | (((x) & 0x0f) << 25)

CLKSEL mask offset on MODULE index

Definition at line 284 of file clk.h.

## ◆ MODULE_CLKSEL_Pos

#define MODULE_CLKSEL_Pos | ( |  | x | ) | ((x >>20) & 0x1f)

Calculate CLKSEL position offset on MODULE index

Definition at line 274 of file clk.h.

## ◆ MODULE_CLKSEL_Pos_ENC

#define MODULE_CLKSEL_Pos_ENC | ( |  | x | ) | (((x) & 0x1f) << 20)

CLKSEL position offset on MODULE index

Definition at line 285 of file clk.h.

## ◆ MODULE_IP_EN_Pos

#define MODULE_IP_EN_Pos | ( |  | x | ) | ((x >>0 ) & 0x1f)

Calculate APBCLK offset on MODULE index

Definition at line 278 of file clk.h.

## ◆ MODULE_IP_EN_Pos_ENC

#define MODULE_IP_EN_Pos_ENC | ( |  | x | ) | (((x) & 0x1f) << 0)

APBCLK offset on MODULE index

Definition at line 289 of file clk.h.

## ◆ MODULE_NoMsk

#define MODULE_NoMsk 0x0

Not mask on MODULE index

Definition at line 279 of file clk.h.

## ◆ NA

#define NA MODULE_NoMsk

Not Available

Definition at line 280 of file clk.h.

## ◆ PDMA_MODULE

#define PDMA_MODULE

PDMA Module

Definition at line 295 of file clk.h.

## ◆ PWM0_MODULE

#define PWM0_MODULE

PWM0 Module

Definition at line 316 of file clk.h.

## ◆ RTC_MODULE

#define RTC_MODULE

RTC Module

Definition at line 301 of file clk.h.

## ◆ SC0_MODULE

#define SC0_MODULE

SC0 Module

Definition at line 318 of file clk.h.

## ◆ SC1_MODULE

#define SC1_MODULE

SC1 Module

Definition at line 319 of file clk.h.

## ◆ SPI0_MODULE

#define SPI0_MODULE

SPI0 Module

Definition at line 310 of file clk.h.

## ◆ SPI1_MODULE

#define SPI1_MODULE

SPI1 Module

Definition at line 311 of file clk.h.

## ◆ SPI2_MODULE

#define SPI2_MODULE

SPI2 Module

Definition at line 312 of file clk.h.

## ◆ SPI3_MODULE

#define SPI3_MODULE

SPI3 Module

Definition at line 313 of file clk.h.

## ◆ SRAM_MODULE

#define SRAM_MODULE

SRAM Module

Definition at line 297 of file clk.h.

## ◆ STC_MODULE

#define STC_MODULE

STC Module

Definition at line 298 of file clk.h.

## ◆ TMR0_MODULE

#define TMR0_MODULE

TMR0 Module

Definition at line 302 of file clk.h.

## ◆ TMR1_MODULE

#define TMR1_MODULE

TMR1 Module

Definition at line 303 of file clk.h.

## ◆ TMR2_MODULE

#define TMR2_MODULE

TMR2 Module

Definition at line 304 of file clk.h.

## ◆ TMR3_MODULE

#define TMR3_MODULE

TMR3 Module

Definition at line 305 of file clk.h.

## ◆ UART0_MODULE

#define UART0_MODULE

UART0 Module

Definition at line 314 of file clk.h.

## ◆ UART1_MODULE

#define UART1_MODULE

UART1 Module

Definition at line 315 of file clk.h.

## ◆ WDT_MODULE

#define WDT_MODULE

WDT Module

Definition at line 299 of file clk.h.

## ◆ WWDT_MODULE

#define WWDT_MODULE

WWDT Module

Definition at line 300 of file clk.h.