| Nano103 BSP V3.01.002 The Board Support Package for Nano103 Series

Data Fields
TIMER_T Struct Reference

`#include <Nano103.h>`

## Data Fields
__IO uint32_t | CTL
__IO uint32_t | PRECNT
__IO uint32_t | CMP
__IO uint32_t | INTEN
__IO uint32_t | INTSTS
__IO uint32_t | CNT
__I uint32_t | CAP
__IO uint32_t | ECTL

## Detailed Description

    @addtogroup TMR Timer Controller(TMR)
    Memory Mapped Structure for TMR Controller

Definition at line 13684 of file Nano103.h.

## Field Documentation

## ◆ CAP

TIMER_T::CAP

[0x0018] Timer Capture Data Register

CAP

Offset: 0x18 Timer Capture Data Register

Bits | Field | Descriptions
[23:0] | CAPDAT | Timer Capture Data Register When CAPEN (TIMERx_CTL[16]) bit is set, CAPFUNCS (TIMERx_CTL[17]) bit is 0, CAPCNTMD (TIMERx_CTL[20]) bit is 0, and the transition on Tx_EXT pin matched the CAPEDGE (TIMERx_CTL[19:18]) setting, CAPIF (TIMERx_INTSTS[1]) will set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field. When CAPEN (TIMERx_CTL[16]) bit is set, CAPFUNCS (TIMERx_CTL[17]) bit is 0, CAPCNTMD (TIMERx_CTL[20]) bit is 1, and the transition on Tx_EXT pin matched the 2nd transition of CAPEDGE (TIMERx_CTL[19:18]) setting, CAPIF (TIMERx_INTSTS[1]) will set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field. Note: When edge transition defined by CAPEDGE (TIMERx_CTL[19:18]) is detected on Tx_EXT (x = 0 ~ 3) before CPU clears the CAPIF (TIMERxISR[1]) status, the timer keeps this value unchanged and CAPDATOF (TIMERx_INTSTS[5]) is set to 1.

Definition at line 14233 of file Nano103.h.

## ◆ CMP

TIMER_T::CMP

[0x0008] Timer Compare Register

CMP

Offset: 0x08 Timer Compare Register

Bits | Field | Descriptions
[23:0] | CMPDAT | Timer Compared Value CMPDAT is a 24-bit compared value register When the internal 24-bit up counter value is equal to CMPDAT value, the CNTIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will be set to 1. Time-out period = (Period of timer clock input) * (8-bit PSC + 1) * (24-bit CMPDAT). Note1: Never write 0x0 or 0x1 in CMPDAT, or the core will run into unknown state. Note2: When the timer is operating in Continuous Counting mode (OPMODE (TIMERx_CTL[5:4] is 11), the 24-bit up counter will keep counting continuously even if user writes a new value into CMPDAT field. Note3: When the timer is not operating in Continuous Counting mode (OPMODE (TIMERx_CTL[5:4] is not 11), the 24-bit up counter will restart counting from 0 and use the newest CMPDAT value as the timer compared value when user writes a new value into the CMPDAT field In addition, the prescale counter will be reloaded.

Definition at line 14229 of file Nano103.h.

## ◆ CNT

TIMER_T::CNT

[0x0014] Timer Counter Data Register

CNT

Offset: 0x14 Timer Counter Data Register

Bits | Field | Descriptions
[23:0] | CNT | Timer Counter Data (Read) This field can reflect the internal 24-bit timer counter value or external event input counter value from Tx (x=0~3) pin. Counter Reset (Write) User can write any value to TIEMRx_CNT to reset internal 24-bit timer up-counter and 8-bit pre-scale counter This reset operation wouldn't affect any other timer control registers and circuit After reset completed, the 24-bit timer up-counter and 8-bit pre-scale counter restart the counting based on the TIMERx_CTL register setting.
[31] | RSTACT | Reset Active This bit indicates if the counter reset operation active. When user write this register, timer starts to reset its internal 24-bit timer up-counter and 8-bit pre-scale counter to 0 At the same time, timer set this flag to 1 to indicate the counter reset operation is in progress Once the counter reset operation done, timer clear this bit to 0 automatically. 0 = Reset operation is done. 1 = Reset operation triggered by writing TIMERx_CNT is in progress. Note: This bit is read only. Write operation wouldn't take any effect.

Definition at line 14232 of file Nano103.h.

## ◆ CTL

TIMER_T::CTL

[0x0000] Timer Control and Status Register

CTL

Offset: 0x00 Timer Control and Status Register

Bits | Field | Descriptions
[0] | CNTEN | Timer Counting Enable Bit 0 = Stops/Suspends counting. 1 = Starts counting. Note1: In stop status, set CNTEN to 1 enables 24-bit counter keeps up counting from the last stop counting value. Note2: This bit is auto-cleared by hardware in one-shot mode (OPMODE (TIMERx_CTL[5:4]) = 00) when the timer interrupt flag TIF (TIMERx_INTSTS[0]) is generated. Note3: Writing this bit 1 will not take any effect if RSTCNT (TIMERx_CTL[1]) is also set to 1 at the same time.
[1] | RSTCNT | Timer Counter Reset Bit Setting this bit will reset the internal 8-bit prescale counter, 24-bit up counter value CNT (TIMERx_CNT[23:0]) and also force CNTEN (TIMERx_CTL[0]) to 0. 0 = No effect. 1 = Reset internal 8-bit prescale counter, 24-bit up counter value and CNTEN bit. Note: This bit will be auto cleared and takes at least 3 TIMERx_CLK clock cycles.
[2] | WKEN | Wake-up Function Enable Bit If this bit is set to 1, while CNTIF (TIMERx_INTSTS[0]) or CAPIF (TIMERx_INTSTS[1]) is 1, the timer interrupt signal will generate a wake-up trigger event to CPU. 0 = Wake-up function Disabled if timer interrupt signal generated. 1 = Wake-up function Enabled if timer interrupt signal generated.
[3] | ICEDEBUG | ICE Debug Mode Acknowledge Disable Bit 0 = ICE debug mode acknowledgement affects TIMER counting. Timer counter will be held while CPU is held by ICE. 1 = ICE debug mode acknowledgement Disabled. Timer counter will keep going no matter CPU is held by ICE or not.
[5:4] | OPMODE | Timer Counting Mode Selection 00 = The Timer controller is operated in One-shot mode. 01 = The Timer controller is operated in Periodic mode. 10 = The Timer controller is operated in Toggle-output mode. 11 = The Timer controller is operated in Continuous Counting mode.
[7] | ACTSTS | Timer Active Status Bit (Read Only) This bit indicates the 24-bit up counter status. 0 = 24-bit up counter is not active. 1 = 24-bit up counter is active.
[8] | TRGADC | Trigger ADC Enable Bit If this bit is set to 1, timer time-out interrupt or capture interrupt can trigger ADC. 0 = Timer interrupt trigger ADC Disabled. 1 = Timer interrupt trigger ADC Enabled. Note: If TRGSSEL (TIMERx_CTL[11]) is set to 0, the time-out interrupt signal will trigger ADC. If TRGSSEL (TIMERx_CTL[11]) is set to 1, the capture interrupt signal will trigger ADC.
[10] | TRGPDMA | Timer Trigger PDMA Enable Bit If this bit is set to 1, timer time-out interrupt or capture interrupt can trigger PDMA. 0 = Timer interrupt trigger PWM Disabled. 1 = Timer interrupt trigger PWM Enabled. Note: If TRGSSEL (TIMERx_CTL[11]) is set to 0, the time-out interrupt signal will trigger PWM. If TRGSSEL (TIMERx_CTL[11]) is set to 1, the capture interrupt signal will trigger PWM.
[11] | TRGSSEL | Trigger Source Selection If this bit is set to 1, capture interrupt can trigger ADC, PDMA and PWM Otherwise, time-out interrupt can trigger ADC, PDMA and PWM. 0 = Time-out interrupt is used to trigger ADC, PDMA and PWM. 1 = Capture interrupt is used to trigger ADC, PDMA and PWM.
[12] | EXTCNTEN | Event Counter Mode Enable Bit This bit is for external counting pin function enabled. 0 = Event counter mode Disabled. 1 = Event counter mode Enabled. Note: When timer is used as an event counter, this bit should be set to 1 and HCLK as timer clock source.
[13] | CNTPHASE | Timer External Count Phase This bit indicates the detection phase of external counting pin Tx (x= 0~3). 0 = A Falling edge of external counting pin will be counted. 1 = A Rising edge of external counting pin will be counted.
[14] | CNTDBEN | Timer Counter Pin De-bounce Enable Bit 0 = Tx (x= 0~3) pin de-bounce Disabled. 1 = Tx (x= 0~3) pin de-bounce Enabled. Note: If this bit is set to 1, the edge detection of Tx pin is detected with de-bounce circuit.
[16] | CAPEN | Timer External Capture Pin Enable Bit This bit enables the Tx_EXT pin. 0 = Tx_EXT (x= 0~3) pin Disabled. 1 = Tx_EXT (x= 0~3) pin Enabled. Note1: For TIMERx_CTL, if INTRTGEN (TIMERx_CTL[24]) is set to 1, the CAPEN will be forced to low and the TC pin transition is ignored (where x = 0 or 2). Note2: For TIMERx+1_CTL, if INTRTGEN (TIMERx_CTL[24]) is set to 1, the CAPEN will be forced to high (where x = 0 or 2).
[17] | CAPFUNCS | Capture Function Selection 0 = External Capture Mode Enabled. 1 = External Reset Mode Enabled. Note1: When CAPFUNCS is 0, transition on Tx_EXT (x= 0~3) pin is using to save the 24-bit timer counter value. Note2: When CAPFUNCS is 1, transition on Tx_EXT (x= 0~3) pin is using to reset the 24-bit timer counter value. Note3: For TIMERx+1_CTL (x = 0 or 2), if INTRTGEN (TIMERx_CTL[24]) is set to 1, the CAPFUNCS will be forced to low.
[19:18] | CAPEDGE | Timer External Capture Pin Edge Detection For timer counter reset function and free-counting mode of timer capture function, the configurations are: 00 = A Falling edge on Tx_EXT (x= 0~3) pin will be detected. 01 = A Rising edge on Tx_EXT (x= 0~3) pin will be detected. 10 = Either Rising or Falling edge on Tx_EXT (x= 0~3) pin will be detected. 11 = Either Rising or Falling edge on Tx_EXT (x= 0~3) pin will be detected. For trigger-counting mode of timer capture function, the configurations are: 00 = 1st falling edge on TC pin triggers 24-bit timer to start counting, while 2nd falling edge triggers 24-bit timer to stop counting. 01 = 1st rising edge on TC pin triggers 24-bit timer to start counting, while 2nd rising edge triggers 24-bit timer to stop counting. 10 = Falling edge on TC pin triggers 24-bit timer to start counting, while rising edge triggers 24-bit timer to stop counting. 11 = Rising edge on TC pin triggers 24-bit timer to start counting, while falling edge triggers 24-bit timer to stop counting. Note: For TIMERx+1_CTL, if INTRTGEN (TIMERx_CTL[24]) is set to 1, the CAPEDGE will be forced to 11 (where x = 0 or 2).
[20] | CAPCNTMD | Timer Capture Counting Mode Selection This bit indicates the behavior of 24-bit up-counting timer while CAPEN (TIMERx_CTL[16]) is set to high. If this bit is 0, the free-counting mode, the behavior of 24-bit up-counting timer is defined by OPMODE (TIMERx_CTL[5:4]) field When CAPEN (TIMERx_CTL[16]) is set, CAPFUNCS (TIMERx_CTL[17]) is 0, and the transition of TC pin matches the CAPEDGE (TIMERx_CTL[19:18]) setting, the value of 24-bit up-counting timer will be saved into register TIMERx_CAP. If this bit is 1, Trigger-counting mode, 24-bit up-counting timer will be not counting and keep its value at 0 When CAPEN (TIMERx_CTL[16]) is set, CAPFUNCS (TIMERx_CTL[17]) is 0, and once the transition of external pin matches the 1st transition of CAPEDGE (TIMERx_CTL[19:18]) setting, the 24-bit up-counting timer will start counting And then if the transition of external pin matches the 2nd transition of CAPEDGE (TIMERx_CTL[19:18]) setting, the 24-bit up-counting timer will stop counting And its value will be saved into register TIMERx_CAP. 0 = Capture with free-counting timer mode. 1 = Capture with trigger-counting timer mode. Note: For TIMERx+1_CTL, if INTRTGEN (TIMERx_CTL[24]) is set, the CAPCNTMD will be forced to high, the capture with Trigger-counting Timer mode (where x = 0 or 2).
[22] | CAPDBEN | Timer External Capture Pin De-bounce Enable Bit 0 = Tx_EXT (x= 0~3) pin de-bounce Disabled. 1 = Tx_EXT (x= 0~3) pin de-bounce Enabled. Note1: If this bit is enabled, the edge detection of Tx_EXT pin is detected with de-bounce circuit. Note2: For Timer 1 and 3, when INTRTGEN (TIMERx_CTL[24]) is high, the capture signal is from internal of chip and the de-bounce circuit would not take effect no matter this bit is high or low.
[23] | CMPCTL | Timer Compared Mode Selection 0 = The behavior selection in one-shot, periodic or Toggle-output mode Disabled. When user updates CMPDAT (TIMERx_CMP) while timer is running in One-shot, Periodic or Toggle-output mode, CNT (TIMERx_CNT) will be reset to default value. 1 = The behavior selection in one-shot, periodic or Toggle-output mode Enabled. When user updates CMPDAT (TIMERx_CMP) while timer is running in One-shot, Periodic or Toggle-output mode, the limitations as bellows list, If updated CMPDAT (TIMERx_CMP) value > CNT (TIMERx_CNT), CMPDAT (TIMERx_CMP) will be updated and CNT (TIMERx_CNT) keep running continually. If updated CMPDAT (TIMERx_CMP) value = CNT (TIMERx_CNT), timer time-out interrupt will be asserted immediately. If updated CMPDAT (TIMERx_CMP) value < CNT (TIMERx_CNT), CNT (TIMERx_CNT) will be reset to default value At the same time, prescale counter reloaded.
[24] | INTRTGEN | Inter-timer Trigger Function Enable Bit If INTRTGEN is set to 1 TIMERx (x = 0 or 2), TIMERx and Timerx=1 are operating at inter-timer trigger mode. When Inter-timer Trigger function is enabled, TIMERx is operating at event counting mode to count the input event from Tx pin and TIMERx+1 is operating at external capture trigger-counting mode. 0 = Inter-timer trigger function Disabled. 1 = Inter-timer trigger function Enabled. Note: In TIMERx+1_CTL, this bit is always 0.
[25] | INTRTGMD | Inter-timer Trigger Mode Selection This bit controls the TIMERx (x = 0 or 2) operating behavior when INTRTGEN (TIMERx_CTL[24]) is set to 1. If INTRTGMD is set to 0 and INTRTGEN (TIMERx_CTL[24]) is set to 1, the TIMERx is operating at event counting mode to count the all input events from Tx pin. If INTRTGMD and INTRTGEN (TIMERx_CTL[24]) are both set to 1, TIMERx is operating at event counting mode and the number of first incoming events (defined by EVNTDPCNT (TIMERx_ECTL[31:24])) are ignored. 0 = TIMERx count the all input events from Tx pin. 1 = TIMERx ignored the number of first incoming events based on EVNTDPCNT (TIMERx_ECTL[31:24]). Note: In TIMERx+1_CTL, this bit is always 0.
[28] | TRGPWM | Trigger PWM Enable Bit If this bit is set to 1, timer time-out interrupt or capture interrupt can trigger PWM. 0 = Timer interrupt trigger PWM Disabled. 1 = Timer interrupt trigger PWM Enabled. Note: If TRGSSEL (TIMERx_CTL[11]) = 0, time-out interrupt signal will trigger PWM. If TRGSSEL (TIMERx_CTL[11]) = 1, capture interrupt signal will trigger PWM.

Definition at line 14227 of file Nano103.h.

## ◆ ECTL

TIMER_T::ECTL

[0x0020] Timer Extended Control Register

ECTL

Offset: 0x20 Timer Extended Control Register

Bits | Field | Descriptions
[31:24] | EVNTDPCNT | Event Drop Count This field indicates timer how many events dropped after inter-timer trigger function enable. For example, if user configured EVNTDPCNT to 7, timer would drop 7 first incoming events and starts the inter-timer trigger operation when it get 8th event. Note: ECNTDPCNT only takes effect when INTRTGEN (TIMERx_CTL[24]) INTRTGMD (TIMERx_CTL[25]) are both set to 1.

Definition at line 14237 of file Nano103.h.

## ◆ INTEN

TIMER_T::INTEN

[0x000c] Timer Interrupt Enable Register

INTEN

Offset: 0x0C Timer Interrupt Enable Register

Bits | Field | Descriptions
[0] | CNTIEN | Timer Interrupt Enable Bit 0 = Timer Interrupt Disabled. 1 = Timer Interrupt Enabled. Note: If this bit is enabled, when the timer interrupt flag CNTIF (TIMERx_INTSTS[0]) is set to 1, the timer interrupt signal is generated and informed to CPU.
[1] | CAPIEN | Timer External Capture Interrupt Enable Bit 0 = Tx_EXT (x= 0~3) pin detection Interrupt Disabled. 1 = Tx_EXT (x= 0~3) pin detection Interrupt Enabled. Note: CAPIEN is used to enable timer external interrupt If CAPIEN is enabled, the timer will rise an interrupt when CAPIF (TIMERx_INTSTS[1]) is 1.

Definition at line 14230 of file Nano103.h.

## ◆ INTSTS

TIMER_T::INTSTS

[0x0010] Timer Interrupt Status Register

INTSTS

Offset: 0x10 Timer Interrupt Status Register

Bits | Field | Descriptions
[0] | CNTIF | Timer Interrupt Status This bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value. 0 = No effect. 1 = CNT (TIMERx_CNT[23:0]) value matches the CMPDAT (TIMERx_CMP[23:0]) value. Note: This bit is cleared by writing 1 to it.
[1] | CAPIF | Timer External Capture Interrupt Flag This bit indicates the timer external capture interrupt flag status. 0 = Tx_EXT (x= 0~3) pin interrupt did not occur. 1 = Tx_EXT (x= 0~3) pin interrupt occurred. Note1: This bit is cleared by writing 1 to it. Note2: When CAPEN (TIMERx_CTL[16]) bit is set, CAPFUNCS (TIMERx_CTL[17]) bit is 0, and a transition on Tx_EXT (x= 0~3) pin matched the CAPEDGE (TIMERx_CTL[19:18]) setting, this bit will set to 1 by hardware. Note3: If a new incoming capture event detected before CPU clearing the CAPIF status, the Timer will keep register TIMERx_CAP unchanged and drop the new capture value.
[4] | TWKF | Timer Wake-up Flag This bit indicates the interrupt wake-up flag status of timer. 0 = Timer does not cause CPU wake-up. 1 = CPU wake-up from Idle or Power-down mode if timer time-out interrupt signal generated. Note: This bit is cleared by writing 1 to it.
[5] | CAPDATOF | Capture Data Overflow Flag This status is to indicate there is a new incoming capture event detected before CPU clearing the CAPIF (TIMERx_INTSTS[1]) status. If the above condition occurred, the Timer will keep register TIMERx_CAP unchanged and drop the new capture value. 0 = New incoming capture event didnu2019t detect before CPU clearing CAPIF (TIMERx_INTSTS[1]) status. 1 = New incoming capture event detected before CPU clearing CAPIF (TIMERx_INTSTS[1]) status. Note: This bit is cleared by writing 1 to it.
[6] | CAPFEDF | Capture Falling Edge Detected Flag This flag indicates the edge detected on Tx_EXT pin is rising edge or falling edge. 0 = Rising edge detected on Tx_EXT pin. 1 = Falling edge detected on Tx_EXT pin. Note1: The timer updates this flag when it updates the Timer Capture Data (TMR_CAP[23:0]) value. Note2: When a new incoming capture event detected before CPU clearing the CAPIF (TIMERx_INTSTS[1]) status, Timer will keep this bit unchanged.

Definition at line 14231 of file Nano103.h.

## ◆ PRECNT

TIMER_T::PRECNT

[0x0004] Timer Pre-Scale Counter Register

PRECNT

Offset: 0x04 Timer Pre-Scale Counter Register

Bits | Field | Descriptions
[7:0] | PSC | Prescale Counter Timer input clock or event source is divided by (PSC+1) before it is fed to the timer up counter If this field is 0 (PSC = 0), then there is no scaling. Note: If the PSC value is changed, CNT (TIMERx_CNT) is reset to 0 and prescale counter is reloaded.

Definition at line 14228 of file Nano103.h.

The documentation for this struct was generated from the following file:

- C:/Users/yachen/workzone/bsp/nano103bsp/Library/Device/Nuvoton/Nano103/Include/Nano103.h