| Nano103 BSP V3.01.002 The Board Support Package for Nano103 Series

Data Fields
SYS_T Struct Reference
NANO103 Definitions

`#include <Nano103.h>`

## Data Fields
__I uint32_t | PDID
__IO uint32_t | RSTSTS
__IO uint32_t | IPRST1
__IO uint32_t | IPRST2
__IO uint32_t | MISCCTL
__IO uint32_t | TEMPCTL
__IO uint32_t | RCCFCTL
__IO uint32_t | GPA_MFPL
__IO uint32_t | GPA_MFPH
__IO uint32_t | GPB_MFPL
__IO uint32_t | GPB_MFPH
__IO uint32_t | GPC_MFPL
__IO uint32_t | GPC_MFPH
__IO uint32_t | GPD_MFPL
__IO uint32_t | GPD_MFPH
__IO uint32_t | GPE_MFPL
__IO uint32_t | GPF_MFPL
__IO uint32_t | PORCTL
__IO uint32_t | BODCTL
__IO uint32_t | IVREFCTL
__IO uint32_t | LDOCTL
__IO uint32_t | BATDIVCTL
__I uint32_t | WKSTS
__IO uint32_t | IRC0TCTL
__IO uint32_t | IRC0TIEN
__IO uint32_t | IRC0TISTS
__IO uint32_t | IRC1TCTL
__IO uint32_t | IRC1TIEN
__IO uint32_t | IRC1TISTS
__IO uint32_t | MIRCTCTL
__IO uint32_t | MIRCTIEN
__IO uint32_t | MIRCTISTS
__O uint32_t | REGLCTL
__IO uint32_t | RPDBCLK

## Detailed Description

    @addtogroup SYS System Manger Controller(SYS)
    Memory Mapped Structure for SYS Controller

Definition at line 945 of file Nano103.h.

## Field Documentation

## ◆ BATDIVCTL

SYS_T::BATDIVCTL

[0x0074] Battery Voltage Divider Control Register

BATDIVCTL

Offset: 0x74 Battery Voltage Divider Control Register

Bits | Field | Descriptions
[0] | BATDIV2EN | Battery voltage divide 2 Enable Bit This bit is used to enable/disable battery voltage divider function. 0 = Battery voltage divide 2 function Disabled (default). 1 = Battery voltage divide 2 function Enabled.

Definition at line 3211 of file Nano103.h.

## ◆ BODCTL

SYS_T::BODCTL

[0x0064] Brown-out Detector Controller Register

BODCTL

Offset: 0x64 Brown-out Detector Controller Register

Bits | Field | Descriptions
[0] | BODEN | Brown-out Detector Enable Bit (Write Protect) The default value is set by flash controller user configuration register CBODEN (CONFIG0 []) This Brown-out Detector only valid in Normal Mode. 0 = Brown-out Detector function Disabled in Normal mode. 1 = Brown-out Detector function Enabled in Normal mode. Note1: This bit is write protected. Refer to the SYS_REGLCTL register. Note2: LIRC must be enabled before enable BOD.
[2] | BODIE | BOD Interrupt Enable Control (Write Protect) 0 = Interrupt does not issue when BOD occurs in Normal Mode. 1 = Interrupt issues when BOD occurs in Normal Mode. Note1: While the BOD function is enabled (BODEN high) and BOD interrupt function is enabled (BODRSTEN low), BOD will assert an interrupt if BODOUT is high. Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
[3] | BODREN | Brown-out Reset Enable Bit (Write Protect) The default value is set by flash controller user configuration register CBOV(CONFIG0[]) bit . 0 = Brown-out RESET function Disabled in Normal Mode. 1 = Brown-out RESET function Enabled in Normal Mode. Note1: While the Brown-out Detector function is enabled (BODEN high) and BOD reset function is enabled (BODRSTEN high), BOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BODOUT high). Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
[4] | BODIF | Brown-out Detector Interrupt Flag 0 = Brown-out Detector does not detect any voltage drift at VDD down through or up through the target detected voltage after interrupt is enabled. 1 = When Brown-out Detector detects the VDD is dropped down through the target detected voltage or the VDD is raised up through the target detected voltage, this bit is set to 1 and the brown-out interrupt is requested if brown-out interrupt is enabled. Note: Write 1 to clear this bit to 0.
[6] | BODOUT | Brown-out Detector Output Status 0 = Brown-out Detector output status is 0. It means the detected voltage is higher than BODVL setting or BODEN is 0. 1 = Brown-out Detector output status is 1. It means the detected voltage is lower than BODVL setting If the BODEN is 0, BOD function disabled , this bit always responds 0. Note: This bit is ready-only.
[7] | LVREN | Low Voltage Reset Enable Bit (Write Protect) The LVR function resets the chip when the input power voltage is lower than LVR circuit setting LVR function is enabled by default. 0 = Low Voltage Reset function Disabled. 1 = Low Voltage Reset function Enabled. Note1: After enabling the bit, the LVR function will be active with 100us delay for LVR output stable (default). Note2: This bit is write protected. Refer to the SYS_REGLCTL register. Note3: LIRC must be enabled before enable LVR.
[8] | LPBODEN | Low Power Brown-out Detector Enable Bit (Write Protect) Low Power Brown-out Detector only valid in Power Down mode. 0 = Low Power Brown-out Detector function Disabled in Power Down mode. 1 = Low Power Brown-out Detector function Enabled in Power Down mode. Note1: This bit is write protected. Refer to the SYS_REGLCTL register. Note2: LIRC must be enabled before enable BOD.
[9] | LPBODVL | Low Power Brown-out Detector Threshold Voltage Selection (Write Protect) Low Power Brown-out Detector only valid in Power Down mode. 0 = Low Power Brown-Out Detector threshold voltage is 2.0V in Power Down mode. 1 = Low Power Brown-Out Detector threshold voltage is 2.5V in Power Down mode. Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
[10] | LPBODIE | Low Power BOD Interrupt Enable Control (Write Protect) Low Power Brown-out Detector only valid in Power Down mode. 0 = Interrupt does not issue when LPBOD occurs in Power Down mode. 1 = Interrupt issues when LPBOD occurs in Power Down mode Note1: While the LPBOD function is enabled (LPBODEN high) and LPBOD interrupt function is enabled (LPBODIE high), LPBOD will assert an interrupt if BODOUT is high Note2: This bit is write protected Refer to the SYS_REGLCTL register.
[11] | LPBODREN | Low Power Brown-out Reset Enable Bit (Write Protect) Low Power Brown-out Detector only valid in Power Down mode. 0 = Low power Brown-out Detector RESET function Disabled in Power Down mode. 1 = Low Power Brown-out Detector RESET function Enabled in Power Down mode. Note1: While the Low power Brown-out Detector function is enabled (LPBODEN high) and LPBOD reset function is enabled (LPBODREN high), LPBOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BODOUT high). Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
[15:12] | BODVL | Brown-out Detector Threshold Voltage Selection (Write Protect) The default value is set by flash controller user configuration register CBOV (CONFIG0[]). 0000 = Brown-Out Detector threshold voltage is 1.7V. 0001 = Brown-Out Detector threshold voltage is 1.8V. 0010 = Brown-Out Detector threshold voltage is 1.9V. 0011 = Brown-Out Detector threshold voltage is 2.0V. 0100 = Brown-Out Detector threshold voltage is 2.1V. 0101 = Brown-Out Detector threshold voltage is 2.2V. 0110 = Brown-Out Detector threshold voltage is 2.3V. 0111 = Brown-Out Detector threshold voltage is 2.4V. 1000 = Brown-Out Detector threshold voltage is 2.5V. 1001 = Brown-Out Detector threshold voltage is 2.6V. 1010 = Brown-Out Detector threshold voltage is 2.7V. 1011 = Brown-Out Detector threshold voltage is 2.8V. 1100 = Brown-Out Detector threshold voltage is 2.9V. 1101 = Brown-Out Detector threshold voltage is 3.0V. 1110 = Brown-Out Detector threshold voltage is 3.1V. 1111 = Reserved. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[19:16] | LPBOD20TRIM | Low power BOD 2.0 TRIM Value (Write Protect) This value is used to control BOD20 detect voltage level in power-down mode, nominal 2.0 V Higher trim value, higher detection voltage. Note: These bits are write protected. Refer to the SYS_REGLCTL register.
[23:20] | LPBOD25TRIM | Low power BOD 2.5 TRIM Value (Write Protect) This value is used to control LPBOD25 detect voltage level in power-down mode, nominal 2.5 V Higher trim value, higher detection voltage. Note: These bits are write protected. Refer to the SYS_REGLCTL register.
[26:24] | BODDGSEL | Brown-out Detector Output De-glitch Time Select (Write Protect) 000 = BOD output is sampled by RC10K clock. 001 = 4 system clock (HCLK). 010 = 8 system clock (HCLK). 011 = 16 system clock (HCLK). 100 = 32 system clock (HCLK). 101 = 64 system clock (HCLK). 110 = 128 system clock (HCLK). 111 = 256 system clock (HCLK). Note: These bits are write protected. Refer to the SYS_REGLCTL register.
[30:28] | LVRDGSEL | LVR Output De-glitch Time Select (Write Protect) 000 = Without de-glitch function. 001 = 4 system clock (HCLK). 010 = 8 system clock (HCLK). 011 = 16 system clock (HCLK). 100 = 32 system clock (HCLK). 101 = 64 system clock (HCLK). 110 = 128 system clock (HCLK). 111 = 256 system clock (HCLK). Note: These bits are write protected. Refer to the SYS_REGLCTL register.

Definition at line 3205 of file Nano103.h.

## ◆ GPA_MFPH

SYS_T::GPA_MFPH

[0x0034] GPIOA High Byte Multiple Function Control Register

GPA_MFPH

Offset: 0x34 GPIOA High Byte Multiple Function Control Register

Bits | Field | Descriptions
[3:0] | PA8MFP | PA.8 Multi-function Pin Selection 0000 = GPIOA[8] 0001 = I2C0 data input/output pin. 0010 = Timer0 external counter input. 0011 = SmartCard0 clock pin. 0100 = SPI2 slave select pin. 0101 = Timer0 toggle output. 0110 = UART0 Clear to Send input pin.
[7:4] | PA9MFP | PA.9 Multi-function Pin Selection 0000 = GPIOA[9] 0001 = I2C0 clock pin. 0010 = Timer1 external counter input. 0011 = SmartCard0 data pin. 0100 = SPI0 serial clock pin. 0101 = Timer1 toggle output. 0110 = UART1 Request to Send output pin. 0111 = Snooper pin.
[11:8] | PA10MFP | PA.10 Multi-function Pin Selection 0000 = GPIOA[10] 0001 = I2C1 data input/output pin. 0010 = Timer2 external counter input. 0011 = SmartCard0 power pin. 0100 = SPI2 1st MISO (Master In, Slave Out) pin. 0101 = Timer2 toggle output.
[15:12] | PA11MFP | PA.11 Multi-function Pin Selection 0000 = GPIOA[11] 0001 = I2C1 clock pin. 0010 = Timer3 external counter input. 0011 = SmartCard0 reset pin. 0100 = SPI2 1st MOSI (Master Out, Slave In) pin. 0101 = Timer3 toggle output.
[19:16] | PA12MFP | PA.12 Multi-function Pin Selection 0000 = GPIOA[12] 0001 = PWM0 channel0 output/capture input. 0011 = Timer0 capture input. 0101 = I2C0 data input/output pin.
[23:20] | PA13MFP | PA.13 Multi-function Pin Selection 0000 = GPIOA[13] 0001 = PWM0 channel1 output/capture input. 0011 = Timer1 capture input. 0101 = I2C0 clock pin.
[27:24] | PA14MFP | PA.14 Multi-function Pin Selection 0000 = GPIOA[14] 0001 = PWM0 channel2 output/capture input. 0010 = I2C1 data input/output pin. 0011 = I2C1 data input/output pin. 0101 = Timer2 external counter input. 0110 = Data receiver input pin for UART0. 0111 = Timer2 toggle output.
[31:28] | PA15MFP | PA.15 Multi-function Pin Selection 0000 = GPIOA[15] 0001 = PWM0 channel3 output/capture input. 0010 = I2C1 clock pin. 0011 = Timer1 capture input. 0100 = SmartCard0 power pin. 0110 = Data transmitter output pin for UART0. 0111 = Timer3 toggle output.

Definition at line 3189 of file Nano103.h.

## ◆ GPA_MFPL

SYS_T::GPA_MFPL

[0x0030] GPIOA Low Byte Multiple Function Control Register

GPA_MFPL

Offset: 0x30 GPIOA Low Byte Multiple Function Control Register

Bits | Field | Descriptions
[3:0] | PA0MFP | PA.0 Multi-function Pin Selection 0000 = GPIOA[0] 0001 = ADC analog input0. 0010 = Comparator1 P-end input. 0011 = Timer0 capture input. 0101 = PWM0 channel2 output/capture input.
[7:4] | PA1MFP | PA.1 Multi-function Pin Selection 0000 = GPIOA[1] 0001 = ADC analog input1. 0010 = Comparator1 N-end input. 0110 = SPI0 2nd MISO (Master In, Slave Out) pin.
[11:8] | PA2MFP | PA.2 Multi-function Pin Selection 0000 = GPIOA[2] 0001 = ADC analog input2. 0101 = Data receiver input pin for UART1.
[15:12] | PA3MFP | PA.3 Multi-function Pin Selection 0000 = GPIOA[3] 0001 = ADC analog input3. 0101 = Data transmitter output pin for UART1. 0110 = SPI3 1st MOSI (Master Out, Slave In) pin.
[19:16] | PA4MFP | PA.4 Multi-function Pin Selection 0000 = GPIOA[4] 0001 = ADC analog input4. 0101 = I2C0 data input/output pin. 0110 = SPI3 1st MISO (Master In, Slave Out) pin.
[23:20] | PA5MFP | PA.5 Multi-function Pin Selection 0000 = GPIOA[5] 0001 = ADC analog input5. 0101 = I2C0 clock pin. 0110 = SPI3 serial clock pin.
[27:24] | PA6MFP | PA.6 Multi-function Pin Selection 0000 = GPIOA[6] 0001 = ADC analog input6. 0010 = Comparator1 output. 0011 = Timer3 capture input. 0100 = Timer3 external counter input. 0101 = PWM0 channel3 output/capture input. 0111 = Timer3 toggle output.

Definition at line 3188 of file Nano103.h.

## ◆ GPB_MFPH

SYS_T::GPB_MFPH

[0x003c] GPIOB High Byte Multiple Function Control Register

GPB_MFPH

Offset: 0x3C GPIOB High Byte Multiple Function Control Register

Bits | Field | Descriptions
[3:0] | PB8MFP | PB.8 Multi-function Pin Selection 0000 = GPIOB[8] 0001 = ADC external trigger input. 0010 = Timer0 external counter input. 0011 = External interrupt0 input pin. 0100 = Timer0 toggle output. 0111 = Snooper pin.
[7:4] | PB9MFP | PB.9 Multi-function Pin Selection 0000 = GPIOB[9] 0001 = SPI1 slave select pin. 0010 = Timer2 external counter input. 0100 = Timer2 toggle output. 0101 = External interrupt0 input pin.
[11:8] | PB10MFP | PB.10 Multi-function Pin Selection 0000 = GPIOB[10] 0001 = SPI0 1st MOSI (Master Out, Slave In) pin. 0100 = Timer2 toggle output. 0101 = SPI0 slave select pin.
[15:12] | PB11MFP | PB.11 Multi-function Pin Selection 0000 = GPIOB[11] 0001 = PWM0 channel4 output/capture input. 0010= Timer3 external counter input. 0100 = Timer3 toggle output. 0101 = SPI0 1st MISO (Master In, Slave Out) pin.
[23:20] | PB13MFP | PB.13 Multi-function Pin Selection 0000 = GPIOB[13] 0011 = SPI2 2nd MISO (Master In, Slave Out) pin. 0111 = Snooper pin.
[27:24] | PB14MFP | PB.14 Multi-function Pin Selection 0000 = GPIOB[14] 0001 = External interrupt0 input pin. 0011 = SPI2 2nd MOSI (Master Out, Slave In) pin. 0100 = SPI2 slave select pin.
[31:28] | PB15MFP | PB.15 Multi-function Pin Selection 0000 = GPIOB[15] 0001 = External interrupt1 input pin. 0011 = Snooper pin. 0100 = SmartCard1 card detect pin.

Definition at line 3191 of file Nano103.h.

## ◆ GPB_MFPL

SYS_T::GPB_MFPL

[0x0038] GPIOB Low Byte Multiple Function Control Register

GPB_MFPL

Offset: 0x38 GPIOB Low Byte Multiple Function Control Register

Bits | Field | Descriptions
[3:0] | PB0MFP | PB.0 Multi-function Pin Selection 0000 = GPIOB[0] 0001 = Data receiver input pin for UART0. 0011 = SPI1 1st MOSI (Master Out, Slave In) pin.
[7:4] | PB1MFP | PB.1 Multi-function Pin Selection 0000 = GPIOB[1] 0001 = Data transmitter output pin for UART0. 0011 = SPI1 1st MISO (Master In, Slave Out) pin.
[11:8] | PB2MFP | PB.2 Multi-function Pin Selection 0000 = GPIOB[2] 0001 = UART0 Request to Send output pin. 0011 = SPI1 serial clock pin. 0100 = Frequency Divider output pin.
[15:12] | PB3MFP | PB.3 Multi-function Pin Selection 0000 = GPIOB[3] 0001 = UART0 Clear to Send input pin. 0011 = SPI1 slave select pin. 0100 = SmartCard1 card detect pin.
[19:16] | PB4MFP | PB.4 Multi-function Pin Selection 0000 = GPIOB[4] 0001 = Data receiver input pin for UART1. 0011 = SmartCard0 card detect pin. 0100 = SPI2 slave select pin. 0110 = RTC 1Hz output.
[23:20] | PB5MFP | PB.5 Multi-function Pin Selection 0000 = GPIOB[5] 0001 = Data transmitter output pin for UART1. 0011 = SmartCard0 reset pin. 0100 = SPI2 serial clock pin.
[27:24] | PB6MFP | PB.6 Multi-function Pin Selection 0000 = GPIOB[6] 0001 = UART1 Request to Send output pin. 0100 = SPI2 1st MISO (Master In, Slave Out) pin.
[31:28] | PB7MFP | PB.7 Multi-function Pin Selection 0000 = GPIOB[7] 0001 = UART1 Clear to Send input pin.

Definition at line 3190 of file Nano103.h.

## ◆ GPC_MFPH

SYS_T::GPC_MFPH

[0x0044] GPIOC High Byte Multiple Function Control Register

GPC_MFPH

Offset: 0x44 GPIOC High Byte Multiple Function Control Register

Bits | Field | Descriptions
[3:0] | PC8MFP | PC.8 Multi-function Pin Selection 0000 = GPIOC[8] 0001 = SPI1 slave select pin. 0101 = I2C1 data input/output pin.
[7:4] | PC9MFP | PC.9 Multi-function Pin Selection 0000 = GPIOC[9] 0001 = SPI1 serial clock pin. 0101 = I2C1 clock pin.
[11:8] | PC10MFP | PC.10 Multi-function Pin Selection 0000 = GPIOC[10] 0001 = SPI0 1st MISO (Master In, Slave Out) pin. 0101 = Data receiver input pin for UART1.
[15:12] | PC11MFP | PC.11 Multi-function Pin Selection 0000 = GPIOC[11] 0001 = SPI1 1st MOSI (Master Out, Slave In) pin. 0101 = Data transmitter output pin for UART1.
[27:24] | PC14MFP | PC.14 Multi-function Pin Selection 0000 = GPIOC[14] 0001 = UART0 Clear to Send input pin.
[31:28] | PC15MFP | PC.15 Multi-function Pin Selection 0000 = GPIOC[15] 0001 = UART1 Request to Send output pin. 0011 = Timer0 capture input.

Definition at line 3193 of file Nano103.h.

## ◆ GPC_MFPL

SYS_T::GPC_MFPL

[0x0040] GPIOC Low Byte Multiple Function Control Register

GPC_MFPL

Offset: 0x40 GPIOC Low Byte Multiple Function Control Register

Bits | Field | Descriptions
[3:0] | PC0MFP | PC.0 Multi-function Pin Selection 0000 = GPIOC[0] 0001 = SPI0 slave select pin. 0100 = SmartCard1 clock pin. 0101 = PWM0 break1 input 1.
[7:4] | PC1MFP | PC.1 Multi-function Pin Selection 0000 = GPIOC[1] 0001 = SPI0 serial clock pin. 0100 = SmartCard1 data pin. 0101 = PWM0 break1 input 0.
[11:8] | PC2MFP | PC.2 Multi-function Pin Selection 0000 = GPIOC[2] 0001 = SPI0 1st MISO (Master In, Slave Out) pin. 0100 = SmartCard1 power pin. 0101 = PWM0 break0 input 1.
[15:12] | PC3MFP | PC.3 Multi-function Pin Selection 0000 = GPIOC[3] 0001 = SPI0 1st MOSI (Master Out, Slave In) pin. 0100 = SmartCard1 reset pin. 0101 = PWM0 break0 input 0.
[27:24] | PC6MFP | PC.6 Pin Function Selection 0000 = GPIOC[6] 0001 = Data receiver input pin for UART1. 0011 = Timer0 capture input. 0100 = SmartCard1 card detect pin. 0101 = PWM0 channel0 output/capture input.
[31:28] | PC7MFP | PC.7 Multi-function Pin Selection 0000 = GPIOC[7] 0001 = Data transmitter output pin for UART1. 0010 = ADC analog input7. 0011 = Timer1 capture input. 0101 = PWM0 channel1 output/capture input.

Definition at line 3192 of file Nano103.h.

## ◆ GPD_MFPH

SYS_T::GPD_MFPH

[0x004c] GPIOD High Byte Multiple Function Control Register

GPD_MFPH

Offset: 0x4C GPIOD High Byte Multiple Function Control Register

Bits | Field | Descriptions
[27:24] | PD14MFP | PD.14 Multi-function Pin Selection 0000 = GPIOD[14] 0001 = SPI0 2nd MOSI (Master Out, Slave In) pin.
[30:28] | PD15MFP | PD.15 Multi-function Pin Selection 0000 = GPIOD[15] 0001 = SPI0 2nd MISO (Master In, Slave Out) pin. 0100 = SmartCard1 clock pin.

Definition at line 3195 of file Nano103.h.

## ◆ GPD_MFPL

SYS_T::GPD_MFPL

[0x0048] GPIOD Low Byte Multiple Function Control Register

GPD_MFPL

Offset: 0x48 GPIOD Low Byte Multiple Function Control Register

Bits | Field | Descriptions
[27:24] | PD6MFP | PD.6 Multi-function Pin Selection 0000 = GPIOD[6] 0011 = SPI1 2nd MOSI (Master Out, Slave In) pin. 0100 = SmartCard1 reset pin.
[31:28] | PD7MFP | PD.7 Multi-function Pin Selection 0000 = GPIOD[7] 0011 = SPI1 2nd MISO (Master In, Slave Out) pin. 0100 = SmartCard1 power pin.

Definition at line 3194 of file Nano103.h.

## ◆ GPE_MFPL

SYS_T::GPE_MFPL

[0x0050] GPIOE Low Byte Multiple Function Control Register

GPE_MFPL

Offset: 0x50 GPIOE Low Byte Multiple Function Control Register

Bits | Field | Descriptions
[23:20] | PE5MFP | PE.5 Multi-function Pin Selection 0000 = GPIOE[5] 0001 = PWM0 channel5 output/capture input. 0110 = RTC 1Hz output.

Definition at line 3196 of file Nano103.h.

## ◆ GPF_MFPL

SYS_T::GPF_MFPL

[0x0058] GPIOF Low Byte Multiple Function Control Register

GPF_MFPL

Offset: 0x58 GPIOF Low Byte Multiple Function Control Register

Bits | Field | Descriptions
[3:0] | PF0MFP | PF.0 Multi-function Pin Selection 0000 = GPIOF[1] 0101 = External interrupt0 input pin. X111 = Serial wired debugger data pin
[7:4] | PF1MFP | PF.1 Multi-function Pin Selection 0000 = GPIOF[1] 0100 = Frequency Divider output pin. 0101 = External interrupt1 input pin. X111 = Serial wired debugger clock pin.
[11:8] | PF2MFP | PF.2 Multi-function Pin Selection 0000 = GPIOF[2] X111 = External 4~36 MHz (high speed) crystal output pin.
[15:12] | PF3MFP | PF.3 Multi-function Pin Selection 0000 = GPIOF[3] X111 = External 4~36 MHz (high speed) crystal input pin.
[27:24] | PF6MFP | PF.6 Multi-function Pin Selection 0000 = GPIOF[6] 0001 = I2C1 data input/output pin. X111 = External 32.768 kHz crystal output pin(default).
[31:28] | PF7MFP | PF.7 Multi-function Pin Selection 0000 = GPIOF[7] 0001 = I2C1 clock pin. 0011 = SmartCard0 card detect pin. X111 = External 32.768 kHz crystal input pin(default).

Definition at line 3200 of file Nano103.h.

## ◆ IPRST1

SYS_T::IPRST1

[0x0008] Peripheral Reset Control Resister1

IPRST1

Offset: 0x08 Peripheral Reset Control Resister1

Bits | Field | Descriptions
[0] | CHIPRST | Chip One-shot Reset (Write Protect) Setting this bit will reset the whole chip, including Processor core and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles. The CHIPRST is same as the POR reset, all the chip controllers is reset and the chip setting from flash are also reload. About the difference between CHIPRST and SYSRESETREQ(AIRCR[2]), please refer to section 6.2.2 0 = Chip normal operation. 1 = Chip one-shot reset. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[1] | CPURST | Processor Core One-shot Reset (Write Protect) Setting this bit will only reset the processor core and Flash Memory Controller(FMC), and this bit will automatically return to 0 after the 2 clock cycles. 0 = Processor core normal operation. 1 = Processor core one-shot reset. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[2] | PDMARST | PDMA Controller Reset (Write Protect) Setting this bit to 1 will generate a reset signal to the PDMA User needs to set this bit to 0 to release from reset state. 0 = PDMA controller normal operation. 1 = PDMA controller reset. Note: This bit is write protected. Refer to the SYS_REGLCTL register.

Definition at line 3171 of file Nano103.h.

## ◆ IPRST2

SYS_T::IPRST2

[0x000c] Peripheral Reset Control Resister2

IPRST2

Offset: 0x0C Peripheral Reset Control Resister2

Bits | Field | Descriptions
[1] | GPIORST | GPIO Controller Reset 0 = GPIO module normal operation. 1 = GPIO module reset.
[2] | TMR0RST | Timer0 Controller Reset 0 = Timer0 module normal operation. 1 = Timer0 module reset.
[3] | TMR1RST | Timer1 Controller Reset 0 = Timer1 module normal operation. 1 = Timer1 module reset.
[4] | TMR2RST | Timer2 Controller Reset 0 = Timer2 module normal operation. 1 = Timer2 module reset.
[5] | TMR3RST | Timer3 Controller Reset 0 = Timer3 module normal operation. 1 = Timer3 module reset.
[8] | I2C0RST | I2C0 Controller Reset 0 = I2C0 module normal operation. 1 = I2C0 module reset.
[9] | I2C1RST | I2C1 Controller Reset 0 = I2C1 module normal operation. 1 = I2C1 module reset.
[12] | SPI0RST | SPI0 Controller Reset 0 = SPI0 module normal operation. 1 = SPI0 module reset.
[13] | SPI1RST | SPI1 Controller Reset 0 = SPI1 module normal operation. 1 = SPI1 module reset.
[14] | SPI2RST | SPI2 Controller Reset 0 = SPI2 module normal operation. 1 = SPI2 module reset.
[15] | SPI3RST | SPI3 Controller Reset 0 = SPI3 module normal operation. 1 = SPI3 module reset.
[16] | UART0RST | UART0 Controller Reset 0 = UART0 module normal operation. 1 = UART0 module reset.
[17] | UART1RST | UART1 Controller Reset 0 = UART1 module normal operation. 1 = UART1 module reset.
[20] | PWM0RST | PWM0 Controller Reset 0 = PWM0 module normal operation. 1 = PWM0 module reset.
[22] | ACMP01RST | Comparator Controller Reset 0 = Comparator module normal operation. 1 = Comparator module reset.
[28] | ADCRST | ADC Controller Reset 0 = ADC module normal operation. 1 = ADC module reset.
[30] | SC0RST | SmartCard 0 Controller Reset 0 = SmartCard module normal operation. 1 = SmartCard module reset.
[31] | SC1RST | SmartCard1 Controller Reset 0 = SmartCard module normal operation. 1 = SmartCard module reset.

Definition at line 3172 of file Nano103.h.

## ◆ IRC0TCTL

SYS_T::IRC0TCTL

[0x0080] HIRC0 Trim Control Register

IRC0TCTL

Offset: 0x80 HIRC0 Trim Control Register

Bits | Field | Descriptions
[2:0] | FREQSEL | Trim Frequency Selection This field indicates the target frequency of 12 MHz internal high speed RC oscillator (HIRC0) auto trim. During auto trim operation, if clock error detected with CESTOPEN (SYS_IRC0TCTL[8]) is set to 1 or trim retry limitation count reached, this field will be cleared to 000 automatically. 000 = Disable HIRC0 auto trim function. 001 = Enable HIRC0 auto trim function and trim HIRC to 11.0592 MHz. 010 = Enable HIRC0 auto trim function and trim HIRC to 12 MHz. 011 = Enable HIRC0 auto trim function and trim HIRC to 12.288 MHz. 100 = Enable HIRC0 auto trim function and trim HIRC to 16 MHz. Note: HIRC0 auto trim cannot work normally at power down mode These bits must be cleared before entering power down mode.
[5:4] | LOOPSEL | Trim Calculation Loop Selection This field defines that trim value calculation is based on how many 32.768 kHz clock. 00 = Trim value calculation is based on average difference in 4 32.768 kHz clock. 01 = Trim value calculation is based on average difference in 8 32.768 kHz clock. 10 = Trim value calculation is based on average difference in 16 32.768 kHz clock. 11 = Trim value calculation is based on average difference in 32 32.768 kHz clock. Note: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 32.768 kHz clock.
[7:6] | RETRYCNT | Trim Value Update Limitation Count This field defines that how many times the auto trim circuit will try to update the HIRC0 trim value before the frequency of HIRC0 locked. Once the HIRC0 locked, the internal trim value update counter will be reset. If the trim value update counter reached this limitation value and frequency of HIRC0 still doesn't lock, the auto trim operation will be disabled and FREQSEL (SYS_IRC0TCTL[1:0]) will be cleared to 00. 00 = Trim retry count limitation is 64 loops. 01 = Trim retry count limitation is 128 loops. 10 = Trim retry count limitation is 256 loops. 11 = Trim retry count limitation is 512 loops.
[8] | CESTOPEN | Clock Error Stop Enable Bit This bit is used to control if stop the HIRC0 trim operation when 32.768 kHz clock error is detected. If set this bit high and 32.768 kHz clock error detected, the status CLKERRIF (SYS_IRC0TISTS[2]) would be set high and HIRC0 trim operation was stopped If this bit is low and 32.768 kHz clock error detected, the status CLKERRIF (SYS_IRC0TISTS[2]) would be set high and HIRC0 trim operation is continuously. 0 = The trim operation is keep going if clock is inaccuracy. 1 = The trim operation is stopped if clock is inaccuracy.

Definition at line 3216 of file Nano103.h.

## ◆ IRC0TIEN

SYS_T::IRC0TIEN

[0x0084] HIRC0 Trim Interrupt Enable Register

IRC0TIEN

Offset: 0x84 HIRC0 Trim Interrupt Enable Register

Bits | Field | Descriptions
[1] | TFAILIEN | Trim Failure Interrupt Enable Bit This bit controls if an interrupt will be triggered while HIRC0 trim value update limitation count reached and HIRC0 frequency still not locked on target frequency set by FREQSEL (SYS_IRC0TCTL[1:0]). If this bit is high and TFAILIF (SYS_IRC0TSTS[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC0 trim value update limitation count was reached. 0 = Disable TFAILIF (SYS_IRC0TSTS[1]) status to trigger an interrupt to CPU. 1 = Enable TFAILIF (SYS_IRC0TSTS[1]) status to trigger an interrupt to CPU.
[2] | CLKEIEN | Clock Error Interrupt Enable Bit This bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation. If this bit is set to1, and CLKERRIF (SYS_IRC0TSTS[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy. 0 = Disable CLKERRIF (SYS_IRC0TSTS[2]) status to trigger an interrupt to CPU. 1 = Enable CLKERRIF (SYS_IRC0TSTS[2]) status to trigger an interrupt to CPU.

Definition at line 3217 of file Nano103.h.

## ◆ IRC0TISTS

SYS_T::IRC0TISTS

[0x0088] HIRC0 Trim Interrupt Status Register

IRC0TISTS

Offset: 0x88 HIRC0 Trim Interrupt Status Register

Bits | Field | Descriptions
[0] | FREQLOCK | HIRC0 Frequency Lock Status This bit indicates the HIRC0 frequency is locked. This is a status bit and doesn't trigger any interrupt. 0 = The internal high-speed oscillator frequency doesn't lock at frequency set by FREQSEL (SYS_IRC0TCTL[2:0]). 1 = The internal high-speed oscillator frequency locked at frequency set by FREQSEL (SYS_IRC0TCTL[2:0]).
[1] | TFAILIF | Trim Failure Interrupt Status This bit indicates that HIRC0 trim value update limitation count reached and the HIRC0 clock frequency still doesn't be locked Once this bit is set, the auto trim operation stopped and FREQSEL (SYS_IRC0TCTL[1:0]) will be cleared to 00 by hardware automatically. If this bit is set and TFAILIEN (SYS_IRC0TIEN[1]) is high, an interrupt will be triggered to notify that HIRC0 trim value update limitation count was reached Write 1 to clear this to 0. 0 = Trim value update limitation count does not reach. 1 = Trim value update limitation count reached and HIRC frequency still not locked.
[2] | CLKERRIF | Clock Error Interrupt Status When the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or internal high speed RC oscillator (HIRC0) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy Once this bit is set to 1, the auto trim operation stopped and FREQSEL (SYS_IRC0TCTL[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN (SYS_IRC0TCTL[8]) is set to 1. If this bit is set and CLKEIEN (SYS_IRC0TIEN[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy Write 1 to clear this to 0. 0 = Clock frequency is accuracy. 1 = Clock frequency is inaccuracy.

Definition at line 3218 of file Nano103.h.

## ◆ IRC1TCTL

SYS_T::IRC1TCTL

[0x0090] HIRC1 Trim Control Register

IRC1TCTL

Offset: 0x90 HIRC1 Trim Control Register

Bits | Field | Descriptions
[1:0] | FREQSEL | Trim Frequency Selection This field indicates the target frequency of 36 MHz internal high speed RC oscillator (HIRC1) auto trim. During auto trim operation, if clock error detected with CESTOPEN (SYS_IRC1TCTL[8]) is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically. 00 = Disable HIRC1 auto trim function. 01 = Reserved 10 = Enable HIRC1 auto trim function and trim HIRC to 36 MHz. 11 = Reserved. Note: HIRC1 auto trim cannot work normally at power down mode These bits must be cleared before entering power down mode.
[5:4] | LOOPSEL | Trim Calculation Loop Selection This field defines that trim value calculation is based on how many 32.768 kHz clock. 00 = Trim value calculation is based on average difference in 4 32.768 kHz clock. 01 = Trim value calculation is based on average difference in 8 32.768 kHz clock. 10 = Trim value calculation is based on average difference in 16 32.768 kHz clock. 11 = Trim value calculation is based on average difference in 32 32.768 kHz clock. Note: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 32.768 kHz clock.
[7:6] | RETRYCNT | Trim Value Update Limitation Count This field defines that how many times the auto trim circuit will try to update the HIRC1 trim value before the frequency of HIRC1 locked. Once the HIRC1 locked, the internal trim value update counter will be reset. If the trim value update counter reached this limitation value and frequency of HIRC1 still doesn't lock, the auto trim operation will be disabled and FREQSEL (SYS_IRC1TCTL[1:0]) will be cleared to 00. 00 = Trim retry count limitation is 64 loops. 01 = Trim retry count limitation is 128 loops. 10 = Trim retry count limitation is 256 loops. 11 = Trim retry count limitation is 512 loops.
[8] | CESTOPEN | Clock Error Stop Enable Bit This bit is used to control if stop the HIRC1 trim operation when 32.768 kHz clock error is detected. If set this bit high and 32.768 kHz clock error detected, the status CLKERRIF (SYS_IRC1TISTS[2]) would be set high and HIRC1 trim operation was stopped If this bit is low and 32.768 kHz clock error detected, the status CLKERRIF (SYS_IRC1TISTS[2]) would be set high and HIRC1 trim operation is continuously. 0 = The trim operation is keep going if clock is inaccuracy. 1 = The trim operation is stopped if clock is inaccuracy.

Definition at line 3222 of file Nano103.h.

## ◆ IRC1TIEN

SYS_T::IRC1TIEN

[0x0094] HIRC1 Trim Interrupt Enable Register

IRC1TIEN

Offset: 0x94 HIRC1 Trim Interrupt Enable Register

Bits | Field | Descriptions
[1] | TFAILIEN | Trim Failure Interrupt Enable Bit This bit controls if an interrupt will be triggered while HIRC1 trim value update limitation count reached and HIRC1 frequency still not locked on target frequency set by FREQSEL (SYS_IRC1TCTL[1:0]). If this bit is high and TFAILIF (SYS_IRC1TSTS[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC1 trim value update limitation count was reached. 0 = Disable TFAILIF (SYS_IRC1TSTS[1]) status to trigger an interrupt to CPU. 1 = Enable TFAILIF (SYS_IRC1TSTS[1]) status to trigger an interrupt to CPU.
[2] | CLKEIEN | Clock Error Interrupt Enable Bit This bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation. If this bit is set to1, and CLKERRIF (SYS_IRC1TSTS[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy. 0 = Disable CLKERRIF (SYS_IRC1TSTS[2]) status to trigger an interrupt to CPU. 1 = Enable CLKERRIF (SYS_IRC1TSTS[2]) status to trigger an interrupt to CPU.

Definition at line 3223 of file Nano103.h.

## ◆ IRC1TISTS

SYS_T::IRC1TISTS

[0x0098] HIRC1 Trim Interrupt Status Register

IRC1TISTS

Offset: 0x98 HIRC1 Trim Interrupt Status Register

Bits | Field | Descriptions
[0] | FREQLOCK | HIRC1 Frequency Lock Status This bit indicates the HIRC1 frequency is locked. This is a status bit and doesn't trigger any interrupt. 0 = The internal high-speed oscillator frequency doesn't lock at 36 MHz yet. 1 = The internal high-speed oscillator frequency locked at 36 MHz.
[1] | TFAILIF | Trim Failure Interrupt Status This bit indicates that HIRC1 trim value update limitation count reached and the HIRC1 clock frequency still doesn't be locked Once this bit is set, the auto trim operation stopped and FREQSEL (SYS_IRC1TCTL[1:0]) will be cleared to 00 by hardware automatically. If this bit is set and TFAILIEN (SYS_IRC1TIEN[1]) is high, an interrupt will be triggered to notify that HIRC1 trim value update limitation count was reached Write 1 to clear this to 0. 0 = Trim value update limitation count does not reach. 1 = Trim value update limitation count reached and HIRC1 frequency still not locked.
[2] | CLKERRIF | Clock Error Interrupt Status When the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 36 MHz internal high speed RC oscillator (HIRC1) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy Once this bit is set to 1, the auto trim operation stopped and FREQSEL (SYS_IRC1TCTL[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN (SYS_IRC1TCTL[8]) is set to 1. If this bit is set and CLKEIEN (SYS_IRC1TIEN[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy Write 1 to clear this to 0. 0 = Clock frequency is accuracy. 1 = Clock frequency is inaccuracy.

Definition at line 3224 of file Nano103.h.

## ◆ IVREFCTL

SYS_T::IVREFCTL

[0x006c] Internal Voltage Reference Control Register

IVREFCTL

Offset: 0x6C Internal Voltage Reference Control Register

Bits | Field | Descriptions
[0] | BGPEN | Band-gap Enable Control (Write Protect) This is a protected register. Please refer to open lock sequence to program it. Band-gap is the reference voltage of internal reference voltage User must enable band-gap if want to enable internal 1.5, 1.8V or 2.5V reference voltage. 0 = Disabled. 1 = Enabled. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[1] | REGEN | Regulator Enable Control (Write Protect) Enable internal 1.5, 1.8V or 2.5V reference voltage. This is a protected register. Please refer to open lock sequence to program it. 0 = Disabled. 1 = Enabled. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[3:2] | SEL25 | Regulator Output Voltage Selection (Write Protect) Select internal reference voltage level. 00 = 1.5V. 01 = 1.8V. 10 = 2.5V. 11 = 2.5V. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[4] | EXTMODE | Regulator External Mode (Write Protect) Users can output regulator output voltage in VREF pin if EXT_MODE is high. 0 = No connection with external VREF pin. 1 = Connect to external VREF pin Connect a 1uF to 10uF capacitor to AVSS will let internal voltage reference be more stable. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[11:8] | VREFTRIM | Internal Voltage Reference Trim (Write Protect) Note: This bit is write protected. Refer to the SYS_REGLCTL register.

Definition at line 3209 of file Nano103.h.

## ◆ LDOCTL

SYS_T::LDOCTL

[0x0070] LDO Control Register

LDOCTL

Offset: 0x70 LDO Control Register

Bits | Field | Descriptions
[1] | FASTWK | Fast Wakeup Control Bit (Write Protect) 0 = Fast Wakeup from Power-Down mode Disabled. 1 = Fast Wakeup from Power-Down mode Enabled Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[3:2] | LDOLVL | LDO Output Voltage Select (Write Protect) 00 = 1.2V. 01 = 1.6V. 10 = 1.8V. 11 = 1.8V. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[4] | LPRMEN | Low-Power Run Mode Enable Bit (Write Protect) 0 = Low-Power run mode Enabled. 1 = Low-Power run mode Disabled. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[5] | FMCLVEN | Flash memory Low voltage Mode Enable Bit (Write Protect) 0 = Flash memory low voltage(1.2V) mode Enabled. 1 = Flash memory low voltage(1.2V) mode Disabled. Note: This bit is write protected. Refer to the SYS_REGLCTL register.

Definition at line 3210 of file Nano103.h.

## ◆ MIRCTCTL

SYS_T::MIRCTCTL

[0x00a0] MIRC Trim Control Register

MIRCTCTL

Offset: 0xA0 MIRC Trim Control Register

Bits | Field | Descriptions
[1:0] | FREQSEL | Trim Frequency Selection This field indicates the target frequency of 4 MHz internal medium speed RC oscillator (MIRC) auto trim. During auto trim operation, if clock error detected with CESTOPEN (SYS_MIRCTCTL[8]) is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically. 00 = Disable MIRC auto trim function. 01 = Reserved. 10 = Enable MIRC auto trim function and trim HIRC to 4 MHz. 11 = Reserved. Note: MIRC auto trim cannot work normally at power down mode These bits must be cleared before entering power down mode.
[5:4] | LOOPSEL | Trim Calculation Loop Selection This field defines that trim value calculation is based on how many 32.768 kHz clock. 00 = Trim value calculation is based on average difference in 4 32.768 kHz clock. 01 = Trim value calculation is based on average difference in 8 32.768 kHz clock. 10 = Trim value calculation is based on average difference in 16 32.768 kHz clock. 11 = Trim value calculation is based on average difference in 32 32.768 kHz clock. Note: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 32.768 kHz clock.
[7:6] | RETRYCNT | Trim Value Update Limitation Count This field defines that how many times the auto trim circuit will try to update the MIRC trim value before the frequency of MIRC locked. Once the MIRC locked, the internal trim value update counter will be reset. If the trim value update counter reached this limitation value and frequency of MIRC still doesn't lock, the auto trim operation will be disabled and FREQSEL (SYS_MIRCTCTL[1:0]) will be cleared to 00. 00 = Trim retry count limitation is 64 loops. 01 = Trim retry count limitation is 128 loops. 10 = Trim retry count limitation is 256 loops. 11 = Trim retry count limitation is 512 loops.
[8] | CESTOPEN | Clock Error Stop Enable Bit This bit is used to control if stop the MIRC trim operation when 32.768 kHz clock error is detected. If set this bit high and 32.768 kHz clock error detected, the status CLKERRIF (SYS_MIRCTISTS[2]) would be set high and MIRC trim operation was stopped If this bit is low and 32.768 kHz clock error detected, the status CLKERRIF (SYS_MIRCTISTS[2]) would be set high and MIRC trim operation is continuously. 0 = The trim operation is keep going if clock is inaccuracy. 1 = The trim operation is stopped if clock is inaccuracy.

Definition at line 3228 of file Nano103.h.

## ◆ MIRCTIEN

SYS_T::MIRCTIEN

[0x00a4] MIRC Trim Interrupt Enable Register

MIRCTIEN

Offset: 0xA4 MIRC Trim Interrupt Enable Register

Bits | Field | Descriptions
[1] | TFAILIEN | Trim Failure Interrupt Enable Bit This bit controls if an interrupt will be triggered while MIRC trim value update limitation count reached and MIRC frequency still not locked on target frequency set by FREQSEL (SYS_MIRCTCTL[1:0]). If this bit is high and TFAILIF (SYS_MIRCTSTS[1]) is set during auto trim operation, an interrupt will be triggered to notify that MIRC trim value update limitation count was reached. 0 = Disable TFAILIF (SYS_MIRCTSTS[1]) status to trigger an interrupt to CPU. 1 = Enable TFAILIF (SYS_MIRCTSTS[1]) status to trigger an interrupt to CPU.
[2] | CLKEIEN | Clock Error Interrupt Enable Bit This bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation. If this bit is set to1, and CLKERRIF (SYS_MIRCTSTS[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy. 0 = Disable CLKERRIF (SYS_MIRCTSTS[2]) status to trigger an interrupt to CPU. 1 = Enable CLKERRIF (SYS_MIRCTSTS[2]) status to trigger an interrupt to CPU.

Definition at line 3229 of file Nano103.h.

## ◆ MIRCTISTS

SYS_T::MIRCTISTS

[0x00a8] MIRC Trim Interrupt Status Register

MIRCTISTS

Offset: 0xA8 MIRC Trim Interrupt Status Register

Bits | Field | Descriptions
[0] | FREQLOCK | MIRC Frequency Lock Status This bit indicates the MIRC frequency is locked. This is a status bit and doesn't trigger any interrupt. 0 = The internal medium-speed oscillator frequency doesn't lock at 4 MHz yet. 1 = The internal medium-speed oscillator frequency locked at 4 MHz.
[1] | TFAILIF | Trim Failure Interrupt Status This bit indicates that MIRC trim value update limitation count reached and the MIRC clock frequency still doesn't be locked Once this bit is set, the auto trim operation stopped and FREQSEL (SYS_MIRCTCTL[1:0]) will be cleared to 00 by hardware automatically. If this bit is set and TFAILIEN (SYS_MIRCTIEN[1]) is high, an interrupt will be triggered to notify that MIRC trim value update limitation count was reached Write 1 to clear this to 0. 0 = Trim value update limitation count does not reach. 1 = Trim value update limitation count reached and MIRC frequency still not locked.
[2] | CLKERRIF | Clock Error Interrupt Status When the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 4 MHz internal medium speed RC oscillator (MIRC) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy Once this bit is set to 1, the auto trim operation stopped and FREQSEL (SYS_MIRCTCTL[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN (SYS_MIRCTCTL[8]) is set to 1. If this bit is set and CLKEIEN (SYS_MIRCTIEN[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy Write 1 to clear this to 0. 0 = Clock frequency is accuracy. 1 = Clock frequency is inaccuracy.

Definition at line 3230 of file Nano103.h.

## ◆ MISCCTL

SYS_T::MISCCTL

[0x0014] Miscellaneous Control Resister

MISCCTL

Offset: 0x0C Miscellaneous Control Resister

Bits | Field | Descriptions
[6] | POR33DIS | POR 33 Disable 0 = POR33 is enable in normal operation. 1 = POR33 is disable in normal operation.
[7] | POR18DIS | POR 18 Disable 0 = POR18 is enable in normal operation. 1 = POR18 is disable in normal operation.

Definition at line 3176 of file Nano103.h.

## ◆ PDID

SYS_T::PDID

[0x0000] Part Device Identification Number Register

PDID

Offset: 0x00 Part Device Identification Number Register

Bits | Field | Descriptions
[31:0] | PDID | Part Device Identification Number (Read Only) This register reflects device part number code Software can read this register to identify which device is used.

Definition at line 3169 of file Nano103.h.

## ◆ PORCTL

SYS_T::PORCTL

[0x0060] Power-On-Reset Controller Register

PORCTL

Offset: 0x60 Power-On-Reset Controller Register

Bits | Field | Descriptions
[15:0] | POROFF | Power-on Reset Enable Bit (Write Protect) When powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field. The POR function will be active again when this field is set to another value or chip is reset by other reset source, including: nRESET, Watchdog, BOD reset, ICE reset command and the software-chip reset function. Note: This bit is write protected. Refer to the SYS_REGLCTL register.

Definition at line 3204 of file Nano103.h.

## ◆ RCCFCTL

SYS_T::RCCFCTL

[0x0028] RC Clock Filter Control Register

RCCFCTL

Offset: 0x28 RC Clock Filter Control Register

Bits | Field | Descriptions
[0] | HIRC0FEN | HIRC0 Clock Filter Enable Bit This bit is used to enable/disable HIRC0 clock filter function. 0 = HIRC0 clock filter function Disabled. 1 = HIRC0 clock filter function Enabled (default).
[1] | HIRC1FEN | HIRC1 Clock Filter Enable Bit This bit is used to enable/disable HIRC1 clock filter function. 0 = HIRC1 clock filter function Disabled. 1 = HIRC1 clock filter function Enabled (default).
[2] | MRCFEN | MRC Clock Filter Enable Bit This bit is used to enable/disable MRC clock filter function. 0 = 4MHz MRC clock filter function Disabled. 1 = 4MHz MRC clock filter function Enabled (default).

Definition at line 3184 of file Nano103.h.

## ◆ REGLCTL

SYS_T::REGLCTL

[0x0100] Register Lock Control Register

REGLCTL

Offset: 0x100 Register Lock Control Register

Bits | Field | Descriptions
[7:0] | REGLCTL | Register Lock Control Code (Write Only) Some registers have write-protection function Writing these registers have to disable the protected function by writing the sequence value 59h, 16h, 88h to this field After this sequence is completed, the REGLCTL bit will be set to 1 and write-protection registers can be normal write. Register Lock Control Disable Index (Read Only) 0 = Write-protection Enabled for writing protected registers Any write to the protected register is ignored. 1 = Write-protection Disabled for writing protected registers.

Definition at line 3234 of file Nano103.h.

## ◆ RPDBCLK

SYS_T::RPDBCLK

[0x0120] Reset Pin Debounce Clock Selection Register

RPDBCLK

Offset: 0x120 Reset Pin Debounce Clock Selection Register

Bits | Field | Descriptions
[6] | RSTPDBCLK | Reset Pin Debounce Clock Selection Bit Before switch clock, both clock sources must be enabled. 0 = MIRC is selected as reset pin debounce clock. 1 = HIRC0 is selected as reset pin debounce clock.(default)

Definition at line 3238 of file Nano103.h.

## ◆ RSTSTS

SYS_T::RSTSTS

[0x0004] System Reset Status Register

RSTSTS

Offset: 0x04 System Reset Status Register

Bits | Field | Descriptions
[0] | PORF | POR Reset Flag The POR reset flag is set by the Reset Signal from the Power-on Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source. 0 = No reset from POR or CHIPRST. 1 = Power-on Reset (POR) or CHIPRST had issued the reset signal to reset the system. Note: Write 1 to clear this bit to 0.
[1] | PINRF | NRESET Pin Reset Flag The nRESET pin reset flag is set by the Reset Signal from the nRESET Pin to indicate the previous reset source. 0 = No reset from nRESET pin. 1 = Pin nRESET had issued the reset signal to reset the system. Note: Write 1 to clear this bit to 0.
[2] | WDTRF | WDT Reset Flag The WDT reset flag is set by the Reset Signal from the Watchdog Timer to indicate the previous reset source. 0 = No reset from watchdog timer or window watchdog timer. 1 = The watchdog timer had issued the reset signal to reset the system. Note: Write 1 to clear this bit to 0.
[3] | LVRF | LVR Reset Flag The LVR reset flag is set by the Reset Signal from the Low-Voltage Reset controller to indicate the previous reset source. 0 = No reset from LVR. 1 = The LVR had issued the reset signal to reset the system. Note: Write 1 to clear this bit to 0.
[4] | BODRF | BOD Reset Flag The BOD reset flag is set by the Reset Signal from the Brown-Out Detector to indicate the previous reset source. 0 = No reset from BOD. 1 = The BOD had issued the reset signal to reset the system. Note: Write 1 to clear this bit to 0.
[5] | SYSRF | System Reset Flag The system reset flag is set by the Reset Signal from the Cortex-M0 Core to indicate the previous reset source. 0 = No reset from Cortex-M0. 1 = The Cortex-M0 had issued the reset signal to reset the system by writing 1 to the bit SYSRESETREQ(AIRCR[2], Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex-M0 core. Note: Write 1 to clear this bit to 0.
[7] | CPURF | CPU Reset Flag The CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex-M0 Core and Flash Memory Controller (FMC). 0 = No reset from CPU. 1 = The Cortex-M0 Core and FMC are reset by software setting CPURST to 1. Note: Write 1 to clear this bit to 0.
[8] | LOCKRF | Lockup Reset Flag 0 = No reset from Cortex-M0. 1 = The Cortex-M0 had issued the reset signal to reset the system by Cortex-M0 lockup event.

Definition at line 3170 of file Nano103.h.

## ◆ TEMPCTL

SYS_T::TEMPCTL

[0x0020] Temperature Sensor Control Register

TEMPCTL

Offset: 0x20 Temperature Sensor Control Register

Bits | Field | Descriptions
[0] | VTEMPEN | Temperature Sensor Enable Bit This bit is used to enable/disable temperature sensor function. 0 = Temperature sensor function Disabled (default). 1 = Temperature sensor function Enabled.

Definition at line 3180 of file Nano103.h.

## ◆ WKSTS

SYS_T::WKSTS

[0x007c] System Wakeup Status Register

WKSTS

Offset: 0x7C System Wakeup Status Register

Bits | Field | Descriptions
[0] | ACMPWK | ACMP Wake-up Flag (Read Only) This flag indicates that wakeup of device from Power-down mode was requested with ACMP wakeup event This flag is cleared when Power-down mode is entered.
[1] | I2C1WK | I2C1 Wake-up Flag (Read Only) This flag indicates that wakeup of device from Power-down mode was requested with I2C1 wakeup event This flag is cleared when Power-down mode is entered.
[2] | I2C0WK | I2C0 Wake-up Flag (Read Only) This flag indicates that wakeup of device from Power-down mode was requested with I2C0 wakeup event This flag is cleared when Power-down mode is entered.
[3] | TMR3WK | TMR3 Wake-up Flag (Read Only) This flag indicates that wakeup of device from Power-down mode was requested withTMR3 wakeup event This flag is cleared when Power-down mode is entered.
[4] | TMR2WK | TMR2 Wake-up Flag (Read Only) This flag indicates that wakeup of device from Power-down mode was requested withTMR2 wakeup event This flag is cleared when Power-down mode is entered.
[5] | TMR1WK | TMR1 Wake-up Flag (Read Only) This flag indicates that wakeup of device from Power-down mode was requested withTMR1 wakeup event This flag is cleared when Power-down mode is entered.
[6] | TMR0WK | TMR0 Wake-up Flag (Read Only) This flag indicates that wakeup of device from Power-down mode was requested withTMR0 wakeup event This flag is cleared when Power-down mode is entered.
[7] | WDTWK | WDT Wake-up Flag (Read Only) This flag indicates that wakeup of device from Power-down mode was requested with WDT wakeup event This flag is cleared when Power-down mode is entered.
[8] | BODWK | BOD Wake-up Flag (Read Only) This flag indicates that wakeup of device from Power-down mode was requested with BOD wakeup event This flag is cleared when Power-down mode is entered.
[9] | SPI3WK | SPI3 Wake-up Flag (Read Only) This flag indicates that wakeup of device from Power-down mode was requested with SPI3 wakeup event This flag is cleared when Power-down mode is entered.
[10] | SPI2WK | SPI2 Wake-up Flag (Read Only) This flag indicates that wakeup of device from Power-down mode was requested with SPI2 wakeup event This flag is cleared when Power-down mode is entered.
[11] | SPI1WK | SPI1 Wake-up Flag (Read Only) This flag indicates that wakeup of device from Power-down mode was requested with SPI1 wakeup event This flag is cleared when Power-down mode is entered.
[12] | SPI0WK | SPI0 Wake-up Flag (Read Only) This flag indicates that wakeup of device from Power-down mode was requested with SPI0 wakeup event This flag is cleared when Power-down mode is entered.
[13] | UART1WK | UART1 Wake-up Flag (Read Only) This flag indicates that wakeup of device from Power-down mode was requested with UART1 wakeup event This flag is cleared when Power-down mode is entered.
[14] | UART0WK | UART0 Wake-up Flag (Read Only) This flag indicates that wakeup of device from Power-down mode was requested with UART0 wakeup event This flag is cleared when Power-down mode is entered.
[15] | RTCWK | RTC Wake-up Flag (Read Only) This flag indicates that wakeup of device from Power-down mode was requested with a RTC alarm or tick time happened This flag is cleared when Power-down mode is entered.
[16] | GPIOWK | GPIO Wake-up Flag (Read Only) This flag indicates that wakeup of device from Power-down mode was requested with GPIO wakeup event This flag is cleared when Power-down mode is entered.

Definition at line 3215 of file Nano103.h.

The documentation for this struct was generated from the following file:

- C:/Users/yachen/workzone/bsp/nano103bsp/Library/Device/Nuvoton/Nano103/Include/Nano103.h