| Nano103 BSP V3.01.002 The Board Support Package for Nano103 Series

Macros
NANO103 Peripheral Memory Map

## Macros
#define | FLASH_BASE ((uint32_t)0x00000000)
| Flash base address. More...
#define | SRAM_BASE ((uint32_t)0x20000000)
| SRAM base address. More...
#define | APB1PERIPH_BASE ((uint32_t)0x40000000)
| APB1 base address. More...
#define | APB2PERIPH_BASE ((uint32_t)0x40100000)
| APB2 base address. More...
#define | AHBPERIPH_BASE ((uint32_t)0x50000000)
| AHB base address. More...
#define | WDT_BASE (APB1PERIPH_BASE + 0x04000)
| WDT register base address. More...
#define | WWDT_BASE (APB1PERIPH_BASE + 0x04100)
| WWDT register base address. More...
#define | RTC_BASE (APB1PERIPH_BASE + 0x08000)
| RTC register base address. More...
#define | TIMER0_BASE (APB1PERIPH_BASE + 0x10000)
| TIMER0 register base address. More...
#define | TIMER1_BASE (APB1PERIPH_BASE + 0x10100)
| TIMER1 register base address. More...
#define | I2C0_BASE (APB1PERIPH_BASE + 0x20000)
| I2C0 register base address. More...
#define | SPI0_BASE (APB1PERIPH_BASE + 0x30000)
| SPI0 register base address. More...
#define | SPI2_BASE (APB1PERIPH_BASE + 0xD0000)
| SPI2 register base address. More...
#define | PWM0_BASE (APB1PERIPH_BASE + 0x40000)
| PWM0 register base address. More...
#define | UART0_BASE (APB1PERIPH_BASE + 0x50000)
| UART0 register base address. More...
#define | LCD_BASE (APB1PERIPH_BASE + 0xB0000)
| LCD register base address. More...
#define | ADC_BASE (APB1PERIPH_BASE + 0xE0000)
| ADC register base address. More...
#define | TIMER2_BASE (APB2PERIPH_BASE + 0x10000)
| TIMER2 register base address. More...
#define | TIMER3_BASE (APB2PERIPH_BASE + 0x10100)
| TIMER3 register base address. More...
#define | I2C1_BASE (APB2PERIPH_BASE + 0x20000)
| I2C1 register base address. More...
#define | SPI1_BASE (APB2PERIPH_BASE + 0x30000)
| SPI1 register base address. More...
#define | SPI3_BASE (APB2PERIPH_BASE + 0xE0000)
| SPI3 register base address. More...
#define | UART1_BASE (APB2PERIPH_BASE + 0x50000)
| UART1 register base address. More...
#define | SC0_BASE (APB2PERIPH_BASE + 0x90000)
| SC0 register base address. More...
#define | SC1_BASE (APB2PERIPH_BASE + 0xB0000)
| SC1 register base address. More...
#define | ACMP_BASE (APB2PERIPH_BASE + 0xD0000)
| ACMP register base address. More...
#define | SYS_BASE (AHBPERIPH_BASE + 0x00000)
| SYS register base address. More...
#define | CLK_BASE (AHBPERIPH_BASE + 0x00200)
| CLK register base address. More...
#define | INTID_BASE (AHBPERIPH_BASE + 0x00300)
| INT register base address. More...
#define | GPIOA_BASE (AHBPERIPH_BASE + 0x04000)
| GPIO port A register base address. More...
#define | GPIOB_BASE (AHBPERIPH_BASE + 0x04040)
| GPIO port B register base address. More...
#define | GPIOC_BASE (AHBPERIPH_BASE + 0x04080)
| GPIO port C register base address. More...
#define | GPIOD_BASE (AHBPERIPH_BASE + 0x040C0)
| GPIO port D register base address. More...
#define | GPIOE_BASE (AHBPERIPH_BASE + 0x04100)
| GPIO port E register base address. More...
#define | GPIOF_BASE (AHBPERIPH_BASE + 0x04140)
| GPIO port F register base address. More...
#define | GPIODBNCE_BASE (AHBPERIPH_BASE + 0x04180)
| GPIO debounce register base address. More...
#define | GPIO_PIN_DATA_BASE (AHBPERIPH_BASE + 0x04200)
| GPIO bit access register base address. More...
#define | PDMA0_BASE (AHBPERIPH_BASE + 0x08000)
| PDMA0 register base address. More...
#define | PDMA1_BASE (AHBPERIPH_BASE + 0x08100)
| PDMA1 register base address. More...
#define | PDMA2_BASE (AHBPERIPH_BASE + 0x08200)
| PDMA2 register base address. More...
#define | PDMA3_BASE (AHBPERIPH_BASE + 0x08300)
| PDMA3 register base address. More...
#define | PDMA4_BASE (AHBPERIPH_BASE + 0x08400)
| PDMA4 register base address. More...
#define | PDMACRC_BASE (AHBPERIPH_BASE + 0x08E00)
| PDMA global control register base address. More...
#define | PDMAGCR_BASE (AHBPERIPH_BASE + 0x08F00)
| PDMA CRC register base address. More...
#define | FMC_BASE (AHBPERIPH_BASE + 0x0C000)
| FMC register base address. More...

## Detailed Description

Memory Mapped Structure for NANO103 Series Peripheral

## Macro Definition Documentation

## ◆ ACMP_BASE

#define ACMP_BASE (APB2PERIPH_BASE + 0xD0000)

ACMP register base address.

Definition at line 24832 of file Nano103.h.

## ◆ ADC_BASE

#define ADC_BASE (APB1PERIPH_BASE + 0xE0000)

ADC register base address.

Definition at line 24821 of file Nano103.h.

## ◆ AHBPERIPH_BASE

#define AHBPERIPH_BASE ((uint32_t)0x50000000)

AHB base address.

Peripheral memory map

Definition at line 24806 of file Nano103.h.

## ◆ APB1PERIPH_BASE

#define APB1PERIPH_BASE ((uint32_t)0x40000000)

APB1 base address.

Definition at line 24804 of file Nano103.h.

## ◆ APB2PERIPH_BASE

#define APB2PERIPH_BASE ((uint32_t)0x40100000)

APB2 base address.

Definition at line 24805 of file Nano103.h.

## ◆ CLK_BASE

#define CLK_BASE (AHBPERIPH_BASE + 0x00200)

CLK register base address.

Definition at line 24835 of file Nano103.h.

## ◆ FLASH_BASE

#define FLASH_BASE ((uint32_t)0x00000000)

Flash base address.

<Peripheral and SRAM base address

Definition at line 24802 of file Nano103.h.

## ◆ FMC_BASE

#define FMC_BASE (AHBPERIPH_BASE + 0x0C000)

FMC register base address.

Definition at line 24852 of file Nano103.h.

## ◆ GPIO_PIN_DATA_BASE

#define GPIO_PIN_DATA_BASE (AHBPERIPH_BASE + 0x04200)

GPIO bit access register base address.

Definition at line 24844 of file Nano103.h.

## ◆ GPIOA_BASE

#define GPIOA_BASE (AHBPERIPH_BASE + 0x04000)

GPIO port A register base address.

Definition at line 24837 of file Nano103.h.

## ◆ GPIOB_BASE

#define GPIOB_BASE (AHBPERIPH_BASE + 0x04040)

GPIO port B register base address.

Definition at line 24838 of file Nano103.h.

## ◆ GPIOC_BASE

#define GPIOC_BASE (AHBPERIPH_BASE + 0x04080)

GPIO port C register base address.

Definition at line 24839 of file Nano103.h.

## ◆ GPIOD_BASE

#define GPIOD_BASE (AHBPERIPH_BASE + 0x040C0)

GPIO port D register base address.

Definition at line 24840 of file Nano103.h.

## ◆ GPIODBNCE_BASE

#define GPIODBNCE_BASE (AHBPERIPH_BASE + 0x04180)

GPIO debounce register base address.

Definition at line 24843 of file Nano103.h.

## ◆ GPIOE_BASE

#define GPIOE_BASE (AHBPERIPH_BASE + 0x04100)

GPIO port E register base address.

Definition at line 24841 of file Nano103.h.

## ◆ GPIOF_BASE

#define GPIOF_BASE (AHBPERIPH_BASE + 0x04140)

GPIO port F register base address.

Definition at line 24842 of file Nano103.h.

## ◆ I2C0_BASE

#define I2C0_BASE (APB1PERIPH_BASE + 0x20000)

I2C0 register base address.

Definition at line 24815 of file Nano103.h.

## ◆ I2C1_BASE

#define I2C1_BASE (APB2PERIPH_BASE + 0x20000)

I2C1 register base address.

Definition at line 24825 of file Nano103.h.

## ◆ INTID_BASE

#define INTID_BASE (AHBPERIPH_BASE + 0x00300)

INT register base address.

Definition at line 24836 of file Nano103.h.

## ◆ LCD_BASE

#define LCD_BASE (APB1PERIPH_BASE + 0xB0000)

LCD register base address.

Definition at line 24820 of file Nano103.h.

## ◆ PDMA0_BASE

#define PDMA0_BASE (AHBPERIPH_BASE + 0x08000)

PDMA0 register base address.

Definition at line 24845 of file Nano103.h.

## ◆ PDMA1_BASE

#define PDMA1_BASE (AHBPERIPH_BASE + 0x08100)

PDMA1 register base address.

Definition at line 24846 of file Nano103.h.

## ◆ PDMA2_BASE

#define PDMA2_BASE (AHBPERIPH_BASE + 0x08200)

PDMA2 register base address.

Definition at line 24847 of file Nano103.h.

## ◆ PDMA3_BASE

#define PDMA3_BASE (AHBPERIPH_BASE + 0x08300)

PDMA3 register base address.

Definition at line 24848 of file Nano103.h.

## ◆ PDMA4_BASE

#define PDMA4_BASE (AHBPERIPH_BASE + 0x08400)

PDMA4 register base address.

Definition at line 24849 of file Nano103.h.

## ◆ PDMACRC_BASE

#define PDMACRC_BASE (AHBPERIPH_BASE + 0x08E00)

PDMA global control register base address.

Definition at line 24850 of file Nano103.h.

## ◆ PDMAGCR_BASE

#define PDMAGCR_BASE (AHBPERIPH_BASE + 0x08F00)

PDMA CRC register base address.

Definition at line 24851 of file Nano103.h.

## ◆ PWM0_BASE

#define PWM0_BASE (APB1PERIPH_BASE + 0x40000)

PWM0 register base address.

Definition at line 24818 of file Nano103.h.

## ◆ RTC_BASE

#define RTC_BASE (APB1PERIPH_BASE + 0x08000)

RTC register base address.

Definition at line 24812 of file Nano103.h.

## ◆ SC0_BASE

#define SC0_BASE (APB2PERIPH_BASE + 0x90000)

SC0 register base address.

Definition at line 24830 of file Nano103.h.

## ◆ SC1_BASE

#define SC1_BASE (APB2PERIPH_BASE + 0xB0000)

SC1 register base address.

Definition at line 24831 of file Nano103.h.

## ◆ SPI0_BASE

#define SPI0_BASE (APB1PERIPH_BASE + 0x30000)

SPI0 register base address.

Definition at line 24816 of file Nano103.h.

## ◆ SPI1_BASE

#define SPI1_BASE (APB2PERIPH_BASE + 0x30000)

SPI1 register base address.

Definition at line 24826 of file Nano103.h.

## ◆ SPI2_BASE

#define SPI2_BASE (APB1PERIPH_BASE + 0xD0000)

SPI2 register base address.

Definition at line 24817 of file Nano103.h.

## ◆ SPI3_BASE

#define SPI3_BASE (APB2PERIPH_BASE + 0xE0000)

SPI3 register base address.

Definition at line 24827 of file Nano103.h.

## ◆ SRAM_BASE

#define SRAM_BASE ((uint32_t)0x20000000)

SRAM base address.

Definition at line 24803 of file Nano103.h.

## ◆ SYS_BASE

#define SYS_BASE (AHBPERIPH_BASE + 0x00000)

SYS register base address.

Definition at line 24834 of file Nano103.h.

## ◆ TIMER0_BASE

#define TIMER0_BASE (APB1PERIPH_BASE + 0x10000)

TIMER0 register base address.

Definition at line 24813 of file Nano103.h.

## ◆ TIMER1_BASE

#define TIMER1_BASE (APB1PERIPH_BASE + 0x10100)

TIMER1 register base address.

Definition at line 24814 of file Nano103.h.

## ◆ TIMER2_BASE

#define TIMER2_BASE (APB2PERIPH_BASE + 0x10000)

TIMER2 register base address.

Definition at line 24823 of file Nano103.h.

## ◆ TIMER3_BASE

#define TIMER3_BASE (APB2PERIPH_BASE + 0x10100)

TIMER3 register base address.

Definition at line 24824 of file Nano103.h.

## ◆ UART0_BASE

#define UART0_BASE (APB1PERIPH_BASE + 0x50000)

UART0 register base address.

Definition at line 24819 of file Nano103.h.

## ◆ UART1_BASE

#define UART1_BASE (APB2PERIPH_BASE + 0x50000)

UART1 register base address.

Definition at line 24829 of file Nano103.h.

## ◆ WDT_BASE

#define WDT_BASE (APB1PERIPH_BASE + 0x04000)

WDT register base address.

Definition at line 24810 of file Nano103.h.

## ◆ WWDT_BASE

#define WWDT_BASE (APB1PERIPH_BASE + 0x04100)

WWDT register base address.

Definition at line 24811 of file Nano103.h.