| Nano103 BSP V3.01.002 The Board Support Package for Nano103 Series

Nano103.h
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1 /**************************************************************************/
52 #ifndef __NANO103_H__
53 #define __NANO103_H__
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58
69 /******************************************************************************/
70 /* Processor and Core Peripherals */
71 /******************************************************************************/
80 typedef enum IRQn
81 {
82 /****** Cortex-M0 Processor Exceptions Numbers *****************************************/
83
84 NonMaskableInt_IRQn = -14,
85 HardFault_IRQn = -13,
86 SVCall_IRQn = -5,
87 PendSV_IRQn = -2,
88 SysTick_IRQn = -1,
90 /****** NANO103 specific Interrupt Numbers ***********************************************/
91 BOD_IRQn = 0,
92 WDT_IRQn = 1,
93 EINT0_IRQn = 2,
94 EINT1_IRQn = 3,
95 GPABC_IRQn = 4,
96 GPDEF_IRQn = 5,
97 PWM0_IRQn = 6,
98 TMR0_IRQn = 8,
99 TMR1_IRQn = 9,
100 TMR2_IRQn = 10,
101 TMR3_IRQn = 11,
102 UART0_IRQn = 12,
103 UART1_IRQn = 13,
104 SPI0_IRQn = 14,
105 SPI1_IRQn = 15,
106 SPI2_IRQn = 16,
107 HIRC_IRQn = 17,
108 I2C0_IRQn = 18,
109 I2C1_IRQn = 19,
110 SC0_IRQn = 21,
111 SC1_IRQn = 22,
112 CKSD_IRQn = 24,
113 PDMA_IRQn = 26,
114 SPI3_IRQn = 27,
115 PDWU_IRQn = 28,
116 ADC_IRQn = 29,
117 ACMP_IRQn = 30,
118 RTC_IRQn = 31
119 } IRQn_Type;
120
121
122 /*
123 * ==========================================================================
124 * ----------- Processor and Core Peripheral Section ------------------------
125 * ==========================================================================
126 */
127
128 /* Configuration of the Cortex-M0 Processor and Core Peripherals */
129 #define __CM0_REV 0x0201
130 #define __NVIC_PRIO_BITS 2
131 #define __Vendor_SysTickConfig 0
132 #define __MPU_PRESENT 0
133 #define __FPU_PRESENT 0
135 /* end of group NANO103_CMSIS */
136
137
138 #include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
139 #include "system_Nano103.h" /* NANO103 Series System include file */
140 #include <stdint.h>
141
142 /******************************************************************************/
143 /* Device Specific Peripheral registers structures */
144 /******************************************************************************/
150 #if defined ( __CC_ARM )
151 #pragma anon_unions
152 #endif
153
154
155 /*---------------------- INT Controller -------------------------*/
161 typedef struct
162 {
163
164
790 __I uint32_t IRQ0_SRC;
791 __I uint32_t IRQ1_SRC;
792 __I uint32_t IRQ2_SRC;
793 __I uint32_t IRQ3_SRC;
794 __I uint32_t IRQ4_SRC;
795 __I uint32_t IRQ5_SRC;
796 __I uint32_t IRQ6_SRC;
797 __I uint32_t IRQ7_SRC;
798 __I uint32_t IRQ8_SRC;
799 __I uint32_t IRQ9_SRC;
800 __I uint32_t IRQ10_SRC;
801 __I uint32_t IRQ11_SRC;
802 __I uint32_t IRQ12_SRC;
803 __I uint32_t IRQ13_SRC;
804 __I uint32_t IRQ14_SRC;
805 __I uint32_t IRQ15_SRC;
806 __I uint32_t IRQ16_SRC;
807 __I uint32_t IRQ17_SRC;
808 __I uint32_t IRQ18_SRC;
809 __I uint32_t IRQ19_SRC;
810 __I uint32_t IRQ20_SRC;
811 __I uint32_t IRQ21_SRC;
812 __I uint32_t IRQ22_SRC;
813 __I uint32_t IRQ23_SRC;
814 __I uint32_t IRQ24_SRC;
815 __I uint32_t IRQ25_SRC;
816 __I uint32_t IRQ26_SRC;
817 __I uint32_t IRQ27_SRC;
818 __I uint32_t IRQ28_SRC;
819 __I uint32_t IRQ29_SRC;
820 __I uint32_t IRQ30_SRC;
821 __I uint32_t IRQ31_SRC;
822 __IO uint32_t NMI_SEL;
823 __IO uint32_t MCU_IRQ;
826 } INT_T;
827
833 #define INT_IRQ0_SRC_INT_SRC_Pos (0)
834 #define INT_IRQ0_SRC_INT_SRC_Msk (0xful << INT_IRQ0_SRC_INT_SRC_Pos)
836 #define INT_IRQ1_SRC_INT_SRC_Pos (0)
837 #define INT_IRQ1_SRC_INT_SRC_Msk (0xful << INT_IRQ1_SRC_INT_SRC_Pos)
839 #define INT_IRQ2_SRC_INT_SRC_Pos (0)
840 #define INT_IRQ2_SRC_INT_SRC_Msk (0xful << INT_IRQ2_SRC_INT_SRC_Pos)
842 #define INT_IRQ3_SRC_INT_SRC_Pos (0)
843 #define INT_IRQ3_SRC_INT_SRC_Msk (0xful << INT_IRQ3_SRC_INT_SRC_Pos)
845 #define INT_IRQ4_SRC_INT_SRC_Pos (0)
846 #define INT_IRQ4_SRC_INT_SRC_Msk (0xful << INT_IRQ4_SRC_INT_SRC_Pos)
848 #define INT_IRQ5_SRC_INT_SRC_Pos (0)
849 #define INT_IRQ5_SRC_INT_SRC_Msk (0xful << INT_IRQ5_SRC_INT_SRC_Pos)
851 #define INT_IRQ6_SRC_INT_SRC_Pos (0)
852 #define INT_IRQ6_SRC_INT_SRC_Msk (0xful << INT_IRQ6_SRC6_INT_SRC_Pos)
854 #define INT_IRQ7_SRC_INT_SRC_Pos (0)
855 #define INT_IRQ7_SRC_INT_SRC_Msk (0xful << INT_IRQ7_SRC_INT_SRC_Pos)
857 #define INT_IRQ8_SRC_INT_SRC_Pos (0)
858 #define INT_IRQ8_SRC_INT_SRC_Msk (0xful << INT_IRQ8_SRC_INT_SRC_Pos)
860 #define INT_IRQ9_SRC_INT_SRC_Pos (0)
861 #define INT_IRQ9_SRC_INT_SRC_Msk (0xful << INT_IRQ9_SRC_INT_SRC_Pos)
863 #define INT_IRQ10_SRC_INT_SRC_Pos (0)
864 #define INT_IRQ10_SRC_INT_SRC_Msk (0xful << INT_IRQ10_SRC_INT_SRC_Pos)
866 #define INT_IRQ11_SRC_INT_SRC_Pos (0)
867 #define INT_IRQ11_SRC_INT_SRC_Msk (0xful << INT_IRQ11_SRC_INT_SRC_Pos)
869 #define INT_IRQ12_SRC_INT_SRC_Pos (0)
870 #define INT_IRQ12_SRC_INT_SRC_Msk (0xful << INT_IRQ12_SRC_INT_SRC_Pos)
872 #define INT_IRQ13_SRC_INT_SRC_Pos (0)
873 #define INT_IRQ13_SRC_INT_SRC_Msk (0xful << INT_IRQ13_SRC_INT_SRC_Pos)
875 #define INT_IRQ14_SRC_INT_SRC_Pos (0)
876 #define INT_IRQ14_SRC_INT_SRC_Msk (0xful << INT_IRQ14_SRC_INT_SRC_Pos)
878 #define INT_IRQ15_SRC_INT_SRC_Pos (0)
879 #define INT_IRQ15_SRC_INT_SRC_Msk (0xful << INT_IRQ15_SRC_INT_SRC_Pos)
881 #define INT_IRQ16_SRC_INT_SRC_Pos (0)
882 #define INT_IRQ16_SRC_INT_SRC_Msk (0xful << INT_IRQ16_SRC_INT_SRC_Pos)
884 #define INT_IRQ17_SRC_INT_SRC_Pos (0)
885 #define INT_IRQ17_SRC_INT_SRC_Msk (0xful << INT_IRQ17_SRC_INT_SRC_Pos)
887 #define INT_IRQ18_SRC_INT_SRC_Pos (0)
888 #define INT_IRQ18_SRC_INT_SRC_Msk (0xful << INT_IRQ18_SRC_INT_SRC_Pos)
890 #define INT_IRQ19_SRC_INT_SRC_Pos (0)
891 #define INT_IRQ19_SRC_INT_SRC_Msk (0xful << INT_IRQ19_SRC_INT_SRC_Pos)
893 #define INT_IRQ20_SRC_INT_SRC_Pos (0)
894 #define INT_IRQ20_SRC_INT_SRC_Msk (0xful << INT_IRQ20_SRC_INT_SRC_Pos)
896 #define INT_IRQ21_SRC_INT_SRC_Pos (0)
897 #define INT_IRQ21_SRC_INT_SRC_Msk (0xful << INT_IRQ21_SRC_INT_SRC_Pos)
899 #define INT_IRQ22_SRC_INT_SRC_Pos (0)
900 #define INT_IRQ22_SRC_INT_SRC_Msk (0xful << INT_IRQ22_SRC_INT_SRC_Pos)
902 #define INT_IRQ23_SRC_INT_SRC_Pos (0)
903 #define INT_IRQ23_SRC_INT_SRC_Msk (0xful << INT_IRQ23_SRC_INT_SRC_Pos)
905 #define INT_IRQ24_SRC_INT_SRC_Pos (0)
906 #define INT_IRQ24_SRC_INT_SRC_Msk (0xful << INT_IRQ24_SRC_INT_SRC_Pos)
908 #define INT_IRQ25_SRC_INT_SRC_Pos (0)
909 #define INT_IRQ25_SRC_INT_SRC_Msk (0xful << INT_IRQ25_SRC_INT_SRC_Pos)
911 #define INT_IRQ26_SRC_INT_SRC_Pos (0)
912 #define INT_IRQ26_SRC_INT_SRC_Msk (0xful << INT_IRQ26_SRC_INT_SRC_Pos)
914 #define INT_IRQ27_SRC_INT_SRC_Pos (0)
915 #define INT_IRQ27_SRC_INT_SRC_Msk (0xful << INT_IRQ27_SRC_INT_SRC_Pos)
917 #define INT_IRQ28_SRC_INT_SRC_Pos (0)
918 #define INT_IRQ28_SRC_INT_SRC_Msk (0xful << INT_IRQ28_SRC_INT_SRC_Pos)
920 #define INT_IRQ29_SRC_INT_SRC_Pos (0)
921 #define INT_IRQ29_SRC_INT_SRC_Msk (0xful << INT_IRQ29_SRC_INT_SRC_Pos)
923 #define INT_IRQ30_SRC_INT_SRC_Pos (0)
924 #define INT_IRQ30_SRC_INT_SRC_Msk (0xful << INT_IRQ30_SRC_INT_SRC_Pos)
926 #define INT_IRQ31_SRC_INT_SRC_Pos (0)
927 #define INT_IRQ31_SRC_INT_SRC_Msk (0xful << INT_IRQ31_SRC_INT_SRC_Pos)
929 #define INT_NMI_SEL_NMI_SEL_Pos (0)
930 #define INT_NMI_SEL_NMI_SEL_Msk (0x1ful << INT_NMI_SEL_NMI_SEL_Pos)
932 #define INT_MCU_IRQ_MCU_IRQ_Pos (0)
933 #define INT_MCU_IRQ_MCU_IRQ_Msk (0xfffffffful << INT_MCU_IRQ_MCU_IRQ_Pos) /* INT_CONST */
936 /* end of INT register group */
937
938
939 /*---------------------- System Manger Controller -------------------------*/
945 typedef struct
946 {
947
948
3169 __I uint32_t PDID;
3170 __IO uint32_t RSTSTS;
3171 __IO uint32_t IPRST1;
3172 __IO uint32_t IPRST2;
3173 __I uint32_t RESERVE[1];
3176 __IO uint32_t MISCCTL;
3177 __I uint32_t RESERVE0[2];
3180 __IO uint32_t TEMPCTL;
3181 __I uint32_t RESERVE1[1];
3184 __IO uint32_t RCCFCTL;
3185 __I uint32_t RESERVE2[1];
3188 __IO uint32_t GPA_MFPL;
3189 __IO uint32_t GPA_MFPH;
3190 __IO uint32_t GPB_MFPL;
3191 __IO uint32_t GPB_MFPH;
3192 __IO uint32_t GPC_MFPL;
3193 __IO uint32_t GPC_MFPH;
3194 __IO uint32_t GPD_MFPL;
3195 __IO uint32_t GPD_MFPH;
3196 __IO uint32_t GPE_MFPL;
3197 __I uint32_t RESERVE3[1];
3200 __IO uint32_t GPF_MFPL;
3201 __I uint32_t RESERVE4[1];
3204 __IO uint32_t PORCTL;
3205 __IO uint32_t BODCTL;
3206 __I uint32_t RESERVE5[1];
3209 __IO uint32_t IVREFCTL;
3210 __IO uint32_t LDOCTL;
3211 __IO uint32_t BATDIVCTL;
3212 __I uint32_t RESERVE6[1];
3215 __I uint32_t WKSTS;
3216 __IO uint32_t IRC0TCTL;
3217 __IO uint32_t IRC0TIEN;
3218 __IO uint32_t IRC0TISTS;
3219 __I uint32_t RESERVE7[1];
3222 __IO uint32_t IRC1TCTL;
3223 __IO uint32_t IRC1TIEN;
3224 __IO uint32_t IRC1TISTS;
3225 __I uint32_t RESERVE8[1];
3228 __IO uint32_t MIRCTCTL;
3229 __IO uint32_t MIRCTIEN;
3230 __IO uint32_t MIRCTISTS;
3231 __I uint32_t RESERVE9[21];
3234 __O uint32_t REGLCTL;
3235 __I uint32_t RESERVE10[7];
3238 __IO uint32_t RPDBCLK;
3240 } SYS_T;
3241
3247 #define SYS_PDID_PDID_Pos (0)
3248 #define SYS_PDID_PDID_Msk (0xfffffffful << SYS_PDID_PDID_Pos)
3250 #define SYS_RSTSTS_PORF_Pos (0)
3251 #define SYS_RSTSTS_PORF_Msk (0x1ul << SYS_RSTSTS_PORF_Pos)
3253 #define SYS_RSTSTS_PINRF_Pos (1)
3254 #define SYS_RSTSTS_PINRF_Msk (0x1ul << SYS_RSTSTS_PINRF_Pos)
3256 #define SYS_RSTSTS_WDTRF_Pos (2)
3257 #define SYS_RSTSTS_WDTRF_Msk (0x1ul << SYS_RSTSTS_WDTRF_Pos)
3259 #define SYS_RSTSTS_LVRF_Pos (3)
3260 #define SYS_RSTSTS_LVRF_Msk (0x1ul << SYS_RSTSTS_LVRF_Pos)
3262 #define SYS_RSTSTS_BODRF_Pos (4)
3263 #define SYS_RSTSTS_BODRF_Msk (0x1ul << SYS_RSTSTS_BODRF_Pos)
3265 #define SYS_RSTSTS_SYSRF_Pos (5)
3266 #define SYS_RSTSTS_SYSRF_Msk (0x1ul << SYS_RSTSTS_SYSRF_Pos)
3268 #define SYS_RSTSTS_CPURF_Pos (7)
3269 #define SYS_RSTSTS_CPURF_Msk (0x1ul << SYS_RSTSTS_CPURF_Pos)
3271 #define SYS_RSTSTS_LOCKRF_Pos (8)
3272 #define SYS_RSTSTS_LOCKRF_Msk (0x1ul << SYS_RSTSTS_LOCKRF_Pos)
3274 #define SYS_IPRST1_CHIPRST_Pos (0)
3275 #define SYS_IPRST1_CHIPRST_Msk (0x1ul << SYS_IPRST1_CHIPRST_Pos)
3277 #define SYS_IPRST1_CPURST_Pos (1)
3278 #define SYS_IPRST1_CPURST_Msk (0x1ul << SYS_IPRST1_CPURST_Pos)
3280 #define SYS_IPRST1_PDMARST_Pos (2)
3281 #define SYS_IPRST1_PDMARST_Msk (0x1ul << SYS_IPRST1_PDMARST_Pos)
3283 #define SYS_IPRST2_GPIORST_Pos (1)
3284 #define SYS_IPRST2_GPIORST_Msk (0x1ul << SYS_IPRST2_GPIORST_Pos)
3286 #define SYS_IPRST2_TMR0RST_Pos (2)
3287 #define SYS_IPRST2_TMR0RST_Msk (0x1ul << SYS_IPRST2_TMR0RST_Pos)
3289 #define SYS_IPRST2_TMR1RST_Pos (3)
3290 #define SYS_IPRST2_TMR1RST_Msk (0x1ul << SYS_IPRST2_TMR1RST_Pos)
3292 #define SYS_IPRST2_TMR2RST_Pos (4)
3293 #define SYS_IPRST2_TMR2RST_Msk (0x1ul << SYS_IPRST2_TMR2RST_Pos)
3295 #define SYS_IPRST2_TMR3RST_Pos (5)
3296 #define SYS_IPRST2_TMR3RST_Msk (0x1ul << SYS_IPRST2_TMR3RST_Pos)
3298 #define SYS_IPRST2_I2C0RST_Pos (8)
3299 #define SYS_IPRST2_I2C0RST_Msk (0x1ul << SYS_IPRST2_I2C0RST_Pos)
3301 #define SYS_IPRST2_I2C1RST_Pos (9)
3302 #define SYS_IPRST2_I2C1RST_Msk (0x1ul << SYS_IPRST2_I2C1RST_Pos)
3304 #define SYS_IPRST2_SPI0RST_Pos (12)
3305 #define SYS_IPRST2_SPI0RST_Msk (0x1ul << SYS_IPRST2_SPI0RST_Pos)
3307 #define SYS_IPRST2_SPI1RST_Pos (13)
3308 #define SYS_IPRST2_SPI1RST_Msk (0x1ul << SYS_IPRST2_SPI1RST_Pos)
3310 #define SYS_IPRST2_SPI2RST_Pos (14)
3311 #define SYS_IPRST2_SPI2RST_Msk (0x1ul << SYS_IPRST2_SPI2RST_Pos)
3313 #define SYS_IPRST2_SPI3RST_Pos (15)
3314 #define SYS_IPRST2_SPI3RST_Msk (0x1ul << SYS_IPRST2_SPI3RST_Pos)
3316 #define SYS_IPRST2_UART0RST_Pos (16)
3317 #define SYS_IPRST2_UART0RST_Msk (0x1ul << SYS_IPRST2_UART0RST_Pos)
3319 #define SYS_IPRST2_UART1RST_Pos (17)
3320 #define SYS_IPRST2_UART1RST_Msk (0x1ul << SYS_IPRST2_UART1RST_Pos)
3322 #define SYS_IPRST2_PWM0RST_Pos (20)
3323 #define SYS_IPRST2_PWM0RST_Msk (0x1ul << SYS_IPRST2_PWM0RST_Pos)
3325 #define SYS_IPRST2_ACMP0RST_Pos (22)
3326 #define SYS_IPRST2_ACMP0RST_Msk (0x1ul << SYS_IPRST2_ACMP0RST_Pos)
3328 #define SYS_IPRST2_ADCRST_Pos (28)
3329 #define SYS_IPRST2_ADCRST_Msk (0x1ul << SYS_IPRST2_ADCRST_Pos)
3331 #define SYS_IPRST2_SC0RST_Pos (30)
3332 #define SYS_IPRST2_SC0RST_Msk (0x1ul << SYS_IPRST2_SC0RST_Pos)
3334 #define SYS_IPRST2_SC1RST_Pos (31)
3335 #define SYS_IPRST2_SC1RST_Msk (0x1ul << SYS_IPRST2_SC1RST_Pos)
3337 #define SYS_MISCCTL_POR33DIS_Pos (6)
3338 #define SYS_MISCCTL_POR33DIS_Msk (0x1ul << SYS_MISCCTL_POR33DIS_Pos)
3340 #define SYS_MISCCTL_POR18DIS_Pos (7)
3341 #define SYS_MISCCTL_POR18DIS_Msk (0x1ul << SYS_MISCCTL_POR18DIS_Pos)
3343 #define SYS_TEMPCTL_VTEMPEN_Pos (0)
3344 #define SYS_TEMPCTL_VTEMPEN_Msk (0x1ul << SYS_TEMPCTL_VTEMPEN_Pos)
3346 #define SYS_RCCFCTL_HIRC0FEN_Pos (0)
3347 #define SYS_RCCFCTL_HIRC0FEN_Msk (0x1ul << SYS_RCCFCTL_HIRC0FEN_Pos)
3349 #define SYS_RCCFCTL_HIRC1FEN_Pos (1)
3350 #define SYS_RCCFCTL_HIRC1FEN_Msk (0x1ul << SYS_RCCFCTL_HIRC1FEN_Pos)
3352 #define SYS_RCCFCTL_MRCFEN_Pos (2)
3353 #define SYS_RCCFCTL_MRCFEN_Msk (0x1ul << SYS_RCCFCTL_MRCFEN_Pos)
3355 #define SYS_GPA_MFPL_PA0MFP_Pos (0)
3356 #define SYS_GPA_MFPL_PA0MFP_Msk (0xful << SYS_GPA_MFPL_PA0MFP_Pos)
3358 #define SYS_GPA_MFPL_PA1MFP_Pos (4)
3359 #define SYS_GPA_MFPL_PA1MFP_Msk (0xful << SYS_GPA_MFPL_PA1MFP_Pos)
3361 #define SYS_GPA_MFPL_PA2MFP_Pos (8)
3362 #define SYS_GPA_MFPL_PA2MFP_Msk (0xful << SYS_GPA_MFPL_PA2MFP_Pos)
3364 #define SYS_GPA_MFPL_PA3MFP_Pos (12)
3365 #define SYS_GPA_MFPL_PA3MFP_Msk (0xful << SYS_GPA_MFPL_PA3MFP_Pos)
3367 #define SYS_GPA_MFPL_PA4MFP_Pos (16)
3368 #define SYS_GPA_MFPL_PA4MFP_Msk (0xful << SYS_GPA_MFPL_PA4MFP_Pos)
3370 #define SYS_GPA_MFPL_PA5MFP_Pos (20)
3371 #define SYS_GPA_MFPL_PA5MFP_Msk (0xful << SYS_GPA_MFPL_PA5MFP_Pos)
3373 #define SYS_GPA_MFPL_PA6MFP_Pos (24)
3374 #define SYS_GPA_MFPL_PA6MFP_Msk (0xful << SYS_GPA_MFPL_PA6MFP_Pos)
3376 #define SYS_GPA_MFPH_PA8MFP_Pos (0)
3377 #define SYS_GPA_MFPH_PA8MFP_Msk (0xful << SYS_GPA_MFPH_PA8MFP_Pos)
3379 #define SYS_GPA_MFPH_PA9MFP_Pos (4)
3380 #define SYS_GPA_MFPH_PA9MFP_Msk (0xful << SYS_GPA_MFPH_PA9MFP_Pos)
3382 #define SYS_GPA_MFPH_PA10MFP_Pos (8)
3383 #define SYS_GPA_MFPH_PA10MFP_Msk (0xful << SYS_GPA_MFPH_PA10MFP_Pos)
3385 #define SYS_GPA_MFPH_PA11MFP_Pos (12)
3386 #define SYS_GPA_MFPH_PA11MFP_Msk (0xful << SYS_GPA_MFPH_PA11MFP_Pos)
3388 #define SYS_GPA_MFPH_PA12MFP_Pos (16)
3389 #define SYS_GPA_MFPH_PA12MFP_Msk (0xful << SYS_GPA_MFPH_PA12MFP_Pos)
3391 #define SYS_GPA_MFPH_PA13MFP_Pos (20)
3392 #define SYS_GPA_MFPH_PA13MFP_Msk (0xful << SYS_GPA_MFPH_PA13MFP_Pos)
3394 #define SYS_GPA_MFPH_PA14MFP_Pos (24)
3395 #define SYS_GPA_MFPH_PA14MFP_Msk (0xful << SYS_GPA_MFPH_PA14MFP_Pos)
3397 #define SYS_GPA_MFPH_PA15MFP_Pos (28)
3398 #define SYS_GPA_MFPH_PA15MFP_Msk (0xful << SYS_GPA_MFPH_PA15MFP_Pos)
3400 #define SYS_GPB_MFPL_PB0MFP_Pos (0)
3401 #define SYS_GPB_MFPL_PB0MFP_Msk (0xful << SYS_GPB_MFPL_PB0MFP_Pos)
3403 #define SYS_GPB_MFPL_PB1MFP_Pos (4)
3404 #define SYS_GPB_MFPL_PB1MFP_Msk (0xful << SYS_GPB_MFPL_PB1MFP_Pos)
3406 #define SYS_GPB_MFPL_PB2MFP_Pos (8)
3407 #define SYS_GPB_MFPL_PB2MFP_Msk (0xful << SYS_GPB_MFPL_PB2MFP_Pos)
3409 #define SYS_GPB_MFPL_PB3MFP_Pos (12)
3410 #define SYS_GPB_MFPL_PB3MFP_Msk (0xful << SYS_GPB_MFPL_PB3MFP_Pos)
3412 #define SYS_GPB_MFPL_PB4MFP_Pos (16)
3413 #define SYS_GPB_MFPL_PB4MFP_Msk (0xful << SYS_GPB_MFPL_PB4MFP_Pos)
3415 #define SYS_GPB_MFPL_PB5MFP_Pos (20)
3416 #define SYS_GPB_MFPL_PB5MFP_Msk (0xful << SYS_GPB_MFPL_PB5MFP_Pos)
3418 #define SYS_GPB_MFPL_PB6MFP_Pos (24)
3419 #define SYS_GPB_MFPL_PB6MFP_Msk (0xful << SYS_GPB_MFPL_PB6MFP_Pos)
3421 #define SYS_GPB_MFPL_PB7MFP_Pos (28)
3422 #define SYS_GPB_MFPL_PB7MFP_Msk (0xful << SYS_GPB_MFPL_PB7MFP_Pos)
3424 #define SYS_GPB_MFPH_PB8MFP_Pos (0)
3425 #define SYS_GPB_MFPH_PB8MFP_Msk (0xful << SYS_GPB_MFPH_PB8MFP_Pos)
3427 #define SYS_GPB_MFPH_PB9MFP_Pos (4)
3428 #define SYS_GPB_MFPH_PB9MFP_Msk (0xful << SYS_GPB_MFPH_PB9MFP_Pos)
3430 #define SYS_GPB_MFPH_PB10MFP_Pos (8)
3431 #define SYS_GPB_MFPH_PB10MFP_Msk (0xful << SYS_GPB_MFPH_PB10MFP_Pos)
3433 #define SYS_GPB_MFPH_PB11MFP_Pos (12)
3434 #define SYS_GPB_MFPH_PB11MFP_Msk (0xful << SYS_GPB_MFPH_PB11MFP_Pos)
3436 #define SYS_GPB_MFPH_PB13MFP_Pos (20)
3437 #define SYS_GPB_MFPH_PB13MFP_Msk (0xful << SYS_GPB_MFPH_PB13MFP_Pos)
3439 #define SYS_GPB_MFPH_PB14MFP_Pos (24)
3440 #define SYS_GPB_MFPH_PB14MFP_Msk (0xful << SYS_GPB_MFPH_PB14MFP_Pos)
3442 #define SYS_GPB_MFPH_PB15MFP_Pos (28)
3443 #define SYS_GPB_MFPH_PB15MFP_Msk (0xful << SYS_GPB_MFPH_PB15MFP_Pos)
3445 #define SYS_GPC_MFPL_PC0MFP_Pos (0)
3446 #define SYS_GPC_MFPL_PC0MFP_Msk (0xful << SYS_GPC_MFPL_PC0MFP_Pos)
3448 #define SYS_GPC_MFPL_PC1MFP_Pos (4)
3449 #define SYS_GPC_MFPL_PC1MFP_Msk (0xful << SYS_GPC_MFPL_PC1MFP_Pos)
3451 #define SYS_GPC_MFPL_PC2MFP_Pos (8)
3452 #define SYS_GPC_MFPL_PC2MFP_Msk (0xful << SYS_GPC_MFPL_PC2MFP_Pos)
3454 #define SYS_GPC_MFPL_PC3MFP_Pos (12)
3455 #define SYS_GPC_MFPL_PC3MFP_Msk (0xful << SYS_GPC_MFPL_PC3MFP_Pos)
3457 #define SYS_GPC_MFPL_PC6MFP_Pos (24)
3458 #define SYS_GPC_MFPL_PC6MFP_Msk (0xful << SYS_GPC_MFPL_PC6MFP_Pos)
3460 #define SYS_GPC_MFPL_PC7MFP_Pos (28)
3461 #define SYS_GPC_MFPL_PC7MFP_Msk (0xful << SYS_GPC_MFPL_PC7MFP_Pos)
3463 #define SYS_GPC_MFPH_PC8MFP_Pos (0)
3464 #define SYS_GPC_MFPH_PC8MFP_Msk (0xful << SYS_GPC_MFPH_PC8MFP_Pos)
3466 #define SYS_GPC_MFPH_PC9MFP_Pos (4)
3467 #define SYS_GPC_MFPH_PC9MFP_Msk (0xful << SYS_GPC_MFPH_PC9MFP_Pos)
3469 #define SYS_GPC_MFPH_PC10MFP_Pos (8)
3470 #define SYS_GPC_MFPH_PC10MFP_Msk (0xful << SYS_GPC_MFPH_PC10MFP_Pos)
3472 #define SYS_GPC_MFPH_PC11MFP_Pos (12)
3473 #define SYS_GPC_MFPH_PC11MFP_Msk (0xful << SYS_GPC_MFPH_PC11MFP_Pos)
3475 #define SYS_GPC_MFPH_PC14MFP_Pos (24)
3476 #define SYS_GPC_MFPH_PC14MFP_Msk (0xful << SYS_GPC_MFPH_PC14MFP_Pos)
3478 #define SYS_GPC_MFPH_PC15MFP_Pos (28)
3479 #define SYS_GPC_MFPH_PC15MFP_Msk (0xful << SYS_GPC_MFPH_PC15MFP_Pos)
3481 #define SYS_GPD_MFPL_PD6MFP_Pos (24)
3482 #define SYS_GPD_MFPL_PD6MFP_Msk (0xful << SYS_GPD_MFPL_PD6MFP_Pos)
3484 #define SYS_GPD_MFPL_PD7MFP_Pos (28)
3485 #define SYS_GPD_MFPL_PD7MFP_Msk (0xful << SYS_GPD_MFPL_PD7MFP_Pos)
3487 #define SYS_GPD_MFPH_PD14MFP_Pos (24)
3488 #define SYS_GPD_MFPH_PD14MFP_Msk (0xful << SYS_GPD_MFPH_PD14MFP_Pos)
3490 #define SYS_GPD_MFPH_PD15MFP_Pos (28)
3491 #define SYS_GPD_MFPH_PD15MFP_Msk (0x7ul << SYS_GPD_MFPH_PD15MFP_Pos)
3493 #define SYS_GPE_MFPL_PE5MFP_Pos (20)
3494 #define SYS_GPE_MFPL_PE5MFP_Msk (0xful << SYS_GPE_MFPL_PE5MFP_Pos)
3496 #define SYS_GPF_MFPL_PF0MFP_Pos (0)
3497 #define SYS_GPF_MFPL_PF0MFP_Msk (0xful << SYS_GPF_MFPL_PF0MFP_Pos)
3499 #define SYS_GPF_MFPL_PF1MFP_Pos (4)
3500 #define SYS_GPF_MFPL_PF1MFP_Msk (0xful << SYS_GPF_MFPL_PF1MFP_Pos)
3502 #define SYS_GPF_MFPL_PF2MFP_Pos (8)
3503 #define SYS_GPF_MFPL_PF2MFP_Msk (0xful << SYS_GPF_MFPL_PF2MFP_Pos)
3505 #define SYS_GPF_MFPL_PF3MFP_Pos (12)
3506 #define SYS_GPF_MFPL_PF3MFP_Msk (0xful << SYS_GPF_MFPL_PF3MFP_Pos)
3508 #define SYS_GPF_MFPL_PF6MFP_Pos (24)
3509 #define SYS_GPF_MFPL_PF6MFP_Msk (0xful << SYS_GPF_MFPL_PF6MFP_Pos)
3511 #define SYS_GPF_MFPL_PF7MFP_Pos (28)
3512 #define SYS_GPF_MFPL_PF7MFP_Msk (0xful << SYS_GPF_MFPL_PF7MFP_Pos)
3514 #define SYS_PORCTL_POROFF_Pos (0)
3515 #define SYS_PORCTL_POROFF_Msk (0xfffful << SYS_PORCTL_POROFF_Pos)
3517 #define SYS_BODCTL_BODEN_Pos (0)
3518 #define SYS_BODCTL_BODEN_Msk (0x1ul << SYS_BODCTL_BODEN_Pos)
3520 #define SYS_BODCTL_BODIE_Pos (2)
3521 #define SYS_BODCTL_BODIE_Msk (0x1ul << SYS_BODCTL_BODIE_Pos)
3523 #define SYS_BODCTL_BODREN_Pos (3)
3524 #define SYS_BODCTL_BODREN_Msk (0x1ul << SYS_BODCTL_BODREN_Pos)
3526 #define SYS_BODCTL_BODIF_Pos (4)
3527 #define SYS_BODCTL_BODIF_Msk (0x1ul << SYS_BODCTL_BODIF_Pos)
3529 #define SYS_BODCTL_BODOUT_Pos (6)
3530 #define SYS_BODCTL_BODOUT_Msk (0x1ul << SYS_BODCTL_BODOUT_Pos)
3532 #define SYS_BODCTL_LVREN_Pos (7)
3533 #define SYS_BODCTL_LVREN_Msk (0x1ul << SYS_BODCTL_LVREN_Pos)
3535 #define SYS_BODCTL_LPBODEN_Pos (8)
3536 #define SYS_BODCTL_LPBODEN_Msk (0x1ul << SYS_BODCTL_LPBODEN_Pos)
3538 #define SYS_BODCTL_LPBODVL_Pos (9)
3539 #define SYS_BODCTL_LPBODVL_Msk (0x1ul << SYS_BODCTL_LPBODVL_Pos)
3541 #define SYS_BODCTL_LPBODIE_Pos (10)
3542 #define SYS_BODCTL_LPBODIE_Msk (0x1ul << SYS_BODCTL_LPBODIE_Pos)
3544 #define SYS_BODCTL_LPBODREN_Pos (11)
3545 #define SYS_BODCTL_LPBODREN_Msk (0x1ul << SYS_BODCTL_LPBODREN_Pos)
3547 #define SYS_BODCTL_BODVL_Pos (12)
3548 #define SYS_BODCTL_BODVL_Msk (0xful << SYS_BODCTL_BODVL_Pos)
3550 #define SYS_BODCTL_LPBOD20TRIM_Pos (16)
3551 #define SYS_BODCTL_LPBOD20TRIM_Msk (0xful << SYS_BODCTL_LPBOD20TRIM_Pos)
3553 #define SYS_BODCTL_LPBOD25TRIM_Pos (20)
3554 #define SYS_BODCTL_LPBOD25TRIM_Msk (0xful << SYS_BODCTL_LPBOD25TRIM_Pos)
3556 #define SYS_BODCTL_BODDGSEL_Pos (24)
3557 #define SYS_BODCTL_BODDGSEL_Msk (0x7ul << SYS_BODCTL_BODDGSEL_Pos)
3559 #define SYS_BODCTL_LVRDGSEL_Pos (28)
3560 #define SYS_BODCTL_LVRDGSEL_Msk (0x7ul << SYS_BODCTL_LVRDGSEL_Pos)
3562 #define SYS_IVREFCTL_BGPEN_Pos (0)
3563 #define SYS_IVREFCTL_BGPEN_Msk (0x1ul << SYS_IVREFCTL_BGPEN_Pos)
3565 #define SYS_IVREFCTL_REGEN_Pos (1)
3566 #define SYS_IVREFCTL_REGEN_Msk (0x1ul << SYS_IVREFCTL_REGEN_Pos)
3568 #define SYS_IVREFCTL_SEL25_Pos (2)
3569 #define SYS_IVREFCTL_SEL25_Msk (0x3ul << SYS_IVREFCTL_SEL25_Pos)
3571 #define SYS_IVREFCTL_EXTMODE_Pos (4)
3572 #define SYS_IVREFCTL_EXTMODE_Msk (0x1ul << SYS_IVREFCTL_EXTMODE_Pos)
3574 #define SYS_IVREFCTL_VREFTRIM_Pos (8)
3575 #define SYS_IVREFCTL_VREFTRIM_Msk (0xful << SYS_IVREFCTL_VREFTRIM_Pos)
3577 #define SYS_LDOCTL_FASTWK_Pos (1)
3578 #define SYS_LDOCTL_FASTWK_Msk (0x1ul << SYS_LDOCTL_FASTWK_Pos)
3580 #define SYS_LDOCTL_LDOLVL_Pos (2)
3581 #define SYS_LDOCTL_LDOLVL_Msk (0x3ul << SYS_LDOCTL_LDOLVL_Pos)
3583 #define SYS_LDOCTL_LPRMEN_Pos (4)
3584 #define SYS_LDOCTL_LPRMEN_Msk (0x1ul << SYS_LDOCTL_LPRMEN_Pos)
3586 #define SYS_LDOCTL_FMCLVEN_Pos (5)
3587 #define SYS_LDOCTL_FMCLVEN_Msk (0x1ul << SYS_LDOCTL_FMCLVEN_Pos)
3589 #define SYS_BATDIVCTL_BATDIV2EN_Pos (0)
3590 #define SYS_BATDIVCTL_BATDIV2EN_Msk (0x1ul << SYS_BATDIVCTL_BATDIV2EN_Pos)
3592 #define SYS_WKSTS_ACMPWK_Pos (0)
3593 #define SYS_WKSTS_ACMPWK_Msk (0x1ul << SYS_WKSTS_ACMPWK_Pos)
3595 #define SYS_WKSTS_I2C1WK_Pos (1)
3596 #define SYS_WKSTS_I2C1WK_Msk (0x1ul << SYS_WKSTS_I2C1WK_Pos)
3598 #define SYS_WKSTS_I2C0WK_Pos (2)
3599 #define SYS_WKSTS_I2C0WK_Msk (0x1ul << SYS_WKSTS_I2C0WK_Pos)
3601 #define SYS_WKSTS_TMR3WK_Pos (3)
3602 #define SYS_WKSTS_TMR3WK_Msk (0x1ul << SYS_WKSTS_TMR3WK_Pos)
3604 #define SYS_WKSTS_TMR2WK_Pos (4)
3605 #define SYS_WKSTS_TMR2WK_Msk (0x1ul << SYS_WKSTS_TMR2WK_Pos)
3607 #define SYS_WKSTS_TMR1WK_Pos (5)
3608 #define SYS_WKSTS_TMR1WK_Msk (0x1ul << SYS_WKSTS_TMR1WK_Pos)
3610 #define SYS_WKSTS_TMR0WK_Pos (6)
3611 #define SYS_WKSTS_TMR0WK_Msk (0x1ul << SYS_WKSTS_TMR0WK_Pos)
3613 #define SYS_WKSTS_WDTWK_Pos (7)
3614 #define SYS_WKSTS_WDTWK_Msk (0x1ul << SYS_WKSTS_WDTWK_Pos)
3616 #define SYS_WKSTS_BODWK_Pos (8)
3617 #define SYS_WKSTS_BODWK_Msk (0x1ul << SYS_WKSTS_BODWK_Pos)
3619 #define SYS_WKSTS_SPI3WK_Pos (9)
3620 #define SYS_WKSTS_SPI3WK_Msk (0x1ul << SYS_WKSTS_SPI3WK_Pos)
3622 #define SYS_WKSTS_SPI2WK_Pos (10)
3623 #define SYS_WKSTS_SPI2WK_Msk (0x1ul << SYS_WKSTS_SPI2WK_Pos)
3625 #define SYS_WKSTS_SPI1WK_Pos (11)
3626 #define SYS_WKSTS_SPI1WK_Msk (0x1ul << SYS_WKSTS_SPI1WK_Pos)
3628 #define SYS_WKSTS_SPI0WK_Pos (12)
3629 #define SYS_WKSTS_SPI0WK_Msk (0x1ul << SYS_WKSTS_SPI0WK_Pos)
3631 #define SYS_WKSTS_UART1WK_Pos (13)
3632 #define SYS_WKSTS_UART1WK_Msk (0x1ul << SYS_WKSTS_UART1WK_Pos)
3634 #define SYS_WKSTS_UART0WK_Pos (14)
3635 #define SYS_WKSTS_UART0WK_Msk (0x1ul << SYS_WKSTS_UART0WK_Pos)
3637 #define SYS_WKSTS_RTCWK_Pos (15)
3638 #define SYS_WKSTS_RTCWK_Msk (0x1ul << SYS_WKSTS_RTCWK_Pos)
3640 #define SYS_WKSTS_GPIOWK_Pos (16)
3641 #define SYS_WKSTS_GPIOWK_Msk (0x1ul << SYS_WKSTS_GPIOWK_Pos)
3643 #define SYS_IRC0TCTL_FREQSEL_Pos (0)
3644 #define SYS_IRC0TCTL_FREQSEL_Msk (0x7ul << SYS_IRC0TCTL_FREQSEL_Pos)
3646 #define SYS_IRC0TCTL_LOOPSEL_Pos (4)
3647 #define SYS_IRC0TCTL_LOOPSEL_Msk (0x3ul << SYS_IRC0TCTL_LOOPSEL_Pos)
3649 #define SYS_IRC0TCTL_RETRYCNT_Pos (6)
3650 #define SYS_IRC0TCTL_RETRYCNT_Msk (0x3ul << SYS_IRC0TCTL_RETRYCNT_Pos)
3652 #define SYS_IRC0TCTL_CESTOPEN_Pos (8)
3653 #define SYS_IRC0TCTL_CESTOPEN_Msk (0x1ul << SYS_IRC0TCTL_CESTOPEN_Pos)
3655 #define SYS_IRC0TIEN_TFAILIEN_Pos (1)
3656 #define SYS_IRC0TIEN_TFAILIEN_Msk (0x1ul << SYS_IRC0TIEN_TFAILIEN_Pos)
3658 #define SYS_IRC0TIEN_CLKEIEN_Pos (2)
3659 #define SYS_IRC0TIEN_CLKEIEN_Msk (0x1ul << SYS_IRC0TIEN_CLKEIEN_Pos)
3661 #define SYS_IRC0TISTS_FREQLOCK_Pos (0)
3662 #define SYS_IRC0TISTS_FREQLOCK_Msk (0x1ul << SYS_IRC0TISTS_FREQLOCK_Pos)
3664 #define SYS_IRC0TISTS_TFAILIF_Pos (1)
3665 #define SYS_IRC0TISTS_TFAILIF_Msk (0x1ul << SYS_IRC0TISTS_TFAILIF_Pos)
3667 #define SYS_IRC0TISTS_CLKERRIF_Pos (2)
3668 #define SYS_IRC0TISTS_CLKERRIF_Msk (0x1ul << SYS_IRC0TISTS_CLKERRIF_Pos)
3670 #define SYS_IRC1TCTL_FREQSEL_Pos (0)
3671 #define SYS_IRC1TCTL_FREQSEL_Msk (0x3ul << SYS_IRC1TCTL_FREQSEL_Pos)
3673 #define SYS_IRC1TCTL_LOOPSEL_Pos (4)
3674 #define SYS_IRC1TCTL_LOOPSEL_Msk (0x3ul << SYS_IRC1TCTL_LOOPSEL_Pos)
3676 #define SYS_IRC1TCTL_RETRYCNT_Pos (6)
3677 #define SYS_IRC1TCTL_RETRYCNT_Msk (0x3ul << SYS_IRC1TCTL_RETRYCNT_Pos)
3679 #define SYS_IRC1TCTL_CESTOPEN_Pos (8)
3680 #define SYS_IRC1TCTL_CESTOPEN_Msk (0x1ul << SYS_IRC1TCTL_CESTOPEN_Pos)
3682 #define SYS_IRC1TIEN_TFAILIEN_Pos (1)
3683 #define SYS_IRC1TIEN_TFAILIEN_Msk (0x1ul << SYS_IRC1TIEN_TFAILIEN_Pos)
3685 #define SYS_IRC1TIEN_CLKEIEN_Pos (2)
3686 #define SYS_IRC1TIEN_CLKEIEN_Msk (0x1ul << SYS_IRC1TIEN_CLKEIEN_Pos)
3688 #define SYS_IRC1TISTS_FREQLOCK_Pos (0)
3689 #define SYS_IRC1TISTS_FREQLOCK_Msk (0x1ul << SYS_IRC1TISTS_FREQLOCK_Pos)
3691 #define SYS_IRC1TISTS_TFAILIF_Pos (1)
3692 #define SYS_IRC1TISTS_TFAILIF_Msk (0x1ul << SYS_IRC1TISTS_TFAILIF_Pos)
3694 #define SYS_IRC1TISTS_CLKERRIF_Pos (2)
3695 #define SYS_IRC1TISTS_CLKERRIF_Msk (0x1ul << SYS_IRC1TISTS_CLKERRIF_Pos)
3697 #define SYS_MIRCTCTL_FREQSEL_Pos (0)
3698 #define SYS_MIRCTCTL_FREQSEL_Msk (0x3ul << SYS_MIRCTCTL_FREQSEL_Pos)
3700 #define SYS_MIRCTCTL_LOOPSEL_Pos (4)
3701 #define SYS_MIRCTCTL_LOOPSEL_Msk (0x3ul << SYS_MIRCTCTL_LOOPSEL_Pos)
3703 #define SYS_MIRCTCTL_RETRYCNT_Pos (6)
3704 #define SYS_MIRCTCTL_RETRYCNT_Msk (0x3ul << SYS_MIRCTCTL_RETRYCNT_Pos)
3706 #define SYS_MIRCTCTL_CESTOPEN_Pos (8)
3707 #define SYS_MIRCTCTL_CESTOPEN_Msk (0x1ul << SYS_MIRCTCTL_CESTOPEN_Pos)
3709 #define SYS_MIRCTIEN_TFAILIEN_Pos (1)
3710 #define SYS_MIRCTIEN_TFAILIEN_Msk (0x1ul << SYS_MIRCTIEN_TFAILIEN_Pos)
3712 #define SYS_MIRCTIEN_CLKEIEN_Pos (2)
3713 #define SYS_MIRCTIEN_CLKEIEN_Msk (0x1ul << SYS_MIRCTIEN_CLKEIEN_Pos)
3715 #define SYS_MIRCTISTS_FREQLOCK_Pos (0)
3716 #define SYS_MIRCTISTS_FREQLOCK_Msk (0x1ul << SYS_MIRCTISTS_FREQLOCK_Pos)
3718 #define SYS_MIRCTISTS_TFAILIF_Pos (1)
3719 #define SYS_MIRCTISTS_TFAILIF_Msk (0x1ul << SYS_MIRCTISTS_TFAILIF_Pos)
3721 #define SYS_MIRCTISTS_CLKERRIF_Pos (2)
3722 #define SYS_MIRCTISTS_CLKERRIF_Msk (0x1ul << SYS_MIRCTISTS_CLKERRIF_Pos)
3724 #define SYS_REGLCTL_REGLCTL_Pos (0)
3725 #define SYS_REGLCTL_REGLCTL_Msk (0x1ul << SYS_REGLCTL_REGLCTL_Pos)
3727 #define SYS_RPDBCLK_RSTPDBCLK_Pos (6)
3728 #define SYS_RPDBCLK_RSTPDBCLK_Msk (0x1ul << SYS_RPDBCLK_RSTPDBCLK_Pos) /* SYS_CONST */
3731 /* end of SYS register group */
3732
3733
3734 /*---------------------- System Clock Controller -------------------------*/
3740 typedef struct
3741 {
3742
3743
4901 __IO uint32_t PWRCTL;
4902 __IO uint32_t AHBCLK;
4903 __IO uint32_t APBCLK;
4904 __I uint32_t STATUS;
4905 __IO uint32_t CLKSEL0;
4906 __IO uint32_t CLKSEL1;
4907 __IO uint32_t CLKSEL2;
4908 __IO uint32_t CLKDIV0;
4909 __IO uint32_t CLKDIV1;
4910 __IO uint32_t PLLCTL;
4911 __IO uint32_t CLKOCTL;
4912 __I uint32_t RESERVE0[1];
4915 __IO uint32_t WKINTSTS;
4916 __IO uint32_t APBDIV;
4917 __IO uint32_t CLKDCTL;
4918 __IO uint32_t CLKDIE;
4919 __IO uint32_t CLKDSTS;
4920 __IO uint32_t CDUPB;
4921 __IO uint32_t CDLOWB;
4922 } CLK_T;
4923
4929 #define CLK_PWRCTL_HXTEN_Pos (0)
4930 #define CLK_PWRCTL_HXTEN_Msk (0x1ul << CLK_PWRCTL_HXTEN_Pos)
4932 #define CLK_PWRCTL_LXTEN_Pos (1)
4933 #define CLK_PWRCTL_LXTEN_Msk (0x1ul << CLK_PWRCTL_LXTEN_Pos)
4935 #define CLK_PWRCTL_HIRC0EN_Pos (2)
4936 #define CLK_PWRCTL_HIRC0EN_Msk (0x1ul << CLK_PWRCTL_HIRC0EN_Pos)
4938 #define CLK_PWRCTL_LIRCEN_Pos (3)
4939 #define CLK_PWRCTL_LIRCEN_Msk (0x1ul << CLK_PWRCTL_LIRCEN_Pos)
4941 #define CLK_PWRCTL_PDWKDLY_Pos (4)
4942 #define CLK_PWRCTL_PDWKDLY_Msk (0x1ul << CLK_PWRCTL_PDWKDLY_Pos)
4944 #define CLK_PWRCTL_PDWKIEN_Pos (5)
4945 #define CLK_PWRCTL_PDWKIEN_Msk (0x1ul << CLK_PWRCTL_PDWKIEN_Pos)
4947 #define CLK_PWRCTL_PDEN_Pos (6)
4948 #define CLK_PWRCTL_PDEN_Msk (0x1ul << CLK_PWRCTL_PDEN_Pos)
4950 #define CLK_PWRCTL_HXTSLTYP_Pos (8)
4951 #define CLK_PWRCTL_HXTSLTYP_Msk (0x1ul << CLK_PWRCTL_HXTSLTYP_Pos)
4953 #define CLK_PWRCTL_HXTGAIN_Pos (10)
4954 #define CLK_PWRCTL_HXTGAIN_Msk (0x7ul << CLK_PWRCTL_HXTGAIN_Pos)
4956 #define CLK_PWRCTL_HIRC0FSEL_Pos (13)
4957 #define CLK_PWRCTL_HIRC0FSEL_Msk (0x1ul << CLK_PWRCTL_HIRC0FSEL_Pos)
4959 #define CLK_PWRCTL_HIRC0FSTOP_Pos (14)
4960 #define CLK_PWRCTL_HIRC0FSTOP_Msk (0x1ul << CLK_PWRCTL_HIRC0FSTOP_Pos)
4962 #define CLK_PWRCTL_HIRC1EN_Pos (24)
4963 #define CLK_PWRCTL_HIRC1EN_Msk (0x1ul << CLK_PWRCTL_HIRC1EN_Pos)
4965 #define CLK_PWRCTL_MIRCEN_Pos (25)
4966 #define CLK_PWRCTL_MIRCEN_Msk (0x1ul << CLK_PWRCTL_MIRCEN_Pos)
4968 #define CLK_AHBCLK_GPIOCKEN_Pos (0)
4969 #define CLK_AHBCLK_GPIOCKEN_Msk (0x1ul << CLK_AHBCLK_GPIOCKEN_Pos)
4971 #define CLK_AHBCLK_PDMACKEN_Pos (1)
4972 #define CLK_AHBCLK_PDMACKEN_Msk (0x1ul << CLK_AHBCLK_PDMACKEN_Pos)
4974 #define CLK_AHBCLK_ISPCKEN_Pos (2)
4975 #define CLK_AHBCLK_ISPCKEN_Msk (0x1ul << CLK_AHBCLK_ISPCKEN_Pos)
4977 #define CLK_AHBCLK_SRAMCKEN_Pos (4)
4978 #define CLK_AHBCLK_SRAMCKEN_Msk (0x1ul << CLK_AHBCLK_SRAMCKEN_Pos)
4980 #define CLK_AHBCLK_STCKEN_Pos (5)
4981 #define CLK_AHBCLK_STCKEN_Msk (0x1ul << CLK_AHBCLK_STCKEN_Pos)
4983 #define CLK_APBCLK_WDTCKEN_Pos (0)
4984 #define CLK_APBCLK_WDTCKEN_Msk (0x1ul << CLK_APBCLK_WDTCKEN_Pos)
4986 #define CLK_APBCLK_RTCCKEN_Pos (1)
4987 #define CLK_APBCLK_RTCCKEN_Msk (0x1ul << CLK_APBCLK_RTCCKEN_Pos)
4989 #define CLK_APBCLK_TMR0CKEN_Pos (2)
4990 #define CLK_APBCLK_TMR0CKEN_Msk (0x1ul << CLK_APBCLK_TMR0CKEN_Pos)
4992 #define CLK_APBCLK_TMR1CKEN_Pos (3)
4993 #define CLK_APBCLK_TMR1CKEN_Msk (0x1ul << CLK_APBCLK_TMR1CKEN_Pos)
4995 #define CLK_APBCLK_TMR2CKEN_Pos (4)
4996 #define CLK_APBCLK_TMR2CKEN_Msk (0x1ul << CLK_APBCLK_TMR2CKEN_Pos)
4998 #define CLK_APBCLK_TMR3CKEN_Pos (5)
4999 #define CLK_APBCLK_TMR3CKEN_Msk (0x1ul << CLK_APBCLK_TMR3CKEN_Pos)
5001 #define CLK_APBCLK_CLKOCKEN_Pos (6)
5002 #define CLK_APBCLK_CLKOCKEN_Msk (0x1ul << CLK_APBCLK_CLKOCKEN_Pos)
5004 #define CLK_APBCLK_I2C0CKEN_Pos (8)
5005 #define CLK_APBCLK_I2C0CKEN_Msk (0x1ul << CLK_APBCLK_I2C0CKEN_Pos)
5007 #define CLK_APBCLK_I2C1CKEN_Pos (9)
5008 #define CLK_APBCLK_I2C1CKEN_Msk (0x1ul << CLK_APBCLK_I2C1CKEN_Pos)
5010 #define CLK_APBCLK_ACMP0CKEN_Pos (11)
5011 #define CLK_APBCLK_ACMP0CKEN_Msk (0x1ul << CLK_APBCLK_ACMP0CKEN_Pos)
5013 #define CLK_APBCLK_SPI0CKEN_Pos (12)
5014 #define CLK_APBCLK_SPI0CKEN_Msk (0x1ul << CLK_APBCLK_SPI0CKEN_Pos)
5016 #define CLK_APBCLK_SPI1CKEN_Pos (13)
5017 #define CLK_APBCLK_SPI1CKEN_Msk (0x1ul << CLK_APBCLK_SPI1CKEN_Pos)
5019 #define CLK_APBCLK_SPI2CKEN_Pos (14)
5020 #define CLK_APBCLK_SPI2CKEN_Msk (0x1ul << CLK_APBCLK_SPI2CKEN_Pos)
5022 #define CLK_APBCLK_SPI3CKEN_Pos (15)
5023 #define CLK_APBCLK_SPI3CKEN_Msk (0x1ul << CLK_APBCLK_SPI3CKEN_Pos)
5025 #define CLK_APBCLK_UART0CKEN_Pos (16)
5026 #define CLK_APBCLK_UART0CKEN_Msk (0x1ul << CLK_APBCLK_UART0CKEN_Pos)
5028 #define CLK_APBCLK_UART1CKEN_Pos (17)
5029 #define CLK_APBCLK_UART1CKEN_Msk (0x1ul << CLK_APBCLK_UART1CKEN_Pos)
5031 #define CLK_APBCLK_PWM0CKEN_Pos (20)
5032 #define CLK_APBCLK_PWM0CKEN_Msk (0x1ul << CLK_APBCLK_PWM0CKEN_Pos)
5034 #define CLK_APBCLK_ADCCKEN_Pos (28)
5035 #define CLK_APBCLK_ADCCKEN_Msk (0x1ul << CLK_APBCLK_ADCCKEN_Pos)
5037 #define CLK_APBCLK_SC0CKEN_Pos (30)
5038 #define CLK_APBCLK_SC0CKEN_Msk (0x1ul << CLK_APBCLK_SC0CKEN_Pos)
5040 #define CLK_APBCLK_SC1CKEN_Pos (31)
5041 #define CLK_APBCLK_SC1CKEN_Msk (0x1ul << CLK_APBCLK_SC1CKEN_Pos)
5043 #define CLK_STATUS_HXTSTB_Pos (0)
5044 #define CLK_STATUS_HXTSTB_Msk (0x1ul << CLK_STATUS_HXTSTB_Pos)
5046 #define CLK_STATUS_LXTSTB_Pos (1)
5047 #define CLK_STATUS_LXTSTB_Msk (0x1ul << CLK_STATUS_LXTSTB_Pos)
5049 #define CLK_STATUS_PLLSTB_Pos (2)
5050 #define CLK_STATUS_PLLSTB_Msk (0x1ul << CLK_STATUS_PLLSTB_Pos)
5052 #define CLK_STATUS_LIRCSTB_Pos (3)
5053 #define CLK_STATUS_LIRCSTB_Msk (0x1ul << CLK_STATUS_LIRCSTB_Pos)
5055 #define CLK_STATUS_HIRC0STB_Pos (4)
5056 #define CLK_STATUS_HIRC0STB_Msk (0x1ul << CLK_STATUS_HIRC0STB_Pos)
5058 #define CLK_STATUS_HIRC1STB_Pos (5)
5059 #define CLK_STATUS_HIRC1STB_Msk (0x1ul << CLK_STATUS_HIRC1STB_Pos)
5061 #define CLK_STATUS_MIRCSTB_Pos (6)
5062 #define CLK_STATUS_MIRCSTB_Msk (0x1ul << CLK_STATUS_MIRCSTB_Pos)
5064 #define CLK_STATUS_CLKSFAIL_Pos (7)
5065 #define CLK_STATUS_CLKSFAIL_Msk (0x1ul << CLK_STATUS_CLKSFAIL_Pos)
5067 #define CLK_CLKSEL0_HCLKSEL_Pos (0)
5068 #define CLK_CLKSEL0_HCLKSEL_Msk (0x7ul << CLK_CLKSEL0_HCLKSEL_Pos)
5070 #define CLK_CLKSEL0_HIRCSEL_Pos (3)
5071 #define CLK_CLKSEL0_HIRCSEL_Msk (0x1ul << CLK_CLKSEL0_HIRCSEL_Pos)
5073 #define CLK_CLKSEL0_ISPSEL_Pos (4)
5074 #define CLK_CLKSEL0_ISPSEL_Msk (0x1ul << CLK_CLKSEL0_ISPSEL_Pos)
5076 #define CLK_CLKSEL1_UART0SEL_Pos (0)
5077 #define CLK_CLKSEL1_UART0SEL_Msk (0x7ul << CLK_CLKSEL1_UART0SEL_Pos)
5079 #define CLK_CLKSEL1_PWM0SEL_Pos (4)
5080 #define CLK_CLKSEL1_PWM0SEL_Msk (0x1ul << CLK_CLKSEL1_PWM0SEL_Pos)
5082 #define CLK_CLKSEL1_TMR0SEL_Pos (8)
5083 #define CLK_CLKSEL1_TMR0SEL_Msk (0x7ul << CLK_CLKSEL1_TMR0SEL_Pos)
5085 #define CLK_CLKSEL1_TMR1SEL_Pos (12)
5086 #define CLK_CLKSEL1_TMR1SEL_Msk (0x7ul << CLK_CLKSEL1_TMR1SEL_Pos)
5088 #define CLK_CLKSEL1_ADCSEL_Pos (19)
5089 #define CLK_CLKSEL1_ADCSEL_Msk (0x7ul << CLK_CLKSEL1_ADCSEL_Pos)
5091 #define CLK_CLKSEL1_SPI0SEL_Pos (24)
5092 #define CLK_CLKSEL1_SPI0SEL_Msk (0x3ul << CLK_CLKSEL1_SPI0SEL_Pos)
5094 #define CLK_CLKSEL1_SPI2SEL_Pos (26)
5095 #define CLK_CLKSEL1_SPI2SEL_Msk (0x3ul << CLK_CLKSEL1_SPI2SEL_Pos)
5097 #define CLK_CLKSEL1_WDTSEL_Pos (28)
5098 #define CLK_CLKSEL1_WDTSEL_Msk (0x3ul << CLK_CLKSEL1_WDTSEL_Pos)
5100 #define CLK_CLKSEL1_WWDTSEL_Pos (30)
5101 #define CLK_CLKSEL1_WWDTSEL_Msk (0x3ul << CLK_CLKSEL1_WWDTSEL_Pos)
5103 #define CLK_CLKSEL2_UART1SEL_Pos (0)
5104 #define CLK_CLKSEL2_UART1SEL_Msk (0x7ul << CLK_CLKSEL2_UART1SEL_Pos)
5106 #define CLK_CLKSEL2_CLKOSEL_Pos (4)
5107 #define CLK_CLKSEL2_CLKOSEL_Msk (0x7ul << CLK_CLKSEL2_CLKOSEL_Pos)
5109 #define CLK_CLKSEL2_TMR2SEL_Pos (8)
5110 #define CLK_CLKSEL2_TMR2SEL_Msk (0x7ul << CLK_CLKSEL2_TMR2SEL_Pos)
5112 #define CLK_CLKSEL2_TMR3SEL_Pos (12)
5113 #define CLK_CLKSEL2_TMR3SEL_Msk (0x7ul << CLK_CLKSEL2_TMR3SEL_Pos)
5115 #define CLK_CLKSEL2_SC0SEL_Pos (16)
5116 #define CLK_CLKSEL2_SC0SEL_Msk (0x7ul << CLK_CLKSEL2_SC0SEL_Pos)
5118 #define CLK_CLKSEL2_SC1SEL_Pos (20)
5119 #define CLK_CLKSEL2_SC1SEL_Msk (0x7ul << CLK_CLKSEL2_SC1SEL_Pos)
5121 #define CLK_CLKSEL2_SPI1SEL_Pos (24)
5122 #define CLK_CLKSEL2_SPI1SEL_Msk (0x3ul << CLK_CLKSEL2_SPI1SEL_Pos)
5124 #define CLK_CLKSEL2_SPI3SEL_Pos (26)
5125 #define CLK_CLKSEL2_SPI3SEL_Msk (0x3ul << CLK_CLKSEL2_SPI3SEL_Pos)
5127 #define CLK_CLKDIV0_HCLKDIV_Pos (0)
5128 #define CLK_CLKDIV0_HCLKDIV_Msk (0xful << CLK_CLKDIV0_HCLKDIV_Pos)
5130 #define CLK_CLKDIV0_UART0DIV_Pos (8)
5131 #define CLK_CLKDIV0_UART0DIV_Msk (0xful << CLK_CLKDIV0_UART0DIV_Pos)
5133 #define CLK_CLKDIV0_UART1DIV_Pos (12)
5134 #define CLK_CLKDIV0_UART1DIV_Msk (0xful << CLK_CLKDIV0_UART1DIV_Pos)
5136 #define CLK_CLKDIV0_ADCDIV_Pos (16)
5137 #define CLK_CLKDIV0_ADCDIV_Msk (0xfful << CLK_CLKDIV0_ADCDIV_Pos)
5139 #define CLK_CLKDIV0_SC0DIV_Pos (28)
5140 #define CLK_CLKDIV0_SC0DIV_Msk (0xful << CLK_CLKDIV0_SC0DIV_Pos)
5142 #define CLK_CLKDIV1_SC1DIV_Pos (0)
5143 #define CLK_CLKDIV1_SC1DIV_Msk (0xful << CLK_CLKDIV1_SC1DIV_Pos)
5145 #define CLK_CLKDIV1_TMR0DIV_Pos (8)
5146 #define CLK_CLKDIV1_TMR0DIV_Msk (0xful << CLK_CLKDIV1_TMR0DIV_Pos)
5148 #define CLK_CLKDIV1_TMR1DIV_Pos (12)
5149 #define CLK_CLKDIV1_TMR1DIV_Msk (0xful << CLK_CLKDIV1_TMR1DIV_Pos)
5151 #define CLK_CLKDIV1_TMR2DIV_Pos (16)
5152 #define CLK_CLKDIV1_TMR2DIV_Msk (0xful << CLK_CLKDIV1_TMR2DIV_Pos)
5154 #define CLK_CLKDIV1_TMR3DIV_Pos (20)
5155 #define CLK_CLKDIV1_TMR3DIV_Msk (0xful << CLK_CLKDIV1_TMR3DIV_Pos)
5157 #define CLK_PLLCTL_PLLMLP_Pos (0)
5158 #define CLK_PLLCTL_PLLMLP_Msk (0x3ful << CLK_PLLCTL_PLLMLP_Pos)
5160 #define CLK_PLLCTL_INDIV_Pos (8)
5161 #define CLK_PLLCTL_INDIV_Msk (0x3ful << CLK_PLLCTL_INDIV_Pos)
5163 #define CLK_PLLCTL_STBTSEL_Pos (14)
5164 #define CLK_PLLCTL_STBTSEL_Msk (0x3ul << CLK_PLLCTL_STBTSEL_Pos)
5166 #define CLK_PLLCTL_PD_Pos (16)
5167 #define CLK_PLLCTL_PD_Msk (0x1ul << CLK_PLLCTL_PD_Pos)
5169 #define CLK_PLLCTL_PLLSRC_Pos (17)
5170 #define CLK_PLLCTL_PLLSRC_Msk (0x3ul << CLK_PLLCTL_PLLSRC_Pos)
5172 #define CLK_CLKOCTL_FREQSEL_Pos (0)
5173 #define CLK_CLKOCTL_FREQSEL_Msk (0xful << CLK_CLKOCTL_FREQSEL_Pos)
5175 #define CLK_CLKOCTL_CLKOEN_Pos (4)
5176 #define CLK_CLKOCTL_CLKOEN_Msk (0x1ul << CLK_CLKOCTL_CLKOEN_Pos)
5178 #define CLK_CLKOCTL_DIV1EN_Pos (5)
5179 #define CLK_CLKOCTL_DIV1EN_Msk (0x1ul << CLK_CLKOCTL_DIV1EN_Pos)
5181 #define CLK_WKINTSTS_PDWKIF_Pos (0)
5182 #define CLK_WKINTSTS_PDWKIF_Msk (0x1ul << CLK_WKINTSTS_PDWKIF_Pos)
5184 #define CLK_APBDIV_APB0DIV_Pos (0)
5185 #define CLK_APBDIV_APB0DIV_Msk (0x7ul << CLK_APBDIV_APB0DIV_Pos)
5187 #define CLK_APBDIV_APB1DIV_Pos (4)
5188 #define CLK_APBDIV_APB1DIV_Msk (0x7ul << CLK_APBDIV_APB1DIV_Pos)
5190 #define CLK_CLKDCTL_HXTFDEN_Pos (0)
5191 #define CLK_CLKDCTL_HXTFDEN_Msk (0x1ul << CLK_CLKDCTL_HXTFDEN_Pos)
5193 #define CLK_CLKDCTL_LXTFDEN_Pos (1)
5194 #define CLK_CLKDCTL_LXTFDEN_Msk (0x1ul << CLK_CLKDCTL_LXTFDEN_Pos)
5196 #define CLK_CLKDCTL_HXTFQDEN_Pos (2)
5197 #define CLK_CLKDCTL_HXTFQDEN_Msk (0x1ul << CLK_CLKDCTL_HXTFQDEN_Pos)
5199 #define CLK_CLKDIE_HXTFIEN_Pos (0)
5200 #define CLK_CLKDIE_HXTFIEN_Msk (0x1ul << CLK_CLKDIE_HXTFIEN_Pos)
5202 #define CLK_CLKDIE_LXTFIEN_Pos (1)
5203 #define CLK_CLKDIE_LXTFIEN_Msk (0x1ul << CLK_CLKDIE_LXTFIEN_Pos)
5205 #define CLK_CLKDIE_HXTFQIEN_Pos (2)
5206 #define CLK_CLKDIE_HXTFQIEN_Msk (0x1ul << CLK_CLKDIE_HXTFQIEN_Pos)
5208 #define CLK_CLKDSTS_HXTFIF_Pos (0)
5209 #define CLK_CLKDSTS_HXTFIF_Msk (0x1ul << CLK_CLKDSTS_HXTFIF_Pos)
5211 #define CLK_CLKDSTS_LXTFIF_Pos (1)
5212 #define CLK_CLKDSTS_LXTFIF_Msk (0x1ul << CLK_CLKDSTS_LXTFIF_Pos)
5214 #define CLK_CLKDSTS_HXTFQIF_Pos (2)
5215 #define CLK_CLKDSTS_HXTFQIF_Msk (0x1ul << CLK_CLKDSTS_HXTFQIF_Pos)
5217 #define CLK_CDUPB_UPERBD_Pos (0)
5218 #define CLK_CDUPB_UPERBD_Msk (0x7fful << CLK_CDUPB_UPERBD_Pos)
5220 #define CLK_CDLOWB_LOWERBD_Pos (0)
5221 #define CLK_CDLOWB_LOWERBD_Msk (0x7fful << CLK_CDLOWB_LOWERBD_Pos) /* CLK_CONST */
5224 /* end of CLK register group */
5225
5226
5227 /*---------------------- Flash Memory Controller -------------------------*/
5233 typedef struct
5234 {
5235
5236
5857 __IO uint32_t ISPCTL;
5858 __IO uint32_t ISPADDR;
5859 __IO uint32_t ISPDAT;
5860 __IO uint32_t ISPCMD;
5861 __IO uint32_t ISPTRG;
5862 __I uint32_t DFBA;
5863 __IO uint32_t FTCTL;
5864 __I uint32_t RESERVE0[9];
5867 __IO uint32_t ISPSTS;
5868 __I uint32_t RESERVE1[3];
5871 __O uint32_t KEY0;
5872 __O uint32_t KEY1;
5873 __O uint32_t KEY2;
5874 __IO uint32_t KEYTRG;
5875 __IO uint32_t KEYSTS;
5876 __I uint32_t KECNT;
5877 __I uint32_t KPCNT;
5879 } FMC_T;
5880
5886 #define FMC_ISPCTL_ISPEN_Pos (0)
5887 #define FMC_ISPCTL_ISPEN_Msk (0x1ul << FMC_ISPCTL_ISPEN_Pos)
5889 #define FMC_ISPCTL_BS_Pos (1)
5890 #define FMC_ISPCTL_BS_Msk (0x1ul << FMC_ISPCTL_BS_Pos)
5892 #define FMC_ISPCTL_APUEN_Pos (3)
5893 #define FMC_ISPCTL_APUEN_Msk (0x1ul << FMC_ISPCTL_APUEN_Pos)
5895 #define FMC_ISPCTL_CFGUEN_Pos (4)
5896 #define FMC_ISPCTL_CFGUEN_Msk (0x1ul << FMC_ISPCTL_CFGUEN_Pos)
5898 #define FMC_ISPCTL_LDUEN_Pos (5)
5899 #define FMC_ISPCTL_LDUEN_Msk (0x1ul << FMC_ISPCTL_LDUEN_Pos)
5901 #define FMC_ISPCTL_ISPFF_Pos (6)
5902 #define FMC_ISPCTL_ISPFF_Msk (0x1ul << FMC_ISPCTL_ISPFF_Pos)
5904 #define FMC_ISPADDR_ISPADDR_Pos (0)
5905 #define FMC_ISPADDR_ISPADDR_Msk (0xfffffffful << FMC_ISPADDR_ISPADDR_Pos)
5907 #define FMC_ISPDAT_ISPDAT_Pos (0)
5908 #define FMC_ISPDAT_ISPDAT_Msk (0xfffffffful << FMC_ISPDAT_ISPDAT_Pos)
5910 #define FMC_ISPCMD_CMD_Pos (0)
5911 #define FMC_ISPCMD_CMD_Msk (0x3ful << FMC_ISPCMD_CMD_Pos)
5913 #define FMC_ISPTRG_ISPGO_Pos (0)
5914 #define FMC_ISPTRG_ISPGO_Msk (0x1ul << FMC_ISPTRG_ISPGO_Pos)
5916 #define FMC_DFBA_DFBA_Pos (0)
5917 #define FMC_DFBA_DFBA_Msk (0xfffffffful << FMC_DFBA_DFBA_Pos)
5919 #define FMC_FTCTL_FOM_Pos (4)
5920 #define FMC_FTCTL_FOM_Msk (0x7ul << FMC_FTCTL_FOM_Pos)
5922 #define FMC_FTCTL_CACHEOFF_Pos (7)
5923 #define FMC_FTCTL_CACHEOFF_Msk (0x1ul << FMC_FTCTL_CACHEOFF_Pos)
5925 #define FMC_ISPSTS_ISPBUSY_Pos (0)
5926 #define FMC_ISPSTS_ISPBUSY_Msk (0x1ul << FMC_ISPSTS_ISPBUSY_Pos)
5928 #define FMC_ISPSTS_CBS_Pos (1)
5929 #define FMC_ISPSTS_CBS_Msk (0x3ul << FMC_ISPSTS_CBS_Pos)
5931 #define FMC_ISPSTS_PGFF_Pos (5)
5932 #define FMC_ISPSTS_PGFF_Msk (0x1ul << FMC_ISPSTS_PGFF_Pos)
5934 #define FMC_ISPSTS_ISPFF_Pos (6)
5935 #define FMC_ISPSTS_ISPFF_Msk (0x1ul << FMC_ISPSTS_ISPFF_Pos)
5937 #define FMC_ISPSTS_ALLONE_Pos (7)
5938 #define FMC_ISPSTS_ALLONE_Msk (0x1ul << FMC_ISPSTS_ALLONE_Pos)
5940 #define FMC_ISPSTS_VECMAP_Pos (9)
5941 #define FMC_ISPSTS_VECMAP_Msk (0x1ffffful << FMC_ISPSTS_VECMAP_Pos)
5943 #define FMC_KEY0_KEY0_Pos (0)
5944 #define FMC_KEY0_KEY0_Msk (0xfffffffful << FMC_KEY0_KEY0_Pos)
5946 #define FMC_KEY1_KEY1_Pos (0)
5947 #define FMC_KEY1_KEY1_Msk (0xfffffffful << FMC_KEY1_KEY1_Pos)
5949 #define FMC_KEY2_KEY2_Pos (0)
5950 #define FMC_KEY2_KEY2_Msk (0xfffffffful << FMC_KEY2_KEY2_Pos)
5952 #define FMC_KEYTRG_KEYGO_Pos (0)
5953 #define FMC_KEYTRG_KEYGO_Msk (0x1ul << FMC_KEYTRG_KEYGO_Pos)
5955 #define FMC_KEYTRG_TCEN_Pos (1)
5956 #define FMC_KEYTRG_TCEN_Msk (0x1ul << FMC_KEYTRG_TCEN_Pos)
5958 #define FMC_KEYSTS_KEYBUSY_Pos (0)
5959 #define FMC_KEYSTS_KEYBUSY_Msk (0x1ul << FMC_KEYSTS_KEYBUSY_Pos)
5961 #define FMC_KEYSTS_KEYLOCK_Pos (1)
5962 #define FMC_KEYSTS_KEYLOCK_Msk (0x1ul << FMC_KEYSTS_KEYLOCK_Pos)
5964 #define FMC_KEYSTS_KEYMATCH_Pos (2)
5965 #define FMC_KEYSTS_KEYMATCH_Msk (0x1ul << FMC_KEYSTS_KEYMATCH_Pos)
5967 #define FMC_KEYSTS_FORBID_Pos (3)
5968 #define FMC_KEYSTS_FORBID_Msk (0x1ul << FMC_KEYSTS_FORBID_Pos)
5970 #define FMC_KEYSTS_KEYFLAG_Pos (4)
5971 #define FMC_KEYSTS_KEYFLAG_Msk (0x1ul << FMC_KEYSTS_KEYFLAG_Pos)
5973 #define FMC_KEYSTS_CFGFLAG_Pos (5)
5974 #define FMC_KEYSTS_CFGFLAG_Msk (0x1ul << FMC_KEYSTS_CFGFLAG_Pos)
5976 #define FMC_KECNT_KECNT_Pos (0)
5977 #define FMC_KECNT_KECNT_Msk (0x3ful << FMC_KECNT_KECNT_Pos)
5979 #define FMC_KECNT_KEMAX_Pos (8)
5980 #define FMC_KECNT_KEMAX_Msk (0x3ful << FMC_KECNT_KEMAX_Pos)
5982 #define FMC_KPCNT_KPCNT_Pos (0)
5983 #define FMC_KPCNT_KPCNT_Msk (0xful << FMC_KPCNT_KPCNT_Pos)
5985 #define FMC_KPCNT_KPMAX_Pos (8)
5986 #define FMC_KPCNT_KPMAX_Msk (0xful << FMC_KPCNT_KPMAX_Pos) /* FMC_CONST */
5989 /* end of FMC register group */
5990
5991
5992 /*---------------------- General Purpose Input/Output Controller -------------------------*/
5998 typedef struct
5999 {
6000
6001
11764 __IO uint32_t MODE;
11765 __IO uint32_t DINOFF;
11766 __IO uint32_t DOUT;
11767 __IO uint32_t DATMSK;
11768 __I uint32_t PIN;
11769 __IO uint32_t DBEN;
11770 __IO uint32_t INTTYPE;
11771 __IO uint32_t INTEN;
11772 __IO uint32_t INTSRC;
11773 __IO uint32_t PUEN;
11774 __I uint32_t INTSTS;
11776 } GPIO_T;
11777
11778 typedef struct
11779 {
11780
11848 __IO uint32_t DBCTL;
11849 } GP_DB_T;
11850
11856 #define GPIO_MODE_MODE0_Pos (0)
11857 #define GPIO_MODE_MODE0_Msk (0x3ul << GPIO_MODE_MODE0_Pos)
11859 #define GPIO_MODE_MODE1_Pos (2)
11860 #define GPIO_MODE_MODE1_Msk (0x3ul << GPIO_MODE_MODE1_Pos)
11862 #define GPIO_MODE_MODE2_Pos (4)
11863 #define GPIO_MODE_MODE2_Msk (0x3ul << GPIO_MODE_MODE2_Pos)
11865 #define GPIO_MODE_MODE3_Pos (6)
11866 #define GPIO_MODE_MODE3_Msk (0x3ul << GPIO_MODE_MODE3_Pos)
11868 #define GPIO_MODE_MODE4_Pos (8)
11869 #define GPIO_MODE_MODE4_Msk (0x3ul << GPIO_MODE_MODE4_Pos)
11871 #define GPIO_MODE_MODE5_Pos (10)
11872 #define GPIO_MODE_MODE5_Msk (0x3ul << GPIO_MODE_MODE5_Pos)
11874 #define GPIO_MODE_MODE6_Pos (12)
11875 #define GPIO_MODE_MODE6_Msk (0x3ul << GPIO_MODE_MODE6_Pos)
11877 #define GPIO_MODE_MODE7_Pos (14)
11878 #define GPIO_MODE_MODE7_Msk (0x3ul << GPIO_MODE_MODE7_Pos)
11880 #define GPIO_MODE_MODE8_Pos (16)
11881 #define GPIO_MODE_MODE8_Msk (0x3ul << GPIO_MODE_MODE8_Pos)
11883 #define GPIO_MODE_MODE9_Pos (18)
11884 #define GPIO_MODE_MODE9_Msk (0x3ul << GPIO_MODE_MODE9_Pos)
11886 #define GPIO_MODE_MODE10_Pos (20)
11887 #define GPIO_MODE_MODE10_Msk (0x3ul << GPIO_MODE_MODE10_Pos)
11889 #define GPIO_MODE_MODE11_Pos (22)
11890 #define GPIO_MODE_MODE11_Msk (0x3ul << GPIO_MODE_MODE11_Pos)
11892 #define GPIO_MODE_MODE12_Pos (24)
11893 #define GPIO_MODE_MODE12_Msk (0x3ul << GPIO_MODE_MODE12_Pos)
11895 #define GPIO_MODE_MODE13_Pos (26)
11896 #define GPIO_MODE_MODE13_Msk (0x3ul << GPIO_MODE_MODE13_Pos)
11898 #define GPIO_MODE_MODE14_Pos (28)
11899 #define GPIO_MODE_MODE14_Msk (0x3ul << GPIO_MODE_MODE14_Pos)
11901 #define GPIO_MODE_MODE15_Pos (30)
11902 #define GPIO_MODE_MODE15_Msk (0x3ul << GPIO_MODE_MODE15_Pos)
11904 #define GPIO_DINOFF_DINOFF0_Pos (16)
11905 #define GPIO_DINOFF_DINOFF0_Msk (0x1ul << GPIO_DINOFF_DINOFF0_Pos)
11907 #define GPIO_DINOFF_DINOFF1_Pos (17)
11908 #define GPIO_DINOFF_DINOFF1_Msk (0x1ul << GPIO_DINOFF_DINOFF1_Pos)
11910 #define GPIO_DINOFF_DINOFF2_Pos (18)
11911 #define GPIO_DINOFF_DINOFF2_Msk (0x1ul << GPIO_DINOFF_DINOFF2_Pos)
11913 #define GPIO_DINOFF_DINOFF3_Pos (19)
11914 #define GPIO_DINOFF_DINOFF3_Msk (0x1ul << GPIO_DINOFF_DINOFF3_Pos)
11916 #define GPIO_DINOFF_DINOFF4_Pos (20)
11917 #define GPIO_DINOFF_DINOFF4_Msk (0x1ul << GPIO_DINOFF_DINOFF4_Pos)
11919 #define GPIO_DINOFF_DINOFF5_Pos (21)
11920 #define GPIO_DINOFF_DINOFF5_Msk (0x1ul << GPIO_DINOFF_DINOFF5_Pos)
11922 #define GPIO_DINOFF_DINOFF6_Pos (22)
11923 #define GPIO_DINOFF_DINOFF6_Msk (0x1ul << GPIO_DINOFF_DINOFF6_Pos)
11925 #define GPIO_DINOFF_DINOFF7_Pos (23)
11926 #define GPIO_DINOFF_DINOFF7_Msk (0x1ul << GPIO_DINOFF_DINOFF7_Pos)
11928 #define GPIO_DINOFF_DINOFF8_Pos (24)
11929 #define GPIO_DINOFF_DINOFF8_Msk (0x1ul << GPIO_DINOFF_DINOFF8_Pos)
11931 #define GPIO_DINOFF_DINOFF9_Pos (25)
11932 #define GPIO_DINOFF_DINOFF9_Msk (0x1ul << GPIO_DINOFF_DINOFF9_Pos)
11934 #define GPIO_DINOFF_DINOFF10_Pos (26)
11935 #define GPIO_DINOFF_DINOFF10_Msk (0x1ul << GPIO_DINOFF_DINOFF10_Pos)
11937 #define GPIO_DINOFF_DINOFF11_Pos (27)
11938 #define GPIO_DINOFF_DINOFF11_Msk (0x1ul << GPIO_DINOFF_DINOFF11_Pos)
11940 #define GPIO_DINOFF_DINOFF12_Pos (28)
11941 #define GPIO_DINOFF_DINOFF12_Msk (0x1ul << GPIO_DINOFF_DINOFF12_Pos)
11943 #define GPIO_DINOFF_DINOFF13_Pos (29)
11944 #define GPIO_DINOFF_DINOFF13_Msk (0x1ul << GPIO_DINOFF_DINOFF13_Pos)
11946 #define GPIO_DINOFF_DINOFF14_Pos (30)
11947 #define GPIO_DINOFF_DINOFF14_Msk (0x1ul << GPIO_DINOFF_DINOFF14_Pos)
11949 #define GPIO_DINOFF_DINOFF15_Pos (31)
11950 #define GPIO_DINOFF_DINOFF15_Msk (0x1ul << GPIO_DINOFF_DINOFF15_Pos)
11952 #define GPIO_DOUT_DOUT0_Pos (0)
11953 #define GPIO_DOUT_DOUT0_Msk (0x1ul << GPIO_DOUT_DOUT0_Pos)
11955 #define GPIO_DOUT_DOUT1_Pos (1)
11956 #define GPIO_DOUT_DOUT1_Msk (0x1ul << GPIO_DOUT_DOUT1_Pos)
11958 #define GPIO_DOUT_DOUT2_Pos (2)
11959 #define GPIO_DOUT_DOUT2_Msk (0x1ul << GPIO_DOUT_DOUT2_Pos)
11961 #define GPIO_DOUT_DOUT3_Pos (3)
11962 #define GPIO_DOUT_DOUT3_Msk (0x1ul << GPIO_DOUT_DOUT3_Pos)
11964 #define GPIO_DOUT_DOUT4_Pos (4)
11965 #define GPIO_DOUT_DOUT4_Msk (0x1ul << GPIO_DOUT_DOUT4_Pos)
11967 #define GPIO_DOUT_DOUT5_Pos (5)
11968 #define GPIO_DOUT_DOUT5_Msk (0x1ul << GPIO_DOUT_DOUT5_Pos)
11970 #define GPIO_DOUT_DOUT6_Pos (6)
11971 #define GPIO_DOUT_DOUT6_Msk (0x1ul << GPIO_DOUT_DOUT6_Pos)
11973 #define GPIO_DOUT_DOUT7_Pos (7)
11974 #define GPIO_DOUT_DOUT7_Msk (0x1ul << GPIO_DOUT_DOUT7_Pos)
11976 #define GPIO_DOUT_DOUT8_Pos (8)
11977 #define GPIO_DOUT_DOUT8_Msk (0x1ul << GPIO_DOUT_DOUT8_Pos)
11979 #define GPIO_DOUT_DOUT9_Pos (9)
11980 #define GPIO_DOUT_DOUT9_Msk (0x1ul << GPIO_DOUT_DOUT9_Pos)
11982 #define GPIO_DOUT_DOUT10_Pos (10)
11983 #define GPIO_DOUT_DOUT10_Msk (0x1ul << GPIO_DOUT_DOUT10_Pos)
11985 #define GPIO_DOUT_DOUT11_Pos (11)
11986 #define GPIO_DOUT_DOUT11_Msk (0x1ul << GPIO_DOUT_DOUT11_Pos)
11988 #define GPIO_DOUT_DOUT12_Pos (12)
11989 #define GPIO_DOUT_DOUT12_Msk (0x1ul << GPIO_DOUT_DOUT12_Pos)
11991 #define GPIO_DOUT_DOUT13_Pos (13)
11992 #define GPIO_DOUT_DOUT13_Msk (0x1ul << GPIO_DOUT_DOUT13_Pos)
11994 #define GPIO_DOUT_DOUT14_Pos (14)
11995 #define GPIO_DOUT_DOUT14_Msk (0x1ul << GPIO_DOUT_DOUT14_Pos)
11997 #define GPIO_DOUT_DOUT15_Pos (15)
11998 #define GPIO_DOUT_DOUT15_Msk (0x1ul << GPIO_DOUT_DOUT15_Pos)
12000 #define GPIO_DATMSK_DMASK0_Pos (0)
12001 #define GPIO_DATMSK_DMASK0_Msk (0x1ul << GPIO_DATMSK_DMASK0_Pos)
12003 #define GPIO_DATMSK_DMASK1_Pos (1)
12004 #define GPIO_DATMSK_DMASK1_Msk (0x1ul << GPIO_DATMSK_DMASK1_Pos)
12006 #define GPIO_DATMSK_DMASK2_Pos (2)
12007 #define GPIO_DATMSK_DMASK2_Msk (0x1ul << GPIO_DATMSK_DMASK2_Pos)
12009 #define GPIO_DATMSK_DMASK3_Pos (3)
12010 #define GPIO_DATMSK_DMASK3_Msk (0x1ul << GPIO_DATMSK_DMASK3_Pos)
12012 #define GPIO_DATMSK_DMASK4_Pos (4)
12013 #define GPIO_DATMSK_DMASK4_Msk (0x1ul << GPIO_DATMSK_DMASK4_Pos)
12015 #define GPIO_DATMSK_DMASK5_Pos (5)
12016 #define GPIO_DATMSK_DMASK5_Msk (0x1ul << GPIO_DATMSK_DMASK5_Pos)
12018 #define GPIO_DATMSK_DMASK6_Pos (6)
12019 #define GPIO_DATMSK_DMASK6_Msk (0x1ul << GPIO_DATMSK_DMASK6_Pos)
12021 #define GPIO_DATMSK_DMASK7_Pos (7)
12022 #define GPIO_DATMSK_DMASK7_Msk (0x1ul << GPIO_DATMSK_DMASK7_Pos)
12024 #define GPIO_DATMSK_DMASK8_Pos (8)
12025 #define GPIO_DATMSK_DMASK8_Msk (0x1ul << GPIO_DATMSK_DMASK8_Pos)
12027 #define GPIO_DATMSK_DMASK9_Pos (9)
12028 #define GPIO_DATMSK_DMASK9_Msk (0x1ul << GPIO_DATMSK_DMASK9_Pos)
12030 #define GPIO_DATMSK_DMASK10_Pos (10)
12031 #define GPIO_DATMSK_DMASK10_Msk (0x1ul << GPIO_DATMSK_DMASK10_Pos)
12033 #define GPIO_DATMSK_DMASK11_Pos (11)
12034 #define GPIO_DATMSK_DMASK11_Msk (0x1ul << GPIO_DATMSK_DMASK11_Pos)
12036 #define GPIO_DATMSK_DMASK12_Pos (12)
12037 #define GPIO_DATMSK_DMASK12_Msk (0x1ul << GPIO_DATMSK_DMASK12_Pos)
12039 #define GPIO_DATMSK_DMASK13_Pos (13)
12040 #define GPIO_DATMSK_DMASK13_Msk (0x1ul << GPIO_DATMSK_DMASK13_Pos)
12042 #define GPIO_DATMSK_DMASK14_Pos (14)
12043 #define GPIO_DATMSK_DMASK14_Msk (0x1ul << GPIO_DATMSK_DMASK14_Pos)
12045 #define GPIO_DATMSK_DMASK15_Pos (15)
12046 #define GPIO_DATMSK_DMASK15_Msk (0x1ul << GPIO_DATMSK_DMASK15_Pos)
12048 #define GPIO_PIN_PIN0_Pos (0)
12049 #define GPIO_PIN_PIN0_Msk (0x1ul << GPIO_PIN_PIN0_Pos)
12051 #define GPIO_PIN_PIN1_Pos (1)
12052 #define GPIO_PIN_PIN1_Msk (0x1ul << GPIO_PIN_PIN1_Pos)
12054 #define GPIO_PIN_PIN2_Pos (2)
12055 #define GPIO_PIN_PIN2_Msk (0x1ul << GPIO_PIN_PIN2_Pos)
12057 #define GPIO_PIN_PIN3_Pos (3)
12058 #define GPIO_PIN_PIN3_Msk (0x1ul << GPIO_PIN_PIN3_Pos)
12060 #define GPIO_PIN_PIN4_Pos (4)
12061 #define GPIO_PIN_PIN4_Msk (0x1ul << GPIO_PIN_PIN4_Pos)
12063 #define GPIO_PIN_PIN5_Pos (5)
12064 #define GPIO_PIN_PIN5_Msk (0x1ul << GPIO_PIN_PIN5_Pos)
12066 #define GPIO_PIN_PIN6_Pos (6)
12067 #define GPIO_PIN_PIN6_Msk (0x1ul << GPIO_PIN_PIN6_Pos)
12069 #define GPIO_PIN_PIN7_Pos (7)
12070 #define GPIO_PIN_PIN7_Msk (0x1ul << GPIO_PIN_PIN7_Pos)
12072 #define GPIO_PIN_PIN8_Pos (8)
12073 #define GPIO_PIN_PIN8_Msk (0x1ul << GPIO_PIN_PIN8_Pos)
12075 #define GPIO_PIN_PIN9_Pos (9)
12076 #define GPIO_PIN_PIN9_Msk (0x1ul << GPIO_PIN_PIN9_Pos)
12078 #define GPIO_PIN_PIN10_Pos (10)
12079 #define GPIO_PIN_PIN10_Msk (0x1ul << GPIO_PIN_PIN10_Pos)
12081 #define GPIO_PIN_PIN11_Pos (11)
12082 #define GPIO_PIN_PIN11_Msk (0x1ul << GPIO_PIN_PIN11_Pos)
12084 #define GPIO_PIN_PIN12_Pos (12)
12085 #define GPIO_PIN_PIN12_Msk (0x1ul << GPIO_PIN_PIN12_Pos)
12087 #define GPIO_PIN_PIN13_Pos (13)
12088 #define GPIO_PIN_PIN13_Msk (0x1ul << GPIO_PIN_PIN13_Pos)
12090 #define GPIO_PIN_PIN14_Pos (14)
12091 #define GPIO_PIN_PIN14_Msk (0x1ul << GPIO_PIN_PIN14_Pos)
12093 #define GPIO_PIN_PIN15_Pos (15)
12094 #define GPIO_PIN_PIN15_Msk (0x1ul << GPIO_PIN_PIN15_Pos)
12096 #define GPIO_DBEN_DBEN0_Pos (0)
12097 #define GPIO_DBEN_DBEN0_Msk (0x1ul << GPIO_DBEN_DBEN0_Pos)
12099 #define GPIO_DBEN_DBEN1_Pos (1)
12100 #define GPIO_DBEN_DBEN1_Msk (0x1ul << GPIO_DBEN_DBEN1_Pos)
12102 #define GPIO_DBEN_DBEN2_Pos (2)
12103 #define GPIO_DBEN_DBEN2_Msk (0x1ul << GPIO_DBEN_DBEN2_Pos)
12105 #define GPIO_DBEN_DBEN3_Pos (3)
12106 #define GPIO_DBEN_DBEN3_Msk (0x1ul << GPIO_DBEN_DBEN3_Pos)
12108 #define GPIO_DBEN_DBEN4_Pos (4)
12109 #define GPIO_DBEN_DBEN4_Msk (0x1ul << GPIO_DBEN_DBEN4_Pos)
12111 #define GPIO_DBEN_DBEN5_Pos (5)
12112 #define GPIO_DBEN_DBEN5_Msk (0x1ul << GPIO_DBEN_DBEN5_Pos)
12114 #define GPIO_DBEN_DBEN6_Pos (6)
12115 #define GPIO_DBEN_DBEN6_Msk (0x1ul << GPIO_DBEN_DBEN6_Pos)
12117 #define GPIO_DBEN_DBEN7_Pos (7)
12118 #define GPIO_DBEN_DBEN7_Msk (0x1ul << GPIO_DBEN_DBEN7_Pos)
12120 #define GPIO_DBEN_DBEN8_Pos (8)
12121 #define GPIO_DBEN_DBEN8_Msk (0x1ul << GPIO_DBEN_DBEN8_Pos)
12123 #define GPIO_DBEN_DBEN9_Pos (9)
12124 #define GPIO_DBEN_DBEN9_Msk (0x1ul << GPIO_DBEN_DBEN9_Pos)
12126 #define GPIO_DBEN_DBEN10_Pos (10)
12127 #define GPIO_DBEN_DBEN10_Msk (0x1ul << GPIO_DBEN_DBEN10_Pos)
12129 #define GPIO_DBEN_DBEN11_Pos (11)
12130 #define GPIO_DBEN_DBEN11_Msk (0x1ul << GPIO_DBEN_DBEN11_Pos)
12132 #define GPIO_DBEN_DBEN12_Pos (12)
12133 #define GPIO_DBEN_DBEN12_Msk (0x1ul << GPIO_DBEN_DBEN12_Pos)
12135 #define GPIO_DBEN_DBEN13_Pos (13)
12136 #define GPIO_DBEN_DBEN13_Msk (0x1ul << GPIO_DBEN_DBEN13_Pos)
12138 #define GPIO_DBEN_DBEN14_Pos (14)
12139 #define GPIO_DBEN_DBEN14_Msk (0x1ul << GPIO_DBEN_DBEN14_Pos)
12141 #define GPIO_DBEN_DBEN15_Pos (15)
12142 #define GPIO_DBEN_DBEN15_Msk (0x1ul << GPIO_DBEN_DBEN15_Pos)
12144 #define GPIO_INTTYPE_TYPE0_Pos (0)
12145 #define GPIO_INTTYPE_TYPE0_Msk (0x1ul << GPIO_INTTYPE_TYPE0_Pos)
12147 #define GPIO_INTTYPE_TYPE1_Pos (1)
12148 #define GPIO_INTTYPE_TYPE1_Msk (0x1ul << GPIO_INTTYPE_TYPE1_Pos)
12150 #define GPIO_INTTYPE_TYPE2_Pos (2)
12151 #define GPIO_INTTYPE_TYPE2_Msk (0x1ul << GPIO_INTTYPE_TYPE2_Pos)
12153 #define GPIO_INTTYPE_TYPE3_Pos (3)
12154 #define GPIO_INTTYPE_TYPE3_Msk (0x1ul << GPIO_INTTYPE_TYPE3_Pos)
12156 #define GPIO_INTTYPE_TYPE4_Pos (4)
12157 #define GPIO_INTTYPE_TYPE4_Msk (0x1ul << GPIO_INTTYPE_TYPE4_Pos)
12159 #define GPIO_INTTYPE_TYPE5_Pos (5)
12160 #define GPIO_INTTYPE_TYPE5_Msk (0x1ul << GPIO_INTTYPE_TYPE5_Pos)
12162 #define GPIO_INTTYPE_TYPE6_Pos (6)
12163 #define GPIO_INTTYPE_TYPE6_Msk (0x1ul << GPIO_INTTYPE_TYPE6_Pos)
12165 #define GPIO_INTTYPE_TYPE7_Pos (7)
12166 #define GPIO_INTTYPE_TYPE7_Msk (0x1ul << GPIO_INTTYPE_TYPE7_Pos)
12168 #define GPIO_INTTYPE_TYPE8_Pos (8)
12169 #define GPIO_INTTYPE_TYPE8_Msk (0x1ul << GPIO_INTTYPE_TYPE8_Pos)
12171 #define GPIO_INTTYPE_TYPE9_Pos (9)
12172 #define GPIO_INTTYPE_TYPE9_Msk (0x1ul << GPIO_INTTYPE_TYPE9_Pos)
12174 #define GPIO_INTTYPE_TYPE10_Pos (10)
12175 #define GPIO_INTTYPE_TYPE10_Msk (0x1ul << GPIO_INTTYPE_TYPE10_Pos)
12177 #define GPIO_INTTYPE_TYPE11_Pos (11)
12178 #define GPIO_INTTYPE_TYPE11_Msk (0x1ul << GPIO_INTTYPE_TYPE11_Pos)
12180 #define GPIO_INTTYPE_TYPE12_Pos (12)
12181 #define GPIO_INTTYPE_TYPE12_Msk (0x1ul << GPIO_INTTYPE_TYPE12_Pos)
12183 #define GPIO_INTTYPE_TYPE13_Pos (13)
12184 #define GPIO_INTTYPE_TYPE13_Msk (0x1ul << GPIO_INTTYPE_TYPE13_Pos)
12186 #define GPIO_INTTYPE_TYPE14_Pos (14)
12187 #define GPIO_INTTYPE_TYPE14_Msk (0x1ul << GPIO_INTTYPE_TYPE14_Pos)
12189 #define GPIO_INTTYPE_TYPE15_Pos (15)
12190 #define GPIO_INTTYPE_TYPE15_Msk (0x1ul << GPIO_INTTYPE_TYPE15_Pos)
12192 #define GPIO_INTEN_FLIEN0_Pos (0)
12193 #define GPIO_INTEN_FLIEN0_Msk (0x1ul << GPIO_INTEN_FLIEN0_Pos)
12195 #define GPIO_INTEN_FLIEN1_Pos (1)
12196 #define GPIO_INTEN_FLIEN1_Msk (0x1ul << GPIO_INTEN_FLIEN1_Pos)
12198 #define GPIO_INTEN_FLIEN2_Pos (2)
12199 #define GPIO_INTEN_FLIEN2_Msk (0x1ul << GPIO_INTEN_FLIEN2_Pos)
12201 #define GPIO_INTEN_FLIEN3_Pos (3)
12202 #define GPIO_INTEN_FLIEN3_Msk (0x1ul << GPIO_INTEN_FLIEN3_Pos)
12204 #define GPIO_INTEN_FLIEN4_Pos (4)
12205 #define GPIO_INTEN_FLIEN4_Msk (0x1ul << GPIO_INTEN_FLIEN4_Pos)
12207 #define GPIO_INTEN_FLIEN5_Pos (5)
12208 #define GPIO_INTEN_FLIEN5_Msk (0x1ul << GPIO_INTEN_FLIEN5_Pos)
12210 #define GPIO_INTEN_FLIEN6_Pos (6)
12211 #define GPIO_INTEN_FLIEN6_Msk (0x1ul << GPIO_INTEN_FLIEN6_Pos)
12213 #define GPIO_INTEN_FLIEN7_Pos (7)
12214 #define GPIO_INTEN_FLIEN7_Msk (0x1ul << GPIO_INTEN_FLIEN7_Pos)
12216 #define GPIO_INTEN_FLIEN8_Pos (8)
12217 #define GPIO_INTEN_FLIEN8_Msk (0x1ul << GPIO_INTEN_FLIEN8_Pos)
12219 #define GPIO_INTEN_FLIEN9_Pos (9)
12220 #define GPIO_INTEN_FLIEN9_Msk (0x1ul << GPIO_INTEN_FLIEN9_Pos)
12222 #define GPIO_INTEN_FLIEN10_Pos (10)
12223 #define GPIO_INTEN_FLIEN10_Msk (0x1ul << GPIO_INTEN_FLIEN10_Pos)
12225 #define GPIO_INTEN_FLIEN11_Pos (11)
12226 #define GPIO_INTEN_FLIEN11_Msk (0x1ul << GPIO_INTEN_FLIEN11_Pos)
12228 #define GPIO_INTEN_FLIEN12_Pos (12)
12229 #define GPIO_INTEN_FLIEN12_Msk (0x1ul << GPIO_INTEN_FLIEN12_Pos)
12231 #define GPIO_INTEN_FLIEN13_Pos (13)
12232 #define GPIO_INTEN_FLIEN13_Msk (0x1ul << GPIO_INTEN_FLIEN13_Pos)
12234 #define GPIO_INTEN_FLIEN14_Pos (14)
12235 #define GPIO_INTEN_FLIEN14_Msk (0x1ul << GPIO_INTEN_FLIEN14_Pos)
12237 #define GPIO_INTEN_FLIEN15_Pos (15)
12238 #define GPIO_INTEN_FLIEN15_Msk (0x1ul << GPIO_INTEN_FLIEN15_Pos)
12240 #define GPIO_INTEN_RHIEN0_Pos (16)
12241 #define GPIO_INTEN_RHIEN0_Msk (0x1ul << GPIO_INTEN_RHIEN0_Pos)
12243 #define GPIO_INTEN_RHIEN1_Pos (17)
12244 #define GPIO_INTEN_RHIEN1_Msk (0x1ul << GPIO_INTEN_RHIEN1_Pos)
12246 #define GPIO_INTEN_RHIEN2_Pos (18)
12247 #define GPIO_INTEN_RHIEN2_Msk (0x1ul << GPIO_INTEN_RHIEN2_Pos)
12249 #define GPIO_INTEN_RHIEN3_Pos (19)
12250 #define GPIO_INTEN_RHIEN3_Msk (0x1ul << GPIO_INTEN_RHIEN3_Pos)
12252 #define GPIO_INTEN_RHIEN4_Pos (20)
12253 #define GPIO_INTEN_RHIEN4_Msk (0x1ul << GPIO_INTEN_RHIEN4_Pos)
12255 #define GPIO_INTEN_RHIEN5_Pos (21)
12256 #define GPIO_INTEN_RHIEN5_Msk (0x1ul << GPIO_INTEN_RHIEN5_Pos)
12258 #define GPIO_INTEN_RHIEN6_Pos (22)
12259 #define GPIO_INTEN_RHIEN6_Msk (0x1ul << GPIO_INTEN_RHIEN6_Pos)
12261 #define GPIO_INTEN_RHIEN7_Pos (23)
12262 #define GPIO_INTEN_RHIEN7_Msk (0x1ul << GPIO_INTEN_RHIEN7_Pos)
12264 #define GPIO_INTEN_RHIEN8_Pos (24)
12265 #define GPIO_INTEN_RHIEN8_Msk (0x1ul << GPIO_INTEN_RHIEN8_Pos)
12267 #define GPIO_INTEN_RHIEN9_Pos (25)
12268 #define GPIO_INTEN_RHIEN9_Msk (0x1ul << GPIO_INTEN_RHIEN9_Pos)
12270 #define GPIO_INTEN_RHIEN10_Pos (26)
12271 #define GPIO_INTEN_RHIEN10_Msk (0x1ul << GPIO_INTEN_RHIEN10_Pos)
12273 #define GPIO_INTEN_RHIEN11_Pos (27)
12274 #define GPIO_INTEN_RHIEN11_Msk (0x1ul << GPIO_INTEN_RHIEN11_Pos)
12276 #define GPIO_INTEN_RHIEN12_Pos (28)
12277 #define GPIO_INTEN_RHIEN12_Msk (0x1ul << GPIO_INTEN_RHIEN12_Pos)
12279 #define GPIO_INTEN_RHIEN13_Pos (29)
12280 #define GPIO_INTEN_RHIEN13_Msk (0x1ul << GPIO_INTEN_RHIEN13_Pos)
12282 #define GPIO_INTEN_RHIEN14_Pos (30)
12283 #define GPIO_INTEN_RHIEN14_Msk (0x1ul << GPIO_INTEN_RHIEN14_Pos)
12285 #define GPIO_INTEN_RHIEN15_Pos (31)
12286 #define GPIO_INTEN_RHIEN15_Msk (0x1ul << GPIO_INTEN_RHIEN15_Pos)
12288 #define GPIO_INTSRC_INTSRC0_Pos (0)
12289 #define GPIO_INTSRC_INTSRC0_Msk (0x1ul << GPIO_INTSRC_INTSRC0_Pos)
12291 #define GPIO_INTSRC_INTSRC1_Pos (1)
12292 #define GPIO_INTSRC_INTSRC1_Msk (0x1ul << GPIO_INTSRC_INTSRC1_Pos)
12294 #define GPIO_INTSRC_INTSRC2_Pos (2)
12295 #define GPIO_INTSRC_INTSRC2_Msk (0x1ul << GPIO_INTSRC_INTSRC2_Pos)
12297 #define GPIO_INTSRC_INTSRC3_Pos (3)
12298 #define GPIO_INTSRC_INTSRC3_Msk (0x1ul << GPIO_INTSRC_INTSRC3_Pos)
12300 #define GPIO_INTSRC_INTSRC4_Pos (4)
12301 #define GPIO_INTSRC_INTSRC4_Msk (0x1ul << GPIO_INTSRC_INTSRC4_Pos)
12303 #define GPIO_INTSRC_INTSRC5_Pos (5)
12304 #define GPIO_INTSRC_INTSRC5_Msk (0x1ul << GPIO_INTSRC_INTSRC5_Pos)
12306 #define GPIO_INTSRC_INTSRC6_Pos (6)
12307 #define GPIO_INTSRC_INTSRC6_Msk (0x1ul << GPIO_INTSRC_INTSRC6_Pos)
12309 #define GPIO_INTSRC_INTSRC7_Pos (7)
12310 #define GPIO_INTSRC_INTSRC7_Msk (0x1ul << GPIO_INTSRC_INTSRC7_Pos)
12312 #define GPIO_INTSRC_INTSRC8_Pos (8)
12313 #define GPIO_INTSRC_INTSRC8_Msk (0x1ul << GPIO_INTSRC_INTSRC8_Pos)
12315 #define GPIO_INTSRC_INTSRC9_Pos (9)
12316 #define GPIO_INTSRC_INTSRC9_Msk (0x1ul << GPIO_INTSRC_INTSRC9_Pos)
12318 #define GPIO_INTSRC_INTSRC10_Pos (10)
12319 #define GPIO_INTSRC_INTSRC10_Msk (0x1ul << GPIO_INTSRC_INTSRC10_Pos)
12321 #define GPIO_INTSRC_INTSRC11_Pos (11)
12322 #define GPIO_INTSRC_INTSRC11_Msk (0x1ul << GPIO_INTSRC_INTSRC11_Pos)
12324 #define GPIO_INTSRC_INTSRC12_Pos (12)
12325 #define GPIO_INTSRC_INTSRC12_Msk (0x1ul << GPIO_INTSRC_INTSRC12_Pos)
12327 #define GPIO_INTSRC_INTSRC13_Pos (13)
12328 #define GPIO_INTSRC_INTSRC13_Msk (0x1ul << GPIO_INTSRC_INTSRC13_Pos)
12330 #define GPIO_INTSRC_INTSRC14_Pos (14)
12331 #define GPIO_INTSRC_INTSRC14_Msk (0x1ul << GPIO_INTSRC_INTSRC14_Pos)
12333 #define GPIO_INTSRC_INTSRC15_Pos (15)
12334 #define GPIO_INTSRC_INTSRC15_Msk (0x1ul << GPIO_INTSRC_INTSRC15_Pos)
12336 #define GPIO_PUEN_PUEN0_Pos (0)
12337 #define GPIO_PUEN_PUEN0_Msk (0x1ul << GPIO_PUEN_PUEN0_Pos)
12339 #define GPIO_PUEN_PUEN1_Pos (1)
12340 #define GPIO_PUEN_PUEN1_Msk (0x1ul << GPIO_PUEN_PUEN1_Pos)
12342 #define GPIO_PUEN_PUEN2_Pos (2)
12343 #define GPIO_PUEN_PUEN2_Msk (0x1ul << GPIO_PUEN_PUEN2_Pos)
12345 #define GPIO_PUEN_PUEN3_Pos (3)
12346 #define GPIO_PUEN_PUEN3_Msk (0x1ul << GPIO_PUEN_PUEN3_Pos)
12348 #define GPIO_PUEN_PUEN4_Pos (4)
12349 #define GPIO_PUEN_PUEN4_Msk (0x1ul << GPIO_PUEN_PUEN4_Pos)
12351 #define GPIO_PUEN_PUEN5_Pos (5)
12352 #define GPIO_PUEN_PUEN5_Msk (0x1ul << GPIO_PUEN_PUEN5_Pos)
12354 #define GPIO_PUEN_PUEN6_Pos (6)
12355 #define GPIO_PUEN_PUEN6_Msk (0x1ul << GPIO_PUEN_PUEN6_Pos)
12357 #define GPIO_PUEN_PUEN7_Pos (7)
12358 #define GPIO_PUEN_PUEN7_Msk (0x1ul << GPIO_PUEN_PUEN7_Pos)
12360 #define GPIO_PUEN_PUEN8_Pos (8)
12361 #define GPIO_PUEN_PUEN8_Msk (0x1ul << GPIO_PUEN_PUEN8_Pos)
12363 #define GPIO_PUEN_PUEN9_Pos (9)
12364 #define GPIO_PUEN_PUEN9_Msk (0x1ul << GPIO_PUEN_PUEN9_Pos)
12366 #define GPIO_PUEN_PUEN10_Pos (10)
12367 #define GPIO_PUEN_PUEN10_Msk (0x1ul << GPIO_PUEN_PUEN10_Pos)
12369 #define GPIO_PUEN_PUEN11_Pos (11)
12370 #define GPIO_PUEN_PUEN11_Msk (0x1ul << GPIO_PUEN_PUEN11_Pos)
12372 #define GPIO_PUEN_PUEN12_Pos (12)
12373 #define GPIO_PUEN_PUEN12_Msk (0x1ul << GPIO_PUEN_PUEN12_Pos)
12375 #define GPIO_PUEN_PUEN13_Pos (13)
12376 #define GPIO_PUEN_PUEN13_Msk (0x1ul << GPIO_PUEN_PUEN13_Pos)
12378 #define GPIO_PUEN_PUEN14_Pos (14)
12379 #define GPIO_PUEN_PUEN14_Msk (0x1ul << GPIO_PUEN_PUEN14_Pos)
12381 #define GPIO_PUEN_PUEN15_Pos (15)
12382 #define GPIO_PUEN_PUEN15_Msk (0x1ul << GPIO_PUEN_PUEN15_Pos)
12384 #define GPIO_INTSTS_FLISTS0_Pos (0)
12385 #define GPIO_INTSTS_FLISTS0_Msk (0x1ul << GPIO_INTSTS_FLISTS0_Pos)
12387 #define GPIO_INTSTS_FLISTS1_Pos (1)
12388 #define GPIO_INTSTS_FLISTS1_Msk (0x1ul << GPIO_INTSTS_FLISTS1_Pos)
12390 #define GPIO_INTSTS_FLISTS2_Pos (2)
12391 #define GPIO_INTSTS_FLISTS2_Msk (0x1ul << GPIO_INTSTS_FLISTS2_Pos)
12393 #define GPIO_INTSTS_FLISTS3_Pos (3)
12394 #define GPIO_INTSTS_FLISTS3_Msk (0x1ul << GPIO_INTSTS_FLISTS3_Pos)
12396 #define GPIO_INTSTS_FLISTS4_Pos (4)
12397 #define GPIO_INTSTS_FLISTS4_Msk (0x1ul << GPIO_INTSTS_FLISTS4_Pos)
12399 #define GPIO_INTSTS_FLISTS5_Pos (5)
12400 #define GPIO_INTSTS_FLISTS5_Msk (0x1ul << GPIO_INTSTS_FLISTS5_Pos)
12402 #define GPIO_INTSTS_FLISTS6_Pos (6)
12403 #define GPIO_INTSTS_FLISTS6_Msk (0x1ul << GPIO_INTSTS_FLISTS6_Pos)
12405 #define GPIO_INTSTS_FLISTS7_Pos (7)
12406 #define GPIO_INTSTS_FLISTS7_Msk (0x1ul << GPIO_INTSTS_FLISTS7_Pos)
12408 #define GPIO_INTSTS_FLISTS8_Pos (8)
12409 #define GPIO_INTSTS_FLISTS8_Msk (0x1ul << GPIO_INTSTS_FLISTS8_Pos)
12411 #define GPIO_INTSTS_FLISTS9_Pos (9)
12412 #define GPIO_INTSTS_FLISTS9_Msk (0x1ul << GPIO_INTSTS_FLISTS9_Pos)
12414 #define GPIO_INTSTS_FLISTS10_Pos (10)
12415 #define GPIO_INTSTS_FLISTS10_Msk (0x1ul << GPIO_INTSTS_FLISTS10_Pos)
12417 #define GPIO_INTSTS_FLISTS11_Pos (11)
12418 #define GPIO_INTSTS_FLISTS11_Msk (0x1ul << GPIO_INTSTS_FLISTS11_Pos)
12420 #define GPIO_INTSTS_FLISTS12_Pos (12)
12421 #define GPIO_INTSTS_FLISTS12_Msk (0x1ul << GPIO_INTSTS_FLISTS12_Pos)
12423 #define GPIO_INTSTS_FLISTS13_Pos (13)
12424 #define GPIO_INTSTS_FLISTS13_Msk (0x1ul << GPIO_INTSTS_FLISTS13_Pos)
12426 #define GPIO_INTSTS_FLISTS14_Pos (14)
12427 #define GPIO_INTSTS_FLISTS14_Msk (0x1ul << GPIO_INTSTS_FLISTS14_Pos)
12429 #define GPIO_INTSTS_FLISTS15_Pos (15)
12430 #define GPIO_INTSTS_FLISTS15_Msk (0x1ul << GPIO_INTSTS_FLISTS15_Pos)
12432 #define GPIO_INTSTS_RHISTS0_Pos (16)
12433 #define GPIO_INTSTS_RHISTS0_Msk (0x1ul << GPIO_INTSTS_RHISTS0_Pos)
12435 #define GPIO_INTSTS_RHISTS1_Pos (17)
12436 #define GPIO_INTSTS_RHISTS1_Msk (0x1ul << GPIO_INTSTS_RHISTS1_Pos)
12438 #define GPIO_INTSTS_RHISTS2_Pos (18)
12439 #define GPIO_INTSTS_RHISTS2_Msk (0x1ul << GPIO_INTSTS_RHISTS2_Pos)
12441 #define GPIO_INTSTS_RHISTS3_Pos (19)
12442 #define GPIO_INTSTS_RHISTS3_Msk (0x1ul << GPIO_INTSTS_RHISTS3_Pos)
12444 #define GPIO_INTSTS_RHISTS4_Pos (20)
12445 #define GPIO_INTSTS_RHISTS4_Msk (0x1ul << GPIO_INTSTS_RHISTS4_Pos)
12447 #define GPIO_INTSTS_RHISTS5_Pos (21)
12448 #define GPIO_INTSTS_RHISTS5_Msk (0x1ul << GPIO_INTSTS_RHISTS5_Pos)
12450 #define GPIO_INTSTS_RHISTS6_Pos (22)
12451 #define GPIO_INTSTS_RHISTS6_Msk (0x1ul << GPIO_INTSTS_RHISTS6_Pos)
12453 #define GPIO_INTSTS_RHISTS7_Pos (23)
12454 #define GPIO_INTSTS_RHISTS7_Msk (0x1ul << GPIO_INTSTS_RHISTS7_Pos)
12456 #define GPIO_INTSTS_RHISTS8_Pos (24)
12457 #define GPIO_INTSTS_RHISTS8_Msk (0x1ul << GPIO_INTSTS_RHISTS8_Pos)
12459 #define GPIO_INTSTS_RHISTS9_Pos (25)
12460 #define GPIO_INTSTS_RHISTS9_Msk (0x1ul << GPIO_INTSTS_RHISTS9_Pos)
12462 #define GPIO_INTSTS_RHISTS10_Pos (26)
12463 #define GPIO_INTSTS_RHISTS10_Msk (0x1ul << GPIO_INTSTS_RHISTS10_Pos)
12465 #define GPIO_INTSTS_RHISTS11_Pos (27)
12466 #define GPIO_INTSTS_RHISTS11_Msk (0x1ul << GPIO_INTSTS_RHISTS11_Pos)
12468 #define GPIO_INTSTS_RHISTS12_Pos (28)
12469 #define GPIO_INTSTS_RHISTS12_Msk (0x1ul << GPIO_INTSTS_RHISTS12_Pos)
12471 #define GPIO_INTSTS_RHISTS13_Pos (29)
12472 #define GPIO_INTSTS_RHISTS13_Msk (0x1ul << GPIO_INTSTS_RHISTS13_Pos)
12474 #define GPIO_INTSTS_RHISTS14_Pos (30)
12475 #define GPIO_INTSTS_RHISTS14_Msk (0x1ul << GPIO_INTSTS_RHISTS14_Pos)
12477 #define GPIO_INTSTS_RHISTS15_Pos (31)
12478 #define GPIO_INTSTS_RHISTS15_Msk (0x1ul << GPIO_INTSTS_RHISTS15_Pos)
12480 #define GPIO_DBCTL_DBCLKSEL_Pos (0)
12481 #define GPIO_DBCTL_DBCLKSEL_Msk (0xful << GPIO_DBCTL_DBCLKSEL_Pos)
12483 #define GPIO_DBCTL_DBCLKSRC_Pos (4)
12484 #define GPIO_DBCTL_DBCLKSRC_Msk (0x1ul << GPIO_DBCTL_DBCLKSRC_Pos)
12486 #define GPIO_DBCTL_ICLKON_Pos (5)
12487 #define GPIO_DBCTL_ICLKON_Msk (0x1ul << GPIO_DBCTL_ICLKON_Pos) /* GPIO_CONST */
12491 /* end of GPIO register group */
12492
12493 /*---------------------- Peripheral Direct Memory Access Controller -------------------------*/
12499 typedef struct
12500 {
12501
12502
12872 __IO uint32_t CTLn;
12873 __IO uint32_t SAn;
12874 __IO uint32_t DAn;
12875 __IO uint32_t CNTn;
12876 __I uint32_t RESERVE0[1];
12879 __I uint32_t CSAn;
12880 __I uint32_t CDAn;
12881 __I uint32_t CCNTn;
12882 __IO uint32_t INTENn;
12883 __IO uint32_t INTSTSn;
12884 __IO uint32_t TOCn;
12886 } PDMA_CH_T;
12887
12888
12889
12890 typedef struct
12891 {
12892
12893
13233 __IO uint32_t CTL;
13234 __IO uint32_t DMASA;
13235 __I uint32_t RESERVE0[1];
13238 __IO uint32_t DMABCNT;
13239 __I uint32_t RESERVE1[1];
13242 __I uint32_t DMACSA;
13243 __I uint32_t RESERVE2[1];
13246 __I uint32_t DMACBCNT;
13247 __IO uint32_t DMAINTEN;
13248 __IO uint32_t DMAISTS;
13249 __I uint32_t RESERVE3[22];
13252 __IO uint32_t DAT;
13253 __IO uint32_t SEED;
13254 __I uint32_t CHECKSUM;
13256 } DMA_CRC_T;
13257
13258
13259
13260 typedef struct
13261 {
13262
13263
13473 __IO uint32_t GCTL;
13474 __IO uint32_t REQSEL0;
13475 __IO uint32_t REQSEL1;
13476 __I uint32_t GINTSTS;
13478 } DMA_GCR_T;
13479
13485 #define PDMA_CH_CTLn_CHEN_Pos (0)
13486 #define PDMA_CH_CTLn_CHEN_Msk (0x1ul << PDMA_CH_CTLn_CHEN_Pos)
13488 #define PDMA_CH_CTLn_SWRST_Pos (1)
13489 #define PDMA_CH_CTLn_SWRST_Msk (0x1ul << PDMA_CH_CTLn_SWRST_Pos)
13491 #define PDMA_CH_CTLn_SASEL_Pos (4)
13492 #define PDMA_CH_CTLn_SASEL_Msk (0x3ul << PDMA_CH_CTLn_SASEL_Pos)
13494 #define PDMA_CH_CTLn_DASEL_Pos (6)
13495 #define PDMA_CH_CTLn_DASEL_Msk (0x3ul << PDMA_CH_CTLn_DASEL_Pos)
13497 #define PDMA_CH_CTLn_TOUTEN_Pos (12)
13498 #define PDMA_CH_CTLn_TOUTEN_Msk (0x1ul << PDMA_CH_CTLn_TOUTEN_Pos)
13500 #define PDMA_CH_CTLn_TXWIDTH_Pos (19)
13501 #define PDMA_CH_CTLn_TXWIDTH_Msk (0x3ul << PDMA_CH_CTLn_TXWIDTH_Pos)
13503 #define PDMA_CH_CTLn_TRIGEN_Pos (23)
13504 #define PDMA_CH_CTLn_TRIGEN_Msk (0x1ul << PDMA_CH_CTLn_TRIGEN_Pos)
13506 #define PDMA_CH_SAn_SA_Pos (0)
13507 #define PDMA_CH_SAn_SA_Msk (0xfffffffful << PDMA_CH_SAn_SA_Pos)
13509 #define PDMA_CH_DAn_DA_Pos (0)
13510 #define PDMA_CH_DAn_DA_Msk (0xfffffffful << PDMA_CH_DAn_DA_Pos)
13512 #define PDMA_CH_CNTn_TCNT_Pos (0)
13513 #define PDMA_CH_CNTn_TCNT_Msk (0xfffful << PDMA_CH_CNTn_TCNT_Pos)
13515 #define PDMA_CH_CNTn_PCNTITH_Pos (16)
13516 #define PDMA_CH_CNTn_PCNTITH_Msk (0xfffful << PDMA_CH_CNTn_PCNTITH_Pos)
13518 #define PDMA_CH_CSAn_CSA_Pos (0)
13519 #define PDMA_CH_CSAn_CSA_Msk (0xfffffffful << PDMA_CH_CSAn_CSA_Pos)
13521 #define PDMA_CH_CDAn_CDA_Pos (0)
13522 #define PDMA_CH_CDAn_CDA_Msk (0xfffffffful << PDMA_CH_CDAn_CDA_Pos)
13524 #define PDMA_CH_CCNTn_CCNT_Pos (0)
13525 #define PDMA_CH_CCNTn_CCNT_Msk (0xfffful << PDMA_CH_CCNTn_CCNT_Pos)
13527 #define PDMA_CH_INTENn_TABTIEN_Pos (0)
13528 #define PDMA_CH_INTENn_TABTIEN_Msk (0x1ul << PDMA_CH_INTENn_TABTIEN_Pos)
13530 #define PDMA_CH_INTENn_TDIEN_Pos (1)
13531 #define PDMA_CH_INTENn_TDIEN_Msk (0x1ul << PDMA_CH_INTENn_TDIEN_Pos)
13533 #define PDMA_CH_INTENn_TOUTIEN_Pos (6)
13534 #define PDMA_CH_INTENn_TOUTIEN_Msk (0x1ul << PDMA_CH_INTENn_TOUTIEN_Pos)
13536 #define PDMA_CH_INTENn_PCNTIEN_Pos (8)
13537 #define PDMA_CH_INTENn_PCNTIEN_Msk (0x1ul << PDMA_CH_INTENn_PCNTIEN_Pos)
13539 #define PDMA_CH_INTSTSn_TABTIF_Pos (0)
13540 #define PDMA_CH_INTSTSn_TABTIF_Msk (0x1ul << PDMA_CH_INTSTSn_TABTIF_Pos)
13542 #define PDMA_CH_INTSTSn_TDIF_Pos (1)
13543 #define PDMA_CH_INTSTSn_TDIF_Msk (0x1ul << PDMA_CH_INTSTSn_TDIF_Pos)
13545 #define PDMA_CH_INTSTSn_TOUTIF_Pos (6)
13546 #define PDMA_CH_INTSTSn_TOUTIF_Msk (0x1ul << PDMA_CH_INTSTSn_TOUTIF_Pos)
13548 #define PDMA_CH_INTSTSn_PCNTIF_Pos (8)
13549 #define PDMA_CH_INTSTSn_PCNTIF_Msk (0x1ul << PDMA_CH_INTSTSn_PCNTIF_Pos)
13551 #define PDMA_CH_TOCn_TOC_Pos (0)
13552 #define PDMA_CH_TOCn_TOC_Msk (0xfffful << PDMA_CH_TOCn_TOC_Pos)
13554 #define PDMA_CH_TOCn_TPSC_Pos (16)
13555 #define PDMA_CH_TOCn_TPSC_Msk (0x7ul << PDMA_CH_TOCn_TPSC_Pos) /* PDMA_CH_CONST */
13558
13559
13565 #define DMA_CRC_CTL_CRCEN_Pos (0)
13566 #define DMA_CRC_CTL_CRCEN_Msk (0x1ul << DMA_CRC_CTL_CRCEN_Pos)
13568 #define DMA_CRC_CTL_CRCRST_Pos (1)
13569 #define DMA_CRC_CTL_CRCRST_Msk (0x1ul << DMA_CRC_CTL_CRCRST_Pos)
13571 #define DMA_CRC_CTL_TRIGEN_Pos (23)
13572 #define DMA_CRC_CTL_TRIGEN_Msk (0x1ul << DMA_CRC_CTL_TRIGEN_Pos)
13574 #define DMA_CRC_CTL_DATREV_Pos (24)
13575 #define DMA_CRC_CTL_DATREV_Msk (0x1ul << DMA_CRC_CTL_DATREV_Pos)
13577 #define DMA_CRC_CTL_CHKSREV_Pos (25)
13578 #define DMA_CRC_CTL_CHKSREV_Msk (0x1ul << DMA_CRC_CTL_CHKSREV_Pos)
13580 #define DMA_CRC_CTL_DATFMT_Pos (26)
13581 #define DMA_CRC_CTL_DATFMT_Msk (0x1ul << DMA_CRC_CTL_DATFMT_Pos)
13583 #define DMA_CRC_CTL_CHKSFMT_Pos (27)
13584 #define DMA_CRC_CTL_CHKSFMT_Msk (0x1ul << DMA_CRC_CTL_CHKSFMT_Pos)
13586 #define DMA_CRC_CTL_DATLEN_Pos (28)
13587 #define DMA_CRC_CTL_DATLEN_Msk (0x3ul << DMA_CRC_CTL_DATLEN_Pos)
13589 #define DMA_CRC_CTL_CRCMODE_Pos (30)
13590 #define DMA_CRC_CTL_CRCMODE_Msk (0x3ul << DMA_CRC_CTL_CRCMODE_Pos)
13592 #define DMA_CRC_DMASA_SA_Pos (0)
13593 #define DMA_CRC_DMASA_SA_Msk (0xfffffffful << DMA_CRC_DMASA_SA_Pos)
13595 #define DMA_CRC_DMABCNT_BCNT_Pos (0)
13596 #define DMA_CRC_DMABCNT_BCNT_Msk (0xfffful << DMA_CRC_DMABCNT_BCNT_Pos)
13598 #define DMA_CRC_DMACSA_CSA_Pos (0)
13599 #define DMA_CRC_DMACSA_CSA_Msk (0xfffffffful << DMA_CRC_DMACSA_CSA_Pos)
13601 #define DMA_CRC_DMACBCNT_CBCNT_Pos (0)
13602 #define DMA_CRC_DMACBCNT_CBCNT_Msk (0xfffful << DMA_CRC_DMACBCNT_CBCNT_Pos)
13604 #define DMA_CRC_DMAINTEN_TABTIEN_Pos (0)
13605 #define DMA_CRC_DMAINTEN_TABTIEN_Msk (0x1ul << DMA_CRC_DMAINTEN_TABTIEN_Pos)
13607 #define DMA_CRC_DMAINTEN_TDIEN_Pos (1)
13608 #define DMA_CRC_DMAINTEN_TDIEN_Msk (0x1ul << DMA_CRC_DMAINTEN_TDIEN_Pos)
13610 #define DMA_CRC_DMAISTS_TABTIF_Pos (0)
13611 #define DMA_CRC_DMAISTS_TABTIF_Msk (0x1ul << DMA_CRC_DMAISTS_TABTIF_Pos)
13613 #define DMA_CRC_DMAISTS_TDIF_Pos (1)
13614 #define DMA_CRC_DMAISTS_TDIF_Msk (0x1ul << DMA_CRC_DMAISTS_TDIF_Pos)
13616 #define DMA_CRC_DAT_DATA_Pos (0)
13617 #define DMA_CRC_DAT_DATA_Msk (0xfffffffful << DMA_CRC_DAT_DATA_Pos)
13619 #define DMA_CRC_SEED_SEED_Pos (0)
13620 #define DMA_CRC_SEED_SEED_Msk (0xfffffffful << DMA_CRC_SEED_SEED_Pos)
13622 #define DMA_CRC_CHECKSUM_CHECKSUM_Pos (0)
13623 #define DMA_CRC_CHECKSUM_CHECKSUM_Msk (0xfffffffful << DMA_CRC_CHECKSUM_CHECKSUM_Pos) /* CRC_CONST */
13626
13632 #define DMA_GCR_GCTL_CKEN1_Pos (9)
13633 #define DMA_GCR_GCTL_CKEN1_Msk (0x1ul << DMA_GCR_GCTL_CKEN1_Pos)
13635 #define DMA_GCR_GCTL_CKEN2_Pos (10)
13636 #define DMA_GCR_GCTL_CKEN2_Msk (0x1ul << DMA_GCR_GCTL_CKEN2_Pos)
13638 #define DMA_GCR_GCTL_CKEN3_Pos (11)
13639 #define DMA_GCR_GCTL_CKEN3_Msk (0x1ul << DMA_GCR_GCTL_CKEN3_Pos)
13641 #define DMA_GCR_GCTL_CKEN4_Pos (12)
13642 #define DMA_GCR_GCTL_CKEN4_Msk (0x1ul << DMA_GCR_GCTL_CKEN4_Pos)
13644 #define DMA_GCR_GCTL_CKENCRC_Pos (24)
13645 #define DMA_GCR_GCTL_CKENCRC_Msk (0x1ul << DMA_GCR_GCTL_CKENCRC_Pos)
13647 #define DMA_GCR_REQSEL0_REQSRC1_Pos (8)
13648 #define DMA_GCR_REQSEL0_REQSRC1_Msk (0x1ful << DMA_GCR_REQSEL0_REQSRC1_Pos)
13650 #define DMA_GCR_REQSEL0_REQSRC2_Pos (16)
13651 #define DMA_GCR_REQSEL0_REQSRC2_Msk (0x1ful << DMA_GCR_REQSEL0_REQSRC2_Pos)
13653 #define DMA_GCR_REQSEL0_REQSRC3_Pos (24)
13654 #define DMA_GCR_REQSEL0_REQSRC3_Msk (0x1ful << DMA_GCR_REQSEL0_REQSRC3_Pos)
13656 #define DMA_GCR_REQSEL1_REQSRC4_Pos (0)
13657 #define DMA_GCR_REQSEL1_REQSRC4_Msk (0x1ful << DMA_GCR_REQSEL1_REQSRC4_Pos)
13659 #define DMA_GCR_GINTSTS_IF1_Pos (1)
13660 #define DMA_GCR_GINTSTS_IF1_Msk (0x1ul << DMA_GCR_GINTSTS_IF1_Pos)
13662 #define DMA_GCR_GINTSTS_IF2_Pos (2)
13663 #define DMA_GCR_GINTSTS_IF2_Msk (0x1ul << DMA_GCR_GINTSTS_IF2_Pos)
13665 #define DMA_GCR_GINTSTS_IF3_Pos (3)
13666 #define DMA_GCR_GINTSTS_IF3_Msk (0x1ul << DMA_GCR_GINTSTS_IF3_Pos)
13668 #define DMA_GCR_GINTSTS_IF4_Pos (4)
13669 #define DMA_GCR_GINTSTS_IF4_Msk (0x1ul << DMA_GCR_GINTSTS_IF4_Pos)
13671 #define DMA_GCR_GINTSTS_IFCRC_Pos (16)
13672 #define DMA_GCR_GINTSTS_IFCRC_Msk (0x1ul << DMA_GCR_GINTSTS_IFCRC_Pos) /* PDMA_GCR_CONST */
13675 /* end of DMA register group */
13676
13677
13678 /*---------------------- Timer Controller -------------------------*/
13684 typedef struct
13685 {
13686
13687
14227 __IO uint32_t CTL;
14228 __IO uint32_t PRECNT;
14229 __IO uint32_t CMP;
14230 __IO uint32_t INTEN;
14231 __IO uint32_t INTSTS;
14232 __IO uint32_t CNT;
14233 __I uint32_t CAP;
14234 __I uint32_t RESERVE0[1];
14237 __IO uint32_t ECTL;
14239 } TIMER_T;
14240
14245 #define TIMER_CTL_CNTEN_Pos (0)
14246 #define TIMER_CTL_CNTEN_Msk (0x1ul << TIMER_CTL_CNTEN_Pos)
14248 #define TIMER_CTL_RSTCNT_Pos (1)
14249 #define TIMER_CTL_RSTCNT_Msk (0x1ul << TIMER_CTL_RSTCNT_Pos)
14251 #define TIMER_CTL_WKEN_Pos (2)
14252 #define TIMER_CTL_WKEN_Msk (0x1ul << TIMER_CTL_WKEN_Pos)
14254 #define TIMER_CTL_ICEDEBUG_Pos (3)
14255 #define TIMER_CTL_ICEDEBUG_Msk (0x1ul << TIMER_CTL_ICEDEBUG_Pos)
14257 #define TIMER_CTL_OPMODE_Pos (4)
14258 #define TIMER_CTL_OPMODE_Msk (0x3ul << TIMER_CTL_OPMODE_Pos)
14260 #define TIMER_CTL_ACTSTS_Pos (7)
14261 #define TIMER_CTL_ACTSTS_Msk (0x1ul << TIMER_CTL_ACTSTS_Pos)
14263 #define TIMER_CTL_TRGADC_Pos (8)
14264 #define TIMER_CTL_TRGADC_Msk (0x1ul << TIMER_CTL_TRGADC_Pos)
14266 #define TIMER_CTL_TRGPDMA_Pos (10)
14267 #define TIMER_CTL_TRGPDMA_Msk (0x1ul << TIMER_CTL_TRGPDMA_Pos)
14269 #define TIMER_CTL_TRGSSEL_Pos (11)
14270 #define TIMER_CTL_TRGSSEL_Msk (0x1ul << TIMER_CTL_TRGSSEL_Pos)
14272 #define TIMER_CTL_EXTCNTEN_Pos (12)
14273 #define TIMER_CTL_EXTCNTEN_Msk (0x1ul << TIMER_CTL_EXTCNTEN_Pos)
14275 #define TIMER_CTL_CNTPHASE_Pos (13)
14276 #define TIMER_CTL_CNTPHASE_Msk (0x1ul << TIMER_CTL_CNTPHASE_Pos)
14278 #define TIMER_CTL_CNTDBEN_Pos (14)
14279 #define TIMER_CTL_CNTDBEN_Msk (0x1ul << TIMER_CTL_CNTDBEN_Pos)
14281 #define TIMER_CTL_CAPEN_Pos (16)
14282 #define TIMER_CTL_CAPEN_Msk (0x1ul << TIMER_CTL_CAPEN_Pos)
14284 #define TIMER_CTL_CAPFUNCS_Pos (17)
14285 #define TIMER_CTL_CAPFUNCS_Msk (0x1ul << TIMER_CTL_CAPFUNCS_Pos)
14287 #define TIMER_CTL_CAPEDGE_Pos (18)
14288 #define TIMER_CTL_CAPEDGE_Msk (0x3ul << TIMER_CTL_CAPEDGE_Pos)
14290 #define TIMER_CTL_CAPCNTMD_Pos (20)
14291 #define TIMER_CTL_CAPCNTMD_Msk (0x1ul << TIMER_CTL_CAPCNTMD_Pos)
14293 #define TIMER_CTL_CAPDBEN_Pos (22)
14294 #define TIMER_CTL_CAPDBEN_Msk (0x1ul << TIMER_CTL_CAPDBEN_Pos)
14296 #define TIMER_CTL_CMPCTL_Pos (23)
14297 #define TIMER_CTL_CMPCTL_Msk (0x1ul << TIMER_CTL_CMPCTL_Pos)
14299 #define TIMER_CTL_INTRTGEN_Pos (24)
14300 #define TIMER_CTL_INTRTGEN_Msk (0x1ul << TIMER_CTL_INTRTGEN_Pos)
14302 #define TIMER_CTL_INTRTGMD_Pos (25)
14303 #define TIMER_CTL_INTRTGMD_Msk (0x1ul << TIMER_CTL_INTRTGMD_Pos)
14305 #define TIMER_CTL_TRGPWM_Pos (28)
14306 #define TIMER_CTL_TRGPWM_Msk (0x1ul << TIMER_CTL_TRGPWM_Pos)
14308 #define TIMER_PRECNT_PSC_Pos (0)
14309 #define TIMER_PRECNT_PSC_Msk (0xfful << TIMER_PRECNT_PSC_Pos)
14311 #define TIMER_CMP_CMPDAT_Pos (0)
14312 #define TIMER_CMP_CMPDAT_Msk (0xfffffful << TIMER_CMP_CMPDAT_P)
14314 #define TIMER_INTEN_CNTIEN_Pos (0)
14315 #define TIMER_INTEN_CNTIEN_Msk (0x1ul << TIMER_INTEN_CNTIEN_Pos)
14317 #define TIMER_INTEN_CAPIEN_Pos (1)
14318 #define TIMER_INTEN_CAPIEN_Msk (0x1ul << TIMER_INTEN_CAPIEN_Pos)
14320 #define TIMER_INTSTS_CNTIF_Pos (0)
14321 #define TIMER_INTSTS_CNTIF_Msk (0x1ul << TIMER_INTSTS_CNTIF_Pos)
14323 #define TIMER_INTSTS_CAPIF_Pos (1)
14324 #define TIMER_INTSTS_CAPIF_Msk (0x1ul << TIMER_INTSTS_CAPIF_Pos)
14326 #define TIMER_INTSTS_TWKF_Pos (4)
14327 #define TIMER_INTSTS_TWKF_Msk (0x1ul << TIMER_INTSTS_TWKF_Pos)
14329 #define TIMER_INTSTS_CAPDATOF_Pos (5)
14330 #define TIMER_INTSTS_CAPDATOF_Msk (0x1ul << TIMER_INTSTS_CAPDATOF_Pos)
14332 #define TIMER_INTSTS_CAPFEDF_Pos (6)
14333 #define TIMER_INTSTS_CAPFEDF_Msk (0x1ul << TIMER_INTSTS_CAPFEDF_Pos)
14335 #define TIMER_CNT_CNT_Pos (0)
14336 #define TIMER_CNT_CNT_Msk (0xfffffful << TIMER_CNT_CNT_Pos)
14338 #define TIMER_CNT_RSTACT_Pos (31)
14339 #define TIMER_CNT_RSTACT_Msk (0x1ul << TIMER_CNT_RSTACT_Pos)
14341 #define TIMER_CAP_CAPDAT_Pos (0)
14342 #define TIMER_CAP_CAPDAT_Msk (0xfffffful << TIMER_CAP_CAPDAT_Pos)
14344 #define TIMER_ECTL_EVNTDPCNT_Pos (24)
14345 #define TIMER_ECTL_EVNTDPCNT_Msk (0xfful << TIMER_ECTL_EVNTDPCNT_Pos) /* TMR_CONST */
14348 /* end of TMR register group */
14349
14350
14351 /*---------------------- Pulse Width Modulation Controller -------------------------*/
14357 typedef struct
14358 {
14359
14360
16815 __IO uint32_t CTL0;
16816 __IO uint32_t CTL1;
16817 __I uint32_t RESERVE0[2];
16820 __IO uint32_t CLKSRC;
16821 __IO uint32_t CLKPSC0_1;
16822 __IO uint32_t CLKPSC2_3;
16823 __IO uint32_t CLKPSC4_5;
16824 __IO uint32_t CNTEN;
16825 __IO uint32_t CNTCLR;
16826 __I uint32_t RESERVE1[2];
16829 __IO uint32_t PERIOD[6];
16830 __I uint32_t RESERVE4[2];
16833 __IO uint32_t CMPDAT[6];
16834 __I uint32_t RESERVE5[2];
16837 __IO uint32_t DTCTL0_1;
16838 __IO uint32_t DTCTL2_3;
16839 __IO uint32_t DTCTL4_5;
16840 __I uint32_t RESERVE6[5];
16843 __I uint32_t CNT[6];
16844 __I uint32_t RESERVE9[2];
16847 __IO uint32_t WGCTL0;
16848 __IO uint32_t WGCTL1;
16849 __IO uint32_t MSKEN;
16850 __IO uint32_t MSK;
16851 __IO uint32_t BNF;
16852 __IO uint32_t FAILBRK;
16853 __IO uint32_t BRKCTL0_1;
16854 __IO uint32_t BRKCTL2_3;
16855 __IO uint32_t BRKCTL4_5;
16856 __IO uint32_t POLCTL;
16857 __IO uint32_t POEN;
16858 __O uint32_t SWBRK;
16859 __IO uint32_t INTEN0;
16860 __IO uint32_t INTEN1;
16861 __IO uint32_t INTSTS0;
16862 __IO uint32_t INTSTS1;
16863 __I uint32_t RESERVE10[2];
16866 __IO uint32_t ADCTS0;
16867 __IO uint32_t ADCTS1;
16868 __I uint32_t RESERVE11[8];
16871 __IO uint32_t STATUS;
16872 __I uint32_t RESERVE12[55];
16875 __IO uint32_t CAPINEN;
16876 __IO uint32_t CAPCTL;
16877 __I uint32_t CAPSTS;
16878 __I uint32_t RCAPDAT0;
16879 __I uint32_t FCAPDAT0;
16880 __I uint32_t RCAPDAT1;
16881 __I uint32_t FCAPDAT1;
16882 __I uint32_t RCAPDAT2;
16883 __I uint32_t FCAPDAT2;
16884 __I uint32_t RCAPDAT3;
16885 __I uint32_t FCAPDAT3;
16886 __I uint32_t RCAPDAT4;
16887 __I uint32_t FCAPDAT4;
16888 __I uint32_t RCAPDAT5;
16889 __I uint32_t FCAPDAT5;
16890 __I uint32_t RESERVE13[5];
16893 __IO uint32_t CAPIEN;
16894 __IO uint32_t CAPIF;
16895 __I uint32_t RESERVE14[42];
16898 __IO uint32_t SELFTEST;
16899 __I uint32_t PBUF0;
16900 __I uint32_t RESERVE15[1];
16903 __I uint32_t PBUF2;
16904 __I uint32_t RESERVE16[1];
16907 __I uint32_t PBUF4;
16908 __I uint32_t RESERVE17[1];
16911 __I uint32_t CMPBUF0;
16912 __I uint32_t CMPBUF1;
16913 __I uint32_t CMPBUF2;
16914 __I uint32_t CMPBUF3;
16915 __I uint32_t CMPBUF4;
16916 __I uint32_t CMPBUF5;
16918 } PWM_T;
16919
16925 #define PWM_CTL0_CTRLDn_Pos (0)
16926 #define PWM_CTL0_CTRLDn_Msk (0x3ful << PWM_CTL0_CTRLDn_Pos)
16928 #define PWM_CTL0_IMMLDENn_Pos (16)
16929 #define PWM_CTL0_IMMLDENn_Msk (0x3ful << PWM_CTL0_IMMLDENn_Pos)
16931 #define PWM_CTL0_DBGHALT_Pos (30)
16932 #define PWM_CTL0_DBGHALT_Msk (0x1ul << PWM_CTL0_DBGHALT_Pos)
16934 #define PWM_CTL0_DBGTRIOFF_Pos (31)
16935 #define PWM_CTL0_DBGTRIOFF_Msk (0x1ul << PWM_CTL0_DBGTRIOFF_Pos)
16937 #define PWM_CTL1_CNTTYPE0_Pos (0)
16938 #define PWM_CTL1_CNTTYPE0_Msk (0x3ul << PWM_CTL1_CNTTYPE0_Pos)
16940 #define PWM_CTL1_CNTTYPE2_Pos (4)
16941 #define PWM_CTL1_CNTTYPE2_Msk (0x3ul << PWM_CTL1_CNTTYPE2_Pos)
16943 #define PWM_CTL1_CNTTYPE4_Pos (8)
16944 #define PWM_CTL1_CNTTYPE4_Msk (0x3ul << PWM_CTL1_CNTTYPE4_Pos)
16946 #define PWM_CTL1_PWMMODEn_Pos (24)
16947 #define PWM_CTL1_PWMMODEn_Msk (0x7ul << PWM_CTL1_PWMMODEn_Pos)
16949 #define PWM_CLKSRC_ECLKSRC0_Pos (0)
16950 #define PWM_CLKSRC_ECLKSRC0_Msk (0x7ul << PWM_CLKSRC_ECLKSRC0_Pos)
16952 #define PWM_CLKSRC_ECLKSRC2_Pos (8)
16953 #define PWM_CLKSRC_ECLKSRC2_Msk (0x7ul << PWM_CLKSRC_ECLKSRC2_Pos)
16955 #define PWM_CLKSRC_ECLKSRC4_Pos (16)
16956 #define PWM_CLKSRC_ECLKSRC4_Msk (0x7ul << PWM_CLKSRC_ECLKSRC4_Pos)
16958 #define PWM_CLKPSC0_1_CLKPSC_Pos (0)
16959 #define PWM_CLKPSC0_1_CLKPSC_Msk (0xffful << PWM_CLKPSC0_1_CLKPSC_Pos)
16961 #define PWM_CLKPSC2_3_CLKPSC_Pos (0)
16962 #define PWM_CLKPSC2_3_CLKPSC_Msk (0xffful << PWM_CLKPSC2_3_CLKPSC_Pos)
16964 #define PWM_CLKPSC4_5_CLKPSC_Pos (0)
16965 #define PWM_CLKPSC4_5_CLKPSC_Msk (0xffful << PWM_CLKPSC4_5_CLKPSC_Pos)
16967 #define PWM_CNTEN_CNTEN0_Pos (0)
16968 #define PWM_CNTEN_CNTEN0_Msk (0x1ul << PWM_CNTEN_CNTEN0_Pos)
16970 #define PWM_CNTEN_CNTEN2_Pos (2)
16971 #define PWM_CNTEN_CNTEN2_Msk (0x1ul << PWM_CNTEN_CNTEN2_Pos)
16973 #define PWM_CNTEN_CNTEN4_Pos (4)
16974 #define PWM_CNTEN_CNTEN4_Msk (0x1ul << PWM_CNTEN_CNTEN4_Pos)
16976 #define PWM_CNTCLR_CNTCLR0_Pos (0)
16977 #define PWM_CNTCLR_CNTCLR0_Msk (0x1ul << PWM_CNTCLR_CNTCLR0_Pos)
16979 #define PWM_CNTCLR_CNTCLR2_Pos (2)
16980 #define PWM_CNTCLR_CNTCLR2_Msk (0x1ul << PWM_CNTCLR_CNTCLR2_Pos)
16982 #define PWM_CNTCLR_CNTCLR4_Pos (4)
16983 #define PWM_CNTCLR_CNTCLR4_Msk (0x1ul << PWM_CNTCLR_CNTCLR4_Pos)
16985 #define PWM_PERIOD0_PERIOD_Pos (0)
16986 #define PWM_PERIOD0_PERIOD_Msk (0xfffful << PWM_PERIOD0_PERIOD_Pos)
16988 #define PWM_CMPDAT0_CMPDAT_Pos (0)
16989 #define PWM_CMPDAT0_CMPDAT_Msk (0xfffful << PWM_CMPDAT0_CMPDAT_Pos)
16991 #define PWM_DTCTL0_1_DTCNT_Pos (0)
16992 #define PWM_DTCTL0_1_DTCNT_Msk (0xffful << PWM_DTCTL0_1_DTCNT_Pos)
16994 #define PWM_DTCTL0_1_DTEN_Pos (16)
16995 #define PWM_DTCTL0_1_DTEN_Msk (0x1ul << PWM_DTCTL0_1_DTEN_Pos)
16997 #define PWM_DTCTL0_1_DTCKSEL_Pos (24)
16998 #define PWM_DTCTL0_1_DTCKSEL_Msk (0x1ul << PWM_DTCTL0_1_DTCKSEL_Pos)
17000 #define PWM_DTCTL2_3_DTCNT_Pos (0)
17001 #define PWM_DTCTL2_3_DTCNT_Msk (0xffful << PWM_DTCTL2_3_DTCNT_Pos)
17003 #define PWM_DTCTL2_3_DTEN_Pos (16)
17004 #define PWM_DTCTL2_3_DTEN_Msk (0x1ul << PWM_DTCTL2_3_DTEN_Pos)
17006 #define PWM_DTCTL2_3_DTCKSEL_Pos (24)
17007 #define PWM_DTCTL2_3_DTCKSEL_Msk (0x1ul << PWM_DTCTL2_3_DTCKSEL_Pos)
17009 #define PWM_DTCTL4_5_DTCNT_Pos (0)
17010 #define PWM_DTCTL4_5_DTCNT_Msk (0xffful << PWM_DTCTL4_5_DTCNT_Pos)
17012 #define PWM_DTCTL4_5_DTEN_Pos (16)
17013 #define PWM_DTCTL4_5_DTEN_Msk (0x1ul << PWM_DTCTL4_5_DTEN_Pos)
17015 #define PWM_DTCTL4_5_DTCKSEL_Pos (24)
17016 #define PWM_DTCTL4_5_DTCKSEL_Msk (0x1ul << PWM_DTCTL4_5_DTCKSEL_Pos)
17018 #define PWM_CNT0_CNT_Pos (0)
17019 #define PWM_CNT0_CNT_Msk (0xfffful << PWM_CNT0_CNT_Pos)
17021 #define PWM_CNT0_DIRF_Pos (16)
17022 #define PWM_CNT0_DIRF_Msk (0x1ul << PWM_CNT0_DIRF_Pos)
17024 #define PWM_WGCTL0_ZPCTLn_Pos (0)
17025 #define PWM_WGCTL0_ZPCTLn_Msk (0xffful << PWM_WGCTL0_ZPCTLn_Pos)
17027 #define PWM_WGCTL0_PRDPCTLn_Pos (16)
17028 #define PWM_WGCTL0_PRDPCTLn_Msk (0xffful << PWM_WGCTL0_PRDPCTLn_Pos)
17030 #define PWM_WGCTL1_CMPUCTLn_Pos (0)
17031 #define PWM_WGCTL1_CMPUCTLn_Msk (0xffful << PWM_WGCTL1_CMPUCTLn_Pos)
17033 #define PWM_WGCTL1_CMPDCTLn_Pos (16)
17034 #define PWM_WGCTL1_CMPDCTLn_Msk (0xffful << PWM_WGCTL1_CMPDCTLn_Pos)
17036 #define PWM_MSKEN_MSKENn_Pos (0)
17037 #define PWM_MSKEN_MSKENn_Msk (0x3ful << PWM_MSKEN_MSKENn_Pos)
17039 #define PWM_MSK_MSKDATn_Pos (0)
17040 #define PWM_MSK_MSKDATn_Msk (0x3ful << PWM_MSK_MSKDATn_Pos)
17042 #define PWM_BNF_BRK0FEN_Pos (0)
17043 #define PWM_BNF_BRK0FEN_Msk (0x1ul << PWM_BNF_BRK0FEN_Pos)
17045 #define PWM_BNF_BRK0FCS_Pos (1)
17046 #define PWM_BNF_BRK0FCS_Msk (0x7ul << PWM_BNF_BRK0FCS_Pos)
17048 #define PWM_BNF_BRK0FCNT_Pos (4)
17049 #define PWM_BNF_BRK0FCNT_Msk (0x7ul << PWM_BNF_BRK0FCNT_Pos)
17051 #define PWM_BNF_BRK0PINV_Pos (7)
17052 #define PWM_BNF_BRK0PINV_Msk (0x1ul << PWM_BNF_BRK0PINV_Pos)
17054 #define PWM_BNF_BRK1FEN_Pos (8)
17055 #define PWM_BNF_BRK1FEN_Msk (0x1ul << PWM_BNF_BRK1FEN_Pos)
17057 #define PWM_BNF_BRK1FCS_Pos (9)
17058 #define PWM_BNF_BRK1FCS_Msk (0x7ul << PWM_BNF_BRK1FCS_Pos)
17060 #define PWM_BNF_BRK1FCNT_Pos (12)
17061 #define PWM_BNF_BRK1FCNT_Msk (0x7ul << PWM_BNF_BRK1FCNT_Pos)
17063 #define PWM_BNF_BRK1PINV_Pos (15)
17064 #define PWM_BNF_BRK1PINV_Msk (0x1ul << PWM_BNF_BRK1PINV_Pos)
17066 #define PWM_BNF_BK0SRC_Pos (16)
17067 #define PWM_BNF_BK0SRC_Msk (0x1ul << PWM_BNF_BK0SRC_Pos)
17069 #define PWM_BNF_BK1SRC_Pos (24)
17070 #define PWM_BNF_BK1SRC_Msk (0x1ul << PWM_BNF_BK1SRC_Pos)
17072 #define PWM_FAILBRK_BODBRKEN_Pos (1)
17073 #define PWM_FAILBRK_BODBRKEN_Msk (0x1ul << PWM_FAILBRK_BODBRKEN_Pos)
17075 #define PWM_FAILBRK_CORBRKEN_Pos (3)
17076 #define PWM_FAILBRK_CORBRKEN_Msk (0x1ul << PWM_FAILBRK_CORBRKEN_Pos)
17078 #define PWM_BRKCTL0_1_BRKP0EEN_Pos (4)
17079 #define PWM_BRKCTL0_1_BRKP0EEN_Msk (0x1ul << PWM_BRKCTL0_1_BRKP0EEN_Pos)
17081 #define PWM_BRKCTL0_1_BRKP1EEN_Pos (5)
17082 #define PWM_BRKCTL0_1_BRKP1EEN_Msk (0x1ul << PWM_BRKCTL0_1_BRKP1EEN_Pos)
17084 #define PWM_BRKCTL0_1_SYSEEN_Pos (7)
17085 #define PWM_BRKCTL0_1_SYSEEN_Msk (0x1ul << PWM_BRKCTL0_1_SYSEEN_Pos)
17087 #define PWM_BRKCTL0_1_BRKP0LEN_Pos (12)
17088 #define PWM_BRKCTL0_1_BRKP0LEN_Msk (0x1ul << PWM_BRKCTL0_1_BRKP0LEN_Pos)
17090 #define PWM_BRKCTL0_1_BRKP1LEN_Pos (13)
17091 #define PWM_BRKCTL0_1_BRKP1LEN_Msk (0x1ul << PWM_BRKCTL0_1_BRKP1LEN_Pos)
17093 #define PWM_BRKCTL0_1_SYSLEN_Pos (15)
17094 #define PWM_BRKCTL0_1_SYSLEN_Msk (0x1ul << PWM_BRKCTL0_1_SYSLEN_Pos)
17096 #define PWM_BRKCTL0_1_BRKAEVEN_Pos (16)
17097 #define PWM_BRKCTL0_1_BRKAEVEN_Msk (0x3ul << PWM_BRKCTL0_1_BRKAEVEN_Pos)
17099 #define PWM_BRKCTL0_1_BRKAODD_Pos (18)
17100 #define PWM_BRKCTL0_1_BRKAODD_Msk (0x3ul << PWM_BRKCTL0_1_BRKAODD_Pos)
17102 #define PWM_BRKCTL2_3_BRKP0EEN_Pos (4)
17103 #define PWM_BRKCTL2_3_BRKP0EEN_Msk (0x1ul << PWM_BRKCTL2_3_BRKP0EEN_Pos)
17105 #define PWM_BRKCTL2_3_BRKP1EEN_Pos (5)
17106 #define PWM_BRKCTL2_3_BRKP1EEN_Msk (0x1ul << PWM_BRKCTL2_3_BRKP1EEN_Pos)
17108 #define PWM_BRKCTL2_3_SYSEEN_Pos (7)
17109 #define PWM_BRKCTL2_3_SYSEEN_Msk (0x1ul << PWM_BRKCTL2_3_SYSEEN_Pos)
17111 #define PWM_BRKCTL2_3_BRKP0LEN_Pos (12)
17112 #define PWM_BRKCTL2_3_BRKP0LEN_Msk (0x1ul << PWM_BRKCTL2_3_BRKP0LEN_Pos)
17114 #define PWM_BRKCTL2_3_BRKP1LEN_Pos (13)
17115 #define PWM_BRKCTL2_3_BRKP1LEN_Msk (0x1ul << PWM_BRKCTL2_3_BRKP1LEN_Pos)
17117 #define PWM_BRKCTL2_3_SYSLEN_Pos (15)
17118 #define PWM_BRKCTL2_3_SYSLEN_Msk (0x1ul << PWM_BRKCTL2_3_SYSLEN_Pos)
17120 #define PWM_BRKCTL2_3_BRKAEVEN_Pos (16)
17121 #define PWM_BRKCTL2_3_BRKAEVEN_Msk (0x3ul << PWM_BRKCTL2_3_BRKAEVEN_Pos)
17123 #define PWM_BRKCTL2_3_BRKAODD_Pos (18)
17124 #define PWM_BRKCTL2_3_BRKAODD_Msk (0x3ul << PWM_BRKCTL2_3_BRKAODD_Pos)
17126 #define PWM_BRKCTL4_5_BRKP0EEN_Pos (4)
17127 #define PWM_BRKCTL4_5_BRKP0EEN_Msk (0x1ul << PWM_BRKCTL4_5_BRKP0EEN_Pos)
17129 #define PWM_BRKCTL4_5_BRKP1EEN_Pos (5)
17130 #define PWM_BRKCTL4_5_BRKP1EEN_Msk (0x1ul << PWM_BRKCTL4_5_BRKP1EEN_Pos)
17132 #define PWM_BRKCTL4_5_SYSEEN_Pos (7)
17133 #define PWM_BRKCTL4_5_SYSEEN_Msk (0x1ul << PWM_BRKCTL4_5_SYSEEN_Pos)
17135 #define PWM_BRKCTL4_5_BRKP0LEN_Pos (12)
17136 #define PWM_BRKCTL4_5_BRKP0LEN_Msk (0x1ul << PWM_BRKCTL4_5_BRKP0LEN_Pos)
17138 #define PWM_BRKCTL4_5_BRKP1LEN_Pos (13)
17139 #define PWM_BRKCTL4_5_BRKP1LEN_Msk (0x1ul << PWM_BRKCTL4_5_BRKP1LEN_Pos)
17141 #define PWM_BRKCTL4_5_SYSLEN_Pos (15)
17142 #define PWM_BRKCTL4_5_SYSLEN_Msk (0x1ul << PWM_BRKCTL4_5_SYSLEN_Pos)
17144 #define PWM_BRKCTL4_5_BRKAEVEN_Pos (16)
17145 #define PWM_BRKCTL4_5_BRKAEVEN_Msk (0x3ul << PWM_BRKCTL4_5_BRKAEVEN_Pos)
17147 #define PWM_BRKCTL4_5_BRKAODD_Pos (18)
17148 #define PWM_BRKCTL4_5_BRKAODD_Msk (0x3ul << PWM_BRKCTL4_5_BRKAODD_Pos)
17150 #define PWM_POLCTL_PINVn_Pos (0)
17151 #define PWM_POLCTL_PINVn_Msk (0x3ful << PWM_POLCTL_PINVn_Pos)
17153 #define PWM_POEN_POENn_Pos (0)
17154 #define PWM_POEN_POENn_Msk (0x3ful << PWM_POEN_POENn_Pos)
17156 #define PWM_SWBRK_BRKETRGn_Pos (0)
17157 #define PWM_SWBRK_BRKETRGn_Msk (0x7ul << PWM_SWBRK_BRKETRGn_Pos)
17159 #define PWM_SWBRK_BRKLTRGn_Pos (8)
17160 #define PWM_SWBRK_BRKLTRGn_Msk (0x7ul << PWM_SWBRK_BRKLTRGn_Pos)
17162 #define PWM_INTEN0_ZIEN0_Pos (0)
17163 #define PWM_INTEN0_ZIEN0_Msk (0x1ul << PWM_INTEN0_ZIEN0_Pos)
17165 #define PWM_INTEN0_ZIEN2_Pos (2)
17166 #define PWM_INTEN0_ZIEN2_Msk (0x1ul << PWM_INTEN0_ZIEN2_Pos)
17168 #define PWM_INTEN0_ZIEN4_Pos (4)
17169 #define PWM_INTEN0_ZIEN4_Msk (0x1ul << PWM_INTEN0_ZIEN4_Pos)
17171 #define PWM_INTEN0_PIEN0_Pos (8)
17172 #define PWM_INTEN0_PIEN0_Msk (0x1ul << PWM_INTEN0_PIEN0_Pos)
17174 #define PWM_INTEN0_PIEN2_Pos (10)
17175 #define PWM_INTEN0_PIEN2_Msk (0x1ul << PWM_INTEN0_PIEN2_Pos)
17177 #define PWM_INTEN0_PIEN4_Pos (12)
17178 #define PWM_INTEN0_PIEN4_Msk (0x1ul << PWM_INTEN0_PIEN4_Pos)
17180 #define PWM_INTEN0_CMPUIENn_Pos (16)
17181 #define PWM_INTEN0_CMPUIENn_Msk (0x3ful << PWM_INTEN0_CMPUIENn_Pos)
17183 #define PWM_INTEN0_CMPDIENn_Pos (24)
17184 #define PWM_INTEN0_CMPDIENn_Msk (0x3ful << PWM_INTEN0_CMPDIENn_Pos)
17186 #define PWM_INTEN1_BRKEIEN0_1_Pos (0)
17187 #define PWM_INTEN1_BRKEIEN0_1_Msk (0x1ul << PWM_INTEN1_BRKEIEN0_1_Pos)
17189 #define PWM_INTEN1_BRKEIEN2_3_Pos (1)
17190 #define PWM_INTEN1_BRKEIEN2_3_Msk (0x1ul << PWM_INTEN1_BRKEIEN2_3_Pos)
17192 #define PWM_INTEN1_BRKEIEN4_5_Pos (2)
17193 #define PWM_INTEN1_BRKEIEN4_5_Msk (0x1ul << PWM_INTEN1_BRKEIEN4_5_Pos)
17195 #define PWM_INTEN1_BRKLIEN0_1_Pos (8)
17196 #define PWM_INTEN1_BRKLIEN0_1_Msk (0x1ul << PWM_INTEN1_BRKLIEN0_1_Pos)
17198 #define PWM_INTEN1_BRKLIEN2_3_Pos (9)
17199 #define PWM_INTEN1_BRKLIEN2_3_Msk (0x1ul << PWM_INTEN1_BRKLIEN2_3_Pos)
17201 #define PWM_INTEN1_BRKLIEN4_5_Pos (10)
17202 #define PWM_INTEN1_BRKLIEN4_5_Msk (0x1ul << PWM_INTEN1_BRKLIEN4_5_Pos)
17204 #define PWM_INTSTS0_ZIF0_Pos (0)
17205 #define PWM_INTSTS0_ZIF0_Msk (0x1ul << PWM_INTSTS0_ZIF0_Pos)
17207 #define PWM_INTSTS0_ZIF2_Pos (2)
17208 #define PWM_INTSTS0_ZIF2_Msk (0x1ul << PWM_INTSTS0_ZIF2_Pos)
17210 #define PWM_INTSTS0_ZIF4_Pos (4)
17211 #define PWM_INTSTS0_ZIF4_Msk (0x1ul << PWM_INTSTS0_ZIF4_Pos)
17213 #define PWM_INTSTS0_PIF0_Pos (8)
17214 #define PWM_INTSTS0_PIF0_Msk (0x1ul << PWM_INTSTS0_PIF0_Pos)
17216 #define PWM_INTSTS0_PIF2_Pos (10)
17217 #define PWM_INTSTS0_PIF2_Msk (0x1ul << PWM_INTSTS0_PIF2_Pos)
17219 #define PWM_INTSTS0_PIF4_Pos (12)
17220 #define PWM_INTSTS0_PIF4_Msk (0x1ul << PWM_INTSTS0_PIF4_Pos)
17222 #define PWM_INTSTS0_CMPUIFn_Pos (16)
17223 #define PWM_INTSTS0_CMPUIFn_Msk (0x3ful << PWM_INTSTS0_CMPUIFn_Pos)
17225 #define PWM_INTSTS0_CMPDIFn_Pos (24)
17226 #define PWM_INTSTS0_CMPDIFn_Msk (0x3ful << PWM_INTSTS0_CMPDIFn_Pos)
17228 #define PWM_INTSTS1_BRKEIF0_Pos (0)
17229 #define PWM_INTSTS1_BRKEIF0_Msk (0x1ul << PWM_INTSTS1_BRKEIF0_Pos)
17231 #define PWM_INTSTS1_BRKEIF1_Pos (1)
17232 #define PWM_INTSTS1_BRKEIF1_Msk (0x1ul << PWM_INTSTS1_BRKEIF1_Pos)
17234 #define PWM_INTSTS1_BRKEIF2_Pos (2)
17235 #define PWM_INTSTS1_BRKEIF2_Msk (0x1ul << PWM_INTSTS1_BRKEIF2_Pos)
17237 #define PWM_INTSTS1_BRKEIF3_Pos (3)
17238 #define PWM_INTSTS1_BRKEIF3_Msk (0x1ul << PWM_INTSTS1_BRKEIF3_Pos)
17240 #define PWM_INTSTS1_BRKEIF4_Pos (4)
17241 #define PWM_INTSTS1_BRKEIF4_Msk (0x1ul << PWM_INTSTS1_BRKEIF4_Pos)
17243 #define PWM_INTSTS1_BRKEIF5_Pos (5)
17244 #define PWM_INTSTS1_BRKEIF5_Msk (0x1ul << PWM_INTSTS1_BRKEIF5_Pos)
17246 #define PWM_INTSTS1_BRKLIF0_Pos (8)
17247 #define PWM_INTSTS1_BRKLIF0_Msk (0x1ul << PWM_INTSTS1_BRKLIF0_Pos)
17249 #define PWM_INTSTS1_BRKLIF1_Pos (9)
17250 #define PWM_INTSTS1_BRKLIF1_Msk (0x1ul << PWM_INTSTS1_BRKLIF1_Pos)
17252 #define PWM_INTSTS1_BRKLIF2_Pos (10)
17253 #define PWM_INTSTS1_BRKLIF2_Msk (0x1ul << PWM_INTSTS1_BRKLIF2_Pos)
17255 #define PWM_INTSTS1_BRKLIF3_Pos (11)
17256 #define PWM_INTSTS1_BRKLIF3_Msk (0x1ul << PWM_INTSTS1_BRKLIF3_Pos)
17258 #define PWM_INTSTS1_BRKLIF4_Pos (12)
17259 #define PWM_INTSTS1_BRKLIF4_Msk (0x1ul << PWM_INTSTS1_BRKLIF4_Pos)
17261 #define PWM_INTSTS1_BRKLIF5_Pos (13)
17262 #define PWM_INTSTS1_BRKLIF5_Msk (0x1ul << PWM_INTSTS1_BRKLIF5_Pos)
17264 #define PWM_INTSTS1_BRKESTS0_Pos (16)
17265 #define PWM_INTSTS1_BRKESTS0_Msk (0x1ul << PWM_INTSTS1_BRKESTS0_Pos)
17267 #define PWM_INTSTS1_BRKESTS1_Pos (17)
17268 #define PWM_INTSTS1_BRKESTS1_Msk (0x1ul << PWM_INTSTS1_BRKESTS1_Pos)
17270 #define PWM_INTSTS1_BRKESTS2_Pos (18)
17271 #define PWM_INTSTS1_BRKESTS2_Msk (0x1ul << PWM_INTSTS1_BRKESTS2_Pos)
17273 #define PWM_INTSTS1_BRKESTS3_Pos (19)
17274 #define PWM_INTSTS1_BRKESTS3_Msk (0x1ul << PWM_INTSTS1_BRKESTS3_Pos)
17276 #define PWM_INTSTS1_BRKESTS4_Pos (20)
17277 #define PWM_INTSTS1_BRKESTS4_Msk (0x1ul << PWM_INTSTS1_BRKESTS4_Pos)
17279 #define PWM_INTSTS1_BRKESTS5_Pos (21)
17280 #define PWM_INTSTS1_BRKESTS5_Msk (0x1ul << PWM_INTSTS1_BRKESTS5_Pos)
17282 #define PWM_INTSTS1_BRKLSTS0_Pos (24)
17283 #define PWM_INTSTS1_BRKLSTS0_Msk (0x1ul << PWM_INTSTS1_BRKLSTS0_Pos)
17285 #define PWM_INTSTS1_BRKLSTS1_Pos (25)
17286 #define PWM_INTSTS1_BRKLSTS1_Msk (0x1ul << PWM_INTSTS1_BRKLSTS1_Pos)
17288 #define PWM_INTSTS1_BRKLSTS2_Pos (26)
17289 #define PWM_INTSTS1_BRKLSTS2_Msk (0x1ul << PWM_INTSTS1_BRKLSTS2_Pos)
17291 #define PWM_INTSTS1_BRKLSTS3_Pos (27)
17292 #define PWM_INTSTS1_BRKLSTS3_Msk (0x1ul << PWM_INTSTS1_BRKLSTS3_Pos)
17294 #define PWM_INTSTS1_BRKLSTS4_Pos (28)
17295 #define PWM_INTSTS1_BRKLSTS4_Msk (0x1ul << PWM_INTSTS1_BRKLSTS4_Pos)
17297 #define PWM_INTSTS1_BRKLSTS5_Pos (29)
17298 #define PWM_INTSTS1_BRKLSTS5_Msk (0x1ul << PWM_INTSTS1_BRKLSTS5_Pos)
17300 #define PWM_ADCTS0_TRGSEL0_Pos (0)
17301 #define PWM_ADCTS0_TRGSEL0_Msk (0xful << PWM_ADCTS0_TRGSEL0_Pos)
17303 #define PWM_ADCTS0_TRGEN0_Pos (7)
17304 #define PWM_ADCTS0_TRGEN0_Msk (0x1ul << PWM_ADCTS0_TRGEN0_Pos)
17306 #define PWM_ADCTS0_TRGSEL1_Pos (8)
17307 #define PWM_ADCTS0_TRGSEL1_Msk (0xful << PWM_ADCTS0_TRGSEL1_Pos)
17309 #define PWM_ADCTS0_TRGEN1_Pos (15)
17310 #define PWM_ADCTS0_TRGEN1_Msk (0x1ul << PWM_ADCTS0_TRGEN1_Pos)
17312 #define PWM_ADCTS0_TRGSEL2_Pos (16)
17313 #define PWM_ADCTS0_TRGSEL2_Msk (0xful << PWM_ADCTS0_TRGSEL2_Pos)
17315 #define PWM_ADCTS0_TRGEN2_Pos (23)
17316 #define PWM_ADCTS0_TRGEN2_Msk (0x1ul << PWM_ADCTS0_TRGEN2_Pos)
17318 #define PWM_ADCTS0_TRGSEL3_Pos (24)
17319 #define PWM_ADCTS0_TRGSEL3_Msk (0xful << PWM_ADCTS0_TRGSEL3_Pos)
17321 #define PWM_ADCTS0_TRGEN3_Pos (31)
17322 #define PWM_ADCTS0_TRGEN3_Msk (0x1ul << PWM_ADCTS0_TRGEN3_Pos)
17324 #define PWM_ADCTS1_TRGSEL4_Pos (0)
17325 #define PWM_ADCTS1_TRGSEL4_Msk (0xful << PWM_ADCTS1_TRGSEL4_Pos)
17327 #define PWM_ADCTS1_TRGEN4_Pos (7)
17328 #define PWM_ADCTS1_TRGEN4_Msk (0x1ul << PWM_ADCTS1_TRGEN4_Pos)
17330 #define PWM_ADCTS1_TRGSEL5_Pos (8)
17331 #define PWM_ADCTS1_TRGSEL5_Msk (0xful << PWM_ADCTS1_TRGSEL5_Pos)
17333 #define PWM_ADCTS1_TRGEN5_Pos (15)
17334 #define PWM_ADCTS1_TRGEN5_Msk (0x1ul << PWM_ADCTS1_TRGEN5_Pos)
17336 #define PWM_STATUS_CNTMAX0_Pos (0)
17337 #define PWM_STATUS_CNTMAX0_Msk (0x1ul << PWM_STATUS_CNTMAX0_Pos)
17339 #define PWM_STATUS_CNTMAX2_Pos (2)
17340 #define PWM_STATUS_CNTMAX2_Msk (0x1ul << PWM_STATUS_CNTMAX2_Pos)
17342 #define PWM_STATUS_CNTMAX4_Pos (4)
17343 #define PWM_STATUS_CNTMAX4_Msk (0x1ul << PWM_STATUS_CNTMAX4_Pos)
17345 #define PWM_STATUS_ADCTRGn_Pos (16)
17346 #define PWM_STATUS_ADCTRGn_Msk (0x3ful << PWM_STATUS_ADCTRGn_Pos)
17348 #define PWM_CAPINEN_CAPINENn_Pos (0)
17349 #define PWM_CAPINEN_CAPINENn_Msk (0x3ful << PWM_CAPINEN_CAPINENn_Pos)
17351 #define PWM_CAPCTL_CAPENn_Pos (0)
17352 #define PWM_CAPCTL_CAPENn_Msk (0x3ful << PWM_CAPCTL_CAPENn_Pos)
17354 #define PWM_CAPCTL_CAPINVn_Pos (8)
17355 #define PWM_CAPCTL_CAPINVn_Msk (0x3ful << PWM_CAPCTL_CAPINVn_Pos)
17357 #define PWM_CAPCTL_RCRLDENn_Pos (16)
17358 #define PWM_CAPCTL_RCRLDENn_Msk (0x3ful << PWM_CAPCTL_RCRLDENn_Pos)
17360 #define PWM_CAPCTL_FCRLDENn_Pos (24)
17361 #define PWM_CAPCTL_FCRLDENn_Msk (0x3ful << PWM_CAPCTL_FCRLDENn_Pos)
17363 #define PWM_CAPSTS_CRIFOVn_Pos (0)
17364 #define PWM_CAPSTS_CRIFOVn_Msk (0x3ful << PWM_CAPSTS_CRIFOVn_Pos)
17366 #define PWM_CAPSTS_CFIFOVn_Pos (8)
17367 #define PWM_CAPSTS_CFIFOVn_Msk (0x3ful << PWM_CAPSTS_CFIFOVn_Pos)
17369 #define PWM_RCAPDAT0_RCAPDAT_Pos (0)
17370 #define PWM_RCAPDAT0_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT0_RCAPDAT_Pos)
17372 #define PWM_FCAPDAT0_FCAPDAT_Pos (0)
17373 #define PWM_FCAPDAT0_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT0_FCAPDAT_Pos)
17375 #define PWM_RCAPDAT1_RCAPDAT_Pos (0)
17376 #define PWM_RCAPDAT1_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT1_RCAPDAT_Pos)
17378 #define PWM_FCAPDAT1_FCAPDAT_Pos (0)
17379 #define PWM_FCAPDAT1_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT1_FCAPDAT_Pos)
17381 #define PWM_RCAPDAT2_RCAPDAT_Pos (0)
17382 #define PWM_RCAPDAT2_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT2_RCAPDAT_Pos)
17384 #define PWM_FCAPDAT2_FCAPDAT_Pos (0)
17385 #define PWM_FCAPDAT2_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT2_FCAPDAT_Pos)
17387 #define PWM_RCAPDAT3_RCAPDAT_Pos (0)
17388 #define PWM_RCAPDAT3_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT3_RCAPDAT_Pos)
17390 #define PWM_FCAPDAT3_FCAPDAT_Pos (0)
17391 #define PWM_FCAPDAT3_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT3_FCAPDAT_Pos)
17393 #define PWM_RCAPDAT4_RCAPDAT_Pos (0)
17394 #define PWM_RCAPDAT4_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT4_RCAPDAT_Pos)
17396 #define PWM_FCAPDAT4_FCAPDAT_Pos (0)
17397 #define PWM_FCAPDAT4_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT4_FCAPDAT_Pos)
17399 #define PWM_RCAPDAT5_RCAPDAT_Pos (0)
17400 #define PWM_RCAPDAT5_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT5_RCAPDAT_Pos)
17402 #define PWM_FCAPDAT5_FCAPDAT_Pos (0)
17403 #define PWM_FCAPDAT5_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT5_FCAPDAT_Pos)
17405 #define PWM_CAPIEN_CAPRIENn_Pos (0)
17406 #define PWM_CAPIEN_CAPRIENn_Msk (0x3ful << PWM_CAPIEN_CAPRIENn_Pos)
17408 #define PWM_CAPIEN_CAPFIENn_Pos (8)
17409 #define PWM_CAPIEN_CAPFIENn_Msk (0x3ful << PWM_CAPIEN_CAPFIENn_Pos)
17411 #define PWM_CAPIF_CAPRIFn_Pos (0)
17412 #define PWM_CAPIF_CAPRIFn_Msk (0x3ful << PWM_CAPIF_CAPRIFn_Pos)
17414 #define PWM_CAPIF_CAPFIFn_Pos (8)
17415 #define PWM_CAPIF_CAPFIFn_Msk (0x3ful << PWM_CAPIF_CAPFIFn_Pos)
17417 #define PWM_PBUF0_PBUF_Pos (0)
17418 #define PWM_PBUF0_PBUF_Msk (0xfffful << PWM_PBUF0_PBUF_Pos)
17420 #define PWM_PBUF2_PBUF_Pos (0)
17421 #define PWM_PBUF2_PBUF_Msk (0xfffful << PWM_PBUF2_PBUF_Pos)
17423 #define PWM_PBUF4_PBUF_Pos (0)
17424 #define PWM_PBUF4_PBUF_Msk (0xfffful << PWM_PBUF4_PBUF_Pos)
17426 #define PWM_CMPBUF0_CMPBUF_Pos (0)
17427 #define PWM_CMPBUF0_CMPBUF_Msk (0xfffful << PWM_CMPBUF0_CMPBUF_Pos)
17429 #define PWM_CMPBUF1_CMPBUF_Pos (0)
17430 #define PWM_CMPBUF1_CMPBUF_Msk (0xfffful << PWM_CMPBUF1_CMPBUF_Pos)
17432 #define PWM_CMPBUF2_CMPBUF_Pos (0)
17433 #define PWM_CMPBUF2_CMPBUF_Msk (0xfffful << PWM_CMPBUF2_CMPBUF_Pos)
17435 #define PWM_CMPBUF3_CMPBUF_Pos (0)
17436 #define PWM_CMPBUF3_CMPBUF_Msk (0xfffful << PWM_CMPBUF3_CMPBUF_Pos)
17438 #define PWM_CMPBUF4_CMPBUF_Pos (0)
17439 #define PWM_CMPBUF4_CMPBUF_Msk (0xfffful << PWM_CMPBUF4_CMPBUF_Pos)
17441 #define PWM_CMPBUF5_CMPBUF_Pos (0)
17442 #define PWM_CMPBUF5_CMPBUF_Msk (0xfffful << PWM_CMPBUF5_CMPBUF_Pos) /* PWM_CONST */
17445 /* end of PWM register group */
17446
17447
17448 /*---------------------- Watch Dog Timer Controller -------------------------*/
17454 typedef struct
17455 {
17456
17457
17627 __IO uint32_t CTL;
17628 __IO uint32_t INTEN;
17629 __IO uint32_t STATUS;
17631 } WDT_T;
17632
17638 #define WDT_CTL_RSTCNT_Pos (0)
17639 #define WDT_CTL_RSTCNT_Msk (0x1ul << WDT_CTL_RSTCNT_Pos)
17641 #define WDT_CTL_RSTEN_Pos (1)
17642 #define WDT_CTL_RSTEN_Msk (0x1ul << WDT_CTL_RSTEN_Pos)
17644 #define WDT_CTL_WKEN_Pos (2)
17645 #define WDT_CTL_WKEN_Msk (0x1ul << WDT_CTL_WKEN_Pos)
17647 #define WDT_CTL_WDTEN_Pos (3)
17648 #define WDT_CTL_WDTEN_Msk (0x1ul << WDT_CTL_WDTEN_Pos)
17650 #define WDT_CTL_WTIS_Pos (4)
17651 #define WDT_CTL_WTIS_Msk (0x7ul << WDT_CTL_WTIS_Pos)
17653 #define WDT_CTL_WTRDSEL_Pos (8)
17654 #define WDT_CTL_WTRDSEL_Msk (0x3ul << WDT_CTL_WTRDSEL_Pos)
17656 #define WDT_CTL_DBGEN_Pos (31)
17657 #define WDT_CTL_DBGEN_Msk (0x1ul << WDT_CTL_DBGEN_Pos)
17659 #define WDT_INTEN_WDTIE_Pos (0)
17660 #define WDT_INTEN_WDTIE_Msk (0x1ul << WDT_INTEN_WDTIE_Pos)
17662 #define WDT_STATUS_WDTIF_Pos (0)
17663 #define WDT_STATUS_WDTIF_Msk (0x1ul << WDT_STATUS_WDTIF_Pos)
17665 #define WDT_STATUS_RSTF_Pos (1)
17666 #define WDT_STATUS_RSTF_Msk (0x1ul << WDT_STATUS_RSTF_Pos)
17668 #define WDT_STATUS_WKF_Pos (2)
17669 #define WDT_STATUS_WKF_Msk (0x1ul << WDT_STATUS_WKF_Pos) /* WDT_CONST */
17672 /* end of WDT register group */
17673
17674
17675 /*---------------------- Window Watchdog Timer -------------------------*/
17681 typedef struct
17682 {
17683
17684
17818 __O uint32_t RLDCNT;
17819 __IO uint32_t CTL;
17820 __IO uint32_t INTEN;
17821 __IO uint32_t STATUS;
17822 __I uint32_t CNT;
17824 } WWDT_T;
17825
17831 #define WWDT_RLDCNT_RLDCNT_Pos (0)
17832 #define WWDT_RLDCNT_RLDCNT_Msk (0xfffffffful << WWDT_RLDCNT_RLDCNT_Pos)
17834 #define WWDT_CTL_WWDTEN_Pos (0)
17835 #define WWDT_CTL_WWDTEN_Msk (0x1ul << WWDT_CTL_WWDTEN_Pos)
17837 #define WWDT_CTL_PERIODSEL_Pos (8)
17838 #define WWDT_CTL_PERIODSEL_Msk (0xful << WWDT_CTL_PERIODSEL_Pos)
17840 #define WWDT_CTL_WINCMP_Pos (16)
17841 #define WWDT_CTL_WINCMP_Msk (0x3ful << WWDT_CTL_WINCMP_Pos)
17843 #define WWDT_CTL_DBGEN_Pos (31)
17844 #define WWDT_CTL_DBGEN_Msk (0x1ul << WWDT_CTL_DBGEN_Pos)
17846 #define WWDT_INTEN_WWDTIE_Pos (0)
17847 #define WWDT_INTEN_WWDTIE_Msk (0x1ul << WWDT_INTEN_WWDTIE_Pos)
17849 #define WWDT_STATUS_WWDTIF_Pos (0)
17850 #define WWDT_STATUS_WWDTIF_Msk (0x1ul << WWDT_STATUS_WWDTIF_Pos)
17852 #define WWDT_STATUS_WWDTRF_Pos (1)
17853 #define WWDT_STATUS_WWDTRF_Msk (0x1ul << WWDT_STATUS_WWDTRF_Pos)
17855 #define WWDT_CNT_WWDT_CNTDAT_Pos (0)
17856 #define WWDT_CNT_WWDT_CNTDAT_Msk (0x3ful << WWDT_CNT_WWDT_CNTDAT_Pos) /* WWDT_CONST */
17859 /* end of WWDT register group */
17860
17861
17862 /*---------------------- Real Time Clock Controller -------------------------*/
17868 typedef struct
17869 {
17870
17871
18619 __IO uint32_t INIT;
18620 __IO uint32_t RWEN;
18621 __IO uint32_t FREQADJ;
18622 __IO uint32_t TIME;
18623 __IO uint32_t CAL;
18624 __IO uint32_t CLKFMT;
18625 __IO uint32_t WEEKDAY;
18626 __IO uint32_t TALM;
18627 __IO uint32_t CALM;
18628 __I uint32_t LEAPYEAR;
18629 __IO uint32_t INTEN;
18630 __IO uint32_t INTSTS;
18631 __IO uint32_t TICK;
18632 __IO uint32_t TAMSK;
18633 __IO uint32_t CAMSK;
18634 __IO uint32_t SPRCTL;
18635 __IO uint32_t SPR[5];
18636 __I uint32_t RESERVE0[43];
18639 __IO uint32_t LXTCTL;
18640 __IO uint32_t LXTOCTL;
18641 __IO uint32_t LXTICTL;
18642 __IO uint32_t TAMPCTL;
18643 __I uint32_t RESERVE1[56];
18646 __IO uint32_t MISCCTL;
18647 } RTC_T;
18648
18654 #define RTC_INIT_INIT_ACTIVE_Pos (0)
18655 #define RTC_INIT_INIT_ACTIVE_Msk (0x1ul << RTC_INIT_INIT_ACTIVE_Pos)
18657 #define RTC_INIT_INIT_Pos (1)
18658 #define RTC_INIT_INIT_Msk (0x7ffffffful << RTC_INIT_INIT_Pos)
18660 #define RTC_RWEN_RWEN_Pos (0)
18661 #define RTC_RWEN_RWEN_Msk (0xfffful << RTC_RWEN_RWEN_Pos)
18663 #define RTC_RWEN_RWENF_Pos (16)
18664 #define RTC_RWEN_RWENF_Msk (0x1ul << RTC_RWEN_RWENF_Pos)
18666 #define RTC_RWEN_RTCBUSY_Pos (24)
18667 #define RTC_RWEN_RTCBUSY_Msk (0x1ul << RTC_RWEN_RTCBUSY_Pos)
18669 #define RTC_FREQADJ_FREQADJ_Pos (0)
18670 #define RTC_FREQADJ_FREQADJ_Msk (0x3ffffful << RTC_FCR_FCR_Pos)
18672 #define RTC_TIME_SEC_Pos (0)
18673 #define RTC_TIME_SEC_Msk (0xful << RTC_TIME_SEC_Pos)
18675 #define RTC_TIME_TENSEC_Pos (4)
18676 #define RTC_TIME_TENSEC_Msk (0x7ul << RTC_TIME_TENSEC_Pos)
18678 #define RTC_TIME_MIN_Pos (8)
18679 #define RTC_TIME_MIN_Msk (0xful << RTC_TIME_MIN_Pos)
18681 #define RTC_TIME_TENMIN_Pos (12)
18682 #define RTC_TIME_TENMIN_Msk (0x7ul << RTC_TIME_TENMIN_Pos)
18684 #define RTC_TIME_HR_Pos (16)
18685 #define RTC_TIME_HR_Msk (0xful << RTC_TIME_HR_Pos)
18687 #define RTC_TIME_TENHR_Pos (20)
18688 #define RTC_TIME_TENHR_Msk (0x3ul << RTC_TIME_TENHR_Pos)
18690 #define RTC_CAL_DAY_Pos (0)
18691 #define RTC_CAL_DAY_Msk (0xful << RTC_CAL_DAY_Pos)
18693 #define RTC_CAL_TENDAY_Pos (4)
18694 #define RTC_CAL_TENDAY_Msk (0x3ul << RTC_CAL_TENDAY_Pos)
18696 #define RTC_CAL_MON_Pos (8)
18697 #define RTC_CAL_MON_Msk (0xful << RTC_CAL_MON_Pos)
18699 #define RTC_CAL_TENMON_Pos (12)
18700 #define RTC_CAL_TENMON_Msk (0x1ul << RTC_CAL_TENMON_Pos)
18702 #define RTC_CAL_YEAR_Pos (16)
18703 #define RTC_CAL_YEAR_Msk (0xful << RTC_CAL_YEAR_Pos)
18705 #define RTC_CAL_TENYEAR_Pos (20)
18706 #define RTC_CAL_TENYEAR_Msk (0xful << RTC_CAL_TENYEAR_Pos)
18708 #define RTC_CLKFMT_24HEN_Pos (0)
18709 #define RTC_CLKFMT_24HEN_Msk (0x1ul << RTC_CLKFMT_24HEN_Pos)
18711 #define RTC_WEEKDAY_WEEKDAY_Pos (0)
18712 #define RTC_WEEKDAY_WEEKDAY_Msk (0x7ul << RTC_WEEKDAY_WEEKDAY_Pos)
18714 #define RTC_TALM_SEC_Pos (0)
18715 #define RTC_TALM_SEC_Msk (0xful << RTC_TALM_SEC_Pos)
18717 #define RTC_TALM_TENSEC_Pos (4)
18718 #define RTC_TALM_TENSEC_Msk (0x7ul << RTC_TALM_TENSEC_Pos)
18720 #define RTC_TALM_MIN_Pos (8)
18721 #define RTC_TALM_MIN_Msk (0xful << RTC_TALM_MIN_Pos)
18723 #define RTC_TALM_TENMIN_Pos (12)
18724 #define RTC_TALM_TENMIN_Msk (0x7ul << RTC_TALM_TENMIN_Pos)
18726 #define RTC_TALM_HR_Pos (16)
18727 #define RTC_TALM_HR_Msk (0xful << RTC_TALM_HR_Pos)
18729 #define RTC_TALM_TENHR_Pos (20)
18730 #define RTC_TALM_TENHR_Msk (0x3ul << RTC_TALM_TENHR_Pos)
18732 #define RTC_CALM_DAY_Pos (0)
18733 #define RTC_CALM_DAY_Msk (0xful << RTC_CALM_DAY_Pos)
18735 #define RTC_CALM_TENDAY_Pos (4)
18736 #define RTC_CALM_TENDAY_Msk (0x3ul << RTC_CALM_TENDAY_Pos)
18738 #define RTC_CALM_MON_Pos (8)
18739 #define RTC_CALM_MON_Msk (0xful << RTC_CALM_MON_Pos)
18741 #define RTC_CALM_TENMON_Pos (12)
18742 #define RTC_CALM_TENMON_Msk (0x1ul << RTC_CALM_TENMON_Pos)
18744 #define RTC_CALM_YEAR_Pos (16)
18745 #define RTC_CALM_YEAR_Msk (0xful << RTC_CALM_YEAR_Pos)
18747 #define RTC_CALM_TENYEAR_Pos (20)
18748 #define RTC_CALM_TENYEAR_Msk (0xful << RTC_CALM_TENYEAR_Pos)
18750 #define RTC_LEAPYEAR_LEAPYEAR_Pos (0)
18751 #define RTC_LEAPYEAR_LEAPYEAR_Msk (0x1ul << RTC_LEAPYEAR_LEAPYEAR_Pos)
18753 #define RTC_INTEN_ALMIEN_Pos (0)
18754 #define RTC_INTEN_ALMIEN_Msk (0x1ul << RTC_INTEN_ALMIEN_Pos)
18756 #define RTC_INTEN_TICKIEN_Pos (1)
18757 #define RTC_INTEN_TICKIEN_Msk (0x1ul << RTC_INTEN_TICKIEN_Pos)
18759 #define RTC_INTEN_SNPDIEN_Pos (2)
18760 #define RTC_INTEN_SNPDIEN_Msk (0x1ul << RTC_INTEN_SNPDIEN_Pos)
18762 #define RTC_INTSTS_ALMIF_Pos (0)
18763 #define RTC_INTSTS_ALMIF_Msk (0x1ul << RTC_INTSTS_ALMIF_Pos)
18765 #define RTC_INTSTS_TICKIF_Pos (1)
18766 #define RTC_INTSTS_TICKIF_Msk (0x1ul << RTC_INTSTS_TICKIF_Pos)
18768 #define RTC_INTSTS_SNPDIF_Pos (2)
18769 #define RTC_INTSTS_SNPDIF_Msk (0x1ul << RTC_INTSTS_SNPDIF_Pos)
18771 #define RTC_TICK_TICK_Pos (0)
18772 #define RTC_TICK_TICK_Msk (0x7ul << RTC_TICK_TICK_Pos)
18774 #define RTC_TAMSK_MSEC_Pos (0)
18775 #define RTC_TAMSK_MSEC_Msk (0x1ul << RTC_TAMSK_MSEC_Pos)
18777 #define RTC_TAMSK_MTENSEC_Pos (1)
18778 #define RTC_TAMSK_MTENSEC_Msk (0x1ul << RTC_TAMSK_MTENSEC_Pos)
18780 #define RTC_TAMSK_MMIN_Pos (2)
18781 #define RTC_TAMSK_MMIN_Msk (0x1ul << RTC_TAMSK_MMIN_Pos)
18783 #define RTC_TAMSK_MTENMIN_Pos (3)
18784 #define RTC_TAMSK_MTENMIN_Msk (0x1ul << RTC_TAMSK_MTENMIN_Pos)
18786 #define RTC_TAMSK_MHR_Pos (4)
18787 #define RTC_TAMSK_MHR_Msk (0x1ul << RTC_TAMSK_MHR_Pos)
18789 #define RTC_TAMSK_MTENHR_Pos (5)
18790 #define RTC_TAMSK_MTENHR_Msk (0x1ul << RTC_TAMSK_MTENHR_Pos)
18792 #define RTC_CAMSK_MDAY_Pos (0)
18793 #define RTC_CAMSK_MDAY_Msk (0x1ul << RTC_CAMSK_MDAY_Pos)
18795 #define RTC_CAMSK_MTENDAY_Pos (1)
18796 #define RTC_CAMSK_MTENDAY_Msk (0x1ul << RTC_CAMSK_MTENDAY_Pos)
18798 #define RTC_CAMSK_MMON_Pos (2)
18799 #define RTC_CAMSK_MMON_Msk (0x1ul << RTC_CAMSK_MMON_Pos)
18801 #define RTC_CAMSK_MTENMON_Pos (3)
18802 #define RTC_CAMSK_MTENMON_Msk (0x1ul << RTC_CAMSK_MTENMON_Pos)
18804 #define RTC_CAMSK_MYEAR_Pos (4)
18805 #define RTC_CAMSK_MYEAR_Msk (0x1ul << RTC_CAMSK_MYEAR_Pos)
18807 #define RTC_CAMSK_MTENYEAR_Pos (5)
18808 #define RTC_CAMSK_MTENYEAR_Msk (0x1ul << RTC_CAMSK_MTENYEAR_Pos)
18810 #define RTC_SPRCTL_SNPDEN_Pos (0)
18811 #define RTC_SPRCTL_SNPDEN_Msk (0x1ul << RTC_SPRCTL_SNPDEN_Pos)
18813 #define RTC_SPRCTL_SNPTYPE0_Pos (1)
18814 #define RTC_SPRCTL_SNPTYPE0_Msk (0x1ul << RTC_SPRCTL_SNPTYPE0_Pos)
18816 #define RTC_SPRCTL_SPRRWEN_Pos (2)
18817 #define RTC_SPRCTL_SPRRWEN_Msk (0x1ul << RTC_SPRCTL_SPRRWEN_Pos)
18819 #define RTC_SPRCTL_SPRCSTS_Pos (5)
18820 #define RTC_SPRCTL_SPRCSTS_Msk (0x1ul << RTC_SPRCTL_SPRCSTS_Pos)
18822 #define RTC_SPR0_SPARE_Pos (0)
18823 #define RTC_SPR0_SPARE_Msk (0xfffffffful << RTC_SPR0_SPARE_Pos)
18825 #define RTC_SPR1_SPARE_Pos (0)
18826 #define RTC_SPR1_SPARE_Msk (0xfffffffful << RTC_SPR1_SPARE_Pos)
18828 #define RTC_SPR2_SPARE_Pos (0)
18829 #define RTC_SPR2_SPARE_Msk (0xfffffffful << RTC_SPR2_SPARE_Pos)
18831 #define RTC_SPR3_SPARE_Pos (0)
18832 #define RTC_SPR3_SPARE_Msk (0xfffffffful << RTC_SPR3_SPARE_Pos)
18834 #define RTC_SPR4_SPARE_Pos (0)
18835 #define RTC_SPR4_SPARE_Msk (0xfffffffful << RTC_SPR4_SPARE_Pos)
18837 #define RTC_LXTCTL_LXT_TYPE_Pos (0)
18838 #define RTC_LXTCTL_LXT_TYPE_Msk (0x1ul << RTC_LXTCTL_LXT_TYPE_Pos)
18840 #define RTC_LXTOCTL_OPMODE_Pos (0)
18841 #define RTC_LXTOCTL_OPMODE_Msk (0x3ul << RTC_LXTOCTL_OPMODE_Pos)
18843 #define RTC_LXTOCTL_DOUT_Pos (2)
18844 #define RTC_LXTOCTL_DOUT_Msk (0x1ul << RTC_LXTOCTL_DOUT_Pos)
18846 #define RTC_LXTOCTL_CTLSEL_Pos (3)
18847 #define RTC_LXTOCTL_CTLSEL_Msk (0x1ul << RTC_LXTOCTL_CTLSEL_Pos)
18849 #define RTC_LXTICTL_OPMODE_Pos (0)
18850 #define RTC_LXTICTL_OPMODE_Msk (0x3ul << RTC_LXTICTL_OPMODE_Pos)
18852 #define RTC_LXTICTL_DOUT_Pos (2)
18853 #define RTC_LXTICTL_DOUT_Msk (0x1ul << RTC_LXTICTL_DOUT_Pos)
18855 #define RTC_LXTICTL_CTLSEL_Pos (3)
18856 #define RTC_LXTICTL_CTLSEL_Msk (0x1ul << RTC_LXTICTL_CTLSEL_Pos)
18858 #define RTC_TAMPCTL_OPMODE_Pos (0)
18859 #define RTC_TAMPCTL_OPMODE_Msk (0x3ul << RTC_TAMPCTL_OPMODE_Pos)
18861 #define RTC_TAMPCTL_DOUT_Pos (2)
18862 #define RTC_TAMPCTL_DOUT_Msk (0x1ul << RTC_TAMPCTL_DOUT_Pos)
18864 #define RTC_TAMPCTL_CTLSEL_Pos (3)
18865 #define RTC_TAMPCTL_CTLSEL_Msk (0x1ul << RTC_TAMPCTL_CTLSEL_Pos)
18867 #define RTC_MISCCTL_GAINSEL_Pos (12)
18868 #define RTC_MISCCTL_GAINSEL_Msk (0x3ul << RTC_MISCCTL_GAINSEL_Pos) /* RTC_CONST */
18871 /* end of RTC register group */
18872
18873
18874 /*---------------------- Universal Asynchronous Receiver/Transmitter Controller -------------------------*/
18880 typedef struct
18881 {
18882
18883
20103 __IO uint32_t DAT;
20104 __IO uint32_t CTRL;
20105 __IO uint32_t LINE;
20106 __IO uint32_t INTEN;
20107 __IO uint32_t INTSTS;
20108 __IO uint32_t TRSR;
20109 __IO uint32_t FIFOSTS;
20110 __IO uint32_t MODEM;
20111 __IO uint32_t TOUT;
20112 __IO uint32_t BAUD;
20113 __I uint32_t RESERVE0[2];
20116 __IO uint32_t IRDA;
20117 __IO uint32_t ALTCTL;
20118 __IO uint32_t FUNCSEL;
20119 __IO uint32_t BRCOMPAT;
20120 __IO uint32_t WKUPEN;
20121 __IO uint32_t WKUPSTS;
20123 } UART_T;
20124
20130 #define UART_DAT_DAT_Pos (0)
20131 #define UART_DAT_DAT_Msk (0xfful << UART_RBR_RBR_Pos)
20133 #define UART_CTRL_RXRST_Pos (0)
20134 #define UART_CTRL_RXRST_Msk (0x1ul << UART_CTRL_RXRST_Pos)
20136 #define UART_CTRL_TXRST_Pos (1)
20137 #define UART_CTRL_TXRST_Msk (0x1ul << UART_CTRL_TXRST_Pos)
20139 #define UART_CTRL_RXOFF_Pos (2)
20140 #define UART_CTRL_RXOFF_Msk (0x1ul << UART_CTRL_RXOFF_Pos)
20142 #define UART_CTRL_TXOFF_Pos (3)
20143 #define UART_CTRL_TXOFF_Msk (0x1ul << UART_CTRL_TXOFF_Pos)
20145 #define UART_CTRL_ATORTSEN_Pos (4)
20146 #define UART_CTRL_ATORTSEN_Msk (0x1ul << UART_CTRL_ATORTSEN_Pos)
20148 #define UART_CTRL_ATOCTSEN_Pos (5)
20149 #define UART_CTRL_ATOCTSEN_Msk (0x1ul << UART_CTRL_ATOCTSEN_Pos)
20151 #define UART_CTRL_RXDMAEN_Pos (6)
20152 #define UART_CTRL_RXDMAEN_Msk (0x1ul << UART_CTRL_RXDMAEN_Pos)
20154 #define UART_CTRL_TXDMAEN_Pos (7)
20155 #define UART_CTRL_TXDMAEN_Msk (0x1ul << UART_CTRL_TXDMAEN_Pos)
20157 #define UART_CTRL_FTOEN_Pos (8)
20158 #define UART_CTRL_FTOEN_Msk (0x1ul << UART_CTRL_FTOEN_Pos)
20160 #define UART_CTRL_ABRDEN_Pos (12)
20161 #define UART_CTRL_ABRDEN_Msk (0x1ul << UART_CTRL_ABRDEN_Pos)
20163 #define UART_CTRL_ABRDBITS_Pos (13)
20164 #define UART_CTRL_ABRDBITS_Msk (0x3ul << UART_CTRL_ABRDBITS_Pos)
20166 #define UART_LINE_WLS_Pos (0)
20167 #define UART_LINE_WLS_Msk (0x3ul << UART_LINE_WLS_Pos)
20169 #define UART_LINE_NSB_Pos (2)
20170 #define UART_LINE_NSB_Msk (0x1ul << UART_LINE_NSB_Pos)
20172 #define UART_LINE_PBE_Pos (3)
20173 #define UART_LINE_PBE_Msk (0x1ul << UART_LINE_PBE_Pos)
20175 #define UART_LINE_EPE_Pos (4)
20176 #define UART_LINE_EPE_Msk (0x1ul << UART_LINE_EPE_Pos)
20178 #define UART_LINE_SPE_Pos (5)
20179 #define UART_LINE_SPE_Msk (0x1ul << UART_LINE_SPE_Pos)
20181 #define UART_LINE_BCB_Pos (6)
20182 #define UART_LINE_BCB_Msk (0x1ul << UART_LINE_BCB_Pos)
20184 #define UART_LINE_RFITL_Pos (8)
20185 #define UART_LINE_RFITL_Msk (0x3ul << UART_LINE_RFITL_Pos)
20187 #define UART_LINE_RTSTRGLV_Pos (12)
20188 #define UART_LINE_RTSTRGLV_Msk (0x3ul << UART_LINE_RTSTRGLV_Pos)
20190 #define UART_INTEN_RDAIEN_Pos (0)
20191 #define UART_INTEN_RDAIEN_Msk (0x1ul << UART_INTEN_RDAIEN_Pos)
20193 #define UART_INTEN_THREIEN_Pos (1)
20194 #define UART_INTEN_THREIEN_Msk (0x1ul << UART_INTEN_THREIEN_Pos)
20196 #define UART_INTEN_RLSIEN_Pos (2)
20197 #define UART_INTEN_RLSIEN_Msk (0x1ul << UART_INTEN_RLSIEN_Pos)
20199 #define UART_INTEN_MODEMIEN_Pos (3)
20200 #define UART_INTEN_MODEMIEN_Msk (0x1ul << UART_INTEN_MODEMIEN_Pos)
20202 #define UART_INTEN_RXTOIEN_Pos (4)
20203 #define UART_INTEN_RXTOIEN_Msk (0x1ul << UART_INTEN_RXTOIEN_Pos)
20205 #define UART_INTEN_BUFERRIEN_Pos (5)
20206 #define UART_INTEN_BUFERRIEN_Msk (0x1ul << UART_INTEN_BUFERRIEN_Pos)
20208 #define UART_INTEN_WKUPIEN_Pos (6)
20209 #define UART_INTEN_WKUPIEN_Msk (0x1ul << UART_INTEN_WKUPIEN_Pos)
20211 #define UART_INTEN_ABRIEN_Pos (7)
20212 #define UART_INTEN_ABRIEN_Msk (0x1ul << UART_INTEN_ABRIEN_Pos)
20214 #define UART_INTEN_LINIEN_Pos (8)
20215 #define UART_INTEN_LINIEN_Msk (0x1ul << UART_INTEN_LINIEN_Pos)
20217 #define UART_INTEN_TXENDIEN_Pos (9)
20218 #define UART_INTEN_TXENDIEN_Msk (0x1ul << UART_INTEN_TXENDIEN_Pos)
20220 #define UART_INTSTS_RDAIF_Pos (0)
20221 #define UART_INTSTS_RDAIF_Msk (0x1ul << UART_INTSTS_RDAIF_Pos)
20223 #define UART_INTSTS_THREIF_Pos (1)
20224 #define UART_INTSTS_THREIF_Msk (0x1ul << UART_INTSTS_THREIF_Pos)
20226 #define UART_INTSTS_RLSIF_Pos (2)
20227 #define UART_INTSTS_RLSIF_Msk (0x1ul << UART_INTSTS_RLSIF_Pos)
20229 #define UART_INTSTS_MODEMIF_Pos (3)
20230 #define UART_INTSTS_MODEMIF_Msk (0x1ul << UART_INTSTS_MODEMIF_Pos)
20232 #define UART_INTSTS_RXTOIF_Pos (4)
20233 #define UART_INTSTS_RXTOIF_Msk (0x1ul << UART_INTSTS_RXTOIF_Pos)
20235 #define UART_INTSTS_BUFERRIF_Pos (5)
20236 #define UART_INTSTS_BUFERRIF_Msk (0x1ul << UART_INTSTS_BUFERRIF_Pos)
20238 #define UART_INTSTS_WKUPIF_Pos (6)
20239 #define UART_INTSTS_WKUPIF_Msk (0x1ul << UART_INTSTS_WKUPIF_Pos)
20241 #define UART_INTSTS_ABRIF_Pos (7)
20242 #define UART_INTSTS_ABRIF_Msk (0x1ul << UART_INTSTS_ABRIF_Pos)
20244 #define UART_INTSTS_LINIF_Pos (8)
20245 #define UART_INTSTS_LINIF_Msk (0x1ul << UART_INTSTS_LINIF_Pos)
20247 #define UART_TRSR_ADDRDETF_Pos (0)
20248 #define UART_TRSR_ADDRDETF_Msk (0x1ul << UART_TRSR_ADDRDETF_Pos)
20250 #define UART_TRSR_ABRDIF_Pos (1)
20251 #define UART_TRSR_ABRDIF_Msk (0x1ul << UART_TRSR_ABRDIF_Pos)
20253 #define UART_TRSR_ABRDTOIF_Pos (2)
20254 #define UART_TRSR_ABRDTOIF_Msk (0x1ul << UART_TRSR_ABRDTOIF_Pos)
20256 #define UART_TRSR_LINTXIF_Pos (3)
20257 #define UART_TRSR_LINTXIF_Msk (0x1ul << UART_TRSR_LINTXIF_Pos)
20259 #define UART_TRSR_LINRXIF_Pos (4)
20260 #define UART_TRSR_LINRXIF_Msk (0x1ul << UART_TRSR_LINRXIF_Pos)
20262 #define UART_TRSR_BITEF_Pos (5)
20263 #define UART_TRSR_BITEF_Msk (0x1ul << UART_TRSR_BITEF_Pos)
20265 #define UART_TRSR_RXBUSY_Pos (7)
20266 #define UART_TRSR_RXBUSY_Msk (0x1ul << UART_TRSR_RXBUSY_Pos)
20268 #define UART_TRSR_SLVSYNCF_Pos (8)
20269 #define UART_TRSR_SLVSYNCF_Msk (0x1ul << UART_TRSR_SLVSYNCF_Pos)
20271 #define UART_FIFOSTS_RXOVIF_Pos (0)
20272 #define UART_FIFOSTS_RXOVIF_Msk (0x1ul << UART_FIFOSTS_RXOVIF_Pos)
20274 #define UART_FIFOSTS_RXEMPTY_Pos (1)
20275 #define UART_FIFOSTS_RXEMPTY_Msk (0x1ul << UART_FIFOSTS_RXEMPTY_Pos)
20277 #define UART_FIFOSTS_RXFULL_Pos (2)
20278 #define UART_FIFOSTS_RXFULL_Msk (0x1ul << UART_FIFOSTS_RXFULL_Pos)
20280 #define UART_FIFOSTS_PEF_Pos (4)
20281 #define UART_FIFOSTS_PEF_Msk (0x1ul << UART_FIFOSTS_PEF_Pos)
20283 #define UART_FIFOSTS_FEF_Pos (5)
20284 #define UART_FIFOSTS_FEF_Msk (0x1ul << UART_FIFOSTS_FEF_Pos)
20286 #define UART_FIFOSTS_BIF_Pos (6)
20287 #define UART_FIFOSTS_BIF_Msk (0x1ul << UART_FIFOSTS_BIF_Pos)
20289 #define UART_FIFOSTS_TXOVIF_Pos (8)
20290 #define UART_FIFOSTS_TXOVIF_Msk (0x1ul << UART_FIFOSTS_TXOVIF_Pos)
20292 #define UART_FIFOSTS_TXEMPTY_Pos (9)
20293 #define UART_FIFOSTS_TXEMPTY_Msk (0x1ul << UART_FIFOSTS_TXEMPTY_Pos)
20295 #define UART_FIFOSTS_TXFULL_Pos (10)
20296 #define UART_FIFOSTS_TXFULL_Msk (0x1ul << UART_FIFOSTS_TXFULL_Pos)
20298 #define UART_FIFOSTS_TXENDF_Pos (11)
20299 #define UART_FIFOSTS_TXENDF_Msk (0x1ul << UART_FIFOSTS_TXENDF_Pos)
20301 #define UART_FIFOSTS_RXPTR_Pos (16)
20302 #define UART_FIFOSTS_RXPTR_Msk (0x1ful << UART_FIFOSTS_RXPTR_Pos)
20304 #define UART_FIFOSTS_TXPTR_Pos (24)
20305 #define UART_FIFOSTS_TXPTR_Msk (0x1ful << UART_FIFOSTS_TXPTR_Pos)
20307 #define UART_MODEM_RTSACTLV_Pos (0)
20308 #define UART_MODEM_RTSACTLV_Msk (0x1ul << UART_MODEM_RTSACTLV_Pos)
20310 #define UART_MODEM_RTSSTS_Pos (1)
20311 #define UART_MODEM_RTSSTS_Msk (0x1ul << UART_MODEM_RTSSTS_Pos)
20313 #define UART_MODEM_CTSACTLV_Pos (16)
20314 #define UART_MODEM_CTSACTLV_Msk (0x1ul << UART_MODEM_CTSACTLV_Pos)
20316 #define UART_MODEM_CTSSTS_Pos (17)
20317 #define UART_MODEM_CTSSTS_Msk (0x1ul << UART_MODEM_CTSSTS_Pos)
20319 #define UART_MODEM_CTSDETF_Pos (18)
20320 #define UART_MODEM_CTSDETF_Msk (0x1ul << UART_MODEM_CTSDETF_Pos)
20322 #define UART_TOUT_TOIC_Pos (0)
20323 #define UART_TOUT_TOIC_Msk (0x1fful << UART_TOUT_TOIC_Pos)
20325 #define UART_TOUT_DLY_Pos (16)
20326 #define UART_TOUT_DLY_Msk (0xfful << UART_TOUT_DLY_Pos)
20328 #define UART_BAUD_BRD_Pos (0)
20329 #define UART_BAUD_BRD_Msk (0xfffful << UART_BAUD_BRD_Pos)
20331 #define UART_BAUD_DIV16EN_Pos (31)
20332 #define UART_BAUD_DIV16EN_Msk (0x1ul << UART_BAUD_DIV16EN_Pos)
20334 #define UART_IRDA_TXEN_Pos (1)
20335 #define UART_IRDA_TXEN_Msk (0x1ul << UART_IRDA_TXEN_Pos)
20337 #define UART_IRDA_TXINV_Pos (5)
20338 #define UART_IRDA_TXINV_Msk (0x1ul << UART_IRDA_TXINV_Pos)
20340 #define UART_IRDA_RXINV_Pos (6)
20341 #define UART_IRDA_RXINV_Msk (0x1ul << UART_IRDA_RXINV_Pos)
20343 #define UART_ALTCTL_BRKFL_Pos (0)
20344 #define UART_ALTCTL_BRKFL_Msk (0x7ul << UART_ALTCTL_BRKFL_Pos)
20346 #define UART_ALTCTL_LINHSEL_Pos (4)
20347 #define UART_ALTCTL_LINHSEL_Msk (0x3ul << UART_ALTCTL_LINHSEL_Pos)
20349 #define UART_ALTCTL_LINRXEN_Pos (6)
20350 #define UART_ALTCTL_LINRXEN_Msk (0x1ul << UART_ALTCTL_LINRXEN_Pos)
20352 #define UART_ALTCTL_LINTXEN_Pos (7)
20353 #define UART_ALTCTL_LINTXEN_Msk (0x1ul << UART_ALTCTL_LINTXEN_Pos)
20355 #define UART_ALTCTL_BITERREN_Pos (8)
20356 #define UART_ALTCTL_BITERREN_Msk (0x1ul << UART_ALTCTL_BITERREN_Pos)
20358 #define UART_ALTCTL_RS485NMM_Pos (16)
20359 #define UART_ALTCTL_RS485NMM_Msk (0x1ul << UART_ALTCTL_RS485NMM_Pos)
20361 #define UART_ALTCTL_RS485AAD_Pos (17)
20362 #define UART_ALTCTL_RS485AAD_Msk (0x1ul << UART_ALTCTL_RS485AAD_Pos)
20364 #define UART_ALTCTL_RS485AUD_Pos (18)
20365 #define UART_ALTCTL_RS485AUD_Msk (0x1ul << UART_ALTCTL_RS485AUD_Pos)
20367 #define UART_ALTCTL_ADDRDEN_Pos (19)
20368 #define UART_ALTCTL_ADDRDEN_Msk (0x1ul << UART_ALTCTL_ADDRDEN_Pos)
20370 #define UART_ALTCTL_ADRMPID_Pos (24)
20371 #define UART_ALTCTL_ADRMPID_Msk (0xfful << UART_ALTCTL_ADRMPID_Pos)
20373 #define UART_FUNCSEL_FUNCSEL_Pos (0)
20374 #define UART_FUNCSEL_FUNCSEL_Msk (0x3ul << UART_FUNCSEL_FUNCSEL_Pos)
20376 #define UART_BRCOMPAT_BRCOMPAT_Pos (0)
20377 #define UART_BRCOMPAT_BRCOMPAT_Msk (0x1fful << UART_BRCOMPAT_BRCOMPAT_Pos)
20379 #define UART_BRCOMPAT_BRCOMPDEC_Pos (31)
20380 #define UART_BRCOMPAT_BRCOMPDEC_Msk (0x1ul << UART_BRCOMPAT_BRCOMPDEC_Pos)
20382 #define UART_WKUPEN_WKCTSEN_Pos (0)
20383 #define UART_WKUPEN_WKCTSEN_Msk (0x1ul << UART_WKUPEN_WKCTSEN_Pos)
20385 #define UART_WKUPEN_WKDATEN_Pos (1)
20386 #define UART_WKUPEN_WKDATEN_Msk (0x1ul << UART_WKUPEN_WKDATEN_Pos)
20388 #define UART_WKUPEN_WKTHREN_Pos (2)
20389 #define UART_WKUPEN_WKTHREN_Msk (0x1ul << UART_WKUPEN_WKTHREN_Pos)
20391 #define UART_WKUPEN_WKTHRTOEN_Pos (3)
20392 #define UART_WKUPEN_WKTHRTOEN_Msk (0x1ul << UART_WKUPEN_WKTHRTOEN_Pos)
20394 #define UART_WKUPEN_WKADRMEN_Pos (4)
20395 #define UART_WKUPEN_WKADRMEN_Msk (0x1ul << UART_WKUPEN_WKADRMEN_Pos)
20397 #define UART_WKUPSTS_CTSWKSTS_Pos (0)
20398 #define UART_WKUPSTS_CTSWKSTS_Msk (0x1ul << UART_WKUPSTS_CTSWKSTS_Pos)
20400 #define UART_WKUPSTS_DATWKSTS_Pos (1)
20401 #define UART_WKUPSTS_DATWKSTS_Msk (0x1ul << UART_WKUPSTS_DATWKSTS_Pos)
20403 #define UART_WKUPSTS_THRWKSTS_Pos (2)
20404 #define UART_WKUPSTS_THRWKSTS_Msk (0x1ul << UART_WKUPSTS_THRWKSTS_Pos)
20406 #define UART_WKUPSTS_THRTOWKSTS_Pos (3)
20407 #define UART_WKUPSTS_THRTOWKSTS_Msk (0x1ul << UART_WKUPSTS_THRTOWKSTS_Pos)
20409 #define UART_WKUPSTS_ADRWKSTS_Pos (4)
20410 #define UART_WKUPSTS_ADRWKSTS_Msk (0x1ul << UART_WKUPSTS_ADRWKSTS_Pos) /* UART_CONST */
20413 /* end of UART register group */
20414
20415
20416 /*---------------------- Smart Card Host Interface Controller -------------------------*/
20422 typedef struct
20423 {
20424
20425
21636 __IO uint32_t DAT;
21637 __IO uint32_t CTL;
21638 __IO uint32_t ALTCTL;
21639 __IO uint32_t EGT;
21640 __IO uint32_t RXTOUT;
21641 __IO uint32_t ETUCTL;
21642 __IO uint32_t INTEN;
21643 __IO uint32_t INTSTS;
21644 __IO uint32_t STATUS;
21645 __IO uint32_t PINCTL;
21646 __IO uint32_t TMRCTL0;
21647 __IO uint32_t TMRCTL1;
21648 __IO uint32_t TMRCTL2;
21649 __IO uint32_t UARTCTL;
21650 __I uint32_t RESERVE0[2];
21653 __IO uint32_t ACTCTL;
21655 } SC_T;
21656
21662 #define SC_DAT_DAT_Pos (0)
21663 #define SC_DAT_DAT_Msk (0xfful << SC_DAT_DAT_Pos)
21665 #define SC_CTL_SCEN_Pos (0)
21666 #define SC_CTL_SCEN_Msk (0x1ul << SC_CTL_SCEN_Pos)
21668 #define SC_CTL_RXOFF_Pos (1)
21669 #define SC_CTL_RXOFF_Msk (0x1ul << SC_CTL_RXOFF_Pos)
21671 #define SC_CTL_TXOFF_Pos (2)
21672 #define SC_CTL_TXOFF_Msk (0x1ul << SC_CTL_TXOFF_Pos)
21674 #define SC_CTL_AUTOCEN_Pos (3)
21675 #define SC_CTL_AUTOCEN_Msk (0x1ul << SC_CTL_AUTOCEN_Pos)
21677 #define SC_CTL_CONSEL_Pos (4)
21678 #define SC_CTL_CONSEL_Msk (0x3ul << SC_CTL_CONSEL_Pos)
21680 #define SC_CTL_RXTRGLV_Pos (6)
21681 #define SC_CTL_RXTRGLV_Msk (0x3ul << SC_CTL_RXTRGLV_Pos)
21683 #define SC_CTL_BGT_Pos (8)
21684 #define SC_CTL_BGT_Msk (0x1ful << SC_CTL_BGT_Pos)
21686 #define SC_CTL_TMRSEL_Pos (13)
21687 #define SC_CTL_TMRSEL_Msk (0x3ul << SC_CTL_TMRSEL_Pos)
21689 #define SC_CTL_NSB_Pos (15)
21690 #define SC_CTL_NSB_Msk (0x1ul << SC_CTL_NSB_Pos)
21692 #define SC_CTL_RXRTY_Pos (16)
21693 #define SC_CTL_RXRTY_Msk (0x7ul << SC_CTL_RXRTY_Pos)
21695 #define SC_CTL_RXRTYEN_Pos (19)
21696 #define SC_CTL_RXRTYEN_Msk (0x1ul << SC_CTL_RXRTYEN_Pos)
21698 #define SC_CTL_TXRTY_Pos (20)
21699 #define SC_CTL_TXRTY_Msk (0x7ul << SC_CTL_TXRTY_Pos)
21701 #define SC_CTL_TXRTYEN_Pos (23)
21702 #define SC_CTL_TXRTYEN_Msk (0x1ul << SC_CTL_TXRTYEN_Pos)
21704 #define SC_CTL_CDDBSEL_Pos (24)
21705 #define SC_CTL_CDDBSEL_Msk (0x3ul << SC_CTL_CDDBSEL_Pos)
21707 #define SC_CTL_SYNC_Pos (30)
21708 #define SC_CTL_SYNC_Msk (0x1ul << SC_CTL_SYNC_Pos)
21710 #define SC_ALTCTL_TXRST_Pos (0)
21711 #define SC_ALTCTL_TXRST_Msk (0x1ul << SC_ALTCTL_TXRST_Pos)
21713 #define SC_ALTCTL_RXRST_Pos (1)
21714 #define SC_ALTCTL_RXRST_Msk (0x1ul << SC_ALTCTL_RXRST_Pos)
21716 #define SC_ALTCTL_DACTEN_Pos (2)
21717 #define SC_ALTCTL_DACTEN_Msk (0x1ul << SC_ALTCTL_DACTEN_Pos)
21719 #define SC_ALTCTL_ACTEN_Pos (3)
21720 #define SC_ALTCTL_ACTEN_Msk (0x1ul << SC_ALTCTL_ACTEN_Pos)
21722 #define SC_ALTCTL_WARSTEN_Pos (4)
21723 #define SC_ALTCTL_WARSTEN_Msk (0x1ul << SC_ALTCTL_WARSTEN_Pos)
21725 #define SC_ALTCTL_CNTEN0_Pos (5)
21726 #define SC_ALTCTL_CNTEN0_Msk (0x1ul << SC_ALTCTL_CNTEN0_Pos)
21728 #define SC_ALTCTL_CNTEN1_Pos (6)
21729 #define SC_ALTCTL_CNTEN1_Msk (0x1ul << SC_ALTCTL_CNTEN1_Pos)
21731 #define SC_ALTCTL_CNTEN2_Pos (7)
21732 #define SC_ALTCTL_CNTEN2_Msk (0x1ul << SC_ALTCTL_CNTEN2_Pos)
21734 #define SC_ALTCTL_INITSEL_Pos (8)
21735 #define SC_ALTCTL_INITSEL_Msk (0x3ul << SC_ALTCTL_INITSEL_Pos)
21737 #define SC_ALTCTL_RXBGTEN_Pos (12)
21738 #define SC_ALTCTL_RXBGTEN_Msk (0x1ul << SC_ALTCTL_RXBGTEN_Pos)
21740 #define SC_ALTCTL_ACTSTS0_Pos (13)
21741 #define SC_ALTCTL_ACTSTS0_Msk (0x1ul << SC_ALTCTL_ACTSTS0_Pos)
21743 #define SC_ALTCTL_ACTSTS1_Pos (14)
21744 #define SC_ALTCTL_ACTSTS1_Msk (0x1ul << SC_ALTCTL_ACTSTS1_Pos)
21746 #define SC_ALTCTL_ACTSTS2_Pos (15)
21747 #define SC_ALTCTL_ACTSTS2_Msk (0x1ul << SC_ALTCTL_ACTSTS2_Pos)
21749 #define SC_ALTCTL_OUTSEL_Pos (16)
21750 #define SC_ALTCTL_OUTSEL_Msk (0x1ul << SC_ALTCTL_OUTSEL_Pos)
21752 #define SC_EGT_EGT_Pos (0)
21753 #define SC_EGT_EGT_Msk (0xfful << SC_EGT_EGT_Pos)
21755 #define SC_RXTOUT_RFTM_Pos (0)
21756 #define SC_RXTOUT_RFTM_Msk (0x1fful << SC_RXTOUT_RFTM_Pos)
21758 #define SC_ETUCTL_ETURDIV_Pos (0)
21759 #define SC_ETUCTL_ETURDIV_Msk (0xffful << SC_ETUCTL_ETURDIV_Pos)
21761 #define SC_INTEN_RDAIEN_Pos (0)
21762 #define SC_INTEN_RDAIEN_Msk (0x1ul << SC_INTEN_RDAIEN_Pos)
21764 #define SC_INTEN_TBEIEN_Pos (1)
21765 #define SC_INTEN_TBEIEN_Msk (0x1ul << SC_INTEN_TBEIEN_Pos)
21767 #define SC_INTEN_TERRIEN_Pos (2)
21768 #define SC_INTEN_TERRIEN_Msk (0x1ul << SC_INTEN_TERRIEN_Pos)
21770 #define SC_INTEN_TMR0IEN_Pos (3)
21771 #define SC_INTEN_TMR0IEN_Msk (0x1ul << SC_INTEN_TMR0IEN_Pos)
21773 #define SC_INTEN_TMR1IEN_Pos (4)
21774 #define SC_INTEN_TMR1IEN_Msk (0x1ul << SC_INTEN_TMR1IEN_Pos)
21776 #define SC_INTEN_TMR2IEN_Pos (5)
21777 #define SC_INTEN_TMR2IEN_Msk (0x1ul << SC_INTEN_TMR2IEN_Pos)
21779 #define SC_INTEN_BGTIEN_Pos (6)
21780 #define SC_INTEN_BGTIEN_Msk (0x1ul << SC_INTEN_BGTIEN_Pos)
21782 #define SC_INTEN_CDIEN_Pos (7)
21783 #define SC_INTEN_CDIEN_Msk (0x1ul << SC_INTEN_CDIEN_Pos)
21785 #define SC_INTEN_INITIEN_Pos (8)
21786 #define SC_INTEN_INITIEN_Msk (0x1ul << SC_INTEN_INITIEN_Pos)
21788 #define SC_INTEN_RXTOIEN_Pos (9)
21789 #define SC_INTEN_RXTOIEN_Msk (0x1ul << SC_INTEN_RXTOIEN_Pos)
21791 #define SC_INTEN_ACERRIEN_Pos (10)
21792 #define SC_INTEN_ACERRIEN_Msk (0x1ul << SC_INTEN_ACERRIEN_Pos)
21794 #define SC_INTSTS_RDAIF_Pos (0)
21795 #define SC_INTSTS_RDAIF_Msk (0x1ul << SC_INTSTS_RDAIF_Pos)
21797 #define SC_INTSTS_TBEIF_Pos (1)
21798 #define SC_INTSTS_TBEIF_Msk (0x1ul << SC_INTSTS_TBEIF_Pos)
21800 #define SC_INTSTS_TERRIF_Pos (2)
21801 #define SC_INTSTS_TERRIF_Msk (0x1ul << SC_INTSTS_TERRIF_Pos)
21803 #define SC_INTSTS_TMR0IF_Pos (3)
21804 #define SC_INTSTS_TMR0IF_Msk (0x1ul << SC_INTSTS_TMR0IF_Pos)
21806 #define SC_INTSTS_TMR1IF_Pos (4)
21807 #define SC_INTSTS_TMR1IF_Msk (0x1ul << SC_INTSTS_TMR1IF_Pos)
21809 #define SC_INTSTS_TMR2IF_Pos (5)
21810 #define SC_INTSTS_TMR2IF_Msk (0x1ul << SC_INTSTS_TMR2IF_Pos)
21812 #define SC_INTSTS_BGTIF_Pos (6)
21813 #define SC_INTSTS_BGTIF_Msk (0x1ul << SC_INTSTS_BGTIF_Pos)
21815 #define SC_INTSTS_CDIF_Pos (7)
21816 #define SC_INTSTS_CDIF_Msk (0x1ul << SC_INTSTS_CDIF_Pos)
21818 #define SC_INTSTS_INITIF_Pos (8)
21819 #define SC_INTSTS_INITIF_Msk (0x1ul << SC_INTSTS_INITIF_Pos)
21821 #define SC_INTSTS_RXTOIF_Pos (9)
21822 #define SC_INTSTS_RXTOIF_Msk (0x1ul << SC_INTSTS_RXTOIF_Pos)
21824 #define SC_INTSTS_ACERRIF_Pos (10)
21825 #define SC_INTSTS_ACERRIF_Msk (0x1ul << SC_INTSTS_ACERRIF_Pos)
21827 #define SC_STATUS_RXOV_Pos (0)
21828 #define SC_STATUS_RXOV_Msk (0x1ul << SC_STATUS_RXOV_Pos)
21830 #define SC_STATUS_RXEMPTY_Pos (1)
21831 #define SC_STATUS_RXEMPTY_Msk (0x1ul << SC_STATUS_RXEMPTY_Pos)
21833 #define SC_STATUS_RXFULL_Pos (2)
21834 #define SC_STATUS_RXFULL_Msk (0x1ul << SC_STATUS_RXFULL_Pos)
21836 #define SC_STATUS_PEF_Pos (4)
21837 #define SC_STATUS_PEF_Msk (0x1ul << SC_STATUS_PEF_Pos)
21839 #define SC_STATUS_FEF_Pos (5)
21840 #define SC_STATUS_FEF_Msk (0x1ul << SC_STATUS_FEF_Pos)
21842 #define SC_STATUS_BEF_Pos (6)
21843 #define SC_STATUS_BEF_Msk (0x1ul << SC_STATUS_BEF_Pos)
21845 #define SC_STATUS_TXOV_Pos (8)
21846 #define SC_STATUS_TXOV_Msk (0x1ul << SC_STATUS_TXOV_Pos)
21848 #define SC_STATUS_TXEMPTY_Pos (9)
21849 #define SC_STATUS_TXEMPTY_Msk (0x1ul << SC_STATUS_TXEMPTY_Pos)
21851 #define SC_STATUS_TXFULL_Pos (10)
21852 #define SC_STATUS_TXFULL_Msk (0x1ul << SC_STATUS_TXFULL_Pos)
21854 #define SC_STATUS_RXPOINT_Pos (16)
21855 #define SC_STATUS_RXPOINT_Msk (0x3ul << SC_STATUS_RXPOINT_Pos)
21857 #define SC_STATUS_RXRERR_Pos (21)
21858 #define SC_STATUS_RXRERR_Msk (0x1ul << SC_STATUS_RXRERR_Pos)
21860 #define SC_STATUS_RXOVERR_Pos (22)
21861 #define SC_STATUS_RXOVERR_Msk (0x1ul << SC_STATUS_RXOVERR_Pos)
21863 #define SC_STATUS_RXACT_Pos (23)
21864 #define SC_STATUS_RXACT_Msk (0x1ul << SC_STATUS_RXACT_Pos)
21866 #define SC_STATUS_TXPOINT_Pos (24)
21867 #define SC_STATUS_TXPOINT_Msk (0x3ul << SC_STATUS_TXPOINT_Pos)
21869 #define SC_STATUS_TXRERR_Pos (29)
21870 #define SC_STATUS_TXRERR_Msk (0x1ul << SC_STATUS_TXRERR_Pos)
21872 #define SC_STATUS_TXOVERR_Pos (30)
21873 #define SC_STATUS_TXOVERR_Msk (0x1ul << SC_STATUS_TXOVERR_Pos)
21875 #define SC_STATUS_TXACT_Pos (31)
21876 #define SC_STATUS_TXACT_Msk (0x1ul << SC_STATUS_TXACT_Pos)
21878 #define SC_PINCTL_PWREN_Pos (0)
21879 #define SC_PINCTL_PWREN_Msk (0x1ul << SC_PINCTL_PWREN_Pos)
21881 #define SC_PINCTL_SCRST_Pos (1)
21882 #define SC_PINCTL_SCRST_Msk (0x1ul << SC_PINCTL_SCRST_Pos)
21884 #define SC_PINCTL_CREMOVE_Pos (2)
21885 #define SC_PINCTL_CREMOVE_Msk (0x1ul << SC_PINCTL_CREMOVE_Pos)
21887 #define SC_PINCTL_CINSERT_Pos (3)
21888 #define SC_PINCTL_CINSERT_Msk (0x1ul << SC_PINCTL_CINSERT_Pos)
21890 #define SC_PINCTL_CDPINSTS_Pos (4)
21891 #define SC_PINCTL_CDPINSTS_Msk (0x1ul << SC_PINCTL_CDPINSTS_Pos)
21893 #define SC_PINCTL_CLKKEEP_Pos (6)
21894 #define SC_PINCTL_CLKKEEP_Msk (0x1ul << SC_PINCTL_CLKKEEP_Pos)
21896 #define SC_PINCTL_ADACEN_Pos (7)
21897 #define SC_PINCTL_ADACEN_Msk (0x1ul << SC_PINCTL_ADACEN_Pos)
21899 #define SC_PINCTL_SCDOUT_Pos (9)
21900 #define SC_PINCTL_SCDOUT_Msk (0x1ul << SC_PINCTL_SCDOUT_Pos)
21902 #define SC_PINCTL_CDLV_Pos (10)
21903 #define SC_PINCTL_CDLV_Msk (0x1ul << SC_PINCTL_CDLV_Pos)
21905 #define SC_PINCTL_PWRINV_Pos (11)
21906 #define SC_PINCTL_PWRINV_Msk (0x1ul << SC_PINCTL_PWRINV_Pos)
21908 #define SC_PINCTL_DATSTS_Pos (16)
21909 #define SC_PINCTL_DATSTS_Msk (0x1ul << SC_PINCTL_DATSTS_Pos)
21911 #define SC_PINCTL_SYNC_Pos (30)
21912 #define SC_PINCTL_SYNC_Msk (0x1ul << SC_PINCTL_SYNC_Pos)
21914 #define SC_TMRCTL0_CNT_Pos (0)
21915 #define SC_TMRCTL0_CNT_Msk (0xfffffful << SC_TMRCTL0_CNT_Pos)
21917 #define SC_TMRCTL0_OPMODE_Pos (24)
21918 #define SC_TMRCTL0_OPMODE_Msk (0xful << SC_TMRCTL0_OPMODE_Pos)
21920 #define SC_TMRCTL0_SYNC_Pos (31)
21921 #define SC_TMRCTL0_SYNC_Msk (0x1ul << SC_TMRCTL0_SYNC_Pos)
21923 #define SC_TMRCTL1_CNT_Pos (0)
21924 #define SC_TMRCTL1_CNT_Msk (0xfful << SC_TMRCTL1_CNT_Pos)
21926 #define SC_TMRCTL1_OPMODE_Pos (24)
21927 #define SC_TMRCTL1_OPMODE_Msk (0xful << SC_TMRCTL1_OPMODE_Pos)
21929 #define SC_TMRCTL1_SYNC_Pos (31)
21930 #define SC_TMRCTL1_SYNC_Msk (0x1ul << SC_TMRCTL1_SYNC_Pos)
21932 #define SC_TMRCTL2_CNT_Pos (0)
21933 #define SC_TMRCTL2_CNT_Msk (0xfful << SC_TMRCTL2_CNT_Pos)
21935 #define SC_TMRCTL2_OPMODE_Pos (24)
21936 #define SC_TMRCTL2_OPMODE_Msk (0xful << SC_TMRCTL2_OPMODE_Pos)
21938 #define SC_TMRCTL2_SYNC_Pos (31)
21939 #define SC_TMRCTL2_SYNC_Msk (0x1ul << SC_TMRCTL2_SYNC_Pos)
21941 #define SC_UARTCTL_UARTEN_Pos (0)
21942 #define SC_UARTCTL_UARTEN_Msk (0x1ul << SC_UARTCTL_UARTEN_Pos)
21944 #define SC_UARTCTL_WLS_Pos (4)
21945 #define SC_UARTCTL_WLS_Msk (0x3ul << SC_UARTCTL_WLS_Pos)
21947 #define SC_UARTCTL_PBOFF_Pos (6)
21948 #define SC_UARTCTL_PBOFF_Msk (0x1ul << SC_UARTCTL_PBOFF_Pos)
21950 #define SC_UARTCTL_OPE_Pos (7)
21951 #define SC_UARTCTL_OPE_Msk (0x1ul << SC_UARTCTL_OPE_Pos)
21953 #define SC_ACTCTL_T1EXT_Pos (0)
21954 #define SC_ACTCTL_T1EXT_Msk (0x1ful << SC_ACTCTL_T1EXT_Pos) /* SC_CONST */
21957 /* end of SC register group */
21958
21959
21960 /*---------------------- Inter-IC Bus Controller -------------------------*/
21966 typedef struct
21967 {
21968
21969
22431 __IO uint32_t CTL;
22432 __IO uint32_t INTSTS;
22433 __I uint32_t STATUS;
22434 __IO uint32_t CLKDIV;
22435 __IO uint32_t TOCTL;
22436 __IO uint32_t DAT;
22437 __IO uint32_t ADDR0;
22438 __IO uint32_t ADDR1;
22439 __I uint32_t RESERVE0[2];
22442 __IO uint32_t ADDRMSK0;
22443 __IO uint32_t ADDRMSK1;
22444 __I uint32_t RESERVE1[4];
22447 __IO uint32_t CTL2;
22448 __IO uint32_t STATUS2;
22450 } I2C_T;
22451
22457 #define I2C_CTL_I2CEN_Pos (0)
22458 #define I2C_CTL_I2CEN_Msk (0x1ul << I2C_CTL_I2CEN_Pos)
22460 #define I2C_CTL_AA_Pos (1)
22461 #define I2C_CTL_AA_Msk (0x1ul << I2C_CTL_AA_Pos)
22463 #define I2C_CTL_STO_Pos (2)
22464 #define I2C_CTL_STO_Msk (0x1ul << I2C_CTL_STO_Pos)
22466 #define I2C_CTL_STA_Pos (3)
22467 #define I2C_CTL_STA_Msk (0x1ul << I2C_CTL_STA_Pos)
22469 #define I2C_CTL_SI_Pos (4)
22470 #define I2C_CTL_SI_Msk (0x1ul << I2C_CTL_SI_Pos)
22472 #define I2C_CTL_INTEN_Pos (7)
22473 #define I2C_CTL_INTEN_Msk (0x1ul << I2C_CTL_INTEN_Pos)
22475 #define I2C_INTSTS_INTSTS_Pos (0)
22476 #define I2C_INTSTS_INTSTS_Msk (0x1ul << I2C_INTSTS_INTSTS_Pos)
22478 #define I2C_INTSTS_TOIF_Pos (1)
22479 #define I2C_INTSTS_TOIF_Msk (0x1ul << I2C_INTSTS_TOIF_Pos)
22481 #define I2C_INTSTS_WKAKDONE_Pos (7)
22482 #define I2C_INTSTS_WKAKDONE_Msk (0x1ul << I2C_INTSTS_WKAKDONE_Pos)
22484 #define I2C_STATUS_STATUS_Pos (0)
22485 #define I2C_STATUS_STATUS_Msk (0xfful << I2C_STATUS_STATUS_Pos)
22487 #define I2C_CLKDIV_DIVIDER_Pos (0)
22488 #define I2C_CLKDIV_DIVIDER_Msk (0xfful << I2C_CLKDIV_DIVIDER_Pos)
22490 #define I2C_TOCTL_TOCEN_Pos (0)
22491 #define I2C_TOCTL_TOCEN_Msk (0x1ul << I2C_TOCTL_TOCEN_Pos)
22493 #define I2C_TOCTL_TOCDIV4_Pos (1)
22494 #define I2C_TOCTL_TOCDIV4_Msk (0x1ul << I2C_TOCTL_TOCDIV4_Pos)
22496 #define I2C_DAT_DAT_Pos (0)
22497 #define I2C_DAT_DAT_Msk (0xfful << I2C_DAT_DAT_Pos)
22499 #define I2C_ADDR0_GC_Pos (0)
22500 #define I2C_ADDR0_GC_Msk (0x1ul << I2C_ADDR0_GC_Pos)
22502 #define I2C_ADDR0_ADDR_Pos (1)
22503 #define I2C_ADDR0_ADDR_Msk (0x7ful << I2C_ADDR0_ADDR_Pos)
22505 #define I2C_ADDR1_GC_Pos (0)
22506 #define I2C_ADDR1_GC_Msk (0x1ul << I2C_ADDR1_GC_Pos)
22508 #define I2C_ADDR1_ADDR_Pos (1)
22509 #define I2C_ADDR1_ADDR_Msk (0x7ful << I2C_ADDR1_ADDR_Pos)
22511 #define I2C_ADDRMSK0_ADDRMSK_Pos (1)
22512 #define I2C_ADDRMSK0_ADDRMSK_Msk (0x7ful << I2C_ADDRMSK0_ADDRMSK_Pos)
22514 #define I2C_ADDRMSK1_ADDRMSK_Pos (1)
22515 #define I2C_ADDRMSK1_ADDRMSK_Msk (0x7ful << I2C_ADDRMSK1_ADDRMSK_Pos)
22517 #define I2C_CTL2_WKUPEN_Pos (0)
22518 #define I2C_CTL2_WKUPEN_Msk (0x1ul << I2C_CTL2_WKUPEN_Pos)
22520 #define I2C_CTL2_OVIEN_Pos (1)
22521 #define I2C_CTL2_OVIEN_Msk (0x1ul << I2C_CTL2_OVIEN_Pos)
22523 #define I2C_CTL2_URIEN_Pos (2)
22524 #define I2C_CTL2_URIEN_Msk (0x1ul << I2C_CTL2_URIEN_Pos)
22526 #define I2C_CTL2_TWOLVBUF_Pos (4)
22527 #define I2C_CTL2_TWOLVBUF_Msk (0x1ul << I2C_CTL2_TWOLVBUF_Pos)
22529 #define I2C_CTL2_NOSTRETCH_Pos (5)
22530 #define I2C_CTL2_NOSTRETCH_Msk (0x1ul << I2C_CTL2_NOSTRETCH_Pos)
22532 #define I2C_CTL2_DATMODE_Pos (6)
22533 #define I2C_CTL2_DATMODE_Msk (0x1ul << I2C_CTL2_DATMODE_Pos)
22535 #define I2C_CTL2_MSDAT_Pos (7)
22536 #define I2C_CTL2_MSDAT_Msk (0x1ul << I2C_CTL2_MSDAT_Pos)
22538 #define I2C_STATUS2_WKIF_Pos (0)
22539 #define I2C_STATUS2_WKIF_Msk (0x1ul << I2C_STATUS2_WKIF_Pos)
22541 #define I2C_STATUS2_OVIF_Pos (1)
22542 #define I2C_STATUS2_OVIF_Msk (0x1ul << I2C_STATUS2_OVIF_Pos)
22544 #define I2C_STATUS2_URIF_Pos (2)
22545 #define I2C_STATUS2_URIF_Msk (0x1ul << I2C_STATUS2_URIF_Pos)
22547 #define I2C_STATUS2_WRSTSWK_Pos (3)
22548 #define I2C_STATUS2_WRSTSWK_Msk (0x1ul << I2C_STATUS2_WRSTSWK_Pos)
22550 #define I2C_STATUS2_FULL_Pos (4)
22551 #define I2C_STATUS2_FULL_Msk (0x1ul << I2C_STATUS2_FULL_Pos)
22553 #define I2C_STATUS2_EMPTY_Pos (5)
22554 #define I2C_STATUS2_EMPTY_Msk (0x1ul << I2C_STATUS2_EMPTY_Pos)
22556 #define I2C_STATUS2_BUSFREE_Pos (6)
22557 #define I2C_STATUS2_BUSFREE_Msk (0x1ul << I2C_STATUS2_BUSFREE_Pos) /* I2C_CONST */
22560 /* end of I2C register group */
22561
22562
22563 /*---------------------- Serial Peripheral Interface Controller -------------------------*/
22569 typedef struct
22570 {
22571
22572
23393 __IO uint32_t CTL;
23394 __IO uint32_t STATUS;
23395 __IO uint32_t CLKDIV;
23396 __IO uint32_t SSCTL;
23397 __I uint32_t RX0;
23398 __I uint32_t RX1;
23399 __I uint32_t RESERVE0[2];
23402 __O uint32_t TX0;
23403 __O uint32_t TX1;
23404 __I uint32_t RESERVE1[4];
23407 __IO uint32_t PDMACTL;
23408 __IO uint32_t FIFOCTL;
23409 } SPI_T;
23410
23416 #define SPI_CTL_GOBUSY_Pos (0)
23417 #define SPI_CTL_GOBUSY_Msk (0x1ul << SPI_CTL_GOBUSY_Pos)
23419 #define SPI_CTL_RXNEG_Pos (1)
23420 #define SPI_CTL_RXNEG_Msk (0x1ul << SPI_CTL_RXNEG_Pos)
23422 #define SPI_CTL_TXNEG_Pos (2)
23423 #define SPI_CTL_TXNEG_Msk (0x1ul << SPI_CTL_TXNEG_Pos)
23425 #define SPI_CTL_DWIDTH_Pos (3)
23426 #define SPI_CTL_DWIDTH_Msk (0x1ful << SPI_CTL_DWIDTH_Pos)
23428 #define SPI_CTL_LSB_Pos (10)
23429 #define SPI_CTL_LSB_Msk (0x1ul << SPI_CTL_LSB_Pos)
23431 #define SPI_CTL_CLKPOL_Pos (11)
23432 #define SPI_CTL_CLKPOL_Msk (0x1ul << SPI_CTL_CLKPOL_Pos)
23434 #define SPI_CTL_SUSPITV_Pos (12)
23435 #define SPI_CTL_SUSPITV_Msk (0xful << SPI_CTL_SUSPITV_Pos)
23437 #define SPI_CTL_UNITIEN_Pos (17)
23438 #define SPI_CTL_UNITIEN_Msk (0x1ul << SPI_CTL_UNITIEN_Pos)
23440 #define SPI_CTL_SLAVE_Pos (18)
23441 #define SPI_CTL_SLAVE_Msk (0x1ul << SPI_CTL_SLAVE_Pos)
23443 #define SPI_CTL_REORDER_Pos (19)
23444 #define SPI_CTL_REORDER_Msk (0x1ul << SPI_CTL_REORDER_Pos)
23446 #define SPI_CTL_FIFOM_Pos (21)
23447 #define SPI_CTL_FIFOM_Msk (0x1ul << SPI_CTL_FIFOM_Pos)
23449 #define SPI_CTL_TWOBIT_Pos (22)
23450 #define SPI_CTL_TWOBIT_Msk (0x1ul << SPI_CTL_TWOBIT_Pos)
23452 #define SPI_CTL_DUALDIR_Pos (28)
23453 #define SPI_CTL_DUALDIR_Msk (0x1ul << SPI_CTL_DUALDIR_Pos)
23455 #define SPI_CTL_DUALIOEN_Pos (29)
23456 #define SPI_CTL_DUALIOEN_Msk (0x1ul << SPI_CTL_DUALIOEN_Pos)
23458 #define SPI_CTL_WKSSEN_Pos (30)
23459 #define SPI_CTL_WKSSEN_Msk (0x1ul << SPI_CTL_WKSSEN_Pos)
23461 #define SPI_CTL_WKCLKEN_Pos (31)
23462 #define SPI_CTL_WKCLKEN_Msk (0x1ul << SPI_CTL_WKCLKEN_Pos)
23464 #define SPI_STATUS_RXEMPTY_Pos (0)
23465 #define SPI_STATUS_RXEMPTY_Msk (0x1ul << SPI_STATUS_RXEMPTY_Pos)
23467 #define SPI_STATUS_RXFULL_Pos (1)
23468 #define SPI_STATUS_RXFULL_Msk (0x1ul << SPI_STATUS_RXFULL_Pos)
23470 #define SPI_STATUS_TXEMPTY_Pos (2)
23471 #define SPI_STATUS_TXEMPTY_Msk (0x1ul << SPI_STATUS_TXEMPTY_Pos)
23473 #define SPI_STATUS_TXFULL_Pos (3)
23474 #define SPI_STATUS_TXFULL_Msk (0x1ul << SPI_STATUS_TXFULL_Pos)
23476 #define SPI_STATUS_LTRIGF_Pos (4)
23477 #define SPI_STATUS_LTRIGF_Msk (0x1ul << SPI_STATUS_LTRIGF_Pos)
23479 #define SPI_STATUS_SLVSTAIF_Pos (6)
23480 #define SPI_STATUS_SLVSTAIF_Msk (0x1ul << SPI_STATUS_SLVSTAIF_Pos)
23482 #define SPI_STATUS_UNITIF_Pos (7)
23483 #define SPI_STATUS_UNITIF_Msk (0x1ul << SPI_STATUS_UNITIF_Pos)
23485 #define SPI_STATUS_RXTHIF_Pos (8)
23486 #define SPI_STATUS_RXTHIF_Msk (0x1ul << SPI_STATUS_RXTHIF_Pos)
23488 #define SPI_STATUS_RXOVIF_Pos (9)
23489 #define SPI_STATUS_RXOVIF_Msk (0x1ul << SPI_STATUS_RXOVIF_Pos)
23491 #define SPI_STATUS_TXTHIF_Pos (10)
23492 #define SPI_STATUS_TXTHIF_Msk (0x1ul << SPI_STATUS_TXTHIF_Pos)
23494 #define SPI_STATUS_RXTOIF_Pos (12)
23495 #define SPI_STATUS_RXTOIF_Msk (0x1ul << SPI_STATUS_RXTOIF_Pos)
23497 #define SPI_STATUS_SLVTOIF_Pos (13)
23498 #define SPI_STATUS_SLVTOIF_Msk (0x1ul << SPI_STATUS_SLVTOIF_Pos)
23500 #define SPI_STATUS_SLVTXSKE_Pos (15)
23501 #define SPI_STATUS_SLVTXSKE_Msk (0x1ul << SPI_STATUS_SLVTXSKE_Pos)
23503 #define SPI_STATUS_RXCNT_Pos (16)
23504 #define SPI_STATUS_RXCNT_Msk (0xful << SPI_STATUS_RXCNT_Pos)
23506 #define SPI_STATUS_TXCNT_Pos (20)
23507 #define SPI_STATUS_TXCNT_Msk (0xful << SPI_STATUS_TXCNT_Pos)
23509 #define SPI_STATUS_WKSSIF_Pos (30)
23510 #define SPI_STATUS_WKSSIF_Msk (0x1ul << SPI_STATUS_WKSSIF_Pos)
23512 #define SPI_STATUS_WKCLKIF_Pos (31)
23513 #define SPI_STATUS_WKCLKIF_Msk (0x1ul << SPI_STATUS_WKCLKIF_Pos)
23515 #define SPI_CLKDIV_DIVIDER_Pos (0)
23516 #define SPI_CLKDIV_DIVIDER_Msk (0xfful << SPI_CLKDIV_DIVIDER_Pos)
23518 #define SPI_SSCTL_SS_Pos (0)
23519 #define SPI_SSCTL_SS_Msk (0x3ul << SPI_SSCTL_SS_Pos)
23521 #define SPI_SSCTL_SSACTPOL_Pos (2)
23522 #define SPI_SSCTL_SSACTPOL_Msk (0x1ul << SPI_SSCTL_SSACTPOL_Pos)
23524 #define SPI_SSCTL_AUTOSS_Pos (3)
23525 #define SPI_SSCTL_AUTOSS_Msk (0x1ul << SPI_SSCTL_AUTOSS_Pos)
23527 #define SPI_SSCTL_SSLTRIG_Pos (4)
23528 #define SPI_SSCTL_SSLTRIG_Msk (0x1ul << SPI_SSCTL_SSLTRIG_Pos)
23530 #define SPI_SSCTL_SLV3WIRE_Pos (5)
23531 #define SPI_SSCTL_SLV3WIRE_Msk (0x1ul << SPI_SSCTL_SLV3WIRE_Pos)
23533 #define SPI_SSCTL_SLVTOIEN_Pos (6)
23534 #define SPI_SSCTL_SLVTOIEN_Msk (0x1ul << SPI_SSCTL_SLVTOIEN_Pos)
23536 #define SPI_SSCTL_SLVABORT_Pos (8)
23537 #define SPI_SSCTL_SLVABORT_Msk (0x1ul << SPI_SSCTL_SLVABORT_Pos)
23539 #define SPI_SSCTL_SSTAIEN_Pos (9)
23540 #define SPI_SSCTL_SSTAIEN_Msk (0x1ul << SPI_SSCTL_SSTAIEN_Pos)
23542 #define SPI_SSCTL_SSINAIEN_Pos (16)
23543 #define SPI_SSCTL_SSINAIEN_Msk (0x1ul << SPI_SSCTL_SSINAIEN_Pos)
23545 #define SPI_SSCTL_SLVTOCNT_Pos (20)
23546 #define SPI_SSCTL_SLVTOCNT_Msk (0x3fful << SPI_SSCTL_SLVTOCNT_Pos)
23548 #define SPI_RX0_RX_Pos (0)
23549 #define SPI_RX0_RX_Msk (0xfffffffful << SPI_RX0_RX_Pos)
23551 #define SPI_RX1_RX_Pos (0)
23552 #define SPI_RX1_RX_Msk (0xfffffffful << SPI_RX1_RX_Pos)
23554 #define SPI_TX0_TX_Pos (0)
23555 #define SPI_TX0_TX_Msk (0xfffffffful << SPI_TX0_TX_Pos)
23557 #define SPI_TX1_TX_Pos (0)
23558 #define SPI_TX1_TX_Msk (0xfffffffful << SPI_TX1_TX_Pos)
23560 #define SPI_PDMACTL_TXPDMAEN_Pos (0)
23561 #define SPI_PDMACTL_TXPDMAEN_Msk (0x1ul << SPI_PDMACTL_TXPDMAEN_Pos)
23563 #define SPI_PDMACTL_RXPDMAEN_Pos (1)
23564 #define SPI_PDMACTL_RXPDMAEN_Msk (0x1ul << SPI_PDMACTL_RXPDMAEN_Pos)
23566 #define SPI_PDMACTL_PDMARST_Pos (2)
23567 #define SPI_PDMACTL_PDMARST_Msk (0x1ul << SPI_PDMACTL_PDMARST_Pos)
23569 #define SPI_FIFOCTL_RXFBCLR_Pos (0)
23570 #define SPI_FIFOCTL_RXFBCLR_Msk (0x1ul << SPI_FIFOCTL_RXFBCLR_Pos)
23572 #define SPI_FIFOCTL_TXFBCLR_Pos (1)
23573 #define SPI_FIFOCTL_TXFBCLR_Msk (0x1ul << SPI_FIFOCTL_TXFBCLR_Pos)
23575 #define SPI_FIFOCTL_RXTHIEN_Pos (2)
23576 #define SPI_FIFOCTL_RXTHIEN_Msk (0x1ul << SPI_FIFOCTL_RXTHIEN_Pos)
23578 #define SPI_FIFOCTL_TXTHIEN_Pos (3)
23579 #define SPI_FIFOCTL_TXTHIEN_Msk (0x1ul << SPI_FIFOCTL_TXTHIEN_Pos)
23581 #define SPI_FIFOCTL_RXOVIEN_Pos (4)
23582 #define SPI_FIFOCTL_RXOVIEN_Msk (0x1ul << SPI_FIFOCTL_RXOVIEN_Pos)
23584 #define SPI_FIFOCTL_RXTOIEN_Pos (7)
23585 #define SPI_FIFOCTL_RXTOIEN_Msk (0x1ul << SPI_FIFOCTL_RXTOIEN_Pos)
23587 #define SPI_FIFOCTL_RXTH_Pos (24)
23588 #define SPI_FIFOCTL_RXTH_Msk (0x7ul << SPI_FIFOCTL_RXTH_Pos)
23590 #define SPI_FIFOCTL_TXTH_Pos (28)
23591 #define SPI_FIFOCTL_TXTH_Msk (0x7ul << SPI_FIFOCTL_TXTH_Pos) /* SPI_CONST */
23594 /* end of SPI register group */
23595
23596
23597 /*---------------------- Analog to Digital Converter -------------------------*/
23603 typedef struct
23604 {
23605
23606
24387 __I uint32_t DAT[18];
24388 __IO uint32_t CTL;
24389 __IO uint32_t CHEN;
24390 __IO uint32_t CMP0;
24391 __IO uint32_t CMP1;
24392 __IO uint32_t STATUS;
24393 __I uint32_t RESERVE1[1];
24396 __I uint32_t PDMA;
24397 __IO uint32_t PWD;
24398 __IO uint32_t CALCTL;
24399 __IO uint32_t CALWORD;
24400 __IO uint32_t EXTSMPT0;
24401 __IO uint32_t EXTSMPT1;
24403 } ADC_T;
24404
24410 #define ADC_DAT0_RESULT_Pos (0)
24411 #define ADC_DAT0_RESULT_Msk (0xffful << ADC_DAT0_RESULT_Pos)
24413 #define ADC_DAT0_VALID_Pos (16)
24414 #define ADC_DAT0_VALID_Msk (0x1ul << ADC_DAT0_VALID_Pos)
24416 #define ADC_DAT0_OV_Pos (17)
24417 #define ADC_DAT0_OV_Msk (0x1ul << ADC_DAT0_OV_Pos)
24419 #define ADC_CTL_ADCEN_Pos (0)
24420 #define ADC_CTL_ADCEN_Msk (0x1ul << ADC_CTL_ADCEN_Pos)
24422 #define ADC_CTL_ADCIEN_Pos (1)
24423 #define ADC_CTL_ADCIEN_Msk (0x1ul << ADC_CTL_ADCIEN_Pos)
24425 #define ADC_CTL_ADMD_Pos (2)
24426 #define ADC_CTL_ADMD_Msk (0x3ul << ADC_CTL_ADMD_Pos)
24428 #define ADC_CTL_HWTRGSEL_Pos (4)
24429 #define ADC_CTL_HWTRGSEL_Msk (0x3ul << ADC_CTL_HWTRGSEL_Pos)
24431 #define ADC_CTL_HWTRGCOND_Pos (6)
24432 #define ADC_CTL_HWTRGCOND_Msk (0x3ul << ADC_CTL_HWTRGCOND_Pos)
24434 #define ADC_CTL_HWTRGEN_Pos (8)
24435 #define ADC_CTL_HWTRGEN_Msk (0x1ul << ADC_CTL_HWTRGEN_Pos)
24437 #define ADC_CTL_PTEN_Pos (9)
24438 #define ADC_CTL_PTEN_Msk (0x1ul << ADC_CTL_PTEN_Pos)
24440 #define ADC_CTL_DIFF_Pos (10)
24441 #define ADC_CTL_DIFF_Msk (0x1ul << ADC_CTL_DIFF_Pos)
24443 #define ADC_CTL_SWTRG_Pos (11)
24444 #define ADC_CTL_SWTRG_Msk (0x1ul << ADC_CTL_SWTRG_Pos)
24446 #define ADC_CTL_TMSEL_Pos (12)
24447 #define ADC_CTL_TMSEL_Msk (0x3ul << ADC_CTL_TMSEL_Pos)
24449 #define ADC_CTL_TMTRGMOD_Pos (15)
24450 #define ADC_CTL_TMTRGMOD_Msk (0x1ul << ADC_CTL_TMTRGMOD_Pos)
24452 #define ADC_CTL_REFSEL_Pos (16)
24453 #define ADC_CTL_REFSEL_Msk (0x3ul << ADC_CTL_REFSEL_Pos)
24455 #define ADC_CTL_RESSEL_Pos (18)
24456 #define ADC_CTL_RESSEL_Msk (0x3ul << ADC_CTL_RESSEL_Pos)
24458 #define ADC_CTL_TMPDMACNT_Pos (24)
24459 #define ADC_CTL_TMPDMACNT_Msk (0xfful << ADC_CTL_TMPDMACNT_Pos)
24461 #define ADC_CHEN_CHEN0_Pos (0)
24462 #define ADC_CHEN_CHEN0_Msk (0x1ul << ADC_CHEN_CHEN0_Pos)
24464 #define ADC_CHEN_CHEN1_Pos (1)
24465 #define ADC_CHEN_CHEN1_Msk (0x1ul << ADC_CHEN_CHEN1_Pos)
24467 #define ADC_CHEN_CHEN2_Pos (2)
24468 #define ADC_CHEN_CHEN2_Msk (0x1ul << ADC_CHEN_CHEN2_Pos)
24470 #define ADC_CHEN_CHEN3_Pos (3)
24471 #define ADC_CHEN_CHEN3_Msk (0x1ul << ADC_CHEN_CHEN3_Pos)
24473 #define ADC_CHEN_CHEN4_Pos (4)
24474 #define ADC_CHEN_CHEN4_Msk (0x1ul << ADC_CHEN_CHEN4_Pos)
24476 #define ADC_CHEN_CHEN5_Pos (5)
24477 #define ADC_CHEN_CHEN5_Msk (0x1ul << ADC_CHEN_CHEN5_Pos)
24479 #define ADC_CHEN_CHEN6_Pos (6)
24480 #define ADC_CHEN_CHEN6_Msk (0x1ul << ADC_CHEN_CHEN6_Pos)
24482 #define ADC_CHEN_CHEN7_Pos (7)
24483 #define ADC_CHEN_CHEN7_Msk (0x1ul << ADC_CHEN_CHEN7_Pos)
24485 #define ADC_CHEN_CHEN12_Pos (12)
24486 #define ADC_CHEN_CHEN12_Msk (0x1ul << ADC_CHEN_CHEN12_Pos)
24488 #define ADC_CHEN_CHEN13_Pos (13)
24489 #define ADC_CHEN_CHEN13_Msk (0x1ul << ADC_CHEN_CHEN13_Pos)
24491 #define ADC_CHEN_CHEN14_Pos (14)
24492 #define ADC_CHEN_CHEN14_Msk (0x1ul << ADC_CHEN_CHEN14_Pos)
24494 #define ADC_CHEN_CHEN15_Pos (15)
24495 #define ADC_CHEN_CHEN15_Msk (0x1ul << ADC_CHEN_CHEN15_Pos)
24497 #define ADC_CHEN_CHEN16_Pos (16)
24498 #define ADC_CHEN_CHEN16_Msk (0x1ul << ADC_CHEN_CHEN16_Pos)
24500 #define ADC_CHEN_CHEN17_Pos (17)
24501 #define ADC_CHEN_CHEN17_Msk (0x1ul << ADC_CHEN_CHEN17_Pos)
24503 #define ADC_CMP0_ADCMPEN_Pos (0)
24504 #define ADC_CMP0_ADCMPEN_Msk (0x1ul << ADC_CMP0_ADCMPEN_Pos)
24506 #define ADC_CMP0_ADCMPIE_Pos (1)
24507 #define ADC_CMP0_ADCMPIE_Msk (0x1ul << ADC_CMP0_ADCMPIE_Pos)
24509 #define ADC_CMP0_CMPCOND_Pos (2)
24510 #define ADC_CMP0_CMPCOND_Msk (0x1ul << ADC_CMP0_CMPCOND_Pos)
24512 #define ADC_CMP0_CMPCH_Pos (3)
24513 #define ADC_CMP0_CMPCH_Msk (0x1ful << ADC_CMP0_CMPCH_Pos)
24515 #define ADC_CMP0_CMPMCNT_Pos (8)
24516 #define ADC_CMP0_CMPMCNT_Msk (0xful << ADC_CMP0_CMPMCNT_Pos)
24518 #define ADC_CMP0_CMPDAT_Pos (16)
24519 #define ADC_CMP0_CMPDAT_Msk (0xffful << ADC_CMP0_CMPDAT_Pos)
24521 #define ADC_CMP1_ADCMPEN_Pos (0)
24522 #define ADC_CMP1_ADCMPEN_Msk (0x1ul << ADC_CMP1_ADCMPEN_Pos)
24524 #define ADC_CMP1_ADCMPIE_Pos (1)
24525 #define ADC_CMP1_ADCMPIE_Msk (0x1ul << ADC_CMP1_ADCMPIE_Pos)
24527 #define ADC_CMP1_CMPCOND_Pos (2)
24528 #define ADC_CMP1_CMPCOND_Msk (0x1ul << ADC_CMP1_CMPCOND_Pos)
24530 #define ADC_CMP1_CMPCH_Pos (3)
24531 #define ADC_CMP1_CMPCH_Msk (0x1ful << ADC_CMP1_CMPCH_Pos)
24533 #define ADC_CMP1_CMPMCNT_Pos (8)
24534 #define ADC_CMP1_CMPMCNT_Msk (0xful << ADC_CMP1_CMPMCNT_Pos)
24536 #define ADC_CMP1_CMPDAT_Pos (16)
24537 #define ADC_CMP1_CMPDAT_Msk (0xffful << ADC_CMP1_CMPDAT_Pos)
24539 #define ADC_STATUS_ADIF_Pos (0)
24540 #define ADC_STATUS_ADIF_Msk (0x1ul << ADC_STATUS_ADIF_Pos)
24542 #define ADC_STATUS_ADCMPF0_Pos (1)
24543 #define ADC_STATUS_ADCMPF0_Msk (0x1ul << ADC_STATUS_ADCMPF0_Pos)
24545 #define ADC_STATUS_ADCMPF1_Pos (2)
24546 #define ADC_STATUS_ADCMPF1_Msk (0x1ul << ADC_STATUS_ADCMPF1_Pos)
24548 #define ADC_STATUS_BUSY_Pos (3)
24549 #define ADC_STATUS_BUSY_Msk (0x1ul << ADC_STATUS_BUSY_Pos)
24551 #define ADC_STATUS_CHANNEL_Pos (4)
24552 #define ADC_STATUS_CHANNEL_Msk (0x1ful << ADC_STATUS_CHANNEL_Pos)
24554 #define ADC_STATUS_INITRDY_Pos (16)
24555 #define ADC_STATUS_INITRDY_Msk (0x1ul << ADC_STATUS_INITRDY_Pos)
24557 #define ADC_PDMA_AD_PDMA_Pos (0)
24558 #define ADC_PDMA_AD_PDMA_Msk (0xffful << ADC_PDMA_AD_PDMA_Pos)
24560 #define ADC_PWD_PWUPRDY_Pos (0)
24561 #define ADC_PWD_PWUPRDY_Msk (0x1ul << ADC_PWD_PWUPRDY_Pos)
24563 #define ADC_PWD_PWDCALEN_Pos (1)
24564 #define ADC_PWD_PWDCALEN_Msk (0x1ul << ADC_PWD_PWDCALEN_Pos)
24566 #define ADC_PWD_PWDMOD_Pos (2)
24567 #define ADC_PWD_PWDMOD_Msk (0x3ul << ADC_PWD_PWDMOD_Pos)
24569 #define ADC_CALCTL_CALEN_Pos (0)
24570 #define ADC_CALCTL_CALEN_Msk (0x1ul << ADC_CALCTL_CALEN_Pos)
24572 #define ADC_CALCTL_CALSTART_Pos (1)
24573 #define ADC_CALCTL_CALSTART_Msk (0x1ul << ADC_CALCTL_CALSTART_Pos)
24575 #define ADC_CALCTL_CALDONE_Pos (2)
24576 #define ADC_CALCTL_CALDONE_Msk (0x1ul << ADC_CALCTL_CALDONE_Pos)
24578 #define ADC_CALCTL_CALSEL_Pos (3)
24579 #define ADC_CALCTL_CALSEL_Msk (0x1ul << ADC_CALCTL_CALSEL_Pos)
24581 #define ADC_CALWORD_CALWORD_Pos (0)
24582 #define ADC_CALWORD_CALWORD_Msk (0x7ful << ADC_CALWORD_CALWORD_Pos)
24584 #define ADC_EXTSMPT0_EXTSMPT_CH0_Pos (0)
24585 #define ADC_EXTSMPT0_EXTSMPT_CH0_Msk (0xful << ADC_EXTSMPT0_EXTSMPT_CH0_Pos)
24587 #define ADC_EXTSMPT0_EXTSMPT_CH1_Pos (4)
24588 #define ADC_EXTSMPT0_EXTSMPT_CH1_Msk (0xful << ADC_EXTSMPT0_EXTSMPT_CH1_Pos)
24590 #define ADC_EXTSMPT0_EXTSMPT_CH2_Pos (8)
24591 #define ADC_EXTSMPT0_EXTSMPT_CH2_Msk (0xful << ADC_EXTSMPT0_EXTSMPT_CH2_Pos)
24593 #define ADC_EXTSMPT0_EXTSMPT_CH3_Pos (12)
24594 #define ADC_EXTSMPT0_EXTSMPT_CH3_Msk (0xful << ADC_EXTSMPT0_EXTSMPT_CH3_Pos)
24596 #define ADC_EXTSMPT0_EXTSMPT_CH4_Pos (16)
24597 #define ADC_EXTSMPT0_EXTSMPT_CH4_Msk (0xful << ADC_EXTSMPT0_EXTSMPT_CH4_Pos)
24599 #define ADC_EXTSMPT0_EXTSMPT_CH5_Pos (20)
24600 #define ADC_EXTSMPT0_EXTSMPT_CH5_Msk (0xful << ADC_EXTSMPT0_EXTSMPT_CH5_Pos)
24602 #define ADC_EXTSMPT0_EXTSMPT_CH6_Pos (24)
24603 #define ADC_EXTSMPT0_EXTSMPT_CH6_Msk (0xful << ADC_EXTSMPT0_EXTSMPT_CH6_Pos)
24605 #define ADC_EXTSMPT0_EXTSMPT_CH7_Pos (28)
24606 #define ADC_EXTSMPT0_EXTSMPT_CH7_Msk (0xful << ADC_EXTSMPT0_EXTSMPT_CH7_Pos)
24608 #define ADC_EXTSMPT1_EXTSMPT_INTCH_Pos (16)
24609 #define ADC_EXTSMPT1_EXTSMPT_INTCH_Msk (0xful << ADC_EXTSMPT1_EXTSMPT_INTCH_Pos) /* ADC_CONST */
24612 /* end of ADC register group */
24613
24614
24615 /*---------------------- Analog Comparator Controller -------------------------*/
24621 typedef struct
24622 {
24623
24624
24747 __IO uint32_t CTL0;
24748 __IO uint32_t STATUS;
24749 __IO uint32_t VREF;
24751 } ACMP_T;
24752
24758 #define ACMP_CTL0_ACMPEN_Pos (0)
24759 #define ACMP_CTL0_ACMPEN_Msk (0x1ul << ACMP_CTL0_ACMPEN_Pos)
24761 #define ACMP_CTL0_ACMPIE_Pos (1)
24762 #define ACMP_CTL0_ACMPIE_Msk (0x1ul << ACMP_CTL0_ACMPIE_Pos)
24764 #define ACMP_CTL0_HYSEN_Pos (2)
24765 #define ACMP_CTL0_HYSEN_Msk (0x1ul << ACMP_CTL0_HYSEN_Pos)
24767 #define ACMP_CTL0_NEGSEL_Pos (4)
24768 #define ACMP_CTL0_NEGSEL_Msk (0x3ul << ACMP_CTL0_NEGSEL_Pos)
24770 #define ACMP_CTL0_WKEN_Pos (31)
24771 #define ACMP_CTL0_WKEN_Msk (0x1ul << ACMP_CTL0_WKEN_Pos)
24773 #define ACMP_STATUS_ACMPIF_Pos (0)
24774 #define ACMP_STATUS_ACMPIF_Msk (0x1ul << ACMP_STATUS_ACMPIF_Pos)
24776 #define ACMP_STATUS_ACMPO_Pos (1)
24777 #define ACMP_STATUS_ACMPO_Msk (0x1ul << ACMP_STATUS_ACMPO_Pos)
24779 #define ACMP_VREF_CRVCTL_Pos (0)
24780 #define ACMP_VREF_CRVCTL_Msk (0xful << ACMP_VREF_CRVCTL_Pos)
24782 #define ACMP_VREF_CRVEN_Pos (4)
24783 #define ACMP_VREF_CRVEN_Msk (0x1ul << ACMP_VREF_CRVEN_Pos)
24785 #define ACMP_VREF_CRVSSEL_Pos (5)
24786 #define ACMP_VREF_CRVSSEL_Msk (0x1ul << ACMP_VREF_CRVSSEL_Pos) /* ACMP_CONST */
24789 /* end of ACMP register group */
24790
24791
24792
24793 #if defined ( __CC_ARM )
24794 #pragma no_anon_unions
24795 #endif
24796
24802 #define FLASH_BASE ((uint32_t)0x00000000)
24803 #define SRAM_BASE ((uint32_t)0x20000000)
24804 #define APB1PERIPH_BASE ((uint32_t)0x40000000)
24805 #define APB2PERIPH_BASE ((uint32_t)0x40100000)
24806 #define AHBPERIPH_BASE ((uint32_t)0x50000000)
24807
24808
24810 #define WDT_BASE (APB1PERIPH_BASE + 0x04000)
24811 #define WWDT_BASE (APB1PERIPH_BASE + 0x04100)
24812 #define RTC_BASE (APB1PERIPH_BASE + 0x08000)
24813 #define TIMER0_BASE (APB1PERIPH_BASE + 0x10000)
24814 #define TIMER1_BASE (APB1PERIPH_BASE + 0x10100)
24815 #define I2C0_BASE (APB1PERIPH_BASE + 0x20000)
24816 #define SPI0_BASE (APB1PERIPH_BASE + 0x30000)
24817 #define SPI2_BASE (APB1PERIPH_BASE + 0xD0000)
24818 #define PWM0_BASE (APB1PERIPH_BASE + 0x40000)
24819 #define UART0_BASE (APB1PERIPH_BASE + 0x50000)
24820 #define LCD_BASE (APB1PERIPH_BASE + 0xB0000)
24821 #define ADC_BASE (APB1PERIPH_BASE + 0xE0000)
24822
24823 #define TIMER2_BASE (APB2PERIPH_BASE + 0x10000)
24824 #define TIMER3_BASE (APB2PERIPH_BASE + 0x10100)
24825 #define I2C1_BASE (APB2PERIPH_BASE + 0x20000)
24826 #define SPI1_BASE (APB2PERIPH_BASE + 0x30000)
24827 #define SPI3_BASE (APB2PERIPH_BASE + 0xE0000)
24828
24829 #define UART1_BASE (APB2PERIPH_BASE + 0x50000)
24830 #define SC0_BASE (APB2PERIPH_BASE + 0x90000)
24831 #define SC1_BASE (APB2PERIPH_BASE + 0xB0000)
24832 #define ACMP_BASE (APB2PERIPH_BASE + 0xD0000)
24833
24834 #define SYS_BASE (AHBPERIPH_BASE + 0x00000)
24835 #define CLK_BASE (AHBPERIPH_BASE + 0x00200)
24836 #define INTID_BASE (AHBPERIPH_BASE + 0x00300)
24837 #define GPIOA_BASE (AHBPERIPH_BASE + 0x04000)
24838 #define GPIOB_BASE (AHBPERIPH_BASE + 0x04040)
24839 #define GPIOC_BASE (AHBPERIPH_BASE + 0x04080)
24840 #define GPIOD_BASE (AHBPERIPH_BASE + 0x040C0)
24841 #define GPIOE_BASE (AHBPERIPH_BASE + 0x04100)
24842 #define GPIOF_BASE (AHBPERIPH_BASE + 0x04140)
24843 #define GPIODBNCE_BASE (AHBPERIPH_BASE + 0x04180)
24844 #define GPIO_PIN_DATA_BASE (AHBPERIPH_BASE + 0x04200)
24845 #define PDMA0_BASE (AHBPERIPH_BASE + 0x08000)
24846 #define PDMA1_BASE (AHBPERIPH_BASE + 0x08100)
24847 #define PDMA2_BASE (AHBPERIPH_BASE + 0x08200)
24848 #define PDMA3_BASE (AHBPERIPH_BASE + 0x08300)
24849 #define PDMA4_BASE (AHBPERIPH_BASE + 0x08400)
24850 #define PDMACRC_BASE (AHBPERIPH_BASE + 0x08E00)
24851 #define PDMAGCR_BASE (AHBPERIPH_BASE + 0x08F00)
24852 #define FMC_BASE (AHBPERIPH_BASE + 0x0C000)
24853
24854 /* end of group NANO103_PERIPHERAL_MEM_MAP */
24855
24856
24861 #define WDT ((WDT_T *) WDT_BASE)
24862 #define WWDT ((WWDT_T *) WWDT_BASE)
24863 #define RTC ((RTC_T *) RTC_BASE)
24864 #define TIMER0 ((TIMER_T *) TIMER0_BASE)
24865 #define TIMER1 ((TIMER_T *) TIMER1_BASE)
24866 #define TIMER2 ((TIMER_T *) TIMER2_BASE)
24867 #define TIMER3 ((TIMER_T *) TIMER3_BASE)
24868 #define I2C0 ((I2C_T *) I2C0_BASE)
24869 #define I2C1 ((I2C_T *) I2C1_BASE)
24870 #define SPI0 ((SPI_T *) SPI0_BASE)
24871 #define SPI1 ((SPI_T *) SPI1_BASE)
24872 #define SPI2 ((SPI_T *) SPI2_BASE)
24873 #define SPI3 ((SPI_T *) SPI3_BASE)
24874 #define PWM0 ((PWM_T *) PWM0_BASE)
24875 #define UART0 ((UART_T *) UART0_BASE)
24876 #define UART1 ((UART_T *) UART1_BASE)
24877 #define LCD ((LCD_T *) LCD_BASE)
24878 #define ADC ((ADC_T *) ADC_BASE)
24879 #define SC0 ((SC_T *) SC0_BASE)
24880 #define SC1 ((SC_T *) SC1_BASE)
24881 #define ACMP ((ACMP_T *) ACMP_BASE)
24882
24883 #define SYS ((SYS_T *) SYS_BASE)
24884 #define CLK ((CLK_T *) CLK_BASE)
24885 #define PA ((GPIO_T *) GPIOA_BASE)
24886 #define PB ((GPIO_T *) GPIOB_BASE)
24887 #define PC ((GPIO_T *) GPIOC_BASE)
24888 #define PD ((GPIO_T *) GPIOD_BASE)
24889 #define PE ((GPIO_T *) GPIOE_BASE)
24890 #define PF ((GPIO_T *) GPIOF_BASE)
24891 #define GPIO ((GP_DB_T *) GPIODBNCE_BASE)
24892 #define PDMA1 ((PDMA_CH_T *) PDMA1_BASE)
24893 #define PDMA2 ((PDMA_CH_T *) PDMA2_BASE)
24894 #define PDMA3 ((PDMA_CH_T *) PDMA3_BASE)
24895 #define PDMA4 ((PDMA_CH_T *) PDMA4_BASE)
24896 #define PDMACRC ((DMA_CRC_T *) PDMACRC_BASE)
24897 #define PDMAGCR ((DMA_GCR_T *) PDMAGCR_BASE)
24898 #define FMC ((FMC_T *) FMC_BASE)
24899
24900 /* end of group NANO103_PERIPHERAL_DECLARATION */
24901 /* end of group NANO103_Peripherals */
24903
24909 typedef volatile unsigned char vu8;
24910 typedef volatile unsigned short vu16;
24911 typedef volatile unsigned long vu32;
24912
24918 #define M8(addr) (*((vu8 *) (addr)))
24919
24926 #define M16(addr) (*((vu16 *) (addr)))
24927
24934 #define M32(addr) (*((vu32 *) (addr)))
24935
24943 #define outpw(port,value) *((volatile unsigned int *)(port)) = value
24944
24951 #define inpw(port) (*((volatile unsigned int *)(port)))
24952
24960 #define outps(port,value) *((volatile unsigned short *)(port)) = value
24961
24968 #define inps(port) (*((volatile unsigned short *)(port)))
24969
24976 #define outpb(port,value) *((volatile unsigned char *)(port)) = value
24977
24983 #define inpb(port) (*((volatile unsigned char *)(port)))
24984
24992 #define outp32(port,value) *((volatile unsigned int *)(port)) = value
24993
25000 #define inp32(port) (*((volatile unsigned int *)(port)))
25001
25009 #define outp16(port,value) *((volatile unsigned short *)(port)) = value
25010
25017 #define inp16(port) (*((volatile unsigned short *)(port)))
25018
25025 #define outp8(port,value) *((volatile unsigned char *)(port)) = value
25026
25032 #define inp8(port) (*((volatile unsigned char *)(port)))
25033 /* end of group NANO103_IO_ROUTINE */
25035
25036 /******************************************************************************/
25037 /* Legacy Constants */
25038 /******************************************************************************/
25044 #ifndef NULL
25045 #define NULL (0)
25046 #endif
25047
25048 #define TRUE (1)
25049 #define FALSE (0)
25050
25051 #define ENABLE (1)
25052 #define DISABLE (0)
25053
25054 /* Define one bit mask */
25055 #define BIT0 (0x00000001)
25056 #define BIT1 (0x00000002)
25057 #define BIT2 (0x00000004)
25058 #define BIT3 (0x00000008)
25059 #define BIT4 (0x00000010)
25060 #define BIT5 (0x00000020)
25061 #define BIT6 (0x00000040)
25062 #define BIT7 (0x00000080)
25063 #define BIT8 (0x00000100)
25064 #define BIT9 (0x00000200)
25065 #define BIT10 (0x00000400)
25066 #define BIT11 (0x00000800)
25067 #define BIT12 (0x00001000)
25068 #define BIT13 (0x00002000)
25069 #define BIT14 (0x00004000)
25070 #define BIT15 (0x00008000)
25071 #define BIT16 (0x00010000)
25072 #define BIT17 (0x00020000)
25073 #define BIT18 (0x00040000)
25074 #define BIT19 (0x00080000)
25075 #define BIT20 (0x00100000)
25076 #define BIT21 (0x00200000)
25077 #define BIT22 (0x00400000)
25078 #define BIT23 (0x00800000)
25079 #define BIT24 (0x01000000)
25080 #define BIT25 (0x02000000)
25081 #define BIT26 (0x04000000)
25082 #define BIT27 (0x08000000)
25083 #define BIT28 (0x10000000)
25084 #define BIT29 (0x20000000)
25085 #define BIT30 (0x40000000)
25086 #define BIT31 (0x80000000)
25087
25088 /* Byte Mask Definitions */
25089 #define BYTE0_Msk (0x000000FF)
25090 #define BYTE1_Msk (0x0000FF00)
25091 #define BYTE2_Msk (0x00FF0000)
25092 #define BYTE3_Msk (0xFF000000)
25093
25094 #define GET_BYTE0(u32Param) ((u32Param & BYTE0_Msk) )
25095 #define GET_BYTE1(u32Param) ((u32Param & BYTE1_Msk) >> 8)
25096 #define GET_BYTE2(u32Param) ((u32Param & BYTE2_Msk) >> 16)
25097 #define GET_BYTE3(u32Param) ((u32Param & BYTE3_Msk) >> 24)
25099 /* end of group NANO103_legacy_Constants */
25100 /* end of group NANO103_Definitions */
25102
25103 #ifdef __cplusplus
25104 }
25105 #endif
25106
25107
25108 /******************************************************************************/
25109 /* Peripheral header files */
25110 /******************************************************************************/
25111 #include "sys.h"
25112 #include "clk.h"
25113 #include "acmp.h"
25114 #include "adc.h"
25115 #include "fmc.h"
25116 #include "gpio.h"
25117 #include "i2c.h"
25118 #include "crc.h"
25119 #include "pdma.h"
25120 #include "pwm.h"
25121 #include "rtc.h"
25122 #include "sc.h"
25123 #include "scuart.h"
25124 #include "spi.h"
25125 #include "timer.h"
25126 #include "uart.h"
25127 #include "wdt.h"
25128 #include "wwdt.h"
25129
25130 #endif // __NANO103_H__
25131
25132 /*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/
25133
PWM_T::FCAPDAT1
__I uint32_t FCAPDAT1
Definition: Nano103.h:16881
ADC_T::CMP1
__IO uint32_t CMP1
Definition: Nano103.h:24391
RTC_T::LEAPYEAR
__I uint32_t LEAPYEAR
Definition: Nano103.h:18628
PDMA_IRQn
Definition: Nano103.h:113
RTC_T::INTEN
__IO uint32_t INTEN
Definition: Nano103.h:18629
INT_T::IRQ7_SRC
__I uint32_t IRQ7_SRC
Definition: Nano103.h:797
UART_T::ALTCTL
__IO uint32_t ALTCTL
Definition: Nano103.h:20117
PWM0_IRQn
Definition: Nano103.h:97
PWM_T::INTEN1
__IO uint32_t INTEN1
Definition: Nano103.h:16860
SYS_T::RPDBCLK
__IO uint32_t RPDBCLK
Definition: Nano103.h:3238
TIMER_T::CTL
__IO uint32_t CTL
Definition: Nano103.h:14227
FMC_T::ISPCTL
__IO uint32_t ISPCTL
Definition: Nano103.h:5857
INT_T::IRQ28_SRC
__I uint32_t IRQ28_SRC
Definition: Nano103.h:818
RTC_T
Definition: Nano103.h:17868
DMA_CRC_T
Definition: Nano103.h:12890
rtc.h
NANO103 series RTC driver header file.
SPI1_IRQn
Definition: Nano103.h:105
uart.h
NANO103 Series UART control header file.
INT_T::IRQ16_SRC
__I uint32_t IRQ16_SRC
Definition: Nano103.h:806
INT_T::IRQ31_SRC
__I uint32_t IRQ31_SRC
Definition: Nano103.h:821
TIMER_T::INTSTS
__IO uint32_t INTSTS
Definition: Nano103.h:14231
GPIO_T
Definition: Nano103.h:5998
PWM_T::CMPBUF5
__I uint32_t CMPBUF5
Definition: Nano103.h:16916
RTC_T::LXTOCTL
__IO uint32_t LXTOCTL
Definition: Nano103.h:18640
pwm.h
NANO103 series PWM driver header file.
PWM_T::BRKCTL2_3
__IO uint32_t BRKCTL2_3
Definition: Nano103.h:16854
DMA_CRC_T::CHECKSUM
__I uint32_t CHECKSUM
Definition: Nano103.h:13254
INT_T::IRQ17_SRC
__I uint32_t IRQ17_SRC
Definition: Nano103.h:807
UART1_IRQn
Definition: Nano103.h:103
SYS_T::GPB_MFPL
__IO uint32_t GPB_MFPL
Definition: Nano103.h:3190
SC_T
Definition: Nano103.h:20422
acmp.h
NANO103 series Analog Comparator(ACMP) driver header file.
DMA_GCR_T::GINTSTS
__I uint32_t GINTSTS
Definition: Nano103.h:13476
INT_T::IRQ30_SRC
__I uint32_t IRQ30_SRC
Definition: Nano103.h:820
SYS_T::GPE_MFPL
__IO uint32_t GPE_MFPL
Definition: Nano103.h:3196
SC_T::STATUS
__IO uint32_t STATUS
Definition: Nano103.h:21644
SC_T::INTSTS
__IO uint32_t INTSTS
Definition: Nano103.h:21643
CLK_T::CLKDIV0
__IO uint32_t CLKDIV0
Definition: Nano103.h:4908
WDT_IRQn
Definition: Nano103.h:92
ADC_T::CMP0
__IO uint32_t CMP0
Definition: Nano103.h:24390
PWM_T::RCAPDAT5
__I uint32_t RCAPDAT5
Definition: Nano103.h:16888
PWM_T::CMPBUF3
__I uint32_t CMPBUF3
Definition: Nano103.h:16914
INT_T::IRQ5_SRC
__I uint32_t IRQ5_SRC
Definition: Nano103.h:795
wwdt.h
NANO103 series WWDT driver header file.
SPI_T::SSCTL
__IO uint32_t SSCTL
Definition: Nano103.h:23396
PDMA_CH_T::TOCn
__IO uint32_t TOCn
Definition: Nano103.h:12884
PDMA_CH_T::INTSTSn
__IO uint32_t INTSTSn
Definition: Nano103.h:12883
FMC_T::KEY1
__O uint32_t KEY1
Definition: Nano103.h:5872
SC_T::CTL
__IO uint32_t CTL
Definition: Nano103.h:21637
SYS_T::RCCFCTL
__IO uint32_t RCCFCTL
Definition: Nano103.h:3184
SYS_T::TEMPCTL
__IO uint32_t TEMPCTL
Definition: Nano103.h:3180
PWM_T::INTEN0
__IO uint32_t INTEN0
Definition: Nano103.h:16859
WDT_T::INTEN
__IO uint32_t INTEN
Definition: Nano103.h:17628
SYS_T::IRC1TCTL
__IO uint32_t IRC1TCTL
Definition: Nano103.h:3222
ADC_T::CALCTL
__IO uint32_t CALCTL
Definition: Nano103.h:24398
INT_T::IRQ25_SRC
__I uint32_t IRQ25_SRC
Definition: Nano103.h:815
SYS_T::IRC0TCTL
__IO uint32_t IRC0TCTL
Definition: Nano103.h:3216
UART_T::WKUPSTS
__IO uint32_t WKUPSTS
Definition: Nano103.h:20121
ACMP_T::VREF
__IO uint32_t VREF
Definition: Nano103.h:24749
GPDEF_IRQn
Definition: Nano103.h:96
I2C_T::ADDRMSK0
__IO uint32_t ADDRMSK0
Definition: Nano103.h:22442
WWDT_T::INTEN
__IO uint32_t INTEN
Definition: Nano103.h:17820
INT_T::IRQ13_SRC
__I uint32_t IRQ13_SRC
Definition: Nano103.h:803
INT_T::IRQ12_SRC
__I uint32_t IRQ12_SRC
Definition: Nano103.h:802
I2C_T::CTL
__IO uint32_t CTL
Definition: Nano103.h:22431
PDMA_CH_T::CCNTn
__I uint32_t CCNTn
Definition: Nano103.h:12881
system_Nano103.h
Nano103 system clock definition file.
SYS_T::GPB_MFPH
__IO uint32_t GPB_MFPH
Definition: Nano103.h:3191
FMC_T::ISPTRG
__IO uint32_t ISPTRG
Definition: Nano103.h:5861
gpio.h
NANO103 series GPIO driver header file.
RTC_T::INTSTS
__IO uint32_t INTSTS
Definition: Nano103.h:18630
I2C1_IRQn
Definition: Nano103.h:109
INT_T::IRQ22_SRC
__I uint32_t IRQ22_SRC
Definition: Nano103.h:812
PWM_T::SWBRK
__O uint32_t SWBRK
Definition: Nano103.h:16858
RTC_T::CAL
__IO uint32_t CAL
Definition: Nano103.h:18623
CLK_T::CLKOCTL
__IO uint32_t CLKOCTL
Definition: Nano103.h:4911
CLK_T::CLKDIV1
__IO uint32_t CLKDIV1
Definition: Nano103.h:4909
SYS_T::GPC_MFPH
__IO uint32_t GPC_MFPH
Definition: Nano103.h:3193
I2C_T
Definition: Nano103.h:21966
DMA_CRC_T::DMABCNT
__IO uint32_t DMABCNT
Definition: Nano103.h:13238
UART_T::IRDA
__IO uint32_t IRDA
Definition: Nano103.h:20116
HardFault_IRQn
Definition: Nano103.h:85
TIMER_T::CAP
__I uint32_t CAP
Definition: Nano103.h:14233
SYS_T::BATDIVCTL
__IO uint32_t BATDIVCTL
Definition: Nano103.h:3211
RTC_T::SPRCTL
__IO uint32_t SPRCTL
Definition: Nano103.h:18634
SC_T::ACTCTL
__IO uint32_t ACTCTL
Definition: Nano103.h:21653
FMC_T::ISPSTS
__IO uint32_t ISPSTS
Definition: Nano103.h:5867
UART_T::TRSR
__IO uint32_t TRSR
Definition: Nano103.h:20108
SYS_T::GPD_MFPL
__IO uint32_t GPD_MFPL
Definition: Nano103.h:3194
SYS_T::IRC0TIEN
__IO uint32_t IRC0TIEN
Definition: Nano103.h:3217
GPIO_T::INTTYPE
__IO uint32_t INTTYPE
Definition: Nano103.h:11770
INT_T
Definition: Nano103.h:161
FMC_T::DFBA
__I uint32_t DFBA
Definition: Nano103.h:5862
PWM_T::CNTEN
__IO uint32_t CNTEN
Definition: Nano103.h:16824
ADC_T::EXTSMPT0
__IO uint32_t EXTSMPT0
Definition: Nano103.h:24400
WWDT_T::CTL
__IO uint32_t CTL
Definition: Nano103.h:17819
EINT1_IRQn
Definition: Nano103.h:94
RTC_T::CALM
__IO uint32_t CALM
Definition: Nano103.h:18627
GPIO_T::PUEN
__IO uint32_t PUEN
Definition: Nano103.h:11773
I2C0_IRQn
Definition: Nano103.h:108
PWM_T::CMPBUF0
__I uint32_t CMPBUF0
Definition: Nano103.h:16911
ADC_IRQn
Definition: Nano103.h:116
sys.h
NANO103 Series system control header file.
PWM_T::CLKSRC
__IO uint32_t CLKSRC
Definition: Nano103.h:16820
PWM_T::FCAPDAT3
__I uint32_t FCAPDAT3
Definition: Nano103.h:16885
PWM_T::RCAPDAT1
__I uint32_t RCAPDAT1
Definition: Nano103.h:16880
UART_T::BRCOMPAT
__IO uint32_t BRCOMPAT
Definition: Nano103.h:20119
DMA_GCR_T
Definition: Nano103.h:13260
INT_T::IRQ11_SRC
__I uint32_t IRQ11_SRC
Definition: Nano103.h:801
CKSD_IRQn
Definition: Nano103.h:112
SYS_T::MIRCTIEN
__IO uint32_t MIRCTIEN
Definition: Nano103.h:3229
CLK_T
Definition: Nano103.h:3740
SPI_T::PDMACTL
__IO uint32_t PDMACTL
Definition: Nano103.h:23407
CLK_T::STATUS
__I uint32_t STATUS
Definition: Nano103.h:4904
INT_T::IRQ0_SRC
__I uint32_t IRQ0_SRC
Definition: Nano103.h:790
PWM_T::FAILBRK
__IO uint32_t FAILBRK
Definition: Nano103.h:16852
I2C_T::ADDR0
__IO uint32_t ADDR0
Definition: Nano103.h:22437
RTC_T::CAMSK
__IO uint32_t CAMSK
Definition: Nano103.h:18633
INT_T::IRQ6_SRC
__I uint32_t IRQ6_SRC
Definition: Nano103.h:796
SC_T::TMRCTL1
__IO uint32_t TMRCTL1
Definition: Nano103.h:21647
DMA_GCR_T::REQSEL0
__IO uint32_t REQSEL0
Definition: Nano103.h:13474
crc.h
NANO103 series CRC driver header file.
FMC_T::KPCNT
__I uint32_t KPCNT
Definition: Nano103.h:5877
PWM_T::WGCTL0
__IO uint32_t WGCTL0
Definition: Nano103.h:16847
RTC_T::TIME
__IO uint32_t TIME
Definition: Nano103.h:18622
PWM_T::POEN
__IO uint32_t POEN
Definition: Nano103.h:16857
pdma.h
NANO103 series PDMA driver header file.
INT_T::IRQ27_SRC
__I uint32_t IRQ27_SRC
Definition: Nano103.h:817
INT_T::IRQ4_SRC
__I uint32_t IRQ4_SRC
Definition: Nano103.h:794
FMC_T::KEYSTS
__IO uint32_t KEYSTS
Definition: Nano103.h:5875
sc.h
NANO103 series Smartcard (SC) driver header file.
EINT0_IRQn
Definition: Nano103.h:93
ADC_T::EXTSMPT1
__IO uint32_t EXTSMPT1
Definition: Nano103.h:24401
GPIO_T::DINOFF
__IO uint32_t DINOFF
Definition: Nano103.h:11765
RTC_IRQn
Definition: Nano103.h:118
PWM_T::BNF
__IO uint32_t BNF
Definition: Nano103.h:16851
PDWU_IRQn
Definition: Nano103.h:115
TIMER_T::PRECNT
__IO uint32_t PRECNT
Definition: Nano103.h:14228
timer.h
NANO103 series TIMER driver header file.
I2C_T::STATUS2
__IO uint32_t STATUS2
Definition: Nano103.h:22448
CLK_T::CLKDSTS
__IO uint32_t CLKDSTS
Definition: Nano103.h:4919
TMR2_IRQn
Definition: Nano103.h:100
adc.h
NANO103 series ADC driver header file.
PWM_T::BRKCTL0_1
__IO uint32_t BRKCTL0_1
Definition: Nano103.h:16853
INT_T::NMI_SEL
__IO uint32_t NMI_SEL
Definition: Nano103.h:822
RTC_T::LXTICTL
__IO uint32_t LXTICTL
Definition: Nano103.h:18641
SPI_T
Definition: Nano103.h:22569
SPI_T::FIFOCTL
__IO uint32_t FIFOCTL
Definition: Nano103.h:23408
I2C_T::ADDRMSK1
__IO uint32_t ADDRMSK1
Definition: Nano103.h:22443
PDMA_CH_T
Definition: Nano103.h:12499
PDMA_CH_T::INTENn
__IO uint32_t INTENn
Definition: Nano103.h:12882
SPI_T::RX0
__I uint32_t RX0
Definition: Nano103.h:23397
UART_T::INTEN
__IO uint32_t INTEN
Definition: Nano103.h:20106
wdt.h
NANO103 series WDT driver header file.
SYS_T::MIRCTCTL
__IO uint32_t MIRCTCTL
Definition: Nano103.h:3228
CLK_T::PWRCTL
__IO uint32_t PWRCTL
Definition: Nano103.h:4901
PWM_T::ADCTS0
__IO uint32_t ADCTS0
Definition: Nano103.h:16866
SC_T::ETUCTL
__IO uint32_t ETUCTL
Definition: Nano103.h:21641
INT_T::IRQ29_SRC
__I uint32_t IRQ29_SRC
Definition: Nano103.h:819
PWM_T::CTL0
__IO uint32_t CTL0
Definition: Nano103.h:16815
PendSV_IRQn
Definition: Nano103.h:87
spi.h
NANO103 series SPI driver header file.
SC_T::EGT
__IO uint32_t EGT
Definition: Nano103.h:21639
ADC_T::CHEN
__IO uint32_t CHEN
Definition: Nano103.h:24389
GPABC_IRQn
Definition: Nano103.h:95
INT_T::IRQ14_SRC
__I uint32_t IRQ14_SRC
Definition: Nano103.h:804
PWM_T::CAPCTL
__IO uint32_t CAPCTL
Definition: Nano103.h:16876
SYS_T
Definition: Nano103.h:945
DMA_CRC_T::DAT
__IO uint32_t DAT
Definition: Nano103.h:13252
INT_T::IRQ8_SRC
__I uint32_t IRQ8_SRC
Definition: Nano103.h:798
INT_T::IRQ26_SRC
__I uint32_t IRQ26_SRC
Definition: Nano103.h:816
FMC_T::ISPDAT
__IO uint32_t ISPDAT
Definition: Nano103.h:5859
SPI_T::RX1
__I uint32_t RX1
Definition: Nano103.h:23398
PWM_T::ADCTS1
__IO uint32_t ADCTS1
Definition: Nano103.h:16867
GPIO_T::DATMSK
__IO uint32_t DATMSK
Definition: Nano103.h:11767
SYS_T::MIRCTISTS
__IO uint32_t MIRCTISTS
Definition: Nano103.h:3230
CLK_T::CLKSEL0
__IO uint32_t CLKSEL0
Definition: Nano103.h:4905
SPI_T::TX0
__O uint32_t TX0
Definition: Nano103.h:23402
SYS_T::IPRST2
__IO uint32_t IPRST2
Definition: Nano103.h:3172
CLK_T::CLKSEL1
__IO uint32_t CLKSEL1
Definition: Nano103.h:4906
SVCall_IRQn
Definition: Nano103.h:86
INT_T::IRQ23_SRC
__I uint32_t IRQ23_SRC
Definition: Nano103.h:813
SC_T::TMRCTL0
__IO uint32_t TMRCTL0
Definition: Nano103.h:21646
ADC_T::STATUS
__IO uint32_t STATUS
Definition: Nano103.h:24392
INT_T::IRQ19_SRC
__I uint32_t IRQ19_SRC
Definition: Nano103.h:809
RTC_T::WEEKDAY
__IO uint32_t WEEKDAY
Definition: Nano103.h:18625
vu8
volatile unsigned char vu8
Define 8-bit unsigned volatile data type.
Definition: Nano103.h:24909
scuart.h
SC_T::INTEN
__IO uint32_t INTEN
Definition: Nano103.h:21642
INT_T::IRQ20_SRC
__I uint32_t IRQ20_SRC
Definition: Nano103.h:810
WDT_T
Definition: Nano103.h:17454
TMR1_IRQn
Definition: Nano103.h:99
SYS_T::BODCTL
__IO uint32_t BODCTL
Definition: Nano103.h:3205
WWDT_T
Definition: Nano103.h:17681
ADC_T::CTL
__IO uint32_t CTL
Definition: Nano103.h:24388
CLK_T::WKINTSTS
__IO uint32_t WKINTSTS
Definition: Nano103.h:4915
CLK_T::CLKSEL2
__IO uint32_t CLKSEL2
Definition: Nano103.h:4907
SPI2_IRQn
Definition: Nano103.h:106
TIMER_T::CMP
__IO uint32_t CMP
Definition: Nano103.h:14229
GPIO_T::INTSRC
__IO uint32_t INTSRC
Definition: Nano103.h:11772
INT_T::IRQ24_SRC
__I uint32_t IRQ24_SRC
Definition: Nano103.h:814
PDMA_CH_T::SAn
__IO uint32_t SAn
Definition: Nano103.h:12873
UART_T::BAUD
__IO uint32_t BAUD
Definition: Nano103.h:20112
ACMP_T
Definition: Nano103.h:24621
SYS_T::PORCTL
__IO uint32_t PORCTL
Definition: Nano103.h:3204
WDT_T::CTL
__IO uint32_t CTL
Definition: Nano103.h:17627
PWM_T::STATUS
__IO uint32_t STATUS
Definition: Nano103.h:16871
SYS_T::IRC1TISTS
__IO uint32_t IRC1TISTS
Definition: Nano103.h:3224
fmc.h
NANO103 Series Flash Memory Controller Driver Header File.
PDMA_CH_T::CTLn
__IO uint32_t CTLn
Definition: Nano103.h:12872
SC_T::PINCTL
__IO uint32_t PINCTL
Definition: Nano103.h:21645
SC_T::TMRCTL2
__IO uint32_t TMRCTL2
Definition: Nano103.h:21648
UART_T::DAT
__IO uint32_t DAT
Definition: Nano103.h:20103
DMA_CRC_T::DMACSA
__I uint32_t DMACSA
Definition: Nano103.h:13242
PWM_T::MSK
__IO uint32_t MSK
Definition: Nano103.h:16850
SPI0_IRQn
Definition: Nano103.h:104
FMC_T::KEYTRG
__IO uint32_t KEYTRG
Definition: Nano103.h:5874
clk.h
NANO103 series CLK driver header file.
PWM_T::BRKCTL4_5
__IO uint32_t BRKCTL4_5
Definition: Nano103.h:16855
WWDT_T::CNT
__I uint32_t CNT
Definition: Nano103.h:17822
PWM_T::CLKPSC4_5
__IO uint32_t CLKPSC4_5
Definition: Nano103.h:16823
UART_T::INTSTS
__IO uint32_t INTSTS
Definition: Nano103.h:20107
WWDT_T::STATUS
__IO uint32_t STATUS
Definition: Nano103.h:17821
SYS_T::IPRST1
__IO uint32_t IPRST1
Definition: Nano103.h:3171
RTC_T::FREQADJ
__IO uint32_t FREQADJ
Definition: Nano103.h:18621
PWM_T::CNTCLR
__IO uint32_t CNTCLR
Definition: Nano103.h:16825
INT_T::IRQ3_SRC
__I uint32_t IRQ3_SRC
Definition: Nano103.h:793
CLK_T::PLLCTL
__IO uint32_t PLLCTL
Definition: Nano103.h:4910
SYS_T::IVREFCTL
__IO uint32_t IVREFCTL
Definition: Nano103.h:3209
PWM_T::DTCTL4_5
__IO uint32_t DTCTL4_5
Definition: Nano103.h:16839
PWM_T::DTCTL2_3
__IO uint32_t DTCTL2_3
Definition: Nano103.h:16838
SC1_IRQn
Definition: Nano103.h:111
DMA_GCR_T::REQSEL1
__IO uint32_t REQSEL1
Definition: Nano103.h:13475
I2C_T::INTSTS
__IO uint32_t INTSTS
Definition: Nano103.h:22432
SYS_T::IRC0TISTS
__IO uint32_t IRC0TISTS
Definition: Nano103.h:3218
RTC_T::TICK
__IO uint32_t TICK
Definition: Nano103.h:18631
DMA_CRC_T::CTL
__IO uint32_t CTL
Definition: Nano103.h:13233
GPIO_T::MODE
__IO uint32_t MODE
Definition: Nano103.h:11764
PWM_T::CLKPSC2_3
__IO uint32_t CLKPSC2_3
Definition: Nano103.h:16822
PWM_T::MSKEN
__IO uint32_t MSKEN
Definition: Nano103.h:16849
PWM_T::CAPINEN
__IO uint32_t CAPINEN
Definition: Nano103.h:16875
PDMA_CH_T::CDAn
__I uint32_t CDAn
Definition: Nano103.h:12880
I2C_T::STATUS
__I uint32_t STATUS
Definition: Nano103.h:22433
I2C_T::CTL2
__IO uint32_t CTL2
Definition: Nano103.h:22447
WWDT_T::RLDCNT
__O uint32_t RLDCNT
Definition: Nano103.h:17818
SC_T::ALTCTL
__IO uint32_t ALTCTL
Definition: Nano103.h:21638
INT_T::MCU_IRQ
__IO uint32_t MCU_IRQ
Definition: Nano103.h:823
NonMaskableInt_IRQn
Definition: Nano103.h:84
PWM_T::SELFTEST
__IO uint32_t SELFTEST
Definition: Nano103.h:16898
RTC_T::INIT
__IO uint32_t INIT
Definition: Nano103.h:18619
SC_T::DAT
__IO uint32_t DAT
Definition: Nano103.h:21636
DMA_CRC_T::SEED
__IO uint32_t SEED
Definition: Nano103.h:13253
FMC_T::ISPCMD
__IO uint32_t ISPCMD
Definition: Nano103.h:5860
ADC_T
Definition: Nano103.h:23603
SYS_T::RSTSTS
__IO uint32_t RSTSTS
Definition: Nano103.h:3170
UART_T::WKUPEN
__IO uint32_t WKUPEN
Definition: Nano103.h:20120
I2C_T::TOCTL
__IO uint32_t TOCTL
Definition: Nano103.h:22435
PWM_T::WGCTL1
__IO uint32_t WGCTL1
Definition: Nano103.h:16848
I2C_T::ADDR1
__IO uint32_t ADDR1
Definition: Nano103.h:22438
SYS_T::GPC_MFPL
__IO uint32_t GPC_MFPL
Definition: Nano103.h:3192
INT_T::IRQ15_SRC
__I uint32_t IRQ15_SRC
Definition: Nano103.h:805
UART0_IRQn
Definition: Nano103.h:102
SC0_IRQn
Definition: Nano103.h:110
SYS_T::IRC1TIEN
__IO uint32_t IRC1TIEN
Definition: Nano103.h:3223
UART_T::TOUT
__IO uint32_t TOUT
Definition: Nano103.h:20111
UART_T::LINE
__IO uint32_t LINE
Definition: Nano103.h:20105
vu32
volatile unsigned long vu32
Define 32-bit unsigned volatile data type.
Definition: Nano103.h:24911
SPI3_IRQn
Definition: Nano103.h:114
I2C_T::CLKDIV
__IO uint32_t CLKDIV
Definition: Nano103.h:22434
PWM_T::RCAPDAT4
__I uint32_t RCAPDAT4
Definition: Nano103.h:16886
SYS_T::GPD_MFPH
__IO uint32_t GPD_MFPH
Definition: Nano103.h:3195
PWM_T::CTL1
__IO uint32_t CTL1
Definition: Nano103.h:16816
FMC_T
Definition: Nano103.h:5233
INT_T::IRQ21_SRC
__I uint32_t IRQ21_SRC
Definition: Nano103.h:811
INT_T::IRQ9_SRC
__I uint32_t IRQ9_SRC
Definition: Nano103.h:799
DMA_CRC_T::DMASA
__IO uint32_t DMASA
Definition: Nano103.h:13234
TMR3_IRQn
Definition: Nano103.h:101
WDT_T::STATUS
__IO uint32_t STATUS
Definition: Nano103.h:17629
ACMP_T::CTL0
__IO uint32_t CTL0
Definition: Nano103.h:24747
FMC_T::FTCTL
__IO uint32_t FTCTL
Definition: Nano103.h:5863
SYS_T::PDID
__I uint32_t PDID
Definition: Nano103.h:3169
TMR0_IRQn
Definition: Nano103.h:98
PWM_T::POLCTL
__IO uint32_t POLCTL
Definition: Nano103.h:16856
TIMER_T
Definition: Nano103.h:13684
PWM_T::CMPBUF2
__I uint32_t CMPBUF2
Definition: Nano103.h:16913
PDMA_CH_T::CSAn
__I uint32_t CSAn
Definition: Nano103.h:12879
RTC_T::CLKFMT
__IO uint32_t CLKFMT
Definition: Nano103.h:18624
GPIO_T::INTSTS
__I uint32_t INTSTS
Definition: Nano103.h:11774
PWM_T::RCAPDAT0
__I uint32_t RCAPDAT0
Definition: Nano103.h:16878
TIMER_T::CNT
__IO uint32_t CNT
Definition: Nano103.h:14232
SYS_T::GPA_MFPL
__IO uint32_t GPA_MFPL
Definition: Nano103.h:3188
GPIO_T::DBEN
__IO uint32_t DBEN
Definition: Nano103.h:11769
CLK_T::CDUPB
__IO uint32_t CDUPB
Definition: Nano103.h:4920
PWM_T::FCAPDAT2
__I uint32_t FCAPDAT2
Definition: Nano103.h:16883
PWM_T::FCAPDAT0
__I uint32_t FCAPDAT0
Definition: Nano103.h:16879
FMC_T::KECNT
__I uint32_t KECNT
Definition: Nano103.h:5876
SC_T::UARTCTL
__IO uint32_t UARTCTL
Definition: Nano103.h:21649
PWM_T::PBUF2
__I uint32_t PBUF2
Definition: Nano103.h:16903
ACMP_T::STATUS
__IO uint32_t STATUS
Definition: Nano103.h:24748
RTC_T::TAMPCTL
__IO uint32_t TAMPCTL
Definition: Nano103.h:18642
SC_T::RXTOUT
__IO uint32_t RXTOUT
Definition: Nano103.h:21640
RTC_T::LXTCTL
__IO uint32_t LXTCTL
Definition: Nano103.h:18639
FMC_T::KEY2
__O uint32_t KEY2
Definition: Nano103.h:5873
SPI_T::CLKDIV
__IO uint32_t CLKDIV
Definition: Nano103.h:23395
GPIO_T::INTEN
__IO uint32_t INTEN
Definition: Nano103.h:11771
BOD_IRQn
Definition: Nano103.h:91
UART_T::CTRL
__IO uint32_t CTRL
Definition: Nano103.h:20104
IRQn
IRQn
Definition: Nano103.h:80
PWM_T::CMPBUF4
__I uint32_t CMPBUF4
Definition: Nano103.h:16915
HIRC_IRQn
Definition: Nano103.h:107
INT_T::IRQ10_SRC
__I uint32_t IRQ10_SRC
Definition: Nano103.h:800
TIMER_T::INTEN
__IO uint32_t INTEN
Definition: Nano103.h:14230
SysTick_IRQn
Definition: Nano103.h:88
CLK_T::CLKDCTL
__IO uint32_t CLKDCTL
Definition: Nano103.h:4917
PDMA_CH_T::CNTn
__IO uint32_t CNTn
Definition: Nano103.h:12875
FMC_T::ISPADDR
__IO uint32_t ISPADDR
Definition: Nano103.h:5858
RTC_T::TAMSK
__IO uint32_t TAMSK
Definition: Nano103.h:18632
UART_T
Definition: Nano103.h:18880
PWM_T::FCAPDAT5
__I uint32_t FCAPDAT5
Definition: Nano103.h:16889
RTC_T::RWEN
__IO uint32_t RWEN
Definition: Nano103.h:18620
SYS_T::REGLCTL
__O uint32_t REGLCTL
Definition: Nano103.h:3234
CLK_T::AHBCLK
__IO uint32_t AHBCLK
Definition: Nano103.h:4902
PWM_T::CLKPSC0_1
__IO uint32_t CLKPSC0_1
Definition: Nano103.h:16821
GPIO_T::DOUT
__IO uint32_t DOUT
Definition: Nano103.h:11766
UART_T::FUNCSEL
__IO uint32_t FUNCSEL
Definition: Nano103.h:20118
UART_T::MODEM
__IO uint32_t MODEM
Definition: Nano103.h:20110
PWM_T::CAPIEN
__IO uint32_t CAPIEN
Definition: Nano103.h:16893
SYS_T::LDOCTL
__IO uint32_t LDOCTL
Definition: Nano103.h:3210
GP_DB_T
Definition: Nano103.h:11778
DMA_GCR_T::GCTL
__IO uint32_t GCTL
Definition: Nano103.h:13473
SPI_T::STATUS
__IO uint32_t STATUS
Definition: Nano103.h:23394
INT_T::IRQ2_SRC
__I uint32_t IRQ2_SRC
Definition: Nano103.h:792
CLK_T::APBCLK
__IO uint32_t APBCLK
Definition: Nano103.h:4903
INT_T::IRQ18_SRC
__I uint32_t IRQ18_SRC
Definition: Nano103.h:808
DMA_CRC_T::DMAISTS
__IO uint32_t DMAISTS
Definition: Nano103.h:13248
RTC_T::TALM
__IO uint32_t TALM
Definition: Nano103.h:18626
PWM_T::CAPIF
__IO uint32_t CAPIF
Definition: Nano103.h:16894
PWM_T::CAPSTS
__I uint32_t CAPSTS
Definition: Nano103.h:16877
UART_T::FIFOSTS
__IO uint32_t FIFOSTS
Definition: Nano103.h:20109
PWM_T::RCAPDAT2
__I uint32_t RCAPDAT2
Definition: Nano103.h:16882
SPI_T::TX1
__O uint32_t TX1
Definition: Nano103.h:23403
PWM_T::PBUF0
__I uint32_t PBUF0
Definition: Nano103.h:16899
GPIO_T::PIN
__I uint32_t PIN
Definition: Nano103.h:11768
DMA_CRC_T::DMAINTEN
__IO uint32_t DMAINTEN
Definition: Nano103.h:13247
PWM_T::CMPBUF1
__I uint32_t CMPBUF1
Definition: Nano103.h:16912
SPI_T::CTL
__IO uint32_t CTL
Definition: Nano103.h:23393
ACMP_IRQn
Definition: Nano103.h:117
ADC_T::PDMA
__I uint32_t PDMA
Definition: Nano103.h:24396
PWM_T::PBUF4
__I uint32_t PBUF4
Definition: Nano103.h:16907
CLK_T::CLKDIE
__IO uint32_t CLKDIE
Definition: Nano103.h:4918
vu16
volatile unsigned short vu16
Define 16-bit unsigned volatile data type.
Definition: Nano103.h:24910
PWM_T::RCAPDAT3
__I uint32_t RCAPDAT3
Definition: Nano103.h:16884
PWM_T::DTCTL0_1
__IO uint32_t DTCTL0_1
Definition: Nano103.h:16837
DMA_CRC_T::DMACBCNT
__I uint32_t DMACBCNT
Definition: Nano103.h:13246
CLK_T::CDLOWB
__IO uint32_t CDLOWB
Definition: Nano103.h:4921
I2C_T::DAT
__IO uint32_t DAT
Definition: Nano103.h:22436
FMC_T::KEY0
__O uint32_t KEY0
Definition: Nano103.h:5871
PWM_T::INTSTS1
__IO uint32_t INTSTS1
Definition: Nano103.h:16862
ADC_T::PWD
__IO uint32_t PWD
Definition: Nano103.h:24397
TIMER_T::ECTL
__IO uint32_t ECTL
Definition: Nano103.h:14237
GP_DB_T::DBCTL
__IO uint32_t DBCTL
Definition: Nano103.h:11848
PWM_T::INTSTS0
__IO uint32_t INTSTS0
Definition: Nano103.h:16861
RTC_T::MISCCTL
__IO uint32_t MISCCTL
Definition: Nano103.h:18646
PWM_T::FCAPDAT4
__I uint32_t FCAPDAT4
Definition: Nano103.h:16887
CLK_T::APBDIV
__IO uint32_t APBDIV
Definition: Nano103.h:4916
PDMA_CH_T::DAn
__IO uint32_t DAn
Definition: Nano103.h:12874
SYS_T::MISCCTL
__IO uint32_t MISCCTL
Definition: Nano103.h:3176
SYS_T::WKSTS
__I uint32_t WKSTS
Definition: Nano103.h:3215
INT_T::IRQ1_SRC
__I uint32_t IRQ1_SRC
Definition: Nano103.h:791
ADC_T::CALWORD
__IO uint32_t CALWORD
Definition: Nano103.h:24399
SYS_T::GPF_MFPL
__IO uint32_t GPF_MFPL
Definition: Nano103.h:3200
IRQn_Type
enum IRQn IRQn_Type
i2c.h
NANO103 series I2C driver header file.
SYS_T::GPA_MFPH
__IO uint32_t GPA_MFPH
Definition: Nano103.h:3189
PWM_T
Definition: Nano103.h:14357