| Nano103 BSP V3.01.002 The Board Support Package for Nano103 Series

sys.h
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1 /**************************************************************************/
12 #ifndef __SYS_H__
13 #define __SYS_H__
14
15 #ifdef __cplusplus
16 extern "C"
17 {
18 #endif
19
32 /*---------------------------------------------------------------------------------------------------------*/
33 /* Module Reset Control Resister constant definitions. */
34 /*---------------------------------------------------------------------------------------------------------*/
35 #define CHIP_RST ((0x0<<24) | SYS_IPRST1_CHIPRST_Pos )
36 #define CPU_RST ((0x0<<24) | SYS_IPRST1_CPURST_Pos )
37 #define DMA_RST ((0x0<<24) | SYS_IPRST1_PDMARST_Pos )
38 #define SC1_RST ((0x4<<24) | SYS_IPRST2_SC1RST_Pos )
39 #define SC0_RST ((0x4<<24) | SYS_IPRST2_SC0RST_Pos )
40 #define ADC_RST ((0x4<<24) | SYS_IPRST2_ADCRST_Pos )
41 #define ACMP0_RST ((0x4<<24) | SYS_IPRST2_ACMP0RST_Pos )
42 #define PWM0_RST ((0x4<<24) | SYS_IPRST2_PWM0RST_Pos )
43 #define UART1_RST ((0x4<<24) | SYS_IPRST2_UART1RST_Pos )
44 #define UART0_RST ((0x4<<24) | SYS_IPRST2_UART0RST_Pos )
45 #define SPI3_RST ((0x4<<24) | SYS_IPRST2_SPI3RST_Pos )
46 #define SPI2_RST ((0x4<<24) | SYS_IPRST2_SPI2RST_Pos )
47 #define SPI1_RST ((0x4<<24) | SYS_IPRST2_SPI1RST_Pos )
48 #define SPI0_RST ((0x4<<24) | SYS_IPRST2_SPI0RST_Pos )
49 #define I2C1_RST ((0x4<<24) | SYS_IPRST2_I2C1RST_Pos )
50 #define I2C0_RST ((0x4<<24) | SYS_IPRST2_I2C0RST_Pos )
51 #define TMR3_RST ((0x4<<24) | SYS_IPRST2_TMR3RST_Pos )
52 #define TMR2_RST ((0x4<<24) | SYS_IPRST2_TMR2RST_Pos )
53 #define TMR1_RST ((0x4<<24) | SYS_IPRST2_TMR1RST_Pos )
54 #define TMR0_RST ((0x4<<24) | SYS_IPRST2_TMR0RST_Pos )
55 #define GPIO_RST ((0x4<<24) | SYS_IPRST2_GPIORST_Pos )
57 /*---------------------------------------------------------------------------------------------------------*/
58 /* Multi-Function constant definitions. */
59 /*---------------------------------------------------------------------------------------------------------*/
60
61
62 /********************** Brown Out Detector Threshold Voltage Selection constant definitions **********************/
63 #define SYS_BODCTL_BOD_RST_EN (1UL<<SYS_BODCTL_BODREN_Pos)
64 #define SYS_BODCTL_BOD_INTERRUPT_EN (1UL<<SYS_BODCTL_BODIE_Pos)
65 #define SYS_BODCTL_BODVL_1_7V (0UL<<SYS_BODCTL_BODVL_Pos)
66 #define SYS_BODCTL_BODVL_1_8V (1UL<<SYS_BODCTL_BODVL_Pos)
67 #define SYS_BODCTL_BODVL_1_9V (2UL<<SYS_BODCTL_BODVL_Pos)
68 #define SYS_BODCTL_BODVL_2_0V (3UL<<SYS_BODCTL_BODVL_Pos)
69 #define SYS_BODCTL_BODVL_2_1V (4UL<<SYS_BODCTL_BODVL_Pos)
70 #define SYS_BODCTL_BODVL_2_2V (5UL<<SYS_BODCTL_BODVL_Pos)
71 #define SYS_BODCTL_BODVL_2_3V (6UL<<SYS_BODCTL_BODVL_Pos)
72 #define SYS_BODCTL_BODVL_2_4V (7UL<<SYS_BODCTL_BODVL_Pos)
73 #define SYS_BODCTL_BODVL_2_5V (8UL<<SYS_BODCTL_BODVL_Pos)
74 #define SYS_BODCTL_BODVL_2_6V (9UL<<SYS_BODCTL_BODVL_Pos)
75 #define SYS_BODCTL_BODVL_2_7V (0xAUL<<SYS_BODCTL_BODVL_Pos)
76 #define SYS_BODCTL_BODVL_2_8V (0xBUL<<SYS_BODCTL_BODVL_Pos)
77 #define SYS_BODCTL_BODVL_2_9V (0xCUL<<SYS_BODCTL_BODVL_Pos)
78 #define SYS_BODCTL_BODVL_3_0V (0xDUL<<SYS_BODCTL_BODVL_Pos)
79 #define SYS_BODCTL_BODVL_3_1V (0xEUL<<SYS_BODCTL_BODVL_Pos)
81 /********************** Low Power Brown Out Detector Threshold Voltage Selection constant definitions **********************/
82 #define SYS_BODCTL_LPBOD_RST_EN (1UL<<SYS_BODCTL_LPBODREN_Pos)
83 #define SYS_BODCTL_LPBOD_INTERRUPT_EN (1UL<<SYS_BODCTL_LPBODIE_Pos)
84 #define SYS_BODCTL_LPBODVL_2_0V (0UL<<SYS_BODCTL_LPBODVL_Pos)
85 #define SYS_BODCTL_LPBODVL_2_5V (1UL<<SYS_BODCTL_LPBODVL_Pos)
87 /********************* Bit definition of IVREFCTL register **********************/
88 #define SYS_IVREFCTL_BGP_EN ((uint32_t)0x00000001)
89 #define SYS_IVREFCTL_REG_EN ((uint32_t)0x00000002)
90 #define SYS_IVREFCTL_SEL25 ((uint32_t)0x00000008)
91 #define SYS_IVREFCTL_SEL18 ((uint32_t)0x00000004)
92 #define SYS_IVREFCTL_SEL15 ((uint32_t)0x00000000)
93 #define SYS_IVREFCTL_EXTMODE ((uint32_t)0x00000010)
96 /********************* Bit definition of LDOCTL register **********************/
97 #define SYS_LDOCTL_LDO_LEVEL12 ((uint32_t)0x00000000)
98 #define SYS_LDOCTL_LDO_LEVEL16 ((uint32_t)0x00000004)
99 #define SYS_LDOCTL_LDO_LEVEL18 ((uint32_t)0x00000008)
102 /********************* Bit definition of IRC0TCTL/IRC1TCTL/MIRCTCTL register **********************/
103 #define SYS_IRC0TCTL_TRIM_11_0592M ((uint32_t)0x00000001)
104 #define SYS_IRC0TCTL_TRIM_12M ((uint32_t)0x00000002)
105 #define SYS_IRC0TCTL_TRIM_12_288M ((uint32_t)0x00000003)
106 #define SYS_IRC0TCTL_TRIM_16M ((uint32_t)0x00000004)
108 #define SYS_IRC1TCTL_TRIM_36M ((uint32_t)0x00000002)
109 #define SYS_MIRCTCTL_TRIM_4M ((uint32_t)0x00000002)
111 #define SYS_IRCTCTL_LOOP_4CLK ((uint32_t)0x00000000)
112 #define SYS_IRCTCTL_LOOP_8CLK ((uint32_t)0x00000010)
113 #define SYS_IRCTCTL_LOOP_16CLK ((uint32_t)0x00000020)
114 #define SYS_IRCTCTL_LOOP_32CLK ((uint32_t)0x00000030)
116 #define SYS_IRCTCTL_RETRY_64 ((uint32_t)0x00000000)
117 #define SYS_IRCTCTL_RETRY_128 ((uint32_t)0x00000040)
118 #define SYS_IRCTCTL_RETRY_256 ((uint32_t)0x00000080)
119 #define SYS_IRCTCTL_RETRY_512 ((uint32_t)0x000000C0)
121 #define SYS_IRCTCTL_CLKERR_STOP ((uint32_t)0x00000100)
123 /********************* Bit definition of IRC0TIEN/IRC1TIEN/MIRCTIEN register **********************/
124 #define SYS_IRCTIEN_DISABLE ((uint32_t)0x00000000)
125 #define SYS_IRCTIEN_FAIL_EN ((uint32_t)0x00000002)
126 #define SYS_IRCTIEN_32KERR_EN ((uint32_t)0x00000004)
128 /********************* Bit definition of IRC0TISTS/IRC1TISTS/MIRCTISTS register **********************/
129 #define SYS_IRCTISTS_FREQLOCK ((uint32_t)0x00000001)
130 #define SYS_IRCTISTS_FAIL_INT ((uint32_t)0x00000002)
131 #define SYS_IRCTISTS_32KERR_INT ((uint32_t)0x00000004)
133 /********************* Bit definition of GPA_MFPL register **********************/
134 #define SYS_GPA_MFPL_PA0MFP_GPIO (0x00UL<<SYS_GPA_MFPL_PA0MFP_Pos)
135 #define SYS_GPA_MFPL_PA0MFP_ADC_CH0 (0x01UL<<SYS_GPA_MFPL_PA0MFP_Pos)
136 #define SYS_GPA_MFPL_PA0MFP_ACMP0_P (0x02UL<<SYS_GPA_MFPL_PA0MFP_Pos)
137 #define SYS_GPA_MFPL_PA0MFP_TM2_EXT (0x03UL<<SYS_GPA_MFPL_PA0MFP_Pos)
138 #define SYS_GPA_MFPL_PA0MFP_PWM0_CH2 (0x05UL<<SYS_GPA_MFPL_PA0MFP_Pos)
139 #define SYS_GPA_MFPL_PA0MFP_SPI3_MOSI1 (0x06UL<<SYS_GPA_MFPL_PA0MFP_Pos)
140 #define SYS_GPA_MFPL_PA1MFP_GPIO (0x00UL<<SYS_GPA_MFPL_PA1MFP_Pos)
141 #define SYS_GPA_MFPL_PA1MFP_ADC_CH1 (0x01UL<<SYS_GPA_MFPL_PA1MFP_Pos)
142 #define SYS_GPA_MFPL_PA1MFP_ACMP0_N (0x02UL<<SYS_GPA_MFPL_PA1MFP_Pos)
143 #define SYS_GPA_MFPL_PA1MFP_SPI3_MISO1 (0x06UL<<SYS_GPA_MFPL_PA1MFP_Pos)
144 #define SYS_GPA_MFPL_PA2MFP_GPIO (0x00UL<<SYS_GPA_MFPL_PA2MFP_Pos)
145 #define SYS_GPA_MFPL_PA2MFP_ADC_CH2 (0x01UL<<SYS_GPA_MFPL_PA2MFP_Pos)
146 #define SYS_GPA_MFPL_PA2MFP_UART1_RXD (0x05UL<<SYS_GPA_MFPL_PA2MFP_Pos)
147 #define SYS_GPA_MFPL_PA3MFP_GPIO (0x00UL<<SYS_GPA_MFPL_PA3MFP_Pos)
148 #define SYS_GPA_MFPL_PA3MFP_ADC_CH3 (0x01UL<<SYS_GPA_MFPL_PA3MFP_Pos)
149 #define SYS_GPA_MFPL_PA3MFP_UART1_TXD (0x05UL<<SYS_GPA_MFPL_PA3MFP_Pos)
150 #define SYS_GPA_MFPL_PA3MFP_SPI3_MOSI0 (0x06UL<<SYS_GPA_MFPL_PA3MFP_Pos)
151 #define SYS_GPA_MFPL_PA4MFP_GPIO (0x00UL<<SYS_GPA_MFPL_PA4MFP_Pos)
152 #define SYS_GPA_MFPL_PA4MFP_ADC_CH4 (0x01UL<<SYS_GPA_MFPL_PA4MFP_Pos)
153 #define SYS_GPA_MFPL_PA4MFP_I2C0_SDA (0x05UL<<SYS_GPA_MFPL_PA4MFP_Pos)
154 #define SYS_GPA_MFPL_PA4MFP_SPI3_MISO0 (0x06UL<<SYS_GPA_MFPL_PA4MFP_Pos)
155 #define SYS_GPA_MFPL_PA5MFP_GPIO (0x00UL<<SYS_GPA_MFPL_PA5MFP_Pos)
156 #define SYS_GPA_MFPL_PA5MFP_ADC_CH5 (0x01UL<<SYS_GPA_MFPL_PA5MFP_Pos)
157 #define SYS_GPA_MFPL_PA5MFP_I2C0_SCL (0x05UL<<SYS_GPA_MFPL_PA5MFP_Pos)
158 #define SYS_GPA_MFPL_PA5MFP_SPI3_CLK (0x06UL<<SYS_GPA_MFPL_PA5MFP_Pos)
159 #define SYS_GPA_MFPL_PA6MFP_GPIO (0x00UL<<SYS_GPA_MFPL_PA6MFP_Pos)
160 #define SYS_GPA_MFPL_PA6MFP_ADC_CH6 (0x01UL<<SYS_GPA_MFPL_PA6MFP_Pos)
161 #define SYS_GPA_MFPL_PA6MFP_ACMP0_O (0x02UL<<SYS_GPA_MFPL_PA6MFP_Pos)
162 #define SYS_GPA_MFPL_PA6MFP_TM3_EXT (0x03UL<<SYS_GPA_MFPL_PA6MFP_Pos)
163 #define SYS_GPA_MFPL_PA6MFP_TM3_CNT (0x04UL<<SYS_GPA_MFPL_PA6MFP_Pos)
164 #define SYS_GPA_MFPL_PA6MFP_PWM0_CH3 (0x05UL<<SYS_GPA_MFPL_PA6MFP_Pos)
165 #define SYS_GPA_MFPL_PA6MFP_SPI3_SS0 (0x06UL<<SYS_GPA_MFPL_PA6MFP_Pos)
166 #define SYS_GPA_MFPL_PA6MFP_TM3_OUT (0x07UL<<SYS_GPA_MFPL_PA6MFP_Pos)
167 /********************* Bit definition of GPA_MFPH register **********************/
168 #define SYS_GPA_MFPH_PA8MFP_GPIO (0x00UL<<SYS_GPA_MFPH_PA8MFP_Pos)
169 #define SYS_GPA_MFPH_PA8MFP_I2C0_SDA (0x01UL<<SYS_GPA_MFPH_PA8MFP_Pos)
170 #define SYS_GPA_MFPH_PA8MFP_TM0_CNT (0x02UL<<SYS_GPA_MFPH_PA8MFP_Pos)
171 #define SYS_GPA_MFPH_PA8MFP_SC0_CLK (0x03UL<<SYS_GPA_MFPH_PA8MFP_Pos)
172 #define SYS_GPA_MFPH_PA8MFP_SPI2_SS0 (0x04UL<<SYS_GPA_MFPH_PA8MFP_Pos)
173 #define SYS_GPA_MFPH_PA8MFP_TM0_OUT (0x05UL<<SYS_GPA_MFPH_PA8MFP_Pos)
174 #define SYS_GPA_MFPH_PA8MFP_UART1_nCTS (0x06UL<<SYS_GPA_MFPH_PA8MFP_Pos)
175 #define SYS_GPA_MFPH_PA9MFP_GPIO (0x00UL<<SYS_GPA_MFPH_PA9MFP_Pos)
176 #define SYS_GPA_MFPH_PA9MFP_I2C0_SCL (0x01UL<<SYS_GPA_MFPH_PA9MFP_Pos)
177 #define SYS_GPA_MFPH_PA9MFP_TM1_CNT (0x02UL<<SYS_GPA_MFPH_PA9MFP_Pos)
178 #define SYS_GPA_MFPH_PA9MFP_SC0_DAT (0x03UL<<SYS_GPA_MFPH_PA9MFP_Pos)
179 #define SYS_GPA_MFPH_PA9MFP_SPI2_CLK (0x04UL<<SYS_GPA_MFPH_PA9MFP_Pos)
180 #define SYS_GPA_MFPH_PA9MFP_TM1_OUT (0x05UL<<SYS_GPA_MFPH_PA9MFP_Pos)
181 #define SYS_GPA_MFPH_PA9MFP_UART1_nRTS (0x06UL<<SYS_GPA_MFPH_PA9MFP_Pos)
182 #define SYS_GPA_MFPH_PA9MFP_SNOOPER (0x07UL<<SYS_GPA_MFPH_PA9MFP_Pos)
183 #define SYS_GPA_MFPH_PA10MFP_GPIO (0x00UL<<SYS_GPA_MFPH_PA10MFP_Pos)
184 #define SYS_GPA_MFPH_PA10MFP_I2C1_SDA (0x01UL<<SYS_GPA_MFPH_PA10MFP_Pos)
185 #define SYS_GPA_MFPH_PA10MFP_TM2_CNT (0x02UL<<SYS_GPA_MFPH_PA10MFP_Pos)
186 #define SYS_GPA_MFPH_PA10MFP_SC0_PWR (0x03UL<<SYS_GPA_MFPH_PA10MFP_Pos)
187 #define SYS_GPA_MFPH_PA10MFP_SPI2_MISO0 (0x04UL<<SYS_GPA_MFPH_PA10MFP_Pos)
188 #define SYS_GPA_MFPH_PA10MFP_TM2_OUT (0x05UL<<SYS_GPA_MFPH_PA10MFP_Pos)
189 #define SYS_GPA_MFPH_PA11MFP_GPIO (0x00UL<<SYS_GPA_MFPH_PA11MFP_Pos)
190 #define SYS_GPA_MFPH_PA11MFP_I2C1_SCL (0x01UL<<SYS_GPA_MFPH_PA11MFP_Pos)
191 #define SYS_GPA_MFPH_PA11MFP_TM3_CNT (0x02UL<<SYS_GPA_MFPH_PA11MFP_Pos)
192 #define SYS_GPA_MFPH_PA11MFP_SC0_RST (0x03UL<<SYS_GPA_MFPH_PA11MFP_Pos)
193 #define SYS_GPA_MFPH_PA11MFP_SPI2_MOSI0 (0x04UL<<SYS_GPA_MFPH_PA11MFP_Pos)
194 #define SYS_GPA_MFPH_PA11MFP_TM3_OUT (0x05UL<<SYS_GPA_MFPH_PA11MFP_Pos)
195 #define SYS_GPA_MFPH_PA12MFP_GPIO (0x00UL<<SYS_GPA_MFPH_PA12MFP_Pos)
196 #define SYS_GPA_MFPH_PA12MFP_PWM0_CH0 (0x01UL<<SYS_GPA_MFPH_PA12MFP_Pos)
197 #define SYS_GPA_MFPH_PA12MFP_TM0_EXT (0x03UL<<SYS_GPA_MFPH_PA12MFP_Pos)
198 #define SYS_GPA_MFPH_PA12MFP_I2C0_SDA (0x05UL<<SYS_GPA_MFPH_PA12MFP_Pos)
199 #define SYS_GPA_MFPH_PA13MFP_GPIO (0x00UL<<SYS_GPA_MFPH_PA13MFP_Pos)
200 #define SYS_GPA_MFPH_PA13MFP_PWM0_CH1 (0x01UL<<SYS_GPA_MFPH_PA13MFP_Pos)
201 #define SYS_GPA_MFPH_PA13MFP_TM1_EXT (0x03UL<<SYS_GPA_MFPH_PA13MFP_Pos)
202 #define SYS_GPA_MFPH_PA13MFP_I2C0_SCL (0x05UL<<SYS_GPA_MFPH_PA13MFP_Pos)
203 #define SYS_GPA_MFPH_PA14MFP_GPIO (0x00UL<<SYS_GPA_MFPH_PA14MFP_Pos)
204 #define SYS_GPA_MFPH_PA14MFP_PWM0_CH2 (0x01UL<<SYS_GPA_MFPH_PA14MFP_Pos)
205 #define SYS_GPA_MFPH_PA14MFP_I2C1_SDA (0x02UL<<SYS_GPA_MFPH_PA14MFP_Pos)
206 #define SYS_GPA_MFPH_PA14MFP_TM2_EXT (0x03UL<<SYS_GPA_MFPH_PA14MFP_Pos)
207 #define SYS_GPA_MFPH_PA14MFP_TM2_CNT (0x05UL<<SYS_GPA_MFPH_PA14MFP_Pos)
208 #define SYS_GPA_MFPH_PA14MFP_UART0_RXD (0x06UL<<SYS_GPA_MFPH_PA14MFP_Pos)
209 #define SYS_GPA_MFPH_PA14MFP_TM2_OUT (0x07UL<<SYS_GPA_MFPH_PA14MFP_Pos)
210 #define SYS_GPA_MFPH_PA15MFP_GPIO (0x00UL<<SYS_GPA_MFPH_PA15MFP_Pos)
211 #define SYS_GPA_MFPH_PA15MFP_PWM0_CH3 (0x01UL<<SYS_GPA_MFPH_PA15MFP_Pos)
212 #define SYS_GPA_MFPH_PA15MFP_I2C1_SCL (0x02UL<<SYS_GPA_MFPH_PA15MFP_Pos)
213 #define SYS_GPA_MFPH_PA15MFP_TM3_EXT (0x03UL<<SYS_GPA_MFPH_PA15MFP_Pos)
214 #define SYS_GPA_MFPH_PA15MFP_SC0_PWR (0x04UL<<SYS_GPA_MFPH_PA15MFP_Pos)
215 #define SYS_GPA_MFPH_PA15MFP_TM3_CNT (0x05UL<<SYS_GPA_MFPH_PA15MFP_Pos)
216 #define SYS_GPA_MFPH_PA15MFP_UART0_TXD (0x06UL<<SYS_GPA_MFPH_PA15MFP_Pos)
217 #define SYS_GPA_MFPH_PA15MFP_TM3_OUT (0x07UL<<SYS_GPA_MFPH_PA15MFP_Pos)
218 /********************* Bit definition of GPB_MFPL register **********************/
219 #define SYS_GPB_MFPL_PB0MFP_GPIO (0x00UL<<SYS_GPB_MFPL_PB0MFP_Pos)
220 #define SYS_GPB_MFPL_PB0MFP_UART0_RXD (0x01UL<<SYS_GPB_MFPL_PB0MFP_Pos)
221 #define SYS_GPB_MFPL_PB0MFP_SPI1_MOSI0 (0x03UL<<SYS_GPB_MFPL_PB0MFP_Pos)
222 #define SYS_GPB_MFPL_PB1MFP_GPIO (0x00UL<<SYS_GPB_MFPL_PB1MFP_Pos)
223 #define SYS_GPB_MFPL_PB1MFP_UART0_TXD (0x01UL<<SYS_GPB_MFPL_PB1MFP_Pos)
224 #define SYS_GPB_MFPL_PB1MFP_SPI1_MISO0 (0x03UL<<SYS_GPB_MFPL_PB1MFP_Pos)
225 #define SYS_GPB_MFPL_PB2MFP_GPIO (0x00UL<<SYS_GPB_MFPL_PB2MFP_Pos)
226 #define SYS_GPB_MFPL_PB2MFP_UART0_nRTS (0x01UL<<SYS_GPB_MFPL_PB2MFP_Pos)
227 #define SYS_GPB_MFPL_PB2MFP_SPI1_CLK (0x03UL<<SYS_GPB_MFPL_PB2MFP_Pos)
228 #define SYS_GPB_MFPL_PB2MFP_CLKO (0x04UL<<SYS_GPB_MFPL_PB2MFP_Pos)
229 #define SYS_GPB_MFPL_PB3MFP_GPIO (0x00UL<<SYS_GPB_MFPL_PB3MFP_Pos)
230 #define SYS_GPB_MFPL_PB3MFP_UART0_nCTS (0x01UL<<SYS_GPB_MFPL_PB3MFP_Pos)
231 #define SYS_GPB_MFPL_PB3MFP_SPI1_SS0 (0x03UL<<SYS_GPB_MFPL_PB3MFP_Pos)
232 #define SYS_GPB_MFPL_PB3MFP_SC1_CD (0x04UL<<SYS_GPB_MFPL_PB3MFP_Pos)
233 #define SYS_GPB_MFPL_PB4MFP_GPIO (0x00UL<<SYS_GPB_MFPL_PB4MFP_Pos)
234 #define SYS_GPB_MFPL_PB4MFP_UART1_RXD (0x01UL<<SYS_GPB_MFPL_PB4MFP_Pos)
235 #define SYS_GPB_MFPL_PB4MFP_SC0_CD (0x03UL<<SYS_GPB_MFPL_PB4MFP_Pos)
236 #define SYS_GPB_MFPL_PB4MFP_SPI2_SS0 (0x04UL<<SYS_GPB_MFPL_PB4MFP_Pos)
237 #define SYS_GPB_MFPL_PB4MFP_RTC_HZ (0x06UL<<SYS_GPB_MFPL_PB4MFP_Pos)
238 #define SYS_GPB_MFPL_PB5MFP_GPIO (0x00UL<<SYS_GPB_MFPL_PB5MFP_Pos)
239 #define SYS_GPB_MFPL_PB5MFP_UART1_TXD (0x01UL<<SYS_GPB_MFPL_PB5MFP_Pos)
240 #define SYS_GPB_MFPL_PB5MFP_SC0_RST (0x03UL<<SYS_GPB_MFPL_PB5MFP_Pos)
241 #define SYS_GPB_MFPL_PB5MFP_SPI2_CLK (0x04UL<<SYS_GPB_MFPL_PB5MFP_Pos)
242 #define SYS_GPB_MFPL_PB6MFP_GPIO (0x00UL<<SYS_GPB_MFPL_PB6MFP_Pos)
243 #define SYS_GPB_MFPL_PB6MFP_UART1_nRTS (0x01UL<<SYS_GPB_MFPL_PB6MFP_Pos)
244 #define SYS_GPB_MFPL_PB6MFP_SPI2_MISO0 (0x04UL<<SYS_GPB_MFPL_PB6MFP_Pos)
245 #define SYS_GPB_MFPL_PB7MFP_GPIO (0x00UL<<SYS_GPB_MFPL_PB7MFP_Pos)
246 #define SYS_GPB_MFPL_PB7MFP_UART1_nCTS (0x01UL<<SYS_GPB_MFPL_PB7MFP_Pos)
247 #define SYS_GPB_MFPL_PB7MFP_SPI2_MOSI0 (0x04UL<<SYS_GPB_MFPL_PB7MFP_Pos)
248 /********************* Bit definition of GPB_MFPH register **********************/
249 #define SYS_GPB_MFPH_PB8MFP_GPIO (0x00UL<<SYS_GPB_MFPH_PB8MFP_Pos)
250 #define SYS_GPB_MFPH_PB8MFP_STADC (0x01UL<<SYS_GPB_MFPH_PB8MFP_Pos)
251 #define SYS_GPB_MFPH_PB8MFP_TM0_CNT (0x02UL<<SYS_GPB_MFPH_PB8MFP_Pos)
252 #define SYS_GPB_MFPH_PB8MFP_INT0 (0x03UL<<SYS_GPB_MFPH_PB8MFP_Pos)
253 #define SYS_GPB_MFPH_PB8MFP_TM0_OUT (0x04UL<<SYS_GPB_MFPH_PB8MFP_Pos)
254 #define SYS_GPB_MFPH_PB8MFP_SNOOPER (0x07UL<<SYS_GPB_MFPH_PB8MFP_Pos)
255 #define SYS_GPB_MFPH_PB9MFP_GPIO (0x00UL<<SYS_GPB_MFPH_PB9MFP_Pos)
256 #define SYS_GPB_MFPH_PB9MFP_SPI1_SS1 (0x01UL<<SYS_GPB_MFPH_PB9MFP_Pos)
257 #define SYS_GPB_MFPH_PB9MFP_TM1_CNT (0x02UL<<SYS_GPB_MFPH_PB9MFP_Pos)
258 #define SYS_GPB_MFPH_PB9MFP_TM1_OUT (0x04UL<<SYS_GPB_MFPH_PB9MFP_Pos)
259 #define SYS_GPB_MFPH_PB9MFP_INT0 (0x05UL<<SYS_GPB_MFPH_PB9MFP_Pos)
260 #define SYS_GPB_MFPH_PB10MFP_GPIO (0x00UL<<SYS_GPB_MFPH_PB10MFP_Pos)
261 #define SYS_GPB_MFPH_PB10MFP_SPI0_MOSI0 (0x01UL<<SYS_GPB_MFPH_PB10MFP_Pos)
262 #define SYS_GPB_MFPH_PB10MFP_TM2_CNT (0x02UL<<SYS_GPB_MFPH_PB10MFP_Pos)
263 #define SYS_GPB_MFPH_PB10MFP_TM2_OUT (0x04UL<<SYS_GPB_MFPH_PB10MFP_Pos)
264 #define SYS_GPB_MFPH_PB10MFP_SPI0_SS1 (0x05UL<<SYS_GPB_MFPH_PB10MFP_Pos)
265 #define SYS_GPB_MFPH_PB11MFP_GPIO (0x00UL<<SYS_GPB_MFPH_PB11MFP_Pos)
266 #define SYS_GPB_MFPH_PB11MFP_PWM0_CH4 (0x01UL<<SYS_GPB_MFPH_PB11MFP_Pos)
267 #define SYS_GPB_MFPH_PB11MFP_TM3_CNT (0x02UL<<SYS_GPB_MFPH_PB11MFP_Pos)
268 #define SYS_GPB_MFPH_PB11MFP_TM3_OUT (0x04UL<<SYS_GPB_MFPH_PB11MFP_Pos)
269 #define SYS_GPB_MFPH_PB11MFP_SPI0_MISO0 (0x05UL<<SYS_GPB_MFPH_PB11MFP_Pos)
270 #define SYS_GPB_MFPH_PB13MFP_GPIO (0x00UL<<SYS_GPB_MFPH_PB13MFP_Pos)
271 #define SYS_GPB_MFPH_PB13MFP_SPI2_MISO1 (0x03UL<<SYS_GPB_MFPH_PB13MFP_Pos)
272 #define SYS_GPB_MFPH_PB13MFP_SNOOPER (0x07UL<<SYS_GPB_MFPH_PB13MFP_Pos)
273 #define SYS_GPB_MFPH_PB14MFP_GPIO (0x00UL<<SYS_GPB_MFPH_PB14MFP_Pos)
274 #define SYS_GPB_MFPH_PB14MFP_INT0 (0x01UL<<SYS_GPB_MFPH_PB14MFP_Pos)
275 #define SYS_GPB_MFPH_PB14MFP_SPI2_MOSI1 (0x03UL<<SYS_GPB_MFPH_PB14MFP_Pos)
276 #define SYS_GPB_MFPH_PB14MFP_SPI2_SS1 (0x04UL<<SYS_GPB_MFPH_PB14MFP_Pos)
277 #define SYS_GPB_MFPH_PB15MFP_GPIO (0x00UL<<SYS_GPB_MFPH_PB15MFP_Pos)
278 #define SYS_GPB_MFPH_PB15MFP_INT1 (0x01UL<<SYS_GPB_MFPH_PB15MFP_Pos)
279 #define SYS_GPB_MFPH_PB15MFP_SNOOPER (0x03UL<<SYS_GPB_MFPH_PB15MFP_Pos)
280 #define SYS_GPB_MFPH_PB15MFP_SC1_CD (0x04UL<<SYS_GPB_MFPH_PB15MFP_Pos)
281 /********************* Bit definition of GPC_MFPL register **********************/
282 #define SYS_GPC_MFPL_PC0MFP_GPIO (0x00UL<<SYS_GPC_MFPL_PC0MFP_Pos)
283 #define SYS_GPC_MFPL_PC0MFP_SPI0_SS0 (0x01UL<<SYS_GPC_MFPL_PC0MFP_Pos)
284 #define SYS_GPC_MFPL_PC0MFP_SC1_CLK (0x04UL<<SYS_GPC_MFPL_PC0MFP_Pos)
285 #define SYS_GPC_MFPL_PC0MFP_PWM0_BRAKE1 (0x05UL<<SYS_GPC_MFPL_PC0MFP_Pos)
286 #define SYS_GPC_MFPL_PC1MFP_GPIO (0x00UL<<SYS_GPC_MFPL_PC1MFP_Pos)
287 #define SYS_GPC_MFPL_PC1MFP_SPI0_CLK (0x01UL<<SYS_GPC_MFPL_PC1MFP_Pos)
288 #define SYS_GPC_MFPL_PC1MFP_SC1_DAT (0x04UL<<SYS_GPC_MFPL_PC1MFP_Pos)
289 #define SYS_GPC_MFPL_PC1MFP_PWM0_BRAKE0 (0x05UL<<SYS_GPC_MFPL_PC1MFP_Pos)
290 #define SYS_GPC_MFPL_PC2MFP_GPIO (0x00UL<<SYS_GPC_MFPL_PC2MFP_Pos)
291 #define SYS_GPC_MFPL_PC2MFP_SPI0_MISO0 (0x01UL<<SYS_GPC_MFPL_PC2MFP_Pos)
292 #define SYS_GPC_MFPL_PC2MFP_SC1_PWR (0x04UL<<SYS_GPC_MFPL_PC2MFP_Pos)
293 #define SYS_GPC_MFPL_PC2MFP_PWM0_BRAKE1 (0x05UL<<SYS_GPC_MFPL_PC2MFP_Pos)
294 #define SYS_GPC_MFPL_PC3MFP_GPIO (0x00UL<<SYS_GPC_MFPL_PC3MFP_Pos)
295 #define SYS_GPC_MFPL_PC3MFP_SPI0_MOSI0 (0x01UL<<SYS_GPC_MFPL_PC3MFP_Pos)
296 #define SYS_GPC_MFPL_PC3MFP_SC1_RST (0x04UL<<SYS_GPC_MFPL_PC3MFP_Pos)
297 #define SYS_GPC_MFPL_PC3MFP_PWM0_BRAKE0 (0x05UL<<SYS_GPC_MFPL_PC3MFP_Pos)
298 #define SYS_GPC_MFPL_PC6MFP_GPIO (0x00UL<<SYS_GPC_MFPL_PC6MFP_Pos)
299 #define SYS_GPC_MFPL_PC6MFP_UART1_RXD (0x01UL<<SYS_GPC_MFPL_PC6MFP_Pos)
300 #define SYS_GPC_MFPL_PC6MFP_TM0_EXT (0x03UL<<SYS_GPC_MFPL_PC6MFP_Pos)
301 #define SYS_GPC_MFPL_PC6MFP_SC1_CD (0x04UL<<SYS_GPC_MFPL_PC6MFP_Pos)
302 #define SYS_GPC_MFPL_PC6MFP_PWM0_CH0 (0x05UL<<SYS_GPC_MFPL_PC6MFP_Pos)
303 #define SYS_GPC_MFPL_PC7MFP_GPIO (0x00UL<<SYS_GPC_MFPL_PC7MFP_Pos)
304 #define SYS_GPC_MFPL_PC7MFP_UART1_TXD (0x01UL<<SYS_GPC_MFPL_PC7MFP_Pos)
305 #define SYS_GPC_MFPL_PC7MFP_ADC_CH7 (0x02UL<<SYS_GPC_MFPL_PC7MFP_Pos)
306 #define SYS_GPC_MFPL_PC7MFP_TM1_EXT (0x03UL<<SYS_GPC_MFPL_PC7MFP_Pos)
307 #define SYS_GPC_MFPL_PC7MFP_PWM0_CH1 (0x05UL<<SYS_GPC_MFPL_PC7MFP_Pos)
308 /********************* Bit definition of GPC_MFPH register **********************/
309 #define SYS_GPC_MFPH_PC8MFP_GPIO (0x00UL<<SYS_GPC_MFPH_PC8MFP_Pos)
310 #define SYS_GPC_MFPH_PC8MFP_SPI1_SS0 (0x01UL<<SYS_GPC_MFPH_PC8MFP_Pos)
311 #define SYS_GPC_MFPH_PC8MFP_I2C1_SDA (0x05UL<<SYS_GPC_MFPH_PC8MFP_Pos)
312 #define SYS_GPC_MFPH_PC9MFP_GPIO (0x00UL<<SYS_GPC_MFPH_PC9MFP_Pos)
313 #define SYS_GPC_MFPH_PC9MFP_SPI1_CLK (0x01UL<<SYS_GPC_MFPH_PC9MFP_Pos)
314 #define SYS_GPC_MFPH_PC9MFP_I2C1_SCL (0x05UL<<SYS_GPC_MFPH_PC9MFP_Pos)
315 #define SYS_GPC_MFPH_PC10MFP_GPIO (0x00UL<<SYS_GPC_MFPH_PC10MFP_Pos)
316 #define SYS_GPC_MFPH_PC10MFP_SPI1_MISO0 (0x01UL<<SYS_GPC_MFPH_PC10MFP_Pos)
317 #define SYS_GPC_MFPH_PC10MFP_UART1_RXD (0x05UL<<SYS_GPC_MFPH_PC10MFP_Pos)
318 #define SYS_GPC_MFPH_PC11MFP_GPIO (0x00UL<<SYS_GPC_MFPH_PC11MFP_Pos)
319 #define SYS_GPC_MFPH_PC11MFP_SPI1_MOSI0 (0x01UL<<SYS_GPC_MFPH_PC11MFP_Pos)
320 #define SYS_GPC_MFPH_PC11MFP_UART1_TXD (0x05UL<<SYS_GPC_MFPH_PC11MFP_Pos)
321 #define SYS_GPC_MFPH_PC14MFP_GPIO (0x00UL<<SYS_GPC_MFPH_PC14MFP_Pos)
322 #define SYS_GPC_MFPH_PC14MFP_UART1_nCTS (0x01UL<<SYS_GPC_MFPH_PC14MFP_Pos)
323 #define SYS_GPC_MFPH_PC15MFP_GPIO (0x00UL<<SYS_GPC_MFPH_PC15MFP_Pos)
324 #define SYS_GPC_MFPH_PC15MFP_UART1_nRTS (0x01UL<<SYS_GPC_MFPH_PC15MFP_Pos)
325 #define SYS_GPC_MFPH_PC15MFP_TM0_EXT (0x03UL<<SYS_GPC_MFPH_PC15MFP_Pos)
326 /********************* Bit definition of GPD_MFPL register **********************/
327 #define SYS_GPD_MFPL_PD6MFP_GPIO (0x00UL<<SYS_GPD_MFPL_PD6MFP_Pos)
328 #define SYS_GPD_MFPL_PD6MFP_SPI1_MOSI1 (0x03UL<<SYS_GPD_MFPL_PD6MFP_Pos)
329 #define SYS_GPD_MFPL_PD6MFP_SC1_RST (0x04UL<<SYS_GPD_MFPL_PD6MFP_Pos)
330 #define SYS_GPD_MFPL_PD7MFP_GPIO (0x00UL<<SYS_GPD_MFPL_PD7MFP_Pos)
331 #define SYS_GPD_MFPL_PD7MFP_SPI1_MISO1 (0x03UL<<SYS_GPD_MFPL_PD7MFP_Pos)
332 #define SYS_GPD_MFPL_PD7MFP_SC1_PWR (0x04UL<<SYS_GPD_MFPL_PD7MFP_Pos)
333 /********************* Bit definition of GPD_MFPH register **********************/
334 #define SYS_GPD_MFPH_PD14MFP_GPIO (0x00UL<<SYS_GPD_MFPH_PD14MFP_Pos)
335 #define SYS_GPD_MFPH_PD14MFP_SPI0_MOSI1 (0x01UL<<SYS_GPD_MFPH_PD14MFP_Pos)
336 #define SYS_GPD_MFPH_PD14MFP_SC1_DAT (0x04UL<<SYS_GPD_MFPH_PD14MFP_Pos)
337 #define SYS_GPD_MFPH_PD15MFP_GPIO (0x00UL<<SYS_GPD_MFPH_PD15MFP_Pos)
338 #define SYS_GPD_MFPH_PD15MFP_SPI0_MISO1 (0x01UL<<SYS_GPD_MFPH_PD15MFP_Pos)
339 #define SYS_GPD_MFPH_PD15MFP_SC1_CLK (0x04UL<<SYS_GPD_MFPH_PD15MFP_Pos)
340 /********************* Bit definition of GPE_MFPL register **********************/
341 #define SYS_GPE_MFPL_PE5MFP_GPIO (0x00UL<<SYS_GPE_MFPL_PE5MFP_Pos)
342 #define SYS_GPE_MFPL_PE5MFP_PWM0_CH5 (0x01UL<<SYS_GPE_MFPL_PE5MFP_Pos)
343 #define SYS_GPE_MFPL_PE5MFP_RTC_HZ (0x06UL<<SYS_GPE_MFPL_PE5MFP_Pos)
344 /********************* Bit definition of GPF_MFPL register **********************/
345 #define SYS_GPF_MFPL_PF0MFP_GPIO (0x00UL<<SYS_GPF_MFPL_PF0MFP_Pos)
346 #define SYS_GPF_MFPL_PF0MFP_INT0 (0x05UL<<SYS_GPF_MFPL_PF0MFP_Pos)
347 #define SYS_GPF_MFPL_PF0MFP_ICE_DAT (0x07UL<<SYS_GPF_MFPL_PF0MFP_Pos)
348 #define SYS_GPF_MFPL_PF1MFP_GPIO (0x00UL<<SYS_GPF_MFPL_PF1MFP_Pos)
349 #define SYS_GPF_MFPL_PF1MFP_CLKO (0x04UL<<SYS_GPF_MFPL_PF1MFP_Pos)
350 #define SYS_GPF_MFPL_PF1MFP_INT1 (0x05UL<<SYS_GPF_MFPL_PF1MFP_Pos)
351 #define SYS_GPF_MFPL_PF1MFP_ICE_CLK (0x07UL<<SYS_GPF_MFPL_PF1MFP_Pos)
352 #define SYS_GPF_MFPL_PF2MFP_GPIO (0x00UL<<SYS_GPF_MFPL_PF2MFP_Pos)
353 #define SYS_GPF_MFPL_PF2MFP_XT1_OUT (0x07UL<<SYS_GPF_MFPL_PF2MFP_Pos)
354 #define SYS_GPF_MFPL_PF3MFP_GPIO (0x00UL<<SYS_GPF_MFPL_PF3MFP_Pos)
355 #define SYS_GPF_MFPL_PF3MFP_XT1_IN (0x07UL<<SYS_GPF_MFPL_PF3MFP_Pos)
356 #define SYS_GPF_MFPL_PF6MFP_GPIO (0x00UL<<SYS_GPF_MFPL_PF6MFP_Pos)
357 #define SYS_GPF_MFPL_PF6MFP_I2C1_SDA (0x01UL<<SYS_GPF_MFPL_PF6MFP_Pos)
358 #define SYS_GPF_MFPL_PF6MFP_X32_OUT (0x07UL<<SYS_GPF_MFPL_PF6MFP_Pos)
359 #define SYS_GPF_MFPL_PF7MFP_GPIO (0x00UL<<SYS_GPF_MFPL_PF7MFP_Pos)
360 #define SYS_GPF_MFPL_PF7MFP_I2C1_SCL (0x01UL<<SYS_GPF_MFPL_PF7MFP_Pos)
361 #define SYS_GPF_MFPL_PF7MFP_SC0_CD (0x03UL<<SYS_GPF_MFPL_PF7MFP_Pos)
362 #define SYS_GPF_MFPL_PF7MFP_X32_IN (0x07UL<<SYS_GPF_MFPL_PF7MFP_Pos)
364 /* end of group NANO103_SYS_EXPORTED_CONSTANTS */
365
375 #define SYS_CLEAR_BOD_INT_FLAG() (SYS->BODCTL |= SYS_BODCTL_BODIF_Msk)
376
384 #define SYS_GET_BOD_INT_FLAG() (SYS->BODCTL & SYS_BODCTL_BODIF_Msk)
385
392 #define SYS_ENABLE_BOD() (SYS->BODCTL |= SYS_BODCTL_BODEN_Msk)
393
400 #define SYS_DISABLE_BOD() (SYS->BODCTL &= ~SYS_BODCTL_BODEN_Msk)
401
408 #define SYS_ENABLE_LPBOD() (SYS->BODCTL |= SYS_BODCTL_LPBODEN_Msk)
409
416 #define SYS_DISABLE_LPBOD() (SYS->BODCTL &= ~SYS_BODCTL_LPBODEN_Msk)
417
426 #define SYS_GET_BOD_OUTPUT() (SYS->BODCTL & SYS_BODCTL_BODOUT_Msk)
427
434 #define SYS_DISABLE_BOD_RST() (SYS->BODCTL &= ~SYS_BODCTL_BODREN_Msk)
435
442 #define SYS_ENABLE_BOD_RST() (SYS->BODCTL |= SYS_BODCTL_BODREN_Msk)
443
450 #define SYS_DISABLE_LPBOD_RST() (SYS->BODCTL &= ~SYS_BODCTL_LPBODREN_Msk)
451
458 #define SYS_ENABLE_LPBOD_RST() (SYS->BODCTL |= SYS_BODCTL_LPBODREN_Msk)
459
482 #define SYS_SET_BOD_LEVEL(u32Level) (SYS->BODCTL = (SYS->BODCTL & ~SYS_BODCTL_BODVL_Msk) | (u32Level))
483
491 #define SYS_IS_BOD_RST() (SYS->RSTSTS & SYS_RSTSTS_BODRF_Msk)
492
500 #define SYS_IS_LVR_RST() (SYS->RSTSTS & SYS_RSTSTS_LVRF_Msk)
501
509 #define SYS_IS_CPU_RST() (SYS->RSTSTS & SYS_RSTSTS_CPURF_Msk)
510
511
519 #define SYS_IS_LOCKUP_RST() (SYS->RSTSTS & SYS_RSTSTS_LOCKRF_Msk)
520
528 #define SYS_IS_POR_RST() (SYS->RSTSTS & SYS_RSTSTS_PORF_Msk)
529
537 #define SYS_IS_RSTPIN_RST() (SYS->RSTSTS & SYS_RSTSTS_PINRF_Msk)
538
546 #define SYS_IS_SYSTEM_RST() (SYS->RSTSTS & SYS_RSTSTS_SYSRF_Msk)
547
548
556 #define SYS_IS_WDT_RST() (SYS->RSTSTS & SYS_RSTSTS_WDTRF_Msk)
557
565 #define SYS_DISABLE_LVR() (SYS->BODCTL &= ~SYS_BODCTL_LVREN_Msk)
566
574 #define SYS_ENABLE_LVR() (SYS->BODCTL |= SYS_BODCTL_LVREN_Msk)
575
582 #define SYS_DISABLE_POR() do{SYS->PORCTL = 0x5AA5;SYS->MISCCTL = SYS_MISCCTL_POR33DIS_Msk | SYS_MISCCTL_POR18DIS_Msk;}while(0)
583
590 #define SYS_ENABLE_POR() do{SYS->PORCTL = 0;SYS->MISCCTL = 0;}while(0)
591
606 #define SYS_CLEAR_RST_SOURCE(u32RstSrc) (SYS->RSTSTS |= u32RstSrc)
607
615 __STATIC_INLINE void SYS_UnlockReg(void)
616 {
617 while(SYS->REGLCTL != SYS_REGLCTL_REGLCTL_Msk)
618 {
619 SYS->REGLCTL = 0x59;
620 SYS->REGLCTL = 0x16;
621 SYS->REGLCTL = 0x88;
622 }
623 }
624
632 __STATIC_INLINE void SYS_LockReg(void)
633 {
634 SYS->REGLCTL = 0;
635 }
636
645 #define SYS_GET_IRC0TRIM_INT_FLAG() (SYS->IRC0TISTS)
646
655 #define SYS_CLEAR_IRC0TRIM_INT_FLAG(u32IRCTrimFlg) (SYS->IRC0TISTS = u32IRCTrimFlg)
656
665 #define SYS_GET_IRC1TRIM_INT_FLAG() (SYS->IRC1TISTS)
666
675 #define SYS_CLEAR_IRC1TRIM_INT_FLAG(u32IRCTrimFlg) (SYS->IRC1TISTS = u32IRCTrimFlg)
676
685 #define SYS_GET_MIRCTRIM_INT_FLAG() (SYS->MIRCTISTS)
686
695 #define SYS_CLEAR_MIRCTRIM_INT_FLAG(u32IRCTrimFlg) (SYS->MIRCTISTS = u32IRCTrimFlg)
696
697 void SYS_ClearResetSrc(uint32_t u32Src);
698 uint32_t SYS_GetBODStatus(void);
699 uint32_t SYS_GetResetSrc(void);
700 uint32_t SYS_IsRegLocked(void);
701 void SYS_LockReg(void);
702 void SYS_UnlockReg(void);
703 uint32_t SYS_ReadPDID(void);
704 void SYS_ResetChip(void);
705 void SYS_ResetCPU(void);
706 void SYS_ResetModule(uint32_t u32ModuleIndex);
707 void SYS_EnableBOD(int32_t i32Mode, uint32_t u32BODLevel);
708 void SYS_DisableBOD(void);
709 void SYS_EnableLPBOD(int32_t i32Mode, uint32_t u32BODLevel);
710 void SYS_DisableLPBOD(void);
711 void SYS_EnableHIRC0Trim(uint32_t u32TrimSel,uint32_t u32TrimEnInt);
712 void SYS_DisableHIRC0Trim(void);
713 void SYS_EnableHIRC1Trim(uint32_t u32TrimSel,uint32_t u32TrimEnInt);
714 void SYS_DisableHIRC1Trim(void);
715 void SYS_EnableMIRCTrim(uint32_t u32TrimSel,uint32_t u32TrimEnInt);
716 void SYS_DisableMIRCTrim(void); /* end of group NANO103_SYS_EXPORTED_FUNCTIONS */
718 /* end of group NANO103_SYS_Driver */
720 /* end of group NANO103_Device_Driver */
722
723 #ifdef __cplusplus
724 }
725 #endif
726
727 #endif //__SYS_H__
728
729 /*** (C) COPYRIGHT 2015 Nuvoton Technology Corp. ***/
SYS_GetResetSrc
uint32_t SYS_GetResetSrc(void)
This function get the system reset source register value.
Definition: sys.c:63
SYS_UnlockReg
__STATIC_INLINE void SYS_UnlockReg(void)
Disable register write-protection function.
Definition: sys.h:615
SYS_LockReg
__STATIC_INLINE void SYS_LockReg(void)
Enable register write-protection function.
Definition: sys.h:632
SYS_ReadPDID
uint32_t SYS_ReadPDID(void)
This function get product ID.
Definition: sys.c:84
SYS_DisableHIRC1Trim
void SYS_DisableHIRC1Trim(void)
This function disable HIRC1 trim function.
Definition: sys.c:258
SYS_DisableLPBOD
void SYS_DisableLPBOD(void)
This function disable Low Power BOD function.
Definition: sys.c:203
SYS_IsRegLocked
uint32_t SYS_IsRegLocked(void)
This function check register write-protection bit setting.
Definition: sys.c:74
SYS_REGLCTL_REGLCTL_Msk
#define SYS_REGLCTL_REGLCTL_Msk
Definition: Nano103.h:3725
SYS_EnableBOD
void SYS_EnableBOD(int32_t i32Mode, uint32_t u32BODLevel)
This function configure Normal BOD function. Configure BOD reset or interrupt mode and set Brown-out ...
Definition: sys.c:166
SYS_EnableHIRC1Trim
void SYS_EnableHIRC1Trim(uint32_t u32TrimSel, uint32_t u32TrimEnInt)
This function enable HIRC1 trim function.
Definition: sys.c:247
SYS_EnableHIRC0Trim
void SYS_EnableHIRC0Trim(uint32_t u32TrimSel, uint32_t u32TrimEnInt)
This function enable HIRC0 trim function.
Definition: sys.c:221
SYS_EnableMIRCTrim
void SYS_EnableMIRCTrim(uint32_t u32TrimSel, uint32_t u32TrimEnInt)
This function enable MIRC trim function.
Definition: sys.c:273
SYS_DisableHIRC0Trim
void SYS_DisableHIRC0Trim(void)
This function disable HIRC0 trim function.
Definition: sys.c:232
SYS_DisableBOD
void SYS_DisableBOD(void)
This function disable Normal BOD function.
Definition: sys.c:176
SYS_ResetCPU
void SYS_ResetCPU(void)
This function reset CPU.
Definition: sys.c:104
SYS_ClearResetSrc
void SYS_ClearResetSrc(uint32_t u32Src)
Clear reset source.
Definition: sys.c:41
SYS_ResetChip
void SYS_ResetChip(void)
This function reset chip.
Definition: sys.c:94
SYS
#define SYS
Pointer to SYS register structure.
Definition: Nano103.h:24883
SYS_ResetModule
void SYS_ResetModule(uint32_t u32ModuleIndex)
This function reset selected modules.
Definition: sys.c:135
SYS_EnableLPBOD
void SYS_EnableLPBOD(int32_t i32Mode, uint32_t u32BODLevel)
This function configure Low Power BOD function only valid in Power Down mode. Configure Low Power BOD...
Definition: sys.c:193
SYS_GetBODStatus
uint32_t SYS_GetBODStatus(void)
Get Brown-out detector output status.
Definition: sys.c:53
SYS_DisableMIRCTrim
void SYS_DisableMIRCTrim(void)
This function disable HIRC0 trim function.
Definition: sys.c:284