Nano103 BSP  V3.01.002
The Board Support Package for Nano103 Series
system_Nano103.c
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1 /****************************************************************************/
13 #include <stdint.h>
14 #include "Nano103.h"
15 
16 
17 /*----------------------------------------------------------------------------
18  Clock Variable definitions
19  *----------------------------------------------------------------------------*/
20 uint32_t SystemCoreClock = __HSI;
21 uint32_t CyclesPerUs = (__HSI / 1000000);
28 uint32_t SysGet_PLLClockFreq(void)
29 {
30  uint32_t u32Freq =0, u32PLLSrc;
31  uint32_t u32SRC_N,u32PLL_M,u32PllReg;
32 
33  u32PllReg = CLK->PLLCTL;
34 
35  if (u32PllReg & CLK_PLLCTL_PD)
36  return 0; /* PLL is in power down mode */
37 
39  {
40  u32PLLSrc = __HXT;
41  }
42  else if((u32PllReg & CLK_PLLCTL_PLLSRC_Msk) == CLK_PLLCTL_PLL_SRC_HIRC)
43  {
44  /* HIRC Source Selection */
45  if(CLK->CLKSEL0 & CLK_CLKSEL0_HIRCSEL_Msk)
46  {
47  /* Clock source from HIRC1 (36MHz) */
48  u32PLLSrc =__HIRC36M;
49  }
50  else
51  {
52  /* Clock source from HIRC0 (12MHz) */
53  if(CLK->PWRCTL & CLK_PWRCTL_HIRC0FSEL_Msk)
54  u32PLLSrc =__HIRC16M;
55  else
56  u32PLLSrc =__HIRC12M;
57  }
58  }
59  else
60  {
61  u32PLLSrc =__MIRC;
62  }
63 
64  u32SRC_N = (u32PllReg & CLK_PLLCTL_INDIV_Msk) >> CLK_PLLCTL_INDIV_Pos;
65  u32PLL_M = (u32PllReg & CLK_PLLCTL_PLLMLP_Msk) >> CLK_PLLCTL_PLLMLP_Pos;
66 
67  u32Freq = u32PLLSrc * u32PLL_M / (u32SRC_N+1);
68 
69  return u32Freq;
70 }
71 
72 
78 uint32_t SysGet_HCLKFreq(void)
79 {
80 
81  uint32_t u32Freqout, u32AHBDivider, u32ClkSel;
82 
83  u32ClkSel = CLK->CLKSEL0 & CLK_CLKSEL0_HCLKSEL_Msk;
84 
85  if (u32ClkSel == CLK_CLKSEL0_HCLKSEL_HXT) /* external HXT crystal clock */
86  {
87  u32Freqout = __HXT;
88  }
89  else if(u32ClkSel == CLK_CLKSEL0_HCLKSEL_LXT) /* external LXT crystal clock */
90  {
91  u32Freqout = __LXT;
92  }
93  else if(u32ClkSel == CLK_CLKSEL0_HCLKSEL_PLL) /* PLL clock */
94  {
95  u32Freqout = SysGet_PLLClockFreq();
96  }
97  else if(u32ClkSel == CLK_CLKSEL0_HCLKSEL_LIRC) /* internal LIRC oscillator clock */
98  {
99  u32Freqout = __LIRC;
100  }
101  else if(u32ClkSel == CLK_CLKSEL0_HCLKSEL_HIRC) /* internal HIRC oscillator clock */
102  {
103  /* HIRC Source Selection */
104  if(CLK->CLKSEL0 & CLK_CLKSEL0_HIRCSEL_Msk)
105  {
106  /* Clock source from HIRC1 (36MHz) */
107  u32Freqout =__HIRC36M;
108  }
109  else
110  {
111  /* Clock source from HIRC0 (12MHz) */
113  u32Freqout =__HIRC16M;
114  else
115  u32Freqout =__HIRC12M;
116  }
117  }
118  else /* internal MIRC oscillator clock */
119  {
120  u32Freqout = __MIRC;
121  }
122  u32AHBDivider = (CLK->CLKDIV0 & CLK_CLKDIV0_HCLKDIV_Msk) + 1 ;
123  return (u32Freqout/u32AHBDivider);
124 }
125 
126 
135 {
136 
138  CyclesPerUs = (SystemCoreClock + 500000) / 1000000;
139 }
140 
148 void SystemInit (void)
149 {
150 
151  CLK->APBCLK |= CLK_APBCLK_RTCCKEN_Msk;
152  RTC->RWEN = RTC_WRITE_KEY;
153  // RTC->MISCCTL = SYS->RPDBCLK will enable PA9 in 32-pin package and do nothing on other packages
154  // Other arithmetic is for adjust LXT gain level.
155  RTC->MISCCTL = ((SYS->RPDBCLK | RTC_MISCCTL_GAINSEL_Msk) & ~0x00FF0000) | 0x00B00000;
156  CLK->APBCLK &= ~CLK_APBCLK_RTCCKEN_Msk;
157 }
158 
159 /*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/
#define CLK_PLLCTL_PLLMLP_Msk
Definition: Nano103.h:5158
void SystemInit(void)
Support PA9 in 32-pin package and adjust LXT gain level. Should call with register protection disable...
#define CLK_PWRCTL_HIRC0FSEL_Msk
Definition: Nano103.h:4957
#define __HXT
#define RTC_MISCCTL_GAINSEL_Msk
Definition: Nano103.h:18868
#define CLK_CLKSEL0_HCLKSEL_PLL
Definition: clk.h:140
#define CLK_PLLCTL_PLL_SRC_HIRC
Definition: clk.h:101
uint32_t SystemCoreClock
#define CLK_CLKSEL0_HCLKSEL_HXT
Definition: clk.h:138
#define __HIRC16M
#define CLK_PLLCTL_PLL_SRC_HXT
Definition: clk.h:100
uint32_t SysGet_PLLClockFreq(void)
Calculate current PLL clock frequency.
#define CLK_CLKSEL0_HCLKSEL_LIRC
Definition: clk.h:141
#define __LXT
#define RTC
Pointer to RTC register structure.
Definition: Nano103.h:24863
#define RTC_WRITE_KEY
Definition: rtc.h:36
#define CLK_PLLCTL_PD
Definition: clk.h:99
#define CLK_CLKSEL0_HCLKSEL_LXT
Definition: clk.h:139
#define CLK_CLKSEL0_HCLKSEL_Msk
Definition: Nano103.h:5068
#define __LIRC
uint32_t SysGet_HCLKFreq(void)
Get current HCLK clock frequency.
#define CLK_PLLCTL_INDIV_Pos
Definition: Nano103.h:5160
void SystemCoreClockUpdate(void)
This function is used to update the variable SystemCoreClock and must be called whenever the core clo...
#define __MIRC
#define CLK_CLKDIV0_HCLKDIV_Msk
Definition: Nano103.h:5128
#define CLK_PLLCTL_PLLSRC_Msk
Definition: Nano103.h:5170
NANO103 peripheral access layer header file. This file contains all the peripheral register's definit...
#define __HIRC36M
#define CLK_CLKSEL0_HIRCSEL_Msk
Definition: Nano103.h:5071
uint32_t CyclesPerUs
#define __HIRC12M
#define CLK_CLKSEL0_HCLKSEL_HIRC
Definition: clk.h:142
#define CLK
Pointer to CLK register structure.
Definition: Nano103.h:24884
#define SYS
Pointer to SYS register structure.
Definition: Nano103.h:24883
#define CLK_PLLCTL_INDIV_Msk
Definition: Nano103.h:5161
#define __HSI
#define CLK_PLLCTL_PLLMLP_Pos
Definition: Nano103.h:5157
#define CLK_APBCLK_RTCCKEN_Msk
Definition: Nano103.h:4987