Nano103 BSP  V3.01.002
The Board Support Package for Nano103 Series
Data Fields
WWDT_T Struct Reference

#include <Nano103.h>

Data Fields

__O uint32_t RLDCNT
 
__IO uint32_t CTL
 
__IO uint32_t INTEN
 
__IO uint32_t STATUS
 
__I uint32_t CNT
 

Detailed Description

@addtogroup WWDT Window Watchdog Timer(WWDT)
Memory Mapped Structure for WWDT Controller

Definition at line 17681 of file Nano103.h.

Field Documentation

◆ CNT

WWDT_T::CNT

[0x0010] Window Watchdog Timer Counter Value Register

CNT

Offset: 0x10 Window Watchdog Timer Counter Value Register

BitsFieldDescriptions
[5:0]WWDT_VAL
WWDT Counter Value
This register reflects the current counter value of window watchdog.

Definition at line 17822 of file Nano103.h.

◆ CTL

WWDT_T::CTL

[0x0004] Window Watchdog Timer Control Register

CTL

Offset: 0x04 Window Watchdog Timer Control Register

BitsFieldDescriptions
[0]WWDTEN
Window Watchdog Enable Bit
Set this bit to enable Window Watchdog timer.
0 = Window Watchdog timer function Disabled.
1 = Window Watchdog timer function Enabled.
[11:8]PERIODSEL
WWDT Pre-scale Period Select
These three bits select the pre-scale for the WWDT counter period.
Please refer toTable 6.12-1 WWDT Prescaler Value Selection.
[21:16]WINCMP
WWDT Window Compare Bits
Set this register to adjust the valid reload window.
Note: WWDTRLD register can only be written when WWDT counter value between 0 and WINCMP, otherwise WWDT will generate RESET signal.
[31]DBGEN
WWDT Debug Enable Bit
0 = WWDT stopped count if system is in Debug mode.
1 = WWDT still counted even system is in Debug mode.

Definition at line 17819 of file Nano103.h.

◆ INTEN

WWDT_T::INTEN

[0x0008] Window Watchdog Timer Interrupt Enable Register

INTEN

Offset: 0x08 Window Watchdog Timer Interrupt Enable Register

BitsFieldDescriptions
[0]WWDTIE
WWDT Interrupt Enable Bit
Setting this bit will enable the Window Watchdog timer interrupt function.
0 = Watchdog timer interrupt function Disabled.
1 = Watchdog timer interrupt function Enabled.

Definition at line 17820 of file Nano103.h.

◆ RLDCNT

WWDT_T::RLDCNT

[0x0000] Window Watchdog Timer Reload Counter Register

RLDCNT

Offset: 0x00 Window Watchdog Timer Reload Counter Register

BitsFieldDescriptions
[31:0]WWDT_RLD
Window Watchdog Timer Reload Counter Register
Writing 0x00005AA5 to this register will reload the Window Watchdog Timer counter value to 0x3F.
Note: This register can only be written when WWDT counter value between 0 and WINCMP, otherwise WWDT will generate RESET signal.

Definition at line 17818 of file Nano103.h.

◆ STATUS

WWDT_T::STATUS

[0x000c] Window Watchdog Timer Status Register

STATUS

Offset: 0x0C Window Watchdog Timer Status Register

BitsFieldDescriptions
[0]WWDTIF
WWDT Compare Match Interrupt Flag
When WWCMP matches the WWDT counter, this bit is set to 1
This bit can be cleared by writing '1' to it.
[1]WWDTRF
WWDT Reset Flag
When the WWDT counter down counts to 0 or writes WWDTRLD during WWDT counter larger than WINCMP, chip will be reset and this bit is set to 1
This bit can be cleared by writing '1' to it.

Definition at line 17821 of file Nano103.h.


The documentation for this struct was generated from the following file: