| Nano103 BSP V3.01.002 The Board Support Package for Nano103 Series

Data Fields
DMA_CRC_T Struct Reference

`#include <Nano103.h>`

## Data Fields
__IO uint32_t | CTL
__IO uint32_t | DMASA
__IO uint32_t | DMABCNT
__I uint32_t | DMACSA
__I uint32_t | DMACBCNT
__IO uint32_t | DMAINTEN
__IO uint32_t | DMAISTS
__IO uint32_t | DAT
__IO uint32_t | SEED
__I uint32_t | CHECKSUM

## Detailed Description

Definition at line 12890 of file Nano103.h.

## Field Documentation

## ◆ CHECKSUM

DMA_CRC_T::CHECKSUM

[0x0088] CRC Checksum Register

CHECKSUM

Offset: 0x88 CRC Checksum Register

Bits | Field | Descriptions
[31:0] | CHECKSUM | CRC Checksum Results This field indicates the CRC checksum result

Definition at line 13254 of file Nano103.h.

## ◆ CTL

DMA_CRC_T::CTL

[0x0000] CRC Control Register

CTL

Offset: 0x00 CRC Control Register

Bits | Field | Descriptions
[0] | CRCEN | CRC Channel Enable Bit 0 = No effect. 1 = CRC operation Enabled. When operating in CRC DMA mode (TRIGEN (CRC_CTL[23]) = 1), if user clears this bit, the PDMA operation will be continuous until all CRC DMA operation is done, and the TRIGEN bit will keep 1 until all CRC DMA operation done But in this case, the CRCTDIF (CRC_DMAINTSTS[1]) flag will be inactive, user can read CRC checksum result only if TRIGEN clears to 0 When operating in CRC DMA mode (TRIGEN (CRC_CTL[23]) = 1), if user wants to stop the transfer immediately, user can write 1 to CRCRST (CRC_CTL[1]) bit to stop the transmission.
[1] | CRCRST | CRC Engine Reset Bit 0 = No effect. 1 = Reset the internal CRC state machine and internal buffer The others contents of CRC_CTL register will not be cleared. Note1: This bit will be cleared automatically. Note2: When operating in CPU mode, setting this bit will reload the seed value from CRC_SEED register as checksum initial value.
[23] | TRIGEN | Trigger Enable Bit This bit is used to trigger the CRC DMA transfer. 0 = No effect. 1 = CRC DMA data read or write transfer Enabled. Note1: If this bit asserts which indicates the CRC engine operation in CRC DMA mode, do not fill in any data in CRC_DAT register. Note2: When CRC DMA transfer completed, this bit will be cleared automatically. Note3: If the bus error occurs when CRC DMA transfer data, all CRC DMA transfer will be stopped User must reset all DMA channel before trigger DMA again.
[24] | DATREV | Write Data Bit Order Reverse This bit is used to enable the bit order reverse function for writing data value in CRC_DTA register. 0 = Bit order reverse for CRC data write in Disabled. 1 = Bit order reverse for CRC data write in Enabled (per byte). Note: If the write data is 0xAABBCCDD, the bit order reverse for CRC data write in is 0x55DD33BB.
[25] | CHKSREV | Checksum Bit Order Reverse This bit is used to enable the bit order reverse function for checksum result in CRC_CHECKSUM register. 0 = Bit order reverse for CRC checksum Disabled. 1 = Bit order reverse for CRC checksum Enabled. Note: If the checksum result is 0XDD7B0F2E, the bit order reverse for CRC checksum is 0x74F0DEBB
[26] | DATFMT | Write Data 1's Complement This bit is used to enable the 1's complement function for write data value in CRC_DTA register. 0 = 1's complement for CRC writes data in Disabled. 1 = 1's complement for CRC writes data in Enabled.
[27] | CHKSFMT | Checksum 1's Complement This bit is used to enable the 1's complement function for checksum result in CRC_CHECKSUM register. 0 = 1's complement for CRC checksum Disabled. 1 = 1's complement for CRC checksum Enabled.
[29:28] | DATLEN | CPU Write Data Length This field indicates the CPU write data length only when operating in CPU mode. 00 = The write data length is 8-bit mode. 01 = The write data length is 16-bit mode. 10 = The write data length is 32-bit mode. 11 = Reserved. Note1: This field is only valid when operating in CPU mode. Note2: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA [7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA [15:0].
[31:30] | CRCMODE | CRC Polynomial Mode This field indicates the CRC operation polynomial mode. 00 = CRC-CCITT Polynomial Mode. 01 = CRC-8 Polynomial Mode. 10 = CRC-16 Polynomial Mode. 11 = CRC-32 Polynomial Mode.

Definition at line 13233 of file Nano103.h.

## ◆ DAT

DMA_CRC_T::DAT

[0x0080] CRC Write Data Register

DAT

Offset: 0x80 CRC Write Data Register

Bits | Field | Descriptions
[31:0] | DATA | CRC Write Data Bits When operating in CPU mode, user can write data to this field to perform CRC operation. When operating in DMA mode, this field indicates the DMA read data from memory and cannot be written by user. Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register are only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register are only DATA[15:0] bits.

Definition at line 13252 of file Nano103.h.

## ◆ DMABCNT

DMA_CRC_T::DMABCNT

[0x000c] CRC DMA Transfer Byte Count Register

DMABCNT

Offset: 0x0C CRC DMA Transfer Byte Count Register

Bits | Field | Descriptions
[15:0] | BCNT | CRC DMA Transfer Byte Count This field indicates a 16-bit total transfer byte count number of CRC DMA.

Definition at line 13238 of file Nano103.h.

## ◆ DMACBCNT

DMA_CRC_T::DMACBCNT

[0x001c] CRC DMA Current Transfer Byte Count Register

DMACBCNT

Offset: 0x1C CRC DMA Current Transfer Byte Count Register

Bits | Field | Descriptions
[15:0] | CBCNT | CRC DMA Current Remained Byte Count (Read Only) This field indicates the current remained byte count of CRC DMA. Note: Setting the CRCRST (CRC_CTL[1]) bit to 1 will clear this register value.

Definition at line 13246 of file Nano103.h.

## ◆ DMACSA

DMA_CRC_T::DMACSA

[0x0014] CRC DMA Current Source Address Register

DMACSA

Offset: 0x14 CRC DMA Current Source Address Register

Bits | Field | Descriptions
[31:0] | CSA | CRC DMA Current Source Address Bits (Read Only) This field indicates the current source address where the CRC DMA transfer just occurs.

Definition at line 13242 of file Nano103.h.

## ◆ DMAINTEN

DMA_CRC_T::DMAINTEN

[0x0020] CRC DMA Interrupt Enable Register

DMAINTEN

Offset: 0x20 CRC DMA Interrupt Enable Register

Bits | Field | Descriptions
[0] | TABTIEN | CRC DMA Read/Write Target Abort Interrupt Enable Bit Enable this bit will generate the CRC DMA Target Abort interrupt signal while TABTIF (CRC_DMAINTSTS[0]) bit is set to 1. 0 = Target abort interrupt Disabled during CRC DMA transfer. 1 = Target abort interrupt Enabled during CRC DMA transfer.
[1] | TDIEN | CRC DMA Block Transfer Done Interrupt Enable Bit Enable this bit will generate the CRC DMA Transfer Done interrupt signal while TDIF (CRC_DMAINTSTS[1]) bit is set to 1. 0 = Interrupt Disabled when CRC DMA transfer done. 1 = Interrupt Enabled when CRC DMA transfer done.

Definition at line 13247 of file Nano103.h.

## ◆ DMAISTS

DMA_CRC_T::DMAISTS

[0x0024] CRC DMA Interrupt Status Register

DMAISTS

Offset: 0x24 CRC DMA Interrupt Status Register

Bits | Field | Descriptions
[0] | TABTIF | CRC DMA Read/Write Target Abort Interrupt Flag This bit indicates that CRC bus has error or not during CRC DMA transfer. 0 = No bus error response received during CRC DMA transfer. 1 = Bus error response received during CRC DMA transfer. Note1: This bit is cleared by writing 1 to it. Note2: This bit indicates bus master received error response or not If bus master received error response, it means that CRC transfer target abort is happened DMA will stop transfer and respond this event to user then CRC state machine goes to IDLE state When target abort occurred, user must reset DMA before transfer those data again.
[1] | TDIF | CRC DMA Transfer Done Interrupt Flag This bit indicates that CRC DMA transfer has finished or not. 0 = Not finished if TRIGEN (CRC_CTL[23]) has enabled. 1 = CRC transfer done if TRIGEN (CRC_CTL[23]) has enabled. Note1: This bit is cleared by writing 1 to it. Note2: When CRC DMA transfer is done, TRIGEN (CRC_CTL[23]) will be cleared automatically.

Definition at line 13248 of file Nano103.h.

## ◆ DMASA

DMA_CRC_T::DMASA

[0x0004] CRC DMA Source Address Register

DMASA

Offset: 0x04 CRC DMA Source Address Register

Bits | Field | Descriptions
[31:0] | SA | CRC DMA Transfer Source Address Bits This field indicates a 32-bit source address of CRC DMA. Note: The source address must be word alignment.

Definition at line 13234 of file Nano103.h.

## ◆ SEED

DMA_CRC_T::SEED

[0x0084] CRC Seed Register

SEED

Offset: 0x84 CRC Seed Register

Bits | Field | Descriptions
[31:0] | SEED | CRC Seed Value This field indicates the CRC seed value.

Definition at line 13253 of file Nano103.h.

The documentation for this struct was generated from the following file:

- C:/Users/yachen/workzone/bsp/nano103bsp/Library/Device/Nuvoton/Nano103/Include/Nano103.h