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Nano103 BSP
V3.01.002
The Board Support Package for Nano103 Series
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#include <Nano103.h>
Data Fields | |
| __IO uint32_t | GCTL |
| __IO uint32_t | REQSEL0 |
| __IO uint32_t | REQSEL1 |
| __I uint32_t | GINTSTS |
| DMA_GCR_T::GCTL |
[0x0000] PDMA Global Control Register
| Bits | Field | Descriptions |
| [9] | CKEN1 | PDMA Controller Channel 1 Clock Enable Bit
0 = PDMA channel 1 clock Disabled. 1 = PDMA channel 1 clock Enabled. |
| [10] | CKEN2 | PDMA Controller Channel 2 Clock Enable Bit
0 = PDMA channel 2 clock Disabled. 1 = PDMA channel 2 clock Enabled. |
| [11] | CKEN3 | PDMA Controller Channel 3 Clock Enable Bit
0 = PDMA channel 3 clock Disabled. 1 = PDMA channel 3 clock Enabled. |
| [12] | CKEN4 | PDMA Controller Channel 4 Clock Enable Bit
0 = PDMA channel 4 clock Disabled. 1 = PDMA channel 4 clock Enabled. |
| [24] | CKENCRC | CRC Controller Clock Enable Bit
0 = CRC channel clock Disabled. 1 = CRC channel clock Enabled. |
| DMA_GCR_T::GINTSTS |
[0x000c] PDMA Global Interrupt Status Register
| Bits | Field | Descriptions |
| [1] | IF1 | PDMA Channel 1 Interrupt Status (Read Only)
This bit indicates the interrupt status of PDMA channel 1. |
| [2] | IF2 | PDMA Channel 2 Interrupt Status Flag of (Read Only)
This bit indicates the interrupt status of PDMA channel 2. |
| [3] | IF3 | PDMA Channel 3 Interrupt Status (Read Only)
This bit indicates the interrupt status of PDMA channel 3. |
| [4] | IF4 | PDMA Channel 4 Interrupt Status Flag (Read Only)
This bit indicates the interrupt status of PDMA channel 4. |
| [16] | IFCRC | CRC Controller Interrupt Status Flag (Read Only)
This bit indicates the interrupt status of CRC controller |
| DMA_GCR_T::REQSEL0 |
[0x0004] PDMA Request Source Select Register 0
| Bits | Field | Descriptions |
| [12:8] | REQSRC1 | Channel 1 Request Source Selection
This filed defines which peripheral is connected to PDMA channel 1 User can configure the peripheral by setting CH1_SEL. 00000 = Connect to SPI0_TX. 00001 = Connect to SPI1_TX. 00010 = Connect to UART0_TX. 00011 = Connect to UART1_TX. 00100 = Reserved. 00101 = Connect to SPI3_TX. 00110 = Reserved. 00111 = Reserved. 01000 = Connect to SPI2_TX. 01001 = Connect to TMR0. 01010 = Connect to TMR1. 01011 = Connect to TMR2. 01100 = Connect to TMR3. 10000 = Connect to SPI0_RX. 10001 = Connect to SPI1_RX. 10010 = Connect to UART0_RX. 10011 = Connect to UART1_RX. 10100 = Reserved. 10101 = Connect to SPI3_RX. 10110 = Connect to ADC. 10111 = Reserved. 11000 = Connect to SPI2_RX. 11001 = Reserved. 11010 = Reserved. 11011 = Reserved. 11100 = Reserved. Others = Disable to connected any peripheral. |
| [20:16] | REQSRC2 | Channel 2 Request Source Selection
This filed defines which peripheral is connected to PDMA channel 2 User can configure the peripheral setting by REQSRC2. Note: The channel configuration is the same as REQSRC1 field Please refer to the explanation of REQSRC1. |
| [28:24] | REQSRC3 | Channel 3 Request Source Selection
This filed defines which peripheral is connected to PDMA channel 3 User can configure the peripheral setting by REQSRC3. Note: The channel configuration is the same as REQSRC1 field Please refer to the explanation of REQSRC1. |
| DMA_GCR_T::REQSEL1 |
[0x0008] PDMA Request Source Select Register 1
| Bits | Field | Descriptions |
| [4:0] | REQSRC4 | Channel 4 Request Source Selection
This filed defines which peripheral is connected to PDMA channel 4 User can configure the peripheral setting by REQSRC4. Note: The channel configuration is the same as REQSRC1 field Please refer to the explanation of REQSRC1. |
1.8.15