| Nano103 BSP V3.01.002 The Board Support Package for Nano103 Series

pdma.c
Go to the documentation of this file.
1 /**************************************************************************/
12 #include "Nano103.h"
13
14
15
38 void PDMA_Open(uint32_t u32Mask)
39 {
40 PDMAGCR->GCTL |= (u32Mask << 8);
41 }
42
52 void PDMA_Close(void)
53 {
54 PDMAGCR->GCTL = 0;
55 }
56
68 void PDMA_SetTransferCnt(uint32_t u32Ch, uint32_t u32Width, uint32_t u32TransCount)
69 {
70 PDMA_CH_T *pdma;
71 pdma = (PDMA_CH_T *)((uint32_t) PDMA0_BASE + (0x100 * u32Ch));
72 pdma->CTLn = (pdma->CTLn & ~PDMA_CH_CTLn_TXWIDTH_Msk) | u32Width;
73 pdma->CNTn = (u32TransCount & 0xffff);
74 }
75
89 void PDMA_SetTransferAddr(uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl)
90 {
91 PDMA_CH_T *pdma;
92 pdma = (PDMA_CH_T *)((uint32_t) PDMA0_BASE + (0x100 * u32Ch));
93
94 pdma->SAn = u32SrcAddr;
95 pdma->DAn = u32DstAddr;
96 pdma->CTLn = (pdma->CTLn & ~(PDMA_CH_CTLn_SASEL_Msk|PDMA_CH_CTLn_DASEL_Msk)) | (u32SrcCtrl | u32DstCtrl);
97 }
98
116 void PDMA_SetTransferMode(uint32_t u32Ch, uint32_t u32Peripheral, uint32_t u32ScatterEn, uint32_t u32DescAddr)
117 {
118 switch (u32Ch)
119 {
120 case 1:
121 PDMAGCR->REQSEL0 = (PDMAGCR->REQSEL0 & ~DMA_GCR_REQSEL0_REQSRC1_Msk) | (u32Peripheral << DMA_GCR_REQSEL0_REQSRC1_Pos);
122 break;
123 case 2:
124 PDMAGCR->REQSEL0 = (PDMAGCR->REQSEL0 & ~DMA_GCR_REQSEL0_REQSRC2_Msk) | (u32Peripheral << DMA_GCR_REQSEL0_REQSRC2_Pos);
125 break;
126 case 3:
127 PDMAGCR->REQSEL0 = (PDMAGCR->REQSEL0 & ~DMA_GCR_REQSEL0_REQSRC3_Msk) | (u32Peripheral << DMA_GCR_REQSEL0_REQSRC3_Pos);
128 break;
129 case 4:
130 PDMAGCR->REQSEL1 = (PDMAGCR->REQSEL1 & ~DMA_GCR_REQSEL1_REQSRC4_Msk) | u32Peripheral;
131 break;
132 default:
133 ;
134 }
135 }
136
148 void PDMA_SetTimeOut(uint32_t u32Ch, uint32_t u32OnOff, uint32_t u32TimeOutCnt)
149 {
150 PDMA_CH_T *pdma;
151 pdma = (PDMA_CH_T *)((uint32_t) PDMA0_BASE + (0x100 * u32Ch));
152
153 pdma->TOCn &= ~PDMA_CH_TOCn_TOC_Msk;
154 pdma->TOCn |= u32TimeOutCnt;
155 pdma->CTLn = (pdma->CTLn & ~PDMA_CH_CTLn_TOUTEN_Msk) | (u32OnOff << PDMA_CH_CTLn_TOUTEN_Pos);
156
157 }
158
168 void PDMA_Trigger(uint32_t u32Ch)
169 {
170 PDMA_CH_T *pdma;
171 pdma = (PDMA_CH_T *)((uint32_t) PDMA0_BASE + (0x100 * u32Ch));
172
173 pdma->CTLn |= (PDMA_CH_CTLn_TRIGEN_Msk | PDMA_CH_CTLn_CHEN_Msk);
174 }
175
186 void PDMA_EnableInt(uint32_t u32Ch, uint32_t u32Mask)
187 {
188 PDMA_CH_T *pdma;
189 pdma = (PDMA_CH_T *)((uint32_t) PDMA0_BASE + (0x100 * u32Ch));
190
191 pdma->INTENn |= u32Mask;
192 }
193
204 void PDMA_DisableInt(uint32_t u32Ch, uint32_t u32Mask)
205 {
206 PDMA_CH_T *pdma;
207 pdma = (PDMA_CH_T *)((uint32_t) PDMA0_BASE + (0x100 * u32Ch));
208
209 pdma->INTENn &= ~u32Mask;
210 }
211
212 /* end of group NANO103_PDMA_EXPORTED_FUNCTIONS */
214 /* end of group NANO103_PDMA_Driver */
216 /* end of group NANO103_Device_Driver */
218
219 /*** (C) COPYRIGHT 2015 Nuvoton Technology Corp. ***/
PDMA_SetTransferMode
void PDMA_SetTransferMode(uint32_t u32Ch, uint32_t u32Periphral, uint32_t u32ScatterEn, uint32_t u32DescAddr)
Set PDMA Transfer Mode.
Definition: pdma.c:116
DMA_GCR_REQSEL0_REQSRC1_Msk
#define DMA_GCR_REQSEL0_REQSRC1_Msk
Definition: Nano103.h:13648
PDMA_Close
void PDMA_Close(void)
PDMA Close.
Definition: pdma.c:52
DMA_GCR_REQSEL1_REQSRC4_Msk
#define DMA_GCR_REQSEL1_REQSRC4_Msk
Definition: Nano103.h:13657
PDMA_CH_T::TOCn
__IO uint32_t TOCn
Definition: Nano103.h:12884
PDMA_CH_CTLn_TOUTEN_Msk
#define PDMA_CH_CTLn_TOUTEN_Msk
Definition: Nano103.h:13498
DMA_GCR_REQSEL0_REQSRC3_Msk
#define DMA_GCR_REQSEL0_REQSRC3_Msk
Definition: Nano103.h:13654
PDMA_CH_CTLn_TRIGEN_Msk
#define PDMA_CH_CTLn_TRIGEN_Msk
Definition: Nano103.h:13504
PDMA_CH_CTLn_TXWIDTH_Msk
#define PDMA_CH_CTLn_TXWIDTH_Msk
Definition: Nano103.h:13501
PDMA_CH_T
Definition: Nano103.h:12499
PDMA_CH_T::INTENn
__IO uint32_t INTENn
Definition: Nano103.h:12882
PDMA_CH_CTLn_TOUTEN_Pos
#define PDMA_CH_CTLn_TOUTEN_Pos
Definition: Nano103.h:13497
PDMA_CH_T::SAn
__IO uint32_t SAn
Definition: Nano103.h:12873
PDMA0_BASE
#define PDMA0_BASE
PDMA0 register base address.
Definition: Nano103.h:24845
DMA_GCR_REQSEL0_REQSRC1_Pos
#define DMA_GCR_REQSEL0_REQSRC1_Pos
Definition: Nano103.h:13647
PDMA_SetTransferCnt
void PDMA_SetTransferCnt(uint32_t u32Ch, uint32_t u32Width, uint32_t u32TransCount)
Set PDMA Transfer Count.
Definition: pdma.c:68
PDMA_CH_T::CTLn
__IO uint32_t CTLn
Definition: Nano103.h:12872
PDMAGCR
#define PDMAGCR
Pointer to PDMA global control register structure.
Definition: Nano103.h:24897
PDMA_CH_CTLn_CHEN_Msk
#define PDMA_CH_CTLn_CHEN_Msk
Definition: Nano103.h:13486
DMA_GCR_REQSEL0_REQSRC2_Pos
#define DMA_GCR_REQSEL0_REQSRC2_Pos
Definition: Nano103.h:13650
PDMA_CH_CTLn_DASEL_Msk
#define PDMA_CH_CTLn_DASEL_Msk
Definition: Nano103.h:13495
Nano103.h
NANO103 peripheral access layer header file. This file contains all the peripheral register's definit...
PDMA_Trigger
void PDMA_Trigger(uint32_t u32Ch)
Trigger PDMA.
Definition: pdma.c:168
PDMA_EnableInt
void PDMA_EnableInt(uint32_t u32Ch, uint32_t u32Mask)
Enable Interrupt.
Definition: pdma.c:186
DMA_GCR_REQSEL0_REQSRC3_Pos
#define DMA_GCR_REQSEL0_REQSRC3_Pos
Definition: Nano103.h:13653
PDMA_CH_CTLn_SASEL_Msk
#define PDMA_CH_CTLn_SASEL_Msk
Definition: Nano103.h:13492
PDMA_CH_T::CNTn
__IO uint32_t CNTn
Definition: Nano103.h:12875
DMA_GCR_REQSEL0_REQSRC2_Msk
#define DMA_GCR_REQSEL0_REQSRC2_Msk
Definition: Nano103.h:13651
PDMA_DisableInt
void PDMA_DisableInt(uint32_t u32Ch, uint32_t u32Mask)
Disable Interrupt.
Definition: pdma.c:204
PDMA_Open
void PDMA_Open(uint32_t u32Mask)
PDMA Open.
Definition: pdma.c:38
PDMA_SetTransferAddr
void PDMA_SetTransferAddr(uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl)
Set PDMA Transfer Address.
Definition: pdma.c:89
PDMA_SetTimeOut
void PDMA_SetTimeOut(uint32_t u32Ch, uint32_t u32OnOff, uint32_t u32TimeOutCnt)
Set PDMA Timeout.
Definition: pdma.c:148
PDMA_CH_T::DAn
__IO uint32_t DAn
Definition: Nano103.h:12874
PDMA_CH_TOCn_TOC_Msk
#define PDMA_CH_TOCn_TOC_Msk
Definition: Nano103.h:13552