| Nano103 BSP V3.01.002 The Board Support Package for Nano103 Series

Data Fields
PWM_T Struct Reference

`#include <Nano103.h>`

## Data Fields
__IO uint32_t | CTL0
__IO uint32_t | CTL1
__IO uint32_t | CLKSRC
__IO uint32_t | CLKPSC0_1
__IO uint32_t | CLKPSC2_3
__IO uint32_t | CLKPSC4_5
__IO uint32_t | CNTEN
__IO uint32_t | CNTCLR
__IO uint32_t | PERIOD [6]
__IO uint32_t | CMPDAT [6]
__IO uint32_t | DTCTL0_1
__IO uint32_t | DTCTL2_3
__IO uint32_t | DTCTL4_5
__I uint32_t | CNT [6]
__IO uint32_t | WGCTL0
__IO uint32_t | WGCTL1
__IO uint32_t | MSKEN
__IO uint32_t | MSK
__IO uint32_t | BNF
__IO uint32_t | FAILBRK
__IO uint32_t | BRKCTL0_1
__IO uint32_t | BRKCTL2_3
__IO uint32_t | BRKCTL4_5
__IO uint32_t | POLCTL
__IO uint32_t | POEN
__O uint32_t | SWBRK
__IO uint32_t | INTEN0
__IO uint32_t | INTEN1
__IO uint32_t | INTSTS0
__IO uint32_t | INTSTS1
__IO uint32_t | ADCTS0
__IO uint32_t | ADCTS1
__IO uint32_t | STATUS
__IO uint32_t | CAPINEN
__IO uint32_t | CAPCTL
__I uint32_t | CAPSTS
__I uint32_t | RCAPDAT0
__I uint32_t | FCAPDAT0
__I uint32_t | RCAPDAT1
__I uint32_t | FCAPDAT1
__I uint32_t | RCAPDAT2
__I uint32_t | FCAPDAT2
__I uint32_t | RCAPDAT3
__I uint32_t | FCAPDAT3
__I uint32_t | RCAPDAT4
__I uint32_t | FCAPDAT4
__I uint32_t | RCAPDAT5
__I uint32_t | FCAPDAT5
__IO uint32_t | CAPIEN
__IO uint32_t | CAPIF
__IO uint32_t | SELFTEST
__I uint32_t | PBUF0
__I uint32_t | PBUF2
__I uint32_t | PBUF4
__I uint32_t | CMPBUF0
__I uint32_t | CMPBUF1
__I uint32_t | CMPBUF2
__I uint32_t | CMPBUF3
__I uint32_t | CMPBUF4
__I uint32_t | CMPBUF5

## Detailed Description

    @addtogroup PWM Pulse Width Modulation Controller(PWM)
    Memory Mapped Structure for PWM Controller

Definition at line 14357 of file Nano103.h.

## Field Documentation

## ◆ ADCTS0

PWM_T::ADCTS0

[0x00f8] PWM0 Trigger ADC Source Select Register 0

ADCTS0

Offset: 0xF8 PWM0 Trigger ADC Source Select Register 0

Bits | Field | Descriptions
[3:0] | TRGSEL0 | PWM0_CH0 Trigger ADC Source Select 0000 = PWM0_CH0 zero point. 0001 = PWM0_CH0 period point. 0010 = PWM0_CH0 zero or period point. 0011 = PWM0_CH0 up-count CMPDAT point. 0100 = PWM0_CH0 down-count CMPDAT point. 0101 = Reserved. 0110 = Reserved. 0111 = Reserved. 1000 = PWM0_CH1 up-count CMPDAT point. 1001 = PWM0_CH1 down-count CMPDAT point. Others reserved
[7] | TRGEN0 | PWM0_CH0 Trigger EADC Enable Bit 0 = PWM0_CH0 Trigger EADC Disabled. 1 = PWM0_CH0 Trigger EADC Enabled.
[11:8] | TRGSEL1 | PWM0_CH1 Trigger ADC Source Select 0000 = PWM0_CH0 zero point. 0001 = PWM0_CH0 period point. 0010 = PWM0_CH0 zero or period point. 0011 = PWM0_CH0 up-count CMPDAT point. 0100 = PWM0_CH0 down-count CMPDAT point. 0101 = Reserved. 0110 = Reserved. 0111 = Reserved. 1000 = PWM0_CH1 up-count CMPDAT point. 1001 = PWM0_CH1 down-count CMPDAT point. Others reserved
[15] | TRGEN1 | PWM0_CH1 Trigger EADC Enable Bit 0 = PWM0_CH1 Trigger EADC Disabled. 1 = PWM0_CH1 Trigger EADC Enabled.
[19:16] | TRGSEL2 | PWM0_CH2 Trigger ADC Source Select 0000 = PWM0_CH2 zero point. 0001 = PWM0_CH2 period point. 0010 = PWM0_CH2 zero or period point. 0011 = PWM0_CH2 up-count CMPDAT point. 0100 = PWM0_CH2 down-count CMPDAT point. 0101 = Reserved. 0110 = Reserved. 0111 = Reserved. 1000 = PWM0_CH3 up-count CMPDAT point. 1001 = PWM0_CH3 down-count CMPDAT point. Others reserved
[23] | TRGEN2 | PWM0_CH2 Trigger EADC Enable Bit 0 = PWM0_CH2 Trigger EADC Disabled. 1 = PWM0_CH2 Trigger EADC Enabled.
[27:24] | TRGSEL3 | PWM0_CH3 Trigger ADC Source Select 0000 = PWM0_CH2 zero point. 0001 = PWM0_CH2 period point. 0010 = PWM0_CH2 zero or period point. 0011 = PWM0_CH2 up-count CMPDAT point. 0100 = PWM0_CH2 down-count CMPDAT point. 0101 = Reserved. 0110 = Reserved. 0111 = Reserved. 1000 = PWM0_CH3 up-count CMPDAT point. 1001 = PWM0_CH3 down-count CMPDAT point. Others reserved
[31] | TRGEN3 | PWM0_CH3 Trigger EADC Enable Bit 0 = PWM0_CH3 Trigger EADC Disabled. 1 = PWM0_CH3 Trigger EADC Enabled.

Definition at line 16866 of file Nano103.h.

## ◆ ADCTS1

PWM_T::ADCTS1

[0x00fc] PWM0 Trigger ADC Source Select Register 1

ADCTS1

Offset: 0xFC PWM0 Trigger ADC Source Select Register 1

Bits | Field | Descriptions
[3:0] | TRGSEL4 | PWM0_CH4 Trigger ADC Source Select 0000 = PWM0_CH4 zero point. 0001 = PWM0_CH4 period point. 0010 = PWM0_CH4 zero or period point. 0011 = PWM0_CH4 up-count CMPDAT point. 0100 = PWM0_CH4 down-count CMPDAT point. 0101 = Reserved. 0110 = Reserved. 0111 = Reserved. 1000 = PWM0_CH5 up-count CMPDAT point. 1001 = PWM0_CH5 down-count CMPDAT point. Others reserved
[7] | TRGEN4 | PWM0_CH4 Trigger EADC Enable Bit 0 = PWM0_CH4 Trigger EADC Disabled. 1 = PWM0_CH4 Trigger EADC Enabled.
[11:8] | TRGSEL5 | PWM0_CH5 Trigger ADC Source Select 0000 = PWM0_CH4 zero point. 0001 = PWM0_CH4 period point. 0010 = PWM0_CH4 zero or period point. 0011 = PWM0_CH4 up-count CMPDAT point. 0100 = PWM0_CH4 down-count CMPDAT point. 0101 = Reserved. 0110 = Reserved. 0111 = Reserved. 1000 = PWM0_CH5 up-count CMPDAT point. 1001 = PWM0_CH5 down-count CMPDAT point. Others reserved
[15] | TRGEN5 | PWM0_CH5 Trigger EADC Enable Bit 0 = PWM0_CH5 Trigger EADC Disabled. 1 = PWM0_CH5 Trigger EADC Enabled.

Definition at line 16867 of file Nano103.h.

## ◆ BNF

PWM_T::BNF

[0x00c0] PWM0 Brake Noise Filter Register

BNF

Offset: 0xC0 PWM0 Brake Noise Filter Register

Bits | Field | Descriptions
[0] | BRK0FEN | PWM0 Brake 0 Noise Filter Enable Bit 0 = Noise filter of PWM0 Brake 0 Disabled. 1 = Noise filter of PWM0 Brake 0 Enabled.
[3:1] | BRK0FCS | Brake 0 Edge Detector Filter Clock Selection 000 = Filter clock = HCLK. 001 = Filter clock = HCLK/2. 010 = Filter clock = HCLK/4. 011 = Filter clock = HCLK/8. 100 = Filter clock = HCLK/16. 101 = Filter clock = HCLK/32. 110 = Filter clock = HCLK/64. 111 = Filter clock = HCLK/128.
[6:4] | BRK0FCNT | Brake 0 Edge Detector Filter Count The register bits control the Brake0 filter counter to count from 0 to BRK1FCNT.
[7] | BRK0PINV | Brake 0 Pin Inverse 0 = The state of pin PWMx_BRAKE0 is passed to the negative edge Detector. 1 = The inversed state of pin PWMx_BRAKE10 is passed to the negative edge Detector.
[8] | BRK1FEN | PWM0 Brake 1 Noise Filter Enable Bit 0 = Noise filter of PWM0 Brake 1 Disabled. 1 = Noise filter of PWM0 Brake 1 Enabled.
[11:9] | BRK1FCS | Brake 1 Edge Detector Filter Clock Selection 000 = Filter clock = HCLK. 001 = Filter clock = HCLK/2. 010 = Filter clock = HCLK/4. 011 = Filter clock = HCLK/8. 100 = Filter clock = HCLK/16. 101 = Filter clock = HCLK/32. 110 = Filter clock = HCLK/64. 111 = Filter clock = HCLK/128.
[14:12] | BRK1FCNT | Brake 1 Edge Detector Filter Count The register bits control the Brake1 filter counter to count from 0 to BRK1FCNT.
[15] | BRK1PINV | Brake 1 Pin Inverse 0 = The state of pin PWMx_BRAKE1 is passed to the negative edge Detector. 1 = The inversed state of pin PWMx_BRAKE1 is passed to the negative edge Detector.
[16] | BK0SRC | Brake 0 Pin Source Select For PWM0 setting: 0 = Brake 0 pin source come from PWM0_BRAKE0. 1 = Brake 0 pin source come from PWM1_BRAKE0. For PWM1 setting: 0 = Brake 0 pin source come from PWM1_BRAKE0. 1 = Brake 0 pin source come from PWM0_BRAKE0.
[24] | BK1SRC | Brake 1 Pin Source Select For PWM0 setting: 0 = Brake 1 pin source come from PWM0_BRAKE1. 1 = Brake 1 pin source come from PWM1_BRAKE1. For PWM1 setting: 0 = Brake 1 pin source come from PWM1_BRAKE1. 1 = Brake 1 pin source come from PWM0_BRAKE1.

Definition at line 16851 of file Nano103.h.

## ◆ BRKCTL0_1

PWM_T::BRKCTL0_1

[0x00c8] PWM0 Brake Edge Detect Control Register 0_1

BRKCTL0_1

Offset: 0xC8 PWM0 Brake Edge Detect Control Register 0_1

Bits | Field | Descriptions
[4] | BRKP0EEN | Enable PWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect) 0 = BKP0 pin as edge-detect brake source Disabled. 1 = BKP0 pin as edge-detect brake source Enabled. Note: This register is write protected. Refer to SYS_REGLCTL register.
[5] | BRKP1EEN | Enable PWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect) 0 = BKP1 pin as edge-detect brake source Disabled. 1 = BKP1 pin as edge-detect brake source Enabled. Note: This register is write protected. Refer to SYS_REGLCTL register.
[7] | SYSEEN | Enable System Fail As Edge-detect Brake Source (Write Protect) 0 = System Fail condition as edge-detect brake source Disabled. 1 = System Fail condition as edge-detect brake source Enabled. Note: This register is write protected. Refer to SYS_REGLCTL register.
[12] | BRKP0LEN | Enable BKP0 Pin As Level-detect Brake Source (Write Protect) 0 = PWMx_BRAKE0 pin as level-detect brake source Disabled. 1 = PWMx_BRAKE0 pin as level-detect brake source Enabled. Note: This register is write protected. Refer to SYS_REGLCTL register.
[13] | BRKP1LEN | Enable BKP1 Pin As Level-detect Brake Source (Write Protect) 0 = PWMx_BRAKE1 pin as level-detect brake source Disabled. 1 = PWMx_BRAKE1 pin as level-detect brake source Enabled. Note: This register is write protected. Refer to SYS_REGLCTL register.
[15] | SYSLEN | Enable System Fail As Level-detect Brake Source (Write Protect) 0 = System Fail condition as level-detect brake source Disabled. 1 = System Fail condition as level-detect brake source Enabled. Note: This register is write protected. Refer to SYS_REGLCTL register.
[17:16] | BRKAEVEN | PWM0 Brake Action Select for Even Channel (Write Protect) 00 = PWM0 even channel brake function not affect channel output. 01 = PWM0 even channel output tri-state when brake happened. 10 = PWM0 even channel output low level when brake happened. 11 = PWM0 even channel output high level when brake happened. Note: This register is write protected. Refer to SYS_REGLCTL register.
[19:18] | BRKAODD | PWM0 Brake Action Select for Odd Channel (Write Protect) 00 = PWM0 odd channel brake function not affect channel output. 01 = PWM0 odd channel output tri-state when brake happened. 10 = PWM0 odd channel output low level when brake happened. 11 = PWM0 odd channel output high level when brake happened. Note: This register is write protected. Refer to SYS_REGLCTL register.

Definition at line 16853 of file Nano103.h.

## ◆ BRKCTL2_3

PWM_T::BRKCTL2_3

[0x00cc] PWM0 Brake Edge Detect Control Register 2_3

BRKCTL2_3

Offset: 0xCC PWM0 Brake Edge Detect Control Register 2_3

Bits | Field | Descriptions
[4] | BRKP0EEN | Enable PWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect) 0 = BKP0 pin as edge-detect brake source Disabled. 1 = BKP0 pin as edge-detect brake source Enabled. Note: This register is write protected. Refer to SYS_REGLCTL register.
[5] | BRKP1EEN | Enable PWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect) 0 = BKP1 pin as edge-detect brake source Disabled. 1 = BKP1 pin as edge-detect brake source Enabled. Note: This register is write protected. Refer to SYS_REGLCTL register.
[7] | SYSEEN | Enable System Fail As Edge-detect Brake Source (Write Protect) 0 = System Fail condition as edge-detect brake source Disabled. 1 = System Fail condition as edge-detect brake source Enabled. Note: This register is write protected. Refer to SYS_REGLCTL register.
[12] | BRKP0LEN | Enable BKP0 Pin As Level-detect Brake Source (Write Protect) 0 = PWMx_BRAKE0 pin as level-detect brake source Disabled. 1 = PWMx_BRAKE0 pin as level-detect brake source Enabled. Note: This register is write protected. Refer to SYS_REGLCTL register.
[13] | BRKP1LEN | Enable BKP1 Pin As Level-detect Brake Source (Write Protect) 0 = PWMx_BRAKE1 pin as level-detect brake source Disabled. 1 = PWMx_BRAKE1 pin as level-detect brake source Enabled. Note: This register is write protected. Refer to SYS_REGLCTL register.
[15] | SYSLEN | Enable System Fail As Level-detect Brake Source (Write Protect) 0 = System Fail condition as level-detect brake source Disabled. 1 = System Fail condition as level-detect brake source Enabled. Note: This register is write protected. Refer to SYS_REGLCTL register.
[17:16] | BRKAEVEN | PWM0 Brake Action Select for Even Channel (Write Protect) 00 = PWM0 even channel brake function not affect channel output. 01 = PWM0 even channel output tri-state when brake happened. 10 = PWM0 even channel output low level when brake happened. 11 = PWM0 even channel output high level when brake happened. Note: This register is write protected. Refer to SYS_REGLCTL register.
[19:18] | BRKAODD | PWM0 Brake Action Select for Odd Channel (Write Protect) 00 = PWM0 odd channel brake function not affect channel output. 01 = PWM0 odd channel output tri-state when brake happened. 10 = PWM0 odd channel output low level when brake happened. 11 = PWM0 odd channel output high level when brake happened. Note: This register is write protected. Refer to SYS_REGLCTL register.

Definition at line 16854 of file Nano103.h.

## ◆ BRKCTL4_5

PWM_T::BRKCTL4_5

[0x00d0] PWM0 Brake Edge Detect Control Register 4_5

BRKCTL4_5

Offset: 0xD0 PWM0 Brake Edge Detect Control Register 4_5

Bits | Field | Descriptions
[4] | BRKP0EEN | Enable PWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect) 0 = BKP0 pin as edge-detect brake source Disabled. 1 = BKP0 pin as edge-detect brake source Enabled. Note: This register is write protected. Refer to SYS_REGLCTL register.
[5] | BRKP1EEN | Enable PWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect) 0 = BKP1 pin as edge-detect brake source Disabled. 1 = BKP1 pin as edge-detect brake source Enabled. Note: This register is write protected. Refer to SYS_REGLCTL register.
[7] | SYSEEN | Enable System Fail As Edge-detect Brake Source (Write Protect) 0 = System Fail condition as edge-detect brake source Disabled. 1 = System Fail condition as edge-detect brake source Enabled. Note: This register is write protected. Refer to SYS_REGLCTL register.
[12] | BRKP0LEN | Enable BKP0 Pin As Level-detect Brake Source (Write Protect) 0 = PWMx_BRAKE0 pin as level-detect brake source Disabled. 1 = PWMx_BRAKE0 pin as level-detect brake source Enabled. Note: This register is write protected. Refer to SYS_REGLCTL register.
[13] | BRKP1LEN | Enable BKP1 Pin As Level-detect Brake Source (Write Protect) 0 = PWMx_BRAKE1 pin as level-detect brake source Disabled. 1 = PWMx_BRAKE1 pin as level-detect brake source Enabled. Note: This register is write protected. Refer to SYS_REGLCTL register.
[15] | SYSLEN | Enable System Fail As Level-detect Brake Source (Write Protect) 0 = System Fail condition as level-detect brake source Disabled. 1 = System Fail condition as level-detect brake source Enabled. Note: This register is write protected. Refer to SYS_REGLCTL register.
[17:16] | BRKAEVEN | PWM0 Brake Action Select for Even Channel (Write Protect) 00 = PWM0 even channel brake function not affect channel output. 01 = PWM0 even channel output tri-state when brake happened. 10 = PWM0 even channel output low level when brake happened. 11 = PWM0 even channel output high level when brake happened. Note: This register is write protected. Refer to SYS_REGLCTL register.
[19:18] | BRKAODD | PWM0 Brake Action Select for Odd Channel (Write Protect) 00 = PWM0 odd channel brake function not affect channel output. 01 = PWM0 odd channel output tri-state when brake happened. 10 = PWM0 odd channel output low level when brake happened. 11 = PWM0 odd channel output high level when brake happened. Note: This register is write protected. Refer to SYS_REGLCTL register.

Definition at line 16855 of file Nano103.h.

## ◆ CAPCTL

PWM_T::CAPCTL

[0x0204] PWM0 Capture Control Register

CAPCTL

Offset: 0x204 PWM0 Capture Control Register

Bits | Field | Descriptions
[5:0] | CAPENn | Capture Function Enable Bits Each bit n controls the corresponding PWM0 channel n. 0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. 1 = Capture function Enabled Capture latched the PWM0 counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
[13:8] | CAPINVn | Capture Inverter Enable Bits Each bit n controls the corresponding PWM0 channel n. 0 = Capture source inverter Disabled. 1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
[21:16] | RCRLDENn | Rising Capture Reload Enable Bits Each bit n controls the corresponding PWM0 channel n. 0 = Rising capture reload counter Disabled. 1 = Rising capture reload counter Enabled.
[29:24] | FCRLDENn | Falling Capture Reload Enable Bits Each bit n controls the corresponding PWM0 channel n. 0 = Falling capture reload counter Disabled. 1 = Falling capture reload counter Enabled.

Definition at line 16876 of file Nano103.h.

## ◆ CAPIEN

PWM_T::CAPIEN

[0x0250] PWM0 Capture Interrupt Enable Register

CAPIEN

Offset: 0x250 PWM0 Capture Interrupt Enable Register

Bits | Field | Descriptions
[5:0] | CAPRIENn | PWM0 Capture Rising Latch Interrupt Enable Bits Each bit n controls the corresponding PWM0 channel n. 0 = Capture rising edge latch interrupt Disabled. 1 = Capture rising edge latch interrupt Enabled.
[13:8] | CAPFIENn | PWM0 Capture Falling Latch Interrupt Enable Bits Each bit n controls the corresponding PWM0 channel n. 0 = Capture falling edge latch interrupt Disabled. 1 = Capture falling edge latch interrupt Enabled.

Definition at line 16893 of file Nano103.h.

## ◆ CAPIF

PWM_T::CAPIF

[0x0254] PWM0 Capture Interrupt Flag Register

CAPIF

Offset: 0x254 PWM0 Capture Interrupt Flag Register

Bits | Field | Descriptions
[5:0] | CAPRIFn | PWM0 Capture Rising Latch Interrupt Flag This bit is writing 1 to clear. Each bit n controls the corresponding PWM0 channel n. 0 = No capture rising latch condition happened. 1 = Capture rising latch condition happened, this flag will be set to high.
[13:8] | CAPFIFn | PWM0 Capture Falling Latch Interrupt Flag This bit is writing 1 to clear. Each bit n controls the corresponding PWM0 channel n. 0 = No capture falling latch condition happened. 1 = Capture falling latch condition happened, this flag will be set to high.

Definition at line 16894 of file Nano103.h.

## ◆ CAPINEN

PWM_T::CAPINEN

[0x0200] PWM0 Capture Input Enable Register

CAPINEN

Offset: 0x200 PWM0 Capture Input Enable Register

Bits | Field | Descriptions
[5:0] | CAPINENn | Capture Input Enable Bits Each bit n controls the corresponding PWM0 channel n. 0 = PWM0 Channel capture input path Disabled The input of PWM0 channel capture function is always regarded as 0. 1 = PWM0 Channel capture input path Enabled The input of PWM0 channel capture function comes from correlative multifunction pin.

Definition at line 16875 of file Nano103.h.

## ◆ CAPSTS

PWM_T::CAPSTS

[0x0208] PWM0 Capture Status Register

CAPSTS

Offset: 0x208 PWM0 Capture Status Register

Bits | Field | Descriptions
[5:0] | CRIFOVn | Capture Rising Interrupt Flag Overrun Status (Read Only) This flag indicates if rising latch happened when the corresponding CAPRIF is 1 Each bit n controls the corresponding PWM0 channel n. Note: This bit will be cleared automatically when user clear corresponding CAPRIF.
[13:8] | CFIFOVn | Capture Falling Interrupt Flag Overrun Status (Read Only) This flag indicates if falling latch happened when the corresponding CAPFIF is 1 Each bit n controls the corresponding PWM0 channel n. Note: This bit will be cleared automatically when user clear corresponding CAPFIF.

Definition at line 16877 of file Nano103.h.

## ◆ CLKPSC0_1

PWM_T::CLKPSC0_1

[0x0014] PWM0 Clock Pre-Scale Register 0_1

CLKPSC0_1

Offset: 0x14 PWM0 Clock Pre-Scale Register 0_1

Bits | Field | Descriptions
[11:0] | CLKPSC | PWM0 Counter Clock Pre-scale The clock of PWM0 counter is decided by clock prescaler Each PWM0 pair share one PWM0 counter clock prescaler The clock of PWM0 counter is divided by (CLKPSC+ 1)

Definition at line 16821 of file Nano103.h.

## ◆ CLKPSC2_3

PWM_T::CLKPSC2_3

[0x0018] PWM0 Clock Pre-Scale Register 2_3

CLKPSC2_3

Offset: 0x18 PWM0 Clock Pre-Scale Register 2_3

Bits | Field | Descriptions
[11:0] | CLKPSC | PWM0 Counter Clock Pre-scale The clock of PWM0 counter is decided by clock prescaler Each PWM0 pair share one PWM0 counter clock prescaler The clock of PWM0 counter is divided by (CLKPSC+ 1)

Definition at line 16822 of file Nano103.h.

## ◆ CLKPSC4_5

PWM_T::CLKPSC4_5

[0x001c] PWM0 Clock Pre-Scale Register 4_5

CLKPSC4_5

Offset: 0x1C PWM0 Clock Pre-Scale Register 4_5

Bits | Field | Descriptions
[11:0] | CLKPSC | PWM0 Counter Clock Pre-scale The clock of PWM0 counter is decided by clock prescaler Each PWM0 pair share one PWM0 counter clock prescaler The clock of PWM0 counter is divided by (CLKPSC+ 1)

Definition at line 16823 of file Nano103.h.

## ◆ CLKSRC

PWM_T::CLKSRC

[0x0010] PWM0 Clock Source Register

CLKSRC

Offset: 0x10 PWM0 Clock Source Register

Bits | Field | Descriptions
[2:0] | ECLKSRC0 | PWM0_CH01 External Clock Source Select 000 = PWMx_CLK, x denotes 0 or 1. 001 = TIMER0 overflow. 010 = TIMER1 overflow. 011 = TIMER2 overflow. 100 = TIMER3 overflow. Others = Reserved.
[10:8] | ECLKSRC2 | PWM0_CH23 External Clock Source Select 000 = PWMx_CLK, x denotes 0 or 1. 001 = TIMER0 overflow. 010 = TIMER1 overflow. 011 = TIMER2 overflow. 100 = TIMER3 overflow. Others = Reserved.
[18:16] | ECLKSRC4 | PWM0_CH45 External Clock Source Select 000 = PWMx_CLK, x denotes 0 or 1. 001 = TIMER0 overflow. 010 = TIMER1 overflow. 011 = TIMER2 overflow. 100 = TIMER3 overflow. Others = Reserved.

Definition at line 16820 of file Nano103.h.

## ◆ CMPBUF0

PWM_T::CMPBUF0

[0x031c] PWM0 CMPDAT0 Buffer

CMPBUF0

Offset: 0x31C PWM0 CMPDAT0 Buffer

Bits | Field | Descriptions
[15:0] | CMPBUF | PWM0 Comparator Register Buffer (Read Only) Used as CMP active register.

Definition at line 16911 of file Nano103.h.

## ◆ CMPBUF1

PWM_T::CMPBUF1

[0x0320] PWM0 CMPDAT1 Buffer

CMPBUF1

Offset: 0x320 PWM0 CMPDAT1 Buffer

Bits | Field | Descriptions
[15:0] | CMPBUF | PWM0 Comparator Register Buffer (Read Only) Used as CMP active register.

Definition at line 16912 of file Nano103.h.

## ◆ CMPBUF2

PWM_T::CMPBUF2

[0x0324] PWM0 CMPDAT2 Buffer

CMPBUF2

Offset: 0x324 PWM0 CMPDAT2 Buffer

Bits | Field | Descriptions
[15:0] | CMPBUF | PWM0 Comparator Register Buffer (Read Only) Used as CMP active register.

Definition at line 16913 of file Nano103.h.

## ◆ CMPBUF3

PWM_T::CMPBUF3

[0x0328] PWM0 CMPDAT3 Buffer

CMPBUF3

Offset: 0x328 PWM0 CMPDAT3 Buffer

Bits | Field | Descriptions
[15:0] | CMPBUF | PWM0 Comparator Register Buffer (Read Only) Used as CMP active register.

Definition at line 16914 of file Nano103.h.

## ◆ CMPBUF4

PWM_T::CMPBUF4

[0x032c] PWM0 CMPDAT4 Buffer

CMPBUF4

Offset: 0x32C PWM0 CMPDAT4 Buffer

Bits | Field | Descriptions
[15:0] | CMPBUF | PWM0 Comparator Register Buffer (Read Only) Used as CMP active register.

Definition at line 16915 of file Nano103.h.

## ◆ CMPBUF5

PWM_T::CMPBUF5

[0x0330] PWM0 CMPDAT5 Buffer

CMPBUF5

Offset: 0x330 PWM0 CMPDAT5 Buffer

Bits | Field | Descriptions
[15:0] | CMPBUF | PWM0 Comparator Register Buffer (Read Only) Used as CMP active register.

Definition at line 16916 of file Nano103.h.

## ◆ CMPDAT

PWM_T::CMPDAT

[0x0050] PWM0 Comparator Register 0,1,2,3,4,5

CMPDAT

Offset: 0x50 PWM0 Comparator Register

Bits | Field | Descriptions
[15:0] | CMPDAT | PWM0 Comparator Register CMPDAT use to compare with CNTR to generate PWM0 waveform, interrupt and trigger ADC. In independent mode, CMPDAT0~5 denote as 6 independent PWM0_CH0~5 compared point. In complementary mode, CMPDAT0, 2, 4 denote as first compared point, and CMPDAT1, 3, 5 denote as second compared point for the corresponding 3 complementary pairs PWM0_CH0 and PWM0_CH1, PWM0_CH2 and PWM0_CH3, PWM0_CH4 and PWM0_CH5.

Definition at line 16833 of file Nano103.h.

## ◆ CNT

PWM_T::CNT

[0x0090] PWM0 Counter Register 0,2,4

CNT

Offset: 0x90 PWM0 Counter Register

Bits | Field | Descriptions
[15:0] | CNT | PWM0 Data Register (Read Only) User can monitor CNTR to know the current value in 16-bit period counter.
[16] | DIRF | PWM0 Direction Indicator Flag (Read Only) 0 = Counter is Down count. 1 = Counter is UP count.

Definition at line 16843 of file Nano103.h.

## ◆ CNTCLR

PWM_T::CNTCLR

[0x0024] PWM0 Clear Counter Register

CNTCLR

Offset: 0x24 PWM0 Clear Counter Register

Bits | Field | Descriptions
[0] | CNTCLR0 | Clear PWM0 Counter Control Bit 0 It is automatically cleared by hardware. 0 = No effect. 1 = Clear 16-bit PWM0 counter to 0000H.
[2] | CNTCLR2 | Clear PWM0 Counter Control Bit 2 It is automatically cleared by hardware. 0 = No effect. 1 = Clear 16-bit PWM0 counter to 0000H.
[4] | CNTCLR4 | Clear PWM0 Counter Control Bit 4 It is automatically cleared by hardware. 0 = No effect. 1 = Clear 16-bit PWM0 counter to 0000H.

Definition at line 16825 of file Nano103.h.

## ◆ CNTEN

PWM_T::CNTEN

[0x0020] PWM0 Counter Enable Register

CNTEN

Offset: 0x20 PWM0 Counter Enable Register

Bits | Field | Descriptions
[0] | CNTEN0 | PWM0 Counter Enable Bit 0 0 = PWM0 Counter0_1 and clock prescaler0 Stop Running. 1 = PWM0 Counter0_1 and clock prescaler0 Start Running.
[2] | CNTEN2 | PWM0 Counter Enable Bit 2 0 = PWM0 Counter2_3 and clock prescaler2 Stop Running. 1 = PWM0 Counter2_3 and clock prescaler2 Start Running.
[4] | CNTEN4 | PWM0 Counter Enable Bit 4 0 = PWM0 Counter4_5 and clock prescaler4 Stop Running. 1 = PWM0 Counter4_5 and clock prescaler4 Start Running.

Definition at line 16824 of file Nano103.h.

## ◆ CTL0

PWM_T::CTL0

[0x0000] PWM0 Control Register 0

CTL0

Offset: 0x00 PWM0 Control Register 0

Bits | Field | Descriptions
[5:0] | CTRLDn | Center Re-load Each bit n controls the corresponding PWM0 channel n. In up-down counter type, PERIOD will load to PBUF at the end point of each period CMPDAT will load to CMPBUF at the center point of a period
[21:16] | IMMLDENn | Immediately Load Enable Bits Each bit n controls the corresponding PWM0 channel n. 0 = PERIOD will load to PBUF at the end point of each period CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. 1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid.
[30] | DBGHALT | ICE Debug Mode Counter Halt (Write Protect) If counter halt is enabled, PWM0 all counters will keep current value until exit ICE debug mode. 0 = ICE debug mode counter halt Disabled. 1 = ICE debug mode counter halt Enabled. Note: This bit is write protected. Refer to SYS_REGLCTL register.
[31] | DBGTRIOFF | ICE Debug Mode Acknowledge Disable Bit (Write Protect) 0 = ICE debug mode acknowledgement effects PWM0 output. PWM0 pin will be forced as tri-state while ICE debug mode acknowledged. 1 = ICE debug mode acknowledgement disabled. PWM0 pin will keep output no matter ICE debug mode acknowledged or not. Note: This bit is write protected. Refer to SYS_REGLCTL register.

Definition at line 16815 of file Nano103.h.

## ◆ CTL1

PWM_T::CTL1

[0x0004] PWM0 Control Register 1

CTL1

Offset: 0x04 PWM0 Control Register 1

Bits | Field | Descriptions
[1:0] | CNTTYPE0 | PWM0 Counter Behavior Type 0 Each bit n controls corresponding PWM0 channel n. 00 = Up counter type (supports in capture mode). 01 = Down count type (supports in capture mode). 10 = Up-down counter type. 11 = Reserved.
[5:4] | CNTTYPE2 | PWM0 Counter Behavior Type 2 Each bit n controls corresponding PWM0 channel n. 00 = Up counter type (supports in capture mode). 01 = Down count type (supports in capture mode). 10 = Up-down counter type. 11 = Reserved.
[9:8] | CNTTYPE4 | PWM0 Counter Behavior Type 4 Each bit n controls corresponding PWM0 channel n. 00 = Up counter type (supports in capture mode). 01 = Down count type (supports in capture mode). 10 = Up-down counter type. 11 = Reserved.
[26:24] | PWMMODEn | PWM0 Mode Each bit n controls the corresponding PWM0 channel n. 0 = PWM0 independent mode. 1 = PWM0 complementary mode. Note: When operating in group function, these bits must all set to the same mode.

Definition at line 16816 of file Nano103.h.

## ◆ DTCTL0_1

PWM_T::DTCTL0_1

[0x0070] PWM0 Dead-Time Control Register 0_1

DTCTL0_1

Offset: 0x70 PWM0 Dead-Time Control Register 0_1

Bits | Field | Descriptions
[11:0] | DTCNT | Dead-time Counter (Write Protect) The dead-time can be calculated from the following formula: Dead-time = (DTCNT[11:0]+1) * PWM0_CLK period. Note: This register is write protected. Refer to SYS_REGLCTL register.
[16] | DTEN | Enable Dead-time Insertion for PWM0 Pair (PWM0_CH0, PWM0_CH1) (PWM0_CH2, PWM0_CH3) (PWM0_CH4, PWM0_CH5) (Write Protect) Dead-time insertion is only active when this PWM0 pair complementary mode is enabled If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay. 0 = Dead-time insertion Disabled on the pin pair. 1 = Dead-time insertion Enabled on the pin pair. Note: This register is write protected. Refer to SYS_REGLCTL register.
[24] | DTCKSEL | Dead-time Clock Select (Write Protect) 0 = Dead-time clock source from PWM0_CLKn. 1 = Dead-time clock source from prescaler output. Note: This register is write protected. Refer to REGWRPROT register.

Definition at line 16837 of file Nano103.h.

## ◆ DTCTL2_3

PWM_T::DTCTL2_3

[0x0074] PWM0 Dead-Time Control Register 2_3

DTCTL2_3

Offset: 0x74 PWM0 Dead-Time Control Register 2_3

Bits | Field | Descriptions
[11:0] | DTCNT | Dead-time Counter (Write Protect) The dead-time can be calculated from the following formula: Dead-time = (DTCNT[11:0]+1) * PWM0_CLK period. Note: This register is write protected. Refer to SYS_REGLCTL register.
[16] | DTEN | Enable Dead-time Insertion for PWM0 Pair (PWM0_CH0, PWM0_CH1) (PWM0_CH2, PWM0_CH3) (PWM0_CH4, PWM0_CH5) (Write Protect) Dead-time insertion is only active when this PWM0 pair complementary mode is enabled If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay. 0 = Dead-time insertion Disabled on the pin pair. 1 = Dead-time insertion Enabled on the pin pair. Note: This register is write protected. Refer to SYS_REGLCTL register.
[24] | DTCKSEL | Dead-time Clock Select (Write Protect) 0 = Dead-time clock source from PWM0_CLKn. 1 = Dead-time clock source from prescaler output. Note: This register is write protected. Refer to REGWRPROT register.

Definition at line 16838 of file Nano103.h.

## ◆ DTCTL4_5

PWM_T::DTCTL4_5

[0x0078] PWM0 Dead-Time Control Register 4_5

DTCTL4_5

Offset: 0x78 PWM0 Dead-Time Control Register 4_5

Bits | Field | Descriptions
[11:0] | DTCNT | Dead-time Counter (Write Protect) The dead-time can be calculated from the following formula: Dead-time = (DTCNT[11:0]+1) * PWM0_CLK period. Note: This register is write protected. Refer to SYS_REGLCTL register.
[16] | DTEN | Enable Dead-time Insertion for PWM0 Pair (PWM0_CH0, PWM0_CH1) (PWM0_CH2, PWM0_CH3) (PWM0_CH4, PWM0_CH5) (Write Protect) Dead-time insertion is only active when this PWM0 pair complementary mode is enabled If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay. 0 = Dead-time insertion Disabled on the pin pair. 1 = Dead-time insertion Enabled on the pin pair. Note: This register is write protected. Refer to SYS_REGLCTL register.
[24] | DTCKSEL | Dead-time Clock Select (Write Protect) 0 = Dead-time clock source from PWM0_CLKn. 1 = Dead-time clock source from prescaler output. Note: This register is write protected. Refer to REGWRPROT register.

Definition at line 16839 of file Nano103.h.

## ◆ FAILBRK

PWM_T::FAILBRK

[0x00c4] PWM0 System Fail Brake Control Register

FAILBRK

Offset: 0xC4 PWM0 System Fail Brake Control Register

Bits | Field | Descriptions
[1] | BODBRKEN | Brown-out Detection Trigger PWM0 Brake Function 0 Enable Bit 0 = Brake Function triggered by BOD Disabled. 1 = Brake Function triggered by BOD Enabled.
[3] | CORBRKEN | Core Lockup Detection Trigger PWM0 Brake Function 0 Enable Bit 0 = Brake Function triggered by Core lockup detection Disabled. 1 = Brake Function triggered by Core lockup detection Enabled.

Definition at line 16852 of file Nano103.h.

## ◆ FCAPDAT0

PWM_T::FCAPDAT0

[0x0210] PWM0 Falling Capture Data Register 0

FCAPDAT0

Offset: 0x210 PWM0 Falling Capture Data Register 0

Bits | Field | Descriptions
[15:0] | FCAPDAT | PWM0 Falling Capture Data Register (Read Only) When falling capture condition happened, the PWM0 counter value will be saved in this register.

Definition at line 16879 of file Nano103.h.

## ◆ FCAPDAT1

PWM_T::FCAPDAT1

[0x0218] PWM0 Falling Capture Data Register 1

FCAPDAT1

Offset: 0x218 PWM0 Falling Capture Data Register 1

Bits | Field | Descriptions
[15:0] | FCAPDAT | PWM0 Falling Capture Data Register (Read Only) When falling capture condition happened, the PWM0 counter value will be saved in this register.

Definition at line 16881 of file Nano103.h.

## ◆ FCAPDAT2

PWM_T::FCAPDAT2

[0x0220] PWM0 Falling Capture Data Register 2

FCAPDAT2

Offset: 0x220 PWM0 Falling Capture Data Register 2

Bits | Field | Descriptions
[15:0] | FCAPDAT | PWM0 Falling Capture Data Register (Read Only) When falling capture condition happened, the PWM0 counter value will be saved in this register.

Definition at line 16883 of file Nano103.h.

## ◆ FCAPDAT3

PWM_T::FCAPDAT3

[0x0228] PWM0 Falling Capture Data Register 3

FCAPDAT3

Offset: 0x228 PWM0 Falling Capture Data Register 3

Bits | Field | Descriptions
[15:0] | FCAPDAT | PWM0 Falling Capture Data Register (Read Only) When falling capture condition happened, the PWM0 counter value will be saved in this register.

Definition at line 16885 of file Nano103.h.

## ◆ FCAPDAT4

PWM_T::FCAPDAT4

[0x0230] PWM0 Falling Capture Data Register 4

FCAPDAT4

Offset: 0x230 PWM0 Falling Capture Data Register 4

Bits | Field | Descriptions
[15:0] | FCAPDAT | PWM0 Falling Capture Data Register (Read Only) When falling capture condition happened, the PWM0 counter value will be saved in this register.

Definition at line 16887 of file Nano103.h.

## ◆ FCAPDAT5

PWM_T::FCAPDAT5

[0x0238] PWM0 Falling Capture Data Register 5

FCAPDAT5

Offset: 0x238 PWM0 Falling Capture Data Register 5

Bits | Field | Descriptions
[15:0] | FCAPDAT | PWM0 Falling Capture Data Register (Read Only) When falling capture condition happened, the PWM0 counter value will be saved in this register.

Definition at line 16889 of file Nano103.h.

## ◆ INTEN0

PWM_T::INTEN0

[0x00e0] PWM0 Interrupt Enable Register 0

INTEN0

Offset: 0xE0 PWM0 Interrupt Enable Register 0

Bits | Field | Descriptions
[0] | ZIEN0 | PWM0 Zero Point Interrupt Enable Bit 0 0 = PWM0 counter0_1 zero point interrupt Disabled. 1 = PWM0 counter0_1 zero point interrupt Enabled. Note: Odd channels will read always 0 at complementary mode.
[2] | ZIEN2 | PWM0 Zero Point Interrupt Enable Bit 2 0 = PWM0 counter2_3 zero point interrupt Disabled. 1 = PWM0 counter2_3 zero point interrupt Enabled. Note: Odd channels will read always 0 at complementary mode.
[4] | ZIEN4 | PWM0 Zero Point Interrupt Enable Bit 4 0 = PWM0 counter4_5 zero point interrupt Disabled. 1 = PWM0 counter4_5 zero point interrupt Enabled. Note: Odd channels will read always 0 at complementary mode.
[8] | PIEN0 | PWM0 Period Point Interrupt Enable Bit 0 0 = PWM0 counter0_1 period point interrupt Disabled. 1 = PWM0 counter0_1 period point interrupt Enabled. Note: When operating in up-down counter type, period point means center point.
[10] | PIEN2 | PWM0 Period Point Interrupt Enable Bit 2 0 = PWM0 counter2_3 period point interrupt Disabled. 1 = PWM0 counter2_3 period point interrupt Enabled. Note: When operating in up-down counter type, period point means center point.
[12] | PIEN4 | PWM0 Period Point Interrupt Enable Bit 4 0 = PWM0 counter4_5 period point interrupt Disabled. 1 = PWM0 counter4_5 period point interrupt Enabled. Note: When operating in up-down counter type, period point means center point.
[21:16] | CMPUIENn | PWM0 Compare Up Count Interrupt Enable Bits Each bit n controls the corresponding PWM0 channel n. 0 = Compare up count interrupt Disabled. 1 = Compare up count interrupt Enabled. Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4.
[29:24] | CMPDIENn | PWM0 Compare Down Count Interrupt Enable Bits Each bit n controls the corresponding PWM0 channel n. 0 = Compare down count interrupt Disabled. 1 = Compare down count interrupt Enabled. Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4.

Definition at line 16859 of file Nano103.h.

## ◆ INTEN1

PWM_T::INTEN1

[0x00e4] PWM0 Interrupt Enable Register 1

INTEN1

Offset: 0xE4 PWM0 Interrupt Enable Register 1

Bits | Field | Descriptions
[0] | BRKEIEN0_1 | PWM0 Edge-detect Brake Interrupt Enable Bit for Channel0/1 (Write Protect) 0 = Edge-detect Brake interrupt for channel0/1 Disabled. 1 = Edge-detect Brake interrupt for channel0/1 Enabled. Note: This register is write protected. Refer to SYS_REGLCTL register.
[1] | BRKEIEN2_3 | PWM0 Edge-detect Brake Interrupt Enable Bit for Channel2/3 (Write Protect) 0 = Edge-detect Brake interrupt for channel2/3 Disabled. 1 = Edge-detect Brake interrupt for channel2/3 Enabled. Note: This register is write protected. Refer to SYS_REGLCTL register.
[2] | BRKEIEN4_5 | PWM0 Edge-detect Brake Interrupt Enable Bit for Channel4/5 (Write Protect) 0 = Edge-detect Brake interrupt for channel4/5 Disabled. 1 = Edge-detect Brake interrupt for channel4/5 Enabled. Note: This register is write protected. Refer to SYS_REGLCTL register.
[8] | BRKLIEN0_1 | PWM0 Level-detect Brake Interrupt Enable Bit for Channel0/1 (Write Protect) 0 = Level-detect Brake interrupt for channel0/1 Disabled. 1 = Level-detect Brake interrupt for channel0/1 Enabled. Note: This register is write protected. Refer to SYS_REGLCTL register.
[9] | BRKLIEN2_3 | PWM0 Level-detect Brake Interrupt Enable Bit for Channel2/3 (Write Protect) 0 = Level-detect Brake interrupt for channel2/3 Disabled. 1 = Level-detect Brake interrupt for channel2/3 Enabled. Note: This register is write protected. Refer to SYS_REGLCTL register.
[10] | BRKLIEN4_5 | PWM0 Level-detect Brake Interrupt Enable Bit for Channel4/5 (Write Protect) 0 = Level-detect Brake interrupt for channel4/5 Disabled. 1 = Level-detect Brake interrupt for channel4/5 Enabled. Note: This register is write protected. Refer to SYS_REGLCTL register.

Definition at line 16860 of file Nano103.h.

## ◆ INTSTS0

PWM_T::INTSTS0

[0x00e8] PWM0 Interrupt Flag Register 0

INTSTS0

Offset: 0xE8 PWM0 Interrupt Flag Register 0

Bits | Field | Descriptions
[0] | ZIF0 | PWM0 Zero Point Interrupt Flag 0 This bit is set by hardware when PWM0_CH0 counter reaches zero, software can write 1 to clear this bit to zero.
[2] | ZIF2 | PWM0 Zero Point Interrupt Flag 2 This bit is set by hardware when PWM0_CH2 counter reaches zero, software can write 1 to clear this bit to zero.
[4] | ZIF4 | PWM0 Zero Point Interrupt Flag 4 This bit is set by hardware when PWM0_CH4 counter reaches zero, software can write 1 to clear this bit to zero.
[8] | PIF0 | PWM0 Period Point Interrupt Flag 0 This bit is set by hardware when PWM0_CH0 counter reaches PWM0_PERIOD0, software can write 1 to clear this bit to zero.
[10] | PIF2 | PWM0 Period Point Interrupt Flag 2 This bit is set by hardware when PWM0_CH2 counter reaches PWM0_PERIOD2, software can write 1 to clear this bit to zero.
[12] | PIF4 | PWM0 Period Point Interrupt Flag 4 This bit is set by hardware when PWM0_CH4 counter reaches PWM0_PERIOD4, software can write 1 to clear this bit to zero.
[21:16] | CMPUIFn | PWM0 Compare Up Count Interrupt Flag Flag is set by hardware when PWM0 counter up count and reaches PWM0_CMPDATn, software can clear this bit by writing 1 to it Each bit n controls the corresponding PWM0 channel n. Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4.
[29:24] | CMPDIFn | PWM0 Compare Down Count Interrupt Flag Each bit n controls the corresponding PWM0 channel n. Flag is set by hardware when PWM0 counter down count and reaches PWM0_CMPDATn, software can clear this bit by writing 1 to it. Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4.

Definition at line 16861 of file Nano103.h.

## ◆ INTSTS1

PWM_T::INTSTS1

[0x00ec] PWM0 Interrupt Flag Register 1

INTSTS1

Offset: 0xEC PWM0 Interrupt Flag Register 1

Bits | Field | Descriptions
[0] | BRKEIF0 | PWM0 Channel0 Edge-detect Brake Interrupt Flag (Write Protect) 0 = PWM0 channel0 edge-detect brake event do not happened. 1 = When PWM0 channel0 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. Note: This bit is write protected. Refer to SYS_REGLCTL register.
[1] | BRKEIF1 | PWM0 Channel1 Edge-detect Brake Interrupt Flag (Write Protect) 0 = PWM0 channel1 edge-detect brake event do not happened. 1 = When PWM0 channel1 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. Note: This bit is write protected. Refer to SYS_REGLCTL register.
[2] | BRKEIF2 | PWM0 Channel2 Edge-detect Brake Interrupt Flag (Write Protect) 0 = PWM0 channel2 edge-detect brake event do not happened. 1 = When PWM0 channel2 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. Note: This bit is write protected. Refer to SYS_REGLCTL register.
[3] | BRKEIF3 | PWM0 Channel3 Edge-detect Brake Interrupt Flag (Write Protect) 0 = PWM0 channel3 edge-detect brake event do not happened. 1 = When PWM0 channel3 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. Note: This bit is write protected. Refer to SYS_REGLCTL register.
[4] | BRKEIF4 | PWM0 Channel4 Edge-detect Brake Interrupt Flag (Write Protect) 0 = PWM0 channel4 edge-detect brake event do not happened. 1 = When PWM0 channel4 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. Note: This bit is write protected. Refer to SYS_REGLCTL register.
[5] | BRKEIF5 | PWM0 Channel5 Edge-detect Brake Interrupt Flag (Write Protect) 0 = PWM0 channel5 edge-detect brake event do not happened. 1 = When PWM0 channel5 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. Note: This bit is write protected. Refer to SYS_REGLCTL register.
[8] | BRKLIF0 | PWM0 Channel0 Level-detect Brake Interrupt Flag (Write Protect) 0 = PWM0 channel0 level-detect brake event do not happened. 1 = When PWM0 channel0 level-detect brake event happened, this bit is set to 1, writing 1 to clear. Note: This bit is write protected. Refer to SYS_REGLCTL register.
[9] | BRKLIF1 | PWM0 Channel1 Level-detect Brake Interrupt Flag (Write Protect) 0 = PWM0 channel1 level-detect brake event do not happened. 1 = When PWM0 channel1 level-detect brake event happened, this bit is set to 1, writing 1 to clear. Note: This bit is write protected. Refer to SYS_REGLCTL register.
[10] | BRKLIF2 | PWM0 Channel2 Level-detect Brake Interrupt Flag (Write Protect) 0 = PWM0 channel2 level-detect brake event do not happened. 1 = When PWM0 channel2 level-detect brake event happened, this bit is set to 1, writing 1 to clear. Note: This bit is write protected. Refer to SYS_REGLCTL register.
[11] | BRKLIF3 | PWM0 Channel3 Level-detect Brake Interrupt Flag (Write Protect) 0 = PWM0 channel3 level-detect brake event do not happened. 1 = When PWM0 channel3 level-detect brake event happened, this bit is set to 1, writing 1 to clear. Note: This bit is write protected. Refer to SYS_REGLCTL register.
[12] | BRKLIF4 | PWM0 Channel4 Level-detect Brake Interrupt Flag (Write Protect) 0 = PWM0 channel4 level-detect brake event do not happened. 1 = When PWM0 channel4 level-detect brake event happened, this bit is set to 1, writing 1 to clear. Note: This bit is write protected. Refer to SYS_REGLCTL register.
[13] | BRKLIF5 | PWM0 Channel5 Level-detect Brake Interrupt Flag (Write Protect) 0 = PWM0 channel5 level-detect brake event do not happened. 1 = When PWM0 channel5 level-detect brake event happened, this bit is set to 1, writing 1 to clear. Note: This bit is write protected. Refer to SYS_REGLCTL register.
[16] | BRKESTS0 | PWM0 Channel0 Edge-detect Brake Status (Read Only) 0 = PWM0 channel0 edge-detect brake state is released. 1 = When PWM0 channel0 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM0 channel0 at brake state, writing 1 to clear.
[17] | BRKESTS1 | PWM0 Channel1 Edge-detect Brake Status (Read Only) 0 = PWM0 channel1 edge-detect brake state is released. 1 = When PWM0 channel1 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM0 channel1 at brake state, writing 1 to clear.
[18] | BRKESTS2 | PWM0 Channel2 Edge-detect Brake Status (Read Only) 0 = PWM0 channel2 edge-detect brake state is released. 1 = When PWM0 channel2 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM0 channel2 at brake state, writing 1 to clear.
[19] | BRKESTS3 | PWM0 Channel3 Edge-detect Brake Status (Read Only) 0 = PWM0 channel3 edge-detect brake state is released. 1 = When PWM0 channel3 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM0 channel3 at brake state, writing 1 to clear.
[20] | BRKESTS4 | PWM0 Channel4 Edge-detect Brake Status (Read Only) 0 = PWM0 channel4 edge-detect brake state is released. 1 = When PWM0 channel4 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM0 channel4 at brake state, writing 1 to clear.
[21] | BRKESTS5 | PWM0 Channel5 Edge-detect Brake Status (Read Only) 0 = PWM0 channel5 edge-detect brake state is released. 1 = When PWM0 channel5 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM0 channel5 at brake state, writing 1 to clear.
[24] | BRKLSTS0 | PWM0 Channel0 Level-detect Brake Status (Read Only) 0 = PWM0 channel0 level-detect brake state is released. 1 = When PWM0 channel0 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM0 channel0 at brake state. Note: This bit is read only and auto cleared by hardware When enabled brake source return to high level, PWM0 will release brake state until current PWM0 period finished The PWM0 waveform will start output from next full PWM0 period.
[25] | BRKLSTS1 | PWM0 Channel1 Level-detect Brake Status (Read Only) 0 = PWM0 channel1 level-detect brake state is released. 1 = When PWM0 channel1 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM0 channel1 at brake state. Note: This bit is read only and auto cleared by hardware When enabled brake source return to high level, PWM0 will release brake state until current PWM0 period finished The PWM0 waveform will start output from next full PWM0 period.
[26] | BRKLSTS2 | PWM0 Channel2 Level-detect Brake Status (Read Only) 0 = PWM0 channel2 level-detect brake state is released. 1 = When PWM0 channel2 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM0 channel2 at brake state. Note: This bit is read only and auto cleared by hardware When enabled brake source return to high level, PWM0 will release brake state until current PWM0 period finished The PWM0 waveform will start output from next full PWM0 period.
[27] | BRKLSTS3 | PWM0 Channel3 Level-detect Brake Status (Read Only) 0 = PWM0 channel3 level-detect brake state is released. 1 = When PWM0 channel3 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM0 channel3 at brake state. Note: This bit is read only and auto cleared by hardware When enabled brake source return to high level, PWM0 will release brake state until current PWM0 period finished The PWM0 waveform will start output from next full PWM0 period.
[28] | BRKLSTS4 | PWM0 Channel4 Level-detect Brake Status (Read Only) 0 = PWM0 channel4 level-detect brake state is released. 1 = When PWM0 channel4 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM0 channel4 at brake state. Note: This bit is read only and auto cleared by hardware When enabled brake source return to high level, PWM0 will release brake state until current PWM0 period finished The PWM0 waveform will start output from next full PWM0 period.
[29] | BRKLSTS5 | PWM0 Channel5 Level-detect Brake Status (Read Only) 0 = PWM0 channel5 level-detect brake state is released. 1 = When PWM0 channel5 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM0 channel5 at brake state. Note: This bit is read only and auto cleared by hardware When enabled brake source return to high level, PWM0 will release brake state until current PWM0 period finished The PWM0 waveform will start output from next full PWM0 period.

Definition at line 16862 of file Nano103.h.

## ◆ MSK

PWM_T::MSK

[0x00bc] PWM0 Mask Data Register

MSK

Offset: 0xBC PWM0 Mask Data Register

Bits | Field | Descriptions
[5:0] | MSKDATn | PWM0 Mask Data Bits This data bit control the state of PWM0_CHn output pin, if corresponding mask function is enabled. 0 = Output logic low to PWM0_CHn. 1 = Output logic high to PWM0_CHn.

Definition at line 16850 of file Nano103.h.

## ◆ MSKEN

PWM_T::MSKEN

[0x00b8] PWM0 Mask Enable Register

MSKEN

Offset: 0xB8 PWM0 Mask Enable Register

Bits | Field | Descriptions
[5:0] | MSKENn | PWM0 Mask Enable Bits Each bit n controls the corresponding PWM0 channel n. The PWM0 output signal will be masked when this bit is enabled The corresponding PWM0 channel n will output MSKDATn (PWM0_MSK[5:0]) data. 0 = PWM0 output signal is non-masked. 1 = PWM0 output signal is masked and output MSKDATn data.

Definition at line 16849 of file Nano103.h.

## ◆ PBUF0

PWM_T::PBUF0

[0x0304] PWM0 PERIOD0 Buffer

PBUF0

Offset: 0x304 PWM0 PERIOD0 Buffer

Bits | Field | Descriptions
[15:0] | PBUF | PWM0 Period Register Buffer (Read Only) Used as PERIOD active register.

Definition at line 16899 of file Nano103.h.

## ◆ PBUF2

PWM_T::PBUF2

[0x030c] PWM0 PERIOD2 Buffer

PBUF2

Offset: 0x30C PWM0 PERIOD2 Buffer

Bits | Field | Descriptions
[15:0] | PBUF | PWM0 Period Register Buffer (Read Only) Used as PERIOD active register.

Definition at line 16903 of file Nano103.h.

## ◆ PBUF4

PWM_T::PBUF4

[0x0314] PWM0 PERIOD4 Buffer

PBUF4

Offset: 0x314 PWM0 PERIOD4 Buffer

Bits | Field | Descriptions
[15:0] | PBUF | PWM0 Period Register Buffer (Read Only) Used as PERIOD active register.

Definition at line 16907 of file Nano103.h.

## ◆ PERIOD

PWM_T::PERIOD

[0x0030] PWM0 Period Register 0,2,4

PERIOD

Offset: 0x30 PWM0 Period Register

Bits | Field | Descriptions
[15:0] | PERIOD | PWM0 Period Register Up-Count mode: In this mode, PWM0 counter counts from 0 to PERIOD, and restarts from 0. Down-Count mode: In this mode, PWM0 counter counts from PERIOD to 0, and restarts from PERIOD. PWM0 period time = (PERIOD+1) * PWM0_CLK period. Up-Down-Count mode: In this mode, PWM0 counter counts from 0 to PERIOD, then decrements to 0 and repeats again. PWM0 period time = 2 * PERIOD * PWM0_CLK period.

Definition at line 16829 of file Nano103.h.

## ◆ POEN

PWM_T::POEN

[0x00d8] PWM0 Output Enable Register

POEN

Offset: 0xD8 PWM0 Output Enable Register

Bits | Field | Descriptions
[5:0] | POENn | PWM0 Pin Output Enable Bits Each bit n controls the corresponding PWM0 channel n. 0 = PWM0 pin at tri-state. 1 = PWM0 pin in output mode.

Definition at line 16857 of file Nano103.h.

## ◆ POLCTL

PWM_T::POLCTL

[0x00d4] PWM0 Pin Polar Inverse Register

POLCTL

Offset: 0xD4 PWM0 Pin Polar Inverse Register

Bits | Field | Descriptions
[5:0] | PINVn | PWM0 PIN Polar Inverse Control The register controls polarity state of PWM0 output Each bit n controls the corresponding PWM0 channel n. 0 = PWM0 output polar inverse Disabled. 1 = PWM0 output polar inverse Enabled.

Definition at line 16856 of file Nano103.h.

## ◆ RCAPDAT0

PWM_T::RCAPDAT0

[0x020c] PWM0 Rising Capture Data Register 0

RCAPDAT0

Offset: 0x20C PWM0 Rising Capture Data Register 0

Bits | Field | Descriptions
[15:0] | RCAPDAT | PWM0 Rising Capture Data Register (Read Only) When rising capture condition happened, the PWM0 counter value will be saved in this register.

Definition at line 16878 of file Nano103.h.

## ◆ RCAPDAT1

PWM_T::RCAPDAT1

[0x0214] PWM0 Rising Capture Data Register 1

RCAPDAT1

Offset: 0x214 PWM0 Rising Capture Data Register 1

Bits | Field | Descriptions
[15:0] | RCAPDAT | PWM0 Rising Capture Data Register (Read Only) When rising capture condition happened, the PWM0 counter value will be saved in this register.

Definition at line 16880 of file Nano103.h.

## ◆ RCAPDAT2

PWM_T::RCAPDAT2

[0x021c] PWM0 Rising Capture Data Register 2

RCAPDAT2

Offset: 0x21C PWM0 Rising Capture Data Register 2

Bits | Field | Descriptions
[15:0] | RCAPDAT | PWM0 Rising Capture Data Register (Read Only) When rising capture condition happened, the PWM0 counter value will be saved in this register.

Definition at line 16882 of file Nano103.h.

## ◆ RCAPDAT3

PWM_T::RCAPDAT3

[0x0224] PWM0 Rising Capture Data Register 3

RCAPDAT3

Offset: 0x224 PWM0 Rising Capture Data Register 3

Bits | Field | Descriptions
[15:0] | RCAPDAT | PWM0 Rising Capture Data Register (Read Only) When rising capture condition happened, the PWM0 counter value will be saved in this register.

Definition at line 16884 of file Nano103.h.

## ◆ RCAPDAT4

PWM_T::RCAPDAT4

[0x022c] PWM0 Rising Capture Data Register 4

RCAPDAT4

Offset: 0x22C PWM0 Rising Capture Data Register 4

Bits | Field | Descriptions
[15:0] | RCAPDAT | PWM0 Rising Capture Data Register (Read Only) When rising capture condition happened, the PWM0 counter value will be saved in this register.

Definition at line 16886 of file Nano103.h.

## ◆ RCAPDAT5

PWM_T::RCAPDAT5

[0x0234] PWM0 Rising Capture Data Register 5

RCAPDAT5

Offset: 0x234 PWM0 Rising Capture Data Register 5

Bits | Field | Descriptions
[15:0] | RCAPDAT | PWM0 Rising Capture Data Register (Read Only) When rising capture condition happened, the PWM0 counter value will be saved in this register.

Definition at line 16888 of file Nano103.h.

## ◆ SELFTEST

PWM_T::SELFTEST

[0x0300] PWM0 Self-test Mode Enable

SELFTEST

Offset: 0x300 PWM0 Self-test Mode Enable

Bits | Field | Descriptions

Definition at line 16898 of file Nano103.h.

## ◆ STATUS

PWM_T::STATUS

[0x0120] PWM0 Status Register

STATUS

Offset: 0x120 PWM0 Status Register

Bits | Field | Descriptions
[0] | CNTMAX0 | Time-base Counter 0 Equal to 0xFFFF Latched Status 0 = indicates the time-base counter never reached its maximum value 0xFFFF. 1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit.
[2] | CNTMAX2 | Time-base Counter 2 Equal to 0xFFFF Latched Status 0 = indicates the time-base counter never reached its maximum value 0xFFFF. 1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit.
[4] | CNTMAX4 | Time-base Counter 4 Equal to 0xFFFF Latched Status 0 = indicates the time-base counter never reached its maximum value 0xFFFF. 1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit.
[21:16] | ADCTRGn | ADC Start of Conversion Status Each bit n controls the corresponding PWM0 channel n. 0 = Indicates no ADC start of conversion trigger event has occurred. 1 = Indicates an ADC start of conversion trigger event has occurred, software can write 1 to clear this bit.

Definition at line 16871 of file Nano103.h.

## ◆ SWBRK

PWM_T::SWBRK

[0x00dc] PWM0 Software Brake Control Register

SWBRK

Offset: 0xDC PWM0 Software Brake Control Register

Bits | Field | Descriptions
[2:0] | BRKETRGn | PWM0 Edge Brake Software Trigger (Write Only) (Write Protect) Each bit n controls the corresponding PWM0 pair n. Write 1 to this bit will trigger Edge brake, and set BRKEIFn to 1 in PWM0_INTSTS1 register. Note: This register is write protected. Refer to SYS_REGLCTL register.
[10:8] | BRKLTRGn | PWM0 Level Brake Software Trigger (Write Only) (Write Protect) Each bit n controls the corresponding PWM0 pair n. Write 1 to this bit will trigger level brake, and set BRKLIFn to 1 in PWM0_INTSTS1 register. Note: This register is write protected. Refer to SYS_REGLCTL register.

Definition at line 16858 of file Nano103.h.

## ◆ WGCTL0

PWM_T::WGCTL0

[0x00b0] PWM0 Waveform Generation Control Register 0

WGCTL0

Offset: 0xB0 PWM0 Waveform Generation Control Register 0

Bits | Field | Descriptions
[11:0] | ZPCTLn | PWM0 Zero Point Control Each bit n controls the corresponding PWM0 channel n. 00 = Do nothing. 01 = PWM0 zero point output Low. 10 = PWM0 zero point output High. 11 = PWM0 zero point output Toggle. PWM0 can control output level when PWM0 counter count to zero.
[27:16] | PRDPCTLn | PWM0 Period (Center) Point Control Each bit n controls the corresponding PWM0 channel n. 00 = Do nothing. 01 = PWM0 period (center) point output Low. 10 = PWM0 period (center) point output High. 11 = PWM0 period (center) point output Toggle. PWM0 can control output level when PWM0 counter count to (PERIODn+1). Note: This bit is center point control when PWM0 counter operating in up-down counter type.

Definition at line 16847 of file Nano103.h.

## ◆ WGCTL1

PWM_T::WGCTL1

[0x00b4] PWM0 Waveform Generation Control Register 1

WGCTL1

Offset: 0xB4 PWM0 Waveform Generation Control Register 1

Bits | Field | Descriptions
[11:0] | CMPUCTLn | PWM0 Compare Up Point Control Each bit n controls the corresponding PWM0 channel n. 00 = Do nothing. 01 = PWM0 compare up point output Low. 10 = PWM0 compare up point output High. 11 = PWM0 compare up point output Toggle. PWM0 can control output level when PWM0 counter up count to CMPDAT. Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4.
[27:16] | CMPDCTLn | PWM0 Compare Down Point Control Each bit n controls the corresponding PWM0 channel n. 00 = Do nothing. 01 = PWM0 compare down point output Low. 10 = PWM0 compare down point output High. 11 = PWM0 compare down point output Toggle. PWM0 can control output level when PWM0 counter down count to CMPDAT. Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4.

Definition at line 16848 of file Nano103.h.

The documentation for this struct was generated from the following file:

- C:/Users/yachen/workzone/bsp/nano103bsp/Library/Device/Nuvoton/Nano103/Include/Nano103.h