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Nano103 BSP
V3.01.002
The Board Support Package for Nano103 Series
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NANO103 peripheral access layer header file. This file contains all the peripheral register's definitions, bits definitions and memory mapping for NuMicro NANO103 MCU. More...
#include "core_cm0.h"#include "system_Nano103.h"#include <stdint.h>#include "sys.h"#include "clk.h"#include "acmp.h"#include "adc.h"#include "fmc.h"#include "gpio.h"#include "i2c.h"#include "crc.h"#include "pdma.h"#include "pwm.h"#include "rtc.h"#include "sc.h"#include "scuart.h"#include "spi.h"#include "timer.h"#include "uart.h"#include "wdt.h"#include "wwdt.h"Go to the source code of this file.
Data Structures | |
| struct | INT_T |
| struct | SYS_T |
| struct | CLK_T |
| struct | FMC_T |
| struct | GPIO_T |
| struct | GP_DB_T |
| struct | PDMA_CH_T |
| struct | DMA_CRC_T |
| struct | DMA_GCR_T |
| struct | TIMER_T |
| struct | PWM_T |
| struct | WDT_T |
| struct | WWDT_T |
| struct | RTC_T |
| struct | UART_T |
| struct | SC_T |
| struct | I2C_T |
| struct | SPI_T |
| struct | ADC_T |
| struct | ACMP_T |
Macros | |
| #define | __CM0_REV 0x0201 |
| #define | __NVIC_PRIO_BITS 2 |
| #define | __Vendor_SysTickConfig 0 |
| #define | __MPU_PRESENT 0 |
| #define | __FPU_PRESENT 0 |
| #define | FLASH_BASE ((uint32_t)0x00000000) |
| Flash base address. More... | |
| #define | SRAM_BASE ((uint32_t)0x20000000) |
| SRAM base address. More... | |
| #define | APB1PERIPH_BASE ((uint32_t)0x40000000) |
| APB1 base address. More... | |
| #define | APB2PERIPH_BASE ((uint32_t)0x40100000) |
| APB2 base address. More... | |
| #define | AHBPERIPH_BASE ((uint32_t)0x50000000) |
| AHB base address. More... | |
| #define | WDT_BASE (APB1PERIPH_BASE + 0x04000) |
| WDT register base address. More... | |
| #define | WWDT_BASE (APB1PERIPH_BASE + 0x04100) |
| WWDT register base address. More... | |
| #define | RTC_BASE (APB1PERIPH_BASE + 0x08000) |
| RTC register base address. More... | |
| #define | TIMER0_BASE (APB1PERIPH_BASE + 0x10000) |
| TIMER0 register base address. More... | |
| #define | TIMER1_BASE (APB1PERIPH_BASE + 0x10100) |
| TIMER1 register base address. More... | |
| #define | I2C0_BASE (APB1PERIPH_BASE + 0x20000) |
| I2C0 register base address. More... | |
| #define | SPI0_BASE (APB1PERIPH_BASE + 0x30000) |
| SPI0 register base address. More... | |
| #define | SPI2_BASE (APB1PERIPH_BASE + 0xD0000) |
| SPI2 register base address. More... | |
| #define | PWM0_BASE (APB1PERIPH_BASE + 0x40000) |
| PWM0 register base address. More... | |
| #define | UART0_BASE (APB1PERIPH_BASE + 0x50000) |
| UART0 register base address. More... | |
| #define | LCD_BASE (APB1PERIPH_BASE + 0xB0000) |
| LCD register base address. More... | |
| #define | ADC_BASE (APB1PERIPH_BASE + 0xE0000) |
| ADC register base address. More... | |
| #define | TIMER2_BASE (APB2PERIPH_BASE + 0x10000) |
| TIMER2 register base address. More... | |
| #define | TIMER3_BASE (APB2PERIPH_BASE + 0x10100) |
| TIMER3 register base address. More... | |
| #define | I2C1_BASE (APB2PERIPH_BASE + 0x20000) |
| I2C1 register base address. More... | |
| #define | SPI1_BASE (APB2PERIPH_BASE + 0x30000) |
| SPI1 register base address. More... | |
| #define | SPI3_BASE (APB2PERIPH_BASE + 0xE0000) |
| SPI3 register base address. More... | |
| #define | UART1_BASE (APB2PERIPH_BASE + 0x50000) |
| UART1 register base address. More... | |
| #define | SC0_BASE (APB2PERIPH_BASE + 0x90000) |
| SC0 register base address. More... | |
| #define | SC1_BASE (APB2PERIPH_BASE + 0xB0000) |
| SC1 register base address. More... | |
| #define | ACMP_BASE (APB2PERIPH_BASE + 0xD0000) |
| ACMP register base address. More... | |
| #define | SYS_BASE (AHBPERIPH_BASE + 0x00000) |
| SYS register base address. More... | |
| #define | CLK_BASE (AHBPERIPH_BASE + 0x00200) |
| CLK register base address. More... | |
| #define | INTID_BASE (AHBPERIPH_BASE + 0x00300) |
| INT register base address. More... | |
| #define | GPIOA_BASE (AHBPERIPH_BASE + 0x04000) |
| GPIO port A register base address. More... | |
| #define | GPIOB_BASE (AHBPERIPH_BASE + 0x04040) |
| GPIO port B register base address. More... | |
| #define | GPIOC_BASE (AHBPERIPH_BASE + 0x04080) |
| GPIO port C register base address. More... | |
| #define | GPIOD_BASE (AHBPERIPH_BASE + 0x040C0) |
| GPIO port D register base address. More... | |
| #define | GPIOE_BASE (AHBPERIPH_BASE + 0x04100) |
| GPIO port E register base address. More... | |
| #define | GPIOF_BASE (AHBPERIPH_BASE + 0x04140) |
| GPIO port F register base address. More... | |
| #define | GPIODBNCE_BASE (AHBPERIPH_BASE + 0x04180) |
| GPIO debounce register base address. More... | |
| #define | GPIO_PIN_DATA_BASE (AHBPERIPH_BASE + 0x04200) |
| GPIO bit access register base address. More... | |
| #define | PDMA0_BASE (AHBPERIPH_BASE + 0x08000) |
| PDMA0 register base address. More... | |
| #define | PDMA1_BASE (AHBPERIPH_BASE + 0x08100) |
| PDMA1 register base address. More... | |
| #define | PDMA2_BASE (AHBPERIPH_BASE + 0x08200) |
| PDMA2 register base address. More... | |
| #define | PDMA3_BASE (AHBPERIPH_BASE + 0x08300) |
| PDMA3 register base address. More... | |
| #define | PDMA4_BASE (AHBPERIPH_BASE + 0x08400) |
| PDMA4 register base address. More... | |
| #define | PDMACRC_BASE (AHBPERIPH_BASE + 0x08E00) |
| PDMA global control register base address. More... | |
| #define | PDMAGCR_BASE (AHBPERIPH_BASE + 0x08F00) |
| PDMA CRC register base address. More... | |
| #define | FMC_BASE (AHBPERIPH_BASE + 0x0C000) |
| FMC register base address. More... | |
| #define | WDT ((WDT_T *) WDT_BASE) |
| Pointer to WDT register structure. More... | |
| #define | WWDT ((WWDT_T *) WWDT_BASE) |
| Pointer to WWDT register structure. More... | |
| #define | RTC ((RTC_T *) RTC_BASE) |
| Pointer to RTC register structure. More... | |
| #define | TIMER0 ((TIMER_T *) TIMER0_BASE) |
| Pointer to TIMER0 register structure. More... | |
| #define | TIMER1 ((TIMER_T *) TIMER1_BASE) |
| Pointer to TIMER1 register structure. More... | |
| #define | TIMER2 ((TIMER_T *) TIMER2_BASE) |
| Pointer to TIMER2 register structure. More... | |
| #define | TIMER3 ((TIMER_T *) TIMER3_BASE) |
| Pointer to TIMER3 register structure. More... | |
| #define | I2C0 ((I2C_T *) I2C0_BASE) |
| Pointer to I2C0 register structure. More... | |
| #define | I2C1 ((I2C_T *) I2C1_BASE) |
| Pointer to I2C1 register structure. More... | |
| #define | SPI0 ((SPI_T *) SPI0_BASE) |
| Pointer to SPI0 register structure. More... | |
| #define | SPI1 ((SPI_T *) SPI1_BASE) |
| Pointer to SPI1 register structure. More... | |
| #define | SPI2 ((SPI_T *) SPI2_BASE) |
| Pointer to SPI2 register structure. More... | |
| #define | SPI3 ((SPI_T *) SPI3_BASE) |
| Pointer to SPI3 register structure. More... | |
| #define | PWM0 ((PWM_T *) PWM0_BASE) |
| Pointer to PWM0 register structure. More... | |
| #define | UART0 ((UART_T *) UART0_BASE) |
| Pointer to UART0 register structure. More... | |
| #define | UART1 ((UART_T *) UART1_BASE) |
| Pointer to UART1 register structure. More... | |
| #define | LCD ((LCD_T *) LCD_BASE) |
| Pointer to LCD register structure. More... | |
| #define | ADC ((ADC_T *) ADC_BASE) |
| Pointer to ADC register structure. More... | |
| #define | SC0 ((SC_T *) SC0_BASE) |
| Pointer to SC0 register structure. More... | |
| #define | SC1 ((SC_T *) SC1_BASE) |
| Pointer to SC1 register structure. More... | |
| #define | ACMP ((ACMP_T *) ACMP_BASE) |
| Pointer to ACMP register structure. More... | |
| #define | SYS ((SYS_T *) SYS_BASE) |
| Pointer to SYS register structure. More... | |
| #define | CLK ((CLK_T *) CLK_BASE) |
| Pointer to CLK register structure. More... | |
| #define | PA ((GPIO_T *) GPIOA_BASE) |
| Pointer to GPIO port A register structure. More... | |
| #define | PB ((GPIO_T *) GPIOB_BASE) |
| Pointer to GPIO port B register structure. More... | |
| #define | PC ((GPIO_T *) GPIOC_BASE) |
| Pointer to GPIO port C register structure. More... | |
| #define | PD ((GPIO_T *) GPIOD_BASE) |
| Pointer to GPIO port D register structure. More... | |
| #define | PE ((GPIO_T *) GPIOE_BASE) |
| Pointer to GPIO port E register structure. More... | |
| #define | PF ((GPIO_T *) GPIOF_BASE) |
| Pointer to GPIO port F register structure. More... | |
| #define | GPIO ((GP_DB_T *) GPIODBNCE_BASE) |
| Pointer to GPIO debounce register structure. More... | |
| #define | PDMA1 ((PDMA_CH_T *) PDMA1_BASE) |
| Pointer to PDMA1 register structure. More... | |
| #define | PDMA2 ((PDMA_CH_T *) PDMA2_BASE) |
| Pointer to PDMA2 register structure. More... | |
| #define | PDMA3 ((PDMA_CH_T *) PDMA3_BASE) |
| Pointer to PDMA3 register structure. More... | |
| #define | PDMA4 ((PDMA_CH_T *) PDMA4_BASE) |
| Pointer to PDMA4 register structure. More... | |
| #define | PDMACRC ((DMA_CRC_T *) PDMACRC_BASE) |
| Pointer to PDMA CRC register structure. More... | |
| #define | PDMAGCR ((DMA_GCR_T *) PDMAGCR_BASE) |
| Pointer to PDMA global control register structure. More... | |
| #define | FMC ((FMC_T *) FMC_BASE) |
| Pointer to FMC register structure. More... | |
| #define | M8(addr) (*((vu8 *) (addr))) |
| Get a 8-bit unsigned value from specified address. More... | |
| #define | M16(addr) (*((vu16 *) (addr))) |
| Get a 16-bit unsigned value from specified address. More... | |
| #define | M32(addr) (*((vu32 *) (addr))) |
| Get a 32-bit unsigned value from specified address. More... | |
| #define | outpw(port, value) *((volatile unsigned int *)(port)) = value |
| Set a 32-bit unsigned value to specified I/O port. More... | |
| #define | inpw(port) (*((volatile unsigned int *)(port))) |
| Get a 32-bit unsigned value from specified I/O port. More... | |
| #define | outps(port, value) *((volatile unsigned short *)(port)) = value |
| Set a 16-bit unsigned value to specified I/O port. More... | |
| #define | inps(port) (*((volatile unsigned short *)(port))) |
| Get a 16-bit unsigned value from specified I/O port. More... | |
| #define | outpb(port, value) *((volatile unsigned char *)(port)) = value |
| Set a 8-bit unsigned value to specified I/O port. More... | |
| #define | inpb(port) (*((volatile unsigned char *)(port))) |
| Get a 8-bit unsigned value from specified I/O port. More... | |
| #define | outp32(port, value) *((volatile unsigned int *)(port)) = value |
| Set a 32-bit unsigned value to specified I/O port. More... | |
| #define | inp32(port) (*((volatile unsigned int *)(port))) |
| Get a 32-bit unsigned value from specified I/O port. More... | |
| #define | outp16(port, value) *((volatile unsigned short *)(port)) = value |
| Set a 16-bit unsigned value to specified I/O port. More... | |
| #define | inp16(port) (*((volatile unsigned short *)(port))) |
| Get a 16-bit unsigned value from specified I/O port. More... | |
| #define | outp8(port, value) *((volatile unsigned char *)(port)) = value |
| Set a 8-bit unsigned value to specified I/O port. More... | |
| #define | inp8(port) (*((volatile unsigned char *)(port))) |
| Get a 8-bit unsigned value from specified I/O port. More... | |
| #define | NULL (0) |
| NULL pointer. More... | |
| #define | TRUE (1) |
| Boolean true, define to use in API parameters or return value. More... | |
| #define | FALSE (0) |
| Boolean false, define to use in API parameters or return value. More... | |
| #define | ENABLE (1) |
| Enable, define to use in API parameters. More... | |
| #define | DISABLE (0) |
| Disable, define to use in API parameters. More... | |
| #define | BIT0 (0x00000001) |
| Bit 0 mask of an 32 bit integer. More... | |
| #define | BIT1 (0x00000002) |
| Bit 1 mask of an 32 bit integer. More... | |
| #define | BIT2 (0x00000004) |
| Bit 2 mask of an 32 bit integer. More... | |
| #define | BIT3 (0x00000008) |
| Bit 3 mask of an 32 bit integer. More... | |
| #define | BIT4 (0x00000010) |
| Bit 4 mask of an 32 bit integer. More... | |
| #define | BIT5 (0x00000020) |
| Bit 5 mask of an 32 bit integer. More... | |
| #define | BIT6 (0x00000040) |
| Bit 6 mask of an 32 bit integer. More... | |
| #define | BIT7 (0x00000080) |
| Bit 7 mask of an 32 bit integer. More... | |
| #define | BIT8 (0x00000100) |
| Bit 8 mask of an 32 bit integer. More... | |
| #define | BIT9 (0x00000200) |
| Bit 9 mask of an 32 bit integer. More... | |
| #define | BIT10 (0x00000400) |
| Bit 10 mask of an 32 bit integer. More... | |
| #define | BIT11 (0x00000800) |
| Bit 11 mask of an 32 bit integer. More... | |
| #define | BIT12 (0x00001000) |
| Bit 12 mask of an 32 bit integer. More... | |
| #define | BIT13 (0x00002000) |
| Bit 13 mask of an 32 bit integer. More... | |
| #define | BIT14 (0x00004000) |
| Bit 14 mask of an 32 bit integer. More... | |
| #define | BIT15 (0x00008000) |
| Bit 15 mask of an 32 bit integer. More... | |
| #define | BIT16 (0x00010000) |
| Bit 16 mask of an 32 bit integer. More... | |
| #define | BIT17 (0x00020000) |
| Bit 17 mask of an 32 bit integer. More... | |
| #define | BIT18 (0x00040000) |
| Bit 18 mask of an 32 bit integer. More... | |
| #define | BIT19 (0x00080000) |
| Bit 19 mask of an 32 bit integer. More... | |
| #define | BIT20 (0x00100000) |
| Bit 20 mask of an 32 bit integer. More... | |
| #define | BIT21 (0x00200000) |
| Bit 21 mask of an 32 bit integer. More... | |
| #define | BIT22 (0x00400000) |
| Bit 22 mask of an 32 bit integer. More... | |
| #define | BIT23 (0x00800000) |
| Bit 23 mask of an 32 bit integer. More... | |
| #define | BIT24 (0x01000000) |
| Bit 24 mask of an 32 bit integer. More... | |
| #define | BIT25 (0x02000000) |
| Bit 25 mask of an 32 bit integer. More... | |
| #define | BIT26 (0x04000000) |
| Bit 26 mask of an 32 bit integer. More... | |
| #define | BIT27 (0x08000000) |
| Bit 27 mask of an 32 bit integer. More... | |
| #define | BIT28 (0x10000000) |
| Bit 28 mask of an 32 bit integer. More... | |
| #define | BIT29 (0x20000000) |
| Bit 29 mask of an 32 bit integer. More... | |
| #define | BIT30 (0x40000000) |
| Bit 30 mask of an 32 bit integer. More... | |
| #define | BIT31 (0x80000000) |
| Bit 31 mask of an 32 bit integer. More... | |
| #define | BYTE0_Msk (0x000000FF) |
| Mask to get bit0~bit7 from a 32 bit integer. More... | |
| #define | BYTE1_Msk (0x0000FF00) |
| Mask to get bit8~bit15 from a 32 bit integer. More... | |
| #define | BYTE2_Msk (0x00FF0000) |
| Mask to get bit16~bit23 from a 32 bit integer. More... | |
| #define | BYTE3_Msk (0xFF000000) |
| Mask to get bit24~bit31 from a 32 bit integer. More... | |
| #define | GET_BYTE0(u32Param) ((u32Param & BYTE0_Msk) ) |
| #define | GET_BYTE1(u32Param) ((u32Param & BYTE1_Msk) >> 8) |
| #define | GET_BYTE2(u32Param) ((u32Param & BYTE2_Msk) >> 16) |
| #define | GET_BYTE3(u32Param) ((u32Param & BYTE3_Msk) >> 24) |
| #define | INT_IRQ0_SRC_INT_SRC_Pos (0) |
| #define | INT_IRQ0_SRC_INT_SRC_Msk (0xful << INT_IRQ0_SRC_INT_SRC_Pos) |
| #define | INT_IRQ1_SRC_INT_SRC_Pos (0) |
| #define | INT_IRQ1_SRC_INT_SRC_Msk (0xful << INT_IRQ1_SRC_INT_SRC_Pos) |
| #define | INT_IRQ2_SRC_INT_SRC_Pos (0) |
| #define | INT_IRQ2_SRC_INT_SRC_Msk (0xful << INT_IRQ2_SRC_INT_SRC_Pos) |
| #define | INT_IRQ3_SRC_INT_SRC_Pos (0) |
| #define | INT_IRQ3_SRC_INT_SRC_Msk (0xful << INT_IRQ3_SRC_INT_SRC_Pos) |
| #define | INT_IRQ4_SRC_INT_SRC_Pos (0) |
| #define | INT_IRQ4_SRC_INT_SRC_Msk (0xful << INT_IRQ4_SRC_INT_SRC_Pos) |
| #define | INT_IRQ5_SRC_INT_SRC_Pos (0) |
| #define | INT_IRQ5_SRC_INT_SRC_Msk (0xful << INT_IRQ5_SRC_INT_SRC_Pos) |
| #define | INT_IRQ6_SRC_INT_SRC_Pos (0) |
| #define | INT_IRQ6_SRC_INT_SRC_Msk (0xful << INT_IRQ6_SRC6_INT_SRC_Pos) |
| #define | INT_IRQ7_SRC_INT_SRC_Pos (0) |
| #define | INT_IRQ7_SRC_INT_SRC_Msk (0xful << INT_IRQ7_SRC_INT_SRC_Pos) |
| #define | INT_IRQ8_SRC_INT_SRC_Pos (0) |
| #define | INT_IRQ8_SRC_INT_SRC_Msk (0xful << INT_IRQ8_SRC_INT_SRC_Pos) |
| #define | INT_IRQ9_SRC_INT_SRC_Pos (0) |
| #define | INT_IRQ9_SRC_INT_SRC_Msk (0xful << INT_IRQ9_SRC_INT_SRC_Pos) |
| #define | INT_IRQ10_SRC_INT_SRC_Pos (0) |
| #define | INT_IRQ10_SRC_INT_SRC_Msk (0xful << INT_IRQ10_SRC_INT_SRC_Pos) |
| #define | INT_IRQ11_SRC_INT_SRC_Pos (0) |
| #define | INT_IRQ11_SRC_INT_SRC_Msk (0xful << INT_IRQ11_SRC_INT_SRC_Pos) |
| #define | INT_IRQ12_SRC_INT_SRC_Pos (0) |
| #define | INT_IRQ12_SRC_INT_SRC_Msk (0xful << INT_IRQ12_SRC_INT_SRC_Pos) |
| #define | INT_IRQ13_SRC_INT_SRC_Pos (0) |
| #define | INT_IRQ13_SRC_INT_SRC_Msk (0xful << INT_IRQ13_SRC_INT_SRC_Pos) |
| #define | INT_IRQ14_SRC_INT_SRC_Pos (0) |
| #define | INT_IRQ14_SRC_INT_SRC_Msk (0xful << INT_IRQ14_SRC_INT_SRC_Pos) |
| #define | INT_IRQ15_SRC_INT_SRC_Pos (0) |
| #define | INT_IRQ15_SRC_INT_SRC_Msk (0xful << INT_IRQ15_SRC_INT_SRC_Pos) |
| #define | INT_IRQ16_SRC_INT_SRC_Pos (0) |
| #define | INT_IRQ16_SRC_INT_SRC_Msk (0xful << INT_IRQ16_SRC_INT_SRC_Pos) |
| #define | INT_IRQ17_SRC_INT_SRC_Pos (0) |
| #define | INT_IRQ17_SRC_INT_SRC_Msk (0xful << INT_IRQ17_SRC_INT_SRC_Pos) |
| #define | INT_IRQ18_SRC_INT_SRC_Pos (0) |
| #define | INT_IRQ18_SRC_INT_SRC_Msk (0xful << INT_IRQ18_SRC_INT_SRC_Pos) |
| #define | INT_IRQ19_SRC_INT_SRC_Pos (0) |
| #define | INT_IRQ19_SRC_INT_SRC_Msk (0xful << INT_IRQ19_SRC_INT_SRC_Pos) |
| #define | INT_IRQ20_SRC_INT_SRC_Pos (0) |
| #define | INT_IRQ20_SRC_INT_SRC_Msk (0xful << INT_IRQ20_SRC_INT_SRC_Pos) |
| #define | INT_IRQ21_SRC_INT_SRC_Pos (0) |
| #define | INT_IRQ21_SRC_INT_SRC_Msk (0xful << INT_IRQ21_SRC_INT_SRC_Pos) |
| #define | INT_IRQ22_SRC_INT_SRC_Pos (0) |
| #define | INT_IRQ22_SRC_INT_SRC_Msk (0xful << INT_IRQ22_SRC_INT_SRC_Pos) |
| #define | INT_IRQ23_SRC_INT_SRC_Pos (0) |
| #define | INT_IRQ23_SRC_INT_SRC_Msk (0xful << INT_IRQ23_SRC_INT_SRC_Pos) |
| #define | INT_IRQ24_SRC_INT_SRC_Pos (0) |
| #define | INT_IRQ24_SRC_INT_SRC_Msk (0xful << INT_IRQ24_SRC_INT_SRC_Pos) |
| #define | INT_IRQ25_SRC_INT_SRC_Pos (0) |
| #define | INT_IRQ25_SRC_INT_SRC_Msk (0xful << INT_IRQ25_SRC_INT_SRC_Pos) |
| #define | INT_IRQ26_SRC_INT_SRC_Pos (0) |
| #define | INT_IRQ26_SRC_INT_SRC_Msk (0xful << INT_IRQ26_SRC_INT_SRC_Pos) |
| #define | INT_IRQ27_SRC_INT_SRC_Pos (0) |
| #define | INT_IRQ27_SRC_INT_SRC_Msk (0xful << INT_IRQ27_SRC_INT_SRC_Pos) |
| #define | INT_IRQ28_SRC_INT_SRC_Pos (0) |
| #define | INT_IRQ28_SRC_INT_SRC_Msk (0xful << INT_IRQ28_SRC_INT_SRC_Pos) |
| #define | INT_IRQ29_SRC_INT_SRC_Pos (0) |
| #define | INT_IRQ29_SRC_INT_SRC_Msk (0xful << INT_IRQ29_SRC_INT_SRC_Pos) |
| #define | INT_IRQ30_SRC_INT_SRC_Pos (0) |
| #define | INT_IRQ30_SRC_INT_SRC_Msk (0xful << INT_IRQ30_SRC_INT_SRC_Pos) |
| #define | INT_IRQ31_SRC_INT_SRC_Pos (0) |
| #define | INT_IRQ31_SRC_INT_SRC_Msk (0xful << INT_IRQ31_SRC_INT_SRC_Pos) |
| #define | INT_NMI_SEL_NMI_SEL_Pos (0) |
| #define | INT_NMI_SEL_NMI_SEL_Msk (0x1ful << INT_NMI_SEL_NMI_SEL_Pos) |
| #define | INT_MCU_IRQ_MCU_IRQ_Pos (0) |
| #define | INT_MCU_IRQ_MCU_IRQ_Msk (0xfffffffful << INT_MCU_IRQ_MCU_IRQ_Pos) |
| #define | SYS_PDID_PDID_Pos (0) |
| #define | SYS_PDID_PDID_Msk (0xfffffffful << SYS_PDID_PDID_Pos) |
| #define | SYS_RSTSTS_PORF_Pos (0) |
| #define | SYS_RSTSTS_PORF_Msk (0x1ul << SYS_RSTSTS_PORF_Pos) |
| #define | SYS_RSTSTS_PINRF_Pos (1) |
| #define | SYS_RSTSTS_PINRF_Msk (0x1ul << SYS_RSTSTS_PINRF_Pos) |
| #define | SYS_RSTSTS_WDTRF_Pos (2) |
| #define | SYS_RSTSTS_WDTRF_Msk (0x1ul << SYS_RSTSTS_WDTRF_Pos) |
| #define | SYS_RSTSTS_LVRF_Pos (3) |
| #define | SYS_RSTSTS_LVRF_Msk (0x1ul << SYS_RSTSTS_LVRF_Pos) |
| #define | SYS_RSTSTS_BODRF_Pos (4) |
| #define | SYS_RSTSTS_BODRF_Msk (0x1ul << SYS_RSTSTS_BODRF_Pos) |
| #define | SYS_RSTSTS_SYSRF_Pos (5) |
| #define | SYS_RSTSTS_SYSRF_Msk (0x1ul << SYS_RSTSTS_SYSRF_Pos) |
| #define | SYS_RSTSTS_CPURF_Pos (7) |
| #define | SYS_RSTSTS_CPURF_Msk (0x1ul << SYS_RSTSTS_CPURF_Pos) |
| #define | SYS_RSTSTS_LOCKRF_Pos (8) |
| #define | SYS_RSTSTS_LOCKRF_Msk (0x1ul << SYS_RSTSTS_LOCKRF_Pos) |
| #define | SYS_IPRST1_CHIPRST_Pos (0) |
| #define | SYS_IPRST1_CHIPRST_Msk (0x1ul << SYS_IPRST1_CHIPRST_Pos) |
| #define | SYS_IPRST1_CPURST_Pos (1) |
| #define | SYS_IPRST1_CPURST_Msk (0x1ul << SYS_IPRST1_CPURST_Pos) |
| #define | SYS_IPRST1_PDMARST_Pos (2) |
| #define | SYS_IPRST1_PDMARST_Msk (0x1ul << SYS_IPRST1_PDMARST_Pos) |
| #define | SYS_IPRST2_GPIORST_Pos (1) |
| #define | SYS_IPRST2_GPIORST_Msk (0x1ul << SYS_IPRST2_GPIORST_Pos) |
| #define | SYS_IPRST2_TMR0RST_Pos (2) |
| #define | SYS_IPRST2_TMR0RST_Msk (0x1ul << SYS_IPRST2_TMR0RST_Pos) |
| #define | SYS_IPRST2_TMR1RST_Pos (3) |
| #define | SYS_IPRST2_TMR1RST_Msk (0x1ul << SYS_IPRST2_TMR1RST_Pos) |
| #define | SYS_IPRST2_TMR2RST_Pos (4) |
| #define | SYS_IPRST2_TMR2RST_Msk (0x1ul << SYS_IPRST2_TMR2RST_Pos) |
| #define | SYS_IPRST2_TMR3RST_Pos (5) |
| #define | SYS_IPRST2_TMR3RST_Msk (0x1ul << SYS_IPRST2_TMR3RST_Pos) |
| #define | SYS_IPRST2_I2C0RST_Pos (8) |
| #define | SYS_IPRST2_I2C0RST_Msk (0x1ul << SYS_IPRST2_I2C0RST_Pos) |
| #define | SYS_IPRST2_I2C1RST_Pos (9) |
| #define | SYS_IPRST2_I2C1RST_Msk (0x1ul << SYS_IPRST2_I2C1RST_Pos) |
| #define | SYS_IPRST2_SPI0RST_Pos (12) |
| #define | SYS_IPRST2_SPI0RST_Msk (0x1ul << SYS_IPRST2_SPI0RST_Pos) |
| #define | SYS_IPRST2_SPI1RST_Pos (13) |
| #define | SYS_IPRST2_SPI1RST_Msk (0x1ul << SYS_IPRST2_SPI1RST_Pos) |
| #define | SYS_IPRST2_SPI2RST_Pos (14) |
| #define | SYS_IPRST2_SPI2RST_Msk (0x1ul << SYS_IPRST2_SPI2RST_Pos) |
| #define | SYS_IPRST2_SPI3RST_Pos (15) |
| #define | SYS_IPRST2_SPI3RST_Msk (0x1ul << SYS_IPRST2_SPI3RST_Pos) |
| #define | SYS_IPRST2_UART0RST_Pos (16) |
| #define | SYS_IPRST2_UART0RST_Msk (0x1ul << SYS_IPRST2_UART0RST_Pos) |
| #define | SYS_IPRST2_UART1RST_Pos (17) |
| #define | SYS_IPRST2_UART1RST_Msk (0x1ul << SYS_IPRST2_UART1RST_Pos) |
| #define | SYS_IPRST2_PWM0RST_Pos (20) |
| #define | SYS_IPRST2_PWM0RST_Msk (0x1ul << SYS_IPRST2_PWM0RST_Pos) |
| #define | SYS_IPRST2_ACMP0RST_Pos (22) |
| #define | SYS_IPRST2_ACMP0RST_Msk (0x1ul << SYS_IPRST2_ACMP0RST_Pos) |
| #define | SYS_IPRST2_ADCRST_Pos (28) |
| #define | SYS_IPRST2_ADCRST_Msk (0x1ul << SYS_IPRST2_ADCRST_Pos) |
| #define | SYS_IPRST2_SC0RST_Pos (30) |
| #define | SYS_IPRST2_SC0RST_Msk (0x1ul << SYS_IPRST2_SC0RST_Pos) |
| #define | SYS_IPRST2_SC1RST_Pos (31) |
| #define | SYS_IPRST2_SC1RST_Msk (0x1ul << SYS_IPRST2_SC1RST_Pos) |
| #define | SYS_MISCCTL_POR33DIS_Pos (6) |
| #define | SYS_MISCCTL_POR33DIS_Msk (0x1ul << SYS_MISCCTL_POR33DIS_Pos) |
| #define | SYS_MISCCTL_POR18DIS_Pos (7) |
| #define | SYS_MISCCTL_POR18DIS_Msk (0x1ul << SYS_MISCCTL_POR18DIS_Pos) |
| #define | SYS_TEMPCTL_VTEMPEN_Pos (0) |
| #define | SYS_TEMPCTL_VTEMPEN_Msk (0x1ul << SYS_TEMPCTL_VTEMPEN_Pos) |
| #define | SYS_RCCFCTL_HIRC0FEN_Pos (0) |
| #define | SYS_RCCFCTL_HIRC0FEN_Msk (0x1ul << SYS_RCCFCTL_HIRC0FEN_Pos) |
| #define | SYS_RCCFCTL_HIRC1FEN_Pos (1) |
| #define | SYS_RCCFCTL_HIRC1FEN_Msk (0x1ul << SYS_RCCFCTL_HIRC1FEN_Pos) |
| #define | SYS_RCCFCTL_MRCFEN_Pos (2) |
| #define | SYS_RCCFCTL_MRCFEN_Msk (0x1ul << SYS_RCCFCTL_MRCFEN_Pos) |
| #define | SYS_GPA_MFPL_PA0MFP_Pos (0) |
| #define | SYS_GPA_MFPL_PA0MFP_Msk (0xful << SYS_GPA_MFPL_PA0MFP_Pos) |
| #define | SYS_GPA_MFPL_PA1MFP_Pos (4) |
| #define | SYS_GPA_MFPL_PA1MFP_Msk (0xful << SYS_GPA_MFPL_PA1MFP_Pos) |
| #define | SYS_GPA_MFPL_PA2MFP_Pos (8) |
| #define | SYS_GPA_MFPL_PA2MFP_Msk (0xful << SYS_GPA_MFPL_PA2MFP_Pos) |
| #define | SYS_GPA_MFPL_PA3MFP_Pos (12) |
| #define | SYS_GPA_MFPL_PA3MFP_Msk (0xful << SYS_GPA_MFPL_PA3MFP_Pos) |
| #define | SYS_GPA_MFPL_PA4MFP_Pos (16) |
| #define | SYS_GPA_MFPL_PA4MFP_Msk (0xful << SYS_GPA_MFPL_PA4MFP_Pos) |
| #define | SYS_GPA_MFPL_PA5MFP_Pos (20) |
| #define | SYS_GPA_MFPL_PA5MFP_Msk (0xful << SYS_GPA_MFPL_PA5MFP_Pos) |
| #define | SYS_GPA_MFPL_PA6MFP_Pos (24) |
| #define | SYS_GPA_MFPL_PA6MFP_Msk (0xful << SYS_GPA_MFPL_PA6MFP_Pos) |
| #define | SYS_GPA_MFPH_PA8MFP_Pos (0) |
| #define | SYS_GPA_MFPH_PA8MFP_Msk (0xful << SYS_GPA_MFPH_PA8MFP_Pos) |
| #define | SYS_GPA_MFPH_PA9MFP_Pos (4) |
| #define | SYS_GPA_MFPH_PA9MFP_Msk (0xful << SYS_GPA_MFPH_PA9MFP_Pos) |
| #define | SYS_GPA_MFPH_PA10MFP_Pos (8) |
| #define | SYS_GPA_MFPH_PA10MFP_Msk (0xful << SYS_GPA_MFPH_PA10MFP_Pos) |
| #define | SYS_GPA_MFPH_PA11MFP_Pos (12) |
| #define | SYS_GPA_MFPH_PA11MFP_Msk (0xful << SYS_GPA_MFPH_PA11MFP_Pos) |
| #define | SYS_GPA_MFPH_PA12MFP_Pos (16) |
| #define | SYS_GPA_MFPH_PA12MFP_Msk (0xful << SYS_GPA_MFPH_PA12MFP_Pos) |
| #define | SYS_GPA_MFPH_PA13MFP_Pos (20) |
| #define | SYS_GPA_MFPH_PA13MFP_Msk (0xful << SYS_GPA_MFPH_PA13MFP_Pos) |
| #define | SYS_GPA_MFPH_PA14MFP_Pos (24) |
| #define | SYS_GPA_MFPH_PA14MFP_Msk (0xful << SYS_GPA_MFPH_PA14MFP_Pos) |
| #define | SYS_GPA_MFPH_PA15MFP_Pos (28) |
| #define | SYS_GPA_MFPH_PA15MFP_Msk (0xful << SYS_GPA_MFPH_PA15MFP_Pos) |
| #define | SYS_GPB_MFPL_PB0MFP_Pos (0) |
| #define | SYS_GPB_MFPL_PB0MFP_Msk (0xful << SYS_GPB_MFPL_PB0MFP_Pos) |
| #define | SYS_GPB_MFPL_PB1MFP_Pos (4) |
| #define | SYS_GPB_MFPL_PB1MFP_Msk (0xful << SYS_GPB_MFPL_PB1MFP_Pos) |
| #define | SYS_GPB_MFPL_PB2MFP_Pos (8) |
| #define | SYS_GPB_MFPL_PB2MFP_Msk (0xful << SYS_GPB_MFPL_PB2MFP_Pos) |
| #define | SYS_GPB_MFPL_PB3MFP_Pos (12) |
| #define | SYS_GPB_MFPL_PB3MFP_Msk (0xful << SYS_GPB_MFPL_PB3MFP_Pos) |
| #define | SYS_GPB_MFPL_PB4MFP_Pos (16) |
| #define | SYS_GPB_MFPL_PB4MFP_Msk (0xful << SYS_GPB_MFPL_PB4MFP_Pos) |
| #define | SYS_GPB_MFPL_PB5MFP_Pos (20) |
| #define | SYS_GPB_MFPL_PB5MFP_Msk (0xful << SYS_GPB_MFPL_PB5MFP_Pos) |
| #define | SYS_GPB_MFPL_PB6MFP_Pos (24) |
| #define | SYS_GPB_MFPL_PB6MFP_Msk (0xful << SYS_GPB_MFPL_PB6MFP_Pos) |
| #define | SYS_GPB_MFPL_PB7MFP_Pos (28) |
| #define | SYS_GPB_MFPL_PB7MFP_Msk (0xful << SYS_GPB_MFPL_PB7MFP_Pos) |
| #define | SYS_GPB_MFPH_PB8MFP_Pos (0) |
| #define | SYS_GPB_MFPH_PB8MFP_Msk (0xful << SYS_GPB_MFPH_PB8MFP_Pos) |
| #define | SYS_GPB_MFPH_PB9MFP_Pos (4) |
| #define | SYS_GPB_MFPH_PB9MFP_Msk (0xful << SYS_GPB_MFPH_PB9MFP_Pos) |
| #define | SYS_GPB_MFPH_PB10MFP_Pos (8) |
| #define | SYS_GPB_MFPH_PB10MFP_Msk (0xful << SYS_GPB_MFPH_PB10MFP_Pos) |
| #define | SYS_GPB_MFPH_PB11MFP_Pos (12) |
| #define | SYS_GPB_MFPH_PB11MFP_Msk (0xful << SYS_GPB_MFPH_PB11MFP_Pos) |
| #define | SYS_GPB_MFPH_PB13MFP_Pos (20) |
| #define | SYS_GPB_MFPH_PB13MFP_Msk (0xful << SYS_GPB_MFPH_PB13MFP_Pos) |
| #define | SYS_GPB_MFPH_PB14MFP_Pos (24) |
| #define | SYS_GPB_MFPH_PB14MFP_Msk (0xful << SYS_GPB_MFPH_PB14MFP_Pos) |
| #define | SYS_GPB_MFPH_PB15MFP_Pos (28) |
| #define | SYS_GPB_MFPH_PB15MFP_Msk (0xful << SYS_GPB_MFPH_PB15MFP_Pos) |
| #define | SYS_GPC_MFPL_PC0MFP_Pos (0) |
| #define | SYS_GPC_MFPL_PC0MFP_Msk (0xful << SYS_GPC_MFPL_PC0MFP_Pos) |
| #define | SYS_GPC_MFPL_PC1MFP_Pos (4) |
| #define | SYS_GPC_MFPL_PC1MFP_Msk (0xful << SYS_GPC_MFPL_PC1MFP_Pos) |
| #define | SYS_GPC_MFPL_PC2MFP_Pos (8) |
| #define | SYS_GPC_MFPL_PC2MFP_Msk (0xful << SYS_GPC_MFPL_PC2MFP_Pos) |
| #define | SYS_GPC_MFPL_PC3MFP_Pos (12) |
| #define | SYS_GPC_MFPL_PC3MFP_Msk (0xful << SYS_GPC_MFPL_PC3MFP_Pos) |
| #define | SYS_GPC_MFPL_PC6MFP_Pos (24) |
| #define | SYS_GPC_MFPL_PC6MFP_Msk (0xful << SYS_GPC_MFPL_PC6MFP_Pos) |
| #define | SYS_GPC_MFPL_PC7MFP_Pos (28) |
| #define | SYS_GPC_MFPL_PC7MFP_Msk (0xful << SYS_GPC_MFPL_PC7MFP_Pos) |
| #define | SYS_GPC_MFPH_PC8MFP_Pos (0) |
| #define | SYS_GPC_MFPH_PC8MFP_Msk (0xful << SYS_GPC_MFPH_PC8MFP_Pos) |
| #define | SYS_GPC_MFPH_PC9MFP_Pos (4) |
| #define | SYS_GPC_MFPH_PC9MFP_Msk (0xful << SYS_GPC_MFPH_PC9MFP_Pos) |
| #define | SYS_GPC_MFPH_PC10MFP_Pos (8) |
| #define | SYS_GPC_MFPH_PC10MFP_Msk (0xful << SYS_GPC_MFPH_PC10MFP_Pos) |
| #define | SYS_GPC_MFPH_PC11MFP_Pos (12) |
| #define | SYS_GPC_MFPH_PC11MFP_Msk (0xful << SYS_GPC_MFPH_PC11MFP_Pos) |
| #define | SYS_GPC_MFPH_PC14MFP_Pos (24) |
| #define | SYS_GPC_MFPH_PC14MFP_Msk (0xful << SYS_GPC_MFPH_PC14MFP_Pos) |
| #define | SYS_GPC_MFPH_PC15MFP_Pos (28) |
| #define | SYS_GPC_MFPH_PC15MFP_Msk (0xful << SYS_GPC_MFPH_PC15MFP_Pos) |
| #define | SYS_GPD_MFPL_PD6MFP_Pos (24) |
| #define | SYS_GPD_MFPL_PD6MFP_Msk (0xful << SYS_GPD_MFPL_PD6MFP_Pos) |
| #define | SYS_GPD_MFPL_PD7MFP_Pos (28) |
| #define | SYS_GPD_MFPL_PD7MFP_Msk (0xful << SYS_GPD_MFPL_PD7MFP_Pos) |
| #define | SYS_GPD_MFPH_PD14MFP_Pos (24) |
| #define | SYS_GPD_MFPH_PD14MFP_Msk (0xful << SYS_GPD_MFPH_PD14MFP_Pos) |
| #define | SYS_GPD_MFPH_PD15MFP_Pos (28) |
| #define | SYS_GPD_MFPH_PD15MFP_Msk (0x7ul << SYS_GPD_MFPH_PD15MFP_Pos) |
| #define | SYS_GPE_MFPL_PE5MFP_Pos (20) |
| #define | SYS_GPE_MFPL_PE5MFP_Msk (0xful << SYS_GPE_MFPL_PE5MFP_Pos) |
| #define | SYS_GPF_MFPL_PF0MFP_Pos (0) |
| #define | SYS_GPF_MFPL_PF0MFP_Msk (0xful << SYS_GPF_MFPL_PF0MFP_Pos) |
| #define | SYS_GPF_MFPL_PF1MFP_Pos (4) |
| #define | SYS_GPF_MFPL_PF1MFP_Msk (0xful << SYS_GPF_MFPL_PF1MFP_Pos) |
| #define | SYS_GPF_MFPL_PF2MFP_Pos (8) |
| #define | SYS_GPF_MFPL_PF2MFP_Msk (0xful << SYS_GPF_MFPL_PF2MFP_Pos) |
| #define | SYS_GPF_MFPL_PF3MFP_Pos (12) |
| #define | SYS_GPF_MFPL_PF3MFP_Msk (0xful << SYS_GPF_MFPL_PF3MFP_Pos) |
| #define | SYS_GPF_MFPL_PF6MFP_Pos (24) |
| #define | SYS_GPF_MFPL_PF6MFP_Msk (0xful << SYS_GPF_MFPL_PF6MFP_Pos) |
| #define | SYS_GPF_MFPL_PF7MFP_Pos (28) |
| #define | SYS_GPF_MFPL_PF7MFP_Msk (0xful << SYS_GPF_MFPL_PF7MFP_Pos) |
| #define | SYS_PORCTL_POROFF_Pos (0) |
| #define | SYS_PORCTL_POROFF_Msk (0xfffful << SYS_PORCTL_POROFF_Pos) |
| #define | SYS_BODCTL_BODEN_Pos (0) |
| #define | SYS_BODCTL_BODEN_Msk (0x1ul << SYS_BODCTL_BODEN_Pos) |
| #define | SYS_BODCTL_BODIE_Pos (2) |
| #define | SYS_BODCTL_BODIE_Msk (0x1ul << SYS_BODCTL_BODIE_Pos) |
| #define | SYS_BODCTL_BODREN_Pos (3) |
| #define | SYS_BODCTL_BODREN_Msk (0x1ul << SYS_BODCTL_BODREN_Pos) |
| #define | SYS_BODCTL_BODIF_Pos (4) |
| #define | SYS_BODCTL_BODIF_Msk (0x1ul << SYS_BODCTL_BODIF_Pos) |
| #define | SYS_BODCTL_BODOUT_Pos (6) |
| #define | SYS_BODCTL_BODOUT_Msk (0x1ul << SYS_BODCTL_BODOUT_Pos) |
| #define | SYS_BODCTL_LVREN_Pos (7) |
| #define | SYS_BODCTL_LVREN_Msk (0x1ul << SYS_BODCTL_LVREN_Pos) |
| #define | SYS_BODCTL_LPBODEN_Pos (8) |
| #define | SYS_BODCTL_LPBODEN_Msk (0x1ul << SYS_BODCTL_LPBODEN_Pos) |
| #define | SYS_BODCTL_LPBODVL_Pos (9) |
| #define | SYS_BODCTL_LPBODVL_Msk (0x1ul << SYS_BODCTL_LPBODVL_Pos) |
| #define | SYS_BODCTL_LPBODIE_Pos (10) |
| #define | SYS_BODCTL_LPBODIE_Msk (0x1ul << SYS_BODCTL_LPBODIE_Pos) |
| #define | SYS_BODCTL_LPBODREN_Pos (11) |
| #define | SYS_BODCTL_LPBODREN_Msk (0x1ul << SYS_BODCTL_LPBODREN_Pos) |
| #define | SYS_BODCTL_BODVL_Pos (12) |
| #define | SYS_BODCTL_BODVL_Msk (0xful << SYS_BODCTL_BODVL_Pos) |
| #define | SYS_BODCTL_LPBOD20TRIM_Pos (16) |
| #define | SYS_BODCTL_LPBOD20TRIM_Msk (0xful << SYS_BODCTL_LPBOD20TRIM_Pos) |
| #define | SYS_BODCTL_LPBOD25TRIM_Pos (20) |
| #define | SYS_BODCTL_LPBOD25TRIM_Msk (0xful << SYS_BODCTL_LPBOD25TRIM_Pos) |
| #define | SYS_BODCTL_BODDGSEL_Pos (24) |
| #define | SYS_BODCTL_BODDGSEL_Msk (0x7ul << SYS_BODCTL_BODDGSEL_Pos) |
| #define | SYS_BODCTL_LVRDGSEL_Pos (28) |
| #define | SYS_BODCTL_LVRDGSEL_Msk (0x7ul << SYS_BODCTL_LVRDGSEL_Pos) |
| #define | SYS_IVREFCTL_BGPEN_Pos (0) |
| #define | SYS_IVREFCTL_BGPEN_Msk (0x1ul << SYS_IVREFCTL_BGPEN_Pos) |
| #define | SYS_IVREFCTL_REGEN_Pos (1) |
| #define | SYS_IVREFCTL_REGEN_Msk (0x1ul << SYS_IVREFCTL_REGEN_Pos) |
| #define | SYS_IVREFCTL_SEL25_Pos (2) |
| #define | SYS_IVREFCTL_SEL25_Msk (0x3ul << SYS_IVREFCTL_SEL25_Pos) |
| #define | SYS_IVREFCTL_EXTMODE_Pos (4) |
| #define | SYS_IVREFCTL_EXTMODE_Msk (0x1ul << SYS_IVREFCTL_EXTMODE_Pos) |
| #define | SYS_IVREFCTL_VREFTRIM_Pos (8) |
| #define | SYS_IVREFCTL_VREFTRIM_Msk (0xful << SYS_IVREFCTL_VREFTRIM_Pos) |
| #define | SYS_LDOCTL_FASTWK_Pos (1) |
| #define | SYS_LDOCTL_FASTWK_Msk (0x1ul << SYS_LDOCTL_FASTWK_Pos) |
| #define | SYS_LDOCTL_LDOLVL_Pos (2) |
| #define | SYS_LDOCTL_LDOLVL_Msk (0x3ul << SYS_LDOCTL_LDOLVL_Pos) |
| #define | SYS_LDOCTL_LPRMEN_Pos (4) |
| #define | SYS_LDOCTL_LPRMEN_Msk (0x1ul << SYS_LDOCTL_LPRMEN_Pos) |
| #define | SYS_LDOCTL_FMCLVEN_Pos (5) |
| #define | SYS_LDOCTL_FMCLVEN_Msk (0x1ul << SYS_LDOCTL_FMCLVEN_Pos) |
| #define | SYS_BATDIVCTL_BATDIV2EN_Pos (0) |
| #define | SYS_BATDIVCTL_BATDIV2EN_Msk (0x1ul << SYS_BATDIVCTL_BATDIV2EN_Pos) |
| #define | SYS_WKSTS_ACMPWK_Pos (0) |
| #define | SYS_WKSTS_ACMPWK_Msk (0x1ul << SYS_WKSTS_ACMPWK_Pos) |
| #define | SYS_WKSTS_I2C1WK_Pos (1) |
| #define | SYS_WKSTS_I2C1WK_Msk (0x1ul << SYS_WKSTS_I2C1WK_Pos) |
| #define | SYS_WKSTS_I2C0WK_Pos (2) |
| #define | SYS_WKSTS_I2C0WK_Msk (0x1ul << SYS_WKSTS_I2C0WK_Pos) |
| #define | SYS_WKSTS_TMR3WK_Pos (3) |
| #define | SYS_WKSTS_TMR3WK_Msk (0x1ul << SYS_WKSTS_TMR3WK_Pos) |
| #define | SYS_WKSTS_TMR2WK_Pos (4) |
| #define | SYS_WKSTS_TMR2WK_Msk (0x1ul << SYS_WKSTS_TMR2WK_Pos) |
| #define | SYS_WKSTS_TMR1WK_Pos (5) |
| #define | SYS_WKSTS_TMR1WK_Msk (0x1ul << SYS_WKSTS_TMR1WK_Pos) |
| #define | SYS_WKSTS_TMR0WK_Pos (6) |
| #define | SYS_WKSTS_TMR0WK_Msk (0x1ul << SYS_WKSTS_TMR0WK_Pos) |
| #define | SYS_WKSTS_WDTWK_Pos (7) |
| #define | SYS_WKSTS_WDTWK_Msk (0x1ul << SYS_WKSTS_WDTWK_Pos) |
| #define | SYS_WKSTS_BODWK_Pos (8) |
| #define | SYS_WKSTS_BODWK_Msk (0x1ul << SYS_WKSTS_BODWK_Pos) |
| #define | SYS_WKSTS_SPI3WK_Pos (9) |
| #define | SYS_WKSTS_SPI3WK_Msk (0x1ul << SYS_WKSTS_SPI3WK_Pos) |
| #define | SYS_WKSTS_SPI2WK_Pos (10) |
| #define | SYS_WKSTS_SPI2WK_Msk (0x1ul << SYS_WKSTS_SPI2WK_Pos) |
| #define | SYS_WKSTS_SPI1WK_Pos (11) |
| #define | SYS_WKSTS_SPI1WK_Msk (0x1ul << SYS_WKSTS_SPI1WK_Pos) |
| #define | SYS_WKSTS_SPI0WK_Pos (12) |
| #define | SYS_WKSTS_SPI0WK_Msk (0x1ul << SYS_WKSTS_SPI0WK_Pos) |
| #define | SYS_WKSTS_UART1WK_Pos (13) |
| #define | SYS_WKSTS_UART1WK_Msk (0x1ul << SYS_WKSTS_UART1WK_Pos) |
| #define | SYS_WKSTS_UART0WK_Pos (14) |
| #define | SYS_WKSTS_UART0WK_Msk (0x1ul << SYS_WKSTS_UART0WK_Pos) |
| #define | SYS_WKSTS_RTCWK_Pos (15) |
| #define | SYS_WKSTS_RTCWK_Msk (0x1ul << SYS_WKSTS_RTCWK_Pos) |
| #define | SYS_WKSTS_GPIOWK_Pos (16) |
| #define | SYS_WKSTS_GPIOWK_Msk (0x1ul << SYS_WKSTS_GPIOWK_Pos) |
| #define | SYS_IRC0TCTL_FREQSEL_Pos (0) |
| #define | SYS_IRC0TCTL_FREQSEL_Msk (0x7ul << SYS_IRC0TCTL_FREQSEL_Pos) |
| #define | SYS_IRC0TCTL_LOOPSEL_Pos (4) |
| #define | SYS_IRC0TCTL_LOOPSEL_Msk (0x3ul << SYS_IRC0TCTL_LOOPSEL_Pos) |
| #define | SYS_IRC0TCTL_RETRYCNT_Pos (6) |
| #define | SYS_IRC0TCTL_RETRYCNT_Msk (0x3ul << SYS_IRC0TCTL_RETRYCNT_Pos) |
| #define | SYS_IRC0TCTL_CESTOPEN_Pos (8) |
| #define | SYS_IRC0TCTL_CESTOPEN_Msk (0x1ul << SYS_IRC0TCTL_CESTOPEN_Pos) |
| #define | SYS_IRC0TIEN_TFAILIEN_Pos (1) |
| #define | SYS_IRC0TIEN_TFAILIEN_Msk (0x1ul << SYS_IRC0TIEN_TFAILIEN_Pos) |
| #define | SYS_IRC0TIEN_CLKEIEN_Pos (2) |
| #define | SYS_IRC0TIEN_CLKEIEN_Msk (0x1ul << SYS_IRC0TIEN_CLKEIEN_Pos) |
| #define | SYS_IRC0TISTS_FREQLOCK_Pos (0) |
| #define | SYS_IRC0TISTS_FREQLOCK_Msk (0x1ul << SYS_IRC0TISTS_FREQLOCK_Pos) |
| #define | SYS_IRC0TISTS_TFAILIF_Pos (1) |
| #define | SYS_IRC0TISTS_TFAILIF_Msk (0x1ul << SYS_IRC0TISTS_TFAILIF_Pos) |
| #define | SYS_IRC0TISTS_CLKERRIF_Pos (2) |
| #define | SYS_IRC0TISTS_CLKERRIF_Msk (0x1ul << SYS_IRC0TISTS_CLKERRIF_Pos) |
| #define | SYS_IRC1TCTL_FREQSEL_Pos (0) |
| #define | SYS_IRC1TCTL_FREQSEL_Msk (0x3ul << SYS_IRC1TCTL_FREQSEL_Pos) |
| #define | SYS_IRC1TCTL_LOOPSEL_Pos (4) |
| #define | SYS_IRC1TCTL_LOOPSEL_Msk (0x3ul << SYS_IRC1TCTL_LOOPSEL_Pos) |
| #define | SYS_IRC1TCTL_RETRYCNT_Pos (6) |
| #define | SYS_IRC1TCTL_RETRYCNT_Msk (0x3ul << SYS_IRC1TCTL_RETRYCNT_Pos) |
| #define | SYS_IRC1TCTL_CESTOPEN_Pos (8) |
| #define | SYS_IRC1TCTL_CESTOPEN_Msk (0x1ul << SYS_IRC1TCTL_CESTOPEN_Pos) |
| #define | SYS_IRC1TIEN_TFAILIEN_Pos (1) |
| #define | SYS_IRC1TIEN_TFAILIEN_Msk (0x1ul << SYS_IRC1TIEN_TFAILIEN_Pos) |
| #define | SYS_IRC1TIEN_CLKEIEN_Pos (2) |
| #define | SYS_IRC1TIEN_CLKEIEN_Msk (0x1ul << SYS_IRC1TIEN_CLKEIEN_Pos) |
| #define | SYS_IRC1TISTS_FREQLOCK_Pos (0) |
| #define | SYS_IRC1TISTS_FREQLOCK_Msk (0x1ul << SYS_IRC1TISTS_FREQLOCK_Pos) |
| #define | SYS_IRC1TISTS_TFAILIF_Pos (1) |
| #define | SYS_IRC1TISTS_TFAILIF_Msk (0x1ul << SYS_IRC1TISTS_TFAILIF_Pos) |
| #define | SYS_IRC1TISTS_CLKERRIF_Pos (2) |
| #define | SYS_IRC1TISTS_CLKERRIF_Msk (0x1ul << SYS_IRC1TISTS_CLKERRIF_Pos) |
| #define | SYS_MIRCTCTL_FREQSEL_Pos (0) |
| #define | SYS_MIRCTCTL_FREQSEL_Msk (0x3ul << SYS_MIRCTCTL_FREQSEL_Pos) |
| #define | SYS_MIRCTCTL_LOOPSEL_Pos (4) |
| #define | SYS_MIRCTCTL_LOOPSEL_Msk (0x3ul << SYS_MIRCTCTL_LOOPSEL_Pos) |
| #define | SYS_MIRCTCTL_RETRYCNT_Pos (6) |
| #define | SYS_MIRCTCTL_RETRYCNT_Msk (0x3ul << SYS_MIRCTCTL_RETRYCNT_Pos) |
| #define | SYS_MIRCTCTL_CESTOPEN_Pos (8) |
| #define | SYS_MIRCTCTL_CESTOPEN_Msk (0x1ul << SYS_MIRCTCTL_CESTOPEN_Pos) |
| #define | SYS_MIRCTIEN_TFAILIEN_Pos (1) |
| #define | SYS_MIRCTIEN_TFAILIEN_Msk (0x1ul << SYS_MIRCTIEN_TFAILIEN_Pos) |
| #define | SYS_MIRCTIEN_CLKEIEN_Pos (2) |
| #define | SYS_MIRCTIEN_CLKEIEN_Msk (0x1ul << SYS_MIRCTIEN_CLKEIEN_Pos) |
| #define | SYS_MIRCTISTS_FREQLOCK_Pos (0) |
| #define | SYS_MIRCTISTS_FREQLOCK_Msk (0x1ul << SYS_MIRCTISTS_FREQLOCK_Pos) |
| #define | SYS_MIRCTISTS_TFAILIF_Pos (1) |
| #define | SYS_MIRCTISTS_TFAILIF_Msk (0x1ul << SYS_MIRCTISTS_TFAILIF_Pos) |
| #define | SYS_MIRCTISTS_CLKERRIF_Pos (2) |
| #define | SYS_MIRCTISTS_CLKERRIF_Msk (0x1ul << SYS_MIRCTISTS_CLKERRIF_Pos) |
| #define | SYS_REGLCTL_REGLCTL_Pos (0) |
| #define | SYS_REGLCTL_REGLCTL_Msk (0x1ul << SYS_REGLCTL_REGLCTL_Pos) |
| #define | SYS_RPDBCLK_RSTPDBCLK_Pos (6) |
| #define | SYS_RPDBCLK_RSTPDBCLK_Msk (0x1ul << SYS_RPDBCLK_RSTPDBCLK_Pos) |
| #define | CLK_PWRCTL_HXTEN_Pos (0) |
| #define | CLK_PWRCTL_HXTEN_Msk (0x1ul << CLK_PWRCTL_HXTEN_Pos) |
| #define | CLK_PWRCTL_LXTEN_Pos (1) |
| #define | CLK_PWRCTL_LXTEN_Msk (0x1ul << CLK_PWRCTL_LXTEN_Pos) |
| #define | CLK_PWRCTL_HIRC0EN_Pos (2) |
| #define | CLK_PWRCTL_HIRC0EN_Msk (0x1ul << CLK_PWRCTL_HIRC0EN_Pos) |
| #define | CLK_PWRCTL_LIRCEN_Pos (3) |
| #define | CLK_PWRCTL_LIRCEN_Msk (0x1ul << CLK_PWRCTL_LIRCEN_Pos) |
| #define | CLK_PWRCTL_PDWKDLY_Pos (4) |
| #define | CLK_PWRCTL_PDWKDLY_Msk (0x1ul << CLK_PWRCTL_PDWKDLY_Pos) |
| #define | CLK_PWRCTL_PDWKIEN_Pos (5) |
| #define | CLK_PWRCTL_PDWKIEN_Msk (0x1ul << CLK_PWRCTL_PDWKIEN_Pos) |
| #define | CLK_PWRCTL_PDEN_Pos (6) |
| #define | CLK_PWRCTL_PDEN_Msk (0x1ul << CLK_PWRCTL_PDEN_Pos) |
| #define | CLK_PWRCTL_HXTSLTYP_Pos (8) |
| #define | CLK_PWRCTL_HXTSLTYP_Msk (0x1ul << CLK_PWRCTL_HXTSLTYP_Pos) |
| #define | CLK_PWRCTL_HXTGAIN_Pos (10) |
| #define | CLK_PWRCTL_HXTGAIN_Msk (0x7ul << CLK_PWRCTL_HXTGAIN_Pos) |
| #define | CLK_PWRCTL_HIRC0FSEL_Pos (13) |
| #define | CLK_PWRCTL_HIRC0FSEL_Msk (0x1ul << CLK_PWRCTL_HIRC0FSEL_Pos) |
| #define | CLK_PWRCTL_HIRC0FSTOP_Pos (14) |
| #define | CLK_PWRCTL_HIRC0FSTOP_Msk (0x1ul << CLK_PWRCTL_HIRC0FSTOP_Pos) |
| #define | CLK_PWRCTL_HIRC1EN_Pos (24) |
| #define | CLK_PWRCTL_HIRC1EN_Msk (0x1ul << CLK_PWRCTL_HIRC1EN_Pos) |
| #define | CLK_PWRCTL_MIRCEN_Pos (25) |
| #define | CLK_PWRCTL_MIRCEN_Msk (0x1ul << CLK_PWRCTL_MIRCEN_Pos) |
| #define | CLK_AHBCLK_GPIOCKEN_Pos (0) |
| #define | CLK_AHBCLK_GPIOCKEN_Msk (0x1ul << CLK_AHBCLK_GPIOCKEN_Pos) |
| #define | CLK_AHBCLK_PDMACKEN_Pos (1) |
| #define | CLK_AHBCLK_PDMACKEN_Msk (0x1ul << CLK_AHBCLK_PDMACKEN_Pos) |
| #define | CLK_AHBCLK_ISPCKEN_Pos (2) |
| #define | CLK_AHBCLK_ISPCKEN_Msk (0x1ul << CLK_AHBCLK_ISPCKEN_Pos) |
| #define | CLK_AHBCLK_SRAMCKEN_Pos (4) |
| #define | CLK_AHBCLK_SRAMCKEN_Msk (0x1ul << CLK_AHBCLK_SRAMCKEN_Pos) |
| #define | CLK_AHBCLK_STCKEN_Pos (5) |
| #define | CLK_AHBCLK_STCKEN_Msk (0x1ul << CLK_AHBCLK_STCKEN_Pos) |
| #define | CLK_APBCLK_WDTCKEN_Pos (0) |
| #define | CLK_APBCLK_WDTCKEN_Msk (0x1ul << CLK_APBCLK_WDTCKEN_Pos) |
| #define | CLK_APBCLK_RTCCKEN_Pos (1) |
| #define | CLK_APBCLK_RTCCKEN_Msk (0x1ul << CLK_APBCLK_RTCCKEN_Pos) |
| #define | CLK_APBCLK_TMR0CKEN_Pos (2) |
| #define | CLK_APBCLK_TMR0CKEN_Msk (0x1ul << CLK_APBCLK_TMR0CKEN_Pos) |
| #define | CLK_APBCLK_TMR1CKEN_Pos (3) |
| #define | CLK_APBCLK_TMR1CKEN_Msk (0x1ul << CLK_APBCLK_TMR1CKEN_Pos) |
| #define | CLK_APBCLK_TMR2CKEN_Pos (4) |
| #define | CLK_APBCLK_TMR2CKEN_Msk (0x1ul << CLK_APBCLK_TMR2CKEN_Pos) |
| #define | CLK_APBCLK_TMR3CKEN_Pos (5) |
| #define | CLK_APBCLK_TMR3CKEN_Msk (0x1ul << CLK_APBCLK_TMR3CKEN_Pos) |
| #define | CLK_APBCLK_CLKOCKEN_Pos (6) |
| #define | CLK_APBCLK_CLKOCKEN_Msk (0x1ul << CLK_APBCLK_CLKOCKEN_Pos) |
| #define | CLK_APBCLK_I2C0CKEN_Pos (8) |
| #define | CLK_APBCLK_I2C0CKEN_Msk (0x1ul << CLK_APBCLK_I2C0CKEN_Pos) |
| #define | CLK_APBCLK_I2C1CKEN_Pos (9) |
| #define | CLK_APBCLK_I2C1CKEN_Msk (0x1ul << CLK_APBCLK_I2C1CKEN_Pos) |
| #define | CLK_APBCLK_ACMP0CKEN_Pos (11) |
| #define | CLK_APBCLK_ACMP0CKEN_Msk (0x1ul << CLK_APBCLK_ACMP0CKEN_Pos) |
| #define | CLK_APBCLK_SPI0CKEN_Pos (12) |
| #define | CLK_APBCLK_SPI0CKEN_Msk (0x1ul << CLK_APBCLK_SPI0CKEN_Pos) |
| #define | CLK_APBCLK_SPI1CKEN_Pos (13) |
| #define | CLK_APBCLK_SPI1CKEN_Msk (0x1ul << CLK_APBCLK_SPI1CKEN_Pos) |
| #define | CLK_APBCLK_SPI2CKEN_Pos (14) |
| #define | CLK_APBCLK_SPI2CKEN_Msk (0x1ul << CLK_APBCLK_SPI2CKEN_Pos) |
| #define | CLK_APBCLK_SPI3CKEN_Pos (15) |
| #define | CLK_APBCLK_SPI3CKEN_Msk (0x1ul << CLK_APBCLK_SPI3CKEN_Pos) |
| #define | CLK_APBCLK_UART0CKEN_Pos (16) |
| #define | CLK_APBCLK_UART0CKEN_Msk (0x1ul << CLK_APBCLK_UART0CKEN_Pos) |
| #define | CLK_APBCLK_UART1CKEN_Pos (17) |
| #define | CLK_APBCLK_UART1CKEN_Msk (0x1ul << CLK_APBCLK_UART1CKEN_Pos) |
| #define | CLK_APBCLK_PWM0CKEN_Pos (20) |
| #define | CLK_APBCLK_PWM0CKEN_Msk (0x1ul << CLK_APBCLK_PWM0CKEN_Pos) |
| #define | CLK_APBCLK_ADCCKEN_Pos (28) |
| #define | CLK_APBCLK_ADCCKEN_Msk (0x1ul << CLK_APBCLK_ADCCKEN_Pos) |
| #define | CLK_APBCLK_SC0CKEN_Pos (30) |
| #define | CLK_APBCLK_SC0CKEN_Msk (0x1ul << CLK_APBCLK_SC0CKEN_Pos) |
| #define | CLK_APBCLK_SC1CKEN_Pos (31) |
| #define | CLK_APBCLK_SC1CKEN_Msk (0x1ul << CLK_APBCLK_SC1CKEN_Pos) |
| #define | CLK_STATUS_HXTSTB_Pos (0) |
| #define | CLK_STATUS_HXTSTB_Msk (0x1ul << CLK_STATUS_HXTSTB_Pos) |
| #define | CLK_STATUS_LXTSTB_Pos (1) |
| #define | CLK_STATUS_LXTSTB_Msk (0x1ul << CLK_STATUS_LXTSTB_Pos) |
| #define | CLK_STATUS_PLLSTB_Pos (2) |
| #define | CLK_STATUS_PLLSTB_Msk (0x1ul << CLK_STATUS_PLLSTB_Pos) |
| #define | CLK_STATUS_LIRCSTB_Pos (3) |
| #define | CLK_STATUS_LIRCSTB_Msk (0x1ul << CLK_STATUS_LIRCSTB_Pos) |
| #define | CLK_STATUS_HIRC0STB_Pos (4) |
| #define | CLK_STATUS_HIRC0STB_Msk (0x1ul << CLK_STATUS_HIRC0STB_Pos) |
| #define | CLK_STATUS_HIRC1STB_Pos (5) |
| #define | CLK_STATUS_HIRC1STB_Msk (0x1ul << CLK_STATUS_HIRC1STB_Pos) |
| #define | CLK_STATUS_MIRCSTB_Pos (6) |
| #define | CLK_STATUS_MIRCSTB_Msk (0x1ul << CLK_STATUS_MIRCSTB_Pos) |
| #define | CLK_STATUS_CLKSFAIL_Pos (7) |
| #define | CLK_STATUS_CLKSFAIL_Msk (0x1ul << CLK_STATUS_CLKSFAIL_Pos) |
| #define | CLK_CLKSEL0_HCLKSEL_Pos (0) |
| #define | CLK_CLKSEL0_HCLKSEL_Msk (0x7ul << CLK_CLKSEL0_HCLKSEL_Pos) |
| #define | CLK_CLKSEL0_HIRCSEL_Pos (3) |
| #define | CLK_CLKSEL0_HIRCSEL_Msk (0x1ul << CLK_CLKSEL0_HIRCSEL_Pos) |
| #define | CLK_CLKSEL0_ISPSEL_Pos (4) |
| #define | CLK_CLKSEL0_ISPSEL_Msk (0x1ul << CLK_CLKSEL0_ISPSEL_Pos) |
| #define | CLK_CLKSEL1_UART0SEL_Pos (0) |
| #define | CLK_CLKSEL1_UART0SEL_Msk (0x7ul << CLK_CLKSEL1_UART0SEL_Pos) |
| #define | CLK_CLKSEL1_PWM0SEL_Pos (4) |
| #define | CLK_CLKSEL1_PWM0SEL_Msk (0x1ul << CLK_CLKSEL1_PWM0SEL_Pos) |
| #define | CLK_CLKSEL1_TMR0SEL_Pos (8) |
| #define | CLK_CLKSEL1_TMR0SEL_Msk (0x7ul << CLK_CLKSEL1_TMR0SEL_Pos) |
| #define | CLK_CLKSEL1_TMR1SEL_Pos (12) |
| #define | CLK_CLKSEL1_TMR1SEL_Msk (0x7ul << CLK_CLKSEL1_TMR1SEL_Pos) |
| #define | CLK_CLKSEL1_ADCSEL_Pos (19) |
| #define | CLK_CLKSEL1_ADCSEL_Msk (0x7ul << CLK_CLKSEL1_ADCSEL_Pos) |
| #define | CLK_CLKSEL1_SPI0SEL_Pos (24) |
| #define | CLK_CLKSEL1_SPI0SEL_Msk (0x3ul << CLK_CLKSEL1_SPI0SEL_Pos) |
| #define | CLK_CLKSEL1_SPI2SEL_Pos (26) |
| #define | CLK_CLKSEL1_SPI2SEL_Msk (0x3ul << CLK_CLKSEL1_SPI2SEL_Pos) |
| #define | CLK_CLKSEL1_WDTSEL_Pos (28) |
| #define | CLK_CLKSEL1_WDTSEL_Msk (0x3ul << CLK_CLKSEL1_WDTSEL_Pos) |
| #define | CLK_CLKSEL1_WWDTSEL_Pos (30) |
| #define | CLK_CLKSEL1_WWDTSEL_Msk (0x3ul << CLK_CLKSEL1_WWDTSEL_Pos) |
| #define | CLK_CLKSEL2_UART1SEL_Pos (0) |
| #define | CLK_CLKSEL2_UART1SEL_Msk (0x7ul << CLK_CLKSEL2_UART1SEL_Pos) |
| #define | CLK_CLKSEL2_CLKOSEL_Pos (4) |
| #define | CLK_CLKSEL2_CLKOSEL_Msk (0x7ul << CLK_CLKSEL2_CLKOSEL_Pos) |
| #define | CLK_CLKSEL2_TMR2SEL_Pos (8) |
| #define | CLK_CLKSEL2_TMR2SEL_Msk (0x7ul << CLK_CLKSEL2_TMR2SEL_Pos) |
| #define | CLK_CLKSEL2_TMR3SEL_Pos (12) |
| #define | CLK_CLKSEL2_TMR3SEL_Msk (0x7ul << CLK_CLKSEL2_TMR3SEL_Pos) |
| #define | CLK_CLKSEL2_SC0SEL_Pos (16) |
| #define | CLK_CLKSEL2_SC0SEL_Msk (0x7ul << CLK_CLKSEL2_SC0SEL_Pos) |
| #define | CLK_CLKSEL2_SC1SEL_Pos (20) |
| #define | CLK_CLKSEL2_SC1SEL_Msk (0x7ul << CLK_CLKSEL2_SC1SEL_Pos) |
| #define | CLK_CLKSEL2_SPI1SEL_Pos (24) |
| #define | CLK_CLKSEL2_SPI1SEL_Msk (0x3ul << CLK_CLKSEL2_SPI1SEL_Pos) |
| #define | CLK_CLKSEL2_SPI3SEL_Pos (26) |
| #define | CLK_CLKSEL2_SPI3SEL_Msk (0x3ul << CLK_CLKSEL2_SPI3SEL_Pos) |
| #define | CLK_CLKDIV0_HCLKDIV_Pos (0) |
| #define | CLK_CLKDIV0_HCLKDIV_Msk (0xful << CLK_CLKDIV0_HCLKDIV_Pos) |
| #define | CLK_CLKDIV0_UART0DIV_Pos (8) |
| #define | CLK_CLKDIV0_UART0DIV_Msk (0xful << CLK_CLKDIV0_UART0DIV_Pos) |
| #define | CLK_CLKDIV0_UART1DIV_Pos (12) |
| #define | CLK_CLKDIV0_UART1DIV_Msk (0xful << CLK_CLKDIV0_UART1DIV_Pos) |
| #define | CLK_CLKDIV0_ADCDIV_Pos (16) |
| #define | CLK_CLKDIV0_ADCDIV_Msk (0xfful << CLK_CLKDIV0_ADCDIV_Pos) |
| #define | CLK_CLKDIV0_SC0DIV_Pos (28) |
| #define | CLK_CLKDIV0_SC0DIV_Msk (0xful << CLK_CLKDIV0_SC0DIV_Pos) |
| #define | CLK_CLKDIV1_SC1DIV_Pos (0) |
| #define | CLK_CLKDIV1_SC1DIV_Msk (0xful << CLK_CLKDIV1_SC1DIV_Pos) |
| #define | CLK_CLKDIV1_TMR0DIV_Pos (8) |
| #define | CLK_CLKDIV1_TMR0DIV_Msk (0xful << CLK_CLKDIV1_TMR0DIV_Pos) |
| #define | CLK_CLKDIV1_TMR1DIV_Pos (12) |
| #define | CLK_CLKDIV1_TMR1DIV_Msk (0xful << CLK_CLKDIV1_TMR1DIV_Pos) |
| #define | CLK_CLKDIV1_TMR2DIV_Pos (16) |
| #define | CLK_CLKDIV1_TMR2DIV_Msk (0xful << CLK_CLKDIV1_TMR2DIV_Pos) |
| #define | CLK_CLKDIV1_TMR3DIV_Pos (20) |
| #define | CLK_CLKDIV1_TMR3DIV_Msk (0xful << CLK_CLKDIV1_TMR3DIV_Pos) |
| #define | CLK_PLLCTL_PLLMLP_Pos (0) |
| #define | CLK_PLLCTL_PLLMLP_Msk (0x3ful << CLK_PLLCTL_PLLMLP_Pos) |
| #define | CLK_PLLCTL_INDIV_Pos (8) |
| #define | CLK_PLLCTL_INDIV_Msk (0x3ful << CLK_PLLCTL_INDIV_Pos) |
| #define | CLK_PLLCTL_STBTSEL_Pos (14) |
| #define | CLK_PLLCTL_STBTSEL_Msk (0x3ul << CLK_PLLCTL_STBTSEL_Pos) |
| #define | CLK_PLLCTL_PD_Pos (16) |
| #define | CLK_PLLCTL_PD_Msk (0x1ul << CLK_PLLCTL_PD_Pos) |
| #define | CLK_PLLCTL_PLLSRC_Pos (17) |
| #define | CLK_PLLCTL_PLLSRC_Msk (0x3ul << CLK_PLLCTL_PLLSRC_Pos) |
| #define | CLK_CLKOCTL_FREQSEL_Pos (0) |
| #define | CLK_CLKOCTL_FREQSEL_Msk (0xful << CLK_CLKOCTL_FREQSEL_Pos) |
| #define | CLK_CLKOCTL_CLKOEN_Pos (4) |
| #define | CLK_CLKOCTL_CLKOEN_Msk (0x1ul << CLK_CLKOCTL_CLKOEN_Pos) |
| #define | CLK_CLKOCTL_DIV1EN_Pos (5) |
| #define | CLK_CLKOCTL_DIV1EN_Msk (0x1ul << CLK_CLKOCTL_DIV1EN_Pos) |
| #define | CLK_WKINTSTS_PDWKIF_Pos (0) |
| #define | CLK_WKINTSTS_PDWKIF_Msk (0x1ul << CLK_WKINTSTS_PDWKIF_Pos) |
| #define | CLK_APBDIV_APB0DIV_Pos (0) |
| #define | CLK_APBDIV_APB0DIV_Msk (0x7ul << CLK_APBDIV_APB0DIV_Pos) |
| #define | CLK_APBDIV_APB1DIV_Pos (4) |
| #define | CLK_APBDIV_APB1DIV_Msk (0x7ul << CLK_APBDIV_APB1DIV_Pos) |
| #define | CLK_CLKDCTL_HXTFDEN_Pos (0) |
| #define | CLK_CLKDCTL_HXTFDEN_Msk (0x1ul << CLK_CLKDCTL_HXTFDEN_Pos) |
| #define | CLK_CLKDCTL_LXTFDEN_Pos (1) |
| #define | CLK_CLKDCTL_LXTFDEN_Msk (0x1ul << CLK_CLKDCTL_LXTFDEN_Pos) |
| #define | CLK_CLKDCTL_HXTFQDEN_Pos (2) |
| #define | CLK_CLKDCTL_HXTFQDEN_Msk (0x1ul << CLK_CLKDCTL_HXTFQDEN_Pos) |
| #define | CLK_CLKDIE_HXTFIEN_Pos (0) |
| #define | CLK_CLKDIE_HXTFIEN_Msk (0x1ul << CLK_CLKDIE_HXTFIEN_Pos) |
| #define | CLK_CLKDIE_LXTFIEN_Pos (1) |
| #define | CLK_CLKDIE_LXTFIEN_Msk (0x1ul << CLK_CLKDIE_LXTFIEN_Pos) |
| #define | CLK_CLKDIE_HXTFQIEN_Pos (2) |
| #define | CLK_CLKDIE_HXTFQIEN_Msk (0x1ul << CLK_CLKDIE_HXTFQIEN_Pos) |
| #define | CLK_CLKDSTS_HXTFIF_Pos (0) |
| #define | CLK_CLKDSTS_HXTFIF_Msk (0x1ul << CLK_CLKDSTS_HXTFIF_Pos) |
| #define | CLK_CLKDSTS_LXTFIF_Pos (1) |
| #define | CLK_CLKDSTS_LXTFIF_Msk (0x1ul << CLK_CLKDSTS_LXTFIF_Pos) |
| #define | CLK_CLKDSTS_HXTFQIF_Pos (2) |
| #define | CLK_CLKDSTS_HXTFQIF_Msk (0x1ul << CLK_CLKDSTS_HXTFQIF_Pos) |
| #define | CLK_CDUPB_UPERBD_Pos (0) |
| #define | CLK_CDUPB_UPERBD_Msk (0x7fful << CLK_CDUPB_UPERBD_Pos) |
| #define | CLK_CDLOWB_LOWERBD_Pos (0) |
| #define | CLK_CDLOWB_LOWERBD_Msk (0x7fful << CLK_CDLOWB_LOWERBD_Pos) |
| #define | FMC_ISPCTL_ISPEN_Pos (0) |
| #define | FMC_ISPCTL_ISPEN_Msk (0x1ul << FMC_ISPCTL_ISPEN_Pos) |
| #define | FMC_ISPCTL_BS_Pos (1) |
| #define | FMC_ISPCTL_BS_Msk (0x1ul << FMC_ISPCTL_BS_Pos) |
| #define | FMC_ISPCTL_APUEN_Pos (3) |
| #define | FMC_ISPCTL_APUEN_Msk (0x1ul << FMC_ISPCTL_APUEN_Pos) |
| #define | FMC_ISPCTL_CFGUEN_Pos (4) |
| #define | FMC_ISPCTL_CFGUEN_Msk (0x1ul << FMC_ISPCTL_CFGUEN_Pos) |
| #define | FMC_ISPCTL_LDUEN_Pos (5) |
| #define | FMC_ISPCTL_LDUEN_Msk (0x1ul << FMC_ISPCTL_LDUEN_Pos) |
| #define | FMC_ISPCTL_ISPFF_Pos (6) |
| #define | FMC_ISPCTL_ISPFF_Msk (0x1ul << FMC_ISPCTL_ISPFF_Pos) |
| #define | FMC_ISPADDR_ISPADDR_Pos (0) |
| #define | FMC_ISPADDR_ISPADDR_Msk (0xfffffffful << FMC_ISPADDR_ISPADDR_Pos) |
| #define | FMC_ISPDAT_ISPDAT_Pos (0) |
| #define | FMC_ISPDAT_ISPDAT_Msk (0xfffffffful << FMC_ISPDAT_ISPDAT_Pos) |
| #define | FMC_ISPCMD_CMD_Pos (0) |
| #define | FMC_ISPCMD_CMD_Msk (0x3ful << FMC_ISPCMD_CMD_Pos) |
| #define | FMC_ISPTRG_ISPGO_Pos (0) |
| #define | FMC_ISPTRG_ISPGO_Msk (0x1ul << FMC_ISPTRG_ISPGO_Pos) |
| #define | FMC_DFBA_DFBA_Pos (0) |
| #define | FMC_DFBA_DFBA_Msk (0xfffffffful << FMC_DFBA_DFBA_Pos) |
| #define | FMC_FTCTL_FOM_Pos (4) |
| #define | FMC_FTCTL_FOM_Msk (0x7ul << FMC_FTCTL_FOM_Pos) |
| #define | FMC_FTCTL_CACHEOFF_Pos (7) |
| #define | FMC_FTCTL_CACHEOFF_Msk (0x1ul << FMC_FTCTL_CACHEOFF_Pos) |
| #define | FMC_ISPSTS_ISPBUSY_Pos (0) |
| #define | FMC_ISPSTS_ISPBUSY_Msk (0x1ul << FMC_ISPSTS_ISPBUSY_Pos) |
| #define | FMC_ISPSTS_CBS_Pos (1) |
| #define | FMC_ISPSTS_CBS_Msk (0x3ul << FMC_ISPSTS_CBS_Pos) |
| #define | FMC_ISPSTS_PGFF_Pos (5) |
| #define | FMC_ISPSTS_PGFF_Msk (0x1ul << FMC_ISPSTS_PGFF_Pos) |
| #define | FMC_ISPSTS_ISPFF_Pos (6) |
| #define | FMC_ISPSTS_ISPFF_Msk (0x1ul << FMC_ISPSTS_ISPFF_Pos) |
| #define | FMC_ISPSTS_ALLONE_Pos (7) |
| #define | FMC_ISPSTS_ALLONE_Msk (0x1ul << FMC_ISPSTS_ALLONE_Pos) |
| #define | FMC_ISPSTS_VECMAP_Pos (9) |
| #define | FMC_ISPSTS_VECMAP_Msk (0x1ffffful << FMC_ISPSTS_VECMAP_Pos) |
| #define | FMC_KEY0_KEY0_Pos (0) |
| #define | FMC_KEY0_KEY0_Msk (0xfffffffful << FMC_KEY0_KEY0_Pos) |
| #define | FMC_KEY1_KEY1_Pos (0) |
| #define | FMC_KEY1_KEY1_Msk (0xfffffffful << FMC_KEY1_KEY1_Pos) |
| #define | FMC_KEY2_KEY2_Pos (0) |
| #define | FMC_KEY2_KEY2_Msk (0xfffffffful << FMC_KEY2_KEY2_Pos) |
| #define | FMC_KEYTRG_KEYGO_Pos (0) |
| #define | FMC_KEYTRG_KEYGO_Msk (0x1ul << FMC_KEYTRG_KEYGO_Pos) |
| #define | FMC_KEYTRG_TCEN_Pos (1) |
| #define | FMC_KEYTRG_TCEN_Msk (0x1ul << FMC_KEYTRG_TCEN_Pos) |
| #define | FMC_KEYSTS_KEYBUSY_Pos (0) |
| #define | FMC_KEYSTS_KEYBUSY_Msk (0x1ul << FMC_KEYSTS_KEYBUSY_Pos) |
| #define | FMC_KEYSTS_KEYLOCK_Pos (1) |
| #define | FMC_KEYSTS_KEYLOCK_Msk (0x1ul << FMC_KEYSTS_KEYLOCK_Pos) |
| #define | FMC_KEYSTS_KEYMATCH_Pos (2) |
| #define | FMC_KEYSTS_KEYMATCH_Msk (0x1ul << FMC_KEYSTS_KEYMATCH_Pos) |
| #define | FMC_KEYSTS_FORBID_Pos (3) |
| #define | FMC_KEYSTS_FORBID_Msk (0x1ul << FMC_KEYSTS_FORBID_Pos) |
| #define | FMC_KEYSTS_KEYFLAG_Pos (4) |
| #define | FMC_KEYSTS_KEYFLAG_Msk (0x1ul << FMC_KEYSTS_KEYFLAG_Pos) |
| #define | FMC_KEYSTS_CFGFLAG_Pos (5) |
| #define | FMC_KEYSTS_CFGFLAG_Msk (0x1ul << FMC_KEYSTS_CFGFLAG_Pos) |
| #define | FMC_KECNT_KECNT_Pos (0) |
| #define | FMC_KECNT_KECNT_Msk (0x3ful << FMC_KECNT_KECNT_Pos) |
| #define | FMC_KECNT_KEMAX_Pos (8) |
| #define | FMC_KECNT_KEMAX_Msk (0x3ful << FMC_KECNT_KEMAX_Pos) |
| #define | FMC_KPCNT_KPCNT_Pos (0) |
| #define | FMC_KPCNT_KPCNT_Msk (0xful << FMC_KPCNT_KPCNT_Pos) |
| #define | FMC_KPCNT_KPMAX_Pos (8) |
| #define | FMC_KPCNT_KPMAX_Msk (0xful << FMC_KPCNT_KPMAX_Pos) |
| #define | GPIO_MODE_MODE0_Pos (0) |
| #define | GPIO_MODE_MODE0_Msk (0x3ul << GPIO_MODE_MODE0_Pos) |
| #define | GPIO_MODE_MODE1_Pos (2) |
| #define | GPIO_MODE_MODE1_Msk (0x3ul << GPIO_MODE_MODE1_Pos) |
| #define | GPIO_MODE_MODE2_Pos (4) |
| #define | GPIO_MODE_MODE2_Msk (0x3ul << GPIO_MODE_MODE2_Pos) |
| #define | GPIO_MODE_MODE3_Pos (6) |
| #define | GPIO_MODE_MODE3_Msk (0x3ul << GPIO_MODE_MODE3_Pos) |
| #define | GPIO_MODE_MODE4_Pos (8) |
| #define | GPIO_MODE_MODE4_Msk (0x3ul << GPIO_MODE_MODE4_Pos) |
| #define | GPIO_MODE_MODE5_Pos (10) |
| #define | GPIO_MODE_MODE5_Msk (0x3ul << GPIO_MODE_MODE5_Pos) |
| #define | GPIO_MODE_MODE6_Pos (12) |
| #define | GPIO_MODE_MODE6_Msk (0x3ul << GPIO_MODE_MODE6_Pos) |
| #define | GPIO_MODE_MODE7_Pos (14) |
| #define | GPIO_MODE_MODE7_Msk (0x3ul << GPIO_MODE_MODE7_Pos) |
| #define | GPIO_MODE_MODE8_Pos (16) |
| #define | GPIO_MODE_MODE8_Msk (0x3ul << GPIO_MODE_MODE8_Pos) |
| #define | GPIO_MODE_MODE9_Pos (18) |
| #define | GPIO_MODE_MODE9_Msk (0x3ul << GPIO_MODE_MODE9_Pos) |
| #define | GPIO_MODE_MODE10_Pos (20) |
| #define | GPIO_MODE_MODE10_Msk (0x3ul << GPIO_MODE_MODE10_Pos) |
| #define | GPIO_MODE_MODE11_Pos (22) |
| #define | GPIO_MODE_MODE11_Msk (0x3ul << GPIO_MODE_MODE11_Pos) |
| #define | GPIO_MODE_MODE12_Pos (24) |
| #define | GPIO_MODE_MODE12_Msk (0x3ul << GPIO_MODE_MODE12_Pos) |
| #define | GPIO_MODE_MODE13_Pos (26) |
| #define | GPIO_MODE_MODE13_Msk (0x3ul << GPIO_MODE_MODE13_Pos) |
| #define | GPIO_MODE_MODE14_Pos (28) |
| #define | GPIO_MODE_MODE14_Msk (0x3ul << GPIO_MODE_MODE14_Pos) |
| #define | GPIO_MODE_MODE15_Pos (30) |
| #define | GPIO_MODE_MODE15_Msk (0x3ul << GPIO_MODE_MODE15_Pos) |
| #define | GPIO_DINOFF_DINOFF0_Pos (16) |
| #define | GPIO_DINOFF_DINOFF0_Msk (0x1ul << GPIO_DINOFF_DINOFF0_Pos) |
| #define | GPIO_DINOFF_DINOFF1_Pos (17) |
| #define | GPIO_DINOFF_DINOFF1_Msk (0x1ul << GPIO_DINOFF_DINOFF1_Pos) |
| #define | GPIO_DINOFF_DINOFF2_Pos (18) |
| #define | GPIO_DINOFF_DINOFF2_Msk (0x1ul << GPIO_DINOFF_DINOFF2_Pos) |
| #define | GPIO_DINOFF_DINOFF3_Pos (19) |
| #define | GPIO_DINOFF_DINOFF3_Msk (0x1ul << GPIO_DINOFF_DINOFF3_Pos) |
| #define | GPIO_DINOFF_DINOFF4_Pos (20) |
| #define | GPIO_DINOFF_DINOFF4_Msk (0x1ul << GPIO_DINOFF_DINOFF4_Pos) |
| #define | GPIO_DINOFF_DINOFF5_Pos (21) |
| #define | GPIO_DINOFF_DINOFF5_Msk (0x1ul << GPIO_DINOFF_DINOFF5_Pos) |
| #define | GPIO_DINOFF_DINOFF6_Pos (22) |
| #define | GPIO_DINOFF_DINOFF6_Msk (0x1ul << GPIO_DINOFF_DINOFF6_Pos) |
| #define | GPIO_DINOFF_DINOFF7_Pos (23) |
| #define | GPIO_DINOFF_DINOFF7_Msk (0x1ul << GPIO_DINOFF_DINOFF7_Pos) |
| #define | GPIO_DINOFF_DINOFF8_Pos (24) |
| #define | GPIO_DINOFF_DINOFF8_Msk (0x1ul << GPIO_DINOFF_DINOFF8_Pos) |
| #define | GPIO_DINOFF_DINOFF9_Pos (25) |
| #define | GPIO_DINOFF_DINOFF9_Msk (0x1ul << GPIO_DINOFF_DINOFF9_Pos) |
| #define | GPIO_DINOFF_DINOFF10_Pos (26) |
| #define | GPIO_DINOFF_DINOFF10_Msk (0x1ul << GPIO_DINOFF_DINOFF10_Pos) |
| #define | GPIO_DINOFF_DINOFF11_Pos (27) |
| #define | GPIO_DINOFF_DINOFF11_Msk (0x1ul << GPIO_DINOFF_DINOFF11_Pos) |
| #define | GPIO_DINOFF_DINOFF12_Pos (28) |
| #define | GPIO_DINOFF_DINOFF12_Msk (0x1ul << GPIO_DINOFF_DINOFF12_Pos) |
| #define | GPIO_DINOFF_DINOFF13_Pos (29) |
| #define | GPIO_DINOFF_DINOFF13_Msk (0x1ul << GPIO_DINOFF_DINOFF13_Pos) |
| #define | GPIO_DINOFF_DINOFF14_Pos (30) |
| #define | GPIO_DINOFF_DINOFF14_Msk (0x1ul << GPIO_DINOFF_DINOFF14_Pos) |
| #define | GPIO_DINOFF_DINOFF15_Pos (31) |
| #define | GPIO_DINOFF_DINOFF15_Msk (0x1ul << GPIO_DINOFF_DINOFF15_Pos) |
| #define | GPIO_DOUT_DOUT0_Pos (0) |
| #define | GPIO_DOUT_DOUT0_Msk (0x1ul << GPIO_DOUT_DOUT0_Pos) |
| #define | GPIO_DOUT_DOUT1_Pos (1) |
| #define | GPIO_DOUT_DOUT1_Msk (0x1ul << GPIO_DOUT_DOUT1_Pos) |
| #define | GPIO_DOUT_DOUT2_Pos (2) |
| #define | GPIO_DOUT_DOUT2_Msk (0x1ul << GPIO_DOUT_DOUT2_Pos) |
| #define | GPIO_DOUT_DOUT3_Pos (3) |
| #define | GPIO_DOUT_DOUT3_Msk (0x1ul << GPIO_DOUT_DOUT3_Pos) |
| #define | GPIO_DOUT_DOUT4_Pos (4) |
| #define | GPIO_DOUT_DOUT4_Msk (0x1ul << GPIO_DOUT_DOUT4_Pos) |
| #define | GPIO_DOUT_DOUT5_Pos (5) |
| #define | GPIO_DOUT_DOUT5_Msk (0x1ul << GPIO_DOUT_DOUT5_Pos) |
| #define | GPIO_DOUT_DOUT6_Pos (6) |
| #define | GPIO_DOUT_DOUT6_Msk (0x1ul << GPIO_DOUT_DOUT6_Pos) |
| #define | GPIO_DOUT_DOUT7_Pos (7) |
| #define | GPIO_DOUT_DOUT7_Msk (0x1ul << GPIO_DOUT_DOUT7_Pos) |
| #define | GPIO_DOUT_DOUT8_Pos (8) |
| #define | GPIO_DOUT_DOUT8_Msk (0x1ul << GPIO_DOUT_DOUT8_Pos) |
| #define | GPIO_DOUT_DOUT9_Pos (9) |
| #define | GPIO_DOUT_DOUT9_Msk (0x1ul << GPIO_DOUT_DOUT9_Pos) |
| #define | GPIO_DOUT_DOUT10_Pos (10) |
| #define | GPIO_DOUT_DOUT10_Msk (0x1ul << GPIO_DOUT_DOUT10_Pos) |
| #define | GPIO_DOUT_DOUT11_Pos (11) |
| #define | GPIO_DOUT_DOUT11_Msk (0x1ul << GPIO_DOUT_DOUT11_Pos) |
| #define | GPIO_DOUT_DOUT12_Pos (12) |
| #define | GPIO_DOUT_DOUT12_Msk (0x1ul << GPIO_DOUT_DOUT12_Pos) |
| #define | GPIO_DOUT_DOUT13_Pos (13) |
| #define | GPIO_DOUT_DOUT13_Msk (0x1ul << GPIO_DOUT_DOUT13_Pos) |
| #define | GPIO_DOUT_DOUT14_Pos (14) |
| #define | GPIO_DOUT_DOUT14_Msk (0x1ul << GPIO_DOUT_DOUT14_Pos) |
| #define | GPIO_DOUT_DOUT15_Pos (15) |
| #define | GPIO_DOUT_DOUT15_Msk (0x1ul << GPIO_DOUT_DOUT15_Pos) |
| #define | GPIO_DATMSK_DMASK0_Pos (0) |
| #define | GPIO_DATMSK_DMASK0_Msk (0x1ul << GPIO_DATMSK_DMASK0_Pos) |
| #define | GPIO_DATMSK_DMASK1_Pos (1) |
| #define | GPIO_DATMSK_DMASK1_Msk (0x1ul << GPIO_DATMSK_DMASK1_Pos) |
| #define | GPIO_DATMSK_DMASK2_Pos (2) |
| #define | GPIO_DATMSK_DMASK2_Msk (0x1ul << GPIO_DATMSK_DMASK2_Pos) |
| #define | GPIO_DATMSK_DMASK3_Pos (3) |
| #define | GPIO_DATMSK_DMASK3_Msk (0x1ul << GPIO_DATMSK_DMASK3_Pos) |
| #define | GPIO_DATMSK_DMASK4_Pos (4) |
| #define | GPIO_DATMSK_DMASK4_Msk (0x1ul << GPIO_DATMSK_DMASK4_Pos) |
| #define | GPIO_DATMSK_DMASK5_Pos (5) |
| #define | GPIO_DATMSK_DMASK5_Msk (0x1ul << GPIO_DATMSK_DMASK5_Pos) |
| #define | GPIO_DATMSK_DMASK6_Pos (6) |
| #define | GPIO_DATMSK_DMASK6_Msk (0x1ul << GPIO_DATMSK_DMASK6_Pos) |
| #define | GPIO_DATMSK_DMASK7_Pos (7) |
| #define | GPIO_DATMSK_DMASK7_Msk (0x1ul << GPIO_DATMSK_DMASK7_Pos) |
| #define | GPIO_DATMSK_DMASK8_Pos (8) |
| #define | GPIO_DATMSK_DMASK8_Msk (0x1ul << GPIO_DATMSK_DMASK8_Pos) |
| #define | GPIO_DATMSK_DMASK9_Pos (9) |
| #define | GPIO_DATMSK_DMASK9_Msk (0x1ul << GPIO_DATMSK_DMASK9_Pos) |
| #define | GPIO_DATMSK_DMASK10_Pos (10) |
| #define | GPIO_DATMSK_DMASK10_Msk (0x1ul << GPIO_DATMSK_DMASK10_Pos) |
| #define | GPIO_DATMSK_DMASK11_Pos (11) |
| #define | GPIO_DATMSK_DMASK11_Msk (0x1ul << GPIO_DATMSK_DMASK11_Pos) |
| #define | GPIO_DATMSK_DMASK12_Pos (12) |
| #define | GPIO_DATMSK_DMASK12_Msk (0x1ul << GPIO_DATMSK_DMASK12_Pos) |
| #define | GPIO_DATMSK_DMASK13_Pos (13) |
| #define | GPIO_DATMSK_DMASK13_Msk (0x1ul << GPIO_DATMSK_DMASK13_Pos) |
| #define | GPIO_DATMSK_DMASK14_Pos (14) |
| #define | GPIO_DATMSK_DMASK14_Msk (0x1ul << GPIO_DATMSK_DMASK14_Pos) |
| #define | GPIO_DATMSK_DMASK15_Pos (15) |
| #define | GPIO_DATMSK_DMASK15_Msk (0x1ul << GPIO_DATMSK_DMASK15_Pos) |
| #define | GPIO_PIN_PIN0_Pos (0) |
| #define | GPIO_PIN_PIN0_Msk (0x1ul << GPIO_PIN_PIN0_Pos) |
| #define | GPIO_PIN_PIN1_Pos (1) |
| #define | GPIO_PIN_PIN1_Msk (0x1ul << GPIO_PIN_PIN1_Pos) |
| #define | GPIO_PIN_PIN2_Pos (2) |
| #define | GPIO_PIN_PIN2_Msk (0x1ul << GPIO_PIN_PIN2_Pos) |
| #define | GPIO_PIN_PIN3_Pos (3) |
| #define | GPIO_PIN_PIN3_Msk (0x1ul << GPIO_PIN_PIN3_Pos) |
| #define | GPIO_PIN_PIN4_Pos (4) |
| #define | GPIO_PIN_PIN4_Msk (0x1ul << GPIO_PIN_PIN4_Pos) |
| #define | GPIO_PIN_PIN5_Pos (5) |
| #define | GPIO_PIN_PIN5_Msk (0x1ul << GPIO_PIN_PIN5_Pos) |
| #define | GPIO_PIN_PIN6_Pos (6) |
| #define | GPIO_PIN_PIN6_Msk (0x1ul << GPIO_PIN_PIN6_Pos) |
| #define | GPIO_PIN_PIN7_Pos (7) |
| #define | GPIO_PIN_PIN7_Msk (0x1ul << GPIO_PIN_PIN7_Pos) |
| #define | GPIO_PIN_PIN8_Pos (8) |
| #define | GPIO_PIN_PIN8_Msk (0x1ul << GPIO_PIN_PIN8_Pos) |
| #define | GPIO_PIN_PIN9_Pos (9) |
| #define | GPIO_PIN_PIN9_Msk (0x1ul << GPIO_PIN_PIN9_Pos) |
| #define | GPIO_PIN_PIN10_Pos (10) |
| #define | GPIO_PIN_PIN10_Msk (0x1ul << GPIO_PIN_PIN10_Pos) |
| #define | GPIO_PIN_PIN11_Pos (11) |
| #define | GPIO_PIN_PIN11_Msk (0x1ul << GPIO_PIN_PIN11_Pos) |
| #define | GPIO_PIN_PIN12_Pos (12) |
| #define | GPIO_PIN_PIN12_Msk (0x1ul << GPIO_PIN_PIN12_Pos) |
| #define | GPIO_PIN_PIN13_Pos (13) |
| #define | GPIO_PIN_PIN13_Msk (0x1ul << GPIO_PIN_PIN13_Pos) |
| #define | GPIO_PIN_PIN14_Pos (14) |
| #define | GPIO_PIN_PIN14_Msk (0x1ul << GPIO_PIN_PIN14_Pos) |
| #define | GPIO_PIN_PIN15_Pos (15) |
| #define | GPIO_PIN_PIN15_Msk (0x1ul << GPIO_PIN_PIN15_Pos) |
| #define | GPIO_DBEN_DBEN0_Pos (0) |
| #define | GPIO_DBEN_DBEN0_Msk (0x1ul << GPIO_DBEN_DBEN0_Pos) |
| #define | GPIO_DBEN_DBEN1_Pos (1) |
| #define | GPIO_DBEN_DBEN1_Msk (0x1ul << GPIO_DBEN_DBEN1_Pos) |
| #define | GPIO_DBEN_DBEN2_Pos (2) |
| #define | GPIO_DBEN_DBEN2_Msk (0x1ul << GPIO_DBEN_DBEN2_Pos) |
| #define | GPIO_DBEN_DBEN3_Pos (3) |
| #define | GPIO_DBEN_DBEN3_Msk (0x1ul << GPIO_DBEN_DBEN3_Pos) |
| #define | GPIO_DBEN_DBEN4_Pos (4) |
| #define | GPIO_DBEN_DBEN4_Msk (0x1ul << GPIO_DBEN_DBEN4_Pos) |
| #define | GPIO_DBEN_DBEN5_Pos (5) |
| #define | GPIO_DBEN_DBEN5_Msk (0x1ul << GPIO_DBEN_DBEN5_Pos) |
| #define | GPIO_DBEN_DBEN6_Pos (6) |
| #define | GPIO_DBEN_DBEN6_Msk (0x1ul << GPIO_DBEN_DBEN6_Pos) |
| #define | GPIO_DBEN_DBEN7_Pos (7) |
| #define | GPIO_DBEN_DBEN7_Msk (0x1ul << GPIO_DBEN_DBEN7_Pos) |
| #define | GPIO_DBEN_DBEN8_Pos (8) |
| #define | GPIO_DBEN_DBEN8_Msk (0x1ul << GPIO_DBEN_DBEN8_Pos) |
| #define | GPIO_DBEN_DBEN9_Pos (9) |
| #define | GPIO_DBEN_DBEN9_Msk (0x1ul << GPIO_DBEN_DBEN9_Pos) |
| #define | GPIO_DBEN_DBEN10_Pos (10) |
| #define | GPIO_DBEN_DBEN10_Msk (0x1ul << GPIO_DBEN_DBEN10_Pos) |
| #define | GPIO_DBEN_DBEN11_Pos (11) |
| #define | GPIO_DBEN_DBEN11_Msk (0x1ul << GPIO_DBEN_DBEN11_Pos) |
| #define | GPIO_DBEN_DBEN12_Pos (12) |
| #define | GPIO_DBEN_DBEN12_Msk (0x1ul << GPIO_DBEN_DBEN12_Pos) |
| #define | GPIO_DBEN_DBEN13_Pos (13) |
| #define | GPIO_DBEN_DBEN13_Msk (0x1ul << GPIO_DBEN_DBEN13_Pos) |
| #define | GPIO_DBEN_DBEN14_Pos (14) |
| #define | GPIO_DBEN_DBEN14_Msk (0x1ul << GPIO_DBEN_DBEN14_Pos) |
| #define | GPIO_DBEN_DBEN15_Pos (15) |
| #define | GPIO_DBEN_DBEN15_Msk (0x1ul << GPIO_DBEN_DBEN15_Pos) |
| #define | GPIO_INTTYPE_TYPE0_Pos (0) |
| #define | GPIO_INTTYPE_TYPE0_Msk (0x1ul << GPIO_INTTYPE_TYPE0_Pos) |
| #define | GPIO_INTTYPE_TYPE1_Pos (1) |
| #define | GPIO_INTTYPE_TYPE1_Msk (0x1ul << GPIO_INTTYPE_TYPE1_Pos) |
| #define | GPIO_INTTYPE_TYPE2_Pos (2) |
| #define | GPIO_INTTYPE_TYPE2_Msk (0x1ul << GPIO_INTTYPE_TYPE2_Pos) |
| #define | GPIO_INTTYPE_TYPE3_Pos (3) |
| #define | GPIO_INTTYPE_TYPE3_Msk (0x1ul << GPIO_INTTYPE_TYPE3_Pos) |
| #define | GPIO_INTTYPE_TYPE4_Pos (4) |
| #define | GPIO_INTTYPE_TYPE4_Msk (0x1ul << GPIO_INTTYPE_TYPE4_Pos) |
| #define | GPIO_INTTYPE_TYPE5_Pos (5) |
| #define | GPIO_INTTYPE_TYPE5_Msk (0x1ul << GPIO_INTTYPE_TYPE5_Pos) |
| #define | GPIO_INTTYPE_TYPE6_Pos (6) |
| #define | GPIO_INTTYPE_TYPE6_Msk (0x1ul << GPIO_INTTYPE_TYPE6_Pos) |
| #define | GPIO_INTTYPE_TYPE7_Pos (7) |
| #define | GPIO_INTTYPE_TYPE7_Msk (0x1ul << GPIO_INTTYPE_TYPE7_Pos) |
| #define | GPIO_INTTYPE_TYPE8_Pos (8) |
| #define | GPIO_INTTYPE_TYPE8_Msk (0x1ul << GPIO_INTTYPE_TYPE8_Pos) |
| #define | GPIO_INTTYPE_TYPE9_Pos (9) |
| #define | GPIO_INTTYPE_TYPE9_Msk (0x1ul << GPIO_INTTYPE_TYPE9_Pos) |
| #define | GPIO_INTTYPE_TYPE10_Pos (10) |
| #define | GPIO_INTTYPE_TYPE10_Msk (0x1ul << GPIO_INTTYPE_TYPE10_Pos) |
| #define | GPIO_INTTYPE_TYPE11_Pos (11) |
| #define | GPIO_INTTYPE_TYPE11_Msk (0x1ul << GPIO_INTTYPE_TYPE11_Pos) |
| #define | GPIO_INTTYPE_TYPE12_Pos (12) |
| #define | GPIO_INTTYPE_TYPE12_Msk (0x1ul << GPIO_INTTYPE_TYPE12_Pos) |
| #define | GPIO_INTTYPE_TYPE13_Pos (13) |
| #define | GPIO_INTTYPE_TYPE13_Msk (0x1ul << GPIO_INTTYPE_TYPE13_Pos) |
| #define | GPIO_INTTYPE_TYPE14_Pos (14) |
| #define | GPIO_INTTYPE_TYPE14_Msk (0x1ul << GPIO_INTTYPE_TYPE14_Pos) |
| #define | GPIO_INTTYPE_TYPE15_Pos (15) |
| #define | GPIO_INTTYPE_TYPE15_Msk (0x1ul << GPIO_INTTYPE_TYPE15_Pos) |
| #define | GPIO_INTEN_FLIEN0_Pos (0) |
| #define | GPIO_INTEN_FLIEN0_Msk (0x1ul << GPIO_INTEN_FLIEN0_Pos) |
| #define | GPIO_INTEN_FLIEN1_Pos (1) |
| #define | GPIO_INTEN_FLIEN1_Msk (0x1ul << GPIO_INTEN_FLIEN1_Pos) |
| #define | GPIO_INTEN_FLIEN2_Pos (2) |
| #define | GPIO_INTEN_FLIEN2_Msk (0x1ul << GPIO_INTEN_FLIEN2_Pos) |
| #define | GPIO_INTEN_FLIEN3_Pos (3) |
| #define | GPIO_INTEN_FLIEN3_Msk (0x1ul << GPIO_INTEN_FLIEN3_Pos) |
| #define | GPIO_INTEN_FLIEN4_Pos (4) |
| #define | GPIO_INTEN_FLIEN4_Msk (0x1ul << GPIO_INTEN_FLIEN4_Pos) |
| #define | GPIO_INTEN_FLIEN5_Pos (5) |
| #define | GPIO_INTEN_FLIEN5_Msk (0x1ul << GPIO_INTEN_FLIEN5_Pos) |
| #define | GPIO_INTEN_FLIEN6_Pos (6) |
| #define | GPIO_INTEN_FLIEN6_Msk (0x1ul << GPIO_INTEN_FLIEN6_Pos) |
| #define | GPIO_INTEN_FLIEN7_Pos (7) |
| #define | GPIO_INTEN_FLIEN7_Msk (0x1ul << GPIO_INTEN_FLIEN7_Pos) |
| #define | GPIO_INTEN_FLIEN8_Pos (8) |
| #define | GPIO_INTEN_FLIEN8_Msk (0x1ul << GPIO_INTEN_FLIEN8_Pos) |
| #define | GPIO_INTEN_FLIEN9_Pos (9) |
| #define | GPIO_INTEN_FLIEN9_Msk (0x1ul << GPIO_INTEN_FLIEN9_Pos) |
| #define | GPIO_INTEN_FLIEN10_Pos (10) |
| #define | GPIO_INTEN_FLIEN10_Msk (0x1ul << GPIO_INTEN_FLIEN10_Pos) |
| #define | GPIO_INTEN_FLIEN11_Pos (11) |
| #define | GPIO_INTEN_FLIEN11_Msk (0x1ul << GPIO_INTEN_FLIEN11_Pos) |
| #define | GPIO_INTEN_FLIEN12_Pos (12) |
| #define | GPIO_INTEN_FLIEN12_Msk (0x1ul << GPIO_INTEN_FLIEN12_Pos) |
| #define | GPIO_INTEN_FLIEN13_Pos (13) |
| #define | GPIO_INTEN_FLIEN13_Msk (0x1ul << GPIO_INTEN_FLIEN13_Pos) |
| #define | GPIO_INTEN_FLIEN14_Pos (14) |
| #define | GPIO_INTEN_FLIEN14_Msk (0x1ul << GPIO_INTEN_FLIEN14_Pos) |
| #define | GPIO_INTEN_FLIEN15_Pos (15) |
| #define | GPIO_INTEN_FLIEN15_Msk (0x1ul << GPIO_INTEN_FLIEN15_Pos) |
| #define | GPIO_INTEN_RHIEN0_Pos (16) |
| #define | GPIO_INTEN_RHIEN0_Msk (0x1ul << GPIO_INTEN_RHIEN0_Pos) |
| #define | GPIO_INTEN_RHIEN1_Pos (17) |
| #define | GPIO_INTEN_RHIEN1_Msk (0x1ul << GPIO_INTEN_RHIEN1_Pos) |
| #define | GPIO_INTEN_RHIEN2_Pos (18) |
| #define | GPIO_INTEN_RHIEN2_Msk (0x1ul << GPIO_INTEN_RHIEN2_Pos) |
| #define | GPIO_INTEN_RHIEN3_Pos (19) |
| #define | GPIO_INTEN_RHIEN3_Msk (0x1ul << GPIO_INTEN_RHIEN3_Pos) |
| #define | GPIO_INTEN_RHIEN4_Pos (20) |
| #define | GPIO_INTEN_RHIEN4_Msk (0x1ul << GPIO_INTEN_RHIEN4_Pos) |
| #define | GPIO_INTEN_RHIEN5_Pos (21) |
| #define | GPIO_INTEN_RHIEN5_Msk (0x1ul << GPIO_INTEN_RHIEN5_Pos) |
| #define | GPIO_INTEN_RHIEN6_Pos (22) |
| #define | GPIO_INTEN_RHIEN6_Msk (0x1ul << GPIO_INTEN_RHIEN6_Pos) |
| #define | GPIO_INTEN_RHIEN7_Pos (23) |
| #define | GPIO_INTEN_RHIEN7_Msk (0x1ul << GPIO_INTEN_RHIEN7_Pos) |
| #define | GPIO_INTEN_RHIEN8_Pos (24) |
| #define | GPIO_INTEN_RHIEN8_Msk (0x1ul << GPIO_INTEN_RHIEN8_Pos) |
| #define | GPIO_INTEN_RHIEN9_Pos (25) |
| #define | GPIO_INTEN_RHIEN9_Msk (0x1ul << GPIO_INTEN_RHIEN9_Pos) |
| #define | GPIO_INTEN_RHIEN10_Pos (26) |
| #define | GPIO_INTEN_RHIEN10_Msk (0x1ul << GPIO_INTEN_RHIEN10_Pos) |
| #define | GPIO_INTEN_RHIEN11_Pos (27) |
| #define | GPIO_INTEN_RHIEN11_Msk (0x1ul << GPIO_INTEN_RHIEN11_Pos) |
| #define | GPIO_INTEN_RHIEN12_Pos (28) |
| #define | GPIO_INTEN_RHIEN12_Msk (0x1ul << GPIO_INTEN_RHIEN12_Pos) |
| #define | GPIO_INTEN_RHIEN13_Pos (29) |
| #define | GPIO_INTEN_RHIEN13_Msk (0x1ul << GPIO_INTEN_RHIEN13_Pos) |
| #define | GPIO_INTEN_RHIEN14_Pos (30) |
| #define | GPIO_INTEN_RHIEN14_Msk (0x1ul << GPIO_INTEN_RHIEN14_Pos) |
| #define | GPIO_INTEN_RHIEN15_Pos (31) |
| #define | GPIO_INTEN_RHIEN15_Msk (0x1ul << GPIO_INTEN_RHIEN15_Pos) |
| #define | GPIO_INTSRC_INTSRC0_Pos (0) |
| #define | GPIO_INTSRC_INTSRC0_Msk (0x1ul << GPIO_INTSRC_INTSRC0_Pos) |
| #define | GPIO_INTSRC_INTSRC1_Pos (1) |
| #define | GPIO_INTSRC_INTSRC1_Msk (0x1ul << GPIO_INTSRC_INTSRC1_Pos) |
| #define | GPIO_INTSRC_INTSRC2_Pos (2) |
| #define | GPIO_INTSRC_INTSRC2_Msk (0x1ul << GPIO_INTSRC_INTSRC2_Pos) |
| #define | GPIO_INTSRC_INTSRC3_Pos (3) |
| #define | GPIO_INTSRC_INTSRC3_Msk (0x1ul << GPIO_INTSRC_INTSRC3_Pos) |
| #define | GPIO_INTSRC_INTSRC4_Pos (4) |
| #define | GPIO_INTSRC_INTSRC4_Msk (0x1ul << GPIO_INTSRC_INTSRC4_Pos) |
| #define | GPIO_INTSRC_INTSRC5_Pos (5) |
| #define | GPIO_INTSRC_INTSRC5_Msk (0x1ul << GPIO_INTSRC_INTSRC5_Pos) |
| #define | GPIO_INTSRC_INTSRC6_Pos (6) |
| #define | GPIO_INTSRC_INTSRC6_Msk (0x1ul << GPIO_INTSRC_INTSRC6_Pos) |
| #define | GPIO_INTSRC_INTSRC7_Pos (7) |
| #define | GPIO_INTSRC_INTSRC7_Msk (0x1ul << GPIO_INTSRC_INTSRC7_Pos) |
| #define | GPIO_INTSRC_INTSRC8_Pos (8) |
| #define | GPIO_INTSRC_INTSRC8_Msk (0x1ul << GPIO_INTSRC_INTSRC8_Pos) |
| #define | GPIO_INTSRC_INTSRC9_Pos (9) |
| #define | GPIO_INTSRC_INTSRC9_Msk (0x1ul << GPIO_INTSRC_INTSRC9_Pos) |
| #define | GPIO_INTSRC_INTSRC10_Pos (10) |
| #define | GPIO_INTSRC_INTSRC10_Msk (0x1ul << GPIO_INTSRC_INTSRC10_Pos) |
| #define | GPIO_INTSRC_INTSRC11_Pos (11) |
| #define | GPIO_INTSRC_INTSRC11_Msk (0x1ul << GPIO_INTSRC_INTSRC11_Pos) |
| #define | GPIO_INTSRC_INTSRC12_Pos (12) |
| #define | GPIO_INTSRC_INTSRC12_Msk (0x1ul << GPIO_INTSRC_INTSRC12_Pos) |
| #define | GPIO_INTSRC_INTSRC13_Pos (13) |
| #define | GPIO_INTSRC_INTSRC13_Msk (0x1ul << GPIO_INTSRC_INTSRC13_Pos) |
| #define | GPIO_INTSRC_INTSRC14_Pos (14) |
| #define | GPIO_INTSRC_INTSRC14_Msk (0x1ul << GPIO_INTSRC_INTSRC14_Pos) |
| #define | GPIO_INTSRC_INTSRC15_Pos (15) |
| #define | GPIO_INTSRC_INTSRC15_Msk (0x1ul << GPIO_INTSRC_INTSRC15_Pos) |
| #define | GPIO_PUEN_PUEN0_Pos (0) |
| #define | GPIO_PUEN_PUEN0_Msk (0x1ul << GPIO_PUEN_PUEN0_Pos) |
| #define | GPIO_PUEN_PUEN1_Pos (1) |
| #define | GPIO_PUEN_PUEN1_Msk (0x1ul << GPIO_PUEN_PUEN1_Pos) |
| #define | GPIO_PUEN_PUEN2_Pos (2) |
| #define | GPIO_PUEN_PUEN2_Msk (0x1ul << GPIO_PUEN_PUEN2_Pos) |
| #define | GPIO_PUEN_PUEN3_Pos (3) |
| #define | GPIO_PUEN_PUEN3_Msk (0x1ul << GPIO_PUEN_PUEN3_Pos) |
| #define | GPIO_PUEN_PUEN4_Pos (4) |
| #define | GPIO_PUEN_PUEN4_Msk (0x1ul << GPIO_PUEN_PUEN4_Pos) |
| #define | GPIO_PUEN_PUEN5_Pos (5) |
| #define | GPIO_PUEN_PUEN5_Msk (0x1ul << GPIO_PUEN_PUEN5_Pos) |
| #define | GPIO_PUEN_PUEN6_Pos (6) |
| #define | GPIO_PUEN_PUEN6_Msk (0x1ul << GPIO_PUEN_PUEN6_Pos) |
| #define | GPIO_PUEN_PUEN7_Pos (7) |
| #define | GPIO_PUEN_PUEN7_Msk (0x1ul << GPIO_PUEN_PUEN7_Pos) |
| #define | GPIO_PUEN_PUEN8_Pos (8) |
| #define | GPIO_PUEN_PUEN8_Msk (0x1ul << GPIO_PUEN_PUEN8_Pos) |
| #define | GPIO_PUEN_PUEN9_Pos (9) |
| #define | GPIO_PUEN_PUEN9_Msk (0x1ul << GPIO_PUEN_PUEN9_Pos) |
| #define | GPIO_PUEN_PUEN10_Pos (10) |
| #define | GPIO_PUEN_PUEN10_Msk (0x1ul << GPIO_PUEN_PUEN10_Pos) |
| #define | GPIO_PUEN_PUEN11_Pos (11) |
| #define | GPIO_PUEN_PUEN11_Msk (0x1ul << GPIO_PUEN_PUEN11_Pos) |
| #define | GPIO_PUEN_PUEN12_Pos (12) |
| #define | GPIO_PUEN_PUEN12_Msk (0x1ul << GPIO_PUEN_PUEN12_Pos) |
| #define | GPIO_PUEN_PUEN13_Pos (13) |
| #define | GPIO_PUEN_PUEN13_Msk (0x1ul << GPIO_PUEN_PUEN13_Pos) |
| #define | GPIO_PUEN_PUEN14_Pos (14) |
| #define | GPIO_PUEN_PUEN14_Msk (0x1ul << GPIO_PUEN_PUEN14_Pos) |
| #define | GPIO_PUEN_PUEN15_Pos (15) |
| #define | GPIO_PUEN_PUEN15_Msk (0x1ul << GPIO_PUEN_PUEN15_Pos) |
| #define | GPIO_INTSTS_FLISTS0_Pos (0) |
| #define | GPIO_INTSTS_FLISTS0_Msk (0x1ul << GPIO_INTSTS_FLISTS0_Pos) |
| #define | GPIO_INTSTS_FLISTS1_Pos (1) |
| #define | GPIO_INTSTS_FLISTS1_Msk (0x1ul << GPIO_INTSTS_FLISTS1_Pos) |
| #define | GPIO_INTSTS_FLISTS2_Pos (2) |
| #define | GPIO_INTSTS_FLISTS2_Msk (0x1ul << GPIO_INTSTS_FLISTS2_Pos) |
| #define | GPIO_INTSTS_FLISTS3_Pos (3) |
| #define | GPIO_INTSTS_FLISTS3_Msk (0x1ul << GPIO_INTSTS_FLISTS3_Pos) |
| #define | GPIO_INTSTS_FLISTS4_Pos (4) |
| #define | GPIO_INTSTS_FLISTS4_Msk (0x1ul << GPIO_INTSTS_FLISTS4_Pos) |
| #define | GPIO_INTSTS_FLISTS5_Pos (5) |
| #define | GPIO_INTSTS_FLISTS5_Msk (0x1ul << GPIO_INTSTS_FLISTS5_Pos) |
| #define | GPIO_INTSTS_FLISTS6_Pos (6) |
| #define | GPIO_INTSTS_FLISTS6_Msk (0x1ul << GPIO_INTSTS_FLISTS6_Pos) |
| #define | GPIO_INTSTS_FLISTS7_Pos (7) |
| #define | GPIO_INTSTS_FLISTS7_Msk (0x1ul << GPIO_INTSTS_FLISTS7_Pos) |
| #define | GPIO_INTSTS_FLISTS8_Pos (8) |
| #define | GPIO_INTSTS_FLISTS8_Msk (0x1ul << GPIO_INTSTS_FLISTS8_Pos) |
| #define | GPIO_INTSTS_FLISTS9_Pos (9) |
| #define | GPIO_INTSTS_FLISTS9_Msk (0x1ul << GPIO_INTSTS_FLISTS9_Pos) |
| #define | GPIO_INTSTS_FLISTS10_Pos (10) |
| #define | GPIO_INTSTS_FLISTS10_Msk (0x1ul << GPIO_INTSTS_FLISTS10_Pos) |
| #define | GPIO_INTSTS_FLISTS11_Pos (11) |
| #define | GPIO_INTSTS_FLISTS11_Msk (0x1ul << GPIO_INTSTS_FLISTS11_Pos) |
| #define | GPIO_INTSTS_FLISTS12_Pos (12) |
| #define | GPIO_INTSTS_FLISTS12_Msk (0x1ul << GPIO_INTSTS_FLISTS12_Pos) |
| #define | GPIO_INTSTS_FLISTS13_Pos (13) |
| #define | GPIO_INTSTS_FLISTS13_Msk (0x1ul << GPIO_INTSTS_FLISTS13_Pos) |
| #define | GPIO_INTSTS_FLISTS14_Pos (14) |
| #define | GPIO_INTSTS_FLISTS14_Msk (0x1ul << GPIO_INTSTS_FLISTS14_Pos) |
| #define | GPIO_INTSTS_FLISTS15_Pos (15) |
| #define | GPIO_INTSTS_FLISTS15_Msk (0x1ul << GPIO_INTSTS_FLISTS15_Pos) |
| #define | GPIO_INTSTS_RHISTS0_Pos (16) |
| #define | GPIO_INTSTS_RHISTS0_Msk (0x1ul << GPIO_INTSTS_RHISTS0_Pos) |
| #define | GPIO_INTSTS_RHISTS1_Pos (17) |
| #define | GPIO_INTSTS_RHISTS1_Msk (0x1ul << GPIO_INTSTS_RHISTS1_Pos) |
| #define | GPIO_INTSTS_RHISTS2_Pos (18) |
| #define | GPIO_INTSTS_RHISTS2_Msk (0x1ul << GPIO_INTSTS_RHISTS2_Pos) |
| #define | GPIO_INTSTS_RHISTS3_Pos (19) |
| #define | GPIO_INTSTS_RHISTS3_Msk (0x1ul << GPIO_INTSTS_RHISTS3_Pos) |
| #define | GPIO_INTSTS_RHISTS4_Pos (20) |
| #define | GPIO_INTSTS_RHISTS4_Msk (0x1ul << GPIO_INTSTS_RHISTS4_Pos) |
| #define | GPIO_INTSTS_RHISTS5_Pos (21) |
| #define | GPIO_INTSTS_RHISTS5_Msk (0x1ul << GPIO_INTSTS_RHISTS5_Pos) |
| #define | GPIO_INTSTS_RHISTS6_Pos (22) |
| #define | GPIO_INTSTS_RHISTS6_Msk (0x1ul << GPIO_INTSTS_RHISTS6_Pos) |
| #define | GPIO_INTSTS_RHISTS7_Pos (23) |
| #define | GPIO_INTSTS_RHISTS7_Msk (0x1ul << GPIO_INTSTS_RHISTS7_Pos) |
| #define | GPIO_INTSTS_RHISTS8_Pos (24) |
| #define | GPIO_INTSTS_RHISTS8_Msk (0x1ul << GPIO_INTSTS_RHISTS8_Pos) |
| #define | GPIO_INTSTS_RHISTS9_Pos (25) |
| #define | GPIO_INTSTS_RHISTS9_Msk (0x1ul << GPIO_INTSTS_RHISTS9_Pos) |
| #define | GPIO_INTSTS_RHISTS10_Pos (26) |
| #define | GPIO_INTSTS_RHISTS10_Msk (0x1ul << GPIO_INTSTS_RHISTS10_Pos) |
| #define | GPIO_INTSTS_RHISTS11_Pos (27) |
| #define | GPIO_INTSTS_RHISTS11_Msk (0x1ul << GPIO_INTSTS_RHISTS11_Pos) |
| #define | GPIO_INTSTS_RHISTS12_Pos (28) |
| #define | GPIO_INTSTS_RHISTS12_Msk (0x1ul << GPIO_INTSTS_RHISTS12_Pos) |
| #define | GPIO_INTSTS_RHISTS13_Pos (29) |
| #define | GPIO_INTSTS_RHISTS13_Msk (0x1ul << GPIO_INTSTS_RHISTS13_Pos) |
| #define | GPIO_INTSTS_RHISTS14_Pos (30) |
| #define | GPIO_INTSTS_RHISTS14_Msk (0x1ul << GPIO_INTSTS_RHISTS14_Pos) |
| #define | GPIO_INTSTS_RHISTS15_Pos (31) |
| #define | GPIO_INTSTS_RHISTS15_Msk (0x1ul << GPIO_INTSTS_RHISTS15_Pos) |
| #define | GPIO_DBCTL_DBCLKSEL_Pos (0) |
| #define | GPIO_DBCTL_DBCLKSEL_Msk (0xful << GPIO_DBCTL_DBCLKSEL_Pos) |
| #define | GPIO_DBCTL_DBCLKSRC_Pos (4) |
| #define | GPIO_DBCTL_DBCLKSRC_Msk (0x1ul << GPIO_DBCTL_DBCLKSRC_Pos) |
| #define | GPIO_DBCTL_ICLKON_Pos (5) |
| #define | GPIO_DBCTL_ICLKON_Msk (0x1ul << GPIO_DBCTL_ICLKON_Pos) |
| #define | PDMA_CH_CTLn_CHEN_Pos (0) |
| #define | PDMA_CH_CTLn_CHEN_Msk (0x1ul << PDMA_CH_CTLn_CHEN_Pos) |
| #define | PDMA_CH_CTLn_SWRST_Pos (1) |
| #define | PDMA_CH_CTLn_SWRST_Msk (0x1ul << PDMA_CH_CTLn_SWRST_Pos) |
| #define | PDMA_CH_CTLn_SASEL_Pos (4) |
| #define | PDMA_CH_CTLn_SASEL_Msk (0x3ul << PDMA_CH_CTLn_SASEL_Pos) |
| #define | PDMA_CH_CTLn_DASEL_Pos (6) |
| #define | PDMA_CH_CTLn_DASEL_Msk (0x3ul << PDMA_CH_CTLn_DASEL_Pos) |
| #define | PDMA_CH_CTLn_TOUTEN_Pos (12) |
| #define | PDMA_CH_CTLn_TOUTEN_Msk (0x1ul << PDMA_CH_CTLn_TOUTEN_Pos) |
| #define | PDMA_CH_CTLn_TXWIDTH_Pos (19) |
| #define | PDMA_CH_CTLn_TXWIDTH_Msk (0x3ul << PDMA_CH_CTLn_TXWIDTH_Pos) |
| #define | PDMA_CH_CTLn_TRIGEN_Pos (23) |
| #define | PDMA_CH_CTLn_TRIGEN_Msk (0x1ul << PDMA_CH_CTLn_TRIGEN_Pos) |
| #define | PDMA_CH_SAn_SA_Pos (0) |
| #define | PDMA_CH_SAn_SA_Msk (0xfffffffful << PDMA_CH_SAn_SA_Pos) |
| #define | PDMA_CH_DAn_DA_Pos (0) |
| #define | PDMA_CH_DAn_DA_Msk (0xfffffffful << PDMA_CH_DAn_DA_Pos) |
| #define | PDMA_CH_CNTn_TCNT_Pos (0) |
| #define | PDMA_CH_CNTn_TCNT_Msk (0xfffful << PDMA_CH_CNTn_TCNT_Pos) |
| #define | PDMA_CH_CNTn_PCNTITH_Pos (16) |
| #define | PDMA_CH_CNTn_PCNTITH_Msk (0xfffful << PDMA_CH_CNTn_PCNTITH_Pos) |
| #define | PDMA_CH_CSAn_CSA_Pos (0) |
| #define | PDMA_CH_CSAn_CSA_Msk (0xfffffffful << PDMA_CH_CSAn_CSA_Pos) |
| #define | PDMA_CH_CDAn_CDA_Pos (0) |
| #define | PDMA_CH_CDAn_CDA_Msk (0xfffffffful << PDMA_CH_CDAn_CDA_Pos) |
| #define | PDMA_CH_CCNTn_CCNT_Pos (0) |
| #define | PDMA_CH_CCNTn_CCNT_Msk (0xfffful << PDMA_CH_CCNTn_CCNT_Pos) |
| #define | PDMA_CH_INTENn_TABTIEN_Pos (0) |
| #define | PDMA_CH_INTENn_TABTIEN_Msk (0x1ul << PDMA_CH_INTENn_TABTIEN_Pos) |
| #define | PDMA_CH_INTENn_TDIEN_Pos (1) |
| #define | PDMA_CH_INTENn_TDIEN_Msk (0x1ul << PDMA_CH_INTENn_TDIEN_Pos) |
| #define | PDMA_CH_INTENn_TOUTIEN_Pos (6) |
| #define | PDMA_CH_INTENn_TOUTIEN_Msk (0x1ul << PDMA_CH_INTENn_TOUTIEN_Pos) |
| #define | PDMA_CH_INTENn_PCNTIEN_Pos (8) |
| #define | PDMA_CH_INTENn_PCNTIEN_Msk (0x1ul << PDMA_CH_INTENn_PCNTIEN_Pos) |
| #define | PDMA_CH_INTSTSn_TABTIF_Pos (0) |
| #define | PDMA_CH_INTSTSn_TABTIF_Msk (0x1ul << PDMA_CH_INTSTSn_TABTIF_Pos) |
| #define | PDMA_CH_INTSTSn_TDIF_Pos (1) |
| #define | PDMA_CH_INTSTSn_TDIF_Msk (0x1ul << PDMA_CH_INTSTSn_TDIF_Pos) |
| #define | PDMA_CH_INTSTSn_TOUTIF_Pos (6) |
| #define | PDMA_CH_INTSTSn_TOUTIF_Msk (0x1ul << PDMA_CH_INTSTSn_TOUTIF_Pos) |
| #define | PDMA_CH_INTSTSn_PCNTIF_Pos (8) |
| #define | PDMA_CH_INTSTSn_PCNTIF_Msk (0x1ul << PDMA_CH_INTSTSn_PCNTIF_Pos) |
| #define | PDMA_CH_TOCn_TOC_Pos (0) |
| #define | PDMA_CH_TOCn_TOC_Msk (0xfffful << PDMA_CH_TOCn_TOC_Pos) |
| #define | PDMA_CH_TOCn_TPSC_Pos (16) |
| #define | PDMA_CH_TOCn_TPSC_Msk (0x7ul << PDMA_CH_TOCn_TPSC_Pos) |
| #define | DMA_CRC_CTL_CRCEN_Pos (0) |
| #define | DMA_CRC_CTL_CRCEN_Msk (0x1ul << DMA_CRC_CTL_CRCEN_Pos) |
| #define | DMA_CRC_CTL_CRCRST_Pos (1) |
| #define | DMA_CRC_CTL_CRCRST_Msk (0x1ul << DMA_CRC_CTL_CRCRST_Pos) |
| #define | DMA_CRC_CTL_TRIGEN_Pos (23) |
| #define | DMA_CRC_CTL_TRIGEN_Msk (0x1ul << DMA_CRC_CTL_TRIGEN_Pos) |
| #define | DMA_CRC_CTL_DATREV_Pos (24) |
| #define | DMA_CRC_CTL_DATREV_Msk (0x1ul << DMA_CRC_CTL_DATREV_Pos) |
| #define | DMA_CRC_CTL_CHKSREV_Pos (25) |
| #define | DMA_CRC_CTL_CHKSREV_Msk (0x1ul << DMA_CRC_CTL_CHKSREV_Pos) |
| #define | DMA_CRC_CTL_DATFMT_Pos (26) |
| #define | DMA_CRC_CTL_DATFMT_Msk (0x1ul << DMA_CRC_CTL_DATFMT_Pos) |
| #define | DMA_CRC_CTL_CHKSFMT_Pos (27) |
| #define | DMA_CRC_CTL_CHKSFMT_Msk (0x1ul << DMA_CRC_CTL_CHKSFMT_Pos) |
| #define | DMA_CRC_CTL_DATLEN_Pos (28) |
| #define | DMA_CRC_CTL_DATLEN_Msk (0x3ul << DMA_CRC_CTL_DATLEN_Pos) |
| #define | DMA_CRC_CTL_CRCMODE_Pos (30) |
| #define | DMA_CRC_CTL_CRCMODE_Msk (0x3ul << DMA_CRC_CTL_CRCMODE_Pos) |
| #define | DMA_CRC_DMASA_SA_Pos (0) |
| #define | DMA_CRC_DMASA_SA_Msk (0xfffffffful << DMA_CRC_DMASA_SA_Pos) |
| #define | DMA_CRC_DMABCNT_BCNT_Pos (0) |
| #define | DMA_CRC_DMABCNT_BCNT_Msk (0xfffful << DMA_CRC_DMABCNT_BCNT_Pos) |
| #define | DMA_CRC_DMACSA_CSA_Pos (0) |
| #define | DMA_CRC_DMACSA_CSA_Msk (0xfffffffful << DMA_CRC_DMACSA_CSA_Pos) |
| #define | DMA_CRC_DMACBCNT_CBCNT_Pos (0) |
| #define | DMA_CRC_DMACBCNT_CBCNT_Msk (0xfffful << DMA_CRC_DMACBCNT_CBCNT_Pos) |
| #define | DMA_CRC_DMAINTEN_TABTIEN_Pos (0) |
| #define | DMA_CRC_DMAINTEN_TABTIEN_Msk (0x1ul << DMA_CRC_DMAINTEN_TABTIEN_Pos) |
| #define | DMA_CRC_DMAINTEN_TDIEN_Pos (1) |
| #define | DMA_CRC_DMAINTEN_TDIEN_Msk (0x1ul << DMA_CRC_DMAINTEN_TDIEN_Pos) |
| #define | DMA_CRC_DMAISTS_TABTIF_Pos (0) |
| #define | DMA_CRC_DMAISTS_TABTIF_Msk (0x1ul << DMA_CRC_DMAISTS_TABTIF_Pos) |
| #define | DMA_CRC_DMAISTS_TDIF_Pos (1) |
| #define | DMA_CRC_DMAISTS_TDIF_Msk (0x1ul << DMA_CRC_DMAISTS_TDIF_Pos) |
| #define | DMA_CRC_DAT_DATA_Pos (0) |
| #define | DMA_CRC_DAT_DATA_Msk (0xfffffffful << DMA_CRC_DAT_DATA_Pos) |
| #define | DMA_CRC_SEED_SEED_Pos (0) |
| #define | DMA_CRC_SEED_SEED_Msk (0xfffffffful << DMA_CRC_SEED_SEED_Pos) |
| #define | DMA_CRC_CHECKSUM_CHECKSUM_Pos (0) |
| #define | DMA_CRC_CHECKSUM_CHECKSUM_Msk (0xfffffffful << DMA_CRC_CHECKSUM_CHECKSUM_Pos) |
| #define | DMA_GCR_GCTL_CKEN1_Pos (9) |
| #define | DMA_GCR_GCTL_CKEN1_Msk (0x1ul << DMA_GCR_GCTL_CKEN1_Pos) |
| #define | DMA_GCR_GCTL_CKEN2_Pos (10) |
| #define | DMA_GCR_GCTL_CKEN2_Msk (0x1ul << DMA_GCR_GCTL_CKEN2_Pos) |
| #define | DMA_GCR_GCTL_CKEN3_Pos (11) |
| #define | DMA_GCR_GCTL_CKEN3_Msk (0x1ul << DMA_GCR_GCTL_CKEN3_Pos) |
| #define | DMA_GCR_GCTL_CKEN4_Pos (12) |
| #define | DMA_GCR_GCTL_CKEN4_Msk (0x1ul << DMA_GCR_GCTL_CKEN4_Pos) |
| #define | DMA_GCR_GCTL_CKENCRC_Pos (24) |
| #define | DMA_GCR_GCTL_CKENCRC_Msk (0x1ul << DMA_GCR_GCTL_CKENCRC_Pos) |
| #define | DMA_GCR_REQSEL0_REQSRC1_Pos (8) |
| #define | DMA_GCR_REQSEL0_REQSRC1_Msk (0x1ful << DMA_GCR_REQSEL0_REQSRC1_Pos) |
| #define | DMA_GCR_REQSEL0_REQSRC2_Pos (16) |
| #define | DMA_GCR_REQSEL0_REQSRC2_Msk (0x1ful << DMA_GCR_REQSEL0_REQSRC2_Pos) |
| #define | DMA_GCR_REQSEL0_REQSRC3_Pos (24) |
| #define | DMA_GCR_REQSEL0_REQSRC3_Msk (0x1ful << DMA_GCR_REQSEL0_REQSRC3_Pos) |
| #define | DMA_GCR_REQSEL1_REQSRC4_Pos (0) |
| #define | DMA_GCR_REQSEL1_REQSRC4_Msk (0x1ful << DMA_GCR_REQSEL1_REQSRC4_Pos) |
| #define | DMA_GCR_GINTSTS_IF1_Pos (1) |
| #define | DMA_GCR_GINTSTS_IF1_Msk (0x1ul << DMA_GCR_GINTSTS_IF1_Pos) |
| #define | DMA_GCR_GINTSTS_IF2_Pos (2) |
| #define | DMA_GCR_GINTSTS_IF2_Msk (0x1ul << DMA_GCR_GINTSTS_IF2_Pos) |
| #define | DMA_GCR_GINTSTS_IF3_Pos (3) |
| #define | DMA_GCR_GINTSTS_IF3_Msk (0x1ul << DMA_GCR_GINTSTS_IF3_Pos) |
| #define | DMA_GCR_GINTSTS_IF4_Pos (4) |
| #define | DMA_GCR_GINTSTS_IF4_Msk (0x1ul << DMA_GCR_GINTSTS_IF4_Pos) |
| #define | DMA_GCR_GINTSTS_IFCRC_Pos (16) |
| #define | DMA_GCR_GINTSTS_IFCRC_Msk (0x1ul << DMA_GCR_GINTSTS_IFCRC_Pos) |
| #define | TIMER_CTL_CNTEN_Pos (0) |
| #define | TIMER_CTL_CNTEN_Msk (0x1ul << TIMER_CTL_CNTEN_Pos) |
| #define | TIMER_CTL_RSTCNT_Pos (1) |
| #define | TIMER_CTL_RSTCNT_Msk (0x1ul << TIMER_CTL_RSTCNT_Pos) |
| #define | TIMER_CTL_WKEN_Pos (2) |
| #define | TIMER_CTL_WKEN_Msk (0x1ul << TIMER_CTL_WKEN_Pos) |
| #define | TIMER_CTL_ICEDEBUG_Pos (3) |
| #define | TIMER_CTL_ICEDEBUG_Msk (0x1ul << TIMER_CTL_ICEDEBUG_Pos) |
| #define | TIMER_CTL_OPMODE_Pos (4) |
| #define | TIMER_CTL_OPMODE_Msk (0x3ul << TIMER_CTL_OPMODE_Pos) |
| #define | TIMER_CTL_ACTSTS_Pos (7) |
| #define | TIMER_CTL_ACTSTS_Msk (0x1ul << TIMER_CTL_ACTSTS_Pos) |
| #define | TIMER_CTL_TRGADC_Pos (8) |
| #define | TIMER_CTL_TRGADC_Msk (0x1ul << TIMER_CTL_TRGADC_Pos) |
| #define | TIMER_CTL_TRGPDMA_Pos (10) |
| #define | TIMER_CTL_TRGPDMA_Msk (0x1ul << TIMER_CTL_TRGPDMA_Pos) |
| #define | TIMER_CTL_TRGSSEL_Pos (11) |
| #define | TIMER_CTL_TRGSSEL_Msk (0x1ul << TIMER_CTL_TRGSSEL_Pos) |
| #define | TIMER_CTL_EXTCNTEN_Pos (12) |
| #define | TIMER_CTL_EXTCNTEN_Msk (0x1ul << TIMER_CTL_EXTCNTEN_Pos) |
| #define | TIMER_CTL_CNTPHASE_Pos (13) |
| #define | TIMER_CTL_CNTPHASE_Msk (0x1ul << TIMER_CTL_CNTPHASE_Pos) |
| #define | TIMER_CTL_CNTDBEN_Pos (14) |
| #define | TIMER_CTL_CNTDBEN_Msk (0x1ul << TIMER_CTL_CNTDBEN_Pos) |
| #define | TIMER_CTL_CAPEN_Pos (16) |
| #define | TIMER_CTL_CAPEN_Msk (0x1ul << TIMER_CTL_CAPEN_Pos) |
| #define | TIMER_CTL_CAPFUNCS_Pos (17) |
| #define | TIMER_CTL_CAPFUNCS_Msk (0x1ul << TIMER_CTL_CAPFUNCS_Pos) |
| #define | TIMER_CTL_CAPEDGE_Pos (18) |
| #define | TIMER_CTL_CAPEDGE_Msk (0x3ul << TIMER_CTL_CAPEDGE_Pos) |
| #define | TIMER_CTL_CAPCNTMD_Pos (20) |
| #define | TIMER_CTL_CAPCNTMD_Msk (0x1ul << TIMER_CTL_CAPCNTMD_Pos) |
| #define | TIMER_CTL_CAPDBEN_Pos (22) |
| #define | TIMER_CTL_CAPDBEN_Msk (0x1ul << TIMER_CTL_CAPDBEN_Pos) |
| #define | TIMER_CTL_CMPCTL_Pos (23) |
| #define | TIMER_CTL_CMPCTL_Msk (0x1ul << TIMER_CTL_CMPCTL_Pos) |
| #define | TIMER_CTL_INTRTGEN_Pos (24) |
| #define | TIMER_CTL_INTRTGEN_Msk (0x1ul << TIMER_CTL_INTRTGEN_Pos) |
| #define | TIMER_CTL_INTRTGMD_Pos (25) |
| #define | TIMER_CTL_INTRTGMD_Msk (0x1ul << TIMER_CTL_INTRTGMD_Pos) |
| #define | TIMER_CTL_TRGPWM_Pos (28) |
| #define | TIMER_CTL_TRGPWM_Msk (0x1ul << TIMER_CTL_TRGPWM_Pos) |
| #define | TIMER_PRECNT_PSC_Pos (0) |
| #define | TIMER_PRECNT_PSC_Msk (0xfful << TIMER_PRECNT_PSC_Pos) |
| #define | TIMER_CMP_CMPDAT_Pos (0) |
| #define | TIMER_CMP_CMPDAT_Msk (0xfffffful << TIMER_CMP_CMPDAT_P) |
| #define | TIMER_INTEN_CNTIEN_Pos (0) |
| #define | TIMER_INTEN_CNTIEN_Msk (0x1ul << TIMER_INTEN_CNTIEN_Pos) |
| #define | TIMER_INTEN_CAPIEN_Pos (1) |
| #define | TIMER_INTEN_CAPIEN_Msk (0x1ul << TIMER_INTEN_CAPIEN_Pos) |
| #define | TIMER_INTSTS_CNTIF_Pos (0) |
| #define | TIMER_INTSTS_CNTIF_Msk (0x1ul << TIMER_INTSTS_CNTIF_Pos) |
| #define | TIMER_INTSTS_CAPIF_Pos (1) |
| #define | TIMER_INTSTS_CAPIF_Msk (0x1ul << TIMER_INTSTS_CAPIF_Pos) |
| #define | TIMER_INTSTS_TWKF_Pos (4) |
| #define | TIMER_INTSTS_TWKF_Msk (0x1ul << TIMER_INTSTS_TWKF_Pos) |
| #define | TIMER_INTSTS_CAPDATOF_Pos (5) |
| #define | TIMER_INTSTS_CAPDATOF_Msk (0x1ul << TIMER_INTSTS_CAPDATOF_Pos) |
| #define | TIMER_INTSTS_CAPFEDF_Pos (6) |
| #define | TIMER_INTSTS_CAPFEDF_Msk (0x1ul << TIMER_INTSTS_CAPFEDF_Pos) |
| #define | TIMER_CNT_CNT_Pos (0) |
| #define | TIMER_CNT_CNT_Msk (0xfffffful << TIMER_CNT_CNT_Pos) |
| #define | TIMER_CNT_RSTACT_Pos (31) |
| #define | TIMER_CNT_RSTACT_Msk (0x1ul << TIMER_CNT_RSTACT_Pos) |
| #define | TIMER_CAP_CAPDAT_Pos (0) |
| #define | TIMER_CAP_CAPDAT_Msk (0xfffffful << TIMER_CAP_CAPDAT_Pos) |
| #define | TIMER_ECTL_EVNTDPCNT_Pos (24) |
| #define | TIMER_ECTL_EVNTDPCNT_Msk (0xfful << TIMER_ECTL_EVNTDPCNT_Pos) |
| #define | PWM_CTL0_CTRLDn_Pos (0) |
| #define | PWM_CTL0_CTRLDn_Msk (0x3ful << PWM_CTL0_CTRLDn_Pos) |
| #define | PWM_CTL0_IMMLDENn_Pos (16) |
| #define | PWM_CTL0_IMMLDENn_Msk (0x3ful << PWM_CTL0_IMMLDENn_Pos) |
| #define | PWM_CTL0_DBGHALT_Pos (30) |
| #define | PWM_CTL0_DBGHALT_Msk (0x1ul << PWM_CTL0_DBGHALT_Pos) |
| #define | PWM_CTL0_DBGTRIOFF_Pos (31) |
| #define | PWM_CTL0_DBGTRIOFF_Msk (0x1ul << PWM_CTL0_DBGTRIOFF_Pos) |
| #define | PWM_CTL1_CNTTYPE0_Pos (0) |
| #define | PWM_CTL1_CNTTYPE0_Msk (0x3ul << PWM_CTL1_CNTTYPE0_Pos) |
| #define | PWM_CTL1_CNTTYPE2_Pos (4) |
| #define | PWM_CTL1_CNTTYPE2_Msk (0x3ul << PWM_CTL1_CNTTYPE2_Pos) |
| #define | PWM_CTL1_CNTTYPE4_Pos (8) |
| #define | PWM_CTL1_CNTTYPE4_Msk (0x3ul << PWM_CTL1_CNTTYPE4_Pos) |
| #define | PWM_CTL1_PWMMODEn_Pos (24) |
| #define | PWM_CTL1_PWMMODEn_Msk (0x7ul << PWM_CTL1_PWMMODEn_Pos) |
| #define | PWM_CLKSRC_ECLKSRC0_Pos (0) |
| #define | PWM_CLKSRC_ECLKSRC0_Msk (0x7ul << PWM_CLKSRC_ECLKSRC0_Pos) |
| #define | PWM_CLKSRC_ECLKSRC2_Pos (8) |
| #define | PWM_CLKSRC_ECLKSRC2_Msk (0x7ul << PWM_CLKSRC_ECLKSRC2_Pos) |
| #define | PWM_CLKSRC_ECLKSRC4_Pos (16) |
| #define | PWM_CLKSRC_ECLKSRC4_Msk (0x7ul << PWM_CLKSRC_ECLKSRC4_Pos) |
| #define | PWM_CLKPSC0_1_CLKPSC_Pos (0) |
| #define | PWM_CLKPSC0_1_CLKPSC_Msk (0xffful << PWM_CLKPSC0_1_CLKPSC_Pos) |
| #define | PWM_CLKPSC2_3_CLKPSC_Pos (0) |
| #define | PWM_CLKPSC2_3_CLKPSC_Msk (0xffful << PWM_CLKPSC2_3_CLKPSC_Pos) |
| #define | PWM_CLKPSC4_5_CLKPSC_Pos (0) |
| #define | PWM_CLKPSC4_5_CLKPSC_Msk (0xffful << PWM_CLKPSC4_5_CLKPSC_Pos) |
| #define | PWM_CNTEN_CNTEN0_Pos (0) |
| #define | PWM_CNTEN_CNTEN0_Msk (0x1ul << PWM_CNTEN_CNTEN0_Pos) |
| #define | PWM_CNTEN_CNTEN2_Pos (2) |
| #define | PWM_CNTEN_CNTEN2_Msk (0x1ul << PWM_CNTEN_CNTEN2_Pos) |
| #define | PWM_CNTEN_CNTEN4_Pos (4) |
| #define | PWM_CNTEN_CNTEN4_Msk (0x1ul << PWM_CNTEN_CNTEN4_Pos) |
| #define | PWM_CNTCLR_CNTCLR0_Pos (0) |
| #define | PWM_CNTCLR_CNTCLR0_Msk (0x1ul << PWM_CNTCLR_CNTCLR0_Pos) |
| #define | PWM_CNTCLR_CNTCLR2_Pos (2) |
| #define | PWM_CNTCLR_CNTCLR2_Msk (0x1ul << PWM_CNTCLR_CNTCLR2_Pos) |
| #define | PWM_CNTCLR_CNTCLR4_Pos (4) |
| #define | PWM_CNTCLR_CNTCLR4_Msk (0x1ul << PWM_CNTCLR_CNTCLR4_Pos) |
| #define | PWM_PERIOD0_PERIOD_Pos (0) |
| #define | PWM_PERIOD0_PERIOD_Msk (0xfffful << PWM_PERIOD0_PERIOD_Pos) |
| #define | PWM_CMPDAT0_CMPDAT_Pos (0) |
| #define | PWM_CMPDAT0_CMPDAT_Msk (0xfffful << PWM_CMPDAT0_CMPDAT_Pos) |
| #define | PWM_DTCTL0_1_DTCNT_Pos (0) |
| #define | PWM_DTCTL0_1_DTCNT_Msk (0xffful << PWM_DTCTL0_1_DTCNT_Pos) |
| #define | PWM_DTCTL0_1_DTEN_Pos (16) |
| #define | PWM_DTCTL0_1_DTEN_Msk (0x1ul << PWM_DTCTL0_1_DTEN_Pos) |
| #define | PWM_DTCTL0_1_DTCKSEL_Pos (24) |
| #define | PWM_DTCTL0_1_DTCKSEL_Msk (0x1ul << PWM_DTCTL0_1_DTCKSEL_Pos) |
| #define | PWM_DTCTL2_3_DTCNT_Pos (0) |
| #define | PWM_DTCTL2_3_DTCNT_Msk (0xffful << PWM_DTCTL2_3_DTCNT_Pos) |
| #define | PWM_DTCTL2_3_DTEN_Pos (16) |
| #define | PWM_DTCTL2_3_DTEN_Msk (0x1ul << PWM_DTCTL2_3_DTEN_Pos) |
| #define | PWM_DTCTL2_3_DTCKSEL_Pos (24) |
| #define | PWM_DTCTL2_3_DTCKSEL_Msk (0x1ul << PWM_DTCTL2_3_DTCKSEL_Pos) |
| #define | PWM_DTCTL4_5_DTCNT_Pos (0) |
| #define | PWM_DTCTL4_5_DTCNT_Msk (0xffful << PWM_DTCTL4_5_DTCNT_Pos) |
| #define | PWM_DTCTL4_5_DTEN_Pos (16) |
| #define | PWM_DTCTL4_5_DTEN_Msk (0x1ul << PWM_DTCTL4_5_DTEN_Pos) |
| #define | PWM_DTCTL4_5_DTCKSEL_Pos (24) |
| #define | PWM_DTCTL4_5_DTCKSEL_Msk (0x1ul << PWM_DTCTL4_5_DTCKSEL_Pos) |
| #define | PWM_CNT0_CNT_Pos (0) |
| #define | PWM_CNT0_CNT_Msk (0xfffful << PWM_CNT0_CNT_Pos) |
| #define | PWM_CNT0_DIRF_Pos (16) |
| #define | PWM_CNT0_DIRF_Msk (0x1ul << PWM_CNT0_DIRF_Pos) |
| #define | PWM_WGCTL0_ZPCTLn_Pos (0) |
| #define | PWM_WGCTL0_ZPCTLn_Msk (0xffful << PWM_WGCTL0_ZPCTLn_Pos) |
| #define | PWM_WGCTL0_PRDPCTLn_Pos (16) |
| #define | PWM_WGCTL0_PRDPCTLn_Msk (0xffful << PWM_WGCTL0_PRDPCTLn_Pos) |
| #define | PWM_WGCTL1_CMPUCTLn_Pos (0) |
| #define | PWM_WGCTL1_CMPUCTLn_Msk (0xffful << PWM_WGCTL1_CMPUCTLn_Pos) |
| #define | PWM_WGCTL1_CMPDCTLn_Pos (16) |
| #define | PWM_WGCTL1_CMPDCTLn_Msk (0xffful << PWM_WGCTL1_CMPDCTLn_Pos) |
| #define | PWM_MSKEN_MSKENn_Pos (0) |
| #define | PWM_MSKEN_MSKENn_Msk (0x3ful << PWM_MSKEN_MSKENn_Pos) |
| #define | PWM_MSK_MSKDATn_Pos (0) |
| #define | PWM_MSK_MSKDATn_Msk (0x3ful << PWM_MSK_MSKDATn_Pos) |
| #define | PWM_BNF_BRK0FEN_Pos (0) |
| #define | PWM_BNF_BRK0FEN_Msk (0x1ul << PWM_BNF_BRK0FEN_Pos) |
| #define | PWM_BNF_BRK0FCS_Pos (1) |
| #define | PWM_BNF_BRK0FCS_Msk (0x7ul << PWM_BNF_BRK0FCS_Pos) |
| #define | PWM_BNF_BRK0FCNT_Pos (4) |
| #define | PWM_BNF_BRK0FCNT_Msk (0x7ul << PWM_BNF_BRK0FCNT_Pos) |
| #define | PWM_BNF_BRK0PINV_Pos (7) |
| #define | PWM_BNF_BRK0PINV_Msk (0x1ul << PWM_BNF_BRK0PINV_Pos) |
| #define | PWM_BNF_BRK1FEN_Pos (8) |
| #define | PWM_BNF_BRK1FEN_Msk (0x1ul << PWM_BNF_BRK1FEN_Pos) |
| #define | PWM_BNF_BRK1FCS_Pos (9) |
| #define | PWM_BNF_BRK1FCS_Msk (0x7ul << PWM_BNF_BRK1FCS_Pos) |
| #define | PWM_BNF_BRK1FCNT_Pos (12) |
| #define | PWM_BNF_BRK1FCNT_Msk (0x7ul << PWM_BNF_BRK1FCNT_Pos) |
| #define | PWM_BNF_BRK1PINV_Pos (15) |
| #define | PWM_BNF_BRK1PINV_Msk (0x1ul << PWM_BNF_BRK1PINV_Pos) |
| #define | PWM_BNF_BK0SRC_Pos (16) |
| #define | PWM_BNF_BK0SRC_Msk (0x1ul << PWM_BNF_BK0SRC_Pos) |
| #define | PWM_BNF_BK1SRC_Pos (24) |
| #define | PWM_BNF_BK1SRC_Msk (0x1ul << PWM_BNF_BK1SRC_Pos) |
| #define | PWM_FAILBRK_BODBRKEN_Pos (1) |
| #define | PWM_FAILBRK_BODBRKEN_Msk (0x1ul << PWM_FAILBRK_BODBRKEN_Pos) |
| #define | PWM_FAILBRK_CORBRKEN_Pos (3) |
| #define | PWM_FAILBRK_CORBRKEN_Msk (0x1ul << PWM_FAILBRK_CORBRKEN_Pos) |
| #define | PWM_BRKCTL0_1_BRKP0EEN_Pos (4) |
| #define | PWM_BRKCTL0_1_BRKP0EEN_Msk (0x1ul << PWM_BRKCTL0_1_BRKP0EEN_Pos) |
| #define | PWM_BRKCTL0_1_BRKP1EEN_Pos (5) |
| #define | PWM_BRKCTL0_1_BRKP1EEN_Msk (0x1ul << PWM_BRKCTL0_1_BRKP1EEN_Pos) |
| #define | PWM_BRKCTL0_1_SYSEEN_Pos (7) |
| #define | PWM_BRKCTL0_1_SYSEEN_Msk (0x1ul << PWM_BRKCTL0_1_SYSEEN_Pos) |
| #define | PWM_BRKCTL0_1_BRKP0LEN_Pos (12) |
| #define | PWM_BRKCTL0_1_BRKP0LEN_Msk (0x1ul << PWM_BRKCTL0_1_BRKP0LEN_Pos) |
| #define | PWM_BRKCTL0_1_BRKP1LEN_Pos (13) |
| #define | PWM_BRKCTL0_1_BRKP1LEN_Msk (0x1ul << PWM_BRKCTL0_1_BRKP1LEN_Pos) |
| #define | PWM_BRKCTL0_1_SYSLEN_Pos (15) |
| #define | PWM_BRKCTL0_1_SYSLEN_Msk (0x1ul << PWM_BRKCTL0_1_SYSLEN_Pos) |
| #define | PWM_BRKCTL0_1_BRKAEVEN_Pos (16) |
| #define | PWM_BRKCTL0_1_BRKAEVEN_Msk (0x3ul << PWM_BRKCTL0_1_BRKAEVEN_Pos) |
| #define | PWM_BRKCTL0_1_BRKAODD_Pos (18) |
| #define | PWM_BRKCTL0_1_BRKAODD_Msk (0x3ul << PWM_BRKCTL0_1_BRKAODD_Pos) |
| #define | PWM_BRKCTL2_3_BRKP0EEN_Pos (4) |
| #define | PWM_BRKCTL2_3_BRKP0EEN_Msk (0x1ul << PWM_BRKCTL2_3_BRKP0EEN_Pos) |
| #define | PWM_BRKCTL2_3_BRKP1EEN_Pos (5) |
| #define | PWM_BRKCTL2_3_BRKP1EEN_Msk (0x1ul << PWM_BRKCTL2_3_BRKP1EEN_Pos) |
| #define | PWM_BRKCTL2_3_SYSEEN_Pos (7) |
| #define | PWM_BRKCTL2_3_SYSEEN_Msk (0x1ul << PWM_BRKCTL2_3_SYSEEN_Pos) |
| #define | PWM_BRKCTL2_3_BRKP0LEN_Pos (12) |
| #define | PWM_BRKCTL2_3_BRKP0LEN_Msk (0x1ul << PWM_BRKCTL2_3_BRKP0LEN_Pos) |
| #define | PWM_BRKCTL2_3_BRKP1LEN_Pos (13) |
| #define | PWM_BRKCTL2_3_BRKP1LEN_Msk (0x1ul << PWM_BRKCTL2_3_BRKP1LEN_Pos) |
| #define | PWM_BRKCTL2_3_SYSLEN_Pos (15) |
| #define | PWM_BRKCTL2_3_SYSLEN_Msk (0x1ul << PWM_BRKCTL2_3_SYSLEN_Pos) |
| #define | PWM_BRKCTL2_3_BRKAEVEN_Pos (16) |
| #define | PWM_BRKCTL2_3_BRKAEVEN_Msk (0x3ul << PWM_BRKCTL2_3_BRKAEVEN_Pos) |
| #define | PWM_BRKCTL2_3_BRKAODD_Pos (18) |
| #define | PWM_BRKCTL2_3_BRKAODD_Msk (0x3ul << PWM_BRKCTL2_3_BRKAODD_Pos) |
| #define | PWM_BRKCTL4_5_BRKP0EEN_Pos (4) |
| #define | PWM_BRKCTL4_5_BRKP0EEN_Msk (0x1ul << PWM_BRKCTL4_5_BRKP0EEN_Pos) |
| #define | PWM_BRKCTL4_5_BRKP1EEN_Pos (5) |
| #define | PWM_BRKCTL4_5_BRKP1EEN_Msk (0x1ul << PWM_BRKCTL4_5_BRKP1EEN_Pos) |
| #define | PWM_BRKCTL4_5_SYSEEN_Pos (7) |
| #define | PWM_BRKCTL4_5_SYSEEN_Msk (0x1ul << PWM_BRKCTL4_5_SYSEEN_Pos) |
| #define | PWM_BRKCTL4_5_BRKP0LEN_Pos (12) |
| #define | PWM_BRKCTL4_5_BRKP0LEN_Msk (0x1ul << PWM_BRKCTL4_5_BRKP0LEN_Pos) |
| #define | PWM_BRKCTL4_5_BRKP1LEN_Pos (13) |
| #define | PWM_BRKCTL4_5_BRKP1LEN_Msk (0x1ul << PWM_BRKCTL4_5_BRKP1LEN_Pos) |
| #define | PWM_BRKCTL4_5_SYSLEN_Pos (15) |
| #define | PWM_BRKCTL4_5_SYSLEN_Msk (0x1ul << PWM_BRKCTL4_5_SYSLEN_Pos) |
| #define | PWM_BRKCTL4_5_BRKAEVEN_Pos (16) |
| #define | PWM_BRKCTL4_5_BRKAEVEN_Msk (0x3ul << PWM_BRKCTL4_5_BRKAEVEN_Pos) |
| #define | PWM_BRKCTL4_5_BRKAODD_Pos (18) |
| #define | PWM_BRKCTL4_5_BRKAODD_Msk (0x3ul << PWM_BRKCTL4_5_BRKAODD_Pos) |
| #define | PWM_POLCTL_PINVn_Pos (0) |
| #define | PWM_POLCTL_PINVn_Msk (0x3ful << PWM_POLCTL_PINVn_Pos) |
| #define | PWM_POEN_POENn_Pos (0) |
| #define | PWM_POEN_POENn_Msk (0x3ful << PWM_POEN_POENn_Pos) |
| #define | PWM_SWBRK_BRKETRGn_Pos (0) |
| #define | PWM_SWBRK_BRKETRGn_Msk (0x7ul << PWM_SWBRK_BRKETRGn_Pos) |
| #define | PWM_SWBRK_BRKLTRGn_Pos (8) |
| #define | PWM_SWBRK_BRKLTRGn_Msk (0x7ul << PWM_SWBRK_BRKLTRGn_Pos) |
| #define | PWM_INTEN0_ZIEN0_Pos (0) |
| #define | PWM_INTEN0_ZIEN0_Msk (0x1ul << PWM_INTEN0_ZIEN0_Pos) |
| #define | PWM_INTEN0_ZIEN2_Pos (2) |
| #define | PWM_INTEN0_ZIEN2_Msk (0x1ul << PWM_INTEN0_ZIEN2_Pos) |
| #define | PWM_INTEN0_ZIEN4_Pos (4) |
| #define | PWM_INTEN0_ZIEN4_Msk (0x1ul << PWM_INTEN0_ZIEN4_Pos) |
| #define | PWM_INTEN0_PIEN0_Pos (8) |
| #define | PWM_INTEN0_PIEN0_Msk (0x1ul << PWM_INTEN0_PIEN0_Pos) |
| #define | PWM_INTEN0_PIEN2_Pos (10) |
| #define | PWM_INTEN0_PIEN2_Msk (0x1ul << PWM_INTEN0_PIEN2_Pos) |
| #define | PWM_INTEN0_PIEN4_Pos (12) |
| #define | PWM_INTEN0_PIEN4_Msk (0x1ul << PWM_INTEN0_PIEN4_Pos) |
| #define | PWM_INTEN0_CMPUIENn_Pos (16) |
| #define | PWM_INTEN0_CMPUIENn_Msk (0x3ful << PWM_INTEN0_CMPUIENn_Pos) |
| #define | PWM_INTEN0_CMPDIENn_Pos (24) |
| #define | PWM_INTEN0_CMPDIENn_Msk (0x3ful << PWM_INTEN0_CMPDIENn_Pos) |
| #define | PWM_INTEN1_BRKEIEN0_1_Pos (0) |
| #define | PWM_INTEN1_BRKEIEN0_1_Msk (0x1ul << PWM_INTEN1_BRKEIEN0_1_Pos) |
| #define | PWM_INTEN1_BRKEIEN2_3_Pos (1) |
| #define | PWM_INTEN1_BRKEIEN2_3_Msk (0x1ul << PWM_INTEN1_BRKEIEN2_3_Pos) |
| #define | PWM_INTEN1_BRKEIEN4_5_Pos (2) |
| #define | PWM_INTEN1_BRKEIEN4_5_Msk (0x1ul << PWM_INTEN1_BRKEIEN4_5_Pos) |
| #define | PWM_INTEN1_BRKLIEN0_1_Pos (8) |
| #define | PWM_INTEN1_BRKLIEN0_1_Msk (0x1ul << PWM_INTEN1_BRKLIEN0_1_Pos) |
| #define | PWM_INTEN1_BRKLIEN2_3_Pos (9) |
| #define | PWM_INTEN1_BRKLIEN2_3_Msk (0x1ul << PWM_INTEN1_BRKLIEN2_3_Pos) |
| #define | PWM_INTEN1_BRKLIEN4_5_Pos (10) |
| #define | PWM_INTEN1_BRKLIEN4_5_Msk (0x1ul << PWM_INTEN1_BRKLIEN4_5_Pos) |
| #define | PWM_INTSTS0_ZIF0_Pos (0) |
| #define | PWM_INTSTS0_ZIF0_Msk (0x1ul << PWM_INTSTS0_ZIF0_Pos) |
| #define | PWM_INTSTS0_ZIF2_Pos (2) |
| #define | PWM_INTSTS0_ZIF2_Msk (0x1ul << PWM_INTSTS0_ZIF2_Pos) |
| #define | PWM_INTSTS0_ZIF4_Pos (4) |
| #define | PWM_INTSTS0_ZIF4_Msk (0x1ul << PWM_INTSTS0_ZIF4_Pos) |
| #define | PWM_INTSTS0_PIF0_Pos (8) |
| #define | PWM_INTSTS0_PIF0_Msk (0x1ul << PWM_INTSTS0_PIF0_Pos) |
| #define | PWM_INTSTS0_PIF2_Pos (10) |
| #define | PWM_INTSTS0_PIF2_Msk (0x1ul << PWM_INTSTS0_PIF2_Pos) |
| #define | PWM_INTSTS0_PIF4_Pos (12) |
| #define | PWM_INTSTS0_PIF4_Msk (0x1ul << PWM_INTSTS0_PIF4_Pos) |
| #define | PWM_INTSTS0_CMPUIFn_Pos (16) |
| #define | PWM_INTSTS0_CMPUIFn_Msk (0x3ful << PWM_INTSTS0_CMPUIFn_Pos) |
| #define | PWM_INTSTS0_CMPDIFn_Pos (24) |
| #define | PWM_INTSTS0_CMPDIFn_Msk (0x3ful << PWM_INTSTS0_CMPDIFn_Pos) |
| #define | PWM_INTSTS1_BRKEIF0_Pos (0) |
| #define | PWM_INTSTS1_BRKEIF0_Msk (0x1ul << PWM_INTSTS1_BRKEIF0_Pos) |
| #define | PWM_INTSTS1_BRKEIF1_Pos (1) |
| #define | PWM_INTSTS1_BRKEIF1_Msk (0x1ul << PWM_INTSTS1_BRKEIF1_Pos) |
| #define | PWM_INTSTS1_BRKEIF2_Pos (2) |
| #define | PWM_INTSTS1_BRKEIF2_Msk (0x1ul << PWM_INTSTS1_BRKEIF2_Pos) |
| #define | PWM_INTSTS1_BRKEIF3_Pos (3) |
| #define | PWM_INTSTS1_BRKEIF3_Msk (0x1ul << PWM_INTSTS1_BRKEIF3_Pos) |
| #define | PWM_INTSTS1_BRKEIF4_Pos (4) |
| #define | PWM_INTSTS1_BRKEIF4_Msk (0x1ul << PWM_INTSTS1_BRKEIF4_Pos) |
| #define | PWM_INTSTS1_BRKEIF5_Pos (5) |
| #define | PWM_INTSTS1_BRKEIF5_Msk (0x1ul << PWM_INTSTS1_BRKEIF5_Pos) |
| #define | PWM_INTSTS1_BRKLIF0_Pos (8) |
| #define | PWM_INTSTS1_BRKLIF0_Msk (0x1ul << PWM_INTSTS1_BRKLIF0_Pos) |
| #define | PWM_INTSTS1_BRKLIF1_Pos (9) |
| #define | PWM_INTSTS1_BRKLIF1_Msk (0x1ul << PWM_INTSTS1_BRKLIF1_Pos) |
| #define | PWM_INTSTS1_BRKLIF2_Pos (10) |
| #define | PWM_INTSTS1_BRKLIF2_Msk (0x1ul << PWM_INTSTS1_BRKLIF2_Pos) |
| #define | PWM_INTSTS1_BRKLIF3_Pos (11) |
| #define | PWM_INTSTS1_BRKLIF3_Msk (0x1ul << PWM_INTSTS1_BRKLIF3_Pos) |
| #define | PWM_INTSTS1_BRKLIF4_Pos (12) |
| #define | PWM_INTSTS1_BRKLIF4_Msk (0x1ul << PWM_INTSTS1_BRKLIF4_Pos) |
| #define | PWM_INTSTS1_BRKLIF5_Pos (13) |
| #define | PWM_INTSTS1_BRKLIF5_Msk (0x1ul << PWM_INTSTS1_BRKLIF5_Pos) |
| #define | PWM_INTSTS1_BRKESTS0_Pos (16) |
| #define | PWM_INTSTS1_BRKESTS0_Msk (0x1ul << PWM_INTSTS1_BRKESTS0_Pos) |
| #define | PWM_INTSTS1_BRKESTS1_Pos (17) |
| #define | PWM_INTSTS1_BRKESTS1_Msk (0x1ul << PWM_INTSTS1_BRKESTS1_Pos) |
| #define | PWM_INTSTS1_BRKESTS2_Pos (18) |
| #define | PWM_INTSTS1_BRKESTS2_Msk (0x1ul << PWM_INTSTS1_BRKESTS2_Pos) |
| #define | PWM_INTSTS1_BRKESTS3_Pos (19) |
| #define | PWM_INTSTS1_BRKESTS3_Msk (0x1ul << PWM_INTSTS1_BRKESTS3_Pos) |
| #define | PWM_INTSTS1_BRKESTS4_Pos (20) |
| #define | PWM_INTSTS1_BRKESTS4_Msk (0x1ul << PWM_INTSTS1_BRKESTS4_Pos) |
| #define | PWM_INTSTS1_BRKESTS5_Pos (21) |
| #define | PWM_INTSTS1_BRKESTS5_Msk (0x1ul << PWM_INTSTS1_BRKESTS5_Pos) |
| #define | PWM_INTSTS1_BRKLSTS0_Pos (24) |
| #define | PWM_INTSTS1_BRKLSTS0_Msk (0x1ul << PWM_INTSTS1_BRKLSTS0_Pos) |
| #define | PWM_INTSTS1_BRKLSTS1_Pos (25) |
| #define | PWM_INTSTS1_BRKLSTS1_Msk (0x1ul << PWM_INTSTS1_BRKLSTS1_Pos) |
| #define | PWM_INTSTS1_BRKLSTS2_Pos (26) |
| #define | PWM_INTSTS1_BRKLSTS2_Msk (0x1ul << PWM_INTSTS1_BRKLSTS2_Pos) |
| #define | PWM_INTSTS1_BRKLSTS3_Pos (27) |
| #define | PWM_INTSTS1_BRKLSTS3_Msk (0x1ul << PWM_INTSTS1_BRKLSTS3_Pos) |
| #define | PWM_INTSTS1_BRKLSTS4_Pos (28) |
| #define | PWM_INTSTS1_BRKLSTS4_Msk (0x1ul << PWM_INTSTS1_BRKLSTS4_Pos) |
| #define | PWM_INTSTS1_BRKLSTS5_Pos (29) |
| #define | PWM_INTSTS1_BRKLSTS5_Msk (0x1ul << PWM_INTSTS1_BRKLSTS5_Pos) |
| #define | PWM_ADCTS0_TRGSEL0_Pos (0) |
| #define | PWM_ADCTS0_TRGSEL0_Msk (0xful << PWM_ADCTS0_TRGSEL0_Pos) |
| #define | PWM_ADCTS0_TRGEN0_Pos (7) |
| #define | PWM_ADCTS0_TRGEN0_Msk (0x1ul << PWM_ADCTS0_TRGEN0_Pos) |
| #define | PWM_ADCTS0_TRGSEL1_Pos (8) |
| #define | PWM_ADCTS0_TRGSEL1_Msk (0xful << PWM_ADCTS0_TRGSEL1_Pos) |
| #define | PWM_ADCTS0_TRGEN1_Pos (15) |
| #define | PWM_ADCTS0_TRGEN1_Msk (0x1ul << PWM_ADCTS0_TRGEN1_Pos) |
| #define | PWM_ADCTS0_TRGSEL2_Pos (16) |
| #define | PWM_ADCTS0_TRGSEL2_Msk (0xful << PWM_ADCTS0_TRGSEL2_Pos) |
| #define | PWM_ADCTS0_TRGEN2_Pos (23) |
| #define | PWM_ADCTS0_TRGEN2_Msk (0x1ul << PWM_ADCTS0_TRGEN2_Pos) |
| #define | PWM_ADCTS0_TRGSEL3_Pos (24) |
| #define | PWM_ADCTS0_TRGSEL3_Msk (0xful << PWM_ADCTS0_TRGSEL3_Pos) |
| #define | PWM_ADCTS0_TRGEN3_Pos (31) |
| #define | PWM_ADCTS0_TRGEN3_Msk (0x1ul << PWM_ADCTS0_TRGEN3_Pos) |
| #define | PWM_ADCTS1_TRGSEL4_Pos (0) |
| #define | PWM_ADCTS1_TRGSEL4_Msk (0xful << PWM_ADCTS1_TRGSEL4_Pos) |
| #define | PWM_ADCTS1_TRGEN4_Pos (7) |
| #define | PWM_ADCTS1_TRGEN4_Msk (0x1ul << PWM_ADCTS1_TRGEN4_Pos) |
| #define | PWM_ADCTS1_TRGSEL5_Pos (8) |
| #define | PWM_ADCTS1_TRGSEL5_Msk (0xful << PWM_ADCTS1_TRGSEL5_Pos) |
| #define | PWM_ADCTS1_TRGEN5_Pos (15) |
| #define | PWM_ADCTS1_TRGEN5_Msk (0x1ul << PWM_ADCTS1_TRGEN5_Pos) |
| #define | PWM_STATUS_CNTMAX0_Pos (0) |
| #define | PWM_STATUS_CNTMAX0_Msk (0x1ul << PWM_STATUS_CNTMAX0_Pos) |
| #define | PWM_STATUS_CNTMAX2_Pos (2) |
| #define | PWM_STATUS_CNTMAX2_Msk (0x1ul << PWM_STATUS_CNTMAX2_Pos) |
| #define | PWM_STATUS_CNTMAX4_Pos (4) |
| #define | PWM_STATUS_CNTMAX4_Msk (0x1ul << PWM_STATUS_CNTMAX4_Pos) |
| #define | PWM_STATUS_ADCTRGn_Pos (16) |
| #define | PWM_STATUS_ADCTRGn_Msk (0x3ful << PWM_STATUS_ADCTRGn_Pos) |
| #define | PWM_CAPINEN_CAPINENn_Pos (0) |
| #define | PWM_CAPINEN_CAPINENn_Msk (0x3ful << PWM_CAPINEN_CAPINENn_Pos) |
| #define | PWM_CAPCTL_CAPENn_Pos (0) |
| #define | PWM_CAPCTL_CAPENn_Msk (0x3ful << PWM_CAPCTL_CAPENn_Pos) |
| #define | PWM_CAPCTL_CAPINVn_Pos (8) |
| #define | PWM_CAPCTL_CAPINVn_Msk (0x3ful << PWM_CAPCTL_CAPINVn_Pos) |
| #define | PWM_CAPCTL_RCRLDENn_Pos (16) |
| #define | PWM_CAPCTL_RCRLDENn_Msk (0x3ful << PWM_CAPCTL_RCRLDENn_Pos) |
| #define | PWM_CAPCTL_FCRLDENn_Pos (24) |
| #define | PWM_CAPCTL_FCRLDENn_Msk (0x3ful << PWM_CAPCTL_FCRLDENn_Pos) |
| #define | PWM_CAPSTS_CRIFOVn_Pos (0) |
| #define | PWM_CAPSTS_CRIFOVn_Msk (0x3ful << PWM_CAPSTS_CRIFOVn_Pos) |
| #define | PWM_CAPSTS_CFIFOVn_Pos (8) |
| #define | PWM_CAPSTS_CFIFOVn_Msk (0x3ful << PWM_CAPSTS_CFIFOVn_Pos) |
| #define | PWM_RCAPDAT0_RCAPDAT_Pos (0) |
| #define | PWM_RCAPDAT0_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT0_RCAPDAT_Pos) |
| #define | PWM_FCAPDAT0_FCAPDAT_Pos (0) |
| #define | PWM_FCAPDAT0_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT0_FCAPDAT_Pos) |
| #define | PWM_RCAPDAT1_RCAPDAT_Pos (0) |
| #define | PWM_RCAPDAT1_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT1_RCAPDAT_Pos) |
| #define | PWM_FCAPDAT1_FCAPDAT_Pos (0) |
| #define | PWM_FCAPDAT1_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT1_FCAPDAT_Pos) |
| #define | PWM_RCAPDAT2_RCAPDAT_Pos (0) |
| #define | PWM_RCAPDAT2_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT2_RCAPDAT_Pos) |
| #define | PWM_FCAPDAT2_FCAPDAT_Pos (0) |
| #define | PWM_FCAPDAT2_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT2_FCAPDAT_Pos) |
| #define | PWM_RCAPDAT3_RCAPDAT_Pos (0) |
| #define | PWM_RCAPDAT3_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT3_RCAPDAT_Pos) |
| #define | PWM_FCAPDAT3_FCAPDAT_Pos (0) |
| #define | PWM_FCAPDAT3_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT3_FCAPDAT_Pos) |
| #define | PWM_RCAPDAT4_RCAPDAT_Pos (0) |
| #define | PWM_RCAPDAT4_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT4_RCAPDAT_Pos) |
| #define | PWM_FCAPDAT4_FCAPDAT_Pos (0) |
| #define | PWM_FCAPDAT4_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT4_FCAPDAT_Pos) |
| #define | PWM_RCAPDAT5_RCAPDAT_Pos (0) |
| #define | PWM_RCAPDAT5_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT5_RCAPDAT_Pos) |
| #define | PWM_FCAPDAT5_FCAPDAT_Pos (0) |
| #define | PWM_FCAPDAT5_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT5_FCAPDAT_Pos) |
| #define | PWM_CAPIEN_CAPRIENn_Pos (0) |
| #define | PWM_CAPIEN_CAPRIENn_Msk (0x3ful << PWM_CAPIEN_CAPRIENn_Pos) |
| #define | PWM_CAPIEN_CAPFIENn_Pos (8) |
| #define | PWM_CAPIEN_CAPFIENn_Msk (0x3ful << PWM_CAPIEN_CAPFIENn_Pos) |
| #define | PWM_CAPIF_CAPRIFn_Pos (0) |
| #define | PWM_CAPIF_CAPRIFn_Msk (0x3ful << PWM_CAPIF_CAPRIFn_Pos) |
| #define | PWM_CAPIF_CAPFIFn_Pos (8) |
| #define | PWM_CAPIF_CAPFIFn_Msk (0x3ful << PWM_CAPIF_CAPFIFn_Pos) |
| #define | PWM_PBUF0_PBUF_Pos (0) |
| #define | PWM_PBUF0_PBUF_Msk (0xfffful << PWM_PBUF0_PBUF_Pos) |
| #define | PWM_PBUF2_PBUF_Pos (0) |
| #define | PWM_PBUF2_PBUF_Msk (0xfffful << PWM_PBUF2_PBUF_Pos) |
| #define | PWM_PBUF4_PBUF_Pos (0) |
| #define | PWM_PBUF4_PBUF_Msk (0xfffful << PWM_PBUF4_PBUF_Pos) |
| #define | PWM_CMPBUF0_CMPBUF_Pos (0) |
| #define | PWM_CMPBUF0_CMPBUF_Msk (0xfffful << PWM_CMPBUF0_CMPBUF_Pos) |
| #define | PWM_CMPBUF1_CMPBUF_Pos (0) |
| #define | PWM_CMPBUF1_CMPBUF_Msk (0xfffful << PWM_CMPBUF1_CMPBUF_Pos) |
| #define | PWM_CMPBUF2_CMPBUF_Pos (0) |
| #define | PWM_CMPBUF2_CMPBUF_Msk (0xfffful << PWM_CMPBUF2_CMPBUF_Pos) |
| #define | PWM_CMPBUF3_CMPBUF_Pos (0) |
| #define | PWM_CMPBUF3_CMPBUF_Msk (0xfffful << PWM_CMPBUF3_CMPBUF_Pos) |
| #define | PWM_CMPBUF4_CMPBUF_Pos (0) |
| #define | PWM_CMPBUF4_CMPBUF_Msk (0xfffful << PWM_CMPBUF4_CMPBUF_Pos) |
| #define | PWM_CMPBUF5_CMPBUF_Pos (0) |
| #define | PWM_CMPBUF5_CMPBUF_Msk (0xfffful << PWM_CMPBUF5_CMPBUF_Pos) |
| #define | WDT_CTL_RSTCNT_Pos (0) |
| #define | WDT_CTL_RSTCNT_Msk (0x1ul << WDT_CTL_RSTCNT_Pos) |
| #define | WDT_CTL_RSTEN_Pos (1) |
| #define | WDT_CTL_RSTEN_Msk (0x1ul << WDT_CTL_RSTEN_Pos) |
| #define | WDT_CTL_WKEN_Pos (2) |
| #define | WDT_CTL_WKEN_Msk (0x1ul << WDT_CTL_WKEN_Pos) |
| #define | WDT_CTL_WDTEN_Pos (3) |
| #define | WDT_CTL_WDTEN_Msk (0x1ul << WDT_CTL_WDTEN_Pos) |
| #define | WDT_CTL_WTIS_Pos (4) |
| #define | WDT_CTL_WTIS_Msk (0x7ul << WDT_CTL_WTIS_Pos) |
| #define | WDT_CTL_WTRDSEL_Pos (8) |
| #define | WDT_CTL_WTRDSEL_Msk (0x3ul << WDT_CTL_WTRDSEL_Pos) |
| #define | WDT_CTL_DBGEN_Pos (31) |
| #define | WDT_CTL_DBGEN_Msk (0x1ul << WDT_CTL_DBGEN_Pos) |
| #define | WDT_INTEN_WDTIE_Pos (0) |
| #define | WDT_INTEN_WDTIE_Msk (0x1ul << WDT_INTEN_WDTIE_Pos) |
| #define | WDT_STATUS_WDTIF_Pos (0) |
| #define | WDT_STATUS_WDTIF_Msk (0x1ul << WDT_STATUS_WDTIF_Pos) |
| #define | WDT_STATUS_RSTF_Pos (1) |
| #define | WDT_STATUS_RSTF_Msk (0x1ul << WDT_STATUS_RSTF_Pos) |
| #define | WDT_STATUS_WKF_Pos (2) |
| #define | WDT_STATUS_WKF_Msk (0x1ul << WDT_STATUS_WKF_Pos) |
| #define | WWDT_RLDCNT_RLDCNT_Pos (0) |
| #define | WWDT_RLDCNT_RLDCNT_Msk (0xfffffffful << WWDT_RLDCNT_RLDCNT_Pos) |
| #define | WWDT_CTL_WWDTEN_Pos (0) |
| #define | WWDT_CTL_WWDTEN_Msk (0x1ul << WWDT_CTL_WWDTEN_Pos) |
| #define | WWDT_CTL_PERIODSEL_Pos (8) |
| #define | WWDT_CTL_PERIODSEL_Msk (0xful << WWDT_CTL_PERIODSEL_Pos) |
| #define | WWDT_CTL_WINCMP_Pos (16) |
| #define | WWDT_CTL_WINCMP_Msk (0x3ful << WWDT_CTL_WINCMP_Pos) |
| #define | WWDT_CTL_DBGEN_Pos (31) |
| #define | WWDT_CTL_DBGEN_Msk (0x1ul << WWDT_CTL_DBGEN_Pos) |
| #define | WWDT_INTEN_WWDTIE_Pos (0) |
| #define | WWDT_INTEN_WWDTIE_Msk (0x1ul << WWDT_INTEN_WWDTIE_Pos) |
| #define | WWDT_STATUS_WWDTIF_Pos (0) |
| #define | WWDT_STATUS_WWDTIF_Msk (0x1ul << WWDT_STATUS_WWDTIF_Pos) |
| #define | WWDT_STATUS_WWDTRF_Pos (1) |
| #define | WWDT_STATUS_WWDTRF_Msk (0x1ul << WWDT_STATUS_WWDTRF_Pos) |
| #define | WWDT_CNT_WWDT_CNTDAT_Pos (0) |
| #define | WWDT_CNT_WWDT_CNTDAT_Msk (0x3ful << WWDT_CNT_WWDT_CNTDAT_Pos) |
| #define | RTC_INIT_INIT_ACTIVE_Pos (0) |
| #define | RTC_INIT_INIT_ACTIVE_Msk (0x1ul << RTC_INIT_INIT_ACTIVE_Pos) |
| #define | RTC_INIT_INIT_Pos (1) |
| #define | RTC_INIT_INIT_Msk (0x7ffffffful << RTC_INIT_INIT_Pos) |
| #define | RTC_RWEN_RWEN_Pos (0) |
| #define | RTC_RWEN_RWEN_Msk (0xfffful << RTC_RWEN_RWEN_Pos) |
| #define | RTC_RWEN_RWENF_Pos (16) |
| #define | RTC_RWEN_RWENF_Msk (0x1ul << RTC_RWEN_RWENF_Pos) |
| #define | RTC_RWEN_RTCBUSY_Pos (24) |
| #define | RTC_RWEN_RTCBUSY_Msk (0x1ul << RTC_RWEN_RTCBUSY_Pos) |
| #define | RTC_FREQADJ_FREQADJ_Pos (0) |
| #define | RTC_FREQADJ_FREQADJ_Msk (0x3ffffful << RTC_FCR_FCR_Pos) |
| #define | RTC_TIME_SEC_Pos (0) |
| #define | RTC_TIME_SEC_Msk (0xful << RTC_TIME_SEC_Pos) |
| #define | RTC_TIME_TENSEC_Pos (4) |
| #define | RTC_TIME_TENSEC_Msk (0x7ul << RTC_TIME_TENSEC_Pos) |
| #define | RTC_TIME_MIN_Pos (8) |
| #define | RTC_TIME_MIN_Msk (0xful << RTC_TIME_MIN_Pos) |
| #define | RTC_TIME_TENMIN_Pos (12) |
| #define | RTC_TIME_TENMIN_Msk (0x7ul << RTC_TIME_TENMIN_Pos) |
| #define | RTC_TIME_HR_Pos (16) |
| #define | RTC_TIME_HR_Msk (0xful << RTC_TIME_HR_Pos) |
| #define | RTC_TIME_TENHR_Pos (20) |
| #define | RTC_TIME_TENHR_Msk (0x3ul << RTC_TIME_TENHR_Pos) |
| #define | RTC_CAL_DAY_Pos (0) |
| #define | RTC_CAL_DAY_Msk (0xful << RTC_CAL_DAY_Pos) |
| #define | RTC_CAL_TENDAY_Pos (4) |
| #define | RTC_CAL_TENDAY_Msk (0x3ul << RTC_CAL_TENDAY_Pos) |
| #define | RTC_CAL_MON_Pos (8) |
| #define | RTC_CAL_MON_Msk (0xful << RTC_CAL_MON_Pos) |
| #define | RTC_CAL_TENMON_Pos (12) |
| #define | RTC_CAL_TENMON_Msk (0x1ul << RTC_CAL_TENMON_Pos) |
| #define | RTC_CAL_YEAR_Pos (16) |
| #define | RTC_CAL_YEAR_Msk (0xful << RTC_CAL_YEAR_Pos) |
| #define | RTC_CAL_TENYEAR_Pos (20) |
| #define | RTC_CAL_TENYEAR_Msk (0xful << RTC_CAL_TENYEAR_Pos) |
| #define | RTC_CLKFMT_24HEN_Pos (0) |
| #define | RTC_CLKFMT_24HEN_Msk (0x1ul << RTC_CLKFMT_24HEN_Pos) |
| #define | RTC_WEEKDAY_WEEKDAY_Pos (0) |
| #define | RTC_WEEKDAY_WEEKDAY_Msk (0x7ul << RTC_WEEKDAY_WEEKDAY_Pos) |
| #define | RTC_TALM_SEC_Pos (0) |
| #define | RTC_TALM_SEC_Msk (0xful << RTC_TALM_SEC_Pos) |
| #define | RTC_TALM_TENSEC_Pos (4) |
| #define | RTC_TALM_TENSEC_Msk (0x7ul << RTC_TALM_TENSEC_Pos) |
| #define | RTC_TALM_MIN_Pos (8) |
| #define | RTC_TALM_MIN_Msk (0xful << RTC_TALM_MIN_Pos) |
| #define | RTC_TALM_TENMIN_Pos (12) |
| #define | RTC_TALM_TENMIN_Msk (0x7ul << RTC_TALM_TENMIN_Pos) |
| #define | RTC_TALM_HR_Pos (16) |
| #define | RTC_TALM_HR_Msk (0xful << RTC_TALM_HR_Pos) |
| #define | RTC_TALM_TENHR_Pos (20) |
| #define | RTC_TALM_TENHR_Msk (0x3ul << RTC_TALM_TENHR_Pos) |
| #define | RTC_CALM_DAY_Pos (0) |
| #define | RTC_CALM_DAY_Msk (0xful << RTC_CALM_DAY_Pos) |
| #define | RTC_CALM_TENDAY_Pos (4) |
| #define | RTC_CALM_TENDAY_Msk (0x3ul << RTC_CALM_TENDAY_Pos) |
| #define | RTC_CALM_MON_Pos (8) |
| #define | RTC_CALM_MON_Msk (0xful << RTC_CALM_MON_Pos) |
| #define | RTC_CALM_TENMON_Pos (12) |
| #define | RTC_CALM_TENMON_Msk (0x1ul << RTC_CALM_TENMON_Pos) |
| #define | RTC_CALM_YEAR_Pos (16) |
| #define | RTC_CALM_YEAR_Msk (0xful << RTC_CALM_YEAR_Pos) |
| #define | RTC_CALM_TENYEAR_Pos (20) |
| #define | RTC_CALM_TENYEAR_Msk (0xful << RTC_CALM_TENYEAR_Pos) |
| #define | RTC_LEAPYEAR_LEAPYEAR_Pos (0) |
| #define | RTC_LEAPYEAR_LEAPYEAR_Msk (0x1ul << RTC_LEAPYEAR_LEAPYEAR_Pos) |
| #define | RTC_INTEN_ALMIEN_Pos (0) |
| #define | RTC_INTEN_ALMIEN_Msk (0x1ul << RTC_INTEN_ALMIEN_Pos) |
| #define | RTC_INTEN_TICKIEN_Pos (1) |
| #define | RTC_INTEN_TICKIEN_Msk (0x1ul << RTC_INTEN_TICKIEN_Pos) |
| #define | RTC_INTEN_SNPDIEN_Pos (2) |
| #define | RTC_INTEN_SNPDIEN_Msk (0x1ul << RTC_INTEN_SNPDIEN_Pos) |
| #define | RTC_INTSTS_ALMIF_Pos (0) |
| #define | RTC_INTSTS_ALMIF_Msk (0x1ul << RTC_INTSTS_ALMIF_Pos) |
| #define | RTC_INTSTS_TICKIF_Pos (1) |
| #define | RTC_INTSTS_TICKIF_Msk (0x1ul << RTC_INTSTS_TICKIF_Pos) |
| #define | RTC_INTSTS_SNPDIF_Pos (2) |
| #define | RTC_INTSTS_SNPDIF_Msk (0x1ul << RTC_INTSTS_SNPDIF_Pos) |
| #define | RTC_TICK_TICK_Pos (0) |
| #define | RTC_TICK_TICK_Msk (0x7ul << RTC_TICK_TICK_Pos) |
| #define | RTC_TAMSK_MSEC_Pos (0) |
| #define | RTC_TAMSK_MSEC_Msk (0x1ul << RTC_TAMSK_MSEC_Pos) |
| #define | RTC_TAMSK_MTENSEC_Pos (1) |
| #define | RTC_TAMSK_MTENSEC_Msk (0x1ul << RTC_TAMSK_MTENSEC_Pos) |
| #define | RTC_TAMSK_MMIN_Pos (2) |
| #define | RTC_TAMSK_MMIN_Msk (0x1ul << RTC_TAMSK_MMIN_Pos) |
| #define | RTC_TAMSK_MTENMIN_Pos (3) |
| #define | RTC_TAMSK_MTENMIN_Msk (0x1ul << RTC_TAMSK_MTENMIN_Pos) |
| #define | RTC_TAMSK_MHR_Pos (4) |
| #define | RTC_TAMSK_MHR_Msk (0x1ul << RTC_TAMSK_MHR_Pos) |
| #define | RTC_TAMSK_MTENHR_Pos (5) |
| #define | RTC_TAMSK_MTENHR_Msk (0x1ul << RTC_TAMSK_MTENHR_Pos) |
| #define | RTC_CAMSK_MDAY_Pos (0) |
| #define | RTC_CAMSK_MDAY_Msk (0x1ul << RTC_CAMSK_MDAY_Pos) |
| #define | RTC_CAMSK_MTENDAY_Pos (1) |
| #define | RTC_CAMSK_MTENDAY_Msk (0x1ul << RTC_CAMSK_MTENDAY_Pos) |
| #define | RTC_CAMSK_MMON_Pos (2) |
| #define | RTC_CAMSK_MMON_Msk (0x1ul << RTC_CAMSK_MMON_Pos) |
| #define | RTC_CAMSK_MTENMON_Pos (3) |
| #define | RTC_CAMSK_MTENMON_Msk (0x1ul << RTC_CAMSK_MTENMON_Pos) |
| #define | RTC_CAMSK_MYEAR_Pos (4) |
| #define | RTC_CAMSK_MYEAR_Msk (0x1ul << RTC_CAMSK_MYEAR_Pos) |
| #define | RTC_CAMSK_MTENYEAR_Pos (5) |
| #define | RTC_CAMSK_MTENYEAR_Msk (0x1ul << RTC_CAMSK_MTENYEAR_Pos) |
| #define | RTC_SPRCTL_SNPDEN_Pos (0) |
| #define | RTC_SPRCTL_SNPDEN_Msk (0x1ul << RTC_SPRCTL_SNPDEN_Pos) |
| #define | RTC_SPRCTL_SNPTYPE0_Pos (1) |
| #define | RTC_SPRCTL_SNPTYPE0_Msk (0x1ul << RTC_SPRCTL_SNPTYPE0_Pos) |
| #define | RTC_SPRCTL_SPRRWEN_Pos (2) |
| #define | RTC_SPRCTL_SPRRWEN_Msk (0x1ul << RTC_SPRCTL_SPRRWEN_Pos) |
| #define | RTC_SPRCTL_SPRCSTS_Pos (5) |
| #define | RTC_SPRCTL_SPRCSTS_Msk (0x1ul << RTC_SPRCTL_SPRCSTS_Pos) |
| #define | RTC_SPR0_SPARE_Pos (0) |
| #define | RTC_SPR0_SPARE_Msk (0xfffffffful << RTC_SPR0_SPARE_Pos) |
| #define | RTC_SPR1_SPARE_Pos (0) |
| #define | RTC_SPR1_SPARE_Msk (0xfffffffful << RTC_SPR1_SPARE_Pos) |
| #define | RTC_SPR2_SPARE_Pos (0) |
| #define | RTC_SPR2_SPARE_Msk (0xfffffffful << RTC_SPR2_SPARE_Pos) |
| #define | RTC_SPR3_SPARE_Pos (0) |
| #define | RTC_SPR3_SPARE_Msk (0xfffffffful << RTC_SPR3_SPARE_Pos) |
| #define | RTC_SPR4_SPARE_Pos (0) |
| #define | RTC_SPR4_SPARE_Msk (0xfffffffful << RTC_SPR4_SPARE_Pos) |
| #define | RTC_LXTCTL_LXT_TYPE_Pos (0) |
| #define | RTC_LXTCTL_LXT_TYPE_Msk (0x1ul << RTC_LXTCTL_LXT_TYPE_Pos) |
| #define | RTC_LXTOCTL_OPMODE_Pos (0) |
| #define | RTC_LXTOCTL_OPMODE_Msk (0x3ul << RTC_LXTOCTL_OPMODE_Pos) |
| #define | RTC_LXTOCTL_DOUT_Pos (2) |
| #define | RTC_LXTOCTL_DOUT_Msk (0x1ul << RTC_LXTOCTL_DOUT_Pos) |
| #define | RTC_LXTOCTL_CTLSEL_Pos (3) |
| #define | RTC_LXTOCTL_CTLSEL_Msk (0x1ul << RTC_LXTOCTL_CTLSEL_Pos) |
| #define | RTC_LXTICTL_OPMODE_Pos (0) |
| #define | RTC_LXTICTL_OPMODE_Msk (0x3ul << RTC_LXTICTL_OPMODE_Pos) |
| #define | RTC_LXTICTL_DOUT_Pos (2) |
| #define | RTC_LXTICTL_DOUT_Msk (0x1ul << RTC_LXTICTL_DOUT_Pos) |
| #define | RTC_LXTICTL_CTLSEL_Pos (3) |
| #define | RTC_LXTICTL_CTLSEL_Msk (0x1ul << RTC_LXTICTL_CTLSEL_Pos) |
| #define | RTC_TAMPCTL_OPMODE_Pos (0) |
| #define | RTC_TAMPCTL_OPMODE_Msk (0x3ul << RTC_TAMPCTL_OPMODE_Pos) |
| #define | RTC_TAMPCTL_DOUT_Pos (2) |
| #define | RTC_TAMPCTL_DOUT_Msk (0x1ul << RTC_TAMPCTL_DOUT_Pos) |
| #define | RTC_TAMPCTL_CTLSEL_Pos (3) |
| #define | RTC_TAMPCTL_CTLSEL_Msk (0x1ul << RTC_TAMPCTL_CTLSEL_Pos) |
| #define | RTC_MISCCTL_GAINSEL_Pos (12) |
| #define | RTC_MISCCTL_GAINSEL_Msk (0x3ul << RTC_MISCCTL_GAINSEL_Pos) |
| #define | UART_DAT_DAT_Pos (0) |
| #define | UART_DAT_DAT_Msk (0xfful << UART_RBR_RBR_Pos) |
| #define | UART_CTRL_RXRST_Pos (0) |
| #define | UART_CTRL_RXRST_Msk (0x1ul << UART_CTRL_RXRST_Pos) |
| #define | UART_CTRL_TXRST_Pos (1) |
| #define | UART_CTRL_TXRST_Msk (0x1ul << UART_CTRL_TXRST_Pos) |
| #define | UART_CTRL_RXOFF_Pos (2) |
| #define | UART_CTRL_RXOFF_Msk (0x1ul << UART_CTRL_RXOFF_Pos) |
| #define | UART_CTRL_TXOFF_Pos (3) |
| #define | UART_CTRL_TXOFF_Msk (0x1ul << UART_CTRL_TXOFF_Pos) |
| #define | UART_CTRL_ATORTSEN_Pos (4) |
| #define | UART_CTRL_ATORTSEN_Msk (0x1ul << UART_CTRL_ATORTSEN_Pos) |
| #define | UART_CTRL_ATOCTSEN_Pos (5) |
| #define | UART_CTRL_ATOCTSEN_Msk (0x1ul << UART_CTRL_ATOCTSEN_Pos) |
| #define | UART_CTRL_RXDMAEN_Pos (6) |
| #define | UART_CTRL_RXDMAEN_Msk (0x1ul << UART_CTRL_RXDMAEN_Pos) |
| #define | UART_CTRL_TXDMAEN_Pos (7) |
| #define | UART_CTRL_TXDMAEN_Msk (0x1ul << UART_CTRL_TXDMAEN_Pos) |
| #define | UART_CTRL_FTOEN_Pos (8) |
| #define | UART_CTRL_FTOEN_Msk (0x1ul << UART_CTRL_FTOEN_Pos) |
| #define | UART_CTRL_ABRDEN_Pos (12) |
| #define | UART_CTRL_ABRDEN_Msk (0x1ul << UART_CTRL_ABRDEN_Pos) |
| #define | UART_CTRL_ABRDBITS_Pos (13) |
| #define | UART_CTRL_ABRDBITS_Msk (0x3ul << UART_CTRL_ABRDBITS_Pos) |
| #define | UART_LINE_WLS_Pos (0) |
| #define | UART_LINE_WLS_Msk (0x3ul << UART_LINE_WLS_Pos) |
| #define | UART_LINE_NSB_Pos (2) |
| #define | UART_LINE_NSB_Msk (0x1ul << UART_LINE_NSB_Pos) |
| #define | UART_LINE_PBE_Pos (3) |
| #define | UART_LINE_PBE_Msk (0x1ul << UART_LINE_PBE_Pos) |
| #define | UART_LINE_EPE_Pos (4) |
| #define | UART_LINE_EPE_Msk (0x1ul << UART_LINE_EPE_Pos) |
| #define | UART_LINE_SPE_Pos (5) |
| #define | UART_LINE_SPE_Msk (0x1ul << UART_LINE_SPE_Pos) |
| #define | UART_LINE_BCB_Pos (6) |
| #define | UART_LINE_BCB_Msk (0x1ul << UART_LINE_BCB_Pos) |
| #define | UART_LINE_RFITL_Pos (8) |
| #define | UART_LINE_RFITL_Msk (0x3ul << UART_LINE_RFITL_Pos) |
| #define | UART_LINE_RTSTRGLV_Pos (12) |
| #define | UART_LINE_RTSTRGLV_Msk (0x3ul << UART_LINE_RTSTRGLV_Pos) |
| #define | UART_INTEN_RDAIEN_Pos (0) |
| #define | UART_INTEN_RDAIEN_Msk (0x1ul << UART_INTEN_RDAIEN_Pos) |
| #define | UART_INTEN_THREIEN_Pos (1) |
| #define | UART_INTEN_THREIEN_Msk (0x1ul << UART_INTEN_THREIEN_Pos) |
| #define | UART_INTEN_RLSIEN_Pos (2) |
| #define | UART_INTEN_RLSIEN_Msk (0x1ul << UART_INTEN_RLSIEN_Pos) |
| #define | UART_INTEN_MODEMIEN_Pos (3) |
| #define | UART_INTEN_MODEMIEN_Msk (0x1ul << UART_INTEN_MODEMIEN_Pos) |
| #define | UART_INTEN_RXTOIEN_Pos (4) |
| #define | UART_INTEN_RXTOIEN_Msk (0x1ul << UART_INTEN_RXTOIEN_Pos) |
| #define | UART_INTEN_BUFERRIEN_Pos (5) |
| #define | UART_INTEN_BUFERRIEN_Msk (0x1ul << UART_INTEN_BUFERRIEN_Pos) |
| #define | UART_INTEN_WKUPIEN_Pos (6) |
| #define | UART_INTEN_WKUPIEN_Msk (0x1ul << UART_INTEN_WKUPIEN_Pos) |
| #define | UART_INTEN_ABRIEN_Pos (7) |
| #define | UART_INTEN_ABRIEN_Msk (0x1ul << UART_INTEN_ABRIEN_Pos) |
| #define | UART_INTEN_LINIEN_Pos (8) |
| #define | UART_INTEN_LINIEN_Msk (0x1ul << UART_INTEN_LINIEN_Pos) |
| #define | UART_INTEN_TXENDIEN_Pos (9) |
| #define | UART_INTEN_TXENDIEN_Msk (0x1ul << UART_INTEN_TXENDIEN_Pos) |
| #define | UART_INTSTS_RDAIF_Pos (0) |
| #define | UART_INTSTS_RDAIF_Msk (0x1ul << UART_INTSTS_RDAIF_Pos) |
| #define | UART_INTSTS_THREIF_Pos (1) |
| #define | UART_INTSTS_THREIF_Msk (0x1ul << UART_INTSTS_THREIF_Pos) |
| #define | UART_INTSTS_RLSIF_Pos (2) |
| #define | UART_INTSTS_RLSIF_Msk (0x1ul << UART_INTSTS_RLSIF_Pos) |
| #define | UART_INTSTS_MODEMIF_Pos (3) |
| #define | UART_INTSTS_MODEMIF_Msk (0x1ul << UART_INTSTS_MODEMIF_Pos) |
| #define | UART_INTSTS_RXTOIF_Pos (4) |
| #define | UART_INTSTS_RXTOIF_Msk (0x1ul << UART_INTSTS_RXTOIF_Pos) |
| #define | UART_INTSTS_BUFERRIF_Pos (5) |
| #define | UART_INTSTS_BUFERRIF_Msk (0x1ul << UART_INTSTS_BUFERRIF_Pos) |
| #define | UART_INTSTS_WKUPIF_Pos (6) |
| #define | UART_INTSTS_WKUPIF_Msk (0x1ul << UART_INTSTS_WKUPIF_Pos) |
| #define | UART_INTSTS_ABRIF_Pos (7) |
| #define | UART_INTSTS_ABRIF_Msk (0x1ul << UART_INTSTS_ABRIF_Pos) |
| #define | UART_INTSTS_LINIF_Pos (8) |
| #define | UART_INTSTS_LINIF_Msk (0x1ul << UART_INTSTS_LINIF_Pos) |
| #define | UART_TRSR_ADDRDETF_Pos (0) |
| #define | UART_TRSR_ADDRDETF_Msk (0x1ul << UART_TRSR_ADDRDETF_Pos) |
| #define | UART_TRSR_ABRDIF_Pos (1) |
| #define | UART_TRSR_ABRDIF_Msk (0x1ul << UART_TRSR_ABRDIF_Pos) |
| #define | UART_TRSR_ABRDTOIF_Pos (2) |
| #define | UART_TRSR_ABRDTOIF_Msk (0x1ul << UART_TRSR_ABRDTOIF_Pos) |
| #define | UART_TRSR_LINTXIF_Pos (3) |
| #define | UART_TRSR_LINTXIF_Msk (0x1ul << UART_TRSR_LINTXIF_Pos) |
| #define | UART_TRSR_LINRXIF_Pos (4) |
| #define | UART_TRSR_LINRXIF_Msk (0x1ul << UART_TRSR_LINRXIF_Pos) |
| #define | UART_TRSR_BITEF_Pos (5) |
| #define | UART_TRSR_BITEF_Msk (0x1ul << UART_TRSR_BITEF_Pos) |
| #define | UART_TRSR_RXBUSY_Pos (7) |
| #define | UART_TRSR_RXBUSY_Msk (0x1ul << UART_TRSR_RXBUSY_Pos) |
| #define | UART_TRSR_SLVSYNCF_Pos (8) |
| #define | UART_TRSR_SLVSYNCF_Msk (0x1ul << UART_TRSR_SLVSYNCF_Pos) |
| #define | UART_FIFOSTS_RXOVIF_Pos (0) |
| #define | UART_FIFOSTS_RXOVIF_Msk (0x1ul << UART_FIFOSTS_RXOVIF_Pos) |
| #define | UART_FIFOSTS_RXEMPTY_Pos (1) |
| #define | UART_FIFOSTS_RXEMPTY_Msk (0x1ul << UART_FIFOSTS_RXEMPTY_Pos) |
| #define | UART_FIFOSTS_RXFULL_Pos (2) |
| #define | UART_FIFOSTS_RXFULL_Msk (0x1ul << UART_FIFOSTS_RXFULL_Pos) |
| #define | UART_FIFOSTS_PEF_Pos (4) |
| #define | UART_FIFOSTS_PEF_Msk (0x1ul << UART_FIFOSTS_PEF_Pos) |
| #define | UART_FIFOSTS_FEF_Pos (5) |
| #define | UART_FIFOSTS_FEF_Msk (0x1ul << UART_FIFOSTS_FEF_Pos) |
| #define | UART_FIFOSTS_BIF_Pos (6) |
| #define | UART_FIFOSTS_BIF_Msk (0x1ul << UART_FIFOSTS_BIF_Pos) |
| #define | UART_FIFOSTS_TXOVIF_Pos (8) |
| #define | UART_FIFOSTS_TXOVIF_Msk (0x1ul << UART_FIFOSTS_TXOVIF_Pos) |
| #define | UART_FIFOSTS_TXEMPTY_Pos (9) |
| #define | UART_FIFOSTS_TXEMPTY_Msk (0x1ul << UART_FIFOSTS_TXEMPTY_Pos) |
| #define | UART_FIFOSTS_TXFULL_Pos (10) |
| #define | UART_FIFOSTS_TXFULL_Msk (0x1ul << UART_FIFOSTS_TXFULL_Pos) |
| #define | UART_FIFOSTS_TXENDF_Pos (11) |
| #define | UART_FIFOSTS_TXENDF_Msk (0x1ul << UART_FIFOSTS_TXENDF_Pos) |
| #define | UART_FIFOSTS_RXPTR_Pos (16) |
| #define | UART_FIFOSTS_RXPTR_Msk (0x1ful << UART_FIFOSTS_RXPTR_Pos) |
| #define | UART_FIFOSTS_TXPTR_Pos (24) |
| #define | UART_FIFOSTS_TXPTR_Msk (0x1ful << UART_FIFOSTS_TXPTR_Pos) |
| #define | UART_MODEM_RTSACTLV_Pos (0) |
| #define | UART_MODEM_RTSACTLV_Msk (0x1ul << UART_MODEM_RTSACTLV_Pos) |
| #define | UART_MODEM_RTSSTS_Pos (1) |
| #define | UART_MODEM_RTSSTS_Msk (0x1ul << UART_MODEM_RTSSTS_Pos) |
| #define | UART_MODEM_CTSACTLV_Pos (16) |
| #define | UART_MODEM_CTSACTLV_Msk (0x1ul << UART_MODEM_CTSACTLV_Pos) |
| #define | UART_MODEM_CTSSTS_Pos (17) |
| #define | UART_MODEM_CTSSTS_Msk (0x1ul << UART_MODEM_CTSSTS_Pos) |
| #define | UART_MODEM_CTSDETF_Pos (18) |
| #define | UART_MODEM_CTSDETF_Msk (0x1ul << UART_MODEM_CTSDETF_Pos) |
| #define | UART_TOUT_TOIC_Pos (0) |
| #define | UART_TOUT_TOIC_Msk (0x1fful << UART_TOUT_TOIC_Pos) |
| #define | UART_TOUT_DLY_Pos (16) |
| #define | UART_TOUT_DLY_Msk (0xfful << UART_TOUT_DLY_Pos) |
| #define | UART_BAUD_BRD_Pos (0) |
| #define | UART_BAUD_BRD_Msk (0xfffful << UART_BAUD_BRD_Pos) |
| #define | UART_BAUD_DIV16EN_Pos (31) |
| #define | UART_BAUD_DIV16EN_Msk (0x1ul << UART_BAUD_DIV16EN_Pos) |
| #define | UART_IRDA_TXEN_Pos (1) |
| #define | UART_IRDA_TXEN_Msk (0x1ul << UART_IRDA_TXEN_Pos) |
| #define | UART_IRDA_TXINV_Pos (5) |
| #define | UART_IRDA_TXINV_Msk (0x1ul << UART_IRDA_TXINV_Pos) |
| #define | UART_IRDA_RXINV_Pos (6) |
| #define | UART_IRDA_RXINV_Msk (0x1ul << UART_IRDA_RXINV_Pos) |
| #define | UART_ALTCTL_BRKFL_Pos (0) |
| #define | UART_ALTCTL_BRKFL_Msk (0x7ul << UART_ALTCTL_BRKFL_Pos) |
| #define | UART_ALTCTL_LINHSEL_Pos (4) |
| #define | UART_ALTCTL_LINHSEL_Msk (0x3ul << UART_ALTCTL_LINHSEL_Pos) |
| #define | UART_ALTCTL_LINRXEN_Pos (6) |
| #define | UART_ALTCTL_LINRXEN_Msk (0x1ul << UART_ALTCTL_LINRXEN_Pos) |
| #define | UART_ALTCTL_LINTXEN_Pos (7) |
| #define | UART_ALTCTL_LINTXEN_Msk (0x1ul << UART_ALTCTL_LINTXEN_Pos) |
| #define | UART_ALTCTL_BITERREN_Pos (8) |
| #define | UART_ALTCTL_BITERREN_Msk (0x1ul << UART_ALTCTL_BITERREN_Pos) |
| #define | UART_ALTCTL_RS485NMM_Pos (16) |
| #define | UART_ALTCTL_RS485NMM_Msk (0x1ul << UART_ALTCTL_RS485NMM_Pos) |
| #define | UART_ALTCTL_RS485AAD_Pos (17) |
| #define | UART_ALTCTL_RS485AAD_Msk (0x1ul << UART_ALTCTL_RS485AAD_Pos) |
| #define | UART_ALTCTL_RS485AUD_Pos (18) |
| #define | UART_ALTCTL_RS485AUD_Msk (0x1ul << UART_ALTCTL_RS485AUD_Pos) |
| #define | UART_ALTCTL_ADDRDEN_Pos (19) |
| #define | UART_ALTCTL_ADDRDEN_Msk (0x1ul << UART_ALTCTL_ADDRDEN_Pos) |
| #define | UART_ALTCTL_ADRMPID_Pos (24) |
| #define | UART_ALTCTL_ADRMPID_Msk (0xfful << UART_ALTCTL_ADRMPID_Pos) |
| #define | UART_FUNCSEL_FUNCSEL_Pos (0) |
| #define | UART_FUNCSEL_FUNCSEL_Msk (0x3ul << UART_FUNCSEL_FUNCSEL_Pos) |
| #define | UART_BRCOMPAT_BRCOMPAT_Pos (0) |
| #define | UART_BRCOMPAT_BRCOMPAT_Msk (0x1fful << UART_BRCOMPAT_BRCOMPAT_Pos) |
| #define | UART_BRCOMPAT_BRCOMPDEC_Pos (31) |
| #define | UART_BRCOMPAT_BRCOMPDEC_Msk (0x1ul << UART_BRCOMPAT_BRCOMPDEC_Pos) |
| #define | UART_WKUPEN_WKCTSEN_Pos (0) |
| #define | UART_WKUPEN_WKCTSEN_Msk (0x1ul << UART_WKUPEN_WKCTSEN_Pos) |
| #define | UART_WKUPEN_WKDATEN_Pos (1) |
| #define | UART_WKUPEN_WKDATEN_Msk (0x1ul << UART_WKUPEN_WKDATEN_Pos) |
| #define | UART_WKUPEN_WKTHREN_Pos (2) |
| #define | UART_WKUPEN_WKTHREN_Msk (0x1ul << UART_WKUPEN_WKTHREN_Pos) |
| #define | UART_WKUPEN_WKTHRTOEN_Pos (3) |
| #define | UART_WKUPEN_WKTHRTOEN_Msk (0x1ul << UART_WKUPEN_WKTHRTOEN_Pos) |
| #define | UART_WKUPEN_WKADRMEN_Pos (4) |
| #define | UART_WKUPEN_WKADRMEN_Msk (0x1ul << UART_WKUPEN_WKADRMEN_Pos) |
| #define | UART_WKUPSTS_CTSWKSTS_Pos (0) |
| #define | UART_WKUPSTS_CTSWKSTS_Msk (0x1ul << UART_WKUPSTS_CTSWKSTS_Pos) |
| #define | UART_WKUPSTS_DATWKSTS_Pos (1) |
| #define | UART_WKUPSTS_DATWKSTS_Msk (0x1ul << UART_WKUPSTS_DATWKSTS_Pos) |
| #define | UART_WKUPSTS_THRWKSTS_Pos (2) |
| #define | UART_WKUPSTS_THRWKSTS_Msk (0x1ul << UART_WKUPSTS_THRWKSTS_Pos) |
| #define | UART_WKUPSTS_THRTOWKSTS_Pos (3) |
| #define | UART_WKUPSTS_THRTOWKSTS_Msk (0x1ul << UART_WKUPSTS_THRTOWKSTS_Pos) |
| #define | UART_WKUPSTS_ADRWKSTS_Pos (4) |
| #define | UART_WKUPSTS_ADRWKSTS_Msk (0x1ul << UART_WKUPSTS_ADRWKSTS_Pos) |
| #define | SC_DAT_DAT_Pos (0) |
| #define | SC_DAT_DAT_Msk (0xfful << SC_DAT_DAT_Pos) |
| #define | SC_CTL_SCEN_Pos (0) |
| #define | SC_CTL_SCEN_Msk (0x1ul << SC_CTL_SCEN_Pos) |
| #define | SC_CTL_RXOFF_Pos (1) |
| #define | SC_CTL_RXOFF_Msk (0x1ul << SC_CTL_RXOFF_Pos) |
| #define | SC_CTL_TXOFF_Pos (2) |
| #define | SC_CTL_TXOFF_Msk (0x1ul << SC_CTL_TXOFF_Pos) |
| #define | SC_CTL_AUTOCEN_Pos (3) |
| #define | SC_CTL_AUTOCEN_Msk (0x1ul << SC_CTL_AUTOCEN_Pos) |
| #define | SC_CTL_CONSEL_Pos (4) |
| #define | SC_CTL_CONSEL_Msk (0x3ul << SC_CTL_CONSEL_Pos) |
| #define | SC_CTL_RXTRGLV_Pos (6) |
| #define | SC_CTL_RXTRGLV_Msk (0x3ul << SC_CTL_RXTRGLV_Pos) |
| #define | SC_CTL_BGT_Pos (8) |
| #define | SC_CTL_BGT_Msk (0x1ful << SC_CTL_BGT_Pos) |
| #define | SC_CTL_TMRSEL_Pos (13) |
| #define | SC_CTL_TMRSEL_Msk (0x3ul << SC_CTL_TMRSEL_Pos) |
| #define | SC_CTL_NSB_Pos (15) |
| #define | SC_CTL_NSB_Msk (0x1ul << SC_CTL_NSB_Pos) |
| #define | SC_CTL_RXRTY_Pos (16) |
| #define | SC_CTL_RXRTY_Msk (0x7ul << SC_CTL_RXRTY_Pos) |
| #define | SC_CTL_RXRTYEN_Pos (19) |
| #define | SC_CTL_RXRTYEN_Msk (0x1ul << SC_CTL_RXRTYEN_Pos) |
| #define | SC_CTL_TXRTY_Pos (20) |
| #define | SC_CTL_TXRTY_Msk (0x7ul << SC_CTL_TXRTY_Pos) |
| #define | SC_CTL_TXRTYEN_Pos (23) |
| #define | SC_CTL_TXRTYEN_Msk (0x1ul << SC_CTL_TXRTYEN_Pos) |
| #define | SC_CTL_CDDBSEL_Pos (24) |
| #define | SC_CTL_CDDBSEL_Msk (0x3ul << SC_CTL_CDDBSEL_Pos) |
| #define | SC_CTL_SYNC_Pos (30) |
| #define | SC_CTL_SYNC_Msk (0x1ul << SC_CTL_SYNC_Pos) |
| #define | SC_ALTCTL_TXRST_Pos (0) |
| #define | SC_ALTCTL_TXRST_Msk (0x1ul << SC_ALTCTL_TXRST_Pos) |
| #define | SC_ALTCTL_RXRST_Pos (1) |
| #define | SC_ALTCTL_RXRST_Msk (0x1ul << SC_ALTCTL_RXRST_Pos) |
| #define | SC_ALTCTL_DACTEN_Pos (2) |
| #define | SC_ALTCTL_DACTEN_Msk (0x1ul << SC_ALTCTL_DACTEN_Pos) |
| #define | SC_ALTCTL_ACTEN_Pos (3) |
| #define | SC_ALTCTL_ACTEN_Msk (0x1ul << SC_ALTCTL_ACTEN_Pos) |
| #define | SC_ALTCTL_WARSTEN_Pos (4) |
| #define | SC_ALTCTL_WARSTEN_Msk (0x1ul << SC_ALTCTL_WARSTEN_Pos) |
| #define | SC_ALTCTL_CNTEN0_Pos (5) |
| #define | SC_ALTCTL_CNTEN0_Msk (0x1ul << SC_ALTCTL_CNTEN0_Pos) |
| #define | SC_ALTCTL_CNTEN1_Pos (6) |
| #define | SC_ALTCTL_CNTEN1_Msk (0x1ul << SC_ALTCTL_CNTEN1_Pos) |
| #define | SC_ALTCTL_CNTEN2_Pos (7) |
| #define | SC_ALTCTL_CNTEN2_Msk (0x1ul << SC_ALTCTL_CNTEN2_Pos) |
| #define | SC_ALTCTL_INITSEL_Pos (8) |
| #define | SC_ALTCTL_INITSEL_Msk (0x3ul << SC_ALTCTL_INITSEL_Pos) |
| #define | SC_ALTCTL_RXBGTEN_Pos (12) |
| #define | SC_ALTCTL_RXBGTEN_Msk (0x1ul << SC_ALTCTL_RXBGTEN_Pos) |
| #define | SC_ALTCTL_ACTSTS0_Pos (13) |
| #define | SC_ALTCTL_ACTSTS0_Msk (0x1ul << SC_ALTCTL_ACTSTS0_Pos) |
| #define | SC_ALTCTL_ACTSTS1_Pos (14) |
| #define | SC_ALTCTL_ACTSTS1_Msk (0x1ul << SC_ALTCTL_ACTSTS1_Pos) |
| #define | SC_ALTCTL_ACTSTS2_Pos (15) |
| #define | SC_ALTCTL_ACTSTS2_Msk (0x1ul << SC_ALTCTL_ACTSTS2_Pos) |
| #define | SC_ALTCTL_OUTSEL_Pos (16) |
| #define | SC_ALTCTL_OUTSEL_Msk (0x1ul << SC_ALTCTL_OUTSEL_Pos) |
| #define | SC_EGT_EGT_Pos (0) |
| #define | SC_EGT_EGT_Msk (0xfful << SC_EGT_EGT_Pos) |
| #define | SC_RXTOUT_RFTM_Pos (0) |
| #define | SC_RXTOUT_RFTM_Msk (0x1fful << SC_RXTOUT_RFTM_Pos) |
| #define | SC_ETUCTL_ETURDIV_Pos (0) |
| #define | SC_ETUCTL_ETURDIV_Msk (0xffful << SC_ETUCTL_ETURDIV_Pos) |
| #define | SC_INTEN_RDAIEN_Pos (0) |
| #define | SC_INTEN_RDAIEN_Msk (0x1ul << SC_INTEN_RDAIEN_Pos) |
| #define | SC_INTEN_TBEIEN_Pos (1) |
| #define | SC_INTEN_TBEIEN_Msk (0x1ul << SC_INTEN_TBEIEN_Pos) |
| #define | SC_INTEN_TERRIEN_Pos (2) |
| #define | SC_INTEN_TERRIEN_Msk (0x1ul << SC_INTEN_TERRIEN_Pos) |
| #define | SC_INTEN_TMR0IEN_Pos (3) |
| #define | SC_INTEN_TMR0IEN_Msk (0x1ul << SC_INTEN_TMR0IEN_Pos) |
| #define | SC_INTEN_TMR1IEN_Pos (4) |
| #define | SC_INTEN_TMR1IEN_Msk (0x1ul << SC_INTEN_TMR1IEN_Pos) |
| #define | SC_INTEN_TMR2IEN_Pos (5) |
| #define | SC_INTEN_TMR2IEN_Msk (0x1ul << SC_INTEN_TMR2IEN_Pos) |
| #define | SC_INTEN_BGTIEN_Pos (6) |
| #define | SC_INTEN_BGTIEN_Msk (0x1ul << SC_INTEN_BGTIEN_Pos) |
| #define | SC_INTEN_CDIEN_Pos (7) |
| #define | SC_INTEN_CDIEN_Msk (0x1ul << SC_INTEN_CDIEN_Pos) |
| #define | SC_INTEN_INITIEN_Pos (8) |
| #define | SC_INTEN_INITIEN_Msk (0x1ul << SC_INTEN_INITIEN_Pos) |
| #define | SC_INTEN_RXTOIEN_Pos (9) |
| #define | SC_INTEN_RXTOIEN_Msk (0x1ul << SC_INTEN_RXTOIEN_Pos) |
| #define | SC_INTEN_ACERRIEN_Pos (10) |
| #define | SC_INTEN_ACERRIEN_Msk (0x1ul << SC_INTEN_ACERRIEN_Pos) |
| #define | SC_INTSTS_RDAIF_Pos (0) |
| #define | SC_INTSTS_RDAIF_Msk (0x1ul << SC_INTSTS_RDAIF_Pos) |
| #define | SC_INTSTS_TBEIF_Pos (1) |
| #define | SC_INTSTS_TBEIF_Msk (0x1ul << SC_INTSTS_TBEIF_Pos) |
| #define | SC_INTSTS_TERRIF_Pos (2) |
| #define | SC_INTSTS_TERRIF_Msk (0x1ul << SC_INTSTS_TERRIF_Pos) |
| #define | SC_INTSTS_TMR0IF_Pos (3) |
| #define | SC_INTSTS_TMR0IF_Msk (0x1ul << SC_INTSTS_TMR0IF_Pos) |
| #define | SC_INTSTS_TMR1IF_Pos (4) |
| #define | SC_INTSTS_TMR1IF_Msk (0x1ul << SC_INTSTS_TMR1IF_Pos) |
| #define | SC_INTSTS_TMR2IF_Pos (5) |
| #define | SC_INTSTS_TMR2IF_Msk (0x1ul << SC_INTSTS_TMR2IF_Pos) |
| #define | SC_INTSTS_BGTIF_Pos (6) |
| #define | SC_INTSTS_BGTIF_Msk (0x1ul << SC_INTSTS_BGTIF_Pos) |
| #define | SC_INTSTS_CDIF_Pos (7) |
| #define | SC_INTSTS_CDIF_Msk (0x1ul << SC_INTSTS_CDIF_Pos) |
| #define | SC_INTSTS_INITIF_Pos (8) |
| #define | SC_INTSTS_INITIF_Msk (0x1ul << SC_INTSTS_INITIF_Pos) |
| #define | SC_INTSTS_RXTOIF_Pos (9) |
| #define | SC_INTSTS_RXTOIF_Msk (0x1ul << SC_INTSTS_RXTOIF_Pos) |
| #define | SC_INTSTS_ACERRIF_Pos (10) |
| #define | SC_INTSTS_ACERRIF_Msk (0x1ul << SC_INTSTS_ACERRIF_Pos) |
| #define | SC_STATUS_RXOV_Pos (0) |
| #define | SC_STATUS_RXOV_Msk (0x1ul << SC_STATUS_RXOV_Pos) |
| #define | SC_STATUS_RXEMPTY_Pos (1) |
| #define | SC_STATUS_RXEMPTY_Msk (0x1ul << SC_STATUS_RXEMPTY_Pos) |
| #define | SC_STATUS_RXFULL_Pos (2) |
| #define | SC_STATUS_RXFULL_Msk (0x1ul << SC_STATUS_RXFULL_Pos) |
| #define | SC_STATUS_PEF_Pos (4) |
| #define | SC_STATUS_PEF_Msk (0x1ul << SC_STATUS_PEF_Pos) |
| #define | SC_STATUS_FEF_Pos (5) |
| #define | SC_STATUS_FEF_Msk (0x1ul << SC_STATUS_FEF_Pos) |
| #define | SC_STATUS_BEF_Pos (6) |
| #define | SC_STATUS_BEF_Msk (0x1ul << SC_STATUS_BEF_Pos) |
| #define | SC_STATUS_TXOV_Pos (8) |
| #define | SC_STATUS_TXOV_Msk (0x1ul << SC_STATUS_TXOV_Pos) |
| #define | SC_STATUS_TXEMPTY_Pos (9) |
| #define | SC_STATUS_TXEMPTY_Msk (0x1ul << SC_STATUS_TXEMPTY_Pos) |
| #define | SC_STATUS_TXFULL_Pos (10) |
| #define | SC_STATUS_TXFULL_Msk (0x1ul << SC_STATUS_TXFULL_Pos) |
| #define | SC_STATUS_RXPOINT_Pos (16) |
| #define | SC_STATUS_RXPOINT_Msk (0x3ul << SC_STATUS_RXPOINT_Pos) |
| #define | SC_STATUS_RXRERR_Pos (21) |
| #define | SC_STATUS_RXRERR_Msk (0x1ul << SC_STATUS_RXRERR_Pos) |
| #define | SC_STATUS_RXOVERR_Pos (22) |
| #define | SC_STATUS_RXOVERR_Msk (0x1ul << SC_STATUS_RXOVERR_Pos) |
| #define | SC_STATUS_RXACT_Pos (23) |
| #define | SC_STATUS_RXACT_Msk (0x1ul << SC_STATUS_RXACT_Pos) |
| #define | SC_STATUS_TXPOINT_Pos (24) |
| #define | SC_STATUS_TXPOINT_Msk (0x3ul << SC_STATUS_TXPOINT_Pos) |
| #define | SC_STATUS_TXRERR_Pos (29) |
| #define | SC_STATUS_TXRERR_Msk (0x1ul << SC_STATUS_TXRERR_Pos) |
| #define | SC_STATUS_TXOVERR_Pos (30) |
| #define | SC_STATUS_TXOVERR_Msk (0x1ul << SC_STATUS_TXOVERR_Pos) |
| #define | SC_STATUS_TXACT_Pos (31) |
| #define | SC_STATUS_TXACT_Msk (0x1ul << SC_STATUS_TXACT_Pos) |
| #define | SC_PINCTL_PWREN_Pos (0) |
| #define | SC_PINCTL_PWREN_Msk (0x1ul << SC_PINCTL_PWREN_Pos) |
| #define | SC_PINCTL_SCRST_Pos (1) |
| #define | SC_PINCTL_SCRST_Msk (0x1ul << SC_PINCTL_SCRST_Pos) |
| #define | SC_PINCTL_CREMOVE_Pos (2) |
| #define | SC_PINCTL_CREMOVE_Msk (0x1ul << SC_PINCTL_CREMOVE_Pos) |
| #define | SC_PINCTL_CINSERT_Pos (3) |
| #define | SC_PINCTL_CINSERT_Msk (0x1ul << SC_PINCTL_CINSERT_Pos) |
| #define | SC_PINCTL_CDPINSTS_Pos (4) |
| #define | SC_PINCTL_CDPINSTS_Msk (0x1ul << SC_PINCTL_CDPINSTS_Pos) |
| #define | SC_PINCTL_CLKKEEP_Pos (6) |
| #define | SC_PINCTL_CLKKEEP_Msk (0x1ul << SC_PINCTL_CLKKEEP_Pos) |
| #define | SC_PINCTL_ADACEN_Pos (7) |
| #define | SC_PINCTL_ADACEN_Msk (0x1ul << SC_PINCTL_ADACEN_Pos) |
| #define | SC_PINCTL_SCDOUT_Pos (9) |
| #define | SC_PINCTL_SCDOUT_Msk (0x1ul << SC_PINCTL_SCDOUT_Pos) |
| #define | SC_PINCTL_CDLV_Pos (10) |
| #define | SC_PINCTL_CDLV_Msk (0x1ul << SC_PINCTL_CDLV_Pos) |
| #define | SC_PINCTL_PWRINV_Pos (11) |
| #define | SC_PINCTL_PWRINV_Msk (0x1ul << SC_PINCTL_PWRINV_Pos) |
| #define | SC_PINCTL_DATSTS_Pos (16) |
| #define | SC_PINCTL_DATSTS_Msk (0x1ul << SC_PINCTL_DATSTS_Pos) |
| #define | SC_PINCTL_SYNC_Pos (30) |
| #define | SC_PINCTL_SYNC_Msk (0x1ul << SC_PINCTL_SYNC_Pos) |
| #define | SC_TMRCTL0_CNT_Pos (0) |
| #define | SC_TMRCTL0_CNT_Msk (0xfffffful << SC_TMRCTL0_CNT_Pos) |
| #define | SC_TMRCTL0_OPMODE_Pos (24) |
| #define | SC_TMRCTL0_OPMODE_Msk (0xful << SC_TMRCTL0_OPMODE_Pos) |
| #define | SC_TMRCTL0_SYNC_Pos (31) |
| #define | SC_TMRCTL0_SYNC_Msk (0x1ul << SC_TMRCTL0_SYNC_Pos) |
| #define | SC_TMRCTL1_CNT_Pos (0) |
| #define | SC_TMRCTL1_CNT_Msk (0xfful << SC_TMRCTL1_CNT_Pos) |
| #define | SC_TMRCTL1_OPMODE_Pos (24) |
| #define | SC_TMRCTL1_OPMODE_Msk (0xful << SC_TMRCTL1_OPMODE_Pos) |
| #define | SC_TMRCTL1_SYNC_Pos (31) |
| #define | SC_TMRCTL1_SYNC_Msk (0x1ul << SC_TMRCTL1_SYNC_Pos) |
| #define | SC_TMRCTL2_CNT_Pos (0) |
| #define | SC_TMRCTL2_CNT_Msk (0xfful << SC_TMRCTL2_CNT_Pos) |
| #define | SC_TMRCTL2_OPMODE_Pos (24) |
| #define | SC_TMRCTL2_OPMODE_Msk (0xful << SC_TMRCTL2_OPMODE_Pos) |
| #define | SC_TMRCTL2_SYNC_Pos (31) |
| #define | SC_TMRCTL2_SYNC_Msk (0x1ul << SC_TMRCTL2_SYNC_Pos) |
| #define | SC_UARTCTL_UARTEN_Pos (0) |
| #define | SC_UARTCTL_UARTEN_Msk (0x1ul << SC_UARTCTL_UARTEN_Pos) |
| #define | SC_UARTCTL_WLS_Pos (4) |
| #define | SC_UARTCTL_WLS_Msk (0x3ul << SC_UARTCTL_WLS_Pos) |
| #define | SC_UARTCTL_PBOFF_Pos (6) |
| #define | SC_UARTCTL_PBOFF_Msk (0x1ul << SC_UARTCTL_PBOFF_Pos) |
| #define | SC_UARTCTL_OPE_Pos (7) |
| #define | SC_UARTCTL_OPE_Msk (0x1ul << SC_UARTCTL_OPE_Pos) |
| #define | SC_ACTCTL_T1EXT_Pos (0) |
| #define | SC_ACTCTL_T1EXT_Msk (0x1ful << SC_ACTCTL_T1EXT_Pos) |
| #define | I2C_CTL_I2CEN_Pos (0) |
| #define | I2C_CTL_I2CEN_Msk (0x1ul << I2C_CTL_I2CEN_Pos) |
| #define | I2C_CTL_AA_Pos (1) |
| #define | I2C_CTL_AA_Msk (0x1ul << I2C_CTL_AA_Pos) |
| #define | I2C_CTL_STO_Pos (2) |
| #define | I2C_CTL_STO_Msk (0x1ul << I2C_CTL_STO_Pos) |
| #define | I2C_CTL_STA_Pos (3) |
| #define | I2C_CTL_STA_Msk (0x1ul << I2C_CTL_STA_Pos) |
| #define | I2C_CTL_SI_Pos (4) |
| #define | I2C_CTL_SI_Msk (0x1ul << I2C_CTL_SI_Pos) |
| #define | I2C_CTL_INTEN_Pos (7) |
| #define | I2C_CTL_INTEN_Msk (0x1ul << I2C_CTL_INTEN_Pos) |
| #define | I2C_INTSTS_INTSTS_Pos (0) |
| #define | I2C_INTSTS_INTSTS_Msk (0x1ul << I2C_INTSTS_INTSTS_Pos) |
| #define | I2C_INTSTS_TOIF_Pos (1) |
| #define | I2C_INTSTS_TOIF_Msk (0x1ul << I2C_INTSTS_TOIF_Pos) |
| #define | I2C_INTSTS_WKAKDONE_Pos (7) |
| #define | I2C_INTSTS_WKAKDONE_Msk (0x1ul << I2C_INTSTS_WKAKDONE_Pos) |
| #define | I2C_STATUS_STATUS_Pos (0) |
| #define | I2C_STATUS_STATUS_Msk (0xfful << I2C_STATUS_STATUS_Pos) |
| #define | I2C_CLKDIV_DIVIDER_Pos (0) |
| #define | I2C_CLKDIV_DIVIDER_Msk (0xfful << I2C_CLKDIV_DIVIDER_Pos) |
| #define | I2C_TOCTL_TOCEN_Pos (0) |
| #define | I2C_TOCTL_TOCEN_Msk (0x1ul << I2C_TOCTL_TOCEN_Pos) |
| #define | I2C_TOCTL_TOCDIV4_Pos (1) |
| #define | I2C_TOCTL_TOCDIV4_Msk (0x1ul << I2C_TOCTL_TOCDIV4_Pos) |
| #define | I2C_DAT_DAT_Pos (0) |
| #define | I2C_DAT_DAT_Msk (0xfful << I2C_DAT_DAT_Pos) |
| #define | I2C_ADDR0_GC_Pos (0) |
| #define | I2C_ADDR0_GC_Msk (0x1ul << I2C_ADDR0_GC_Pos) |
| #define | I2C_ADDR0_ADDR_Pos (1) |
| #define | I2C_ADDR0_ADDR_Msk (0x7ful << I2C_ADDR0_ADDR_Pos) |
| #define | I2C_ADDR1_GC_Pos (0) |
| #define | I2C_ADDR1_GC_Msk (0x1ul << I2C_ADDR1_GC_Pos) |
| #define | I2C_ADDR1_ADDR_Pos (1) |
| #define | I2C_ADDR1_ADDR_Msk (0x7ful << I2C_ADDR1_ADDR_Pos) |
| #define | I2C_ADDRMSK0_ADDRMSK_Pos (1) |
| #define | I2C_ADDRMSK0_ADDRMSK_Msk (0x7ful << I2C_ADDRMSK0_ADDRMSK_Pos) |
| #define | I2C_ADDRMSK1_ADDRMSK_Pos (1) |
| #define | I2C_ADDRMSK1_ADDRMSK_Msk (0x7ful << I2C_ADDRMSK1_ADDRMSK_Pos) |
| #define | I2C_CTL2_WKUPEN_Pos (0) |
| #define | I2C_CTL2_WKUPEN_Msk (0x1ul << I2C_CTL2_WKUPEN_Pos) |
| #define | I2C_CTL2_OVIEN_Pos (1) |
| #define | I2C_CTL2_OVIEN_Msk (0x1ul << I2C_CTL2_OVIEN_Pos) |
| #define | I2C_CTL2_URIEN_Pos (2) |
| #define | I2C_CTL2_URIEN_Msk (0x1ul << I2C_CTL2_URIEN_Pos) |
| #define | I2C_CTL2_TWOLVBUF_Pos (4) |
| #define | I2C_CTL2_TWOLVBUF_Msk (0x1ul << I2C_CTL2_TWOLVBUF_Pos) |
| #define | I2C_CTL2_NOSTRETCH_Pos (5) |
| #define | I2C_CTL2_NOSTRETCH_Msk (0x1ul << I2C_CTL2_NOSTRETCH_Pos) |
| #define | I2C_CTL2_DATMODE_Pos (6) |
| #define | I2C_CTL2_DATMODE_Msk (0x1ul << I2C_CTL2_DATMODE_Pos) |
| #define | I2C_CTL2_MSDAT_Pos (7) |
| #define | I2C_CTL2_MSDAT_Msk (0x1ul << I2C_CTL2_MSDAT_Pos) |
| #define | I2C_STATUS2_WKIF_Pos (0) |
| #define | I2C_STATUS2_WKIF_Msk (0x1ul << I2C_STATUS2_WKIF_Pos) |
| #define | I2C_STATUS2_OVIF_Pos (1) |
| #define | I2C_STATUS2_OVIF_Msk (0x1ul << I2C_STATUS2_OVIF_Pos) |
| #define | I2C_STATUS2_URIF_Pos (2) |
| #define | I2C_STATUS2_URIF_Msk (0x1ul << I2C_STATUS2_URIF_Pos) |
| #define | I2C_STATUS2_WRSTSWK_Pos (3) |
| #define | I2C_STATUS2_WRSTSWK_Msk (0x1ul << I2C_STATUS2_WRSTSWK_Pos) |
| #define | I2C_STATUS2_FULL_Pos (4) |
| #define | I2C_STATUS2_FULL_Msk (0x1ul << I2C_STATUS2_FULL_Pos) |
| #define | I2C_STATUS2_EMPTY_Pos (5) |
| #define | I2C_STATUS2_EMPTY_Msk (0x1ul << I2C_STATUS2_EMPTY_Pos) |
| #define | I2C_STATUS2_BUSFREE_Pos (6) |
| #define | I2C_STATUS2_BUSFREE_Msk (0x1ul << I2C_STATUS2_BUSFREE_Pos) |
| #define | SPI_CTL_GOBUSY_Pos (0) |
| #define | SPI_CTL_GOBUSY_Msk (0x1ul << SPI_CTL_GOBUSY_Pos) |
| #define | SPI_CTL_RXNEG_Pos (1) |
| #define | SPI_CTL_RXNEG_Msk (0x1ul << SPI_CTL_RXNEG_Pos) |
| #define | SPI_CTL_TXNEG_Pos (2) |
| #define | SPI_CTL_TXNEG_Msk (0x1ul << SPI_CTL_TXNEG_Pos) |
| #define | SPI_CTL_DWIDTH_Pos (3) |
| #define | SPI_CTL_DWIDTH_Msk (0x1ful << SPI_CTL_DWIDTH_Pos) |
| #define | SPI_CTL_LSB_Pos (10) |
| #define | SPI_CTL_LSB_Msk (0x1ul << SPI_CTL_LSB_Pos) |
| #define | SPI_CTL_CLKPOL_Pos (11) |
| #define | SPI_CTL_CLKPOL_Msk (0x1ul << SPI_CTL_CLKPOL_Pos) |
| #define | SPI_CTL_SUSPITV_Pos (12) |
| #define | SPI_CTL_SUSPITV_Msk (0xful << SPI_CTL_SUSPITV_Pos) |
| #define | SPI_CTL_UNITIEN_Pos (17) |
| #define | SPI_CTL_UNITIEN_Msk (0x1ul << SPI_CTL_UNITIEN_Pos) |
| #define | SPI_CTL_SLAVE_Pos (18) |
| #define | SPI_CTL_SLAVE_Msk (0x1ul << SPI_CTL_SLAVE_Pos) |
| #define | SPI_CTL_REORDER_Pos (19) |
| #define | SPI_CTL_REORDER_Msk (0x1ul << SPI_CTL_REORDER_Pos) |
| #define | SPI_CTL_FIFOM_Pos (21) |
| #define | SPI_CTL_FIFOM_Msk (0x1ul << SPI_CTL_FIFOM_Pos) |
| #define | SPI_CTL_TWOBIT_Pos (22) |
| #define | SPI_CTL_TWOBIT_Msk (0x1ul << SPI_CTL_TWOBIT_Pos) |
| #define | SPI_CTL_DUALDIR_Pos (28) |
| #define | SPI_CTL_DUALDIR_Msk (0x1ul << SPI_CTL_DUALDIR_Pos) |
| #define | SPI_CTL_DUALIOEN_Pos (29) |
| #define | SPI_CTL_DUALIOEN_Msk (0x1ul << SPI_CTL_DUALIOEN_Pos) |
| #define | SPI_CTL_WKSSEN_Pos (30) |
| #define | SPI_CTL_WKSSEN_Msk (0x1ul << SPI_CTL_WKSSEN_Pos) |
| #define | SPI_CTL_WKCLKEN_Pos (31) |
| #define | SPI_CTL_WKCLKEN_Msk (0x1ul << SPI_CTL_WKCLKEN_Pos) |
| #define | SPI_STATUS_RXEMPTY_Pos (0) |
| #define | SPI_STATUS_RXEMPTY_Msk (0x1ul << SPI_STATUS_RXEMPTY_Pos) |
| #define | SPI_STATUS_RXFULL_Pos (1) |
| #define | SPI_STATUS_RXFULL_Msk (0x1ul << SPI_STATUS_RXFULL_Pos) |
| #define | SPI_STATUS_TXEMPTY_Pos (2) |
| #define | SPI_STATUS_TXEMPTY_Msk (0x1ul << SPI_STATUS_TXEMPTY_Pos) |
| #define | SPI_STATUS_TXFULL_Pos (3) |
| #define | SPI_STATUS_TXFULL_Msk (0x1ul << SPI_STATUS_TXFULL_Pos) |
| #define | SPI_STATUS_LTRIGF_Pos (4) |
| #define | SPI_STATUS_LTRIGF_Msk (0x1ul << SPI_STATUS_LTRIGF_Pos) |
| #define | SPI_STATUS_SLVSTAIF_Pos (6) |
| #define | SPI_STATUS_SLVSTAIF_Msk (0x1ul << SPI_STATUS_SLVSTAIF_Pos) |
| #define | SPI_STATUS_UNITIF_Pos (7) |
| #define | SPI_STATUS_UNITIF_Msk (0x1ul << SPI_STATUS_UNITIF_Pos) |
| #define | SPI_STATUS_RXTHIF_Pos (8) |
| #define | SPI_STATUS_RXTHIF_Msk (0x1ul << SPI_STATUS_RXTHIF_Pos) |
| #define | SPI_STATUS_RXOVIF_Pos (9) |
| #define | SPI_STATUS_RXOVIF_Msk (0x1ul << SPI_STATUS_RXOVIF_Pos) |
| #define | SPI_STATUS_TXTHIF_Pos (10) |
| #define | SPI_STATUS_TXTHIF_Msk (0x1ul << SPI_STATUS_TXTHIF_Pos) |
| #define | SPI_STATUS_RXTOIF_Pos (12) |
| #define | SPI_STATUS_RXTOIF_Msk (0x1ul << SPI_STATUS_RXTOIF_Pos) |
| #define | SPI_STATUS_SLVTOIF_Pos (13) |
| #define | SPI_STATUS_SLVTOIF_Msk (0x1ul << SPI_STATUS_SLVTOIF_Pos) |
| #define | SPI_STATUS_SLVTXSKE_Pos (15) |
| #define | SPI_STATUS_SLVTXSKE_Msk (0x1ul << SPI_STATUS_SLVTXSKE_Pos) |
| #define | SPI_STATUS_RXCNT_Pos (16) |
| #define | SPI_STATUS_RXCNT_Msk (0xful << SPI_STATUS_RXCNT_Pos) |
| #define | SPI_STATUS_TXCNT_Pos (20) |
| #define | SPI_STATUS_TXCNT_Msk (0xful << SPI_STATUS_TXCNT_Pos) |
| #define | SPI_STATUS_WKSSIF_Pos (30) |
| #define | SPI_STATUS_WKSSIF_Msk (0x1ul << SPI_STATUS_WKSSIF_Pos) |
| #define | SPI_STATUS_WKCLKIF_Pos (31) |
| #define | SPI_STATUS_WKCLKIF_Msk (0x1ul << SPI_STATUS_WKCLKIF_Pos) |
| #define | SPI_CLKDIV_DIVIDER_Pos (0) |
| #define | SPI_CLKDIV_DIVIDER_Msk (0xfful << SPI_CLKDIV_DIVIDER_Pos) |
| #define | SPI_SSCTL_SS_Pos (0) |
| #define | SPI_SSCTL_SS_Msk (0x3ul << SPI_SSCTL_SS_Pos) |
| #define | SPI_SSCTL_SSACTPOL_Pos (2) |
| #define | SPI_SSCTL_SSACTPOL_Msk (0x1ul << SPI_SSCTL_SSACTPOL_Pos) |
| #define | SPI_SSCTL_AUTOSS_Pos (3) |
| #define | SPI_SSCTL_AUTOSS_Msk (0x1ul << SPI_SSCTL_AUTOSS_Pos) |
| #define | SPI_SSCTL_SSLTRIG_Pos (4) |
| #define | SPI_SSCTL_SSLTRIG_Msk (0x1ul << SPI_SSCTL_SSLTRIG_Pos) |
| #define | SPI_SSCTL_SLV3WIRE_Pos (5) |
| #define | SPI_SSCTL_SLV3WIRE_Msk (0x1ul << SPI_SSCTL_SLV3WIRE_Pos) |
| #define | SPI_SSCTL_SLVTOIEN_Pos (6) |
| #define | SPI_SSCTL_SLVTOIEN_Msk (0x1ul << SPI_SSCTL_SLVTOIEN_Pos) |
| #define | SPI_SSCTL_SLVABORT_Pos (8) |
| #define | SPI_SSCTL_SLVABORT_Msk (0x1ul << SPI_SSCTL_SLVABORT_Pos) |
| #define | SPI_SSCTL_SSTAIEN_Pos (9) |
| #define | SPI_SSCTL_SSTAIEN_Msk (0x1ul << SPI_SSCTL_SSTAIEN_Pos) |
| #define | SPI_SSCTL_SSINAIEN_Pos (16) |
| #define | SPI_SSCTL_SSINAIEN_Msk (0x1ul << SPI_SSCTL_SSINAIEN_Pos) |
| #define | SPI_SSCTL_SLVTOCNT_Pos (20) |
| #define | SPI_SSCTL_SLVTOCNT_Msk (0x3fful << SPI_SSCTL_SLVTOCNT_Pos) |
| #define | SPI_RX0_RX_Pos (0) |
| #define | SPI_RX0_RX_Msk (0xfffffffful << SPI_RX0_RX_Pos) |
| #define | SPI_RX1_RX_Pos (0) |
| #define | SPI_RX1_RX_Msk (0xfffffffful << SPI_RX1_RX_Pos) |
| #define | SPI_TX0_TX_Pos (0) |
| #define | SPI_TX0_TX_Msk (0xfffffffful << SPI_TX0_TX_Pos) |
| #define | SPI_TX1_TX_Pos (0) |
| #define | SPI_TX1_TX_Msk (0xfffffffful << SPI_TX1_TX_Pos) |
| #define | SPI_PDMACTL_TXPDMAEN_Pos (0) |
| #define | SPI_PDMACTL_TXPDMAEN_Msk (0x1ul << SPI_PDMACTL_TXPDMAEN_Pos) |
| #define | SPI_PDMACTL_RXPDMAEN_Pos (1) |
| #define | SPI_PDMACTL_RXPDMAEN_Msk (0x1ul << SPI_PDMACTL_RXPDMAEN_Pos) |
| #define | SPI_PDMACTL_PDMARST_Pos (2) |
| #define | SPI_PDMACTL_PDMARST_Msk (0x1ul << SPI_PDMACTL_PDMARST_Pos) |
| #define | SPI_FIFOCTL_RXFBCLR_Pos (0) |
| #define | SPI_FIFOCTL_RXFBCLR_Msk (0x1ul << SPI_FIFOCTL_RXFBCLR_Pos) |
| #define | SPI_FIFOCTL_TXFBCLR_Pos (1) |
| #define | SPI_FIFOCTL_TXFBCLR_Msk (0x1ul << SPI_FIFOCTL_TXFBCLR_Pos) |
| #define | SPI_FIFOCTL_RXTHIEN_Pos (2) |
| #define | SPI_FIFOCTL_RXTHIEN_Msk (0x1ul << SPI_FIFOCTL_RXTHIEN_Pos) |
| #define | SPI_FIFOCTL_TXTHIEN_Pos (3) |
| #define | SPI_FIFOCTL_TXTHIEN_Msk (0x1ul << SPI_FIFOCTL_TXTHIEN_Pos) |
| #define | SPI_FIFOCTL_RXOVIEN_Pos (4) |
| #define | SPI_FIFOCTL_RXOVIEN_Msk (0x1ul << SPI_FIFOCTL_RXOVIEN_Pos) |
| #define | SPI_FIFOCTL_RXTOIEN_Pos (7) |
| #define | SPI_FIFOCTL_RXTOIEN_Msk (0x1ul << SPI_FIFOCTL_RXTOIEN_Pos) |
| #define | SPI_FIFOCTL_RXTH_Pos (24) |
| #define | SPI_FIFOCTL_RXTH_Msk (0x7ul << SPI_FIFOCTL_RXTH_Pos) |
| #define | SPI_FIFOCTL_TXTH_Pos (28) |
| #define | SPI_FIFOCTL_TXTH_Msk (0x7ul << SPI_FIFOCTL_TXTH_Pos) |
| #define | ADC_DAT0_RESULT_Pos (0) |
| #define | ADC_DAT0_RESULT_Msk (0xffful << ADC_DAT0_RESULT_Pos) |
| #define | ADC_DAT0_VALID_Pos (16) |
| #define | ADC_DAT0_VALID_Msk (0x1ul << ADC_DAT0_VALID_Pos) |
| #define | ADC_DAT0_OV_Pos (17) |
| #define | ADC_DAT0_OV_Msk (0x1ul << ADC_DAT0_OV_Pos) |
| #define | ADC_CTL_ADCEN_Pos (0) |
| #define | ADC_CTL_ADCEN_Msk (0x1ul << ADC_CTL_ADCEN_Pos) |
| #define | ADC_CTL_ADCIEN_Pos (1) |
| #define | ADC_CTL_ADCIEN_Msk (0x1ul << ADC_CTL_ADCIEN_Pos) |
| #define | ADC_CTL_ADMD_Pos (2) |
| #define | ADC_CTL_ADMD_Msk (0x3ul << ADC_CTL_ADMD_Pos) |
| #define | ADC_CTL_HWTRGSEL_Pos (4) |
| #define | ADC_CTL_HWTRGSEL_Msk (0x3ul << ADC_CTL_HWTRGSEL_Pos) |
| #define | ADC_CTL_HWTRGCOND_Pos (6) |
| #define | ADC_CTL_HWTRGCOND_Msk (0x3ul << ADC_CTL_HWTRGCOND_Pos) |
| #define | ADC_CTL_HWTRGEN_Pos (8) |
| #define | ADC_CTL_HWTRGEN_Msk (0x1ul << ADC_CTL_HWTRGEN_Pos) |
| #define | ADC_CTL_PTEN_Pos (9) |
| #define | ADC_CTL_PTEN_Msk (0x1ul << ADC_CTL_PTEN_Pos) |
| #define | ADC_CTL_DIFF_Pos (10) |
| #define | ADC_CTL_DIFF_Msk (0x1ul << ADC_CTL_DIFF_Pos) |
| #define | ADC_CTL_SWTRG_Pos (11) |
| #define | ADC_CTL_SWTRG_Msk (0x1ul << ADC_CTL_SWTRG_Pos) |
| #define | ADC_CTL_TMSEL_Pos (12) |
| #define | ADC_CTL_TMSEL_Msk (0x3ul << ADC_CTL_TMSEL_Pos) |
| #define | ADC_CTL_TMTRGMOD_Pos (15) |
| #define | ADC_CTL_TMTRGMOD_Msk (0x1ul << ADC_CTL_TMTRGMOD_Pos) |
| #define | ADC_CTL_REFSEL_Pos (16) |
| #define | ADC_CTL_REFSEL_Msk (0x3ul << ADC_CTL_REFSEL_Pos) |
| #define | ADC_CTL_RESSEL_Pos (18) |
| #define | ADC_CTL_RESSEL_Msk (0x3ul << ADC_CTL_RESSEL_Pos) |
| #define | ADC_CTL_TMPDMACNT_Pos (24) |
| #define | ADC_CTL_TMPDMACNT_Msk (0xfful << ADC_CTL_TMPDMACNT_Pos) |
| #define | ADC_CHEN_CHEN0_Pos (0) |
| #define | ADC_CHEN_CHEN0_Msk (0x1ul << ADC_CHEN_CHEN0_Pos) |
| #define | ADC_CHEN_CHEN1_Pos (1) |
| #define | ADC_CHEN_CHEN1_Msk (0x1ul << ADC_CHEN_CHEN1_Pos) |
| #define | ADC_CHEN_CHEN2_Pos (2) |
| #define | ADC_CHEN_CHEN2_Msk (0x1ul << ADC_CHEN_CHEN2_Pos) |
| #define | ADC_CHEN_CHEN3_Pos (3) |
| #define | ADC_CHEN_CHEN3_Msk (0x1ul << ADC_CHEN_CHEN3_Pos) |
| #define | ADC_CHEN_CHEN4_Pos (4) |
| #define | ADC_CHEN_CHEN4_Msk (0x1ul << ADC_CHEN_CHEN4_Pos) |
| #define | ADC_CHEN_CHEN5_Pos (5) |
| #define | ADC_CHEN_CHEN5_Msk (0x1ul << ADC_CHEN_CHEN5_Pos) |
| #define | ADC_CHEN_CHEN6_Pos (6) |
| #define | ADC_CHEN_CHEN6_Msk (0x1ul << ADC_CHEN_CHEN6_Pos) |
| #define | ADC_CHEN_CHEN7_Pos (7) |
| #define | ADC_CHEN_CHEN7_Msk (0x1ul << ADC_CHEN_CHEN7_Pos) |
| #define | ADC_CHEN_CHEN12_Pos (12) |
| #define | ADC_CHEN_CHEN12_Msk (0x1ul << ADC_CHEN_CHEN12_Pos) |
| #define | ADC_CHEN_CHEN13_Pos (13) |
| #define | ADC_CHEN_CHEN13_Msk (0x1ul << ADC_CHEN_CHEN13_Pos) |
| #define | ADC_CHEN_CHEN14_Pos (14) |
| #define | ADC_CHEN_CHEN14_Msk (0x1ul << ADC_CHEN_CHEN14_Pos) |
| #define | ADC_CHEN_CHEN15_Pos (15) |
| #define | ADC_CHEN_CHEN15_Msk (0x1ul << ADC_CHEN_CHEN15_Pos) |
| #define | ADC_CHEN_CHEN16_Pos (16) |
| #define | ADC_CHEN_CHEN16_Msk (0x1ul << ADC_CHEN_CHEN16_Pos) |
| #define | ADC_CHEN_CHEN17_Pos (17) |
| #define | ADC_CHEN_CHEN17_Msk (0x1ul << ADC_CHEN_CHEN17_Pos) |
| #define | ADC_CMP0_ADCMPEN_Pos (0) |
| #define | ADC_CMP0_ADCMPEN_Msk (0x1ul << ADC_CMP0_ADCMPEN_Pos) |
| #define | ADC_CMP0_ADCMPIE_Pos (1) |
| #define | ADC_CMP0_ADCMPIE_Msk (0x1ul << ADC_CMP0_ADCMPIE_Pos) |
| #define | ADC_CMP0_CMPCOND_Pos (2) |
| #define | ADC_CMP0_CMPCOND_Msk (0x1ul << ADC_CMP0_CMPCOND_Pos) |
| #define | ADC_CMP0_CMPCH_Pos (3) |
| #define | ADC_CMP0_CMPCH_Msk (0x1ful << ADC_CMP0_CMPCH_Pos) |
| #define | ADC_CMP0_CMPMCNT_Pos (8) |
| #define | ADC_CMP0_CMPMCNT_Msk (0xful << ADC_CMP0_CMPMCNT_Pos) |
| #define | ADC_CMP0_CMPDAT_Pos (16) |
| #define | ADC_CMP0_CMPDAT_Msk (0xffful << ADC_CMP0_CMPDAT_Pos) |
| #define | ADC_CMP1_ADCMPEN_Pos (0) |
| #define | ADC_CMP1_ADCMPEN_Msk (0x1ul << ADC_CMP1_ADCMPEN_Pos) |
| #define | ADC_CMP1_ADCMPIE_Pos (1) |
| #define | ADC_CMP1_ADCMPIE_Msk (0x1ul << ADC_CMP1_ADCMPIE_Pos) |
| #define | ADC_CMP1_CMPCOND_Pos (2) |
| #define | ADC_CMP1_CMPCOND_Msk (0x1ul << ADC_CMP1_CMPCOND_Pos) |
| #define | ADC_CMP1_CMPCH_Pos (3) |
| #define | ADC_CMP1_CMPCH_Msk (0x1ful << ADC_CMP1_CMPCH_Pos) |
| #define | ADC_CMP1_CMPMCNT_Pos (8) |
| #define | ADC_CMP1_CMPMCNT_Msk (0xful << ADC_CMP1_CMPMCNT_Pos) |
| #define | ADC_CMP1_CMPDAT_Pos (16) |
| #define | ADC_CMP1_CMPDAT_Msk (0xffful << ADC_CMP1_CMPDAT_Pos) |
| #define | ADC_STATUS_ADIF_Pos (0) |
| #define | ADC_STATUS_ADIF_Msk (0x1ul << ADC_STATUS_ADIF_Pos) |
| #define | ADC_STATUS_ADCMPF0_Pos (1) |
| #define | ADC_STATUS_ADCMPF0_Msk (0x1ul << ADC_STATUS_ADCMPF0_Pos) |
| #define | ADC_STATUS_ADCMPF1_Pos (2) |
| #define | ADC_STATUS_ADCMPF1_Msk (0x1ul << ADC_STATUS_ADCMPF1_Pos) |
| #define | ADC_STATUS_BUSY_Pos (3) |
| #define | ADC_STATUS_BUSY_Msk (0x1ul << ADC_STATUS_BUSY_Pos) |
| #define | ADC_STATUS_CHANNEL_Pos (4) |
| #define | ADC_STATUS_CHANNEL_Msk (0x1ful << ADC_STATUS_CHANNEL_Pos) |
| #define | ADC_STATUS_INITRDY_Pos (16) |
| #define | ADC_STATUS_INITRDY_Msk (0x1ul << ADC_STATUS_INITRDY_Pos) |
| #define | ADC_PDMA_AD_PDMA_Pos (0) |
| #define | ADC_PDMA_AD_PDMA_Msk (0xffful << ADC_PDMA_AD_PDMA_Pos) |
| #define | ADC_PWD_PWUPRDY_Pos (0) |
| #define | ADC_PWD_PWUPRDY_Msk (0x1ul << ADC_PWD_PWUPRDY_Pos) |
| #define | ADC_PWD_PWDCALEN_Pos (1) |
| #define | ADC_PWD_PWDCALEN_Msk (0x1ul << ADC_PWD_PWDCALEN_Pos) |
| #define | ADC_PWD_PWDMOD_Pos (2) |
| #define | ADC_PWD_PWDMOD_Msk (0x3ul << ADC_PWD_PWDMOD_Pos) |
| #define | ADC_CALCTL_CALEN_Pos (0) |
| #define | ADC_CALCTL_CALEN_Msk (0x1ul << ADC_CALCTL_CALEN_Pos) |
| #define | ADC_CALCTL_CALSTART_Pos (1) |
| #define | ADC_CALCTL_CALSTART_Msk (0x1ul << ADC_CALCTL_CALSTART_Pos) |
| #define | ADC_CALCTL_CALDONE_Pos (2) |
| #define | ADC_CALCTL_CALDONE_Msk (0x1ul << ADC_CALCTL_CALDONE_Pos) |
| #define | ADC_CALCTL_CALSEL_Pos (3) |
| #define | ADC_CALCTL_CALSEL_Msk (0x1ul << ADC_CALCTL_CALSEL_Pos) |
| #define | ADC_CALWORD_CALWORD_Pos (0) |
| #define | ADC_CALWORD_CALWORD_Msk (0x7ful << ADC_CALWORD_CALWORD_Pos) |
| #define | ADC_EXTSMPT0_EXTSMPT_CH0_Pos (0) |
| #define | ADC_EXTSMPT0_EXTSMPT_CH0_Msk (0xful << ADC_EXTSMPT0_EXTSMPT_CH0_Pos) |
| #define | ADC_EXTSMPT0_EXTSMPT_CH1_Pos (4) |
| #define | ADC_EXTSMPT0_EXTSMPT_CH1_Msk (0xful << ADC_EXTSMPT0_EXTSMPT_CH1_Pos) |
| #define | ADC_EXTSMPT0_EXTSMPT_CH2_Pos (8) |
| #define | ADC_EXTSMPT0_EXTSMPT_CH2_Msk (0xful << ADC_EXTSMPT0_EXTSMPT_CH2_Pos) |
| #define | ADC_EXTSMPT0_EXTSMPT_CH3_Pos (12) |
| #define | ADC_EXTSMPT0_EXTSMPT_CH3_Msk (0xful << ADC_EXTSMPT0_EXTSMPT_CH3_Pos) |
| #define | ADC_EXTSMPT0_EXTSMPT_CH4_Pos (16) |
| #define | ADC_EXTSMPT0_EXTSMPT_CH4_Msk (0xful << ADC_EXTSMPT0_EXTSMPT_CH4_Pos) |
| #define | ADC_EXTSMPT0_EXTSMPT_CH5_Pos (20) |
| #define | ADC_EXTSMPT0_EXTSMPT_CH5_Msk (0xful << ADC_EXTSMPT0_EXTSMPT_CH5_Pos) |
| #define | ADC_EXTSMPT0_EXTSMPT_CH6_Pos (24) |
| #define | ADC_EXTSMPT0_EXTSMPT_CH6_Msk (0xful << ADC_EXTSMPT0_EXTSMPT_CH6_Pos) |
| #define | ADC_EXTSMPT0_EXTSMPT_CH7_Pos (28) |
| #define | ADC_EXTSMPT0_EXTSMPT_CH7_Msk (0xful << ADC_EXTSMPT0_EXTSMPT_CH7_Pos) |
| #define | ADC_EXTSMPT1_EXTSMPT_INTCH_Pos (16) |
| #define | ADC_EXTSMPT1_EXTSMPT_INTCH_Msk (0xful << ADC_EXTSMPT1_EXTSMPT_INTCH_Pos) |
| #define | ACMP_CTL0_ACMPEN_Pos (0) |
| #define | ACMP_CTL0_ACMPEN_Msk (0x1ul << ACMP_CTL0_ACMPEN_Pos) |
| #define | ACMP_CTL0_ACMPIE_Pos (1) |
| #define | ACMP_CTL0_ACMPIE_Msk (0x1ul << ACMP_CTL0_ACMPIE_Pos) |
| #define | ACMP_CTL0_HYSEN_Pos (2) |
| #define | ACMP_CTL0_HYSEN_Msk (0x1ul << ACMP_CTL0_HYSEN_Pos) |
| #define | ACMP_CTL0_NEGSEL_Pos (4) |
| #define | ACMP_CTL0_NEGSEL_Msk (0x3ul << ACMP_CTL0_NEGSEL_Pos) |
| #define | ACMP_CTL0_WKEN_Pos (31) |
| #define | ACMP_CTL0_WKEN_Msk (0x1ul << ACMP_CTL0_WKEN_Pos) |
| #define | ACMP_STATUS_ACMPIF_Pos (0) |
| #define | ACMP_STATUS_ACMPIF_Msk (0x1ul << ACMP_STATUS_ACMPIF_Pos) |
| #define | ACMP_STATUS_ACMPO_Pos (1) |
| #define | ACMP_STATUS_ACMPO_Msk (0x1ul << ACMP_STATUS_ACMPO_Pos) |
| #define | ACMP_VREF_CRVCTL_Pos (0) |
| #define | ACMP_VREF_CRVCTL_Msk (0xful << ACMP_VREF_CRVCTL_Pos) |
| #define | ACMP_VREF_CRVEN_Pos (4) |
| #define | ACMP_VREF_CRVEN_Msk (0x1ul << ACMP_VREF_CRVEN_Pos) |
| #define | ACMP_VREF_CRVSSEL_Pos (5) |
| #define | ACMP_VREF_CRVSSEL_Msk (0x1ul << ACMP_VREF_CRVSSEL_Pos) |
Typedefs | |
| typedef enum IRQn | IRQn_Type |
| typedef volatile unsigned char | vu8 |
| Define 8-bit unsigned volatile data type. More... | |
| typedef volatile unsigned short | vu16 |
| Define 16-bit unsigned volatile data type. More... | |
| typedef volatile unsigned long | vu32 |
| Define 32-bit unsigned volatile data type. More... | |
Enumerations | |
| enum | IRQn { NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, SVCall_IRQn = -5, PendSV_IRQn = -2, SysTick_IRQn = -1, BOD_IRQn = 0, WDT_IRQn = 1, EINT0_IRQn = 2, EINT1_IRQn = 3, GPABC_IRQn = 4, GPDEF_IRQn = 5, PWM0_IRQn = 6, TMR0_IRQn = 8, TMR1_IRQn = 9, TMR2_IRQn = 10, TMR3_IRQn = 11, UART0_IRQn = 12, UART1_IRQn = 13, SPI0_IRQn = 14, SPI1_IRQn = 15, SPI2_IRQn = 16, HIRC_IRQn = 17, I2C0_IRQn = 18, I2C1_IRQn = 19, SC0_IRQn = 21, SC1_IRQn = 22, CKSD_IRQn = 24, PDMA_IRQn = 26, SPI3_IRQn = 27, PDWU_IRQn = 28, ADC_IRQn = 29, ACMP_IRQn = 30, RTC_IRQn = 31 } |
NANO103 peripheral access layer header file. This file contains all the peripheral register's definitions, bits definitions and memory mapping for NuMicro NANO103 MCU.
Definition in file Nano103.h.
| #define ACMP_CTL0_ACMPEN_Msk (0x1ul << ACMP_CTL0_ACMPEN_Pos) |
ACMP_T::CTL0: ACMPEN Mask
| #define ACMP_CTL0_ACMPEN_Pos (0) |
@addtogroup ACMP_CONST ACMP Bit Field Definition Constant Definitions for ACMP Controller
ACMP_T::CTL0: ACMPEN Position
| #define ACMP_CTL0_ACMPIE_Msk (0x1ul << ACMP_CTL0_ACMPIE_Pos) |
ACMP_T::CTL0: ACMPIE Mask
| #define ACMP_CTL0_ACMPIE_Pos (1) |
ACMP_T::CTL0: ACMPIE Position
| #define ACMP_CTL0_HYSEN_Msk (0x1ul << ACMP_CTL0_HYSEN_Pos) |
ACMP_T::CTL0: HYSEN Mask
| #define ACMP_CTL0_HYSEN_Pos (2) |
ACMP_T::CTL0: HYSEN Position
| #define ACMP_CTL0_NEGSEL_Msk (0x3ul << ACMP_CTL0_NEGSEL_Pos) |
ACMP_T::CTL0: NEGSEL Mask
| #define ACMP_CTL0_NEGSEL_Pos (4) |
ACMP_T::CTL0: NEGSEL Position
| #define ACMP_CTL0_WKEN_Msk (0x1ul << ACMP_CTL0_WKEN_Pos) |
ACMP_T::CTL0: WKEN Mask
| #define ACMP_CTL0_WKEN_Pos (31) |
ACMP_T::CTL0: WKEN Position
| #define ACMP_STATUS_ACMPIF_Msk (0x1ul << ACMP_STATUS_ACMPIF_Pos) |
ACMP_T::STATUS: ACMPIF Mask
| #define ACMP_STATUS_ACMPIF_Pos (0) |
ACMP_T::STATUS: ACMPIF Position
| #define ACMP_STATUS_ACMPO_Msk (0x1ul << ACMP_STATUS_ACMPO_Pos) |
ACMP_T::STATUS: ACMPO Mask
| #define ACMP_STATUS_ACMPO_Pos (1) |
ACMP_T::STATUS: ACMPO Position
| #define ACMP_VREF_CRVCTL_Msk (0xful << ACMP_VREF_CRVCTL_Pos) |
ACMP_T::VREF: CRVCTL Mask
| #define ACMP_VREF_CRVCTL_Pos (0) |
ACMP_T::VREF: CRVCTL Position
| #define ACMP_VREF_CRVEN_Msk (0x1ul << ACMP_VREF_CRVEN_Pos) |
ACMP_T::VREF: CRVEN Mask
| #define ACMP_VREF_CRVEN_Pos (4) |
ACMP_T::VREF: CRVEN Position
| #define ACMP_VREF_CRVSSEL_Msk (0x1ul << ACMP_VREF_CRVSSEL_Pos) |
ACMP_T::VREF: CRVSSEL Mask
| #define ACMP_VREF_CRVSSEL_Pos (5) |
ACMP_T::VREF: CRVSSEL Position
| #define ADC_CALCTL_CALDONE_Msk (0x1ul << ADC_CALCTL_CALDONE_Pos) |
ADC_T::CALCTL: CALDONE Mask
| #define ADC_CALCTL_CALDONE_Pos (2) |
ADC_T::CALCTL: CALDONE Position
| #define ADC_CALCTL_CALEN_Msk (0x1ul << ADC_CALCTL_CALEN_Pos) |
ADC_T::CALCTL: CALEN Mask
| #define ADC_CALCTL_CALEN_Pos (0) |
ADC_T::CALCTL: CALEN Position
| #define ADC_CALCTL_CALSEL_Msk (0x1ul << ADC_CALCTL_CALSEL_Pos) |
ADC_T::CALCTL: CALSEL Mask
| #define ADC_CALCTL_CALSEL_Pos (3) |
ADC_T::CALCTL: CALSEL Position
| #define ADC_CALCTL_CALSTART_Msk (0x1ul << ADC_CALCTL_CALSTART_Pos) |
ADC_T::CALCTL: CALSTART Mask
| #define ADC_CALCTL_CALSTART_Pos (1) |
ADC_T::CALCTL: CALSTART Position
| #define ADC_CALWORD_CALWORD_Msk (0x7ful << ADC_CALWORD_CALWORD_Pos) |
ADC_T::CALWORD: CALWORD Mask
| #define ADC_CALWORD_CALWORD_Pos (0) |
ADC_T::CALWORD: CALWORD Position
| #define ADC_CHEN_CHEN0_Msk (0x1ul << ADC_CHEN_CHEN0_Pos) |
ADC_T::CHEN: CHEN0 Mask
| #define ADC_CHEN_CHEN0_Pos (0) |
ADC_T::CHEN: CHEN0 Position
| #define ADC_CHEN_CHEN12_Msk (0x1ul << ADC_CHEN_CHEN12_Pos) |
ADC_T::CHEN: CHEN12 Mask
| #define ADC_CHEN_CHEN12_Pos (12) |
ADC_T::CHEN: CHEN12 Position
| #define ADC_CHEN_CHEN13_Msk (0x1ul << ADC_CHEN_CHEN13_Pos) |
ADC_T::CHEN: CHEN13 Mask
| #define ADC_CHEN_CHEN13_Pos (13) |
ADC_T::CHEN: CHEN13 Position
| #define ADC_CHEN_CHEN14_Msk (0x1ul << ADC_CHEN_CHEN14_Pos) |
ADC_T::CHEN: CHEN14 Mask
| #define ADC_CHEN_CHEN14_Pos (14) |
ADC_T::CHEN: CHEN14 Position
| #define ADC_CHEN_CHEN15_Msk (0x1ul << ADC_CHEN_CHEN15_Pos) |
ADC_T::CHEN: CHEN15 Mask
| #define ADC_CHEN_CHEN15_Pos (15) |
ADC_T::CHEN: CHEN15 Position
| #define ADC_CHEN_CHEN16_Msk (0x1ul << ADC_CHEN_CHEN16_Pos) |
ADC_T::CHEN: CHEN16 Mask
| #define ADC_CHEN_CHEN16_Pos (16) |
ADC_T::CHEN: CHEN16 Position
| #define ADC_CHEN_CHEN17_Msk (0x1ul << ADC_CHEN_CHEN17_Pos) |
ADC_T::CHEN: CHEN17 Mask
| #define ADC_CHEN_CHEN17_Pos (17) |
ADC_T::CHEN: CHEN17 Position
| #define ADC_CHEN_CHEN1_Msk (0x1ul << ADC_CHEN_CHEN1_Pos) |
ADC_T::CHEN: CHEN1 Mask
| #define ADC_CHEN_CHEN1_Pos (1) |
ADC_T::CHEN: CHEN1 Position
| #define ADC_CHEN_CHEN2_Msk (0x1ul << ADC_CHEN_CHEN2_Pos) |
ADC_T::CHEN: CHEN2 Mask
| #define ADC_CHEN_CHEN2_Pos (2) |
ADC_T::CHEN: CHEN2 Position
| #define ADC_CHEN_CHEN3_Msk (0x1ul << ADC_CHEN_CHEN3_Pos) |
ADC_T::CHEN: CHEN3 Mask
| #define ADC_CHEN_CHEN3_Pos (3) |
ADC_T::CHEN: CHEN3 Position
| #define ADC_CHEN_CHEN4_Msk (0x1ul << ADC_CHEN_CHEN4_Pos) |
ADC_T::CHEN: CHEN4 Mask
| #define ADC_CHEN_CHEN4_Pos (4) |
ADC_T::CHEN: CHEN4 Position
| #define ADC_CHEN_CHEN5_Msk (0x1ul << ADC_CHEN_CHEN5_Pos) |
ADC_T::CHEN: CHEN5 Mask
| #define ADC_CHEN_CHEN5_Pos (5) |
ADC_T::CHEN: CHEN5 Position
| #define ADC_CHEN_CHEN6_Msk (0x1ul << ADC_CHEN_CHEN6_Pos) |
ADC_T::CHEN: CHEN6 Mask
| #define ADC_CHEN_CHEN6_Pos (6) |
ADC_T::CHEN: CHEN6 Position
| #define ADC_CHEN_CHEN7_Msk (0x1ul << ADC_CHEN_CHEN7_Pos) |
ADC_T::CHEN: CHEN7 Mask
| #define ADC_CHEN_CHEN7_Pos (7) |
ADC_T::CHEN: CHEN7 Position
| #define ADC_CMP0_ADCMPEN_Msk (0x1ul << ADC_CMP0_ADCMPEN_Pos) |
ADC_T::CMP0: ADCMPEN Mask
| #define ADC_CMP0_ADCMPEN_Pos (0) |
ADC_T::CMP0: ADCMPEN Position
| #define ADC_CMP0_ADCMPIE_Msk (0x1ul << ADC_CMP0_ADCMPIE_Pos) |
ADC_T::CMP0: ADCMPIE Mask
| #define ADC_CMP0_ADCMPIE_Pos (1) |
ADC_T::CMP0: ADCMPIE Position
| #define ADC_CMP0_CMPCH_Msk (0x1ful << ADC_CMP0_CMPCH_Pos) |
ADC_T::CMP0: CMPCH Mask
| #define ADC_CMP0_CMPCH_Pos (3) |
ADC_T::CMP0: CMPCH Position
| #define ADC_CMP0_CMPCOND_Msk (0x1ul << ADC_CMP0_CMPCOND_Pos) |
ADC_T::CMP0: CMPCOND Mask
| #define ADC_CMP0_CMPCOND_Pos (2) |
ADC_T::CMP0: CMPCOND Position
| #define ADC_CMP0_CMPDAT_Msk (0xffful << ADC_CMP0_CMPDAT_Pos) |
ADC_T::CMP0: CMPDAT Mask
| #define ADC_CMP0_CMPDAT_Pos (16) |
ADC_T::CMP0: CMPDAT Position
| #define ADC_CMP0_CMPMCNT_Msk (0xful << ADC_CMP0_CMPMCNT_Pos) |
ADC_T::CMP0: CMPMCNT Mask
| #define ADC_CMP0_CMPMCNT_Pos (8) |
ADC_T::CMP0: CMPMCNT Position
| #define ADC_CMP1_ADCMPEN_Msk (0x1ul << ADC_CMP1_ADCMPEN_Pos) |
ADC_T::CMP1: ADCMPEN Mask
| #define ADC_CMP1_ADCMPEN_Pos (0) |
ADC_T::CMP1: ADCMPEN Position
| #define ADC_CMP1_ADCMPIE_Msk (0x1ul << ADC_CMP1_ADCMPIE_Pos) |
ADC_T::CMP1: ADCMPIE Mask
| #define ADC_CMP1_ADCMPIE_Pos (1) |
ADC_T::CMP1: ADCMPIE Position
| #define ADC_CMP1_CMPCH_Msk (0x1ful << ADC_CMP1_CMPCH_Pos) |
ADC_T::CMP1: CMPCH Mask
| #define ADC_CMP1_CMPCH_Pos (3) |
ADC_T::CMP1: CMPCH Position
| #define ADC_CMP1_CMPCOND_Msk (0x1ul << ADC_CMP1_CMPCOND_Pos) |
ADC_T::CMP1: CMPCOND Mask
| #define ADC_CMP1_CMPCOND_Pos (2) |
ADC_T::CMP1: CMPCOND Position
| #define ADC_CMP1_CMPDAT_Msk (0xffful << ADC_CMP1_CMPDAT_Pos) |
ADC_T::CMP1: CMPDAT Mask
| #define ADC_CMP1_CMPDAT_Pos (16) |
ADC_T::CMP1: CMPDAT Position
| #define ADC_CMP1_CMPMCNT_Msk (0xful << ADC_CMP1_CMPMCNT_Pos) |
ADC_T::CMP1: CMPMCNT Mask
| #define ADC_CMP1_CMPMCNT_Pos (8) |
ADC_T::CMP1: CMPMCNT Position
| #define ADC_CTL_ADCEN_Msk (0x1ul << ADC_CTL_ADCEN_Pos) |
ADC_T::CTL: ADCEN Mask
| #define ADC_CTL_ADCEN_Pos (0) |
ADC_T::CTL: ADCEN Position
| #define ADC_CTL_ADCIEN_Msk (0x1ul << ADC_CTL_ADCIEN_Pos) |
ADC_T::CTL: ADCIEN Mask
| #define ADC_CTL_ADCIEN_Pos (1) |
ADC_T::CTL: ADCIEN Position
| #define ADC_CTL_ADMD_Msk (0x3ul << ADC_CTL_ADMD_Pos) |
ADC_T::CTL: ADMD Mask
| #define ADC_CTL_ADMD_Pos (2) |
ADC_T::CTL: ADMD Position
| #define ADC_CTL_DIFF_Msk (0x1ul << ADC_CTL_DIFF_Pos) |
ADC_T::CTL: DIFF Mask
| #define ADC_CTL_DIFF_Pos (10) |
ADC_T::CTL: DIFF Position
| #define ADC_CTL_HWTRGCOND_Msk (0x3ul << ADC_CTL_HWTRGCOND_Pos) |
ADC_T::CTL: HWTRGCOND Mask
| #define ADC_CTL_HWTRGCOND_Pos (6) |
ADC_T::CTL: HWTRGCOND Position
| #define ADC_CTL_HWTRGEN_Msk (0x1ul << ADC_CTL_HWTRGEN_Pos) |
ADC_T::CTL: HWTRGEN Mask
| #define ADC_CTL_HWTRGEN_Pos (8) |
ADC_T::CTL: HWTRGEN Position
| #define ADC_CTL_HWTRGSEL_Msk (0x3ul << ADC_CTL_HWTRGSEL_Pos) |
ADC_T::CTL: HWTRGSEL Mask
| #define ADC_CTL_HWTRGSEL_Pos (4) |
ADC_T::CTL: HWTRGSEL Position
| #define ADC_CTL_PTEN_Msk (0x1ul << ADC_CTL_PTEN_Pos) |
ADC_T::CTL: PTEN Mask
| #define ADC_CTL_PTEN_Pos (9) |
ADC_T::CTL: PTEN Position
| #define ADC_CTL_REFSEL_Msk (0x3ul << ADC_CTL_REFSEL_Pos) |
ADC_T::CTL: REFSEL Mask
| #define ADC_CTL_REFSEL_Pos (16) |
ADC_T::CTL: REFSEL Position
| #define ADC_CTL_RESSEL_Msk (0x3ul << ADC_CTL_RESSEL_Pos) |
ADC_T::CTL: RESSEL Mask
| #define ADC_CTL_RESSEL_Pos (18) |
ADC_T::CTL: RESSEL Position
| #define ADC_CTL_SWTRG_Msk (0x1ul << ADC_CTL_SWTRG_Pos) |
ADC_T::CTL: SWTRG Mask
| #define ADC_CTL_SWTRG_Pos (11) |
ADC_T::CTL: SWTRG Position
| #define ADC_CTL_TMPDMACNT_Msk (0xfful << ADC_CTL_TMPDMACNT_Pos) |
ADC_T::CTL: TMPDMACNT Mask
| #define ADC_CTL_TMPDMACNT_Pos (24) |
ADC_T::CTL: TMPDMACNT Position
| #define ADC_CTL_TMSEL_Msk (0x3ul << ADC_CTL_TMSEL_Pos) |
ADC_T::CTL: TMSEL Mask
| #define ADC_CTL_TMSEL_Pos (12) |
ADC_T::CTL: TMSEL Position
| #define ADC_CTL_TMTRGMOD_Msk (0x1ul << ADC_CTL_TMTRGMOD_Pos) |
ADC_T::CTL: TMTRGMOD Mask
| #define ADC_CTL_TMTRGMOD_Pos (15) |
ADC_T::CTL: TMTRGMOD Position
| #define ADC_DAT0_OV_Msk (0x1ul << ADC_DAT0_OV_Pos) |
ADC_T::DAT: OV Mask
| #define ADC_DAT0_OV_Pos (17) |
ADC_T::DAT: OV Position
| #define ADC_DAT0_RESULT_Msk (0xffful << ADC_DAT0_RESULT_Pos) |
ADC_T::DAT: RESULT Mask
| #define ADC_DAT0_RESULT_Pos (0) |
@addtogroup ADC_CONST ADC Bit Field Definition Constant Definitions for ADC Controller
ADC_T::DAT: RESULT Position
| #define ADC_DAT0_VALID_Msk (0x1ul << ADC_DAT0_VALID_Pos) |
ADC_T::DAT: VALID Mask
| #define ADC_DAT0_VALID_Pos (16) |
ADC_T::DAT: VALID Position
| #define ADC_EXTSMPT0_EXTSMPT_CH0_Msk (0xful << ADC_EXTSMPT0_EXTSMPT_CH0_Pos) |
ADC_T::EXTSMPT0: EXTSMPT_CH0 Mask
| #define ADC_EXTSMPT0_EXTSMPT_CH0_Pos (0) |
ADC_T::EXTSMPT0: EXTSMPT_CH0 Position
| #define ADC_EXTSMPT0_EXTSMPT_CH1_Msk (0xful << ADC_EXTSMPT0_EXTSMPT_CH1_Pos) |
ADC_T::EXTSMPT0: EXTSMPT_CH1 Mask
| #define ADC_EXTSMPT0_EXTSMPT_CH1_Pos (4) |
ADC_T::EXTSMPT0: EXTSMPT_CH1 Position
| #define ADC_EXTSMPT0_EXTSMPT_CH2_Msk (0xful << ADC_EXTSMPT0_EXTSMPT_CH2_Pos) |
ADC_T::EXTSMPT0: EXTSMPT_CH2 Mask
| #define ADC_EXTSMPT0_EXTSMPT_CH2_Pos (8) |
ADC_T::EXTSMPT0: EXTSMPT_CH2 Position
| #define ADC_EXTSMPT0_EXTSMPT_CH3_Msk (0xful << ADC_EXTSMPT0_EXTSMPT_CH3_Pos) |
ADC_T::EXTSMPT0: EXTSMPT_CH3 Mask
| #define ADC_EXTSMPT0_EXTSMPT_CH3_Pos (12) |
ADC_T::EXTSMPT0: EXTSMPT_CH3 Position
| #define ADC_EXTSMPT0_EXTSMPT_CH4_Msk (0xful << ADC_EXTSMPT0_EXTSMPT_CH4_Pos) |
ADC_T::EXTSMPT0: EXTSMPT_CH4 Mask
| #define ADC_EXTSMPT0_EXTSMPT_CH4_Pos (16) |
ADC_T::EXTSMPT0: EXTSMPT_CH4 Position
| #define ADC_EXTSMPT0_EXTSMPT_CH5_Msk (0xful << ADC_EXTSMPT0_EXTSMPT_CH5_Pos) |
ADC_T::EXTSMPT0: EXTSMPT_CH5 Mask
| #define ADC_EXTSMPT0_EXTSMPT_CH5_Pos (20) |
ADC_T::EXTSMPT0: EXTSMPT_CH5 Position
| #define ADC_EXTSMPT0_EXTSMPT_CH6_Msk (0xful << ADC_EXTSMPT0_EXTSMPT_CH6_Pos) |
ADC_T::EXTSMPT0: EXTSMPT_CH6 Mask
| #define ADC_EXTSMPT0_EXTSMPT_CH6_Pos (24) |
ADC_T::EXTSMPT0: EXTSMPT_CH6 Position
| #define ADC_EXTSMPT0_EXTSMPT_CH7_Msk (0xful << ADC_EXTSMPT0_EXTSMPT_CH7_Pos) |
ADC_T::EXTSMPT0: EXTSMPT_CH7 Mask
| #define ADC_EXTSMPT0_EXTSMPT_CH7_Pos (28) |
ADC_T::EXTSMPT0: EXTSMPT_CH7 Position
| #define ADC_EXTSMPT1_EXTSMPT_INTCH_Msk (0xful << ADC_EXTSMPT1_EXTSMPT_INTCH_Pos) |
ADC_T::EXTSMPT1: EXTSMPT_INTCH Mask
| #define ADC_EXTSMPT1_EXTSMPT_INTCH_Pos (16) |
ADC_T::EXTSMPT1: EXTSMPT_INTCH Position
| #define ADC_PDMA_AD_PDMA_Msk (0xffful << ADC_PDMA_AD_PDMA_Pos) |
ADC_T::PDMA: AD_PDMA Mask
| #define ADC_PDMA_AD_PDMA_Pos (0) |
ADC_T::PDMA: AD_PDMA Position
| #define ADC_PWD_PWDCALEN_Msk (0x1ul << ADC_PWD_PWDCALEN_Pos) |
ADC_T::PWD: PWDCALEN Mask
| #define ADC_PWD_PWDCALEN_Pos (1) |
ADC_T::PWD: PWDCALEN Position
| #define ADC_PWD_PWDMOD_Msk (0x3ul << ADC_PWD_PWDMOD_Pos) |
ADC_T::PWD: PWDMOD Mask
| #define ADC_PWD_PWDMOD_Pos (2) |
ADC_T::PWD: PWDMOD Position
| #define ADC_PWD_PWUPRDY_Msk (0x1ul << ADC_PWD_PWUPRDY_Pos) |
ADC_T::PWD: PWUPRDY Mask
| #define ADC_PWD_PWUPRDY_Pos (0) |
ADC_T::PWD: PWUPRDY Position
| #define ADC_STATUS_ADCMPF0_Msk (0x1ul << ADC_STATUS_ADCMPF0_Pos) |
ADC_T::STATUS: ADCMPF0 Mask
| #define ADC_STATUS_ADCMPF0_Pos (1) |
ADC_T::STATUS: ADCMPF0 Position
| #define ADC_STATUS_ADCMPF1_Msk (0x1ul << ADC_STATUS_ADCMPF1_Pos) |
ADC_T::STATUS: ADCMPF1 Mask
| #define ADC_STATUS_ADCMPF1_Pos (2) |
ADC_T::STATUS: ADCMPF1 Position
| #define ADC_STATUS_ADIF_Msk (0x1ul << ADC_STATUS_ADIF_Pos) |
ADC_T::STATUS: ADIF Mask
| #define ADC_STATUS_ADIF_Pos (0) |
ADC_T::STATUS: ADIF Position
| #define ADC_STATUS_BUSY_Msk (0x1ul << ADC_STATUS_BUSY_Pos) |
ADC_T::STATUS: BUSY Mask
| #define ADC_STATUS_BUSY_Pos (3) |
ADC_T::STATUS: BUSY Position
| #define ADC_STATUS_CHANNEL_Msk (0x1ful << ADC_STATUS_CHANNEL_Pos) |
ADC_T::STATUS: CHANNEL Mask
| #define ADC_STATUS_CHANNEL_Pos (4) |
ADC_T::STATUS: CHANNEL Position
| #define ADC_STATUS_INITRDY_Msk (0x1ul << ADC_STATUS_INITRDY_Pos) |
ADC_T::STATUS: INITRDY Mask
| #define ADC_STATUS_INITRDY_Pos (16) |
ADC_T::STATUS: INITRDY Position
| #define CLK_AHBCLK_GPIOCKEN_Msk (0x1ul << CLK_AHBCLK_GPIOCKEN_Pos) |
CLK_T::AHBCLK: GPIOCKEN Mask
| #define CLK_AHBCLK_GPIOCKEN_Pos (0) |
CLK_T::AHBCLK: GPIOCKEN Position
| #define CLK_AHBCLK_ISPCKEN_Msk (0x1ul << CLK_AHBCLK_ISPCKEN_Pos) |
CLK_T::AHBCLK: ISPCKEN Mask
| #define CLK_AHBCLK_ISPCKEN_Pos (2) |
CLK_T::AHBCLK: ISPCKEN Position
| #define CLK_AHBCLK_PDMACKEN_Msk (0x1ul << CLK_AHBCLK_PDMACKEN_Pos) |
CLK_T::AHBCLK: PDMACKEN Mask
| #define CLK_AHBCLK_PDMACKEN_Pos (1) |
CLK_T::AHBCLK: PDMACKEN Position
| #define CLK_AHBCLK_SRAMCKEN_Msk (0x1ul << CLK_AHBCLK_SRAMCKEN_Pos) |
CLK_T::AHBCLK: SRAMCKEN Mask
| #define CLK_AHBCLK_SRAMCKEN_Pos (4) |
CLK_T::AHBCLK: SRAMCKEN Position
| #define CLK_AHBCLK_STCKEN_Msk (0x1ul << CLK_AHBCLK_STCKEN_Pos) |
CLK_T::AHBCLK: STCKEN Mask
| #define CLK_AHBCLK_STCKEN_Pos (5) |
CLK_T::AHBCLK: STCKEN Position
| #define CLK_APBCLK_ACMP0CKEN_Msk (0x1ul << CLK_APBCLK_ACMP0CKEN_Pos) |
CLK_T::APBCLK: ACMP0CKEN Mask
| #define CLK_APBCLK_ACMP0CKEN_Pos (11) |
CLK_T::APBCLK: ACMP0CKEN Position
| #define CLK_APBCLK_ADCCKEN_Msk (0x1ul << CLK_APBCLK_ADCCKEN_Pos) |
CLK_T::APBCLK: ADCCKEN Mask
| #define CLK_APBCLK_ADCCKEN_Pos (28) |
CLK_T::APBCLK: ADCCKEN Position
| #define CLK_APBCLK_CLKOCKEN_Msk (0x1ul << CLK_APBCLK_CLKOCKEN_Pos) |
CLK_T::APBCLK: CLKOCKEN Mask
| #define CLK_APBCLK_CLKOCKEN_Pos (6) |
CLK_T::APBCLK: CLKOCKEN Position
| #define CLK_APBCLK_I2C0CKEN_Msk (0x1ul << CLK_APBCLK_I2C0CKEN_Pos) |
CLK_T::APBCLK: I2C0CKEN Mask
| #define CLK_APBCLK_I2C0CKEN_Pos (8) |
CLK_T::APBCLK: I2C0CKEN Position
| #define CLK_APBCLK_I2C1CKEN_Msk (0x1ul << CLK_APBCLK_I2C1CKEN_Pos) |
CLK_T::APBCLK: I2C1CKEN Mask
| #define CLK_APBCLK_I2C1CKEN_Pos (9) |
CLK_T::APBCLK: I2C1CKEN Position
| #define CLK_APBCLK_PWM0CKEN_Msk (0x1ul << CLK_APBCLK_PWM0CKEN_Pos) |
CLK_T::APBCLK: PWM0CKEN Mask
| #define CLK_APBCLK_PWM0CKEN_Pos (20) |
CLK_T::APBCLK: PWM0CKEN Position
| #define CLK_APBCLK_RTCCKEN_Msk (0x1ul << CLK_APBCLK_RTCCKEN_Pos) |
CLK_T::APBCLK: RTCCKEN Mask
| #define CLK_APBCLK_RTCCKEN_Pos (1) |
CLK_T::APBCLK: RTCCKEN Position
| #define CLK_APBCLK_SC0CKEN_Msk (0x1ul << CLK_APBCLK_SC0CKEN_Pos) |
CLK_T::APBCLK: SC0CKEN Mask
| #define CLK_APBCLK_SC0CKEN_Pos (30) |
CLK_T::APBCLK: SC0CKEN Position
| #define CLK_APBCLK_SC1CKEN_Msk (0x1ul << CLK_APBCLK_SC1CKEN_Pos) |
CLK_T::APBCLK: SC1CKEN Mask
| #define CLK_APBCLK_SC1CKEN_Pos (31) |
CLK_T::APBCLK: SC1CKEN Position
| #define CLK_APBCLK_SPI0CKEN_Msk (0x1ul << CLK_APBCLK_SPI0CKEN_Pos) |
CLK_T::APBCLK: SPI0CKEN Mask
| #define CLK_APBCLK_SPI0CKEN_Pos (12) |
CLK_T::APBCLK: SPI0CKEN Position
| #define CLK_APBCLK_SPI1CKEN_Msk (0x1ul << CLK_APBCLK_SPI1CKEN_Pos) |
CLK_T::APBCLK: SPI1CKEN Mask
| #define CLK_APBCLK_SPI1CKEN_Pos (13) |
CLK_T::APBCLK: SPI1CKEN Position
| #define CLK_APBCLK_SPI2CKEN_Msk (0x1ul << CLK_APBCLK_SPI2CKEN_Pos) |
CLK_T::APBCLK: SPI2CKEN Mask
| #define CLK_APBCLK_SPI2CKEN_Pos (14) |
CLK_T::APBCLK: SPI2CKEN Position
| #define CLK_APBCLK_SPI3CKEN_Msk (0x1ul << CLK_APBCLK_SPI3CKEN_Pos) |
CLK_T::APBCLK: SPI3CKEN Mask
| #define CLK_APBCLK_SPI3CKEN_Pos (15) |
CLK_T::APBCLK: SPI3CKEN Position
| #define CLK_APBCLK_TMR0CKEN_Msk (0x1ul << CLK_APBCLK_TMR0CKEN_Pos) |
CLK_T::APBCLK: TMR0CKEN Mask
| #define CLK_APBCLK_TMR0CKEN_Pos (2) |
CLK_T::APBCLK: TMR0CKEN Position
| #define CLK_APBCLK_TMR1CKEN_Msk (0x1ul << CLK_APBCLK_TMR1CKEN_Pos) |
CLK_T::APBCLK: TMR1CKEN Mask
| #define CLK_APBCLK_TMR1CKEN_Pos (3) |
CLK_T::APBCLK: TMR1CKEN Position
| #define CLK_APBCLK_TMR2CKEN_Msk (0x1ul << CLK_APBCLK_TMR2CKEN_Pos) |
CLK_T::APBCLK: TMR2CKEN Mask
| #define CLK_APBCLK_TMR2CKEN_Pos (4) |
CLK_T::APBCLK: TMR2CKEN Position
| #define CLK_APBCLK_TMR3CKEN_Msk (0x1ul << CLK_APBCLK_TMR3CKEN_Pos) |
CLK_T::APBCLK: TMR3CKEN Mask
| #define CLK_APBCLK_TMR3CKEN_Pos (5) |
CLK_T::APBCLK: TMR3CKEN Position
| #define CLK_APBCLK_UART0CKEN_Msk (0x1ul << CLK_APBCLK_UART0CKEN_Pos) |
CLK_T::APBCLK: UART0CKEN Mask
| #define CLK_APBCLK_UART0CKEN_Pos (16) |
CLK_T::APBCLK: UART0CKEN Position
| #define CLK_APBCLK_UART1CKEN_Msk (0x1ul << CLK_APBCLK_UART1CKEN_Pos) |
CLK_T::APBCLK: UART1CKEN Mask
| #define CLK_APBCLK_UART1CKEN_Pos (17) |
CLK_T::APBCLK: UART1CKEN Position
| #define CLK_APBCLK_WDTCKEN_Msk (0x1ul << CLK_APBCLK_WDTCKEN_Pos) |
CLK_T::APBCLK: WDTCKEN Mask
| #define CLK_APBCLK_WDTCKEN_Pos (0) |
CLK_T::APBCLK: WDTCKEN Position
| #define CLK_APBDIV_APB0DIV_Msk (0x7ul << CLK_APBDIV_APB0DIV_Pos) |
CLK_T::APBDIV: APB0DIV Mask
| #define CLK_APBDIV_APB0DIV_Pos (0) |
CLK_T::APBDIV: APB0DIV Position
| #define CLK_APBDIV_APB1DIV_Msk (0x7ul << CLK_APBDIV_APB1DIV_Pos) |
CLK_T::APBDIV: APB1DIV Mask
| #define CLK_APBDIV_APB1DIV_Pos (4) |
CLK_T::APBDIV: APB1DIV Position
| #define CLK_CDLOWB_LOWERBD_Msk (0x7fful << CLK_CDLOWB_LOWERBD_Pos) |
CLK_T::CDLOWB: LOWERBD Mask
| #define CLK_CDLOWB_LOWERBD_Pos (0) |
CLK_T::CDLOWB: LOWERBD Position
| #define CLK_CDUPB_UPERBD_Msk (0x7fful << CLK_CDUPB_UPERBD_Pos) |
CLK_T::CDUPB: UPERBD Mask
| #define CLK_CDUPB_UPERBD_Pos (0) |
CLK_T::CDUPB: UPERBD Position
| #define CLK_CLKDCTL_HXTFDEN_Msk (0x1ul << CLK_CLKDCTL_HXTFDEN_Pos) |
CLK_T::CLKDCTL: HXTFDEN Mask
| #define CLK_CLKDCTL_HXTFDEN_Pos (0) |
CLK_T::CLKDCTL: HXTFDEN Position
| #define CLK_CLKDCTL_HXTFQDEN_Msk (0x1ul << CLK_CLKDCTL_HXTFQDEN_Pos) |
CLK_T::CLKDCTL: HXTFQDEN Mask
| #define CLK_CLKDCTL_HXTFQDEN_Pos (2) |
CLK_T::CLKDCTL: HXTFQDEN Position
| #define CLK_CLKDCTL_LXTFDEN_Msk (0x1ul << CLK_CLKDCTL_LXTFDEN_Pos) |
CLK_T::CLKDCTL: LXTFDEN Mask
| #define CLK_CLKDCTL_LXTFDEN_Pos (1) |
CLK_T::CLKDCTL: LXTFDEN Position
| #define CLK_CLKDIE_HXTFIEN_Msk (0x1ul << CLK_CLKDIE_HXTFIEN_Pos) |
CLK_T::CLKDIE: HXTFIEN Mask
| #define CLK_CLKDIE_HXTFIEN_Pos (0) |
CLK_T::CLKDIE: HXTFIEN Position
| #define CLK_CLKDIE_HXTFQIEN_Msk (0x1ul << CLK_CLKDIE_HXTFQIEN_Pos) |
CLK_T::CLKDIE: HXTFQIEN Mask
| #define CLK_CLKDIE_HXTFQIEN_Pos (2) |
CLK_T::CLKDIE: HXTFQIEN Position
| #define CLK_CLKDIE_LXTFIEN_Msk (0x1ul << CLK_CLKDIE_LXTFIEN_Pos) |
CLK_T::CLKDIE: LXTFIEN Mask
| #define CLK_CLKDIE_LXTFIEN_Pos (1) |
CLK_T::CLKDIE: LXTFIEN Position
| #define CLK_CLKDIV0_ADCDIV_Msk (0xfful << CLK_CLKDIV0_ADCDIV_Pos) |
CLK_T::CLKDIV0: ADCDIV Mask
| #define CLK_CLKDIV0_ADCDIV_Pos (16) |
CLK_T::CLKDIV0: ADCDIV Position
| #define CLK_CLKDIV0_HCLKDIV_Msk (0xful << CLK_CLKDIV0_HCLKDIV_Pos) |
CLK_T::CLKDIV0: HCLKDIV Mask
| #define CLK_CLKDIV0_HCLKDIV_Pos (0) |
CLK_T::CLKDIV0: HCLKDIV Position
| #define CLK_CLKDIV0_SC0DIV_Msk (0xful << CLK_CLKDIV0_SC0DIV_Pos) |
CLK_T::CLKDIV0: SC0DIV Mask
| #define CLK_CLKDIV0_SC0DIV_Pos (28) |
CLK_T::CLKDIV0: SC0DIV Position
| #define CLK_CLKDIV0_UART0DIV_Msk (0xful << CLK_CLKDIV0_UART0DIV_Pos) |
CLK_T::CLKDIV0: UART0DIV Mask
| #define CLK_CLKDIV0_UART0DIV_Pos (8) |
CLK_T::CLKDIV0: UART0DIV Position
| #define CLK_CLKDIV0_UART1DIV_Msk (0xful << CLK_CLKDIV0_UART1DIV_Pos) |
CLK_T::CLKDIV0: UART1DIV Mask
| #define CLK_CLKDIV0_UART1DIV_Pos (12) |
CLK_T::CLKDIV0: UART1DIV Position
| #define CLK_CLKDIV1_SC1DIV_Msk (0xful << CLK_CLKDIV1_SC1DIV_Pos) |
CLK_T::CLKDIV1: SC1DIV Mask
| #define CLK_CLKDIV1_SC1DIV_Pos (0) |
CLK_T::CLKDIV1: SC1DIV Position
| #define CLK_CLKDIV1_TMR0DIV_Msk (0xful << CLK_CLKDIV1_TMR0DIV_Pos) |
CLK_T::CLKDIV1: TMR0DIV Mask
| #define CLK_CLKDIV1_TMR0DIV_Pos (8) |
CLK_T::CLKDIV1: TMR0DIV Position
| #define CLK_CLKDIV1_TMR1DIV_Msk (0xful << CLK_CLKDIV1_TMR1DIV_Pos) |
CLK_T::CLKDIV1: TMR1DIV Mask
| #define CLK_CLKDIV1_TMR1DIV_Pos (12) |
CLK_T::CLKDIV1: TMR1DIV Position
| #define CLK_CLKDIV1_TMR2DIV_Msk (0xful << CLK_CLKDIV1_TMR2DIV_Pos) |
CLK_T::CLKDIV1: TMR2DIV Mask
| #define CLK_CLKDIV1_TMR2DIV_Pos (16) |
CLK_T::CLKDIV1: TMR2DIV Position
| #define CLK_CLKDIV1_TMR3DIV_Msk (0xful << CLK_CLKDIV1_TMR3DIV_Pos) |
CLK_T::CLKDIV1: TMR3DIV Mask
| #define CLK_CLKDIV1_TMR3DIV_Pos (20) |
CLK_T::CLKDIV1: TMR3DIV Position
| #define CLK_CLKDSTS_HXTFIF_Msk (0x1ul << CLK_CLKDSTS_HXTFIF_Pos) |
CLK_T::CLKDSTS: HXTFIF Mask
| #define CLK_CLKDSTS_HXTFIF_Pos (0) |
CLK_T::CLKDSTS: HXTFIF Position
| #define CLK_CLKDSTS_HXTFQIF_Msk (0x1ul << CLK_CLKDSTS_HXTFQIF_Pos) |
CLK_T::CLKDSTS: HXTFQIF Mask
| #define CLK_CLKDSTS_HXTFQIF_Pos (2) |
CLK_T::CLKDSTS: HXTFQIF Position
| #define CLK_CLKDSTS_LXTFIF_Msk (0x1ul << CLK_CLKDSTS_LXTFIF_Pos) |
CLK_T::CLKDSTS: LXTFIF Mask
| #define CLK_CLKDSTS_LXTFIF_Pos (1) |
CLK_T::CLKDSTS: LXTFIF Position
| #define CLK_CLKOCTL_CLKOEN_Msk (0x1ul << CLK_CLKOCTL_CLKOEN_Pos) |
CLK_T::CLKOCTL: CLKOEN Mask
| #define CLK_CLKOCTL_CLKOEN_Pos (4) |
CLK_T::CLKOCTL: CLKOEN Position
| #define CLK_CLKOCTL_DIV1EN_Msk (0x1ul << CLK_CLKOCTL_DIV1EN_Pos) |
CLK_T::CLKOCTL: DIV1EN Mask
| #define CLK_CLKOCTL_DIV1EN_Pos (5) |
CLK_T::CLKOCTL: DIV1EN Position
| #define CLK_CLKOCTL_FREQSEL_Msk (0xful << CLK_CLKOCTL_FREQSEL_Pos) |
CLK_T::CLKOCTL: FREQSEL Mask
| #define CLK_CLKOCTL_FREQSEL_Pos (0) |
CLK_T::CLKOCTL: FREQSEL Position
| #define CLK_CLKSEL0_HCLKSEL_Msk (0x7ul << CLK_CLKSEL0_HCLKSEL_Pos) |
CLK_T::CLKSEL0: HCLKSEL Mask
| #define CLK_CLKSEL0_HCLKSEL_Pos (0) |
CLK_T::CLKSEL0: HCLKSEL Position
| #define CLK_CLKSEL0_HIRCSEL_Msk (0x1ul << CLK_CLKSEL0_HIRCSEL_Pos) |
CLK_T::CLKSEL0: HIRCSEL Mask
| #define CLK_CLKSEL0_HIRCSEL_Pos (3) |
CLK_T::CLKSEL0: HIRCSEL Position
| #define CLK_CLKSEL0_ISPSEL_Msk (0x1ul << CLK_CLKSEL0_ISPSEL_Pos) |
CLK_T::CLKSEL0: ISPSEL Mask
| #define CLK_CLKSEL0_ISPSEL_Pos (4) |
CLK_T::CLKSEL0: ISPSEL Position
| #define CLK_CLKSEL1_ADCSEL_Msk (0x7ul << CLK_CLKSEL1_ADCSEL_Pos) |
CLK_T::CLKSEL1: ADCSEL Mask
| #define CLK_CLKSEL1_ADCSEL_Pos (19) |
CLK_T::CLKSEL1: ADCSEL Position
| #define CLK_CLKSEL1_PWM0SEL_Msk (0x1ul << CLK_CLKSEL1_PWM0SEL_Pos) |
CLK_T::CLKSEL1: PWM0SEL Mask
| #define CLK_CLKSEL1_PWM0SEL_Pos (4) |
CLK_T::CLKSEL1: PWM0SEL Position
| #define CLK_CLKSEL1_SPI0SEL_Msk (0x3ul << CLK_CLKSEL1_SPI0SEL_Pos) |
CLK_T::CLKSEL1: SPI0SEL Mask
| #define CLK_CLKSEL1_SPI0SEL_Pos (24) |
CLK_T::CLKSEL1: SPI0SEL Position
| #define CLK_CLKSEL1_SPI2SEL_Msk (0x3ul << CLK_CLKSEL1_SPI2SEL_Pos) |
CLK_T::CLKSEL1: SPI2SEL Mask
| #define CLK_CLKSEL1_SPI2SEL_Pos (26) |
CLK_T::CLKSEL1: SPI2SEL Position
| #define CLK_CLKSEL1_TMR0SEL_Msk (0x7ul << CLK_CLKSEL1_TMR0SEL_Pos) |
CLK_T::CLKSEL1: TMR0SEL Mask
| #define CLK_CLKSEL1_TMR0SEL_Pos (8) |
CLK_T::CLKSEL1: TMR0SEL Position
| #define CLK_CLKSEL1_TMR1SEL_Msk (0x7ul << CLK_CLKSEL1_TMR1SEL_Pos) |
CLK_T::CLKSEL1: TMR1SEL Mask
| #define CLK_CLKSEL1_TMR1SEL_Pos (12) |
CLK_T::CLKSEL1: TMR1SEL Position
| #define CLK_CLKSEL1_UART0SEL_Msk (0x7ul << CLK_CLKSEL1_UART0SEL_Pos) |
CLK_T::CLKSEL1: UART0SEL Mask
| #define CLK_CLKSEL1_UART0SEL_Pos (0) |
CLK_T::CLKSEL1: UART0SEL Position
| #define CLK_CLKSEL1_WDTSEL_Msk (0x3ul << CLK_CLKSEL1_WDTSEL_Pos) |
CLK_T::CLKSEL1: WDTSEL Mask
| #define CLK_CLKSEL1_WDTSEL_Pos (28) |
CLK_T::CLKSEL1: WDTSEL Position
| #define CLK_CLKSEL1_WWDTSEL_Msk (0x3ul << CLK_CLKSEL1_WWDTSEL_Pos) |
CLK_T::CLKSEL1: WWDTSEL Mask
| #define CLK_CLKSEL1_WWDTSEL_Pos (30) |
CLK_T::CLKSEL1: WWDTSEL Position
| #define CLK_CLKSEL2_CLKOSEL_Msk (0x7ul << CLK_CLKSEL2_CLKOSEL_Pos) |
CLK_T::CLKSEL2: CLKOSEL Mask
| #define CLK_CLKSEL2_CLKOSEL_Pos (4) |
CLK_T::CLKSEL2: CLKOSEL Position
| #define CLK_CLKSEL2_SC0SEL_Msk (0x7ul << CLK_CLKSEL2_SC0SEL_Pos) |
CLK_T::CLKSEL2: SC0SEL Mask
| #define CLK_CLKSEL2_SC0SEL_Pos (16) |
CLK_T::CLKSEL2: SC0SEL Position
| #define CLK_CLKSEL2_SC1SEL_Msk (0x7ul << CLK_CLKSEL2_SC1SEL_Pos) |
CLK_T::CLKSEL2: SC1SEL Mask
| #define CLK_CLKSEL2_SC1SEL_Pos (20) |
CLK_T::CLKSEL2: SC1SEL Position
| #define CLK_CLKSEL2_SPI1SEL_Msk (0x3ul << CLK_CLKSEL2_SPI1SEL_Pos) |
CLK_T::CLKSEL2: SPI1SEL Mask
| #define CLK_CLKSEL2_SPI1SEL_Pos (24) |
CLK_T::CLKSEL2: SPI1SEL Position
| #define CLK_CLKSEL2_SPI3SEL_Msk (0x3ul << CLK_CLKSEL2_SPI3SEL_Pos) |
CLK_T::CLKSEL2: SPI3SEL Mask
| #define CLK_CLKSEL2_SPI3SEL_Pos (26) |
CLK_T::CLKSEL2: SPI3SEL Position
| #define CLK_CLKSEL2_TMR2SEL_Msk (0x7ul << CLK_CLKSEL2_TMR2SEL_Pos) |
CLK_T::CLKSEL2: TMR2SEL Mask
| #define CLK_CLKSEL2_TMR2SEL_Pos (8) |
CLK_T::CLKSEL2: TMR2SEL Position
| #define CLK_CLKSEL2_TMR3SEL_Msk (0x7ul << CLK_CLKSEL2_TMR3SEL_Pos) |
CLK_T::CLKSEL2: TMR3SEL Mask
| #define CLK_CLKSEL2_TMR3SEL_Pos (12) |
CLK_T::CLKSEL2: TMR3SEL Position
| #define CLK_CLKSEL2_UART1SEL_Msk (0x7ul << CLK_CLKSEL2_UART1SEL_Pos) |
CLK_T::CLKSEL2: UART1SEL Mask
| #define CLK_CLKSEL2_UART1SEL_Pos (0) |
CLK_T::CLKSEL2: UART1SEL Position
| #define CLK_PLLCTL_INDIV_Msk (0x3ful << CLK_PLLCTL_INDIV_Pos) |
CLK_T::PLLCTL: INDIV Mask
| #define CLK_PLLCTL_INDIV_Pos (8) |
CLK_T::PLLCTL: INDIV Position
| #define CLK_PLLCTL_PD_Msk (0x1ul << CLK_PLLCTL_PD_Pos) |
CLK_T::PLLCTL: PD Mask
| #define CLK_PLLCTL_PD_Pos (16) |
CLK_T::PLLCTL: PD Position
| #define CLK_PLLCTL_PLLMLP_Msk (0x3ful << CLK_PLLCTL_PLLMLP_Pos) |
CLK_T::PLLCTL: PLLMLP Mask
| #define CLK_PLLCTL_PLLMLP_Pos (0) |
CLK_T::PLLCTL: PLLMLP Position
| #define CLK_PLLCTL_PLLSRC_Msk (0x3ul << CLK_PLLCTL_PLLSRC_Pos) |
CLK_T::PLLCTL: PLLSRC Mask
| #define CLK_PLLCTL_PLLSRC_Pos (17) |
CLK_T::PLLCTL: PLLSRC Position
| #define CLK_PLLCTL_STBTSEL_Msk (0x3ul << CLK_PLLCTL_STBTSEL_Pos) |
CLK_T::PLLCTL: STBTSEL Mask
| #define CLK_PLLCTL_STBTSEL_Pos (14) |
CLK_T::PLLCTL: STBTSEL Position
| #define CLK_PWRCTL_HIRC0EN_Msk (0x1ul << CLK_PWRCTL_HIRC0EN_Pos) |
CLK_T::PWRCTL: HIRC0EN Mask
| #define CLK_PWRCTL_HIRC0EN_Pos (2) |
CLK_T::PWRCTL: HIRC0EN Position
| #define CLK_PWRCTL_HIRC0FSEL_Msk (0x1ul << CLK_PWRCTL_HIRC0FSEL_Pos) |
CLK_T::PWRCTL: HIRC0FSEL Mask
| #define CLK_PWRCTL_HIRC0FSEL_Pos (13) |
CLK_T::PWRCTL: HIRC0FSEL Position
| #define CLK_PWRCTL_HIRC0FSTOP_Msk (0x1ul << CLK_PWRCTL_HIRC0FSTOP_Pos) |
CLK_T::PWRCTL: HIRC0FSTOP Mask
| #define CLK_PWRCTL_HIRC0FSTOP_Pos (14) |
CLK_T::PWRCTL: HIRC0FSTOP Position
| #define CLK_PWRCTL_HIRC1EN_Msk (0x1ul << CLK_PWRCTL_HIRC1EN_Pos) |
CLK_T::PWRCTL: HIRC1EN Mask
| #define CLK_PWRCTL_HIRC1EN_Pos (24) |
CLK_T::PWRCTL: HIRC1EN Position
| #define CLK_PWRCTL_HXTEN_Msk (0x1ul << CLK_PWRCTL_HXTEN_Pos) |
CLK_T::PWRCTL: HXTEN Mask
| #define CLK_PWRCTL_HXTEN_Pos (0) |
@addtogroup CLK_CONST CLK Bit Field Definition Constant Definitions for CLK Controller
CLK_T::PWRCTL: HXTEN Position
| #define CLK_PWRCTL_HXTGAIN_Msk (0x7ul << CLK_PWRCTL_HXTGAIN_Pos) |
CLK_T::PWRCTL: HXTGAIN Mask
| #define CLK_PWRCTL_HXTGAIN_Pos (10) |
CLK_T::PWRCTL: HXTGAIN Position
| #define CLK_PWRCTL_HXTSLTYP_Msk (0x1ul << CLK_PWRCTL_HXTSLTYP_Pos) |
CLK_T::PWRCTL: HXTSLTYP Mask
| #define CLK_PWRCTL_HXTSLTYP_Pos (8) |
CLK_T::PWRCTL: HXTSLTYP Position
| #define CLK_PWRCTL_LIRCEN_Msk (0x1ul << CLK_PWRCTL_LIRCEN_Pos) |
CLK_T::PWRCTL: LIRCEN Mask
| #define CLK_PWRCTL_LIRCEN_Pos (3) |
CLK_T::PWRCTL: LIRCEN Position
| #define CLK_PWRCTL_LXTEN_Msk (0x1ul << CLK_PWRCTL_LXTEN_Pos) |
CLK_T::PWRCTL: LXTEN Mask
| #define CLK_PWRCTL_LXTEN_Pos (1) |
CLK_T::PWRCTL: LXTEN Position
| #define CLK_PWRCTL_MIRCEN_Msk (0x1ul << CLK_PWRCTL_MIRCEN_Pos) |
CLK_T::PWRCTL: MIRCEN Mask
| #define CLK_PWRCTL_MIRCEN_Pos (25) |
CLK_T::PWRCTL: MIRCEN Position
| #define CLK_PWRCTL_PDEN_Msk (0x1ul << CLK_PWRCTL_PDEN_Pos) |
CLK_T::PWRCTL: PDEN Mask
| #define CLK_PWRCTL_PDEN_Pos (6) |
CLK_T::PWRCTL: PDEN Position
| #define CLK_PWRCTL_PDWKDLY_Msk (0x1ul << CLK_PWRCTL_PDWKDLY_Pos) |
CLK_T::PWRCTL: PDWKDLY Mask
| #define CLK_PWRCTL_PDWKDLY_Pos (4) |
CLK_T::PWRCTL: PDWKDLY Position
| #define CLK_PWRCTL_PDWKIEN_Msk (0x1ul << CLK_PWRCTL_PDWKIEN_Pos) |
CLK_T::PWRCTL: PDWKIEN Mask
| #define CLK_PWRCTL_PDWKIEN_Pos (5) |
CLK_T::PWRCTL: PDWKIEN Position
| #define CLK_STATUS_CLKSFAIL_Msk (0x1ul << CLK_STATUS_CLKSFAIL_Pos) |
CLK_T::STATUS: CLKSFAIL Mask
| #define CLK_STATUS_CLKSFAIL_Pos (7) |
CLK_T::STATUS: CLKSFAIL Position
| #define CLK_STATUS_HIRC0STB_Msk (0x1ul << CLK_STATUS_HIRC0STB_Pos) |
CLK_T::STATUS: HIRC0STB Mask
| #define CLK_STATUS_HIRC0STB_Pos (4) |
CLK_T::STATUS: HIRC0STB Position
| #define CLK_STATUS_HIRC1STB_Msk (0x1ul << CLK_STATUS_HIRC1STB_Pos) |
CLK_T::STATUS: HIRC1STB Mask
| #define CLK_STATUS_HIRC1STB_Pos (5) |
CLK_T::STATUS: HIRC1STB Position
| #define CLK_STATUS_HXTSTB_Msk (0x1ul << CLK_STATUS_HXTSTB_Pos) |
CLK_T::STATUS: HXTSTB Mask
| #define CLK_STATUS_HXTSTB_Pos (0) |
CLK_T::STATUS: HXTSTB Position
| #define CLK_STATUS_LIRCSTB_Msk (0x1ul << CLK_STATUS_LIRCSTB_Pos) |
CLK_T::STATUS: LIRCSTB Mask
| #define CLK_STATUS_LIRCSTB_Pos (3) |
CLK_T::STATUS: LIRCSTB Position
| #define CLK_STATUS_LXTSTB_Msk (0x1ul << CLK_STATUS_LXTSTB_Pos) |
CLK_T::STATUS: LXTSTB Mask
| #define CLK_STATUS_LXTSTB_Pos (1) |
CLK_T::STATUS: LXTSTB Position
| #define CLK_STATUS_MIRCSTB_Msk (0x1ul << CLK_STATUS_MIRCSTB_Pos) |
CLK_T::STATUS: MIRCSTB Mask
| #define CLK_STATUS_MIRCSTB_Pos (6) |
CLK_T::STATUS: MIRCSTB Position
| #define CLK_STATUS_PLLSTB_Msk (0x1ul << CLK_STATUS_PLLSTB_Pos) |
CLK_T::STATUS: PLLSTB Mask
| #define CLK_STATUS_PLLSTB_Pos (2) |
CLK_T::STATUS: PLLSTB Position
| #define CLK_WKINTSTS_PDWKIF_Msk (0x1ul << CLK_WKINTSTS_PDWKIF_Pos) |
CLK_T::WKINTSTS: PDWKIF Mask
| #define CLK_WKINTSTS_PDWKIF_Pos (0) |
CLK_T::WKINTSTS: PDWKIF Position
| #define DMA_CRC_CHECKSUM_CHECKSUM_Msk (0xfffffffful << DMA_CRC_CHECKSUM_CHECKSUM_Pos) |
DMA_CRC_T::CHECKSUM: CHECKSUM Mask
| #define DMA_CRC_CHECKSUM_CHECKSUM_Pos (0) |
DMA_CRC_T::CHECKSUM: CHECKSUM Position
| #define DMA_CRC_CTL_CHKSFMT_Msk (0x1ul << DMA_CRC_CTL_CHKSFMT_Pos) |
DMA_CRC_T::CTL: CHKSFMT Mask
| #define DMA_CRC_CTL_CHKSFMT_Pos (27) |
DMA_CRC_T::CTL: CHKSFMT Position
| #define DMA_CRC_CTL_CHKSREV_Msk (0x1ul << DMA_CRC_CTL_CHKSREV_Pos) |
DMA_CRC_T::CTL: CHKSREV Mask
| #define DMA_CRC_CTL_CHKSREV_Pos (25) |
DMA_CRC_T::CTL: CHKSREV Position
| #define DMA_CRC_CTL_CRCEN_Msk (0x1ul << DMA_CRC_CTL_CRCEN_Pos) |
DMA_CRC_T::CTL: CRCEN Mask
| #define DMA_CRC_CTL_CRCEN_Pos (0) |
@addtogroup CRC_CONST CRC Bit Field Definition Constant Definitions for CRC Controller
DMA_CRC_T::CTL: CRCEN Position
| #define DMA_CRC_CTL_CRCMODE_Msk (0x3ul << DMA_CRC_CTL_CRCMODE_Pos) |
DMA_CRC_T::CTL: CRCMODE Mask
| #define DMA_CRC_CTL_CRCMODE_Pos (30) |
DMA_CRC_T::CTL: CRCMODE Position
| #define DMA_CRC_CTL_CRCRST_Msk (0x1ul << DMA_CRC_CTL_CRCRST_Pos) |
DMA_CRC_T::CTL: CRCRST Mask
| #define DMA_CRC_CTL_CRCRST_Pos (1) |
DMA_CRC_T::CTL: CRCRST Position
| #define DMA_CRC_CTL_DATFMT_Msk (0x1ul << DMA_CRC_CTL_DATFMT_Pos) |
DMA_CRC_T::CTL: DATFMT Mask
| #define DMA_CRC_CTL_DATFMT_Pos (26) |
DMA_CRC_T::CTL: DATFMT Position
| #define DMA_CRC_CTL_DATLEN_Msk (0x3ul << DMA_CRC_CTL_DATLEN_Pos) |
DMA_CRC_T::CTL: DATLEN Mask
| #define DMA_CRC_CTL_DATLEN_Pos (28) |
DMA_CRC_T::CTL: DATLEN Position
| #define DMA_CRC_CTL_DATREV_Msk (0x1ul << DMA_CRC_CTL_DATREV_Pos) |
DMA_CRC_T::CTL: DATREV Mask
| #define DMA_CRC_CTL_DATREV_Pos (24) |
DMA_CRC_T::CTL: DATREV Position
| #define DMA_CRC_CTL_TRIGEN_Msk (0x1ul << DMA_CRC_CTL_TRIGEN_Pos) |
DMA_CRC_T::CTL: TRIGEN Mask
| #define DMA_CRC_CTL_TRIGEN_Pos (23) |
DMA_CRC_T::CTL: TRIGEN Position
| #define DMA_CRC_DAT_DATA_Msk (0xfffffffful << DMA_CRC_DAT_DATA_Pos) |
DMA_CRC_T::DAT: DATA Mask
| #define DMA_CRC_DAT_DATA_Pos (0) |
DMA_CRC_T::DAT: DATA Position
| #define DMA_CRC_DMABCNT_BCNT_Msk (0xfffful << DMA_CRC_DMABCNT_BCNT_Pos) |
DMA_CRC_T::DMABCNT: BCNT Mask
| #define DMA_CRC_DMABCNT_BCNT_Pos (0) |
DMA_CRC_T::DMABCNT: BCNT Position
| #define DMA_CRC_DMACBCNT_CBCNT_Msk (0xfffful << DMA_CRC_DMACBCNT_CBCNT_Pos) |
DMA_CRC_T::DMACBCNT: CBCNT Mask
| #define DMA_CRC_DMACBCNT_CBCNT_Pos (0) |
DMA_CRC_T::DMACBCNT: CBCNT Position
| #define DMA_CRC_DMACSA_CSA_Msk (0xfffffffful << DMA_CRC_DMACSA_CSA_Pos) |
DMA_CRC_T::DMACSA: CSA Mask
| #define DMA_CRC_DMACSA_CSA_Pos (0) |
DMA_CRC_T::DMACSA: CSA Position
| #define DMA_CRC_DMAINTEN_TABTIEN_Msk (0x1ul << DMA_CRC_DMAINTEN_TABTIEN_Pos) |
DMA_CRC_T::DMAINTEN: TABTIEN Mask
| #define DMA_CRC_DMAINTEN_TABTIEN_Pos (0) |
DMA_CRC_T::DMAINTEN: TABTIEN Position
| #define DMA_CRC_DMAINTEN_TDIEN_Msk (0x1ul << DMA_CRC_DMAINTEN_TDIEN_Pos) |
DMA_CRC_T::DMAINTEN: TDIEN Mask
| #define DMA_CRC_DMAINTEN_TDIEN_Pos (1) |
DMA_CRC_T::DMAINTEN: TDIEN Position
| #define DMA_CRC_DMAISTS_TABTIF_Msk (0x1ul << DMA_CRC_DMAISTS_TABTIF_Pos) |
DMA_CRC_T::DMAISTS: TABTIF Mask
| #define DMA_CRC_DMAISTS_TABTIF_Pos (0) |
DMA_CRC_T::DMAISTS: TABTIF Position
| #define DMA_CRC_DMAISTS_TDIF_Msk (0x1ul << DMA_CRC_DMAISTS_TDIF_Pos) |
DMA_CRC_T::DMAISTS: TDIF Mask
| #define DMA_CRC_DMAISTS_TDIF_Pos (1) |
DMA_CRC_T::DMAISTS: TDIF Position
| #define DMA_CRC_DMASA_SA_Msk (0xfffffffful << DMA_CRC_DMASA_SA_Pos) |
DMA_CRC_T::DMASA: SA Mask
| #define DMA_CRC_DMASA_SA_Pos (0) |
DMA_CRC_T::DMASA: SA Position
| #define DMA_CRC_SEED_SEED_Msk (0xfffffffful << DMA_CRC_SEED_SEED_Pos) |
DMA_CRC_T::SEED: SEED Mask
| #define DMA_CRC_SEED_SEED_Pos (0) |
DMA_CRC_T::SEED: SEED Position
| #define DMA_GCR_GCTL_CKEN1_Msk (0x1ul << DMA_GCR_GCTL_CKEN1_Pos) |
DMA_GCR_T::GCTL: CKEN1 Mask
| #define DMA_GCR_GCTL_CKEN1_Pos (9) |
@addtogroup PDMA_GCR_CONST PDMA_GCR Bit Field Definition Constant Definitions for PDMA_GCR Controller
DMA_GCR_T::GCTL: CKEN1 Position
| #define DMA_GCR_GCTL_CKEN2_Msk (0x1ul << DMA_GCR_GCTL_CKEN2_Pos) |
DMA_GCR_T::GCTL: CKEN2 Mask
| #define DMA_GCR_GCTL_CKEN2_Pos (10) |
DMA_GCR_T::GCTL: CKEN2 Position
| #define DMA_GCR_GCTL_CKEN3_Msk (0x1ul << DMA_GCR_GCTL_CKEN3_Pos) |
DMA_GCR_T::GCTL: CKEN3 Mask
| #define DMA_GCR_GCTL_CKEN3_Pos (11) |
DMA_GCR_T::GCTL: CKEN3 Position
| #define DMA_GCR_GCTL_CKEN4_Msk (0x1ul << DMA_GCR_GCTL_CKEN4_Pos) |
DMA_GCR_T::GCTL: CKEN4 Mask
| #define DMA_GCR_GCTL_CKEN4_Pos (12) |
DMA_GCR_T::GCTL: CKEN4 Position
| #define DMA_GCR_GCTL_CKENCRC_Msk (0x1ul << DMA_GCR_GCTL_CKENCRC_Pos) |
DMA_GCR_T::GCTL: CKENCRC Mask
| #define DMA_GCR_GCTL_CKENCRC_Pos (24) |
DMA_GCR_T::GCTL: CKENCRC Position
| #define DMA_GCR_GINTSTS_IF1_Msk (0x1ul << DMA_GCR_GINTSTS_IF1_Pos) |
DMA_GCR_T::GINTSTS: IF1 Mask
| #define DMA_GCR_GINTSTS_IF1_Pos (1) |
DMA_GCR_T::GINTSTS: IF1 Position
| #define DMA_GCR_GINTSTS_IF2_Msk (0x1ul << DMA_GCR_GINTSTS_IF2_Pos) |
DMA_GCR_T::GINTSTS: IF2 Mask
| #define DMA_GCR_GINTSTS_IF2_Pos (2) |
DMA_GCR_T::GINTSTS: IF2 Position
| #define DMA_GCR_GINTSTS_IF3_Msk (0x1ul << DMA_GCR_GINTSTS_IF3_Pos) |
DMA_GCR_T::GINTSTS: IF3 Mask
| #define DMA_GCR_GINTSTS_IF3_Pos (3) |
DMA_GCR_T::GINTSTS: IF3 Position
| #define DMA_GCR_GINTSTS_IF4_Msk (0x1ul << DMA_GCR_GINTSTS_IF4_Pos) |
DMA_GCR_T::GINTSTS: IF4 Mask
| #define DMA_GCR_GINTSTS_IF4_Pos (4) |
DMA_GCR_T::GINTSTS: IF4 Position
| #define DMA_GCR_GINTSTS_IFCRC_Msk (0x1ul << DMA_GCR_GINTSTS_IFCRC_Pos) |
DMA_GCR_T::GINTSTS: IFCRC Mask
| #define DMA_GCR_GINTSTS_IFCRC_Pos (16) |
DMA_GCR_T::GINTSTS: IFCRC Position
| #define DMA_GCR_REQSEL0_REQSRC1_Msk (0x1ful << DMA_GCR_REQSEL0_REQSRC1_Pos) |
DMA_GCR_T::REQSEL0: REQSRC1 Mask
| #define DMA_GCR_REQSEL0_REQSRC1_Pos (8) |
DMA_GCR_T::REQSEL0: REQSRC1 Position
| #define DMA_GCR_REQSEL0_REQSRC2_Msk (0x1ful << DMA_GCR_REQSEL0_REQSRC2_Pos) |
DMA_GCR_T::REQSEL0: REQSRC2 Mask
| #define DMA_GCR_REQSEL0_REQSRC2_Pos (16) |
DMA_GCR_T::REQSEL0: REQSRC2 Position
| #define DMA_GCR_REQSEL0_REQSRC3_Msk (0x1ful << DMA_GCR_REQSEL0_REQSRC3_Pos) |
DMA_GCR_T::REQSEL0: REQSRC3 Mask
| #define DMA_GCR_REQSEL0_REQSRC3_Pos (24) |
DMA_GCR_T::REQSEL0: REQSRC3 Position
| #define DMA_GCR_REQSEL1_REQSRC4_Msk (0x1ful << DMA_GCR_REQSEL1_REQSRC4_Pos) |
DMA_GCR_T::REQSEL1: REQSRC4 Mask
| #define DMA_GCR_REQSEL1_REQSRC4_Pos (0) |
DMA_GCR_T::REQSEL1: REQSRC4 Position
| #define FMC_DFBA_DFBA_Msk (0xfffffffful << FMC_DFBA_DFBA_Pos) |
FMC_T::DFBA: DFBA Mask
| #define FMC_DFBA_DFBA_Pos (0) |
FMC_T::DFBA: DFBA Position
| #define FMC_FTCTL_CACHEOFF_Msk (0x1ul << FMC_FTCTL_CACHEOFF_Pos) |
FMC_T::FTCTL: CACHEOFF Mask
| #define FMC_FTCTL_CACHEOFF_Pos (7) |
FMC_T::FTCTL: CACHEOFF Position
| #define FMC_FTCTL_FOM_Msk (0x7ul << FMC_FTCTL_FOM_Pos) |
FMC_T::FTCTL: FOM Mask
| #define FMC_FTCTL_FOM_Pos (4) |
FMC_T::FTCTL: FOM Position
| #define FMC_ISPADDR_ISPADDR_Msk (0xfffffffful << FMC_ISPADDR_ISPADDR_Pos) |
FMC_T::ISPADDR: ISPADDR Mask
| #define FMC_ISPADDR_ISPADDR_Pos (0) |
FMC_T::ISPADDR: ISPADDR Position
| #define FMC_ISPCMD_CMD_Msk (0x3ful << FMC_ISPCMD_CMD_Pos) |
FMC_T::ISPCMD: CMD Mask
| #define FMC_ISPCMD_CMD_Pos (0) |
FMC_T::ISPCMD: CMD Position
| #define FMC_ISPCTL_APUEN_Msk (0x1ul << FMC_ISPCTL_APUEN_Pos) |
FMC_T::ISPCTL: APUEN Mask
| #define FMC_ISPCTL_APUEN_Pos (3) |
FMC_T::ISPCTL: APUEN Position
| #define FMC_ISPCTL_BS_Msk (0x1ul << FMC_ISPCTL_BS_Pos) |
FMC_T::ISPCTL: BS Mask
| #define FMC_ISPCTL_BS_Pos (1) |
FMC_T::ISPCTL: BS Position
| #define FMC_ISPCTL_CFGUEN_Msk (0x1ul << FMC_ISPCTL_CFGUEN_Pos) |
FMC_T::ISPCTL: CFGUEN Mask
| #define FMC_ISPCTL_CFGUEN_Pos (4) |
FMC_T::ISPCTL: CFGUEN Position
| #define FMC_ISPCTL_ISPEN_Msk (0x1ul << FMC_ISPCTL_ISPEN_Pos) |
FMC_T::ISPCTL: ISPEN Mask
| #define FMC_ISPCTL_ISPEN_Pos (0) |
@addtogroup FMC_CONST FMC Bit Field Definition Constant Definitions for FMC Controller
FMC_T::ISPCTL: ISPEN Position
| #define FMC_ISPCTL_ISPFF_Msk (0x1ul << FMC_ISPCTL_ISPFF_Pos) |
FMC_T::ISPCTL: ISPFF Mask
| #define FMC_ISPCTL_ISPFF_Pos (6) |
FMC_T::ISPCTL: ISPFF Position
| #define FMC_ISPCTL_LDUEN_Msk (0x1ul << FMC_ISPCTL_LDUEN_Pos) |
FMC_T::ISPCTL: LDUEN Mask
| #define FMC_ISPCTL_LDUEN_Pos (5) |
FMC_T::ISPCTL: LDUEN Position
| #define FMC_ISPDAT_ISPDAT_Msk (0xfffffffful << FMC_ISPDAT_ISPDAT_Pos) |
FMC_T::ISPDAT: ISPDAT Mask
| #define FMC_ISPDAT_ISPDAT_Pos (0) |
FMC_T::ISPDAT: ISPDAT Position
| #define FMC_ISPSTS_ALLONE_Msk (0x1ul << FMC_ISPSTS_ALLONE_Pos) |
FMC_T::ISPSTS: ALLONE Mask
| #define FMC_ISPSTS_ALLONE_Pos (7) |
FMC_T::ISPSTS: ALLONE Position
| #define FMC_ISPSTS_CBS_Msk (0x3ul << FMC_ISPSTS_CBS_Pos) |
FMC_T::ISPSTS: CBS Mask
| #define FMC_ISPSTS_CBS_Pos (1) |
FMC_T::ISPSTS: CBS Position
| #define FMC_ISPSTS_ISPBUSY_Msk (0x1ul << FMC_ISPSTS_ISPBUSY_Pos) |
FMC_T::ISPSTS: ISPBUSY Mask
| #define FMC_ISPSTS_ISPBUSY_Pos (0) |
FMC_T::ISPSTS: ISPBUSY Position
| #define FMC_ISPSTS_ISPFF_Msk (0x1ul << FMC_ISPSTS_ISPFF_Pos) |
FMC_T::ISPSTS: ISPFF Mask
| #define FMC_ISPSTS_ISPFF_Pos (6) |
FMC_T::ISPSTS: ISPFF Position
| #define FMC_ISPSTS_PGFF_Msk (0x1ul << FMC_ISPSTS_PGFF_Pos) |
FMC_T::ISPSTS: PGFF Mask
| #define FMC_ISPSTS_PGFF_Pos (5) |
FMC_T::ISPSTS: PGFF Position
| #define FMC_ISPSTS_VECMAP_Msk (0x1ffffful << FMC_ISPSTS_VECMAP_Pos) |
FMC_T::ISPSTS: VECMAP Mask
| #define FMC_ISPSTS_VECMAP_Pos (9) |
FMC_T::ISPSTS: VECMAP Position
| #define FMC_ISPTRG_ISPGO_Msk (0x1ul << FMC_ISPTRG_ISPGO_Pos) |
FMC_T::ISPTRG: ISPGO Mask
| #define FMC_ISPTRG_ISPGO_Pos (0) |
FMC_T::ISPTRG: ISPGO Position
| #define FMC_KECNT_KECNT_Msk (0x3ful << FMC_KECNT_KECNT_Pos) |
FMC_T::KECNT: KECNT Mask
| #define FMC_KECNT_KECNT_Pos (0) |
FMC_T::KECNT: KECNT Position
| #define FMC_KECNT_KEMAX_Msk (0x3ful << FMC_KECNT_KEMAX_Pos) |
FMC_T::KECNT: KEMAX Mask
| #define FMC_KECNT_KEMAX_Pos (8) |
FMC_T::KECNT: KEMAX Position
| #define FMC_KEY0_KEY0_Msk (0xfffffffful << FMC_KEY0_KEY0_Pos) |
FMC_T::KEY0: KEY0 Mask
| #define FMC_KEY0_KEY0_Pos (0) |
FMC_T::KEY0: KEY0 Position
| #define FMC_KEY1_KEY1_Msk (0xfffffffful << FMC_KEY1_KEY1_Pos) |
FMC_T::KEY1: KEY1 Mask
| #define FMC_KEY1_KEY1_Pos (0) |
FMC_T::KEY1: KEY1 Position
| #define FMC_KEY2_KEY2_Msk (0xfffffffful << FMC_KEY2_KEY2_Pos) |
FMC_T::KEY2: KEY2 Mask
| #define FMC_KEY2_KEY2_Pos (0) |
FMC_T::KEY2: KEY2 Position
| #define FMC_KEYSTS_CFGFLAG_Msk (0x1ul << FMC_KEYSTS_CFGFLAG_Pos) |
FMC_T::KEYSTS: CFGFLAG Mask
| #define FMC_KEYSTS_CFGFLAG_Pos (5) |
FMC_T::KEYSTS: CFGFLAG Position
| #define FMC_KEYSTS_FORBID_Msk (0x1ul << FMC_KEYSTS_FORBID_Pos) |
FMC_T::KEYSTS: FORBID Mask
| #define FMC_KEYSTS_FORBID_Pos (3) |
FMC_T::KEYSTS: FORBID Position
| #define FMC_KEYSTS_KEYBUSY_Msk (0x1ul << FMC_KEYSTS_KEYBUSY_Pos) |
FMC_T::KEYSTS: KEYBUSY Mask
| #define FMC_KEYSTS_KEYBUSY_Pos (0) |
FMC_T::KEYSTS: KEYBUSY Position
| #define FMC_KEYSTS_KEYFLAG_Msk (0x1ul << FMC_KEYSTS_KEYFLAG_Pos) |
FMC_T::KEYSTS: KEYFLAG Mask
| #define FMC_KEYSTS_KEYFLAG_Pos (4) |
FMC_T::KEYSTS: KEYFLAG Position
| #define FMC_KEYSTS_KEYLOCK_Msk (0x1ul << FMC_KEYSTS_KEYLOCK_Pos) |
FMC_T::KEYSTS: KEYLOCK Mask
| #define FMC_KEYSTS_KEYLOCK_Pos (1) |
FMC_T::KEYSTS: KEYLOCK Position
| #define FMC_KEYSTS_KEYMATCH_Msk (0x1ul << FMC_KEYSTS_KEYMATCH_Pos) |
FMC_T::KEYSTS: KEYMATCH Mask
| #define FMC_KEYSTS_KEYMATCH_Pos (2) |
FMC_T::KEYSTS: KEYMATCH Position
| #define FMC_KEYTRG_KEYGO_Msk (0x1ul << FMC_KEYTRG_KEYGO_Pos) |
FMC_T::KEYTRG: KEYGO Mask
| #define FMC_KEYTRG_KEYGO_Pos (0) |
FMC_T::KEYTRG: KEYGO Position
| #define FMC_KEYTRG_TCEN_Msk (0x1ul << FMC_KEYTRG_TCEN_Pos) |
FMC_T::KEYTRG: TCEN Mask
| #define FMC_KEYTRG_TCEN_Pos (1) |
FMC_T::KEYTRG: TCEN Position
| #define FMC_KPCNT_KPCNT_Msk (0xful << FMC_KPCNT_KPCNT_Pos) |
FMC_T::KPCNT: KPCNT Mask
| #define FMC_KPCNT_KPCNT_Pos (0) |
FMC_T::KPCNT: KPCNT Position
| #define FMC_KPCNT_KPMAX_Msk (0xful << FMC_KPCNT_KPMAX_Pos) |
FMC_T::KPCNT: KPMAX Mask
| #define FMC_KPCNT_KPMAX_Pos (8) |
FMC_T::KPCNT: KPMAX Position
| #define GPIO_DATMSK_DMASK0_Msk (0x1ul << GPIO_DATMSK_DMASK0_Pos) |
GPIO_T::DATMSK: DMASK0 Mask
| #define GPIO_DATMSK_DMASK0_Pos (0) |
GPIO_T::DATMSK: DMASK0 Position
| #define GPIO_DATMSK_DMASK10_Msk (0x1ul << GPIO_DATMSK_DMASK10_Pos) |
GPIO_T::DATMSK: DMASK10 Mask
| #define GPIO_DATMSK_DMASK10_Pos (10) |
GPIO_T::DATMSK: DMASK10 Position
| #define GPIO_DATMSK_DMASK11_Msk (0x1ul << GPIO_DATMSK_DMASK11_Pos) |
GPIO_T::DATMSK: DMASK11 Mask
| #define GPIO_DATMSK_DMASK11_Pos (11) |
GPIO_T::DATMSK: DMASK11 Position
| #define GPIO_DATMSK_DMASK12_Msk (0x1ul << GPIO_DATMSK_DMASK12_Pos) |
GPIO_T::DATMSK: DMASK12 Mask
| #define GPIO_DATMSK_DMASK12_Pos (12) |
GPIO_T::DATMSK: DMASK12 Position
| #define GPIO_DATMSK_DMASK13_Msk (0x1ul << GPIO_DATMSK_DMASK13_Pos) |
GPIO_T::DATMSK: DMASK13 Mask
| #define GPIO_DATMSK_DMASK13_Pos (13) |
GPIO_T::DATMSK: DMASK13 Position
| #define GPIO_DATMSK_DMASK14_Msk (0x1ul << GPIO_DATMSK_DMASK14_Pos) |
GPIO_T::DATMSK: DMASK14 Mask
| #define GPIO_DATMSK_DMASK14_Pos (14) |
GPIO_T::DATMSK: DMASK14 Position
| #define GPIO_DATMSK_DMASK15_Msk (0x1ul << GPIO_DATMSK_DMASK15_Pos) |
GPIO_T::DATMSK: DMASK15 Mask
| #define GPIO_DATMSK_DMASK15_Pos (15) |
GPIO_T::DATMSK: DMASK15 Position
| #define GPIO_DATMSK_DMASK1_Msk (0x1ul << GPIO_DATMSK_DMASK1_Pos) |
GPIO_T::DATMSK: DMASK1 Mask
| #define GPIO_DATMSK_DMASK1_Pos (1) |
GPIO_T::DATMSK: DMASK1 Position
| #define GPIO_DATMSK_DMASK2_Msk (0x1ul << GPIO_DATMSK_DMASK2_Pos) |
GPIO_T::DATMSK: DMASK2 Mask
| #define GPIO_DATMSK_DMASK2_Pos (2) |
GPIO_T::DATMSK: DMASK2 Position
| #define GPIO_DATMSK_DMASK3_Msk (0x1ul << GPIO_DATMSK_DMASK3_Pos) |
GPIO_T::DATMSK: DMASK3 Mask
| #define GPIO_DATMSK_DMASK3_Pos (3) |
GPIO_T::DATMSK: DMASK3 Position
| #define GPIO_DATMSK_DMASK4_Msk (0x1ul << GPIO_DATMSK_DMASK4_Pos) |
GPIO_T::DATMSK: DMASK4 Mask
| #define GPIO_DATMSK_DMASK4_Pos (4) |
GPIO_T::DATMSK: DMASK4 Position
| #define GPIO_DATMSK_DMASK5_Msk (0x1ul << GPIO_DATMSK_DMASK5_Pos) |
GPIO_T::DATMSK: DMASK5 Mask
| #define GPIO_DATMSK_DMASK5_Pos (5) |
GPIO_T::DATMSK: DMASK5 Position
| #define GPIO_DATMSK_DMASK6_Msk (0x1ul << GPIO_DATMSK_DMASK6_Pos) |
GPIO_T::DATMSK: DMASK6 Mask
| #define GPIO_DATMSK_DMASK6_Pos (6) |
GPIO_T::DATMSK: DMASK6 Position
| #define GPIO_DATMSK_DMASK7_Msk (0x1ul << GPIO_DATMSK_DMASK7_Pos) |
GPIO_T::DATMSK: DMASK7 Mask
| #define GPIO_DATMSK_DMASK7_Pos (7) |
GPIO_T::DATMSK: DMASK7 Position
| #define GPIO_DATMSK_DMASK8_Msk (0x1ul << GPIO_DATMSK_DMASK8_Pos) |
GPIO_T::DATMSK: DMASK8 Mask
| #define GPIO_DATMSK_DMASK8_Pos (8) |
GPIO_T::DATMSK: DMASK8 Position
| #define GPIO_DATMSK_DMASK9_Msk (0x1ul << GPIO_DATMSK_DMASK9_Pos) |
GPIO_T::DATMSK: DMASK9 Mask
| #define GPIO_DATMSK_DMASK9_Pos (9) |
GPIO_T::DATMSK: DMASK9 Position
| #define GPIO_DBCTL_DBCLKSEL_Msk (0xful << GPIO_DBCTL_DBCLKSEL_Pos) |
GP_DB_T::DBCTL: DBCLKSEL Mask
| #define GPIO_DBCTL_DBCLKSEL_Pos (0) |
GP_DB_T::DBCTL: DBCLKSEL Position
| #define GPIO_DBCTL_DBCLKSRC_Msk (0x1ul << GPIO_DBCTL_DBCLKSRC_Pos) |
GP_DB_T::DBCTL: DBCLKSRC Mask
| #define GPIO_DBCTL_DBCLKSRC_Pos (4) |
GP_DB_T::DBCTL: DBCLKSRC Position
| #define GPIO_DBCTL_ICLKON_Msk (0x1ul << GPIO_DBCTL_ICLKON_Pos) |
GP_DB_T::DBCTL: ICLKON Mask
| #define GPIO_DBCTL_ICLKON_Pos (5) |
GP_DB_T::DBCTL: ICLKON Position
| #define GPIO_DBEN_DBEN0_Msk (0x1ul << GPIO_DBEN_DBEN0_Pos) |
GPIO_T::DBEN: DBEN0 Mask
| #define GPIO_DBEN_DBEN0_Pos (0) |
GPIO_T::DBEN: DBEN0 Position
| #define GPIO_DBEN_DBEN10_Msk (0x1ul << GPIO_DBEN_DBEN10_Pos) |
GPIO_T::DBEN: DBEN10 Mask
| #define GPIO_DBEN_DBEN10_Pos (10) |
GPIO_T::DBEN: DBEN10 Position
| #define GPIO_DBEN_DBEN11_Msk (0x1ul << GPIO_DBEN_DBEN11_Pos) |
GPIO_T::DBEN: DBEN11 Mask
| #define GPIO_DBEN_DBEN11_Pos (11) |
GPIO_T::DBEN: DBEN11 Position
| #define GPIO_DBEN_DBEN12_Msk (0x1ul << GPIO_DBEN_DBEN12_Pos) |
GPIO_T::DBEN: DBEN12 Mask
| #define GPIO_DBEN_DBEN12_Pos (12) |
GPIO_T::DBEN: DBEN12 Position
| #define GPIO_DBEN_DBEN13_Msk (0x1ul << GPIO_DBEN_DBEN13_Pos) |
GPIO_T::DBEN: DBEN13 Mask
| #define GPIO_DBEN_DBEN13_Pos (13) |
GPIO_T::DBEN: DBEN13 Position
| #define GPIO_DBEN_DBEN14_Msk (0x1ul << GPIO_DBEN_DBEN14_Pos) |
GPIO_T::DBEN: DBEN14 Mask
| #define GPIO_DBEN_DBEN14_Pos (14) |
GPIO_T::DBEN: DBEN14 Position
| #define GPIO_DBEN_DBEN15_Msk (0x1ul << GPIO_DBEN_DBEN15_Pos) |
GPIO_T::DBEN: DBEN15 Mask
| #define GPIO_DBEN_DBEN15_Pos (15) |
GPIO_T::DBEN: DBEN15 Position
| #define GPIO_DBEN_DBEN1_Msk (0x1ul << GPIO_DBEN_DBEN1_Pos) |
GPIO_T::DBEN: DBEN1 Mask
| #define GPIO_DBEN_DBEN1_Pos (1) |
GPIO_T::DBEN: DBEN1 Position
| #define GPIO_DBEN_DBEN2_Msk (0x1ul << GPIO_DBEN_DBEN2_Pos) |
GPIO_T::DBEN: DBEN2 Mask
| #define GPIO_DBEN_DBEN2_Pos (2) |
GPIO_T::DBEN: DBEN2 Position
| #define GPIO_DBEN_DBEN3_Msk (0x1ul << GPIO_DBEN_DBEN3_Pos) |
GPIO_T::DBEN: DBEN3 Mask
| #define GPIO_DBEN_DBEN3_Pos (3) |
GPIO_T::DBEN: DBEN3 Position
| #define GPIO_DBEN_DBEN4_Msk (0x1ul << GPIO_DBEN_DBEN4_Pos) |
GPIO_T::DBEN: DBEN4 Mask
| #define GPIO_DBEN_DBEN4_Pos (4) |
GPIO_T::DBEN: DBEN4 Position
| #define GPIO_DBEN_DBEN5_Msk (0x1ul << GPIO_DBEN_DBEN5_Pos) |
GPIO_T::DBEN: DBEN5 Mask
| #define GPIO_DBEN_DBEN5_Pos (5) |
GPIO_T::DBEN: DBEN5 Position
| #define GPIO_DBEN_DBEN6_Msk (0x1ul << GPIO_DBEN_DBEN6_Pos) |
GPIO_T::DBEN: DBEN6 Mask
| #define GPIO_DBEN_DBEN6_Pos (6) |
GPIO_T::DBEN: DBEN6 Position
| #define GPIO_DBEN_DBEN7_Msk (0x1ul << GPIO_DBEN_DBEN7_Pos) |
GPIO_T::DBEN: DBEN7 Mask
| #define GPIO_DBEN_DBEN7_Pos (7) |
GPIO_T::DBEN: DBEN7 Position
| #define GPIO_DBEN_DBEN8_Msk (0x1ul << GPIO_DBEN_DBEN8_Pos) |
GPIO_T::DBEN: DBEN8 Mask
| #define GPIO_DBEN_DBEN8_Pos (8) |
GPIO_T::DBEN: DBEN8 Position
| #define GPIO_DBEN_DBEN9_Msk (0x1ul << GPIO_DBEN_DBEN9_Pos) |
GPIO_T::DBEN: DBEN9 Mask
| #define GPIO_DBEN_DBEN9_Pos (9) |
GPIO_T::DBEN: DBEN9 Position
| #define GPIO_DINOFF_DINOFF0_Msk (0x1ul << GPIO_DINOFF_DINOFF0_Pos) |
GPIO_T::DINOFF: DINOFF0 Mask
| #define GPIO_DINOFF_DINOFF0_Pos (16) |
GPIO_T::DINOFF: DINOFF0 Position
| #define GPIO_DINOFF_DINOFF10_Msk (0x1ul << GPIO_DINOFF_DINOFF10_Pos) |
GPIO_T::DINOFF: DINOFF10 Mask
| #define GPIO_DINOFF_DINOFF10_Pos (26) |
GPIO_T::DINOFF: DINOFF10 Position
| #define GPIO_DINOFF_DINOFF11_Msk (0x1ul << GPIO_DINOFF_DINOFF11_Pos) |
GPIO_T::DINOFF: DINOFF11 Mask
| #define GPIO_DINOFF_DINOFF11_Pos (27) |
GPIO_T::DINOFF: DINOFF11 Position
| #define GPIO_DINOFF_DINOFF12_Msk (0x1ul << GPIO_DINOFF_DINOFF12_Pos) |
GPIO_T::DINOFF: DINOFF12 Mask
| #define GPIO_DINOFF_DINOFF12_Pos (28) |
GPIO_T::DINOFF: DINOFF12 Position
| #define GPIO_DINOFF_DINOFF13_Msk (0x1ul << GPIO_DINOFF_DINOFF13_Pos) |
GPIO_T::DINOFF: DINOFF13 Mask
| #define GPIO_DINOFF_DINOFF13_Pos (29) |
GPIO_T::DINOFF: DINOFF13 Position
| #define GPIO_DINOFF_DINOFF14_Msk (0x1ul << GPIO_DINOFF_DINOFF14_Pos) |
GPIO_T::DINOFF: DINOFF14 Mask
| #define GPIO_DINOFF_DINOFF14_Pos (30) |
GPIO_T::DINOFF: DINOFF14 Position
| #define GPIO_DINOFF_DINOFF15_Msk (0x1ul << GPIO_DINOFF_DINOFF15_Pos) |
GPIO_T::DINOFF: DINOFF15 Mask
| #define GPIO_DINOFF_DINOFF15_Pos (31) |
GPIO_T::DINOFF: DINOFF15 Position
| #define GPIO_DINOFF_DINOFF1_Msk (0x1ul << GPIO_DINOFF_DINOFF1_Pos) |
GPIO_T::DINOFF: DINOFF1 Mask
| #define GPIO_DINOFF_DINOFF1_Pos (17) |
GPIO_T::DINOFF: DINOFF1 Position
| #define GPIO_DINOFF_DINOFF2_Msk (0x1ul << GPIO_DINOFF_DINOFF2_Pos) |
GPIO_T::DINOFF: DINOFF2 Mask
| #define GPIO_DINOFF_DINOFF2_Pos (18) |
GPIO_T::DINOFF: DINOFF2 Position
| #define GPIO_DINOFF_DINOFF3_Msk (0x1ul << GPIO_DINOFF_DINOFF3_Pos) |
GPIO_T::DINOFF: DINOFF3 Mask
| #define GPIO_DINOFF_DINOFF3_Pos (19) |
GPIO_T::DINOFF: DINOFF3 Position
| #define GPIO_DINOFF_DINOFF4_Msk (0x1ul << GPIO_DINOFF_DINOFF4_Pos) |
GPIO_T::DINOFF: DINOFF4 Mask
| #define GPIO_DINOFF_DINOFF4_Pos (20) |
GPIO_T::DINOFF: DINOFF4 Position
| #define GPIO_DINOFF_DINOFF5_Msk (0x1ul << GPIO_DINOFF_DINOFF5_Pos) |
GPIO_T::DINOFF: DINOFF5 Mask
| #define GPIO_DINOFF_DINOFF5_Pos (21) |
GPIO_T::DINOFF: DINOFF5 Position
| #define GPIO_DINOFF_DINOFF6_Msk (0x1ul << GPIO_DINOFF_DINOFF6_Pos) |
GPIO_T::DINOFF: DINOFF6 Mask
| #define GPIO_DINOFF_DINOFF6_Pos (22) |
GPIO_T::DINOFF: DINOFF6 Position
| #define GPIO_DINOFF_DINOFF7_Msk (0x1ul << GPIO_DINOFF_DINOFF7_Pos) |
GPIO_T::DINOFF: DINOFF7 Mask
| #define GPIO_DINOFF_DINOFF7_Pos (23) |
GPIO_T::DINOFF: DINOFF7 Position
| #define GPIO_DINOFF_DINOFF8_Msk (0x1ul << GPIO_DINOFF_DINOFF8_Pos) |
GPIO_T::DINOFF: DINOFF8 Mask
| #define GPIO_DINOFF_DINOFF8_Pos (24) |
GPIO_T::DINOFF: DINOFF8 Position
| #define GPIO_DINOFF_DINOFF9_Msk (0x1ul << GPIO_DINOFF_DINOFF9_Pos) |
GPIO_T::DINOFF: DINOFF9 Mask
| #define GPIO_DINOFF_DINOFF9_Pos (25) |
GPIO_T::DINOFF: DINOFF9 Position
| #define GPIO_DOUT_DOUT0_Msk (0x1ul << GPIO_DOUT_DOUT0_Pos) |
GPIO_T::DOUT: DOUT0 Mask
| #define GPIO_DOUT_DOUT0_Pos (0) |
GPIO_T::DOUT: DOUT0 Position
| #define GPIO_DOUT_DOUT10_Msk (0x1ul << GPIO_DOUT_DOUT10_Pos) |
GPIO_T::DOUT: DOUT10 Mask
| #define GPIO_DOUT_DOUT10_Pos (10) |
GPIO_T::DOUT: DOUT10 Position
| #define GPIO_DOUT_DOUT11_Msk (0x1ul << GPIO_DOUT_DOUT11_Pos) |
GPIO_T::DOUT: DOUT11 Mask
| #define GPIO_DOUT_DOUT11_Pos (11) |
GPIO_T::DOUT: DOUT11 Position
| #define GPIO_DOUT_DOUT12_Msk (0x1ul << GPIO_DOUT_DOUT12_Pos) |
GPIO_T::DOUT: DOUT12 Mask
| #define GPIO_DOUT_DOUT12_Pos (12) |
GPIO_T::DOUT: DOUT12 Position
| #define GPIO_DOUT_DOUT13_Msk (0x1ul << GPIO_DOUT_DOUT13_Pos) |
GPIO_T::DOUT: DOUT13 Mask
| #define GPIO_DOUT_DOUT13_Pos (13) |
GPIO_T::DOUT: DOUT13 Position
| #define GPIO_DOUT_DOUT14_Msk (0x1ul << GPIO_DOUT_DOUT14_Pos) |
GPIO_T::DOUT: DOUT14 Mask
| #define GPIO_DOUT_DOUT14_Pos (14) |
GPIO_T::DOUT: DOUT14 Position
| #define GPIO_DOUT_DOUT15_Msk (0x1ul << GPIO_DOUT_DOUT15_Pos) |
GPIO_T::DOUT: DOUT15 Mask
| #define GPIO_DOUT_DOUT15_Pos (15) |
GPIO_T::DOUT: DOUT15 Position
| #define GPIO_DOUT_DOUT1_Msk (0x1ul << GPIO_DOUT_DOUT1_Pos) |
GPIO_T::DOUT: DOUT1 Mask
| #define GPIO_DOUT_DOUT1_Pos (1) |
GPIO_T::DOUT: DOUT1 Position
| #define GPIO_DOUT_DOUT2_Msk (0x1ul << GPIO_DOUT_DOUT2_Pos) |
GPIO_T::DOUT: DOUT2 Mask
| #define GPIO_DOUT_DOUT2_Pos (2) |
GPIO_T::DOUT: DOUT2 Position
| #define GPIO_DOUT_DOUT3_Msk (0x1ul << GPIO_DOUT_DOUT3_Pos) |
GPIO_T::DOUT: DOUT3 Mask
| #define GPIO_DOUT_DOUT3_Pos (3) |
GPIO_T::DOUT: DOUT3 Position
| #define GPIO_DOUT_DOUT4_Msk (0x1ul << GPIO_DOUT_DOUT4_Pos) |
GPIO_T::DOUT: DOUT4 Mask
| #define GPIO_DOUT_DOUT4_Pos (4) |
GPIO_T::DOUT: DOUT4 Position
| #define GPIO_DOUT_DOUT5_Msk (0x1ul << GPIO_DOUT_DOUT5_Pos) |
GPIO_T::DOUT: DOUT5 Mask
| #define GPIO_DOUT_DOUT5_Pos (5) |
GPIO_T::DOUT: DOUT5 Position
| #define GPIO_DOUT_DOUT6_Msk (0x1ul << GPIO_DOUT_DOUT6_Pos) |
GPIO_T::DOUT: DOUT6 Mask
| #define GPIO_DOUT_DOUT6_Pos (6) |
GPIO_T::DOUT: DOUT6 Position
| #define GPIO_DOUT_DOUT7_Msk (0x1ul << GPIO_DOUT_DOUT7_Pos) |
GPIO_T::DOUT: DOUT7 Mask
| #define GPIO_DOUT_DOUT7_Pos (7) |
GPIO_T::DOUT: DOUT7 Position
| #define GPIO_DOUT_DOUT8_Msk (0x1ul << GPIO_DOUT_DOUT8_Pos) |
GPIO_T::DOUT: DOUT8 Mask
| #define GPIO_DOUT_DOUT8_Pos (8) |
GPIO_T::DOUT: DOUT8 Position
| #define GPIO_DOUT_DOUT9_Msk (0x1ul << GPIO_DOUT_DOUT9_Pos) |
GPIO_T::DOUT: DOUT9 Mask
| #define GPIO_DOUT_DOUT9_Pos (9) |
GPIO_T::DOUT: DOUT9 Position
| #define GPIO_INTEN_FLIEN0_Msk (0x1ul << GPIO_INTEN_FLIEN0_Pos) |
GPIO_T::INTEN: FLIEN0 Mask
| #define GPIO_INTEN_FLIEN0_Pos (0) |
GPIO_T::INTEN: FLIEN0 Position
| #define GPIO_INTEN_FLIEN10_Msk (0x1ul << GPIO_INTEN_FLIEN10_Pos) |
GPIO_T::INTEN: FLIEN10 Mask
| #define GPIO_INTEN_FLIEN10_Pos (10) |
GPIO_T::INTEN: FLIEN10 Position
| #define GPIO_INTEN_FLIEN11_Msk (0x1ul << GPIO_INTEN_FLIEN11_Pos) |
GPIO_T::INTEN: FLIEN11 Mask
| #define GPIO_INTEN_FLIEN11_Pos (11) |
GPIO_T::INTEN: FLIEN11 Position
| #define GPIO_INTEN_FLIEN12_Msk (0x1ul << GPIO_INTEN_FLIEN12_Pos) |
GPIO_T::INTEN: FLIEN12 Mask
| #define GPIO_INTEN_FLIEN12_Pos (12) |
GPIO_T::INTEN: FLIEN12 Position
| #define GPIO_INTEN_FLIEN13_Msk (0x1ul << GPIO_INTEN_FLIEN13_Pos) |
GPIO_T::INTEN: FLIEN13 Mask
| #define GPIO_INTEN_FLIEN13_Pos (13) |
GPIO_T::INTEN: FLIEN13 Position
| #define GPIO_INTEN_FLIEN14_Msk (0x1ul << GPIO_INTEN_FLIEN14_Pos) |
GPIO_T::INTEN: FLIEN14 Mask
| #define GPIO_INTEN_FLIEN14_Pos (14) |
GPIO_T::INTEN: FLIEN14 Position
| #define GPIO_INTEN_FLIEN15_Msk (0x1ul << GPIO_INTEN_FLIEN15_Pos) |
GPIO_T::INTEN: FLIEN15 Mask
| #define GPIO_INTEN_FLIEN15_Pos (15) |
GPIO_T::INTEN: FLIEN15 Position
| #define GPIO_INTEN_FLIEN1_Msk (0x1ul << GPIO_INTEN_FLIEN1_Pos) |
GPIO_T::INTEN: FLIEN1 Mask
| #define GPIO_INTEN_FLIEN1_Pos (1) |
GPIO_T::INTEN: FLIEN1 Position
| #define GPIO_INTEN_FLIEN2_Msk (0x1ul << GPIO_INTEN_FLIEN2_Pos) |
GPIO_T::INTEN: FLIEN2 Mask
| #define GPIO_INTEN_FLIEN2_Pos (2) |
GPIO_T::INTEN: FLIEN2 Position
| #define GPIO_INTEN_FLIEN3_Msk (0x1ul << GPIO_INTEN_FLIEN3_Pos) |
GPIO_T::INTEN: FLIEN3 Mask
| #define GPIO_INTEN_FLIEN3_Pos (3) |
GPIO_T::INTEN: FLIEN3 Position
| #define GPIO_INTEN_FLIEN4_Msk (0x1ul << GPIO_INTEN_FLIEN4_Pos) |
GPIO_T::INTEN: FLIEN4 Mask
| #define GPIO_INTEN_FLIEN4_Pos (4) |
GPIO_T::INTEN: FLIEN4 Position
| #define GPIO_INTEN_FLIEN5_Msk (0x1ul << GPIO_INTEN_FLIEN5_Pos) |
GPIO_T::INTEN: FLIEN5 Mask
| #define GPIO_INTEN_FLIEN5_Pos (5) |
GPIO_T::INTEN: FLIEN5 Position
| #define GPIO_INTEN_FLIEN6_Msk (0x1ul << GPIO_INTEN_FLIEN6_Pos) |
GPIO_T::INTEN: FLIEN6 Mask
| #define GPIO_INTEN_FLIEN6_Pos (6) |
GPIO_T::INTEN: FLIEN6 Position
| #define GPIO_INTEN_FLIEN7_Msk (0x1ul << GPIO_INTEN_FLIEN7_Pos) |
GPIO_T::INTEN: FLIEN7 Mask
| #define GPIO_INTEN_FLIEN7_Pos (7) |
GPIO_T::INTEN: FLIEN7 Position
| #define GPIO_INTEN_FLIEN8_Msk (0x1ul << GPIO_INTEN_FLIEN8_Pos) |
GPIO_T::INTEN: FLIEN8 Mask
| #define GPIO_INTEN_FLIEN8_Pos (8) |
GPIO_T::INTEN: FLIEN8 Position
| #define GPIO_INTEN_FLIEN9_Msk (0x1ul << GPIO_INTEN_FLIEN9_Pos) |
GPIO_T::INTEN: FLIEN9 Mask
| #define GPIO_INTEN_FLIEN9_Pos (9) |
GPIO_T::INTEN: FLIEN9 Position
| #define GPIO_INTEN_RHIEN0_Msk (0x1ul << GPIO_INTEN_RHIEN0_Pos) |
GPIO_T::INTEN: RHIEN0 Mask
| #define GPIO_INTEN_RHIEN0_Pos (16) |
GPIO_T::INTEN: RHIEN0 Position
| #define GPIO_INTEN_RHIEN10_Msk (0x1ul << GPIO_INTEN_RHIEN10_Pos) |
GPIO_T::INTEN: RHIEN10 Mask
| #define GPIO_INTEN_RHIEN10_Pos (26) |
GPIO_T::INTEN: RHIEN10 Position
| #define GPIO_INTEN_RHIEN11_Msk (0x1ul << GPIO_INTEN_RHIEN11_Pos) |
GPIO_T::INTEN: RHIEN11 Mask
| #define GPIO_INTEN_RHIEN11_Pos (27) |
GPIO_T::INTEN: RHIEN11 Position
| #define GPIO_INTEN_RHIEN12_Msk (0x1ul << GPIO_INTEN_RHIEN12_Pos) |
GPIO_T::INTEN: RHIEN12 Mask
| #define GPIO_INTEN_RHIEN12_Pos (28) |
GPIO_T::INTEN: RHIEN12 Position
| #define GPIO_INTEN_RHIEN13_Msk (0x1ul << GPIO_INTEN_RHIEN13_Pos) |
GPIO_T::INTEN: RHIEN13 Mask
| #define GPIO_INTEN_RHIEN13_Pos (29) |
GPIO_T::INTEN: RHIEN13 Position
| #define GPIO_INTEN_RHIEN14_Msk (0x1ul << GPIO_INTEN_RHIEN14_Pos) |
GPIO_T::INTEN: RHIEN14 Mask
| #define GPIO_INTEN_RHIEN14_Pos (30) |
GPIO_T::INTEN: RHIEN14 Position
| #define GPIO_INTEN_RHIEN15_Msk (0x1ul << GPIO_INTEN_RHIEN15_Pos) |
GPIO_T::INTEN: RHIEN15 Mask
| #define GPIO_INTEN_RHIEN15_Pos (31) |
GPIO_T::INTEN: RHIEN15 Position
| #define GPIO_INTEN_RHIEN1_Msk (0x1ul << GPIO_INTEN_RHIEN1_Pos) |
GPIO_T::INTEN: RHIEN1 Mask
| #define GPIO_INTEN_RHIEN1_Pos (17) |
GPIO_T::INTEN: RHIEN1 Position
| #define GPIO_INTEN_RHIEN2_Msk (0x1ul << GPIO_INTEN_RHIEN2_Pos) |
GPIO_T::INTEN: RHIEN2 Mask
| #define GPIO_INTEN_RHIEN2_Pos (18) |
GPIO_T::INTEN: RHIEN2 Position
| #define GPIO_INTEN_RHIEN3_Msk (0x1ul << GPIO_INTEN_RHIEN3_Pos) |
GPIO_T::INTEN: RHIEN3 Mask
| #define GPIO_INTEN_RHIEN3_Pos (19) |
GPIO_T::INTEN: RHIEN3 Position
| #define GPIO_INTEN_RHIEN4_Msk (0x1ul << GPIO_INTEN_RHIEN4_Pos) |
GPIO_T::INTEN: RHIEN4 Mask
| #define GPIO_INTEN_RHIEN4_Pos (20) |
GPIO_T::INTEN: RHIEN4 Position
| #define GPIO_INTEN_RHIEN5_Msk (0x1ul << GPIO_INTEN_RHIEN5_Pos) |
GPIO_T::INTEN: RHIEN5 Mask
| #define GPIO_INTEN_RHIEN5_Pos (21) |
GPIO_T::INTEN: RHIEN5 Position
| #define GPIO_INTEN_RHIEN6_Msk (0x1ul << GPIO_INTEN_RHIEN6_Pos) |
GPIO_T::INTEN: RHIEN6 Mask
| #define GPIO_INTEN_RHIEN6_Pos (22) |
GPIO_T::INTEN: RHIEN6 Position
| #define GPIO_INTEN_RHIEN7_Msk (0x1ul << GPIO_INTEN_RHIEN7_Pos) |
GPIO_T::INTEN: RHIEN7 Mask
| #define GPIO_INTEN_RHIEN7_Pos (23) |
GPIO_T::INTEN: RHIEN7 Position
| #define GPIO_INTEN_RHIEN8_Msk (0x1ul << GPIO_INTEN_RHIEN8_Pos) |
GPIO_T::INTEN: RHIEN8 Mask
| #define GPIO_INTEN_RHIEN8_Pos (24) |
GPIO_T::INTEN: RHIEN8 Position
| #define GPIO_INTEN_RHIEN9_Msk (0x1ul << GPIO_INTEN_RHIEN9_Pos) |
GPIO_T::INTEN: RHIEN9 Mask
| #define GPIO_INTEN_RHIEN9_Pos (25) |
GPIO_T::INTEN: RHIEN9 Position
| #define GPIO_INTSRC_INTSRC0_Msk (0x1ul << GPIO_INTSRC_INTSRC0_Pos) |
GPIO_T::INTSRC: INTSRC0 Mask
| #define GPIO_INTSRC_INTSRC0_Pos (0) |
GPIO_T::INTSRC: INTSRC0 Position
| #define GPIO_INTSRC_INTSRC10_Msk (0x1ul << GPIO_INTSRC_INTSRC10_Pos) |
GPIO_T::INTSRC: INTSRC10 Mask
| #define GPIO_INTSRC_INTSRC10_Pos (10) |
GPIO_T::INTSRC: INTSRC10 Position
| #define GPIO_INTSRC_INTSRC11_Msk (0x1ul << GPIO_INTSRC_INTSRC11_Pos) |
GPIO_T::INTSRC: INTSRC11 Mask
| #define GPIO_INTSRC_INTSRC11_Pos (11) |
GPIO_T::INTSRC: INTSRC11 Position
| #define GPIO_INTSRC_INTSRC12_Msk (0x1ul << GPIO_INTSRC_INTSRC12_Pos) |
GPIO_T::INTSRC: INTSRC12 Mask
| #define GPIO_INTSRC_INTSRC12_Pos (12) |
GPIO_T::INTSRC: INTSRC12 Position
| #define GPIO_INTSRC_INTSRC13_Msk (0x1ul << GPIO_INTSRC_INTSRC13_Pos) |
GPIO_T::INTSRC: INTSRC13 Mask
| #define GPIO_INTSRC_INTSRC13_Pos (13) |
GPIO_T::INTSRC: INTSRC13 Position
| #define GPIO_INTSRC_INTSRC14_Msk (0x1ul << GPIO_INTSRC_INTSRC14_Pos) |
GPIO_T::INTSRC: INTSRC14 Mask
| #define GPIO_INTSRC_INTSRC14_Pos (14) |
GPIO_T::INTSRC: INTSRC14 Position
| #define GPIO_INTSRC_INTSRC15_Msk (0x1ul << GPIO_INTSRC_INTSRC15_Pos) |
GPIO_T::INTSRC: INTSRC15 Mask
| #define GPIO_INTSRC_INTSRC15_Pos (15) |
GPIO_T::INTSRC: INTSRC15 Position
| #define GPIO_INTSRC_INTSRC1_Msk (0x1ul << GPIO_INTSRC_INTSRC1_Pos) |
GPIO_T::INTSRC: INTSRC1 Mask
| #define GPIO_INTSRC_INTSRC1_Pos (1) |
GPIO_T::INTSRC: INTSRC1 Position
| #define GPIO_INTSRC_INTSRC2_Msk (0x1ul << GPIO_INTSRC_INTSRC2_Pos) |
GPIO_T::INTSRC: INTSRC2 Mask
| #define GPIO_INTSRC_INTSRC2_Pos (2) |
GPIO_T::INTSRC: INTSRC2 Position
| #define GPIO_INTSRC_INTSRC3_Msk (0x1ul << GPIO_INTSRC_INTSRC3_Pos) |
GPIO_T::INTSRC: INTSRC3 Mask
| #define GPIO_INTSRC_INTSRC3_Pos (3) |
GPIO_T::INTSRC: INTSRC3 Position
| #define GPIO_INTSRC_INTSRC4_Msk (0x1ul << GPIO_INTSRC_INTSRC4_Pos) |
GPIO_T::INTSRC: INTSRC4 Mask
| #define GPIO_INTSRC_INTSRC4_Pos (4) |
GPIO_T::INTSRC: INTSRC4 Position
| #define GPIO_INTSRC_INTSRC5_Msk (0x1ul << GPIO_INTSRC_INTSRC5_Pos) |
GPIO_T::INTSRC: INTSRC5 Mask
| #define GPIO_INTSRC_INTSRC5_Pos (5) |
GPIO_T::INTSRC: INTSRC5 Position
| #define GPIO_INTSRC_INTSRC6_Msk (0x1ul << GPIO_INTSRC_INTSRC6_Pos) |
GPIO_T::INTSRC: INTSRC6 Mask
| #define GPIO_INTSRC_INTSRC6_Pos (6) |
GPIO_T::INTSRC: INTSRC6 Position
| #define GPIO_INTSRC_INTSRC7_Msk (0x1ul << GPIO_INTSRC_INTSRC7_Pos) |
GPIO_T::INTSRC: INTSRC7 Mask
| #define GPIO_INTSRC_INTSRC7_Pos (7) |
GPIO_T::INTSRC: INTSRC7 Position
| #define GPIO_INTSRC_INTSRC8_Msk (0x1ul << GPIO_INTSRC_INTSRC8_Pos) |
GPIO_T::INTSRC: INTSRC8 Mask
| #define GPIO_INTSRC_INTSRC8_Pos (8) |
GPIO_T::INTSRC: INTSRC8 Position
| #define GPIO_INTSRC_INTSRC9_Msk (0x1ul << GPIO_INTSRC_INTSRC9_Pos) |
GPIO_T::INTSRC: INTSRC9 Mask
| #define GPIO_INTSRC_INTSRC9_Pos (9) |
GPIO_T::INTSRC: INTSRC9 Position
| #define GPIO_INTSTS_FLISTS0_Msk (0x1ul << GPIO_INTSTS_FLISTS0_Pos) |
GPIO_T::INTSTS: FLISTS0 Mask
| #define GPIO_INTSTS_FLISTS0_Pos (0) |
GPIO_T::INTSTS: FLISTS0 Position
| #define GPIO_INTSTS_FLISTS10_Msk (0x1ul << GPIO_INTSTS_FLISTS10_Pos) |
GPIO_T::INTSTS: FLISTS10 Mask
| #define GPIO_INTSTS_FLISTS10_Pos (10) |
GPIO_T::INTSTS: FLISTS10 Position
| #define GPIO_INTSTS_FLISTS11_Msk (0x1ul << GPIO_INTSTS_FLISTS11_Pos) |
GPIO_T::INTSTS: FLISTS11 Mask
| #define GPIO_INTSTS_FLISTS11_Pos (11) |
GPIO_T::INTSTS: FLISTS11 Position
| #define GPIO_INTSTS_FLISTS12_Msk (0x1ul << GPIO_INTSTS_FLISTS12_Pos) |
GPIO_T::INTSTS: FLISTS12 Mask
| #define GPIO_INTSTS_FLISTS12_Pos (12) |
GPIO_T::INTSTS: FLISTS12 Position
| #define GPIO_INTSTS_FLISTS13_Msk (0x1ul << GPIO_INTSTS_FLISTS13_Pos) |
GPIO_T::INTSTS: FLISTS13 Mask
| #define GPIO_INTSTS_FLISTS13_Pos (13) |
GPIO_T::INTSTS: FLISTS13 Position
| #define GPIO_INTSTS_FLISTS14_Msk (0x1ul << GPIO_INTSTS_FLISTS14_Pos) |
GPIO_T::INTSTS: FLISTS14 Mask
| #define GPIO_INTSTS_FLISTS14_Pos (14) |
GPIO_T::INTSTS: FLISTS14 Position
| #define GPIO_INTSTS_FLISTS15_Msk (0x1ul << GPIO_INTSTS_FLISTS15_Pos) |
GPIO_T::INTSTS: FLISTS15 Mask
| #define GPIO_INTSTS_FLISTS15_Pos (15) |
GPIO_T::INTSTS: FLISTS15 Position
| #define GPIO_INTSTS_FLISTS1_Msk (0x1ul << GPIO_INTSTS_FLISTS1_Pos) |
GPIO_T::INTSTS: FLISTS1 Mask
| #define GPIO_INTSTS_FLISTS1_Pos (1) |
GPIO_T::INTSTS: FLISTS1 Position
| #define GPIO_INTSTS_FLISTS2_Msk (0x1ul << GPIO_INTSTS_FLISTS2_Pos) |
GPIO_T::INTSTS: FLISTS2 Mask
| #define GPIO_INTSTS_FLISTS2_Pos (2) |
GPIO_T::INTSTS: FLISTS2 Position
| #define GPIO_INTSTS_FLISTS3_Msk (0x1ul << GPIO_INTSTS_FLISTS3_Pos) |
GPIO_T::INTSTS: FLISTS3 Mask
| #define GPIO_INTSTS_FLISTS3_Pos (3) |
GPIO_T::INTSTS: FLISTS3 Position
| #define GPIO_INTSTS_FLISTS4_Msk (0x1ul << GPIO_INTSTS_FLISTS4_Pos) |
GPIO_T::INTSTS: FLISTS4 Mask
| #define GPIO_INTSTS_FLISTS4_Pos (4) |
GPIO_T::INTSTS: FLISTS4 Position
| #define GPIO_INTSTS_FLISTS5_Msk (0x1ul << GPIO_INTSTS_FLISTS5_Pos) |
GPIO_T::INTSTS: FLISTS5 Mask
| #define GPIO_INTSTS_FLISTS5_Pos (5) |
GPIO_T::INTSTS: FLISTS5 Position
| #define GPIO_INTSTS_FLISTS6_Msk (0x1ul << GPIO_INTSTS_FLISTS6_Pos) |
GPIO_T::INTSTS: FLISTS6 Mask
| #define GPIO_INTSTS_FLISTS6_Pos (6) |
GPIO_T::INTSTS: FLISTS6 Position
| #define GPIO_INTSTS_FLISTS7_Msk (0x1ul << GPIO_INTSTS_FLISTS7_Pos) |
GPIO_T::INTSTS: FLISTS7 Mask
| #define GPIO_INTSTS_FLISTS7_Pos (7) |
GPIO_T::INTSTS: FLISTS7 Position
| #define GPIO_INTSTS_FLISTS8_Msk (0x1ul << GPIO_INTSTS_FLISTS8_Pos) |
GPIO_T::INTSTS: FLISTS8 Mask
| #define GPIO_INTSTS_FLISTS8_Pos (8) |
GPIO_T::INTSTS: FLISTS8 Position
| #define GPIO_INTSTS_FLISTS9_Msk (0x1ul << GPIO_INTSTS_FLISTS9_Pos) |
GPIO_T::INTSTS: FLISTS9 Mask
| #define GPIO_INTSTS_FLISTS9_Pos (9) |
GPIO_T::INTSTS: FLISTS9 Position
| #define GPIO_INTSTS_RHISTS0_Msk (0x1ul << GPIO_INTSTS_RHISTS0_Pos) |
GPIO_T::INTSTS: RHISTS0 Mask
| #define GPIO_INTSTS_RHISTS0_Pos (16) |
GPIO_T::INTSTS: RHISTS0 Position
| #define GPIO_INTSTS_RHISTS10_Msk (0x1ul << GPIO_INTSTS_RHISTS10_Pos) |
GPIO_T::INTSTS: RHISTS10 Mask
| #define GPIO_INTSTS_RHISTS10_Pos (26) |
GPIO_T::INTSTS: RHISTS10 Position
| #define GPIO_INTSTS_RHISTS11_Msk (0x1ul << GPIO_INTSTS_RHISTS11_Pos) |
GPIO_T::INTSTS: RHISTS11 Mask
| #define GPIO_INTSTS_RHISTS11_Pos (27) |
GPIO_T::INTSTS: RHISTS11 Position
| #define GPIO_INTSTS_RHISTS12_Msk (0x1ul << GPIO_INTSTS_RHISTS12_Pos) |
GPIO_T::INTSTS: RHISTS12 Mask
| #define GPIO_INTSTS_RHISTS12_Pos (28) |
GPIO_T::INTSTS: RHISTS12 Position
| #define GPIO_INTSTS_RHISTS13_Msk (0x1ul << GPIO_INTSTS_RHISTS13_Pos) |
GPIO_T::INTSTS: RHISTS13 Mask
| #define GPIO_INTSTS_RHISTS13_Pos (29) |
GPIO_T::INTSTS: RHISTS13 Position
| #define GPIO_INTSTS_RHISTS14_Msk (0x1ul << GPIO_INTSTS_RHISTS14_Pos) |
GPIO_T::INTSTS: RHISTS14 Mask
| #define GPIO_INTSTS_RHISTS14_Pos (30) |
GPIO_T::INTSTS: RHISTS14 Position
| #define GPIO_INTSTS_RHISTS15_Msk (0x1ul << GPIO_INTSTS_RHISTS15_Pos) |
GPIO_T::INTSTS: RHISTS15 Mask
| #define GPIO_INTSTS_RHISTS15_Pos (31) |
GPIO_T::INTSTS: RHISTS15 Position
| #define GPIO_INTSTS_RHISTS1_Msk (0x1ul << GPIO_INTSTS_RHISTS1_Pos) |
GPIO_T::INTSTS: RHISTS1 Mask
| #define GPIO_INTSTS_RHISTS1_Pos (17) |
GPIO_T::INTSTS: RHISTS1 Position
| #define GPIO_INTSTS_RHISTS2_Msk (0x1ul << GPIO_INTSTS_RHISTS2_Pos) |
GPIO_T::INTSTS: RHISTS2 Mask
| #define GPIO_INTSTS_RHISTS2_Pos (18) |
GPIO_T::INTSTS: RHISTS2 Position
| #define GPIO_INTSTS_RHISTS3_Msk (0x1ul << GPIO_INTSTS_RHISTS3_Pos) |
GPIO_T::INTSTS: RHISTS3 Mask
| #define GPIO_INTSTS_RHISTS3_Pos (19) |
GPIO_T::INTSTS: RHISTS3 Position
| #define GPIO_INTSTS_RHISTS4_Msk (0x1ul << GPIO_INTSTS_RHISTS4_Pos) |
GPIO_T::INTSTS: RHISTS4 Mask
| #define GPIO_INTSTS_RHISTS4_Pos (20) |
GPIO_T::INTSTS: RHISTS4 Position
| #define GPIO_INTSTS_RHISTS5_Msk (0x1ul << GPIO_INTSTS_RHISTS5_Pos) |
GPIO_T::INTSTS: RHISTS5 Mask
| #define GPIO_INTSTS_RHISTS5_Pos (21) |
GPIO_T::INTSTS: RHISTS5 Position
| #define GPIO_INTSTS_RHISTS6_Msk (0x1ul << GPIO_INTSTS_RHISTS6_Pos) |
GPIO_T::INTSTS: RHISTS6 Mask
| #define GPIO_INTSTS_RHISTS6_Pos (22) |
GPIO_T::INTSTS: RHISTS6 Position
| #define GPIO_INTSTS_RHISTS7_Msk (0x1ul << GPIO_INTSTS_RHISTS7_Pos) |
GPIO_T::INTSTS: RHISTS7 Mask
| #define GPIO_INTSTS_RHISTS7_Pos (23) |
GPIO_T::INTSTS: RHISTS7 Position
| #define GPIO_INTSTS_RHISTS8_Msk (0x1ul << GPIO_INTSTS_RHISTS8_Pos) |
GPIO_T::INTSTS: RHISTS8 Mask
| #define GPIO_INTSTS_RHISTS8_Pos (24) |
GPIO_T::INTSTS: RHISTS8 Position
| #define GPIO_INTSTS_RHISTS9_Msk (0x1ul << GPIO_INTSTS_RHISTS9_Pos) |
GPIO_T::INTSTS: RHISTS9 Mask
| #define GPIO_INTSTS_RHISTS9_Pos (25) |
GPIO_T::INTSTS: RHISTS9 Position
| #define GPIO_INTTYPE_TYPE0_Msk (0x1ul << GPIO_INTTYPE_TYPE0_Pos) |
GPIO_T::INTTYPE: TYPE0 Mask
| #define GPIO_INTTYPE_TYPE0_Pos (0) |
GPIO_T::INTTYPE: TYPE0 Position
| #define GPIO_INTTYPE_TYPE10_Msk (0x1ul << GPIO_INTTYPE_TYPE10_Pos) |
GPIO_T::INTTYPE: TYPE10 Mask
| #define GPIO_INTTYPE_TYPE10_Pos (10) |
GPIO_T::INTTYPE: TYPE10 Position
| #define GPIO_INTTYPE_TYPE11_Msk (0x1ul << GPIO_INTTYPE_TYPE11_Pos) |
GPIO_T::INTTYPE: TYPE11 Mask
| #define GPIO_INTTYPE_TYPE11_Pos (11) |
GPIO_T::INTTYPE: TYPE11 Position
| #define GPIO_INTTYPE_TYPE12_Msk (0x1ul << GPIO_INTTYPE_TYPE12_Pos) |
GPIO_T::INTTYPE: TYPE12 Mask
| #define GPIO_INTTYPE_TYPE12_Pos (12) |
GPIO_T::INTTYPE: TYPE12 Position
| #define GPIO_INTTYPE_TYPE13_Msk (0x1ul << GPIO_INTTYPE_TYPE13_Pos) |
GPIO_T::INTTYPE: TYPE13 Mask
| #define GPIO_INTTYPE_TYPE13_Pos (13) |
GPIO_T::INTTYPE: TYPE13 Position
| #define GPIO_INTTYPE_TYPE14_Msk (0x1ul << GPIO_INTTYPE_TYPE14_Pos) |
GPIO_T::INTTYPE: TYPE14 Mask
| #define GPIO_INTTYPE_TYPE14_Pos (14) |
GPIO_T::INTTYPE: TYPE14 Position
| #define GPIO_INTTYPE_TYPE15_Msk (0x1ul << GPIO_INTTYPE_TYPE15_Pos) |
GPIO_T::INTTYPE: TYPE15 Mask
| #define GPIO_INTTYPE_TYPE15_Pos (15) |
GPIO_T::INTTYPE: TYPE15 Position
| #define GPIO_INTTYPE_TYPE1_Msk (0x1ul << GPIO_INTTYPE_TYPE1_Pos) |
GPIO_T::INTTYPE: TYPE1 Mask
| #define GPIO_INTTYPE_TYPE1_Pos (1) |
GPIO_T::INTTYPE: TYPE1 Position
| #define GPIO_INTTYPE_TYPE2_Msk (0x1ul << GPIO_INTTYPE_TYPE2_Pos) |
GPIO_T::INTTYPE: TYPE2 Mask
| #define GPIO_INTTYPE_TYPE2_Pos (2) |
GPIO_T::INTTYPE: TYPE2 Position
| #define GPIO_INTTYPE_TYPE3_Msk (0x1ul << GPIO_INTTYPE_TYPE3_Pos) |
GPIO_T::INTTYPE: TYPE3 Mask
| #define GPIO_INTTYPE_TYPE3_Pos (3) |
GPIO_T::INTTYPE: TYPE3 Position
| #define GPIO_INTTYPE_TYPE4_Msk (0x1ul << GPIO_INTTYPE_TYPE4_Pos) |
GPIO_T::INTTYPE: TYPE4 Mask
| #define GPIO_INTTYPE_TYPE4_Pos (4) |
GPIO_T::INTTYPE: TYPE4 Position
| #define GPIO_INTTYPE_TYPE5_Msk (0x1ul << GPIO_INTTYPE_TYPE5_Pos) |
GPIO_T::INTTYPE: TYPE5 Mask
| #define GPIO_INTTYPE_TYPE5_Pos (5) |
GPIO_T::INTTYPE: TYPE5 Position
| #define GPIO_INTTYPE_TYPE6_Msk (0x1ul << GPIO_INTTYPE_TYPE6_Pos) |
GPIO_T::INTTYPE: TYPE6 Mask
| #define GPIO_INTTYPE_TYPE6_Pos (6) |
GPIO_T::INTTYPE: TYPE6 Position
| #define GPIO_INTTYPE_TYPE7_Msk (0x1ul << GPIO_INTTYPE_TYPE7_Pos) |
GPIO_T::INTTYPE: TYPE7 Mask
| #define GPIO_INTTYPE_TYPE7_Pos (7) |
GPIO_T::INTTYPE: TYPE7 Position
| #define GPIO_INTTYPE_TYPE8_Msk (0x1ul << GPIO_INTTYPE_TYPE8_Pos) |
GPIO_T::INTTYPE: TYPE8 Mask
| #define GPIO_INTTYPE_TYPE8_Pos (8) |
GPIO_T::INTTYPE: TYPE8 Position
| #define GPIO_INTTYPE_TYPE9_Msk (0x1ul << GPIO_INTTYPE_TYPE9_Pos) |
GPIO_T::INTTYPE: TYPE9 Mask
| #define GPIO_INTTYPE_TYPE9_Pos (9) |
GPIO_T::INTTYPE: TYPE9 Position
| #define GPIO_MODE_MODE0_Msk (0x3ul << GPIO_MODE_MODE0_Pos) |
GPIO_T::MODE: MODE0 Mask
| #define GPIO_MODE_MODE0_Pos (0) |
@addtogroup GPIO_CONST GPIO Bit Field Definition Constant Definitions for GPIO Controller
GPIO_T::MODE: MODE0 Position
| #define GPIO_MODE_MODE10_Msk (0x3ul << GPIO_MODE_MODE10_Pos) |
GPIO_T::MODE: MODE10 Mask
| #define GPIO_MODE_MODE10_Pos (20) |
GPIO_T::MODE: MODE10 Position
| #define GPIO_MODE_MODE11_Msk (0x3ul << GPIO_MODE_MODE11_Pos) |
GPIO_T::MODE: MODE11 Mask
| #define GPIO_MODE_MODE11_Pos (22) |
GPIO_T::MODE: MODE11 Position
| #define GPIO_MODE_MODE12_Msk (0x3ul << GPIO_MODE_MODE12_Pos) |
GPIO_T::MODE: MODE12 Mask
| #define GPIO_MODE_MODE12_Pos (24) |
GPIO_T::MODE: MODE12 Position
| #define GPIO_MODE_MODE13_Msk (0x3ul << GPIO_MODE_MODE13_Pos) |
GPIO_T::MODE: MODE13 Mask
| #define GPIO_MODE_MODE13_Pos (26) |
GPIO_T::MODE: MODE13 Position
| #define GPIO_MODE_MODE14_Msk (0x3ul << GPIO_MODE_MODE14_Pos) |
GPIO_T::MODE: MODE14 Mask
| #define GPIO_MODE_MODE14_Pos (28) |
GPIO_T::MODE: MODE14 Position
| #define GPIO_MODE_MODE15_Msk (0x3ul << GPIO_MODE_MODE15_Pos) |
GPIO_T::MODE: MODE15 Mask
| #define GPIO_MODE_MODE15_Pos (30) |
GPIO_T::MODE: MODE15 Position
| #define GPIO_MODE_MODE1_Msk (0x3ul << GPIO_MODE_MODE1_Pos) |
GPIO_T::MODE: MODE1 Mask
| #define GPIO_MODE_MODE1_Pos (2) |
GPIO_T::MODE: MODE1 Position
| #define GPIO_MODE_MODE2_Msk (0x3ul << GPIO_MODE_MODE2_Pos) |
GPIO_T::MODE: MODE2 Mask
| #define GPIO_MODE_MODE2_Pos (4) |
GPIO_T::MODE: MODE2 Position
| #define GPIO_MODE_MODE3_Msk (0x3ul << GPIO_MODE_MODE3_Pos) |
GPIO_T::MODE: MODE3 Mask
| #define GPIO_MODE_MODE3_Pos (6) |
GPIO_T::MODE: MODE3 Position
| #define GPIO_MODE_MODE4_Msk (0x3ul << GPIO_MODE_MODE4_Pos) |
GPIO_T::MODE: MODE4 Mask
| #define GPIO_MODE_MODE4_Pos (8) |
GPIO_T::MODE: MODE4 Position
| #define GPIO_MODE_MODE5_Msk (0x3ul << GPIO_MODE_MODE5_Pos) |
GPIO_T::MODE: MODE5 Mask
| #define GPIO_MODE_MODE5_Pos (10) |
GPIO_T::MODE: MODE5 Position
| #define GPIO_MODE_MODE6_Msk (0x3ul << GPIO_MODE_MODE6_Pos) |
GPIO_T::MODE: MODE6 Mask
| #define GPIO_MODE_MODE6_Pos (12) |
GPIO_T::MODE: MODE6 Position
| #define GPIO_MODE_MODE7_Msk (0x3ul << GPIO_MODE_MODE7_Pos) |
GPIO_T::MODE: MODE7 Mask
| #define GPIO_MODE_MODE7_Pos (14) |
GPIO_T::MODE: MODE7 Position
| #define GPIO_MODE_MODE8_Msk (0x3ul << GPIO_MODE_MODE8_Pos) |
GPIO_T::MODE: MODE8 Mask
| #define GPIO_MODE_MODE8_Pos (16) |
GPIO_T::MODE: MODE8 Position
| #define GPIO_MODE_MODE9_Msk (0x3ul << GPIO_MODE_MODE9_Pos) |
GPIO_T::MODE: MODE9 Mask
| #define GPIO_MODE_MODE9_Pos (18) |
GPIO_T::MODE: MODE9 Position
| #define GPIO_PIN_PIN0_Msk (0x1ul << GPIO_PIN_PIN0_Pos) |
GPIO_T::PIN: PIN0 Mask
| #define GPIO_PIN_PIN0_Pos (0) |
GPIO_T::PIN: PIN0 Position
| #define GPIO_PIN_PIN10_Msk (0x1ul << GPIO_PIN_PIN10_Pos) |
GPIO_T::PIN: PIN10 Mask
| #define GPIO_PIN_PIN10_Pos (10) |
GPIO_T::PIN: PIN10 Position
| #define GPIO_PIN_PIN11_Msk (0x1ul << GPIO_PIN_PIN11_Pos) |
GPIO_T::PIN: PIN11 Mask
| #define GPIO_PIN_PIN11_Pos (11) |
GPIO_T::PIN: PIN11 Position
| #define GPIO_PIN_PIN12_Msk (0x1ul << GPIO_PIN_PIN12_Pos) |
GPIO_T::PIN: PIN12 Mask
| #define GPIO_PIN_PIN12_Pos (12) |
GPIO_T::PIN: PIN12 Position
| #define GPIO_PIN_PIN13_Msk (0x1ul << GPIO_PIN_PIN13_Pos) |
GPIO_T::PIN: PIN13 Mask
| #define GPIO_PIN_PIN13_Pos (13) |
GPIO_T::PIN: PIN13 Position
| #define GPIO_PIN_PIN14_Msk (0x1ul << GPIO_PIN_PIN14_Pos) |
GPIO_T::PIN: PIN14 Mask
| #define GPIO_PIN_PIN14_Pos (14) |
GPIO_T::PIN: PIN14 Position
| #define GPIO_PIN_PIN15_Msk (0x1ul << GPIO_PIN_PIN15_Pos) |
GPIO_T::PIN: PIN15 Mask
| #define GPIO_PIN_PIN15_Pos (15) |
GPIO_T::PIN: PIN15 Position
| #define GPIO_PIN_PIN1_Msk (0x1ul << GPIO_PIN_PIN1_Pos) |
GPIO_T::PIN: PIN1 Mask
| #define GPIO_PIN_PIN1_Pos (1) |
GPIO_T::PIN: PIN1 Position
| #define GPIO_PIN_PIN2_Msk (0x1ul << GPIO_PIN_PIN2_Pos) |
GPIO_T::PIN: PIN2 Mask
| #define GPIO_PIN_PIN2_Pos (2) |
GPIO_T::PIN: PIN2 Position
| #define GPIO_PIN_PIN3_Msk (0x1ul << GPIO_PIN_PIN3_Pos) |
GPIO_T::PIN: PIN3 Mask
| #define GPIO_PIN_PIN3_Pos (3) |
GPIO_T::PIN: PIN3 Position
| #define GPIO_PIN_PIN4_Msk (0x1ul << GPIO_PIN_PIN4_Pos) |
GPIO_T::PIN: PIN4 Mask
| #define GPIO_PIN_PIN4_Pos (4) |
GPIO_T::PIN: PIN4 Position
| #define GPIO_PIN_PIN5_Msk (0x1ul << GPIO_PIN_PIN5_Pos) |
GPIO_T::PIN: PIN5 Mask
| #define GPIO_PIN_PIN5_Pos (5) |
GPIO_T::PIN: PIN5 Position
| #define GPIO_PIN_PIN6_Msk (0x1ul << GPIO_PIN_PIN6_Pos) |
GPIO_T::PIN: PIN6 Mask
| #define GPIO_PIN_PIN6_Pos (6) |
GPIO_T::PIN: PIN6 Position
| #define GPIO_PIN_PIN7_Msk (0x1ul << GPIO_PIN_PIN7_Pos) |
GPIO_T::PIN: PIN7 Mask
| #define GPIO_PIN_PIN7_Pos (7) |
GPIO_T::PIN: PIN7 Position
| #define GPIO_PIN_PIN8_Msk (0x1ul << GPIO_PIN_PIN8_Pos) |
GPIO_T::PIN: PIN8 Mask
| #define GPIO_PIN_PIN8_Pos (8) |
GPIO_T::PIN: PIN8 Position
| #define GPIO_PIN_PIN9_Msk (0x1ul << GPIO_PIN_PIN9_Pos) |
GPIO_T::PIN: PIN9 Mask
| #define GPIO_PIN_PIN9_Pos (9) |
GPIO_T::PIN: PIN9 Position
| #define GPIO_PUEN_PUEN0_Msk (0x1ul << GPIO_PUEN_PUEN0_Pos) |
GPIO_T::PUEN: PUEN0 Mask
| #define GPIO_PUEN_PUEN0_Pos (0) |
GPIO_T::PUEN: PUEN0 Position
| #define GPIO_PUEN_PUEN10_Msk (0x1ul << GPIO_PUEN_PUEN10_Pos) |
GPIO_T::PUEN: PUEN10 Mask
| #define GPIO_PUEN_PUEN10_Pos (10) |
GPIO_T::PUEN: PUEN10 Position
| #define GPIO_PUEN_PUEN11_Msk (0x1ul << GPIO_PUEN_PUEN11_Pos) |
GPIO_T::PUEN: PUEN11 Mask
| #define GPIO_PUEN_PUEN11_Pos (11) |
GPIO_T::PUEN: PUEN11 Position
| #define GPIO_PUEN_PUEN12_Msk (0x1ul << GPIO_PUEN_PUEN12_Pos) |
GPIO_T::PUEN: PUEN12 Mask
| #define GPIO_PUEN_PUEN12_Pos (12) |
GPIO_T::PUEN: PUEN12 Position
| #define GPIO_PUEN_PUEN13_Msk (0x1ul << GPIO_PUEN_PUEN13_Pos) |
GPIO_T::PUEN: PUEN13 Mask
| #define GPIO_PUEN_PUEN13_Pos (13) |
GPIO_T::PUEN: PUEN13 Position
| #define GPIO_PUEN_PUEN14_Msk (0x1ul << GPIO_PUEN_PUEN14_Pos) |
GPIO_T::PUEN: PUEN14 Mask
| #define GPIO_PUEN_PUEN14_Pos (14) |
GPIO_T::PUEN: PUEN14 Position
| #define GPIO_PUEN_PUEN15_Msk (0x1ul << GPIO_PUEN_PUEN15_Pos) |
GPIO_T::PUEN: PUEN15 Mask
| #define GPIO_PUEN_PUEN15_Pos (15) |
GPIO_T::PUEN: PUEN15 Position
| #define GPIO_PUEN_PUEN1_Msk (0x1ul << GPIO_PUEN_PUEN1_Pos) |
GPIO_T::PUEN: PUEN1 Mask
| #define GPIO_PUEN_PUEN1_Pos (1) |
GPIO_T::PUEN: PUEN1 Position
| #define GPIO_PUEN_PUEN2_Msk (0x1ul << GPIO_PUEN_PUEN2_Pos) |
GPIO_T::PUEN: PUEN2 Mask
| #define GPIO_PUEN_PUEN2_Pos (2) |
GPIO_T::PUEN: PUEN2 Position
| #define GPIO_PUEN_PUEN3_Msk (0x1ul << GPIO_PUEN_PUEN3_Pos) |
GPIO_T::PUEN: PUEN3 Mask
| #define GPIO_PUEN_PUEN3_Pos (3) |
GPIO_T::PUEN: PUEN3 Position
| #define GPIO_PUEN_PUEN4_Msk (0x1ul << GPIO_PUEN_PUEN4_Pos) |
GPIO_T::PUEN: PUEN4 Mask
| #define GPIO_PUEN_PUEN4_Pos (4) |
GPIO_T::PUEN: PUEN4 Position
| #define GPIO_PUEN_PUEN5_Msk (0x1ul << GPIO_PUEN_PUEN5_Pos) |
GPIO_T::PUEN: PUEN5 Mask
| #define GPIO_PUEN_PUEN5_Pos (5) |
GPIO_T::PUEN: PUEN5 Position
| #define GPIO_PUEN_PUEN6_Msk (0x1ul << GPIO_PUEN_PUEN6_Pos) |
GPIO_T::PUEN: PUEN6 Mask
| #define GPIO_PUEN_PUEN6_Pos (6) |
GPIO_T::PUEN: PUEN6 Position
| #define GPIO_PUEN_PUEN7_Msk (0x1ul << GPIO_PUEN_PUEN7_Pos) |
GPIO_T::PUEN: PUEN7 Mask
| #define GPIO_PUEN_PUEN7_Pos (7) |
GPIO_T::PUEN: PUEN7 Position
| #define GPIO_PUEN_PUEN8_Msk (0x1ul << GPIO_PUEN_PUEN8_Pos) |
GPIO_T::PUEN: PUEN8 Mask
| #define GPIO_PUEN_PUEN8_Pos (8) |
GPIO_T::PUEN: PUEN8 Position
| #define GPIO_PUEN_PUEN9_Msk (0x1ul << GPIO_PUEN_PUEN9_Pos) |
GPIO_T::PUEN: PUEN9 Mask
| #define GPIO_PUEN_PUEN9_Pos (9) |
GPIO_T::PUEN: PUEN9 Position
| #define I2C_ADDR0_ADDR_Msk (0x7ful << I2C_ADDR0_ADDR_Pos) |
I2C_T::ADDR0: ADDR Mask
| #define I2C_ADDR0_ADDR_Pos (1) |
I2C_T::ADDR0: ADDR Position
| #define I2C_ADDR0_GC_Msk (0x1ul << I2C_ADDR0_GC_Pos) |
I2C_T::ADDR0: GC Mask
| #define I2C_ADDR0_GC_Pos (0) |
I2C_T::ADDR0: GC Position
| #define I2C_ADDR1_ADDR_Msk (0x7ful << I2C_ADDR1_ADDR_Pos) |
I2C_T::ADDR1: ADDR Mask
| #define I2C_ADDR1_ADDR_Pos (1) |
I2C_T::ADDR1: ADDR Position
| #define I2C_ADDR1_GC_Msk (0x1ul << I2C_ADDR1_GC_Pos) |
I2C_T::ADDR1: GC Mask
| #define I2C_ADDR1_GC_Pos (0) |
I2C_T::ADDR1: GC Position
| #define I2C_ADDRMSK0_ADDRMSK_Msk (0x7ful << I2C_ADDRMSK0_ADDRMSK_Pos) |
I2C_T::ADDRMSK0: ADDRMSK Mask
| #define I2C_ADDRMSK0_ADDRMSK_Pos (1) |
I2C_T::ADDRMSK0: ADDRMSK Position
| #define I2C_ADDRMSK1_ADDRMSK_Msk (0x7ful << I2C_ADDRMSK1_ADDRMSK_Pos) |
I2C_T::ADDRMSK1: ADDRMSK Mask
| #define I2C_ADDRMSK1_ADDRMSK_Pos (1) |
I2C_T::ADDRMSK1: ADDRMSK Position
| #define I2C_CLKDIV_DIVIDER_Msk (0xfful << I2C_CLKDIV_DIVIDER_Pos) |
I2C_T::CLKDIV: DIVIDER Mask
| #define I2C_CLKDIV_DIVIDER_Pos (0) |
I2C_T::CLKDIV: DIVIDER Position
| #define I2C_CTL2_DATMODE_Msk (0x1ul << I2C_CTL2_DATMODE_Pos) |
I2C_T::CTL2: DATMODE Mask
| #define I2C_CTL2_DATMODE_Pos (6) |
I2C_T::CTL2: DATMODE Position
| #define I2C_CTL2_MSDAT_Msk (0x1ul << I2C_CTL2_MSDAT_Pos) |
I2C_T::CTL2: MSDAT Mask
| #define I2C_CTL2_MSDAT_Pos (7) |
I2C_T::CTL2: MSDAT Position
| #define I2C_CTL2_NOSTRETCH_Msk (0x1ul << I2C_CTL2_NOSTRETCH_Pos) |
I2C_T::CTL2: NOSTRETCH Mask
| #define I2C_CTL2_NOSTRETCH_Pos (5) |
I2C_T::CTL2: NOSTRETCH Position
| #define I2C_CTL2_OVIEN_Msk (0x1ul << I2C_CTL2_OVIEN_Pos) |
I2C_T::CTL2: OVIEN Mask
| #define I2C_CTL2_OVIEN_Pos (1) |
I2C_T::CTL2: OVIEN Position
| #define I2C_CTL2_TWOLVBUF_Msk (0x1ul << I2C_CTL2_TWOLVBUF_Pos) |
I2C_T::CTL2: TWOLVBUF Mask
| #define I2C_CTL2_TWOLVBUF_Pos (4) |
I2C_T::CTL2: TWOLVBUF Position
| #define I2C_CTL2_URIEN_Msk (0x1ul << I2C_CTL2_URIEN_Pos) |
I2C_T::CTL2: URIEN Mask
| #define I2C_CTL2_URIEN_Pos (2) |
I2C_T::CTL2: URIEN Position
| #define I2C_CTL2_WKUPEN_Msk (0x1ul << I2C_CTL2_WKUPEN_Pos) |
I2C_T::CTL2: WKUPEN Mask
| #define I2C_CTL2_WKUPEN_Pos (0) |
I2C_T::CTL2: WKUPEN Position
| #define I2C_CTL_AA_Msk (0x1ul << I2C_CTL_AA_Pos) |
I2C_T::CTL: AA Mask
| #define I2C_CTL_AA_Pos (1) |
I2C_T::CTL: AA Position
| #define I2C_CTL_I2CEN_Msk (0x1ul << I2C_CTL_I2CEN_Pos) |
I2C_T::CTL: I2CEN Mask
| #define I2C_CTL_I2CEN_Pos (0) |
@addtogroup I2C_CONST I2C Bit Field Definition Constant Definitions for I2C Controller
I2C_T::CTL: I2CEN Position
| #define I2C_CTL_INTEN_Msk (0x1ul << I2C_CTL_INTEN_Pos) |
I2C_T::CTL: INTEN Mask
| #define I2C_CTL_INTEN_Pos (7) |
I2C_T::CTL: INTEN Position
| #define I2C_CTL_SI_Msk (0x1ul << I2C_CTL_SI_Pos) |
I2C_T::CTL: SI Mask
| #define I2C_CTL_SI_Pos (4) |
I2C_T::CTL: SI Position
| #define I2C_CTL_STA_Msk (0x1ul << I2C_CTL_STA_Pos) |
I2C_T::CTL: STA Mask
| #define I2C_CTL_STA_Pos (3) |
I2C_T::CTL: STA Position
| #define I2C_CTL_STO_Msk (0x1ul << I2C_CTL_STO_Pos) |
I2C_T::CTL: STO Mask
| #define I2C_CTL_STO_Pos (2) |
I2C_T::CTL: STO Position
| #define I2C_DAT_DAT_Msk (0xfful << I2C_DAT_DAT_Pos) |
I2C_T::DAT: DAT Mask
| #define I2C_DAT_DAT_Pos (0) |
I2C_T::DAT: DAT Position
| #define I2C_INTSTS_INTSTS_Msk (0x1ul << I2C_INTSTS_INTSTS_Pos) |
I2C_T::INTSTS: INTSTS Mask
| #define I2C_INTSTS_INTSTS_Pos (0) |
I2C_T::INTSTS: INTSTS Position
| #define I2C_INTSTS_TOIF_Msk (0x1ul << I2C_INTSTS_TOIF_Pos) |
I2C_T::INTSTS: TOIF Mask
| #define I2C_INTSTS_TOIF_Pos (1) |
I2C_T::INTSTS: TOIF Position
| #define I2C_INTSTS_WKAKDONE_Msk (0x1ul << I2C_INTSTS_WKAKDONE_Pos) |
I2C_T::INTSTS: WKAKDONE Mask
| #define I2C_INTSTS_WKAKDONE_Pos (7) |
I2C_T::INTSTS: WKAKDONE Position
| #define I2C_STATUS2_BUSFREE_Msk (0x1ul << I2C_STATUS2_BUSFREE_Pos) |
I2C_T::STATUS2: BUSFREE Mask
| #define I2C_STATUS2_BUSFREE_Pos (6) |
I2C_T::STATUS2: BUSFREE Position
| #define I2C_STATUS2_EMPTY_Msk (0x1ul << I2C_STATUS2_EMPTY_Pos) |
I2C_T::STATUS2: EMPTY Mask
| #define I2C_STATUS2_EMPTY_Pos (5) |
I2C_T::STATUS2: EMPTY Position
| #define I2C_STATUS2_FULL_Msk (0x1ul << I2C_STATUS2_FULL_Pos) |
I2C_T::STATUS2: FULL Mask
| #define I2C_STATUS2_FULL_Pos (4) |
I2C_T::STATUS2: FULL Position
| #define I2C_STATUS2_OVIF_Msk (0x1ul << I2C_STATUS2_OVIF_Pos) |
I2C_T::STATUS2: OVIF Mask
| #define I2C_STATUS2_OVIF_Pos (1) |
I2C_T::STATUS2: OVIF Position
| #define I2C_STATUS2_URIF_Msk (0x1ul << I2C_STATUS2_URIF_Pos) |
I2C_T::STATUS2: URIF Mask
| #define I2C_STATUS2_URIF_Pos (2) |
I2C_T::STATUS2: URIF Position
| #define I2C_STATUS2_WKIF_Msk (0x1ul << I2C_STATUS2_WKIF_Pos) |
I2C_T::STATUS2: WKIF Mask
| #define I2C_STATUS2_WKIF_Pos (0) |
I2C_T::STATUS2: WKIF Position
| #define I2C_STATUS2_WRSTSWK_Msk (0x1ul << I2C_STATUS2_WRSTSWK_Pos) |
I2C_T::STATUS2: WRSTSWK Mask
| #define I2C_STATUS2_WRSTSWK_Pos (3) |
I2C_T::STATUS2: WRSTSWK Position
| #define I2C_STATUS_STATUS_Msk (0xfful << I2C_STATUS_STATUS_Pos) |
I2C_T::STATUS: STATUS Mask
| #define I2C_STATUS_STATUS_Pos (0) |
I2C_T::STATUS: STATUS Position
| #define I2C_TOCTL_TOCDIV4_Msk (0x1ul << I2C_TOCTL_TOCDIV4_Pos) |
I2C_T::TOCTL: TOCDIV4 Mask
| #define I2C_TOCTL_TOCDIV4_Pos (1) |
I2C_T::TOCTL: TOCDIV4 Position
| #define I2C_TOCTL_TOCEN_Msk (0x1ul << I2C_TOCTL_TOCEN_Pos) |
I2C_T::TOCTL: TOCEN Mask
| #define I2C_TOCTL_TOCEN_Pos (0) |
I2C_T::TOCTL: TOCEN Position
| #define PDMA_CH_CCNTn_CCNT_Msk (0xfffful << PDMA_CH_CCNTn_CCNT_Pos) |
PDMA_CH_T::CCNTn: CCNT Mask
| #define PDMA_CH_CCNTn_CCNT_Pos (0) |
PDMA_CH_T::CCNTn: CCNT Position
| #define PDMA_CH_CDAn_CDA_Msk (0xfffffffful << PDMA_CH_CDAn_CDA_Pos) |
PDMA_CH_T::CDAn: CDA Mask
| #define PDMA_CH_CDAn_CDA_Pos (0) |
PDMA_CH_T::CDAn: CDA Position
| #define PDMA_CH_CNTn_PCNTITH_Msk (0xfffful << PDMA_CH_CNTn_PCNTITH_Pos) |
PDMA_CH_T::CNTn: PCNTITH Mask
| #define PDMA_CH_CNTn_PCNTITH_Pos (16) |
PDMA_CH_T::CNTn: PCNTITH Position
| #define PDMA_CH_CNTn_TCNT_Msk (0xfffful << PDMA_CH_CNTn_TCNT_Pos) |
PDMA_CH_T::CNTn: TCNT Mask
| #define PDMA_CH_CNTn_TCNT_Pos (0) |
PDMA_CH_T::CNTn: TCNT Position
| #define PDMA_CH_CSAn_CSA_Msk (0xfffffffful << PDMA_CH_CSAn_CSA_Pos) |
PDMA_CH_T::CSAn: CSA Mask
| #define PDMA_CH_CSAn_CSA_Pos (0) |
PDMA_CH_T::CSAn: CSA Position
| #define PDMA_CH_CTLn_CHEN_Msk (0x1ul << PDMA_CH_CTLn_CHEN_Pos) |
PDMA_CH_T::CTLn: CHEN Mask
| #define PDMA_CH_CTLn_CHEN_Pos (0) |
@addtogroup PDMA_CH_CONST PDMA_CH Bit Field Definition Constant Definitions for PDMA_CH Controller
PDMA_CH_T::CTLn: CHEN Position
| #define PDMA_CH_CTLn_DASEL_Msk (0x3ul << PDMA_CH_CTLn_DASEL_Pos) |
PDMA_CH_T::CTLn: DASEL Mask
| #define PDMA_CH_CTLn_DASEL_Pos (6) |
PDMA_CH_T::CTLn: DASEL Position
| #define PDMA_CH_CTLn_SASEL_Msk (0x3ul << PDMA_CH_CTLn_SASEL_Pos) |
PDMA_CH_T::CTLn: SASEL Mask
| #define PDMA_CH_CTLn_SASEL_Pos (4) |
PDMA_CH_T::CTLn: SASEL Position
| #define PDMA_CH_CTLn_SWRST_Msk (0x1ul << PDMA_CH_CTLn_SWRST_Pos) |
PDMA_CH_T::CTLn: SWRST Mask
| #define PDMA_CH_CTLn_SWRST_Pos (1) |
PDMA_CH_T::CTLn: SWRST Position
| #define PDMA_CH_CTLn_TOUTEN_Msk (0x1ul << PDMA_CH_CTLn_TOUTEN_Pos) |
PDMA_CH_T::CTLn: TOUTEN Mask
| #define PDMA_CH_CTLn_TOUTEN_Pos (12) |
PDMA_CH_T::CTLn: TOUTEN Position
| #define PDMA_CH_CTLn_TRIGEN_Msk (0x1ul << PDMA_CH_CTLn_TRIGEN_Pos) |
PDMA_CH_T::CTLn: TRIGEN Mask
| #define PDMA_CH_CTLn_TRIGEN_Pos (23) |
PDMA_CH_T::CTLn: TRIGEN Position
| #define PDMA_CH_CTLn_TXWIDTH_Msk (0x3ul << PDMA_CH_CTLn_TXWIDTH_Pos) |
PDMA_CH_T::CTLn: TXWIDTH Mask
| #define PDMA_CH_CTLn_TXWIDTH_Pos (19) |
PDMA_CH_T::CTLn: TXWIDTH Position
| #define PDMA_CH_DAn_DA_Msk (0xfffffffful << PDMA_CH_DAn_DA_Pos) |
PDMA_CH_T::DAn: DA Mask
| #define PDMA_CH_DAn_DA_Pos (0) |
PDMA_CH_T::DAn: DA Position
| #define PDMA_CH_INTENn_PCNTIEN_Msk (0x1ul << PDMA_CH_INTENn_PCNTIEN_Pos) |
PDMA_CH_T::INTENn: PCNTIEN Mask
| #define PDMA_CH_INTENn_PCNTIEN_Pos (8) |
PDMA_CH_T::INTENn: PCNTIEN Position
| #define PDMA_CH_INTENn_TABTIEN_Msk (0x1ul << PDMA_CH_INTENn_TABTIEN_Pos) |
PDMA_CH_T::INTENn: TABTIEN Mask
| #define PDMA_CH_INTENn_TABTIEN_Pos (0) |
PDMA_CH_T::INTENn: TABTIEN Position
| #define PDMA_CH_INTENn_TDIEN_Msk (0x1ul << PDMA_CH_INTENn_TDIEN_Pos) |
PDMA_CH_T::INTENn: TDIEN Mask
| #define PDMA_CH_INTENn_TDIEN_Pos (1) |
PDMA_CH_T::INTENn: TDIEN Position
| #define PDMA_CH_INTENn_TOUTIEN_Msk (0x1ul << PDMA_CH_INTENn_TOUTIEN_Pos) |
PDMA_CH_T::INTENn: TOUTIEN Mask
| #define PDMA_CH_INTENn_TOUTIEN_Pos (6) |
PDMA_CH_T::INTENn: TOUTIEN Position
| #define PDMA_CH_INTSTSn_PCNTIF_Msk (0x1ul << PDMA_CH_INTSTSn_PCNTIF_Pos) |
PDMA_CH_T::INTSTSn: PCNTIF Mask
| #define PDMA_CH_INTSTSn_PCNTIF_Pos (8) |
PDMA_CH_T::INTSTSn: PCNTIF Position
| #define PDMA_CH_INTSTSn_TABTIF_Msk (0x1ul << PDMA_CH_INTSTSn_TABTIF_Pos) |
PDMA_CH_T::INTSTSn: TABTIF Mask
| #define PDMA_CH_INTSTSn_TABTIF_Pos (0) |
PDMA_CH_T::INTSTSn: TABTIF Position
| #define PDMA_CH_INTSTSn_TDIF_Msk (0x1ul << PDMA_CH_INTSTSn_TDIF_Pos) |
PDMA_CH_T::INTSTSn: TDIF Mask
| #define PDMA_CH_INTSTSn_TDIF_Pos (1) |
PDMA_CH_T::INTSTSn: TDIF Position
| #define PDMA_CH_INTSTSn_TOUTIF_Msk (0x1ul << PDMA_CH_INTSTSn_TOUTIF_Pos) |
PDMA_CH_T::INTSTSn: TOUTIF Mask
| #define PDMA_CH_INTSTSn_TOUTIF_Pos (6) |
PDMA_CH_T::INTSTSn: TOUTIF Position
| #define PDMA_CH_SAn_SA_Msk (0xfffffffful << PDMA_CH_SAn_SA_Pos) |
PDMA_CH_T::SAn: SA Mask
| #define PDMA_CH_SAn_SA_Pos (0) |
PDMA_CH_T::SAn: SA Position
| #define PDMA_CH_TOCn_TOC_Msk (0xfffful << PDMA_CH_TOCn_TOC_Pos) |
PDMA_CH_T::TOCn: TOC Mask
| #define PDMA_CH_TOCn_TOC_Pos (0) |
PDMA_CH_T::TOCn: TOC Position
| #define PDMA_CH_TOCn_TPSC_Msk (0x7ul << PDMA_CH_TOCn_TPSC_Pos) |
PDMA_CH_T::TOCn: TPSC Mask
| #define PDMA_CH_TOCn_TPSC_Pos (16) |
PDMA_CH_T::TOCn: TPSC Position
| #define PWM_ADCTS0_TRGEN0_Msk (0x1ul << PWM_ADCTS0_TRGEN0_Pos) |
PWM_T::ADCTS0: TRGEN0 Mask
| #define PWM_ADCTS0_TRGEN0_Pos (7) |
PWM_T::ADCTS0: TRGEN0 Position
| #define PWM_ADCTS0_TRGEN1_Msk (0x1ul << PWM_ADCTS0_TRGEN1_Pos) |
PWM_T::ADCTS0: TRGEN1 Mask
| #define PWM_ADCTS0_TRGEN1_Pos (15) |
PWM_T::ADCTS0: TRGEN1 Position
| #define PWM_ADCTS0_TRGEN2_Msk (0x1ul << PWM_ADCTS0_TRGEN2_Pos) |
PWM_T::ADCTS0: TRGEN2 Mask
| #define PWM_ADCTS0_TRGEN2_Pos (23) |
PWM_T::ADCTS0: TRGEN2 Position
| #define PWM_ADCTS0_TRGEN3_Msk (0x1ul << PWM_ADCTS0_TRGEN3_Pos) |
PWM_T::ADCTS0: TRGEN3 Mask
| #define PWM_ADCTS0_TRGEN3_Pos (31) |
PWM_T::ADCTS0: TRGEN3 Position
| #define PWM_ADCTS0_TRGSEL0_Msk (0xful << PWM_ADCTS0_TRGSEL0_Pos) |
PWM_T::ADCTS0: TRGSEL0 Mask
| #define PWM_ADCTS0_TRGSEL0_Pos (0) |
PWM_T::ADCTS0: TRGSEL0 Position
| #define PWM_ADCTS0_TRGSEL1_Msk (0xful << PWM_ADCTS0_TRGSEL1_Pos) |
PWM_T::ADCTS0: TRGSEL1 Mask
| #define PWM_ADCTS0_TRGSEL1_Pos (8) |
PWM_T::ADCTS0: TRGSEL1 Position
| #define PWM_ADCTS0_TRGSEL2_Msk (0xful << PWM_ADCTS0_TRGSEL2_Pos) |
PWM_T::ADCTS0: TRGSEL2 Mask
| #define PWM_ADCTS0_TRGSEL2_Pos (16) |
PWM_T::ADCTS0: TRGSEL2 Position
| #define PWM_ADCTS0_TRGSEL3_Msk (0xful << PWM_ADCTS0_TRGSEL3_Pos) |
PWM_T::ADCTS0: TRGSEL3 Mask
| #define PWM_ADCTS0_TRGSEL3_Pos (24) |
PWM_T::ADCTS0: TRGSEL3 Position
| #define PWM_ADCTS1_TRGEN4_Msk (0x1ul << PWM_ADCTS1_TRGEN4_Pos) |
PWM_T::ADCTS1: TRGEN4 Mask
| #define PWM_ADCTS1_TRGEN4_Pos (7) |
PWM_T::ADCTS1: TRGEN4 Position
| #define PWM_ADCTS1_TRGEN5_Msk (0x1ul << PWM_ADCTS1_TRGEN5_Pos) |
PWM_T::ADCTS1: TRGEN5 Mask
| #define PWM_ADCTS1_TRGEN5_Pos (15) |
PWM_T::ADCTS1: TRGEN5 Position
| #define PWM_ADCTS1_TRGSEL4_Msk (0xful << PWM_ADCTS1_TRGSEL4_Pos) |
PWM_T::ADCTS1: TRGSEL4 Mask
| #define PWM_ADCTS1_TRGSEL4_Pos (0) |
PWM_T::ADCTS1: TRGSEL4 Position
| #define PWM_ADCTS1_TRGSEL5_Msk (0xful << PWM_ADCTS1_TRGSEL5_Pos) |
PWM_T::ADCTS1: TRGSEL5 Mask
| #define PWM_ADCTS1_TRGSEL5_Pos (8) |
PWM_T::ADCTS1: TRGSEL5 Position
| #define PWM_BNF_BK0SRC_Msk (0x1ul << PWM_BNF_BK0SRC_Pos) |
PWM_T::BNF: BK0SRC Mask
| #define PWM_BNF_BK0SRC_Pos (16) |
PWM_T::BNF: BK0SRC Position
| #define PWM_BNF_BK1SRC_Msk (0x1ul << PWM_BNF_BK1SRC_Pos) |
PWM_T::BNF: BK1SRC Mask
| #define PWM_BNF_BK1SRC_Pos (24) |
PWM_T::BNF: BK1SRC Position
| #define PWM_BNF_BRK0FCNT_Msk (0x7ul << PWM_BNF_BRK0FCNT_Pos) |
PWM_T::BNF: BRK0FCNT Mask
| #define PWM_BNF_BRK0FCNT_Pos (4) |
PWM_T::BNF: BRK0FCNT Position
| #define PWM_BNF_BRK0FCS_Msk (0x7ul << PWM_BNF_BRK0FCS_Pos) |
PWM_T::BNF: BRK0FCS Mask
| #define PWM_BNF_BRK0FCS_Pos (1) |
PWM_T::BNF: BRK0FCS Position
| #define PWM_BNF_BRK0FEN_Msk (0x1ul << PWM_BNF_BRK0FEN_Pos) |
PWM_T::BNF: BRK0FEN Mask
| #define PWM_BNF_BRK0FEN_Pos (0) |
PWM_T::BNF: BRK0FEN Position
| #define PWM_BNF_BRK0PINV_Msk (0x1ul << PWM_BNF_BRK0PINV_Pos) |
PWM_T::BNF: BRK0PINV Mask
| #define PWM_BNF_BRK0PINV_Pos (7) |
PWM_T::BNF: BRK0PINV Position
| #define PWM_BNF_BRK1FCNT_Msk (0x7ul << PWM_BNF_BRK1FCNT_Pos) |
PWM_T::BNF: BRK1FCNT Mask
| #define PWM_BNF_BRK1FCNT_Pos (12) |
PWM_T::BNF: BRK1FCNT Position
| #define PWM_BNF_BRK1FCS_Msk (0x7ul << PWM_BNF_BRK1FCS_Pos) |
PWM_T::BNF: BRK1FCS Mask
| #define PWM_BNF_BRK1FCS_Pos (9) |
PWM_T::BNF: BRK1FCS Position
| #define PWM_BNF_BRK1FEN_Msk (0x1ul << PWM_BNF_BRK1FEN_Pos) |
PWM_T::BNF: BRK1FEN Mask
| #define PWM_BNF_BRK1FEN_Pos (8) |
PWM_T::BNF: BRK1FEN Position
| #define PWM_BNF_BRK1PINV_Msk (0x1ul << PWM_BNF_BRK1PINV_Pos) |
PWM_T::BNF: BRK1PINV Mask
| #define PWM_BNF_BRK1PINV_Pos (15) |
PWM_T::BNF: BRK1PINV Position
| #define PWM_BRKCTL0_1_BRKAEVEN_Msk (0x3ul << PWM_BRKCTL0_1_BRKAEVEN_Pos) |
PWM_T::BRKCTL0_1: BRKAEVEN Mask
| #define PWM_BRKCTL0_1_BRKAEVEN_Pos (16) |
PWM_T::BRKCTL0_1: BRKAEVEN Position
| #define PWM_BRKCTL0_1_BRKAODD_Msk (0x3ul << PWM_BRKCTL0_1_BRKAODD_Pos) |
PWM_T::BRKCTL0_1: BRKAODD Mask
| #define PWM_BRKCTL0_1_BRKAODD_Pos (18) |
PWM_T::BRKCTL0_1: BRKAODD Position
| #define PWM_BRKCTL0_1_BRKP0EEN_Msk (0x1ul << PWM_BRKCTL0_1_BRKP0EEN_Pos) |
PWM_T::BRKCTL0_1: BRKP0EEN Mask
| #define PWM_BRKCTL0_1_BRKP0EEN_Pos (4) |
PWM_T::BRKCTL0_1: BRKP0EEN Position
| #define PWM_BRKCTL0_1_BRKP0LEN_Msk (0x1ul << PWM_BRKCTL0_1_BRKP0LEN_Pos) |
PWM_T::BRKCTL0_1: BRKP0LEN Mask
| #define PWM_BRKCTL0_1_BRKP0LEN_Pos (12) |
PWM_T::BRKCTL0_1: BRKP0LEN Position
| #define PWM_BRKCTL0_1_BRKP1EEN_Msk (0x1ul << PWM_BRKCTL0_1_BRKP1EEN_Pos) |
PWM_T::BRKCTL0_1: BRKP1EEN Mask
| #define PWM_BRKCTL0_1_BRKP1EEN_Pos (5) |
PWM_T::BRKCTL0_1: BRKP1EEN Position
| #define PWM_BRKCTL0_1_BRKP1LEN_Msk (0x1ul << PWM_BRKCTL0_1_BRKP1LEN_Pos) |
PWM_T::BRKCTL0_1: BRKP1LEN Mask
| #define PWM_BRKCTL0_1_BRKP1LEN_Pos (13) |
PWM_T::BRKCTL0_1: BRKP1LEN Position
| #define PWM_BRKCTL0_1_SYSEEN_Msk (0x1ul << PWM_BRKCTL0_1_SYSEEN_Pos) |
PWM_T::BRKCTL0_1: SYSEEN Mask
| #define PWM_BRKCTL0_1_SYSEEN_Pos (7) |
PWM_T::BRKCTL0_1: SYSEEN Position
| #define PWM_BRKCTL0_1_SYSLEN_Msk (0x1ul << PWM_BRKCTL0_1_SYSLEN_Pos) |
PWM_T::BRKCTL0_1: SYSLEN Mask
| #define PWM_BRKCTL0_1_SYSLEN_Pos (15) |
PWM_T::BRKCTL0_1: SYSLEN Position
| #define PWM_BRKCTL2_3_BRKAEVEN_Msk (0x3ul << PWM_BRKCTL2_3_BRKAEVEN_Pos) |
PWM_T::BRKCTL2_3: BRKAEVEN Mask
| #define PWM_BRKCTL2_3_BRKAEVEN_Pos (16) |
PWM_T::BRKCTL2_3: BRKAEVEN Position
| #define PWM_BRKCTL2_3_BRKAODD_Msk (0x3ul << PWM_BRKCTL2_3_BRKAODD_Pos) |
PWM_T::BRKCTL2_3: BRKAODD Mask
| #define PWM_BRKCTL2_3_BRKAODD_Pos (18) |
PWM_T::BRKCTL2_3: BRKAODD Position
| #define PWM_BRKCTL2_3_BRKP0EEN_Msk (0x1ul << PWM_BRKCTL2_3_BRKP0EEN_Pos) |
PWM_T::BRKCTL2_3: BRKP0EEN Mask
| #define PWM_BRKCTL2_3_BRKP0EEN_Pos (4) |
PWM_T::BRKCTL2_3: BRKP0EEN Position
| #define PWM_BRKCTL2_3_BRKP0LEN_Msk (0x1ul << PWM_BRKCTL2_3_BRKP0LEN_Pos) |
PWM_T::BRKCTL2_3: BRKP0LEN Mask
| #define PWM_BRKCTL2_3_BRKP0LEN_Pos (12) |
PWM_T::BRKCTL2_3: BRKP0LEN Position
| #define PWM_BRKCTL2_3_BRKP1EEN_Msk (0x1ul << PWM_BRKCTL2_3_BRKP1EEN_Pos) |
PWM_T::BRKCTL2_3: BRKP1EEN Mask
| #define PWM_BRKCTL2_3_BRKP1EEN_Pos (5) |
PWM_T::BRKCTL2_3: BRKP1EEN Position
| #define PWM_BRKCTL2_3_BRKP1LEN_Msk (0x1ul << PWM_BRKCTL2_3_BRKP1LEN_Pos) |
PWM_T::BRKCTL2_3: BRKP1LEN Mask
| #define PWM_BRKCTL2_3_BRKP1LEN_Pos (13) |
PWM_T::BRKCTL2_3: BRKP1LEN Position
| #define PWM_BRKCTL2_3_SYSEEN_Msk (0x1ul << PWM_BRKCTL2_3_SYSEEN_Pos) |
PWM_T::BRKCTL2_3: SYSEEN Mask
| #define PWM_BRKCTL2_3_SYSEEN_Pos (7) |
PWM_T::BRKCTL2_3: SYSEEN Position
| #define PWM_BRKCTL2_3_SYSLEN_Msk (0x1ul << PWM_BRKCTL2_3_SYSLEN_Pos) |
PWM_T::BRKCTL2_3: SYSLEN Mask
| #define PWM_BRKCTL2_3_SYSLEN_Pos (15) |
PWM_T::BRKCTL2_3: SYSLEN Position
| #define PWM_BRKCTL4_5_BRKAEVEN_Msk (0x3ul << PWM_BRKCTL4_5_BRKAEVEN_Pos) |
PWM_T::BRKCTL4_5: BRKAEVEN Mask
| #define PWM_BRKCTL4_5_BRKAEVEN_Pos (16) |
PWM_T::BRKCTL4_5: BRKAEVEN Position
| #define PWM_BRKCTL4_5_BRKAODD_Msk (0x3ul << PWM_BRKCTL4_5_BRKAODD_Pos) |
PWM_T::BRKCTL4_5: BRKAODD Mask
| #define PWM_BRKCTL4_5_BRKAODD_Pos (18) |
PWM_T::BRKCTL4_5: BRKAODD Position
| #define PWM_BRKCTL4_5_BRKP0EEN_Msk (0x1ul << PWM_BRKCTL4_5_BRKP0EEN_Pos) |
PWM_T::BRKCTL4_5: BRKP0EEN Mask
| #define PWM_BRKCTL4_5_BRKP0EEN_Pos (4) |
PWM_T::BRKCTL4_5: BRKP0EEN Position
| #define PWM_BRKCTL4_5_BRKP0LEN_Msk (0x1ul << PWM_BRKCTL4_5_BRKP0LEN_Pos) |
PWM_T::BRKCTL4_5: BRKP0LEN Mask
| #define PWM_BRKCTL4_5_BRKP0LEN_Pos (12) |
PWM_T::BRKCTL4_5: BRKP0LEN Position
| #define PWM_BRKCTL4_5_BRKP1EEN_Msk (0x1ul << PWM_BRKCTL4_5_BRKP1EEN_Pos) |
PWM_T::BRKCTL4_5: BRKP1EEN Mask
| #define PWM_BRKCTL4_5_BRKP1EEN_Pos (5) |
PWM_T::BRKCTL4_5: BRKP1EEN Position
| #define PWM_BRKCTL4_5_BRKP1LEN_Msk (0x1ul << PWM_BRKCTL4_5_BRKP1LEN_Pos) |
PWM_T::BRKCTL4_5: BRKP1LEN Mask
| #define PWM_BRKCTL4_5_BRKP1LEN_Pos (13) |
PWM_T::BRKCTL4_5: BRKP1LEN Position
| #define PWM_BRKCTL4_5_SYSEEN_Msk (0x1ul << PWM_BRKCTL4_5_SYSEEN_Pos) |
PWM_T::BRKCTL4_5: SYSEEN Mask
| #define PWM_BRKCTL4_5_SYSEEN_Pos (7) |
PWM_T::BRKCTL4_5: SYSEEN Position
| #define PWM_BRKCTL4_5_SYSLEN_Msk (0x1ul << PWM_BRKCTL4_5_SYSLEN_Pos) |
PWM_T::BRKCTL4_5: SYSLEN Mask
| #define PWM_BRKCTL4_5_SYSLEN_Pos (15) |
PWM_T::BRKCTL4_5: SYSLEN Position
| #define PWM_CAPCTL_CAPENn_Msk (0x3ful << PWM_CAPCTL_CAPENn_Pos) |
PWM_T::CAPCTL: CAPENn Mask
| #define PWM_CAPCTL_CAPENn_Pos (0) |
PWM_T::CAPCTL: CAPENn Position
| #define PWM_CAPCTL_CAPINVn_Msk (0x3ful << PWM_CAPCTL_CAPINVn_Pos) |
PWM_T::CAPCTL: CAPINVn Mask
| #define PWM_CAPCTL_CAPINVn_Pos (8) |
PWM_T::CAPCTL: CAPINVn Position
| #define PWM_CAPCTL_FCRLDENn_Msk (0x3ful << PWM_CAPCTL_FCRLDENn_Pos) |
PWM_T::CAPCTL: FCRLDENn Mask
| #define PWM_CAPCTL_FCRLDENn_Pos (24) |
PWM_T::CAPCTL: FCRLDENn Position
| #define PWM_CAPCTL_RCRLDENn_Msk (0x3ful << PWM_CAPCTL_RCRLDENn_Pos) |
PWM_T::CAPCTL: RCRLDENn Mask
| #define PWM_CAPCTL_RCRLDENn_Pos (16) |
PWM_T::CAPCTL: RCRLDENn Position
| #define PWM_CAPIEN_CAPFIENn_Msk (0x3ful << PWM_CAPIEN_CAPFIENn_Pos) |
PWM_T::CAPIEN: CAPFIENn Mask
| #define PWM_CAPIEN_CAPFIENn_Pos (8) |
PWM_T::CAPIEN: CAPFIENn Position
| #define PWM_CAPIEN_CAPRIENn_Msk (0x3ful << PWM_CAPIEN_CAPRIENn_Pos) |
PWM_T::CAPIEN: CAPRIENn Mask
| #define PWM_CAPIEN_CAPRIENn_Pos (0) |
PWM_T::CAPIEN: CAPRIENn Position
| #define PWM_CAPIF_CAPFIFn_Msk (0x3ful << PWM_CAPIF_CAPFIFn_Pos) |
PWM_T::CAPIF: CAPFIFn Mask
| #define PWM_CAPIF_CAPFIFn_Pos (8) |
PWM_T::CAPIF: CAPFIFn Position
| #define PWM_CAPIF_CAPRIFn_Msk (0x3ful << PWM_CAPIF_CAPRIFn_Pos) |
PWM_T::CAPIF: CAPRIFn Mask
| #define PWM_CAPIF_CAPRIFn_Pos (0) |
PWM_T::CAPIF: CAPRIFn Position
| #define PWM_CAPINEN_CAPINENn_Msk (0x3ful << PWM_CAPINEN_CAPINENn_Pos) |
PWM_T::CAPINEN: CAPINENn Mask
| #define PWM_CAPINEN_CAPINENn_Pos (0) |
PWM_T::CAPINEN: CAPINENn Position
| #define PWM_CAPSTS_CFIFOVn_Msk (0x3ful << PWM_CAPSTS_CFIFOVn_Pos) |
PWM_T::CAPSTS: CFIFOVn Mask
| #define PWM_CAPSTS_CFIFOVn_Pos (8) |
PWM_T::CAPSTS: CFIFOVn Position
| #define PWM_CAPSTS_CRIFOVn_Msk (0x3ful << PWM_CAPSTS_CRIFOVn_Pos) |
PWM_T::CAPSTS: CRIFOVn Mask
| #define PWM_CAPSTS_CRIFOVn_Pos (0) |
PWM_T::CAPSTS: CRIFOVn Position
| #define PWM_CLKPSC0_1_CLKPSC_Msk (0xffful << PWM_CLKPSC0_1_CLKPSC_Pos) |
PWM_T::CLKPSC0_1: CLKPSC Mask
| #define PWM_CLKPSC0_1_CLKPSC_Pos (0) |
PWM_T::CLKPSC0_1: CLKPSC Position
| #define PWM_CLKPSC2_3_CLKPSC_Msk (0xffful << PWM_CLKPSC2_3_CLKPSC_Pos) |
PWM_T::CLKPSC2_3: CLKPSC Mask
| #define PWM_CLKPSC2_3_CLKPSC_Pos (0) |
PWM_T::CLKPSC2_3: CLKPSC Position
| #define PWM_CLKPSC4_5_CLKPSC_Msk (0xffful << PWM_CLKPSC4_5_CLKPSC_Pos) |
PWM_T::CLKPSC4_5: CLKPSC Mask
| #define PWM_CLKPSC4_5_CLKPSC_Pos (0) |
PWM_T::CLKPSC4_5: CLKPSC Position
| #define PWM_CLKSRC_ECLKSRC0_Msk (0x7ul << PWM_CLKSRC_ECLKSRC0_Pos) |
PWM_T::CLKSRC: ECLKSRC0 Mask
| #define PWM_CLKSRC_ECLKSRC0_Pos (0) |
PWM_T::CLKSRC: ECLKSRC0 Position
| #define PWM_CLKSRC_ECLKSRC2_Msk (0x7ul << PWM_CLKSRC_ECLKSRC2_Pos) |
PWM_T::CLKSRC: ECLKSRC2 Mask
| #define PWM_CLKSRC_ECLKSRC2_Pos (8) |
PWM_T::CLKSRC: ECLKSRC2 Position
| #define PWM_CLKSRC_ECLKSRC4_Msk (0x7ul << PWM_CLKSRC_ECLKSRC4_Pos) |
PWM_T::CLKSRC: ECLKSRC4 Mask
| #define PWM_CLKSRC_ECLKSRC4_Pos (16) |
PWM_T::CLKSRC: ECLKSRC4 Position
| #define PWM_CMPBUF0_CMPBUF_Msk (0xfffful << PWM_CMPBUF0_CMPBUF_Pos) |
PWM_T::CMPBUF0: CMPBUF Mask
| #define PWM_CMPBUF0_CMPBUF_Pos (0) |
PWM_T::CMPBUF0: CMPBUF Position
| #define PWM_CMPBUF1_CMPBUF_Msk (0xfffful << PWM_CMPBUF1_CMPBUF_Pos) |
PWM_T::CMPBUF1: CMPBUF Mask
| #define PWM_CMPBUF1_CMPBUF_Pos (0) |
PWM_T::CMPBUF1: CMPBUF Position
| #define PWM_CMPBUF2_CMPBUF_Msk (0xfffful << PWM_CMPBUF2_CMPBUF_Pos) |
PWM_T::CMPBUF2: CMPBUF Mask
| #define PWM_CMPBUF2_CMPBUF_Pos (0) |
PWM_T::CMPBUF2: CMPBUF Position
| #define PWM_CMPBUF3_CMPBUF_Msk (0xfffful << PWM_CMPBUF3_CMPBUF_Pos) |
PWM_T::CMPBUF3: CMPBUF Mask
| #define PWM_CMPBUF3_CMPBUF_Pos (0) |
PWM_T::CMPBUF3: CMPBUF Position
| #define PWM_CMPBUF4_CMPBUF_Msk (0xfffful << PWM_CMPBUF4_CMPBUF_Pos) |
PWM_T::CMPBUF4: CMPBUF Mask
| #define PWM_CMPBUF4_CMPBUF_Pos (0) |
PWM_T::CMPBUF4: CMPBUF Position
| #define PWM_CMPBUF5_CMPBUF_Msk (0xfffful << PWM_CMPBUF5_CMPBUF_Pos) |
PWM_T::CMPBUF5: CMPBUF Mask
| #define PWM_CMPBUF5_CMPBUF_Pos (0) |
PWM_T::CMPBUF5: CMPBUF Position
| #define PWM_CMPDAT0_CMPDAT_Msk (0xfffful << PWM_CMPDAT0_CMPDAT_Pos) |
PWM_T::CMPDAT: CMPDAT Mask
| #define PWM_CMPDAT0_CMPDAT_Pos (0) |
PWM_T::CMPDAT: CMPDAT Position
| #define PWM_CNT0_CNT_Msk (0xfffful << PWM_CNT0_CNT_Pos) |
PWM_T::CNT: CNT Mask
| #define PWM_CNT0_CNT_Pos (0) |
PWM_T::CNT: CNT Position
| #define PWM_CNT0_DIRF_Msk (0x1ul << PWM_CNT0_DIRF_Pos) |
PWM_T::CNT: DIRF Mask
| #define PWM_CNT0_DIRF_Pos (16) |
PWM_T::CNT: DIRF Position
| #define PWM_CNTCLR_CNTCLR0_Msk (0x1ul << PWM_CNTCLR_CNTCLR0_Pos) |
PWM_T::CNTCLR: CNTCLR0 Mask
| #define PWM_CNTCLR_CNTCLR0_Pos (0) |
PWM_T::CNTCLR: CNTCLR0 Position
| #define PWM_CNTCLR_CNTCLR2_Msk (0x1ul << PWM_CNTCLR_CNTCLR2_Pos) |
PWM_T::CNTCLR: CNTCLR2 Mask
| #define PWM_CNTCLR_CNTCLR2_Pos (2) |
PWM_T::CNTCLR: CNTCLR2 Position
| #define PWM_CNTCLR_CNTCLR4_Msk (0x1ul << PWM_CNTCLR_CNTCLR4_Pos) |
PWM_T::CNTCLR: CNTCLR4 Mask
| #define PWM_CNTCLR_CNTCLR4_Pos (4) |
PWM_T::CNTCLR: CNTCLR4 Position
| #define PWM_CNTEN_CNTEN0_Msk (0x1ul << PWM_CNTEN_CNTEN0_Pos) |
PWM_T::CNTEN: CNTEN0 Mask
| #define PWM_CNTEN_CNTEN0_Pos (0) |
PWM_T::CNTEN: CNTEN0 Position
| #define PWM_CNTEN_CNTEN2_Msk (0x1ul << PWM_CNTEN_CNTEN2_Pos) |
PWM_T::CNTEN: CNTEN2 Mask
| #define PWM_CNTEN_CNTEN2_Pos (2) |
PWM_T::CNTEN: CNTEN2 Position
| #define PWM_CNTEN_CNTEN4_Msk (0x1ul << PWM_CNTEN_CNTEN4_Pos) |
PWM_T::CNTEN: CNTEN4 Mask
| #define PWM_CNTEN_CNTEN4_Pos (4) |
PWM_T::CNTEN: CNTEN4 Position
| #define PWM_CTL0_CTRLDn_Msk (0x3ful << PWM_CTL0_CTRLDn_Pos) |
PWM_T::CTL0: CTRLDn Mask
| #define PWM_CTL0_CTRLDn_Pos (0) |
@addtogroup PWM_CONST PWM Bit Field Definition Constant Definitions for PWM Controller
PWM_T::CTL0: CTRLDn Position
| #define PWM_CTL0_DBGHALT_Msk (0x1ul << PWM_CTL0_DBGHALT_Pos) |
PWM_T::CTL0: DBGHALT Mask
| #define PWM_CTL0_DBGHALT_Pos (30) |
PWM_T::CTL0: DBGHALT Position
| #define PWM_CTL0_DBGTRIOFF_Msk (0x1ul << PWM_CTL0_DBGTRIOFF_Pos) |
PWM_T::CTL0: DBGTRIOFF Mask
| #define PWM_CTL0_DBGTRIOFF_Pos (31) |
PWM_T::CTL0: DBGTRIOFF Position
| #define PWM_CTL0_IMMLDENn_Msk (0x3ful << PWM_CTL0_IMMLDENn_Pos) |
PWM_T::CTL0: IMMLDENn Mask
| #define PWM_CTL0_IMMLDENn_Pos (16) |
PWM_T::CTL0: IMMLDENn Position
| #define PWM_CTL1_CNTTYPE0_Msk (0x3ul << PWM_CTL1_CNTTYPE0_Pos) |
PWM_T::CTL1: CNTTYPE0 Mask
| #define PWM_CTL1_CNTTYPE0_Pos (0) |
PWM_T::CTL1: CNTTYPE0 Position
| #define PWM_CTL1_CNTTYPE2_Msk (0x3ul << PWM_CTL1_CNTTYPE2_Pos) |
PWM_T::CTL1: CNTTYPE2 Mask
| #define PWM_CTL1_CNTTYPE2_Pos (4) |
PWM_T::CTL1: CNTTYPE2 Position
| #define PWM_CTL1_CNTTYPE4_Msk (0x3ul << PWM_CTL1_CNTTYPE4_Pos) |
PWM_T::CTL1: CNTTYPE4 Mask
| #define PWM_CTL1_CNTTYPE4_Pos (8) |
PWM_T::CTL1: CNTTYPE4 Position
| #define PWM_CTL1_PWMMODEn_Msk (0x7ul << PWM_CTL1_PWMMODEn_Pos) |
PWM_T::CTL1: PWMMODEn Mask
| #define PWM_CTL1_PWMMODEn_Pos (24) |
PWM_T::CTL1: PWMMODEn Position
| #define PWM_DTCTL0_1_DTCKSEL_Msk (0x1ul << PWM_DTCTL0_1_DTCKSEL_Pos) |
PWM_T::DTCTL0_1: DTCKSEL Mask
| #define PWM_DTCTL0_1_DTCKSEL_Pos (24) |
PWM_T::DTCTL0_1: DTCKSEL Position
| #define PWM_DTCTL0_1_DTCNT_Msk (0xffful << PWM_DTCTL0_1_DTCNT_Pos) |
PWM_T::DTCTL0_1: DTCNT Mask
| #define PWM_DTCTL0_1_DTCNT_Pos (0) |
PWM_T::DTCTL0_1: DTCNT Position
| #define PWM_DTCTL0_1_DTEN_Msk (0x1ul << PWM_DTCTL0_1_DTEN_Pos) |
PWM_T::DTCTL0_1: DTEN Mask
| #define PWM_DTCTL0_1_DTEN_Pos (16) |
PWM_T::DTCTL0_1: DTEN Position
| #define PWM_DTCTL2_3_DTCKSEL_Msk (0x1ul << PWM_DTCTL2_3_DTCKSEL_Pos) |
PWM_T::DTCTL2_3: DTCKSEL Mask
| #define PWM_DTCTL2_3_DTCKSEL_Pos (24) |
PWM_T::DTCTL2_3: DTCKSEL Position
| #define PWM_DTCTL2_3_DTCNT_Msk (0xffful << PWM_DTCTL2_3_DTCNT_Pos) |
PWM_T::DTCTL2_3: DTCNT Mask
| #define PWM_DTCTL2_3_DTCNT_Pos (0) |
PWM_T::DTCTL2_3: DTCNT Position
| #define PWM_DTCTL2_3_DTEN_Msk (0x1ul << PWM_DTCTL2_3_DTEN_Pos) |
PWM_T::DTCTL2_3: DTEN Mask
| #define PWM_DTCTL2_3_DTEN_Pos (16) |
PWM_T::DTCTL2_3: DTEN Position
| #define PWM_DTCTL4_5_DTCKSEL_Msk (0x1ul << PWM_DTCTL4_5_DTCKSEL_Pos) |
PWM_T::DTCTL4_5: DTCKSEL Mask
| #define PWM_DTCTL4_5_DTCKSEL_Pos (24) |
PWM_T::DTCTL4_5: DTCKSEL Position
| #define PWM_DTCTL4_5_DTCNT_Msk (0xffful << PWM_DTCTL4_5_DTCNT_Pos) |
PWM_T::DTCTL4_5: DTCNT Mask
| #define PWM_DTCTL4_5_DTCNT_Pos (0) |
PWM_T::DTCTL4_5: DTCNT Position
| #define PWM_DTCTL4_5_DTEN_Msk (0x1ul << PWM_DTCTL4_5_DTEN_Pos) |
PWM_T::DTCTL4_5: DTEN Mask
| #define PWM_DTCTL4_5_DTEN_Pos (16) |
PWM_T::DTCTL4_5: DTEN Position
| #define PWM_FAILBRK_BODBRKEN_Msk (0x1ul << PWM_FAILBRK_BODBRKEN_Pos) |
PWM_T::FAILBRK: BODBRKEN Mask
| #define PWM_FAILBRK_BODBRKEN_Pos (1) |
PWM_T::FAILBRK: BODBRKEN Position
| #define PWM_FAILBRK_CORBRKEN_Msk (0x1ul << PWM_FAILBRK_CORBRKEN_Pos) |
PWM_T::FAILBRK: CORBRKEN Mask
| #define PWM_FAILBRK_CORBRKEN_Pos (3) |
PWM_T::FAILBRK: CORBRKEN Position
| #define PWM_FCAPDAT0_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT0_FCAPDAT_Pos) |
PWM_T::FCAPDAT0: FCAPDAT Mask
| #define PWM_FCAPDAT0_FCAPDAT_Pos (0) |
PWM_T::FCAPDAT0: FCAPDAT Position
| #define PWM_FCAPDAT1_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT1_FCAPDAT_Pos) |
PWM_T::FCAPDAT1: FCAPDAT Mask
| #define PWM_FCAPDAT1_FCAPDAT_Pos (0) |
PWM_T::FCAPDAT1: FCAPDAT Position
| #define PWM_FCAPDAT2_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT2_FCAPDAT_Pos) |
PWM_T::FCAPDAT2: FCAPDAT Mask
| #define PWM_FCAPDAT2_FCAPDAT_Pos (0) |
PWM_T::FCAPDAT2: FCAPDAT Position
| #define PWM_FCAPDAT3_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT3_FCAPDAT_Pos) |
PWM_T::FCAPDAT3: FCAPDAT Mask
| #define PWM_FCAPDAT3_FCAPDAT_Pos (0) |
PWM_T::FCAPDAT3: FCAPDAT Position
| #define PWM_FCAPDAT4_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT4_FCAPDAT_Pos) |
PWM_T::FCAPDAT4: FCAPDAT Mask
| #define PWM_FCAPDAT4_FCAPDAT_Pos (0) |
PWM_T::FCAPDAT4: FCAPDAT Position
| #define PWM_FCAPDAT5_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT5_FCAPDAT_Pos) |
PWM_T::FCAPDAT5: FCAPDAT Mask
| #define PWM_FCAPDAT5_FCAPDAT_Pos (0) |
PWM_T::FCAPDAT5: FCAPDAT Position
| #define PWM_INTEN0_CMPDIENn_Msk (0x3ful << PWM_INTEN0_CMPDIENn_Pos) |
PWM_T::INTEN0: CMPDIENn Mask
| #define PWM_INTEN0_CMPDIENn_Pos (24) |
PWM_T::INTEN0: CMPDIENn Position
| #define PWM_INTEN0_CMPUIENn_Msk (0x3ful << PWM_INTEN0_CMPUIENn_Pos) |
PWM_T::INTEN0: CMPUIENn Mask
| #define PWM_INTEN0_CMPUIENn_Pos (16) |
PWM_T::INTEN0: CMPUIENn Position
| #define PWM_INTEN0_PIEN0_Msk (0x1ul << PWM_INTEN0_PIEN0_Pos) |
PWM_T::INTEN0: PIEN0 Mask
| #define PWM_INTEN0_PIEN0_Pos (8) |
PWM_T::INTEN0: PIEN0 Position
| #define PWM_INTEN0_PIEN2_Msk (0x1ul << PWM_INTEN0_PIEN2_Pos) |
PWM_T::INTEN0: PIEN2 Mask
| #define PWM_INTEN0_PIEN2_Pos (10) |
PWM_T::INTEN0: PIEN2 Position
| #define PWM_INTEN0_PIEN4_Msk (0x1ul << PWM_INTEN0_PIEN4_Pos) |
PWM_T::INTEN0: PIEN4 Mask
| #define PWM_INTEN0_PIEN4_Pos (12) |
PWM_T::INTEN0: PIEN4 Position
| #define PWM_INTEN0_ZIEN0_Msk (0x1ul << PWM_INTEN0_ZIEN0_Pos) |
PWM_T::INTEN0: ZIEN0 Mask
| #define PWM_INTEN0_ZIEN0_Pos (0) |
PWM_T::INTEN0: ZIEN0 Position
| #define PWM_INTEN0_ZIEN2_Msk (0x1ul << PWM_INTEN0_ZIEN2_Pos) |
PWM_T::INTEN0: ZIEN2 Mask
| #define PWM_INTEN0_ZIEN2_Pos (2) |
PWM_T::INTEN0: ZIEN2 Position
| #define PWM_INTEN0_ZIEN4_Msk (0x1ul << PWM_INTEN0_ZIEN4_Pos) |
PWM_T::INTEN0: ZIEN4 Mask
| #define PWM_INTEN0_ZIEN4_Pos (4) |
PWM_T::INTEN0: ZIEN4 Position
| #define PWM_INTEN1_BRKEIEN0_1_Msk (0x1ul << PWM_INTEN1_BRKEIEN0_1_Pos) |
PWM_T::INTEN1: BRKEIEN0_1 Mask
| #define PWM_INTEN1_BRKEIEN0_1_Pos (0) |
PWM_T::INTEN1: BRKEIEN0_1 Position
| #define PWM_INTEN1_BRKEIEN2_3_Msk (0x1ul << PWM_INTEN1_BRKEIEN2_3_Pos) |
PWM_T::INTEN1: BRKEIEN2_3 Mask
| #define PWM_INTEN1_BRKEIEN2_3_Pos (1) |
PWM_T::INTEN1: BRKEIEN2_3 Position
| #define PWM_INTEN1_BRKEIEN4_5_Msk (0x1ul << PWM_INTEN1_BRKEIEN4_5_Pos) |
PWM_T::INTEN1: BRKEIEN4_5 Mask
| #define PWM_INTEN1_BRKEIEN4_5_Pos (2) |
PWM_T::INTEN1: BRKEIEN4_5 Position
| #define PWM_INTEN1_BRKLIEN0_1_Msk (0x1ul << PWM_INTEN1_BRKLIEN0_1_Pos) |
PWM_T::INTEN1: BRKLIEN0_1 Mask
| #define PWM_INTEN1_BRKLIEN0_1_Pos (8) |
PWM_T::INTEN1: BRKLIEN0_1 Position
| #define PWM_INTEN1_BRKLIEN2_3_Msk (0x1ul << PWM_INTEN1_BRKLIEN2_3_Pos) |
PWM_T::INTEN1: BRKLIEN2_3 Mask
| #define PWM_INTEN1_BRKLIEN2_3_Pos (9) |
PWM_T::INTEN1: BRKLIEN2_3 Position
| #define PWM_INTEN1_BRKLIEN4_5_Msk (0x1ul << PWM_INTEN1_BRKLIEN4_5_Pos) |
PWM_T::INTEN1: BRKLIEN4_5 Mask
| #define PWM_INTEN1_BRKLIEN4_5_Pos (10) |
PWM_T::INTEN1: BRKLIEN4_5 Position
| #define PWM_INTSTS0_CMPDIFn_Msk (0x3ful << PWM_INTSTS0_CMPDIFn_Pos) |
PWM_T::INTSTS0: CMPDIFn Mask
| #define PWM_INTSTS0_CMPDIFn_Pos (24) |
PWM_T::INTSTS0: CMPDIFn Position
| #define PWM_INTSTS0_CMPUIFn_Msk (0x3ful << PWM_INTSTS0_CMPUIFn_Pos) |
PWM_T::INTSTS0: CMPUIFn Mask
| #define PWM_INTSTS0_CMPUIFn_Pos (16) |
PWM_T::INTSTS0: CMPUIFn Position
| #define PWM_INTSTS0_PIF0_Msk (0x1ul << PWM_INTSTS0_PIF0_Pos) |
PWM_T::INTSTS0: PIF0 Mask
| #define PWM_INTSTS0_PIF0_Pos (8) |
PWM_T::INTSTS0: PIF0 Position
| #define PWM_INTSTS0_PIF2_Msk (0x1ul << PWM_INTSTS0_PIF2_Pos) |
PWM_T::INTSTS0: PIF2 Mask
| #define PWM_INTSTS0_PIF2_Pos (10) |
PWM_T::INTSTS0: PIF2 Position
| #define PWM_INTSTS0_PIF4_Msk (0x1ul << PWM_INTSTS0_PIF4_Pos) |
PWM_T::INTSTS0: PIF4 Mask
| #define PWM_INTSTS0_PIF4_Pos (12) |
PWM_T::INTSTS0: PIF4 Position
| #define PWM_INTSTS0_ZIF0_Msk (0x1ul << PWM_INTSTS0_ZIF0_Pos) |
PWM_T::INTSTS0: ZIF0 Mask
| #define PWM_INTSTS0_ZIF0_Pos (0) |
PWM_T::INTSTS0: ZIF0 Position
| #define PWM_INTSTS0_ZIF2_Msk (0x1ul << PWM_INTSTS0_ZIF2_Pos) |
PWM_T::INTSTS0: ZIF2 Mask
| #define PWM_INTSTS0_ZIF2_Pos (2) |
PWM_T::INTSTS0: ZIF2 Position
| #define PWM_INTSTS0_ZIF4_Msk (0x1ul << PWM_INTSTS0_ZIF4_Pos) |
PWM_T::INTSTS0: ZIF4 Mask
| #define PWM_INTSTS0_ZIF4_Pos (4) |
PWM_T::INTSTS0: ZIF4 Position
| #define PWM_INTSTS1_BRKEIF0_Msk (0x1ul << PWM_INTSTS1_BRKEIF0_Pos) |
PWM_T::INTSTS1: BRKEIF0 Mask
| #define PWM_INTSTS1_BRKEIF0_Pos (0) |
PWM_T::INTSTS1: BRKEIF0 Position
| #define PWM_INTSTS1_BRKEIF1_Msk (0x1ul << PWM_INTSTS1_BRKEIF1_Pos) |
PWM_T::INTSTS1: BRKEIF1 Mask
| #define PWM_INTSTS1_BRKEIF1_Pos (1) |
PWM_T::INTSTS1: BRKEIF1 Position
| #define PWM_INTSTS1_BRKEIF2_Msk (0x1ul << PWM_INTSTS1_BRKEIF2_Pos) |
PWM_T::INTSTS1: BRKEIF2 Mask
| #define PWM_INTSTS1_BRKEIF2_Pos (2) |
PWM_T::INTSTS1: BRKEIF2 Position
| #define PWM_INTSTS1_BRKEIF3_Msk (0x1ul << PWM_INTSTS1_BRKEIF3_Pos) |
PWM_T::INTSTS1: BRKEIF3 Mask
| #define PWM_INTSTS1_BRKEIF3_Pos (3) |
PWM_T::INTSTS1: BRKEIF3 Position
| #define PWM_INTSTS1_BRKEIF4_Msk (0x1ul << PWM_INTSTS1_BRKEIF4_Pos) |
PWM_T::INTSTS1: BRKEIF4 Mask
| #define PWM_INTSTS1_BRKEIF4_Pos (4) |
PWM_T::INTSTS1: BRKEIF4 Position
| #define PWM_INTSTS1_BRKEIF5_Msk (0x1ul << PWM_INTSTS1_BRKEIF5_Pos) |
PWM_T::INTSTS1: BRKEIF5 Mask
| #define PWM_INTSTS1_BRKEIF5_Pos (5) |
PWM_T::INTSTS1: BRKEIF5 Position
| #define PWM_INTSTS1_BRKESTS0_Msk (0x1ul << PWM_INTSTS1_BRKESTS0_Pos) |
PWM_T::INTSTS1: BRKESTS0 Mask
| #define PWM_INTSTS1_BRKESTS0_Pos (16) |
PWM_T::INTSTS1: BRKESTS0 Position
| #define PWM_INTSTS1_BRKESTS1_Msk (0x1ul << PWM_INTSTS1_BRKESTS1_Pos) |
PWM_T::INTSTS1: BRKESTS1 Mask
| #define PWM_INTSTS1_BRKESTS1_Pos (17) |
PWM_T::INTSTS1: BRKESTS1 Position
| #define PWM_INTSTS1_BRKESTS2_Msk (0x1ul << PWM_INTSTS1_BRKESTS2_Pos) |
PWM_T::INTSTS1: BRKESTS2 Mask
| #define PWM_INTSTS1_BRKESTS2_Pos (18) |
PWM_T::INTSTS1: BRKESTS2 Position
| #define PWM_INTSTS1_BRKESTS3_Msk (0x1ul << PWM_INTSTS1_BRKESTS3_Pos) |
PWM_T::INTSTS1: BRKESTS3 Mask
| #define PWM_INTSTS1_BRKESTS3_Pos (19) |
PWM_T::INTSTS1: BRKESTS3 Position
| #define PWM_INTSTS1_BRKESTS4_Msk (0x1ul << PWM_INTSTS1_BRKESTS4_Pos) |
PWM_T::INTSTS1: BRKESTS4 Mask
| #define PWM_INTSTS1_BRKESTS4_Pos (20) |
PWM_T::INTSTS1: BRKESTS4 Position
| #define PWM_INTSTS1_BRKESTS5_Msk (0x1ul << PWM_INTSTS1_BRKESTS5_Pos) |
PWM_T::INTSTS1: BRKESTS5 Mask
| #define PWM_INTSTS1_BRKESTS5_Pos (21) |
PWM_T::INTSTS1: BRKESTS5 Position
| #define PWM_INTSTS1_BRKLIF0_Msk (0x1ul << PWM_INTSTS1_BRKLIF0_Pos) |
PWM_T::INTSTS1: BRKLIF0 Mask
| #define PWM_INTSTS1_BRKLIF0_Pos (8) |
PWM_T::INTSTS1: BRKLIF0 Position
| #define PWM_INTSTS1_BRKLIF1_Msk (0x1ul << PWM_INTSTS1_BRKLIF1_Pos) |
PWM_T::INTSTS1: BRKLIF1 Mask
| #define PWM_INTSTS1_BRKLIF1_Pos (9) |
PWM_T::INTSTS1: BRKLIF1 Position
| #define PWM_INTSTS1_BRKLIF2_Msk (0x1ul << PWM_INTSTS1_BRKLIF2_Pos) |
PWM_T::INTSTS1: BRKLIF2 Mask
| #define PWM_INTSTS1_BRKLIF2_Pos (10) |
PWM_T::INTSTS1: BRKLIF2 Position
| #define PWM_INTSTS1_BRKLIF3_Msk (0x1ul << PWM_INTSTS1_BRKLIF3_Pos) |
PWM_T::INTSTS1: BRKLIF3 Mask
| #define PWM_INTSTS1_BRKLIF3_Pos (11) |
PWM_T::INTSTS1: BRKLIF3 Position
| #define PWM_INTSTS1_BRKLIF4_Msk (0x1ul << PWM_INTSTS1_BRKLIF4_Pos) |
PWM_T::INTSTS1: BRKLIF4 Mask
| #define PWM_INTSTS1_BRKLIF4_Pos (12) |
PWM_T::INTSTS1: BRKLIF4 Position
| #define PWM_INTSTS1_BRKLIF5_Msk (0x1ul << PWM_INTSTS1_BRKLIF5_Pos) |
PWM_T::INTSTS1: BRKLIF5 Mask
| #define PWM_INTSTS1_BRKLIF5_Pos (13) |
PWM_T::INTSTS1: BRKLIF5 Position
| #define PWM_INTSTS1_BRKLSTS0_Msk (0x1ul << PWM_INTSTS1_BRKLSTS0_Pos) |
PWM_T::INTSTS1: BRKLSTS0 Mask
| #define PWM_INTSTS1_BRKLSTS0_Pos (24) |
PWM_T::INTSTS1: BRKLSTS0 Position
| #define PWM_INTSTS1_BRKLSTS1_Msk (0x1ul << PWM_INTSTS1_BRKLSTS1_Pos) |
PWM_T::INTSTS1: BRKLSTS1 Mask
| #define PWM_INTSTS1_BRKLSTS1_Pos (25) |
PWM_T::INTSTS1: BRKLSTS1 Position
| #define PWM_INTSTS1_BRKLSTS2_Msk (0x1ul << PWM_INTSTS1_BRKLSTS2_Pos) |
PWM_T::INTSTS1: BRKLSTS2 Mask
| #define PWM_INTSTS1_BRKLSTS2_Pos (26) |
PWM_T::INTSTS1: BRKLSTS2 Position
| #define PWM_INTSTS1_BRKLSTS3_Msk (0x1ul << PWM_INTSTS1_BRKLSTS3_Pos) |
PWM_T::INTSTS1: BRKLSTS3 Mask
| #define PWM_INTSTS1_BRKLSTS3_Pos (27) |
PWM_T::INTSTS1: BRKLSTS3 Position
| #define PWM_INTSTS1_BRKLSTS4_Msk (0x1ul << PWM_INTSTS1_BRKLSTS4_Pos) |
PWM_T::INTSTS1: BRKLSTS4 Mask
| #define PWM_INTSTS1_BRKLSTS4_Pos (28) |
PWM_T::INTSTS1: BRKLSTS4 Position
| #define PWM_INTSTS1_BRKLSTS5_Msk (0x1ul << PWM_INTSTS1_BRKLSTS5_Pos) |
PWM_T::INTSTS1: BRKLSTS5 Mask
| #define PWM_INTSTS1_BRKLSTS5_Pos (29) |
PWM_T::INTSTS1: BRKLSTS5 Position
| #define PWM_MSK_MSKDATn_Msk (0x3ful << PWM_MSK_MSKDATn_Pos) |
PWM_T::MSK: MSKDATn Mask
| #define PWM_MSK_MSKDATn_Pos (0) |
PWM_T::MSK: MSKDATn Position
| #define PWM_MSKEN_MSKENn_Msk (0x3ful << PWM_MSKEN_MSKENn_Pos) |
PWM_T::MSKEN: MSKENn Mask
| #define PWM_MSKEN_MSKENn_Pos (0) |
PWM_T::MSKEN: MSKENn Position
| #define PWM_PBUF0_PBUF_Msk (0xfffful << PWM_PBUF0_PBUF_Pos) |
PWM_T::PBUF0: PBUF Mask
| #define PWM_PBUF0_PBUF_Pos (0) |
PWM_T::PBUF0: PBUF Position
| #define PWM_PBUF2_PBUF_Msk (0xfffful << PWM_PBUF2_PBUF_Pos) |
PWM_T::PBUF2: PBUF Mask
| #define PWM_PBUF2_PBUF_Pos (0) |
PWM_T::PBUF2: PBUF Position
| #define PWM_PBUF4_PBUF_Msk (0xfffful << PWM_PBUF4_PBUF_Pos) |
PWM_T::PBUF4: PBUF Mask
| #define PWM_PBUF4_PBUF_Pos (0) |
PWM_T::PBUF4: PBUF Position
| #define PWM_PERIOD0_PERIOD_Msk (0xfffful << PWM_PERIOD0_PERIOD_Pos) |
PWM_T::PERIOD: PERIOD Mask
| #define PWM_PERIOD0_PERIOD_Pos (0) |
PWM_T::PERIOD: PERIOD Position
| #define PWM_POEN_POENn_Msk (0x3ful << PWM_POEN_POENn_Pos) |
PWM_T::POEN: POENn Mask
| #define PWM_POEN_POENn_Pos (0) |
PWM_T::POEN: POENn Position
| #define PWM_POLCTL_PINVn_Msk (0x3ful << PWM_POLCTL_PINVn_Pos) |
PWM_T::POLCTL: PINVn Mask
| #define PWM_POLCTL_PINVn_Pos (0) |
PWM_T::POLCTL: PINVn Position
| #define PWM_RCAPDAT0_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT0_RCAPDAT_Pos) |
PWM_T::RCAPDAT0: RCAPDAT Mask
| #define PWM_RCAPDAT0_RCAPDAT_Pos (0) |
PWM_T::RCAPDAT0: RCAPDAT Position
| #define PWM_RCAPDAT1_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT1_RCAPDAT_Pos) |
PWM_T::RCAPDAT1: RCAPDAT Mask
| #define PWM_RCAPDAT1_RCAPDAT_Pos (0) |
PWM_T::RCAPDAT1: RCAPDAT Position
| #define PWM_RCAPDAT2_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT2_RCAPDAT_Pos) |
PWM_T::RCAPDAT2: RCAPDAT Mask
| #define PWM_RCAPDAT2_RCAPDAT_Pos (0) |
PWM_T::RCAPDAT2: RCAPDAT Position
| #define PWM_RCAPDAT3_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT3_RCAPDAT_Pos) |
PWM_T::RCAPDAT3: RCAPDAT Mask
| #define PWM_RCAPDAT3_RCAPDAT_Pos (0) |
PWM_T::RCAPDAT3: RCAPDAT Position
| #define PWM_RCAPDAT4_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT4_RCAPDAT_Pos) |
PWM_T::RCAPDAT4: RCAPDAT Mask
| #define PWM_RCAPDAT4_RCAPDAT_Pos (0) |
PWM_T::RCAPDAT4: RCAPDAT Position
| #define PWM_RCAPDAT5_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT5_RCAPDAT_Pos) |
PWM_T::RCAPDAT5: RCAPDAT Mask
| #define PWM_RCAPDAT5_RCAPDAT_Pos (0) |
PWM_T::RCAPDAT5: RCAPDAT Position
| #define PWM_STATUS_ADCTRGn_Msk (0x3ful << PWM_STATUS_ADCTRGn_Pos) |
PWM_T::STATUS: ADCTRGn Mask
| #define PWM_STATUS_ADCTRGn_Pos (16) |
PWM_T::STATUS: ADCTRGn Position
| #define PWM_STATUS_CNTMAX0_Msk (0x1ul << PWM_STATUS_CNTMAX0_Pos) |
PWM_T::STATUS: CNTMAX0 Mask
| #define PWM_STATUS_CNTMAX0_Pos (0) |
PWM_T::STATUS: CNTMAX0 Position
| #define PWM_STATUS_CNTMAX2_Msk (0x1ul << PWM_STATUS_CNTMAX2_Pos) |
PWM_T::STATUS: CNTMAX2 Mask
| #define PWM_STATUS_CNTMAX2_Pos (2) |
PWM_T::STATUS: CNTMAX2 Position
| #define PWM_STATUS_CNTMAX4_Msk (0x1ul << PWM_STATUS_CNTMAX4_Pos) |
PWM_T::STATUS: CNTMAX4 Mask
| #define PWM_STATUS_CNTMAX4_Pos (4) |
PWM_T::STATUS: CNTMAX4 Position
| #define PWM_SWBRK_BRKETRGn_Msk (0x7ul << PWM_SWBRK_BRKETRGn_Pos) |
PWM_T::SWBRK: BRKETRGn Mask
| #define PWM_SWBRK_BRKETRGn_Pos (0) |
PWM_T::SWBRK: BRKETRGn Position
| #define PWM_SWBRK_BRKLTRGn_Msk (0x7ul << PWM_SWBRK_BRKLTRGn_Pos) |
PWM_T::SWBRK: BRKLTRGn Mask
| #define PWM_SWBRK_BRKLTRGn_Pos (8) |
PWM_T::SWBRK: BRKLTRGn Position
| #define PWM_WGCTL0_PRDPCTLn_Msk (0xffful << PWM_WGCTL0_PRDPCTLn_Pos) |
PWM_T::WGCTL0: PRDPCTLn Mask
| #define PWM_WGCTL0_PRDPCTLn_Pos (16) |
PWM_T::WGCTL0: PRDPCTLn Position
| #define PWM_WGCTL0_ZPCTLn_Msk (0xffful << PWM_WGCTL0_ZPCTLn_Pos) |
PWM_T::WGCTL0: ZPCTLn Mask
| #define PWM_WGCTL0_ZPCTLn_Pos (0) |
PWM_T::WGCTL0: ZPCTLn Position
| #define PWM_WGCTL1_CMPDCTLn_Msk (0xffful << PWM_WGCTL1_CMPDCTLn_Pos) |
PWM_T::WGCTL1: CMPDCTLn Mask
| #define PWM_WGCTL1_CMPDCTLn_Pos (16) |
PWM_T::WGCTL1: CMPDCTLn Position
| #define PWM_WGCTL1_CMPUCTLn_Msk (0xffful << PWM_WGCTL1_CMPUCTLn_Pos) |
PWM_T::WGCTL1: CMPUCTLn Mask
| #define PWM_WGCTL1_CMPUCTLn_Pos (0) |
PWM_T::WGCTL1: CMPUCTLn Position
| #define RTC_CAL_DAY_Msk (0xful << RTC_CAL_DAY_Pos) |
RTC_T::CAL: DAY Mask
| #define RTC_CAL_DAY_Pos (0) |
RTC_T::CAL: DAY Position
| #define RTC_CAL_MON_Msk (0xful << RTC_CAL_MON_Pos) |
RTC_T::CAL: MON Mask
| #define RTC_CAL_MON_Pos (8) |
RTC_T::CAL: MON Position
| #define RTC_CAL_TENDAY_Msk (0x3ul << RTC_CAL_TENDAY_Pos) |
RTC_T::CAL: TENDAY Mask
| #define RTC_CAL_TENDAY_Pos (4) |
RTC_T::CAL: TENDAY Position
| #define RTC_CAL_TENMON_Msk (0x1ul << RTC_CAL_TENMON_Pos) |
RTC_T::CAL: TENMON Mask
| #define RTC_CAL_TENMON_Pos (12) |
RTC_T::CAL: TENMON Position
| #define RTC_CAL_TENYEAR_Msk (0xful << RTC_CAL_TENYEAR_Pos) |
RTC_T::CAL: TENYEAR Mask
| #define RTC_CAL_TENYEAR_Pos (20) |
RTC_T::CAL: TENYEAR Position
| #define RTC_CAL_YEAR_Msk (0xful << RTC_CAL_YEAR_Pos) |
RTC_T::CAL: YEAR Mask
| #define RTC_CAL_YEAR_Pos (16) |
RTC_T::CAL: YEAR Position
| #define RTC_CALM_DAY_Msk (0xful << RTC_CALM_DAY_Pos) |
RTC_T::CALM: DAY Mask
| #define RTC_CALM_DAY_Pos (0) |
RTC_T::CALM: DAY Position
| #define RTC_CALM_MON_Msk (0xful << RTC_CALM_MON_Pos) |
RTC_T::CALM: MON Mask
| #define RTC_CALM_MON_Pos (8) |
RTC_T::CALM: MON Position
| #define RTC_CALM_TENDAY_Msk (0x3ul << RTC_CALM_TENDAY_Pos) |
RTC_T::CALM: TENDAY Mask
| #define RTC_CALM_TENDAY_Pos (4) |
RTC_T::CALM: TENDAY Position
| #define RTC_CALM_TENMON_Msk (0x1ul << RTC_CALM_TENMON_Pos) |
RTC_T::CALM: TENMON Mask
| #define RTC_CALM_TENMON_Pos (12) |
RTC_T::CALM: TENMON Position
| #define RTC_CALM_TENYEAR_Msk (0xful << RTC_CALM_TENYEAR_Pos) |
RTC_T::CALM: TENYEAR Mask
| #define RTC_CALM_TENYEAR_Pos (20) |
RTC_T::CALM: TENYEAR Position
| #define RTC_CALM_YEAR_Msk (0xful << RTC_CALM_YEAR_Pos) |
RTC_T::CALM: YEAR Mask
| #define RTC_CALM_YEAR_Pos (16) |
RTC_T::CALM: YEAR Position
| #define RTC_CAMSK_MDAY_Msk (0x1ul << RTC_CAMSK_MDAY_Pos) |
RTC_T::CAMSK: MDAY Mask
| #define RTC_CAMSK_MDAY_Pos (0) |
RTC_T::CAMSK: MDAY Position
| #define RTC_CAMSK_MMON_Msk (0x1ul << RTC_CAMSK_MMON_Pos) |
RTC_T::CAMSK: MMON Mask
| #define RTC_CAMSK_MMON_Pos (2) |
RTC_T::CAMSK: MMON Position
| #define RTC_CAMSK_MTENDAY_Msk (0x1ul << RTC_CAMSK_MTENDAY_Pos) |
RTC_T::CAMSK: MTENDAY Mask
| #define RTC_CAMSK_MTENDAY_Pos (1) |
RTC_T::CAMSK: MTENDAY Position
| #define RTC_CAMSK_MTENMON_Msk (0x1ul << RTC_CAMSK_MTENMON_Pos) |
RTC_T::CAMSK: MTENMON Mask
| #define RTC_CAMSK_MTENMON_Pos (3) |
RTC_T::CAMSK: MTENMON Position
| #define RTC_CAMSK_MTENYEAR_Msk (0x1ul << RTC_CAMSK_MTENYEAR_Pos) |
RTC_T::CAMSK: MTENYEAR Mask
| #define RTC_CAMSK_MTENYEAR_Pos (5) |
RTC_T::CAMSK: MTENYEAR Position
| #define RTC_CAMSK_MYEAR_Msk (0x1ul << RTC_CAMSK_MYEAR_Pos) |
RTC_T::CAMSK: MYEAR Mask
| #define RTC_CAMSK_MYEAR_Pos (4) |
RTC_T::CAMSK: MYEAR Position
| #define RTC_CLKFMT_24HEN_Msk (0x1ul << RTC_CLKFMT_24HEN_Pos) |
RTC_T::CLKFMT: 24HEN Mask
| #define RTC_CLKFMT_24HEN_Pos (0) |
RTC_T::CLKFMT: 24HEN Position
| #define RTC_FREQADJ_FREQADJ_Msk (0x3ffffful << RTC_FCR_FCR_Pos) |
RTC_T::FREQADJ: FREQADJ Mask
| #define RTC_FREQADJ_FREQADJ_Pos (0) |
RTC_T::FREQADJ: FREQADJ Position
| #define RTC_INIT_INIT_ACTIVE_Msk (0x1ul << RTC_INIT_INIT_ACTIVE_Pos) |
RTC_T::INIT: INIT_ACTIVE Mask
| #define RTC_INIT_INIT_ACTIVE_Pos (0) |
@addtogroup RTC_CONST RTC Bit Field Definition Constant Definitions for RTC Controller
RTC_T::INIT: INIT_ACTIVE Position
| #define RTC_INIT_INIT_Msk (0x7ffffffful << RTC_INIT_INIT_Pos) |
RTC_T::INIT: INIT Mask
| #define RTC_INIT_INIT_Pos (1) |
RTC_T::INIT: INIT Position
| #define RTC_INTEN_ALMIEN_Msk (0x1ul << RTC_INTEN_ALMIEN_Pos) |
RTC_T::INTEN: ALMIEN Mask
| #define RTC_INTEN_ALMIEN_Pos (0) |
RTC_T::INTEN: ALMIEN Position
| #define RTC_INTEN_SNPDIEN_Msk (0x1ul << RTC_INTEN_SNPDIEN_Pos) |
RTC_T::INTEN: SNPDIEN Mask
| #define RTC_INTEN_SNPDIEN_Pos (2) |
RTC_T::INTEN: SNPDIEN Position
| #define RTC_INTEN_TICKIEN_Msk (0x1ul << RTC_INTEN_TICKIEN_Pos) |
RTC_T::INTEN: TICKIEN Mask
| #define RTC_INTEN_TICKIEN_Pos (1) |
RTC_T::INTEN: TICKIEN Position
| #define RTC_INTSTS_ALMIF_Msk (0x1ul << RTC_INTSTS_ALMIF_Pos) |
RTC_T::INTSTS: ALMIF Mask
| #define RTC_INTSTS_ALMIF_Pos (0) |
RTC_T::INTSTS: ALMIF Position
| #define RTC_INTSTS_SNPDIF_Msk (0x1ul << RTC_INTSTS_SNPDIF_Pos) |
RTC_T::INTSTS: SNPDIF Mask
| #define RTC_INTSTS_SNPDIF_Pos (2) |
RTC_T::INTSTS: SNPDIF Position
| #define RTC_INTSTS_TICKIF_Msk (0x1ul << RTC_INTSTS_TICKIF_Pos) |
RTC_T::INTSTS: TICKIF Mask
| #define RTC_INTSTS_TICKIF_Pos (1) |
RTC_T::INTSTS: TICKIF Position
| #define RTC_LEAPYEAR_LEAPYEAR_Msk (0x1ul << RTC_LEAPYEAR_LEAPYEAR_Pos) |
RTC_T::LEAPYEAR: LEAPYEAR Mask
| #define RTC_LEAPYEAR_LEAPYEAR_Pos (0) |
RTC_T::LEAPYEAR: LEAPYEAR Position
| #define RTC_LXTCTL_LXT_TYPE_Msk (0x1ul << RTC_LXTCTL_LXT_TYPE_Pos) |
RTC_T::LXTCTL: LXT_TYPE Mask
| #define RTC_LXTCTL_LXT_TYPE_Pos (0) |
RTC_T::LXTCTL: LXT_TYPE Position
| #define RTC_LXTICTL_CTLSEL_Msk (0x1ul << RTC_LXTICTL_CTLSEL_Pos) |
RTC_T::LXTICTL: CTLSEL Mask
| #define RTC_LXTICTL_CTLSEL_Pos (3) |
RTC_T::LXTICTL: CTLSEL Position
| #define RTC_LXTICTL_DOUT_Msk (0x1ul << RTC_LXTICTL_DOUT_Pos) |
RTC_T::LXTICTL: DOUT Mask
| #define RTC_LXTICTL_DOUT_Pos (2) |
RTC_T::LXTICTL: DOUT Position
| #define RTC_LXTICTL_OPMODE_Msk (0x3ul << RTC_LXTICTL_OPMODE_Pos) |
RTC_T::LXTICTL: OPMODE Mask
| #define RTC_LXTICTL_OPMODE_Pos (0) |
RTC_T::LXTICTL: OPMODE Position
| #define RTC_LXTOCTL_CTLSEL_Msk (0x1ul << RTC_LXTOCTL_CTLSEL_Pos) |
RTC_T::LXTOCTL: CTLSEL Mask
| #define RTC_LXTOCTL_CTLSEL_Pos (3) |
RTC_T::LXTOCTL: CTLSEL Position
| #define RTC_LXTOCTL_DOUT_Msk (0x1ul << RTC_LXTOCTL_DOUT_Pos) |
RTC_T::LXTOCTL: DOUT Mask
| #define RTC_LXTOCTL_DOUT_Pos (2) |
RTC_T::LXTOCTL: DOUT Position
| #define RTC_LXTOCTL_OPMODE_Msk (0x3ul << RTC_LXTOCTL_OPMODE_Pos) |
RTC_T::LXTOCTL: OPMODE Mask
| #define RTC_LXTOCTL_OPMODE_Pos (0) |
RTC_T::LXTOCTL: OPMODE Position
| #define RTC_MISCCTL_GAINSEL_Msk (0x3ul << RTC_MISCCTL_GAINSEL_Pos) |
RTC_T::MISCCTL: GAINSEL Mask
| #define RTC_MISCCTL_GAINSEL_Pos (12) |
RTC_T::MISCCTL: GAINSEL Position
| #define RTC_RWEN_RTCBUSY_Msk (0x1ul << RTC_RWEN_RTCBUSY_Pos) |
RTC_T::RWEN: RTCBUSY Mask
| #define RTC_RWEN_RTCBUSY_Pos (24) |
RTC_T::RWEN: RTCBUSY Position
| #define RTC_RWEN_RWEN_Msk (0xfffful << RTC_RWEN_RWEN_Pos) |
RTC_T::RWEN: RWEN Mask
| #define RTC_RWEN_RWEN_Pos (0) |
RTC_T::RWEN: RWEN Position
| #define RTC_RWEN_RWENF_Msk (0x1ul << RTC_RWEN_RWENF_Pos) |
RTC_T::RWEN: RWENF Mask
| #define RTC_RWEN_RWENF_Pos (16) |
RTC_T::RWEN: RWENF Position
| #define RTC_SPR0_SPARE_Msk (0xfffffffful << RTC_SPR0_SPARE_Pos) |
RTC_T::SPR: SPARE0 Mask
| #define RTC_SPR0_SPARE_Pos (0) |
RTC_T::SPR: SPARE0 Position
| #define RTC_SPR1_SPARE_Msk (0xfffffffful << RTC_SPR1_SPARE_Pos) |
RTC_T::SPR: SPARE1 Mask
| #define RTC_SPR1_SPARE_Pos (0) |
RTC_T::SPR: SPARE1 Position
| #define RTC_SPR2_SPARE_Msk (0xfffffffful << RTC_SPR2_SPARE_Pos) |
RTC_T::SPR: SPARE2 Mask
| #define RTC_SPR2_SPARE_Pos (0) |
RTC_T::SPR: SPARE2 Position
| #define RTC_SPR3_SPARE_Msk (0xfffffffful << RTC_SPR3_SPARE_Pos) |
RTC_T::SPR: SPARE3 Mask
| #define RTC_SPR3_SPARE_Pos (0) |
RTC_T::SPR: SPARE3 Position
| #define RTC_SPR4_SPARE_Msk (0xfffffffful << RTC_SPR4_SPARE_Pos) |
RTC_T::SPR: SPARE4 Mask
| #define RTC_SPR4_SPARE_Pos (0) |
RTC_T::SPR: SPARE4 Position
| #define RTC_SPRCTL_SNPDEN_Msk (0x1ul << RTC_SPRCTL_SNPDEN_Pos) |
RTC_T::SPRCTL: SNPDEN Mask
| #define RTC_SPRCTL_SNPDEN_Pos (0) |
RTC_T::SPRCTL: SNPDEN Position
| #define RTC_SPRCTL_SNPTYPE0_Msk (0x1ul << RTC_SPRCTL_SNPTYPE0_Pos) |
RTC_T::SPRCTL: SNPTYPE0 Mask
| #define RTC_SPRCTL_SNPTYPE0_Pos (1) |
RTC_T::SPRCTL: SNPTYPE0 Position
| #define RTC_SPRCTL_SPRCSTS_Msk (0x1ul << RTC_SPRCTL_SPRCSTS_Pos) |
RTC_T::SPRCTL: SPRCSTS Mask
| #define RTC_SPRCTL_SPRCSTS_Pos (5) |
RTC_T::SPRCTL: SPRCSTS Position
| #define RTC_SPRCTL_SPRRWEN_Msk (0x1ul << RTC_SPRCTL_SPRRWEN_Pos) |
RTC_T::SPRCTL: SPRRWEN Mask
| #define RTC_SPRCTL_SPRRWEN_Pos (2) |
RTC_T::SPRCTL: SPRRWEN Position
| #define RTC_TALM_HR_Msk (0xful << RTC_TALM_HR_Pos) |
RTC_T::TALM: HR Mask
| #define RTC_TALM_HR_Pos (16) |
RTC_T::TALM: HR Position
| #define RTC_TALM_MIN_Msk (0xful << RTC_TALM_MIN_Pos) |
RTC_T::TALM: MIN Mask
| #define RTC_TALM_MIN_Pos (8) |
RTC_T::TALM: MIN Position
| #define RTC_TALM_SEC_Msk (0xful << RTC_TALM_SEC_Pos) |
RTC_T::TALM: SEC Mask
| #define RTC_TALM_SEC_Pos (0) |
RTC_T::TALM: SEC Position
| #define RTC_TALM_TENHR_Msk (0x3ul << RTC_TALM_TENHR_Pos) |
RTC_T::TALM: TENHR Mask
| #define RTC_TALM_TENHR_Pos (20) |
RTC_T::TALM: TENHR Position
| #define RTC_TALM_TENMIN_Msk (0x7ul << RTC_TALM_TENMIN_Pos) |
RTC_T::TALM: TENMIN Mask
| #define RTC_TALM_TENMIN_Pos (12) |
RTC_T::TALM: TENMIN Position
| #define RTC_TALM_TENSEC_Msk (0x7ul << RTC_TALM_TENSEC_Pos) |
RTC_T::TALM: TENSEC Mask
| #define RTC_TALM_TENSEC_Pos (4) |
RTC_T::TALM: TENSEC Position
| #define RTC_TAMPCTL_CTLSEL_Msk (0x1ul << RTC_TAMPCTL_CTLSEL_Pos) |
RTC_T::TAMPCTL: CTLSEL Mask
| #define RTC_TAMPCTL_CTLSEL_Pos (3) |
RTC_T::TAMPCTL: CTLSEL Position
| #define RTC_TAMPCTL_DOUT_Msk (0x1ul << RTC_TAMPCTL_DOUT_Pos) |
RTC_T::TAMPCTL: DOUT Mask
| #define RTC_TAMPCTL_DOUT_Pos (2) |
RTC_T::TAMPCTL: DOUT Position
| #define RTC_TAMPCTL_OPMODE_Msk (0x3ul << RTC_TAMPCTL_OPMODE_Pos) |
RTC_T::TAMPCTL: OPMODE Mask
| #define RTC_TAMPCTL_OPMODE_Pos (0) |
RTC_T::TAMPCTL: OPMODE Position
| #define RTC_TAMSK_MHR_Msk (0x1ul << RTC_TAMSK_MHR_Pos) |
RTC_T::TAMSK: MHR Mask
| #define RTC_TAMSK_MHR_Pos (4) |
RTC_T::TAMSK: MHR Position
| #define RTC_TAMSK_MMIN_Msk (0x1ul << RTC_TAMSK_MMIN_Pos) |
RTC_T::TAMSK: MMIN Mask
| #define RTC_TAMSK_MMIN_Pos (2) |
RTC_T::TAMSK: MMIN Position
| #define RTC_TAMSK_MSEC_Msk (0x1ul << RTC_TAMSK_MSEC_Pos) |
RTC_T::TAMSK: MSEC Mask
| #define RTC_TAMSK_MSEC_Pos (0) |
RTC_T::TAMSK: MSEC Position
| #define RTC_TAMSK_MTENHR_Msk (0x1ul << RTC_TAMSK_MTENHR_Pos) |
RTC_T::TAMSK: MTENHR Mask
| #define RTC_TAMSK_MTENHR_Pos (5) |
RTC_T::TAMSK: MTENHR Position
| #define RTC_TAMSK_MTENMIN_Msk (0x1ul << RTC_TAMSK_MTENMIN_Pos) |
RTC_T::TAMSK: MTENMIN Mask
| #define RTC_TAMSK_MTENMIN_Pos (3) |
RTC_T::TAMSK: MTENMIN Position
| #define RTC_TAMSK_MTENSEC_Msk (0x1ul << RTC_TAMSK_MTENSEC_Pos) |
RTC_T::TAMSK: MTENSEC Mask
| #define RTC_TAMSK_MTENSEC_Pos (1) |
RTC_T::TAMSK: MTENSEC Position
| #define RTC_TICK_TICK_Msk (0x7ul << RTC_TICK_TICK_Pos) |
RTC_T::TICK: TICK Mask
| #define RTC_TICK_TICK_Pos (0) |
RTC_T::TICK: TICK Position
| #define RTC_TIME_HR_Msk (0xful << RTC_TIME_HR_Pos) |
RTC_T::TIME: HR Mask
| #define RTC_TIME_HR_Pos (16) |
RTC_T::TIME: HR Position
| #define RTC_TIME_MIN_Msk (0xful << RTC_TIME_MIN_Pos) |
RTC_T::TIME: MIN Mask
| #define RTC_TIME_MIN_Pos (8) |
RTC_T::TIME: MIN Position
| #define RTC_TIME_SEC_Msk (0xful << RTC_TIME_SEC_Pos) |
RTC_T::TIME: SEC Mask
| #define RTC_TIME_SEC_Pos (0) |
RTC_T::TIME: SEC Position
| #define RTC_TIME_TENHR_Msk (0x3ul << RTC_TIME_TENHR_Pos) |
RTC_T::TIME: TENHR Mask
| #define RTC_TIME_TENHR_Pos (20) |
RTC_T::TIME: TENHR Position
| #define RTC_TIME_TENMIN_Msk (0x7ul << RTC_TIME_TENMIN_Pos) |
RTC_T::TIME: TENMIN Mask
| #define RTC_TIME_TENMIN_Pos (12) |
RTC_T::TIME: TENMIN Position
| #define RTC_TIME_TENSEC_Msk (0x7ul << RTC_TIME_TENSEC_Pos) |
RTC_T::TIME: TENSEC Mask
| #define RTC_TIME_TENSEC_Pos (4) |
RTC_T::TIME: TENSEC Position
| #define RTC_WEEKDAY_WEEKDAY_Msk (0x7ul << RTC_WEEKDAY_WEEKDAY_Pos) |
RTC_T::WEEKDAY: WEEKDAY Mask
| #define RTC_WEEKDAY_WEEKDAY_Pos (0) |
RTC_T::WEEKDAY: WEEKDAY Position
| #define SC_ACTCTL_T1EXT_Msk (0x1ful << SC_ACTCTL_T1EXT_Pos) |
SC_T::ACTCTL: T1EXT Mask
| #define SC_ACTCTL_T1EXT_Pos (0) |
SC_T::ACTCTL: T1EXT Position
| #define SC_ALTCTL_ACTEN_Msk (0x1ul << SC_ALTCTL_ACTEN_Pos) |
SC_T::ALTCTL: ACTEN Mask
| #define SC_ALTCTL_ACTEN_Pos (3) |
SC_T::ALTCTL: ACTEN Position
| #define SC_ALTCTL_ACTSTS0_Msk (0x1ul << SC_ALTCTL_ACTSTS0_Pos) |
SC_T::ALTCTL: ACTSTS0 Mask
| #define SC_ALTCTL_ACTSTS0_Pos (13) |
SC_T::ALTCTL: ACTSTS0 Position
| #define SC_ALTCTL_ACTSTS1_Msk (0x1ul << SC_ALTCTL_ACTSTS1_Pos) |
SC_T::ALTCTL: ACTSTS1 Mask
| #define SC_ALTCTL_ACTSTS1_Pos (14) |
SC_T::ALTCTL: ACTSTS1 Position
| #define SC_ALTCTL_ACTSTS2_Msk (0x1ul << SC_ALTCTL_ACTSTS2_Pos) |
SC_T::ALTCTL: ACTSTS2 Mask
| #define SC_ALTCTL_ACTSTS2_Pos (15) |
SC_T::ALTCTL: ACTSTS2 Position
| #define SC_ALTCTL_CNTEN0_Msk (0x1ul << SC_ALTCTL_CNTEN0_Pos) |
SC_T::ALTCTL: CNTEN0 Mask
| #define SC_ALTCTL_CNTEN0_Pos (5) |
SC_T::ALTCTL: CNTEN0 Position
| #define SC_ALTCTL_CNTEN1_Msk (0x1ul << SC_ALTCTL_CNTEN1_Pos) |
SC_T::ALTCTL: CNTEN1 Mask
| #define SC_ALTCTL_CNTEN1_Pos (6) |
SC_T::ALTCTL: CNTEN1 Position
| #define SC_ALTCTL_CNTEN2_Msk (0x1ul << SC_ALTCTL_CNTEN2_Pos) |
SC_T::ALTCTL: CNTEN2 Mask
| #define SC_ALTCTL_CNTEN2_Pos (7) |
SC_T::ALTCTL: CNTEN2 Position
| #define SC_ALTCTL_DACTEN_Msk (0x1ul << SC_ALTCTL_DACTEN_Pos) |
SC_T::ALTCTL: DACTEN Mask
| #define SC_ALTCTL_DACTEN_Pos (2) |
SC_T::ALTCTL: DACTEN Position
| #define SC_ALTCTL_INITSEL_Msk (0x3ul << SC_ALTCTL_INITSEL_Pos) |
SC_T::ALTCTL: INITSEL Mask
| #define SC_ALTCTL_INITSEL_Pos (8) |
SC_T::ALTCTL: INITSEL Position
| #define SC_ALTCTL_OUTSEL_Msk (0x1ul << SC_ALTCTL_OUTSEL_Pos) |
SC_T::ALTCTL: OUTSEL Mask
| #define SC_ALTCTL_OUTSEL_Pos (16) |
SC_T::ALTCTL: OUTSEL Position
| #define SC_ALTCTL_RXBGTEN_Msk (0x1ul << SC_ALTCTL_RXBGTEN_Pos) |
SC_T::ALTCTL: RXBGTEN Mask
| #define SC_ALTCTL_RXBGTEN_Pos (12) |
SC_T::ALTCTL: RXBGTEN Position
| #define SC_ALTCTL_RXRST_Msk (0x1ul << SC_ALTCTL_RXRST_Pos) |
SC_T::ALTCTL: RXRST Mask
| #define SC_ALTCTL_RXRST_Pos (1) |
SC_T::ALTCTL: RXRST Position
| #define SC_ALTCTL_TXRST_Msk (0x1ul << SC_ALTCTL_TXRST_Pos) |
SC_T::ALTCTL: TXRST Mask
| #define SC_ALTCTL_TXRST_Pos (0) |
SC_T::ALTCTL: TXRST Position
| #define SC_ALTCTL_WARSTEN_Msk (0x1ul << SC_ALTCTL_WARSTEN_Pos) |
SC_T::ALTCTL: WARSTEN Mask
| #define SC_ALTCTL_WARSTEN_Pos (4) |
SC_T::ALTCTL: WARSTEN Position
| #define SC_CTL_AUTOCEN_Msk (0x1ul << SC_CTL_AUTOCEN_Pos) |
| #define SC_CTL_AUTOCEN_Pos (3) |
| #define SC_CTL_BGT_Msk (0x1ful << SC_CTL_BGT_Pos) |
| #define SC_CTL_CDDBSEL_Msk (0x3ul << SC_CTL_CDDBSEL_Pos) |
| #define SC_CTL_CDDBSEL_Pos (24) |
| #define SC_CTL_CONSEL_Msk (0x3ul << SC_CTL_CONSEL_Pos) |
| #define SC_CTL_CONSEL_Pos (4) |
| #define SC_CTL_NSB_Msk (0x1ul << SC_CTL_NSB_Pos) |
| #define SC_CTL_RXOFF_Msk (0x1ul << SC_CTL_RXOFF_Pos) |
| #define SC_CTL_RXRTY_Msk (0x7ul << SC_CTL_RXRTY_Pos) |
| #define SC_CTL_RXRTYEN_Msk (0x1ul << SC_CTL_RXRTYEN_Pos) |
| #define SC_CTL_RXRTYEN_Pos (19) |
| #define SC_CTL_RXTRGLV_Msk (0x3ul << SC_CTL_RXTRGLV_Pos) |
| #define SC_CTL_RXTRGLV_Pos (6) |
| #define SC_CTL_SCEN_Msk (0x1ul << SC_CTL_SCEN_Pos) |
| #define SC_CTL_SYNC_Msk (0x1ul << SC_CTL_SYNC_Pos) |
| #define SC_CTL_TMRSEL_Msk (0x3ul << SC_CTL_TMRSEL_Pos) |
| #define SC_CTL_TMRSEL_Pos (13) |
| #define SC_CTL_TXOFF_Msk (0x1ul << SC_CTL_TXOFF_Pos) |
| #define SC_CTL_TXRTY_Msk (0x7ul << SC_CTL_TXRTY_Pos) |
| #define SC_CTL_TXRTYEN_Msk (0x1ul << SC_CTL_TXRTYEN_Pos) |
| #define SC_CTL_TXRTYEN_Pos (23) |
| #define SC_DAT_DAT_Msk (0xfful << SC_DAT_DAT_Pos) |
| #define SC_DAT_DAT_Pos (0) |
| #define SC_EGT_EGT_Msk (0xfful << SC_EGT_EGT_Pos) |
| #define SC_ETUCTL_ETURDIV_Msk (0xffful << SC_ETUCTL_ETURDIV_Pos) |
SC_T::ETUCTL: ETURDIV Mask
| #define SC_ETUCTL_ETURDIV_Pos (0) |
SC_T::ETUCTL: ETURDIV Position
| #define SC_INTEN_ACERRIEN_Msk (0x1ul << SC_INTEN_ACERRIEN_Pos) |
SC_T::INTEN: ACERRIEN Mask
| #define SC_INTEN_ACERRIEN_Pos (10) |
SC_T::INTEN: ACERRIEN Position
| #define SC_INTEN_BGTIEN_Msk (0x1ul << SC_INTEN_BGTIEN_Pos) |
SC_T::INTEN: BGTIEN Mask
| #define SC_INTEN_BGTIEN_Pos (6) |
SC_T::INTEN: BGTIEN Position
| #define SC_INTEN_CDIEN_Msk (0x1ul << SC_INTEN_CDIEN_Pos) |
SC_T::INTEN: CDIEN Mask
| #define SC_INTEN_CDIEN_Pos (7) |
SC_T::INTEN: CDIEN Position
| #define SC_INTEN_INITIEN_Msk (0x1ul << SC_INTEN_INITIEN_Pos) |
SC_T::INTEN: INITIEN Mask
| #define SC_INTEN_INITIEN_Pos (8) |
SC_T::INTEN: INITIEN Position
| #define SC_INTEN_RDAIEN_Msk (0x1ul << SC_INTEN_RDAIEN_Pos) |
SC_T::INTEN: RDAIEN Mask
| #define SC_INTEN_RDAIEN_Pos (0) |
SC_T::INTEN: RDAIEN Position
| #define SC_INTEN_RXTOIEN_Msk (0x1ul << SC_INTEN_RXTOIEN_Pos) |
SC_T::INTEN: RXTOIEN Mask
| #define SC_INTEN_RXTOIEN_Pos (9) |
SC_T::INTEN: RXTOIEN Position
| #define SC_INTEN_TBEIEN_Msk (0x1ul << SC_INTEN_TBEIEN_Pos) |
SC_T::INTEN: TBEIEN Mask
| #define SC_INTEN_TBEIEN_Pos (1) |
SC_T::INTEN: TBEIEN Position
| #define SC_INTEN_TERRIEN_Msk (0x1ul << SC_INTEN_TERRIEN_Pos) |
SC_T::INTEN: TERRIEN Mask
| #define SC_INTEN_TERRIEN_Pos (2) |
SC_T::INTEN: TERRIEN Position
| #define SC_INTEN_TMR0IEN_Msk (0x1ul << SC_INTEN_TMR0IEN_Pos) |
SC_T::INTEN: TMR0IEN Mask
| #define SC_INTEN_TMR0IEN_Pos (3) |
SC_T::INTEN: TMR0IEN Position
| #define SC_INTEN_TMR1IEN_Msk (0x1ul << SC_INTEN_TMR1IEN_Pos) |
SC_T::INTEN: TMR1IEN Mask
| #define SC_INTEN_TMR1IEN_Pos (4) |
SC_T::INTEN: TMR1IEN Position
| #define SC_INTEN_TMR2IEN_Msk (0x1ul << SC_INTEN_TMR2IEN_Pos) |
SC_T::INTEN: TMR2IEN Mask
| #define SC_INTEN_TMR2IEN_Pos (5) |
SC_T::INTEN: TMR2IEN Position
| #define SC_INTSTS_ACERRIF_Msk (0x1ul << SC_INTSTS_ACERRIF_Pos) |
SC_T::INTSTS: ACERRIF Mask
| #define SC_INTSTS_ACERRIF_Pos (10) |
SC_T::INTSTS: ACERRIF Position
| #define SC_INTSTS_BGTIF_Msk (0x1ul << SC_INTSTS_BGTIF_Pos) |
SC_T::INTSTS: BGTIF Mask
| #define SC_INTSTS_BGTIF_Pos (6) |
SC_T::INTSTS: BGTIF Position
| #define SC_INTSTS_CDIF_Msk (0x1ul << SC_INTSTS_CDIF_Pos) |
SC_T::INTSTS: CDIF Mask
| #define SC_INTSTS_CDIF_Pos (7) |
SC_T::INTSTS: CDIF Position
| #define SC_INTSTS_INITIF_Msk (0x1ul << SC_INTSTS_INITIF_Pos) |
SC_T::INTSTS: INITIF Mask
| #define SC_INTSTS_INITIF_Pos (8) |
SC_T::INTSTS: INITIF Position
| #define SC_INTSTS_RDAIF_Msk (0x1ul << SC_INTSTS_RDAIF_Pos) |
SC_T::INTSTS: RDAIF Mask
| #define SC_INTSTS_RDAIF_Pos (0) |
SC_T::INTSTS: RDAIF Position
| #define SC_INTSTS_RXTOIF_Msk (0x1ul << SC_INTSTS_RXTOIF_Pos) |
SC_T::INTSTS: RXTOIF Mask
| #define SC_INTSTS_RXTOIF_Pos (9) |
SC_T::INTSTS: RXTOIF Position
| #define SC_INTSTS_TBEIF_Msk (0x1ul << SC_INTSTS_TBEIF_Pos) |
SC_T::INTSTS: TBEIF Mask
| #define SC_INTSTS_TBEIF_Pos (1) |
SC_T::INTSTS: TBEIF Position
| #define SC_INTSTS_TERRIF_Msk (0x1ul << SC_INTSTS_TERRIF_Pos) |
SC_T::INTSTS: TERRIF Mask
| #define SC_INTSTS_TERRIF_Pos (2) |
SC_T::INTSTS: TERRIF Position
| #define SC_INTSTS_TMR0IF_Msk (0x1ul << SC_INTSTS_TMR0IF_Pos) |
SC_T::INTSTS: TMR0IF Mask
| #define SC_INTSTS_TMR0IF_Pos (3) |
SC_T::INTSTS: TMR0IF Position
| #define SC_INTSTS_TMR1IF_Msk (0x1ul << SC_INTSTS_TMR1IF_Pos) |
SC_T::INTSTS: TMR1IF Mask
| #define SC_INTSTS_TMR1IF_Pos (4) |
SC_T::INTSTS: TMR1IF Position
| #define SC_INTSTS_TMR2IF_Msk (0x1ul << SC_INTSTS_TMR2IF_Pos) |
SC_T::INTSTS: TMR2IF Mask
| #define SC_INTSTS_TMR2IF_Pos (5) |
SC_T::INTSTS: TMR2IF Position
| #define SC_PINCTL_ADACEN_Msk (0x1ul << SC_PINCTL_ADACEN_Pos) |
SC_T::PINCTL: ADACEN Mask
| #define SC_PINCTL_ADACEN_Pos (7) |
SC_T::PINCTL: ADACEN Position
| #define SC_PINCTL_CDLV_Msk (0x1ul << SC_PINCTL_CDLV_Pos) |
SC_T::PINCTL: CDLV Mask
| #define SC_PINCTL_CDLV_Pos (10) |
SC_T::PINCTL: CDLV Position
| #define SC_PINCTL_CDPINSTS_Msk (0x1ul << SC_PINCTL_CDPINSTS_Pos) |
SC_T::PINCTL: CDPINSTS Mask
| #define SC_PINCTL_CDPINSTS_Pos (4) |
SC_T::PINCTL: CDPINSTS Position
| #define SC_PINCTL_CINSERT_Msk (0x1ul << SC_PINCTL_CINSERT_Pos) |
SC_T::PINCTL: CINSERT Mask
| #define SC_PINCTL_CINSERT_Pos (3) |
SC_T::PINCTL: CINSERT Position
| #define SC_PINCTL_CLKKEEP_Msk (0x1ul << SC_PINCTL_CLKKEEP_Pos) |
SC_T::PINCTL: CLKKEEP Mask
| #define SC_PINCTL_CLKKEEP_Pos (6) |
SC_T::PINCTL: CLKKEEP Position
| #define SC_PINCTL_CREMOVE_Msk (0x1ul << SC_PINCTL_CREMOVE_Pos) |
SC_T::PINCTL: CREMOVE Mask
| #define SC_PINCTL_CREMOVE_Pos (2) |
SC_T::PINCTL: CREMOVE Position
| #define SC_PINCTL_DATSTS_Msk (0x1ul << SC_PINCTL_DATSTS_Pos) |
SC_T::PINCTL: DATSTS Mask
| #define SC_PINCTL_DATSTS_Pos (16) |
SC_T::PINCTL: DATSTS Position
| #define SC_PINCTL_PWREN_Msk (0x1ul << SC_PINCTL_PWREN_Pos) |
SC_T::PINCTL: PWREN Mask
| #define SC_PINCTL_PWREN_Pos (0) |
SC_T::PINCTL: PWREN Position
| #define SC_PINCTL_PWRINV_Msk (0x1ul << SC_PINCTL_PWRINV_Pos) |
SC_T::PINCTL: PWRINV Mask
| #define SC_PINCTL_PWRINV_Pos (11) |
SC_T::PINCTL: PWRINV Position
| #define SC_PINCTL_SCDOUT_Msk (0x1ul << SC_PINCTL_SCDOUT_Pos) |
SC_T::PINCTL: SCDOUT Mask
| #define SC_PINCTL_SCDOUT_Pos (9) |
SC_T::PINCTL: SCDOUT Position
| #define SC_PINCTL_SCRST_Msk (0x1ul << SC_PINCTL_SCRST_Pos) |
SC_T::PINCTL: SCRST Mask
| #define SC_PINCTL_SCRST_Pos (1) |
SC_T::PINCTL: SCRST Position
| #define SC_PINCTL_SYNC_Msk (0x1ul << SC_PINCTL_SYNC_Pos) |
SC_T::PINCTL: SYNC Mask
| #define SC_PINCTL_SYNC_Pos (30) |
SC_T::PINCTL: SYNC Position
| #define SC_RXTOUT_RFTM_Msk (0x1fful << SC_RXTOUT_RFTM_Pos) |
SC_T::RXTOUT: RFTM Mask
| #define SC_RXTOUT_RFTM_Pos (0) |
SC_T::RXTOUT: RFTM Position
| #define SC_STATUS_BEF_Msk (0x1ul << SC_STATUS_BEF_Pos) |
SC_T::STATUS: BEF Mask
| #define SC_STATUS_BEF_Pos (6) |
SC_T::STATUS: BEF Position
| #define SC_STATUS_FEF_Msk (0x1ul << SC_STATUS_FEF_Pos) |
SC_T::STATUS: FEF Mask
| #define SC_STATUS_FEF_Pos (5) |
SC_T::STATUS: FEF Position
| #define SC_STATUS_PEF_Msk (0x1ul << SC_STATUS_PEF_Pos) |
SC_T::STATUS: PEF Mask
| #define SC_STATUS_PEF_Pos (4) |
SC_T::STATUS: PEF Position
| #define SC_STATUS_RXACT_Msk (0x1ul << SC_STATUS_RXACT_Pos) |
SC_T::STATUS: RXACT Mask
| #define SC_STATUS_RXACT_Pos (23) |
SC_T::STATUS: RXACT Position
| #define SC_STATUS_RXEMPTY_Msk (0x1ul << SC_STATUS_RXEMPTY_Pos) |
SC_T::STATUS: RXEMPTY Mask
| #define SC_STATUS_RXEMPTY_Pos (1) |
SC_T::STATUS: RXEMPTY Position
| #define SC_STATUS_RXFULL_Msk (0x1ul << SC_STATUS_RXFULL_Pos) |
SC_T::STATUS: RXFULL Mask
| #define SC_STATUS_RXFULL_Pos (2) |
SC_T::STATUS: RXFULL Position
| #define SC_STATUS_RXOV_Msk (0x1ul << SC_STATUS_RXOV_Pos) |
SC_T::STATUS: RXOV Mask
| #define SC_STATUS_RXOV_Pos (0) |
SC_T::STATUS: RXOV Position
| #define SC_STATUS_RXOVERR_Msk (0x1ul << SC_STATUS_RXOVERR_Pos) |
SC_T::STATUS: RXOVERR Mask
| #define SC_STATUS_RXOVERR_Pos (22) |
SC_T::STATUS: RXOVERR Position
| #define SC_STATUS_RXPOINT_Msk (0x3ul << SC_STATUS_RXPOINT_Pos) |
SC_T::STATUS: RXPOINT Mask
| #define SC_STATUS_RXPOINT_Pos (16) |
SC_T::STATUS: RXPOINT Position
| #define SC_STATUS_RXRERR_Msk (0x1ul << SC_STATUS_RXRERR_Pos) |
SC_T::STATUS: RXRERR Mask
| #define SC_STATUS_RXRERR_Pos (21) |
SC_T::STATUS: RXRERR Position
| #define SC_STATUS_TXACT_Msk (0x1ul << SC_STATUS_TXACT_Pos) |
SC_T::STATUS: TXACT Mask
| #define SC_STATUS_TXACT_Pos (31) |
SC_T::STATUS: TXACT Position
| #define SC_STATUS_TXEMPTY_Msk (0x1ul << SC_STATUS_TXEMPTY_Pos) |
SC_T::STATUS: TXEMPTY Mask
| #define SC_STATUS_TXEMPTY_Pos (9) |
SC_T::STATUS: TXEMPTY Position
| #define SC_STATUS_TXFULL_Msk (0x1ul << SC_STATUS_TXFULL_Pos) |
SC_T::STATUS: TXFULL Mask
| #define SC_STATUS_TXFULL_Pos (10) |
SC_T::STATUS: TXFULL Position
| #define SC_STATUS_TXOV_Msk (0x1ul << SC_STATUS_TXOV_Pos) |
SC_T::STATUS: TXOV Mask
| #define SC_STATUS_TXOV_Pos (8) |
SC_T::STATUS: TXOV Position
| #define SC_STATUS_TXOVERR_Msk (0x1ul << SC_STATUS_TXOVERR_Pos) |
SC_T::STATUS: TXOVERR Mask
| #define SC_STATUS_TXOVERR_Pos (30) |
SC_T::STATUS: TXOVERR Position
| #define SC_STATUS_TXPOINT_Msk (0x3ul << SC_STATUS_TXPOINT_Pos) |
SC_T::STATUS: TXPOINT Mask
| #define SC_STATUS_TXPOINT_Pos (24) |
SC_T::STATUS: TXPOINT Position
| #define SC_STATUS_TXRERR_Msk (0x1ul << SC_STATUS_TXRERR_Pos) |
SC_T::STATUS: TXRERR Mask
| #define SC_STATUS_TXRERR_Pos (29) |
SC_T::STATUS: TXRERR Position
| #define SC_TMRCTL0_CNT_Msk (0xfffffful << SC_TMRCTL0_CNT_Pos) |
SC_T::TMRCTL0: CNT Mask
| #define SC_TMRCTL0_CNT_Pos (0) |
SC_T::TMRCTL0: CNT Position
| #define SC_TMRCTL0_OPMODE_Msk (0xful << SC_TMRCTL0_OPMODE_Pos) |
SC_T::TMRCTL0: OPMODE Mask
| #define SC_TMRCTL0_OPMODE_Pos (24) |
SC_T::TMRCTL0: OPMODE Position
| #define SC_TMRCTL0_SYNC_Msk (0x1ul << SC_TMRCTL0_SYNC_Pos) |
SC_T::TMRCTL0: SYNC Mask
| #define SC_TMRCTL0_SYNC_Pos (31) |
SC_T::TMRCTL0: SYNC Position
| #define SC_TMRCTL1_CNT_Msk (0xfful << SC_TMRCTL1_CNT_Pos) |
SC_T::TMRCTL1: CNT Mask
| #define SC_TMRCTL1_CNT_Pos (0) |
SC_T::TMRCTL1: CNT Position
| #define SC_TMRCTL1_OPMODE_Msk (0xful << SC_TMRCTL1_OPMODE_Pos) |
SC_T::TMRCTL1: OPMODE Mask
| #define SC_TMRCTL1_OPMODE_Pos (24) |
SC_T::TMRCTL1: OPMODE Position
| #define SC_TMRCTL1_SYNC_Msk (0x1ul << SC_TMRCTL1_SYNC_Pos) |
SC_T::TMRCTL1: SYNC Mask
| #define SC_TMRCTL1_SYNC_Pos (31) |
SC_T::TMRCTL1: SYNC Position
| #define SC_TMRCTL2_CNT_Msk (0xfful << SC_TMRCTL2_CNT_Pos) |
SC_T::TMRCTL2: CNT Mask
| #define SC_TMRCTL2_CNT_Pos (0) |
SC_T::TMRCTL2: CNT Position
| #define SC_TMRCTL2_OPMODE_Msk (0xful << SC_TMRCTL2_OPMODE_Pos) |
SC_T::TMRCTL2: OPMODE Mask
| #define SC_TMRCTL2_OPMODE_Pos (24) |
SC_T::TMRCTL2: OPMODE Position
| #define SC_TMRCTL2_SYNC_Msk (0x1ul << SC_TMRCTL2_SYNC_Pos) |
SC_T::TMRCTL2: SYNC Mask
| #define SC_TMRCTL2_SYNC_Pos (31) |
SC_T::TMRCTL2: SYNC Position
| #define SC_UARTCTL_OPE_Msk (0x1ul << SC_UARTCTL_OPE_Pos) |
SC_T::UARTCTL: OPE Mask
| #define SC_UARTCTL_OPE_Pos (7) |
SC_T::UARTCTL: OPE Position
| #define SC_UARTCTL_PBOFF_Msk (0x1ul << SC_UARTCTL_PBOFF_Pos) |
SC_T::UARTCTL: PBOFF Mask
| #define SC_UARTCTL_PBOFF_Pos (6) |
SC_T::UARTCTL: PBOFF Position
| #define SC_UARTCTL_UARTEN_Msk (0x1ul << SC_UARTCTL_UARTEN_Pos) |
SC_T::UARTCTL: UARTEN Mask
| #define SC_UARTCTL_UARTEN_Pos (0) |
SC_T::UARTCTL: UARTEN Position
| #define SC_UARTCTL_WLS_Msk (0x3ul << SC_UARTCTL_WLS_Pos) |
SC_T::UARTCTL: WLS Mask
| #define SC_UARTCTL_WLS_Pos (4) |
SC_T::UARTCTL: WLS Position
| #define SPI_CLKDIV_DIVIDER_Msk (0xfful << SPI_CLKDIV_DIVIDER_Pos) |
SPI_T::CLKDIV: DIVIDER Mask
| #define SPI_CLKDIV_DIVIDER_Pos (0) |
SPI_T::CLKDIV: DIVIDER Position
| #define SPI_CTL_CLKPOL_Msk (0x1ul << SPI_CTL_CLKPOL_Pos) |
SPI_T::CTL: CLKPOL Mask
| #define SPI_CTL_CLKPOL_Pos (11) |
SPI_T::CTL: CLKPOL Position
| #define SPI_CTL_DUALDIR_Msk (0x1ul << SPI_CTL_DUALDIR_Pos) |
SPI_T::CTL: DUALDIR Mask
| #define SPI_CTL_DUALDIR_Pos (28) |
SPI_T::CTL: DUALDIR Position
| #define SPI_CTL_DUALIOEN_Msk (0x1ul << SPI_CTL_DUALIOEN_Pos) |
SPI_T::CTL: DUALIOEN Mask
| #define SPI_CTL_DUALIOEN_Pos (29) |
SPI_T::CTL: DUALIOEN Position
| #define SPI_CTL_DWIDTH_Msk (0x1ful << SPI_CTL_DWIDTH_Pos) |
SPI_T::CTL: DWIDTH Mask
| #define SPI_CTL_DWIDTH_Pos (3) |
SPI_T::CTL: DWIDTH Position
| #define SPI_CTL_FIFOM_Msk (0x1ul << SPI_CTL_FIFOM_Pos) |
SPI_T::CTL: FIFOM Mask
| #define SPI_CTL_FIFOM_Pos (21) |
SPI_T::CTL: FIFOM Position
| #define SPI_CTL_GOBUSY_Msk (0x1ul << SPI_CTL_GOBUSY_Pos) |
SPI_T::CTL: GOBUSY Mask
| #define SPI_CTL_GOBUSY_Pos (0) |
@addtogroup SPI_CONST SPI Bit Field Definition Constant Definitions for SPI Controller
SPI_T::CTL: GOBUSY Position
| #define SPI_CTL_LSB_Msk (0x1ul << SPI_CTL_LSB_Pos) |
SPI_T::CTL: LSB Mask
| #define SPI_CTL_LSB_Pos (10) |
SPI_T::CTL: LSB Position
| #define SPI_CTL_REORDER_Msk (0x1ul << SPI_CTL_REORDER_Pos) |
SPI_T::CTL: REORDER Mask
| #define SPI_CTL_REORDER_Pos (19) |
SPI_T::CTL: REORDER Position
| #define SPI_CTL_RXNEG_Msk (0x1ul << SPI_CTL_RXNEG_Pos) |
SPI_T::CTL: RXNEG Mask
| #define SPI_CTL_RXNEG_Pos (1) |
SPI_T::CTL: RXNEG Position
| #define SPI_CTL_SLAVE_Msk (0x1ul << SPI_CTL_SLAVE_Pos) |
SPI_T::CTL: SLAVE Mask
| #define SPI_CTL_SLAVE_Pos (18) |
SPI_T::CTL: SLAVE Position
| #define SPI_CTL_SUSPITV_Msk (0xful << SPI_CTL_SUSPITV_Pos) |
SPI_T::CTL: SUSPITV Mask
| #define SPI_CTL_SUSPITV_Pos (12) |
SPI_T::CTL: SUSPITV Position
| #define SPI_CTL_TWOBIT_Msk (0x1ul << SPI_CTL_TWOBIT_Pos) |
SPI_T::CTL: TWOBIT Mask
| #define SPI_CTL_TWOBIT_Pos (22) |
SPI_T::CTL: TWOBIT Position
| #define SPI_CTL_TXNEG_Msk (0x1ul << SPI_CTL_TXNEG_Pos) |
SPI_T::CTL: TXNEG Mask
| #define SPI_CTL_TXNEG_Pos (2) |
SPI_T::CTL: TXNEG Position
| #define SPI_CTL_UNITIEN_Msk (0x1ul << SPI_CTL_UNITIEN_Pos) |
SPI_T::CTL: UNITIEN Mask
| #define SPI_CTL_UNITIEN_Pos (17) |
SPI_T::CTL: UNITIEN Position
| #define SPI_CTL_WKCLKEN_Msk (0x1ul << SPI_CTL_WKCLKEN_Pos) |
SPI_T::CTL: WKCLKEN Mask
| #define SPI_CTL_WKCLKEN_Pos (31) |
SPI_T::CTL: WKCLKEN Position
| #define SPI_CTL_WKSSEN_Msk (0x1ul << SPI_CTL_WKSSEN_Pos) |
SPI_T::CTL: WKSSEN Mask
| #define SPI_CTL_WKSSEN_Pos (30) |
SPI_T::CTL: WKSSEN Position
| #define SPI_FIFOCTL_RXFBCLR_Msk (0x1ul << SPI_FIFOCTL_RXFBCLR_Pos) |
SPI_T::FIFOCTL: RXFBCLR Mask
| #define SPI_FIFOCTL_RXFBCLR_Pos (0) |
SPI_T::FIFOCTL: RXFBCLR Position
| #define SPI_FIFOCTL_RXOVIEN_Msk (0x1ul << SPI_FIFOCTL_RXOVIEN_Pos) |
SPI_T::FIFOCTL: RXOVIEN Mask
| #define SPI_FIFOCTL_RXOVIEN_Pos (4) |
SPI_T::FIFOCTL: RXOVIEN Position
| #define SPI_FIFOCTL_RXTH_Msk (0x7ul << SPI_FIFOCTL_RXTH_Pos) |
SPI_T::FIFOCTL: RXTH Mask
| #define SPI_FIFOCTL_RXTH_Pos (24) |
SPI_T::FIFOCTL: RXTH Position
| #define SPI_FIFOCTL_RXTHIEN_Msk (0x1ul << SPI_FIFOCTL_RXTHIEN_Pos) |
SPI_T::FIFOCTL: RXTHIEN Mask
| #define SPI_FIFOCTL_RXTHIEN_Pos (2) |
SPI_T::FIFOCTL: RXTHIEN Position
| #define SPI_FIFOCTL_RXTOIEN_Msk (0x1ul << SPI_FIFOCTL_RXTOIEN_Pos) |
SPI_T::FIFOCTL: RXTOIEN Mask
| #define SPI_FIFOCTL_RXTOIEN_Pos (7) |
SPI_T::FIFOCTL: RXTOIEN Position
| #define SPI_FIFOCTL_TXFBCLR_Msk (0x1ul << SPI_FIFOCTL_TXFBCLR_Pos) |
SPI_T::FIFOCTL: TXFBCLR Mask
| #define SPI_FIFOCTL_TXFBCLR_Pos (1) |
SPI_T::FIFOCTL: TXFBCLR Position
| #define SPI_FIFOCTL_TXTH_Msk (0x7ul << SPI_FIFOCTL_TXTH_Pos) |
SPI_T::FIFOCTL: TXTH Mask
| #define SPI_FIFOCTL_TXTH_Pos (28) |
SPI_T::FIFOCTL: TXTH Position
| #define SPI_FIFOCTL_TXTHIEN_Msk (0x1ul << SPI_FIFOCTL_TXTHIEN_Pos) |
SPI_T::FIFOCTL: TXTHIEN Mask
| #define SPI_FIFOCTL_TXTHIEN_Pos (3) |
SPI_T::FIFOCTL: TXTHIEN Position
| #define SPI_PDMACTL_PDMARST_Msk (0x1ul << SPI_PDMACTL_PDMARST_Pos) |
SPI_T::PDMACTL: PDMARST Mask
| #define SPI_PDMACTL_PDMARST_Pos (2) |
SPI_T::PDMACTL: PDMARST Position
| #define SPI_PDMACTL_RXPDMAEN_Msk (0x1ul << SPI_PDMACTL_RXPDMAEN_Pos) |
SPI_T::PDMACTL: RXPDMAEN Mask
| #define SPI_PDMACTL_RXPDMAEN_Pos (1) |
SPI_T::PDMACTL: RXPDMAEN Position
| #define SPI_PDMACTL_TXPDMAEN_Msk (0x1ul << SPI_PDMACTL_TXPDMAEN_Pos) |
SPI_T::PDMACTL: TXPDMAEN Mask
| #define SPI_PDMACTL_TXPDMAEN_Pos (0) |
SPI_T::PDMACTL: TXPDMAEN Position
| #define SPI_RX0_RX_Msk (0xfffffffful << SPI_RX0_RX_Pos) |
SPI_T::RX0: RX Mask
| #define SPI_RX0_RX_Pos (0) |
SPI_T::RX0: RX Position
| #define SPI_RX1_RX_Msk (0xfffffffful << SPI_RX1_RX_Pos) |
SPI_T::RX1: RX Mask
| #define SPI_RX1_RX_Pos (0) |
SPI_T::RX1: RX Position
| #define SPI_SSCTL_AUTOSS_Msk (0x1ul << SPI_SSCTL_AUTOSS_Pos) |
SPI_T::SSCTL: AUTOSS Mask
| #define SPI_SSCTL_AUTOSS_Pos (3) |
SPI_T::SSCTL: AUTOSS Position
| #define SPI_SSCTL_SLV3WIRE_Msk (0x1ul << SPI_SSCTL_SLV3WIRE_Pos) |
SPI_T::SSCTL: SLV3WIRE Mask
| #define SPI_SSCTL_SLV3WIRE_Pos (5) |
SPI_T::SSCTL: SLV3WIRE Position
| #define SPI_SSCTL_SLVABORT_Msk (0x1ul << SPI_SSCTL_SLVABORT_Pos) |
SPI_T::SSCTL: SLVABORT Mask
| #define SPI_SSCTL_SLVABORT_Pos (8) |
SPI_T::SSCTL: SLVABORT Position
| #define SPI_SSCTL_SLVTOCNT_Msk (0x3fful << SPI_SSCTL_SLVTOCNT_Pos) |
SPI_T::SSCTL: SLVTOCNT Mask
| #define SPI_SSCTL_SLVTOCNT_Pos (20) |
SPI_T::SSCTL: SLVTOCNT Position
| #define SPI_SSCTL_SLVTOIEN_Msk (0x1ul << SPI_SSCTL_SLVTOIEN_Pos) |
SPI_T::SSCTL: SLVTOIEN Mask
| #define SPI_SSCTL_SLVTOIEN_Pos (6) |
SPI_T::SSCTL: SLVTOIEN Position
| #define SPI_SSCTL_SS_Msk (0x3ul << SPI_SSCTL_SS_Pos) |
SPI_T::SSCTL: SS Mask
| #define SPI_SSCTL_SS_Pos (0) |
SPI_T::SSCTL: SS Position
| #define SPI_SSCTL_SSACTPOL_Msk (0x1ul << SPI_SSCTL_SSACTPOL_Pos) |
SPI_T::SSCTL: SSACTPOL Mask
| #define SPI_SSCTL_SSACTPOL_Pos (2) |
SPI_T::SSCTL: SSACTPOL Position
| #define SPI_SSCTL_SSINAIEN_Msk (0x1ul << SPI_SSCTL_SSINAIEN_Pos) |
SPI_T::SSCTL: SSINAIEN Mask
| #define SPI_SSCTL_SSINAIEN_Pos (16) |
SPI_T::SSCTL: SSINAIEN Position
| #define SPI_SSCTL_SSLTRIG_Msk (0x1ul << SPI_SSCTL_SSLTRIG_Pos) |
SPI_T::SSCTL: SSLTRIG Mask
| #define SPI_SSCTL_SSLTRIG_Pos (4) |
SPI_T::SSCTL: SSLTRIG Position
| #define SPI_SSCTL_SSTAIEN_Msk (0x1ul << SPI_SSCTL_SSTAIEN_Pos) |
SPI_T::SSCTL: SSTAIEN Mask
| #define SPI_SSCTL_SSTAIEN_Pos (9) |
SPI_T::SSCTL: SSTAIEN Position
| #define SPI_STATUS_LTRIGF_Msk (0x1ul << SPI_STATUS_LTRIGF_Pos) |
SPI_T::STATUS: LTRIGF Mask
| #define SPI_STATUS_LTRIGF_Pos (4) |
SPI_T::STATUS: LTRIGF Position
| #define SPI_STATUS_RXCNT_Msk (0xful << SPI_STATUS_RXCNT_Pos) |
SPI_T::STATUS: RXCNT Mask
| #define SPI_STATUS_RXCNT_Pos (16) |
SPI_T::STATUS: RXCNT Position
| #define SPI_STATUS_RXEMPTY_Msk (0x1ul << SPI_STATUS_RXEMPTY_Pos) |
SPI_T::STATUS: RXEMPTY Mask
| #define SPI_STATUS_RXEMPTY_Pos (0) |
SPI_T::STATUS: RXEMPTY Position
| #define SPI_STATUS_RXFULL_Msk (0x1ul << SPI_STATUS_RXFULL_Pos) |
SPI_T::STATUS: RXFULL Mask
| #define SPI_STATUS_RXFULL_Pos (1) |
SPI_T::STATUS: RXFULL Position
| #define SPI_STATUS_RXOVIF_Msk (0x1ul << SPI_STATUS_RXOVIF_Pos) |
SPI_T::STATUS: RXOVIF Mask
| #define SPI_STATUS_RXOVIF_Pos (9) |
SPI_T::STATUS: RXOVIF Position
| #define SPI_STATUS_RXTHIF_Msk (0x1ul << SPI_STATUS_RXTHIF_Pos) |
SPI_T::STATUS: RXTHIF Mask
| #define SPI_STATUS_RXTHIF_Pos (8) |
SPI_T::STATUS: RXTHIF Position
| #define SPI_STATUS_RXTOIF_Msk (0x1ul << SPI_STATUS_RXTOIF_Pos) |
SPI_T::STATUS: RXTOIF Mask
| #define SPI_STATUS_RXTOIF_Pos (12) |
SPI_T::STATUS: RXTOIF Position
| #define SPI_STATUS_SLVSTAIF_Msk (0x1ul << SPI_STATUS_SLVSTAIF_Pos) |
SPI_T::STATUS: SLVSTAIF Mask
| #define SPI_STATUS_SLVSTAIF_Pos (6) |
SPI_T::STATUS: SLVSTAIF Position
| #define SPI_STATUS_SLVTOIF_Msk (0x1ul << SPI_STATUS_SLVTOIF_Pos) |
SPI_T::STATUS: SLVTOIF Mask
| #define SPI_STATUS_SLVTOIF_Pos (13) |
SPI_T::STATUS: SLVTOIF Position
| #define SPI_STATUS_SLVTXSKE_Msk (0x1ul << SPI_STATUS_SLVTXSKE_Pos) |
SPI_T::STATUS: SLVTXSKE Mask
| #define SPI_STATUS_SLVTXSKE_Pos (15) |
SPI_T::STATUS: SLVTXSKE Position
| #define SPI_STATUS_TXCNT_Msk (0xful << SPI_STATUS_TXCNT_Pos) |
SPI_T::STATUS: TXCNT Mask
| #define SPI_STATUS_TXCNT_Pos (20) |
SPI_T::STATUS: TXCNT Position
| #define SPI_STATUS_TXEMPTY_Msk (0x1ul << SPI_STATUS_TXEMPTY_Pos) |
SPI_T::STATUS: TXEMPTY Mask
| #define SPI_STATUS_TXEMPTY_Pos (2) |
SPI_T::STATUS: TXEMPTY Position
| #define SPI_STATUS_TXFULL_Msk (0x1ul << SPI_STATUS_TXFULL_Pos) |
SPI_T::STATUS: TXFULL Mask
| #define SPI_STATUS_TXFULL_Pos (3) |
SPI_T::STATUS: TXFULL Position
| #define SPI_STATUS_TXTHIF_Msk (0x1ul << SPI_STATUS_TXTHIF_Pos) |
SPI_T::STATUS: TXTHIF Mask
| #define SPI_STATUS_TXTHIF_Pos (10) |
SPI_T::STATUS: TXTHIF Position
| #define SPI_STATUS_UNITIF_Msk (0x1ul << SPI_STATUS_UNITIF_Pos) |
SPI_T::STATUS: UNITIF Mask
| #define SPI_STATUS_UNITIF_Pos (7) |
SPI_T::STATUS: UNITIF Position
| #define SPI_STATUS_WKCLKIF_Msk (0x1ul << SPI_STATUS_WKCLKIF_Pos) |
SPI_T::STATUS: WKCLKIF Mask
| #define SPI_STATUS_WKCLKIF_Pos (31) |
SPI_T::STATUS: WKCLKIF Position
| #define SPI_STATUS_WKSSIF_Msk (0x1ul << SPI_STATUS_WKSSIF_Pos) |
SPI_T::STATUS: WKSSIF Mask
| #define SPI_STATUS_WKSSIF_Pos (30) |
SPI_T::STATUS: WKSSIF Position
| #define SPI_TX0_TX_Msk (0xfffffffful << SPI_TX0_TX_Pos) |
SPI_T::TX0: TX Mask
| #define SPI_TX0_TX_Pos (0) |
SPI_T::TX0: TX Position
| #define SPI_TX1_TX_Msk (0xfffffffful << SPI_TX1_TX_Pos) |
SPI_T::TX1: TX Mask
| #define SPI_TX1_TX_Pos (0) |
SPI_T::TX1: TX Position
| #define TIMER_CAP_CAPDAT_Msk (0xfffffful << TIMER_CAP_CAPDAT_Pos) |
TIMER_T::CAP: CAPDAT Mask
| #define TIMER_CAP_CAPDAT_Pos (0) |
TIMER_T::CAP: CAPDAT Position
| #define TIMER_CMP_CMPDAT_Msk (0xfffffful << TIMER_CMP_CMPDAT_P) |
TIMER_T::CMP: CMPDAT Mask
| #define TIMER_CMP_CMPDAT_Pos (0) |
TIMER_T::CMP: CMPDAT Position
| #define TIMER_CNT_CNT_Msk (0xfffffful << TIMER_CNT_CNT_Pos) |
TIMER_T::CNT: CNT Mask
| #define TIMER_CNT_CNT_Pos (0) |
TIMER_T::CNT: CNT Position
| #define TIMER_CNT_RSTACT_Msk (0x1ul << TIMER_CNT_RSTACT_Pos) |
TIMER_T::CNT: RSTACT Mask
| #define TIMER_CNT_RSTACT_Pos (31) |
TIMER_T::CNT: RSTACT Position
| #define TIMER_CTL_ACTSTS_Msk (0x1ul << TIMER_CTL_ACTSTS_Pos) |
TIMER_T::CTL ACTSTS Mask
| #define TIMER_CTL_ACTSTS_Pos (7) |
TIMER_T::CTL ACTSTS Position
| #define TIMER_CTL_CAPCNTMD_Msk (0x1ul << TIMER_CTL_CAPCNTMD_Pos) |
TIMER_T::CTL CAPCNTMD Mask
| #define TIMER_CTL_CAPCNTMD_Pos (20) |
TIMER_T::CTL CAPCNTMD Position
| #define TIMER_CTL_CAPDBEN_Msk (0x1ul << TIMER_CTL_CAPDBEN_Pos) |
TIMER_T::CTL CAPDBEN Mask
| #define TIMER_CTL_CAPDBEN_Pos (22) |
TIMER_T::CTL CAPDBEN Position
| #define TIMER_CTL_CAPEDGE_Msk (0x3ul << TIMER_CTL_CAPEDGE_Pos) |
TIMER_T::CTL CAPEDGE Mask
| #define TIMER_CTL_CAPEDGE_Pos (18) |
TIMER_T::CTL CAPEDGE Position
| #define TIMER_CTL_CAPEN_Msk (0x1ul << TIMER_CTL_CAPEN_Pos) |
TIMER_T::CTL CAPEN Mask
| #define TIMER_CTL_CAPEN_Pos (16) |
TIMER_T::CTL CAPEN Position
| #define TIMER_CTL_CAPFUNCS_Msk (0x1ul << TIMER_CTL_CAPFUNCS_Pos) |
TIMER_T::CTL CAPFUNCS Mask
| #define TIMER_CTL_CAPFUNCS_Pos (17) |
TIMER_T::CTL CAPFUNCS Position
| #define TIMER_CTL_CMPCTL_Msk (0x1ul << TIMER_CTL_CMPCTL_Pos) |
TIMER_T::CTL CMPCTL Mask
| #define TIMER_CTL_CMPCTL_Pos (23) |
TIMER_T::CTL CMPCTL Position
| #define TIMER_CTL_CNTDBEN_Msk (0x1ul << TIMER_CTL_CNTDBEN_Pos) |
TIMER_T::CTL CNTDBEN Mask
| #define TIMER_CTL_CNTDBEN_Pos (14) |
TIMER_T::CTL CNTDBEN Position
| #define TIMER_CTL_CNTEN_Msk (0x1ul << TIMER_CTL_CNTEN_Pos) |
TIMER_T::CTL CNTEN Mask
| #define TIMER_CTL_CNTEN_Pos (0) |
@addtogroup TMR_CONST TMR Bit Field Definition Constant Definitions for TMR Controller
TIMER_T::CTL CNTEN Position
| #define TIMER_CTL_CNTPHASE_Msk (0x1ul << TIMER_CTL_CNTPHASE_Pos) |
TIMER_T::CTL CNTPHASE Mask
| #define TIMER_CTL_CNTPHASE_Pos (13) |
TIMER_T::CTL CNTPHASE Position
| #define TIMER_CTL_EXTCNTEN_Msk (0x1ul << TIMER_CTL_EXTCNTEN_Pos) |
TIMER_T::CTL EXTCNTEN Mask
| #define TIMER_CTL_EXTCNTEN_Pos (12) |
TIMER_T::CTL EXTCNTEN Position
| #define TIMER_CTL_ICEDEBUG_Msk (0x1ul << TIMER_CTL_ICEDEBUG_Pos) |
TIMER_T::CTL ICEDEBUG Mask
| #define TIMER_CTL_ICEDEBUG_Pos (3) |
TIMER_T::CTL ICEDEBUG Position
| #define TIMER_CTL_INTRTGEN_Msk (0x1ul << TIMER_CTL_INTRTGEN_Pos) |
TIMER_T::CTL INTRTGEN Mask
| #define TIMER_CTL_INTRTGEN_Pos (24) |
TIMER_T::CTL INTRTGEN Position
| #define TIMER_CTL_INTRTGMD_Msk (0x1ul << TIMER_CTL_INTRTGMD_Pos) |
TIMER_T::CTL INTRTGMD Mask
| #define TIMER_CTL_INTRTGMD_Pos (25) |
TIMER_T::CTL INTRTGMD Position
| #define TIMER_CTL_OPMODE_Msk (0x3ul << TIMER_CTL_OPMODE_Pos) |
TIMER_T::CTL OPMODE Mask
| #define TIMER_CTL_OPMODE_Pos (4) |
TIMER_T::CTL OPMODE Position
| #define TIMER_CTL_RSTCNT_Msk (0x1ul << TIMER_CTL_RSTCNT_Pos) |
TIMER_T::CTL RSTCNT Mask
| #define TIMER_CTL_RSTCNT_Pos (1) |
TIMER_T::CTL RSTCNT Position
| #define TIMER_CTL_TRGADC_Msk (0x1ul << TIMER_CTL_TRGADC_Pos) |
TIMER_T::CTL TRGADC Mask
| #define TIMER_CTL_TRGADC_Pos (8) |
TIMER_T::CTL TRGADC Position
| #define TIMER_CTL_TRGPDMA_Msk (0x1ul << TIMER_CTL_TRGPDMA_Pos) |
TIMER_T::CTL TRGPDMA Mask
| #define TIMER_CTL_TRGPDMA_Pos (10) |
TIMER_T::CTL TRGPDMA Position
| #define TIMER_CTL_TRGPWM_Msk (0x1ul << TIMER_CTL_TRGPWM_Pos) |
TIMER_T::CTL TRGPWM Mask
| #define TIMER_CTL_TRGPWM_Pos (28) |
TIMER_T::CTL TRGPWM Position
| #define TIMER_CTL_TRGSSEL_Msk (0x1ul << TIMER_CTL_TRGSSEL_Pos) |
TIMER_T::CTL TRGSSEL Mask
| #define TIMER_CTL_TRGSSEL_Pos (11) |
TIMER_T::CTL TRGSSEL Position
| #define TIMER_CTL_WKEN_Msk (0x1ul << TIMER_CTL_WKEN_Pos) |
TIMER_T::CTL WKEN Mask
| #define TIMER_CTL_WKEN_Pos (2) |
TIMER_T::CTL WKEN Position
| #define TIMER_ECTL_EVNTDPCNT_Msk (0xfful << TIMER_ECTL_EVNTDPCNT_Pos) |
TIMER_T::ECTL: EVNTDPCNT Mask
| #define TIMER_ECTL_EVNTDPCNT_Pos (24) |
TIMER_T::ECTL: EVNTDPCNT Position
| #define TIMER_INTEN_CAPIEN_Msk (0x1ul << TIMER_INTEN_CAPIEN_Pos) |
TIMER_T::INTEN: CAPIEN Mask
| #define TIMER_INTEN_CAPIEN_Pos (1) |
TIMER_T::INTEN: CAPIEN Position
| #define TIMER_INTEN_CNTIEN_Msk (0x1ul << TIMER_INTEN_CNTIEN_Pos) |
TIMER_T::INTEN: CNTIEN Mask
| #define TIMER_INTEN_CNTIEN_Pos (0) |
TIMER_T::INTEN: CNTIEN Position
| #define TIMER_INTSTS_CAPDATOF_Msk (0x1ul << TIMER_INTSTS_CAPDATOF_Pos) |
TIMER_T::INTSTS: CAPDATOF Mask
| #define TIMER_INTSTS_CAPDATOF_Pos (5) |
TIMER_T::INTSTS: CAPDATOF Position
| #define TIMER_INTSTS_CAPFEDF_Msk (0x1ul << TIMER_INTSTS_CAPFEDF_Pos) |
TIMER_T::INTSTS: CAPFEDF Mask
| #define TIMER_INTSTS_CAPFEDF_Pos (6) |
TIMER_T::INTSTS: CAPFEDF Position
| #define TIMER_INTSTS_CAPIF_Msk (0x1ul << TIMER_INTSTS_CAPIF_Pos) |
TIMER_T::INTSTS: CAPIF Mask
| #define TIMER_INTSTS_CAPIF_Pos (1) |
TIMER_T::INTSTS: CAPIF Position
| #define TIMER_INTSTS_CNTIF_Msk (0x1ul << TIMER_INTSTS_CNTIF_Pos) |
TIMER_T::INTSTS: CNTIF Mask
| #define TIMER_INTSTS_CNTIF_Pos (0) |
TIMER_T::INTSTS: CNTIF Position
| #define TIMER_INTSTS_TWKF_Msk (0x1ul << TIMER_INTSTS_TWKF_Pos) |
TIMER_T::INTSTS: TWKF Mask
| #define TIMER_INTSTS_TWKF_Pos (4) |
TIMER_T::INTSTS: TWKF Position
| #define TIMER_PRECNT_PSC_Msk (0xfful << TIMER_PRECNT_PSC_Pos) |
TIMER_T::PRECNT: PSC Mask
| #define TIMER_PRECNT_PSC_Pos (0) |
TIMER_T::PRECNT: PSC Position
| #define UART_ALTCTL_ADDRDEN_Msk (0x1ul << UART_ALTCTL_ADDRDEN_Pos) |
UART_T::ALTCTL: ADDRDEN Mask
| #define UART_ALTCTL_ADDRDEN_Pos (19) |
UART_T::ALTCTL: ADDRDEN Position
| #define UART_ALTCTL_ADRMPID_Msk (0xfful << UART_ALTCTL_ADRMPID_Pos) |
UART_T::ALTCTL: ADRMPID Mask
| #define UART_ALTCTL_ADRMPID_Pos (24) |
UART_T::ALTCTL: ADRMPID Position
| #define UART_ALTCTL_BITERREN_Msk (0x1ul << UART_ALTCTL_BITERREN_Pos) |
UART_T::ALTCTL: BITERREN Mask
| #define UART_ALTCTL_BITERREN_Pos (8) |
UART_T::ALTCTL: BITERREN Position
| #define UART_ALTCTL_BRKFL_Msk (0x7ul << UART_ALTCTL_BRKFL_Pos) |
UART_T::ALTCTL: BRKFL Mask
| #define UART_ALTCTL_BRKFL_Pos (0) |
UART_T::ALTCTL: BRKFL Position
| #define UART_ALTCTL_LINHSEL_Msk (0x3ul << UART_ALTCTL_LINHSEL_Pos) |
UART_T::ALTCTL: LINHSEL Mask
| #define UART_ALTCTL_LINHSEL_Pos (4) |
UART_T::ALTCTL: LINHSEL Position
| #define UART_ALTCTL_LINRXEN_Msk (0x1ul << UART_ALTCTL_LINRXEN_Pos) |
UART_T::ALTCTL: LINRXEN Mask
| #define UART_ALTCTL_LINRXEN_Pos (6) |
UART_T::ALTCTL: LINRXEN Position
| #define UART_ALTCTL_LINTXEN_Msk (0x1ul << UART_ALTCTL_LINTXEN_Pos) |
UART_T::ALTCTL: LINTXEN Mask
| #define UART_ALTCTL_LINTXEN_Pos (7) |
UART_T::ALTCTL: LINTXEN Position
| #define UART_ALTCTL_RS485AAD_Msk (0x1ul << UART_ALTCTL_RS485AAD_Pos) |
UART_T::ALTCTL: RS485AAD Mask
| #define UART_ALTCTL_RS485AAD_Pos (17) |
UART_T::ALTCTL: RS485AAD Position
| #define UART_ALTCTL_RS485AUD_Msk (0x1ul << UART_ALTCTL_RS485AUD_Pos) |
UART_T::ALTCTL: RS485AUD Mask
| #define UART_ALTCTL_RS485AUD_Pos (18) |
UART_T::ALTCTL: RS485AUD Position
| #define UART_ALTCTL_RS485NMM_Msk (0x1ul << UART_ALTCTL_RS485NMM_Pos) |
UART_T::ALTCTL: RS485NMM Mask
| #define UART_ALTCTL_RS485NMM_Pos (16) |
UART_T::ALTCTL: RS485NMM Position
| #define UART_BAUD_BRD_Msk (0xfffful << UART_BAUD_BRD_Pos) |
UART_T::BAUD: BRD Mask
| #define UART_BAUD_BRD_Pos (0) |
UART_T::BAUD: BRD Position
| #define UART_BAUD_DIV16EN_Msk (0x1ul << UART_BAUD_DIV16EN_Pos) |
UART_T::BAUD: DIV16EN Mask
| #define UART_BAUD_DIV16EN_Pos (31) |
UART_T::BAUD: DIV16EN Position
| #define UART_BRCOMPAT_BRCOMPAT_Msk (0x1fful << UART_BRCOMPAT_BRCOMPAT_Pos) |
UART_T::BRCOMPAT: BRCOMPAT Mask
| #define UART_BRCOMPAT_BRCOMPAT_Pos (0) |
UART_T::BRCOMPAT: BRCOMPAT Position
| #define UART_BRCOMPAT_BRCOMPDEC_Msk (0x1ul << UART_BRCOMPAT_BRCOMPDEC_Pos) |
UART_T::BRCOMPAT: BRCOMPDEC Mask
| #define UART_BRCOMPAT_BRCOMPDEC_Pos (31) |
UART_T::BRCOMPAT: BRCOMPDEC Position
| #define UART_CTRL_ABRDBITS_Msk (0x3ul << UART_CTRL_ABRDBITS_Pos) |
UART_T::CTRL: ABRDBITS Mask
| #define UART_CTRL_ABRDBITS_Pos (13) |
UART_T::CTRL: ABRDBITS Position
| #define UART_CTRL_ABRDEN_Msk (0x1ul << UART_CTRL_ABRDEN_Pos) |
UART_T::CTRL: ABRDEN Mask
| #define UART_CTRL_ABRDEN_Pos (12) |
UART_T::CTRL: ABRDEN Position
| #define UART_CTRL_ATOCTSEN_Msk (0x1ul << UART_CTRL_ATOCTSEN_Pos) |
UART_T::CTRL: ATOCTSEN Mask
| #define UART_CTRL_ATOCTSEN_Pos (5) |
UART_T::CTRL: ATOCTSEN Position
| #define UART_CTRL_ATORTSEN_Msk (0x1ul << UART_CTRL_ATORTSEN_Pos) |
UART_T::CTRL: ATORTSEN Mask
| #define UART_CTRL_ATORTSEN_Pos (4) |
UART_T::CTRL: ATORTSEN Position
| #define UART_CTRL_FTOEN_Msk (0x1ul << UART_CTRL_FTOEN_Pos) |
UART_T::CTRL: FTOEN Mask
| #define UART_CTRL_FTOEN_Pos (8) |
UART_T::CTRL: FTOEN Position
| #define UART_CTRL_RXDMAEN_Msk (0x1ul << UART_CTRL_RXDMAEN_Pos) |
UART_T::CTRL: RXDMAEN Mask
| #define UART_CTRL_RXDMAEN_Pos (6) |
UART_T::CTRL: RXDMAEN Position
| #define UART_CTRL_RXOFF_Msk (0x1ul << UART_CTRL_RXOFF_Pos) |
UART_T::CTRL: RXOFF Mask
| #define UART_CTRL_RXOFF_Pos (2) |
UART_T::CTRL: RXOFF Position
| #define UART_CTRL_RXRST_Msk (0x1ul << UART_CTRL_RXRST_Pos) |
UART_T::CTRL: RXRST Mask
| #define UART_CTRL_RXRST_Pos (0) |
UART_T::CTRL: RXRST Position
| #define UART_CTRL_TXDMAEN_Msk (0x1ul << UART_CTRL_TXDMAEN_Pos) |
UART_T::CTRL: TXDMAEN Mask
| #define UART_CTRL_TXDMAEN_Pos (7) |
UART_T::CTRL: TXDMAEN Position
| #define UART_CTRL_TXOFF_Msk (0x1ul << UART_CTRL_TXOFF_Pos) |
UART_T::CTRL: TXOFF Mask
| #define UART_CTRL_TXOFF_Pos (3) |
UART_T::CTRL: TXOFF Position
| #define UART_CTRL_TXRST_Msk (0x1ul << UART_CTRL_TXRST_Pos) |
UART_T::CTRL: TXRST Mask
| #define UART_CTRL_TXRST_Pos (1) |
UART_T::CTRL: TXRST Position
| #define UART_DAT_DAT_Msk (0xfful << UART_RBR_RBR_Pos) |
UART_T::DAT: DAT Mask
| #define UART_DAT_DAT_Pos (0) |
@addtogroup UART_CONST UART Bit Field Definition Constant Definitions for UART Controller
UART_T::DAT: DAT Position
| #define UART_FIFOSTS_BIF_Msk (0x1ul << UART_FIFOSTS_BIF_Pos) |
UART_T::FIFOSTS: BIF Mask
| #define UART_FIFOSTS_BIF_Pos (6) |
UART_T::FIFOSTS: BIF Position
| #define UART_FIFOSTS_FEF_Msk (0x1ul << UART_FIFOSTS_FEF_Pos) |
UART_T::FIFOSTS: FEF Mask
| #define UART_FIFOSTS_FEF_Pos (5) |
UART_T::FIFOSTS: FEF Position
| #define UART_FIFOSTS_PEF_Msk (0x1ul << UART_FIFOSTS_PEF_Pos) |
UART_T::FIFOSTS: PEF Mask
| #define UART_FIFOSTS_PEF_Pos (4) |
UART_T::FIFOSTS: PEF Position
| #define UART_FIFOSTS_RXEMPTY_Msk (0x1ul << UART_FIFOSTS_RXEMPTY_Pos) |
UART_T::FIFOSTS: RXEMPTY Mask
| #define UART_FIFOSTS_RXEMPTY_Pos (1) |
UART_T::FIFOSTS: RXEMPTY Position
| #define UART_FIFOSTS_RXFULL_Msk (0x1ul << UART_FIFOSTS_RXFULL_Pos) |
UART_T::FIFOSTS: RXFULL Mask
| #define UART_FIFOSTS_RXFULL_Pos (2) |
UART_T::FIFOSTS: RXFULL Position
| #define UART_FIFOSTS_RXOVIF_Msk (0x1ul << UART_FIFOSTS_RXOVIF_Pos) |
UART_T::FIFOSTS: RXOVIF Mask
| #define UART_FIFOSTS_RXOVIF_Pos (0) |
UART_T::FIFOSTS: RXOVIF Position
| #define UART_FIFOSTS_RXPTR_Msk (0x1ful << UART_FIFOSTS_RXPTR_Pos) |
UART_T::FIFOSTS: RXPTR Mask
| #define UART_FIFOSTS_RXPTR_Pos (16) |
UART_T::FIFOSTS: RXPTR Position
| #define UART_FIFOSTS_TXEMPTY_Msk (0x1ul << UART_FIFOSTS_TXEMPTY_Pos) |
UART_T::FIFOSTS: TXEMPTY Mask
| #define UART_FIFOSTS_TXEMPTY_Pos (9) |
UART_T::FIFOSTS: TXEMPTY Position
| #define UART_FIFOSTS_TXENDF_Msk (0x1ul << UART_FIFOSTS_TXENDF_Pos) |
UART_T::FIFOSTS: TXENDF Mask
| #define UART_FIFOSTS_TXENDF_Pos (11) |
UART_T::FIFOSTS: TXENDF Position
| #define UART_FIFOSTS_TXFULL_Msk (0x1ul << UART_FIFOSTS_TXFULL_Pos) |
UART_T::FIFOSTS: TXFULL Mask
| #define UART_FIFOSTS_TXFULL_Pos (10) |
UART_T::FIFOSTS: TXFULL Position
| #define UART_FIFOSTS_TXOVIF_Msk (0x1ul << UART_FIFOSTS_TXOVIF_Pos) |
UART_T::FIFOSTS: TXOVIF Mask
| #define UART_FIFOSTS_TXOVIF_Pos (8) |
UART_T::FIFOSTS: TXOVIF Position
| #define UART_FIFOSTS_TXPTR_Msk (0x1ful << UART_FIFOSTS_TXPTR_Pos) |
UART_T::FIFOSTS: TXPTR Mask
| #define UART_FIFOSTS_TXPTR_Pos (24) |
UART_T::FIFOSTS: TXPTR Position
| #define UART_FUNCSEL_FUNCSEL_Msk (0x3ul << UART_FUNCSEL_FUNCSEL_Pos) |
UART_T::FUNCSEL: FUNCSEL Mask
| #define UART_FUNCSEL_FUNCSEL_Pos (0) |
UART_T::FUNCSEL: FUNCSEL Position
| #define UART_INTEN_ABRIEN_Msk (0x1ul << UART_INTEN_ABRIEN_Pos) |
UART_T::INTEN: ABRIEN Mask
| #define UART_INTEN_ABRIEN_Pos (7) |
UART_T::INTEN: ABRIEN Position
| #define UART_INTEN_BUFERRIEN_Msk (0x1ul << UART_INTEN_BUFERRIEN_Pos) |
UART_T::INTEN: BUFERRIEN Mask
| #define UART_INTEN_BUFERRIEN_Pos (5) |
UART_T::INTEN: BUFERRIEN Position
| #define UART_INTEN_LINIEN_Msk (0x1ul << UART_INTEN_LINIEN_Pos) |
UART_T::INTEN: LINIEN Mask
| #define UART_INTEN_LINIEN_Pos (8) |
UART_T::INTEN: LINIEN Position
| #define UART_INTEN_MODEMIEN_Msk (0x1ul << UART_INTEN_MODEMIEN_Pos) |
UART_T::INTEN: MODEMIEN Mask
| #define UART_INTEN_MODEMIEN_Pos (3) |
UART_T::INTEN: MODEMIEN Position
| #define UART_INTEN_RDAIEN_Msk (0x1ul << UART_INTEN_RDAIEN_Pos) |
UART_T::INTEN: RDAIEN Mask
| #define UART_INTEN_RDAIEN_Pos (0) |
UART_T::INTEN: RDAIEN Position
| #define UART_INTEN_RLSIEN_Msk (0x1ul << UART_INTEN_RLSIEN_Pos) |
UART_T::INTEN: RLSIEN Mask
| #define UART_INTEN_RLSIEN_Pos (2) |
UART_T::INTEN: RLSIEN Position
| #define UART_INTEN_RXTOIEN_Msk (0x1ul << UART_INTEN_RXTOIEN_Pos) |
UART_T::INTEN: RXTOIEN Mask
| #define UART_INTEN_RXTOIEN_Pos (4) |
UART_T::INTEN: RXTOIEN Position
| #define UART_INTEN_THREIEN_Msk (0x1ul << UART_INTEN_THREIEN_Pos) |
UART_T::INTEN: THREIEN Mask
| #define UART_INTEN_THREIEN_Pos (1) |
UART_T::INTEN: THREIEN Position
| #define UART_INTEN_TXENDIEN_Msk (0x1ul << UART_INTEN_TXENDIEN_Pos) |
UART_T::INTEN: TXENDIEN Mask
| #define UART_INTEN_TXENDIEN_Pos (9) |
UART_T::INTEN: TXENDIEN Position
| #define UART_INTEN_WKUPIEN_Msk (0x1ul << UART_INTEN_WKUPIEN_Pos) |
UART_T::INTEN: WKUPIEN Mask
| #define UART_INTEN_WKUPIEN_Pos (6) |
UART_T::INTEN: WKUPIEN Position
| #define UART_INTSTS_ABRIF_Msk (0x1ul << UART_INTSTS_ABRIF_Pos) |
UART_T::INTSTS: ABRIF Mask
| #define UART_INTSTS_ABRIF_Pos (7) |
UART_T::INTSTS: ABRIF Position
| #define UART_INTSTS_BUFERRIF_Msk (0x1ul << UART_INTSTS_BUFERRIF_Pos) |
UART_T::INTSTS: BUFERRIF Mask
| #define UART_INTSTS_BUFERRIF_Pos (5) |
UART_T::INTSTS: BUFERRIF Position
| #define UART_INTSTS_LINIF_Msk (0x1ul << UART_INTSTS_LINIF_Pos) |
UART_T::INTSTS: LINEIF Mask
| #define UART_INTSTS_LINIF_Pos (8) |
UART_T::INTSTS: LINEIF Position
| #define UART_INTSTS_MODEMIF_Msk (0x1ul << UART_INTSTS_MODEMIF_Pos) |
UART_T::INTSTS: MODEMIF Mask
| #define UART_INTSTS_MODEMIF_Pos (3) |
UART_T::INTSTS: MODEMIF Position
| #define UART_INTSTS_RDAIF_Msk (0x1ul << UART_INTSTS_RDAIF_Pos) |
UART_T::INTSTS: RDAIF Mask
| #define UART_INTSTS_RDAIF_Pos (0) |
UART_T::INTSTS: RDAIF Position
| #define UART_INTSTS_RLSIF_Msk (0x1ul << UART_INTSTS_RLSIF_Pos) |
UART_T::INTSTS: RLSIF Mask
| #define UART_INTSTS_RLSIF_Pos (2) |
UART_T::INTSTS: RLSIF Position
| #define UART_INTSTS_RXTOIF_Msk (0x1ul << UART_INTSTS_RXTOIF_Pos) |
UART_T::INTSTS: RXTOIF Mask
| #define UART_INTSTS_RXTOIF_Pos (4) |
UART_T::INTSTS: RXTOIF Position
| #define UART_INTSTS_THREIF_Msk (0x1ul << UART_INTSTS_THREIF_Pos) |
UART_T::INTSTS: THREIF Mask
| #define UART_INTSTS_THREIF_Pos (1) |
UART_T::INTSTS: THREIF Position
| #define UART_INTSTS_WKUPIF_Msk (0x1ul << UART_INTSTS_WKUPIF_Pos) |
UART_T::INTSTS: WKUPIF Mask
| #define UART_INTSTS_WKUPIF_Pos (6) |
UART_T::INTSTS: WKUPIF Position
| #define UART_IRDA_RXINV_Msk (0x1ul << UART_IRDA_RXINV_Pos) |
UART_T::IRDA: RXINV Mask
| #define UART_IRDA_RXINV_Pos (6) |
UART_T::IRDA: RXINV Position
| #define UART_IRDA_TXEN_Msk (0x1ul << UART_IRDA_TXEN_Pos) |
UART_T::IRDA: TXEN Mask
| #define UART_IRDA_TXEN_Pos (1) |
UART_T::IRDA: TXEN Position
| #define UART_IRDA_TXINV_Msk (0x1ul << UART_IRDA_TXINV_Pos) |
UART_T::IRDA: TXINV Mask
| #define UART_IRDA_TXINV_Pos (5) |
UART_T::IRDA: TXINV Position
| #define UART_LINE_BCB_Msk (0x1ul << UART_LINE_BCB_Pos) |
UART_T::LINE: BCB Mask
| #define UART_LINE_BCB_Pos (6) |
UART_T::LINE: BCB Position
| #define UART_LINE_EPE_Msk (0x1ul << UART_LINE_EPE_Pos) |
UART_T::LINE: EPE Mask
| #define UART_LINE_EPE_Pos (4) |
UART_T::LINE: EPE Position
| #define UART_LINE_NSB_Msk (0x1ul << UART_LINE_NSB_Pos) |
UART_T::LINE: NSB Mask
| #define UART_LINE_NSB_Pos (2) |
UART_T::LINE: NSB Position
| #define UART_LINE_PBE_Msk (0x1ul << UART_LINE_PBE_Pos) |
UART_T::LINE: PBE Mask
| #define UART_LINE_PBE_Pos (3) |
UART_T::LINE: PBE Position
| #define UART_LINE_RFITL_Msk (0x3ul << UART_LINE_RFITL_Pos) |
UART_T::LINE: RFITL Mask
| #define UART_LINE_RFITL_Pos (8) |
UART_T::LINE: RFITL Position
| #define UART_LINE_RTSTRGLV_Msk (0x3ul << UART_LINE_RTSTRGLV_Pos) |
UART_T::LINE: RTSTRGLV Mask
| #define UART_LINE_RTSTRGLV_Pos (12) |
UART_T::LINE: RTSTRGLV Position
| #define UART_LINE_SPE_Msk (0x1ul << UART_LINE_SPE_Pos) |
UART_T::LINE: SPE Mask
| #define UART_LINE_SPE_Pos (5) |
UART_T::LINE: SPE Position
| #define UART_LINE_WLS_Msk (0x3ul << UART_LINE_WLS_Pos) |
UART_T::LINE: WLS Mask
| #define UART_LINE_WLS_Pos (0) |
UART_T::LINE: WLS Position
| #define UART_MODEM_CTSACTLV_Msk (0x1ul << UART_MODEM_CTSACTLV_Pos) |
UART_T::MODEM: CTSACTLV Mask
| #define UART_MODEM_CTSACTLV_Pos (16) |
UART_T::MODEM: CTSACTLV Position
| #define UART_MODEM_CTSDETF_Msk (0x1ul << UART_MODEM_CTSDETF_Pos) |
UART_T::MODEM: CTSDETF Mask
| #define UART_MODEM_CTSDETF_Pos (18) |
UART_T::MODEM: CTSDETF Position
| #define UART_MODEM_CTSSTS_Msk (0x1ul << UART_MODEM_CTSSTS_Pos) |
UART_T::MODEM: CTSSTS Mask
| #define UART_MODEM_CTSSTS_Pos (17) |
UART_T::MODEM: CTSSTS Position
| #define UART_MODEM_RTSACTLV_Msk (0x1ul << UART_MODEM_RTSACTLV_Pos) |
UART_T::MODEM: RTSACTLV Mask
| #define UART_MODEM_RTSACTLV_Pos (0) |
UART_T::MODEM: RTSACTLV Position
| #define UART_MODEM_RTSSTS_Msk (0x1ul << UART_MODEM_RTSSTS_Pos) |
UART_T::MODEM: RTSSTS Mask
| #define UART_MODEM_RTSSTS_Pos (1) |
UART_T::MODEM: RTSSTS Position
| #define UART_TOUT_DLY_Msk (0xfful << UART_TOUT_DLY_Pos) |
UART_T::TOUT: DLY Mask
| #define UART_TOUT_DLY_Pos (16) |
UART_T::TOUT: DLY Position
| #define UART_TOUT_TOIC_Msk (0x1fful << UART_TOUT_TOIC_Pos) |
UART_T::TOUT: TOIC Mask
| #define UART_TOUT_TOIC_Pos (0) |
UART_T::TOUT: TOIC Position
| #define UART_TRSR_ABRDIF_Msk (0x1ul << UART_TRSR_ABRDIF_Pos) |
UART_T::TRSR: ABRDIF Mask
| #define UART_TRSR_ABRDIF_Pos (1) |
UART_T::TRSR: ABRDIF Position
| #define UART_TRSR_ABRDTOIF_Msk (0x1ul << UART_TRSR_ABRDTOIF_Pos) |
UART_T::TRSR: ABRDTOIF Mask
| #define UART_TRSR_ABRDTOIF_Pos (2) |
UART_T::TRSR: ABRDTOIF Position
| #define UART_TRSR_ADDRDETF_Msk (0x1ul << UART_TRSR_ADDRDETF_Pos) |
UART_T::TRSR: ADDRDETF Mask
| #define UART_TRSR_ADDRDETF_Pos (0) |
UART_T::TRSR: ADDRDETF Position
| #define UART_TRSR_BITEF_Msk (0x1ul << UART_TRSR_BITEF_Pos) |
UART_T::TRSR: BITEF Mask
| #define UART_TRSR_BITEF_Pos (5) |
UART_T::TRSR: BITEF Position
| #define UART_TRSR_LINRXIF_Msk (0x1ul << UART_TRSR_LINRXIF_Pos) |
UART_T::TRSR: LINRXIF Mask
| #define UART_TRSR_LINRXIF_Pos (4) |
UART_T::TRSR: LINRXIF Position
| #define UART_TRSR_LINTXIF_Msk (0x1ul << UART_TRSR_LINTXIF_Pos) |
UART_T::TRSR: LINTXIF Mask
| #define UART_TRSR_LINTXIF_Pos (3) |
UART_T::TRSR: LINTXIF Position
| #define UART_TRSR_RXBUSY_Msk (0x1ul << UART_TRSR_RXBUSY_Pos) |
UART_T::TRSR: RXBUSY Mask
| #define UART_TRSR_RXBUSY_Pos (7) |
UART_T::TRSR: RXBUSY Position
| #define UART_TRSR_SLVSYNCF_Msk (0x1ul << UART_TRSR_SLVSYNCF_Pos) |
UART_T::TRSR: SLVSYNCF Mask
| #define UART_TRSR_SLVSYNCF_Pos (8) |
UART_T::TRSR: SLVSYNCF Position
| #define UART_WKUPEN_WKADRMEN_Msk (0x1ul << UART_WKUPEN_WKADRMEN_Pos) |
UART_T::WKUPEN: WKADRMEN Mask
| #define UART_WKUPEN_WKADRMEN_Pos (4) |
UART_T::WKUPEN: WKADRMEN Position
| #define UART_WKUPEN_WKCTSEN_Msk (0x1ul << UART_WKUPEN_WKCTSEN_Pos) |
UART_T::WKUPEN: WKCTSEN Mask
| #define UART_WKUPEN_WKCTSEN_Pos (0) |
UART_T::WKUPEN: WKCTSEN Position
| #define UART_WKUPEN_WKDATEN_Msk (0x1ul << UART_WKUPEN_WKDATEN_Pos) |
UART_T::WKUPEN: WKDATEN Mask
| #define UART_WKUPEN_WKDATEN_Pos (1) |
UART_T::WKUPEN: WKDATEN Position
| #define UART_WKUPEN_WKTHREN_Msk (0x1ul << UART_WKUPEN_WKTHREN_Pos) |
UART_T::WKUPEN: WKTHREN Mask
| #define UART_WKUPEN_WKTHREN_Pos (2) |
UART_T::WKUPEN: WKTHREN Position
| #define UART_WKUPEN_WKTHRTOEN_Msk (0x1ul << UART_WKUPEN_WKTHRTOEN_Pos) |
UART_T::WKUPEN: WKTHRTOEN Mask
| #define UART_WKUPEN_WKTHRTOEN_Pos (3) |
UART_T::WKUPEN: WKTHRTOEN Position
| #define UART_WKUPSTS_ADRWKSTS_Msk (0x1ul << UART_WKUPSTS_ADRWKSTS_Pos) |
UART_T::WKUPSTS: ADRWKSTS Mask
| #define UART_WKUPSTS_ADRWKSTS_Pos (4) |
UART_T::WKUPSTS: ADRWKSTS Position
| #define UART_WKUPSTS_CTSWKSTS_Msk (0x1ul << UART_WKUPSTS_CTSWKSTS_Pos) |
UART_T::WKUPSTS: CTSWKSTS Mask
| #define UART_WKUPSTS_CTSWKSTS_Pos (0) |
UART_T::WKUPSTS: CTSWKSTS Position
| #define UART_WKUPSTS_DATWKSTS_Msk (0x1ul << UART_WKUPSTS_DATWKSTS_Pos) |
UART_T::WKUPSTS: DATWKSTS Mask
| #define UART_WKUPSTS_DATWKSTS_Pos (1) |
UART_T::WKUPSTS: DATWKSTS Position
| #define UART_WKUPSTS_THRTOWKSTS_Msk (0x1ul << UART_WKUPSTS_THRTOWKSTS_Pos) |
UART_T::WKUPSTS: THRTOWKSTS Mask
| #define UART_WKUPSTS_THRTOWKSTS_Pos (3) |
UART_T::WKUPSTS: THRTOWKSTS Position
| #define UART_WKUPSTS_THRWKSTS_Msk (0x1ul << UART_WKUPSTS_THRWKSTS_Pos) |
UART_T::WKUPSTS: THRWKSTS Mask
| #define UART_WKUPSTS_THRWKSTS_Pos (2) |
UART_T::WKUPSTS: THRWKSTS Position
| #define WDT_CTL_DBGEN_Msk (0x1ul << WDT_CTL_DBGEN_Pos) |
WDT_T::CTL: DBGEN Mask
| #define WDT_CTL_DBGEN_Pos (31) |
WDT_T::CTL: DBGEN Position
| #define WDT_CTL_RSTCNT_Msk (0x1ul << WDT_CTL_RSTCNT_Pos) |
WDT_T::CTL: WTR Mask
| #define WDT_CTL_RSTCNT_Pos (0) |
@addtogroup WDT_CONST WDT Bit Field Definition Constant Definitions for WDT Controller
WDT_T::CTL: WTR Position
| #define WDT_CTL_RSTEN_Msk (0x1ul << WDT_CTL_RSTEN_Pos) |
WDT_T::CTL: WTRE Mask
| #define WDT_CTL_RSTEN_Pos (1) |
WDT_T::CTL: WTRE Position
| #define WDT_CTL_WDTEN_Msk (0x1ul << WDT_CTL_WDTEN_Pos) |
WDT_T::CTL: WTE Mask
| #define WDT_CTL_WDTEN_Pos (3) |
WDT_T::CTL: WTE Position
| #define WDT_CTL_WKEN_Msk (0x1ul << WDT_CTL_WKEN_Pos) |
WDT_T::CTL: WTWKE Mask
| #define WDT_CTL_WKEN_Pos (2) |
WDT_T::CTL: WTWKE Position
| #define WDT_CTL_WTIS_Msk (0x7ul << WDT_CTL_WTIS_Pos) |
WDT_T::CTL: WTIS Mask
| #define WDT_CTL_WTIS_Pos (4) |
WDT_T::CTL: WTIS Position
| #define WDT_CTL_WTRDSEL_Msk (0x3ul << WDT_CTL_WTRDSEL_Pos) |
WDT_T::CTL: WTRDSEL Mask
| #define WDT_CTL_WTRDSEL_Pos (8) |
WDT_T::CTL: WTRDSEL Position
| #define WDT_INTEN_WDTIE_Msk (0x1ul << WDT_INTEN_WDTIE_Pos) |
WDT_T::INTEN: WDT_IE Mask
| #define WDT_INTEN_WDTIE_Pos (0) |
WDT_T::INTEN: WDT_IE Position
| #define WDT_STATUS_RSTF_Msk (0x1ul << WDT_STATUS_RSTF_Pos) |
WDT_T::STATUS: WDT_RST_IS Mask
| #define WDT_STATUS_RSTF_Pos (1) |
WDT_T::STATUS: WDT_RST_IS Position
| #define WDT_STATUS_WDTIF_Msk (0x1ul << WDT_STATUS_WDTIF_Pos) |
WDT_T::STATUS: WDT_IS Mask
| #define WDT_STATUS_WDTIF_Pos (0) |
WDT_T::STATUS: WDT_IS Position
| #define WDT_STATUS_WKF_Msk (0x1ul << WDT_STATUS_WKF_Pos) |
WDT_T::STATUS: WDT_WAKE_IS Mask
| #define WDT_STATUS_WKF_Pos (2) |
WDT_T::STATUS: WDT_WAKE_IS Position
| #define WWDT_CNT_WWDT_CNTDAT_Msk (0x3ful << WWDT_CNT_WWDT_CNTDAT_Pos) |
WWDT_T::CNT: WWDT_VAL Mask
| #define WWDT_CNT_WWDT_CNTDAT_Pos (0) |
WWDT_T::CNT: WWDT_VAL Position
| #define WWDT_CTL_DBGEN_Msk (0x1ul << WWDT_CTL_DBGEN_Pos) |
WWDT_T::CTL: DBGEN Mask
| #define WWDT_CTL_DBGEN_Pos (31) |
WWDT_T::CTL: DBGEN Position
| #define WWDT_CTL_PERIODSEL_Msk (0xful << WWDT_CTL_PERIODSEL_Pos) |
WWDT_T::CTL: PERIODSEL Mask
| #define WWDT_CTL_PERIODSEL_Pos (8) |
WWDT_T::CTL: PERIODSEL Position
| #define WWDT_CTL_WINCMP_Msk (0x3ful << WWDT_CTL_WINCMP_Pos) |
WWDT_T::CTL: WINCMP Mask
| #define WWDT_CTL_WINCMP_Pos (16) |
WWDT_T::CTL: WINCMP Position
| #define WWDT_CTL_WWDTEN_Msk (0x1ul << WWDT_CTL_WWDTEN_Pos) |
WWDT_T::CTL: WWDTEN Mask
| #define WWDT_CTL_WWDTEN_Pos (0) |
WWDT_T::CTL: WWDTEN Position
| #define WWDT_INTEN_WWDTIE_Msk (0x1ul << WWDT_INTEN_WWDTIE_Pos) |
WWDT_T::INTEN: WWDTIE Mask
| #define WWDT_INTEN_WWDTIE_Pos (0) |
WWDT_T::INTEN: WWDTIE Position
| #define WWDT_RLDCNT_RLDCNT_Msk (0xfffffffful << WWDT_RLDCNT_RLDCNT_Pos) |
WWDT_T::RLDCNT: WWDT_RLD Mask
| #define WWDT_RLDCNT_RLDCNT_Pos (0) |
@addtogroup WWDT_CONST WWDT Bit Field Definition Constant Definitions for WWDT Controller
WWDT_T::RLDCNT: WWDT_RLD Position
| #define WWDT_STATUS_WWDTIF_Msk (0x1ul << WWDT_STATUS_WWDTIF_Pos) |
WWDT_T::STATUS: WWDTIF Mask
| #define WWDT_STATUS_WWDTIF_Pos (0) |
WWDT_T::STATUS: WWDTIF Position
| #define WWDT_STATUS_WWDTRF_Msk (0x1ul << WWDT_STATUS_WWDTRF_Pos) |
WWDT_T::STATUS: WWDTRF Mask
| #define WWDT_STATUS_WWDTRF_Pos (1) |
WWDT_T::STATUS: WWDTRF Position
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