36 #define PDMA_WIDTH_8 0x00080000UL 37 #define PDMA_WIDTH_16 0x00100000UL 38 #define PDMA_WIDTH_32 0x00000000UL 43 #define PDMA_SAR_INC 0x00000000UL 44 #define PDMA_SAR_FIX 0x00000020UL 45 #define PDMA_SAR_WRA 0x00000030UL 46 #define PDMA_DAR_INC 0x00000000UL 47 #define PDMA_DAR_FIX 0x00000080UL 48 #define PDMA_DAR_WRA 0x000000C0UL 53 #define PDMA_SPI0_TX 0x00000000UL 54 #define PDMA_SPI1_TX 0x00000001UL 55 #define PDMA_UART0_TX 0x00000002UL 56 #define PDMA_UART1_TX 0x00000003UL 57 #define PDMA_SPI3_TX 0x00000005UL 58 #define PDMA_SPI2_TX 0x00000008UL 59 #define PDMA_TMR0 0x00000009UL 60 #define PDMA_TMR1 0x0000000AUL 61 #define PDMA_TMR2 0x0000000BUL 62 #define PDMA_TMR3 0x0000000CUL 64 #define PDMA_SPI0_RX 0x00000010UL 65 #define PDMA_SPI1_RX 0x00000011UL 66 #define PDMA_UART0_RX 0x00000012UL 67 #define PDMA_UART1_RX 0x00000013UL 68 #define PDMA_SPI3_RX 0x00000015UL 69 #define PDMA_ADC 0x00000016UL 70 #define PDMA_SPI2_RX 0x00000018UL 71 #define PDMA_MEM 0x0000001FUL 76 #define PDMA_TOC_TPSC_HCLK_DIV_2POW8 0x00000000UL 77 #define PDMA_TOC_TPSC_HCLK_DIV_2POW9 0x00000000UL 78 #define PDMA_TOC_TPSC_HCLK_DIV_2POW10 0x00000000UL 79 #define PDMA_TOC_TPSC_HCLK_DIV_2POW11 0x00000000UL 80 #define PDMA_TOC_TPSC_HCLK_DIV_2POW12 0x00000000UL 81 #define PDMA_TOC_TPSC_HCLK_DIV_2POW13 0x00000000UL 82 #define PDMA_TOC_TPSC_HCLK_DIV_2POW14 0x00000000UL 83 #define PDMA_TOC_TPSC_HCLK_DIV_2POW15 0x00000000UL 101 #define PDMA_GET_INT_STATUS() ((uint32_t)(PDMAGCR->GINTSTS)) 113 #define PDMA_GET_CH_INT_STS(u32Ch) (*((__IO uint32_t *)((uint32_t)&PDMA1->INTSTSn + (uint32_t)((u32Ch-1)*0x100)))) 126 #define PDMA_CLR_CH_INT_FLAG(u32Ch, u32Mask) (*((__IO uint32_t *)((uint32_t)&PDMA1->INTSTSn + (uint32_t)((u32Ch-1)*0x100))) = (u32Mask)) 139 #define PDMA_IS_CH_BUSY(u32Ch) ((*((__IO uint32_t *)((uint32_t)&PDMA1->CTLn +(uint32_t)((u32Ch-1)*0x100))) & PDMA_CH_CTLn_TRIGEN_Msk)? 1 : 0) 152 #define PDMA_SET_SRC_ADDR(u32Ch, u32Addr) (*((__IO uint32_t *)((uint32_t)&PDMA1->SAn + (uint32_t)((u32Ch-1)*0x100))) = (u32Addr)) 165 #define PDMA_SET_DST_ADDR(u32Ch, u32Addr) (*((__IO uint32_t *)((uint32_t)&PDMA1->DAn + (uint32_t)((u32Ch-1)*0x100))) = (u32Addr)) 178 #define PDMA_SET_TRANS_CNT(u32Ch, u32Count) \ 179 (*((__IO uint32_t *)((uint32_t)&PDMA1->CNTn + (uint32_t)((u32Ch-1)*0x100))) = \ 180 ((*((__IO uint32_t *)((uint32_t)&PDMA1->CNTn + (uint32_t)((u32Ch-1)*0x100))) & ~PDMA_CH_CNTn_TCNT_Msk) | (u32Count & 0xffff))) \ 194 #define PDMA_SET_PERIODIC_CNT(u32Ch, u32Count) \ 195 (*((__IO uint32_t *)((uint32_t)&PDMA1->CNTn + (uint32_t)((u32Ch-1)*0x100))) = \ 196 ((*((__IO uint32_t *)((uint32_t)&PDMA1->CNTn + (uint32_t)((u32Ch-1)*0x100))) & ~PDMA_CH_TOCn_TPSC_Msk) | ((u32Count & 0xffff) << PDMA_CH_TOCn_TPSC_Pos))) \ 209 #define PDMA_STOP(u32Ch) (*((__IO uint32_t *)((uint32_t)&PDMA1->CTLn + (uint32_t)((u32Ch-1)*0x100))) &= ~PDMA_CH_CTLn_CHEN_Msk) 214 void PDMA_SetTransferAddr(uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl);
215 void PDMA_SetTransferMode(uint32_t u32Ch, uint32_t u32Periphral, uint32_t u32ScatterEn, uint32_t u32DescAddr);
216 void PDMA_SetTimeOut(uint32_t u32Ch, uint32_t u32OnOff, uint32_t u32TimeOutCnt);
void PDMA_SetTransferMode(uint32_t u32Ch, uint32_t u32Periphral, uint32_t u32ScatterEn, uint32_t u32DescAddr)
Set PDMA Transfer Mode.
void PDMA_Close(void)
PDMA Close.
void PDMA_SetTransferCnt(uint32_t u32Ch, uint32_t u32Width, uint32_t u32TransCount)
Set PDMA Transfer Count.
void PDMA_Trigger(uint32_t u32Ch)
Trigger PDMA.
void PDMA_EnableInt(uint32_t u32Ch, uint32_t u32Mask)
Enable Interrupt.
void PDMA_DisableInt(uint32_t u32Ch, uint32_t u32Mask)
Disable Interrupt.
void PDMA_Open(uint32_t u32Mask)
PDMA Open.
void PDMA_SetTransferAddr(uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl)
Set PDMA Transfer Address.
void PDMA_SetTimeOut(uint32_t u32Ch, uint32_t u32OnOff, uint32_t u32TimeOutCnt)
Set PDMA Timeout.