Nano103 BSP  V3.01.002
The Board Support Package for Nano103 Series
Data Fields
PDMA_CH_T Struct Reference

#include <Nano103.h>

Data Fields

__IO uint32_t CTLn
 
__IO uint32_t SAn
 
__IO uint32_t DAn
 
__IO uint32_t CNTn
 
__I uint32_t CSAn
 
__I uint32_t CDAn
 
__I uint32_t CCNTn
 
__IO uint32_t INTENn
 
__IO uint32_t INTSTSn
 
__IO uint32_t TOCn
 

Detailed Description

@addtogroup DMA Direct Memory Access Controller(DMA)
Memory Mapped Structure for DMA Controller

Definition at line 12499 of file Nano103.h.

Field Documentation

◆ CCNTn

PDMA_CH_T::CCNTn

[0x001c] PDMA channel n Current Transfer Count Register

CCNTn

Offset: 0x1C PDMA channel n Current Transfer Count Register

BitsFieldDescriptions
[15:0]CCNT
PDMA Current Count Bits (Read Only)
This field indicates the current remained transfer count of PDMA.
Note: This field value will be cleared to 0 when user sets SWRST (PDMA_CTLn[1],n=1~4) to 1.

Definition at line 12881 of file Nano103.h.

◆ CDAn

PDMA_CH_T::CDAn

[0x0018] PDMA channel n Current Destination Address Register

CDAn

Offset: 0x18 PDMA channel n Current Destination Address Register

BitsFieldDescriptions
[31:0]CDA
PDMA Current Destination Address Bits (Read Only)
This field indicates the destination address where the PDMA transfer just occurred.

Definition at line 12880 of file Nano103.h.

◆ CNTn

PDMA_CH_T::CNTn

[0x000c] PDMA channel n Transfer Count Register

CNTn

Offset: 0x0C PDMA channel n Transfer Count Register

BitsFieldDescriptions
[15:0]TCNT
PDMA Transfer Count Bits
This field indicates a 16-bit transfer count number of PDMA.
[31:16]PCNTITH
PDMA Periodic Count Interrupt Threshold
This field indicates how many data transferred to generate periodic interrupt
Note: write 0 to this field to disable this function.

Definition at line 12875 of file Nano103.h.

◆ CSAn

PDMA_CH_T::CSAn

[0x0014] PDMA channel n Current Source Address Register

CSAn

Offset: 0x14 PDMA channel n Current Source Address Register

BitsFieldDescriptions
[31:0]CSA
PDMA Current Source Address Bits (Read Only)
This field indicates the source address where the PDMA transfer just occurred.

Definition at line 12879 of file Nano103.h.

◆ CTLn

PDMA_CH_T::CTLn

[0x0000] PDMA channel n Control Register

CTLn

Offset: 0x00 PDMA channel n Control Register

BitsFieldDescriptions
[0]CHEN
PDMA Channel Enable Bit
Setting this bit to 1 enables PDMA operation
If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state.
Note: SWRST (PDMA_CTLn[1], n= 1~4) will clear this bit.
[1]SWRST
Software Engine Reset
0 = No effect.
1 = Reset the internal state machine, pointers and internal buffer
The contents of all control registers will not be cleared
This bit will be automatically cleared after few clock cycles.
[5:4]SASEL
Transfer Source Address Direction Selection
00 = Transfer Source address is incremented successively.
01 = Reserved.
10 = Transfer Source address is fixed (This feature can be used when data where transferred from a single source to multiple destinations).
11 = Transfer Source address is wrap around (When the PDMA_CCNT is equal to 0, the PDMA_CSA and PDMA_CCNT registers will be updated by PDMA_SA and PDMA_CNT automatically
PDMA will start another transfer without user trigger until CHEN disabled
When the CHEN is disabled, the PDMA will complete the active transfer but the remained data which in the PDMA buffer will not transfer to destination address).
[7:6]DASEL
Transfer Destination Address Direction Selection
00 = Transfer Destination address is incremented successively.
01 = Reserved.
10 = Transfer Destination address is fixed
(This feature can be used when data transferred from multiple sources to a single destination).
11 = Transfer Destination address is wrapped around (When the PDMA_CCNT is equal to 0, the PDMA_CDA and PDMA_CCNT registers will be updated by PDMA_DA and PDMA_CNT automatically
PDMA will start another transfer without user trigger until CHEN disabled
When the CHEN is disabled, the PDMA will complete the active transfer but the remained data which in the PDMA buffer will not transfer to destination address).
[12]TOUTEN
Time-out Enable Bit
This bit will enable PDMA Time-out counter (PDMA_TOCn, n=1~4)
While this counter counts to 0, the TOUTIF (PDMA_INTSTSn[6], n=1~4) will be set.
0 = PDMA internal counter Disabled.
1 = PDMA internal counter Enabled.
[20:19]TXWIDTH
Transfer Width Selection
This field is used for transfer width.
00 = One word (32-bit) is transferred for every PDMA operation.
01 = One byte (8-bit) is transferred for every PDMA operation.
10 = One half-word (16-bit) is transferred for every PDMA operation.
11 = Reserved.
[23]TRIGEN
Trigger Enable Bit
0 = No effect.
1 = PDMA data transfer Enabled.
Note1: When PDMA transfer completed, this bit will be cleared automatically.
Note2: If the bus error occurs, all PDMA transfer will be stopped
User must reset all PDMA channels, and then trigger again.

Definition at line 12872 of file Nano103.h.

◆ DAn

PDMA_CH_T::DAn

[0x0008] PDMA channel n Destination Address Register

DAn

Offset: 0x08 PDMA channel n Destination Address Register

BitsFieldDescriptions
[31:0]DA
PDMA Transfer Destination Address Bits
This field indicates a 32-bit destination address of PDMA.
Note: The Destination address must be word alignment.

Definition at line 12874 of file Nano103.h.

◆ INTENn

PDMA_CH_T::INTENn

[0x0020] PDMA channel n Interrupt Enable Register

INTENn

Offset: 0x20 PDMA channel n Interrupt Enable Register

BitsFieldDescriptions
[0]TABTIEN
PDMA Read/Write Target Abort Interrupt Enable Bit
0 = Target abort interrupt Disabled during PDMA transfer.
1 = Target abort interrupt Enabled during PDMA transfer.
[1]TDIEN
PDMA Transfer Done Interrupt Enable Bit
0 = Interrupt Disabled when PDMA transfer is done.
1 = Interrupt Enabled when PDMA transfer is done.
[6]TOUTIEN
Time-out Interrupt Enable Bit
0 = Time-out interrupt Disabled.
1 = Time-out interrupt Enabled.
[8]PCNTIEN
Periodic Count Interrupt Enable Bit
This field indicates how many data transferred to generate interrupt periodically.
0 = Periodic transfer count interrupt Disabled.
1 = Periodic transfer count interrupt Enabled.

Definition at line 12882 of file Nano103.h.

◆ INTSTSn

PDMA_CH_T::INTSTSn

[0x0024] PDMA channel n Interrupt Status Register

INTSTSn

Offset: 0x24 PDMA channel n Interrupt Status Register

BitsFieldDescriptions
[0]TABTIF
PDMA Read/Write Target Abort Interrupt Status Flag
0 = No bus ERROR response received.
1 = Bus ERROR response received.
Note1: This bit is cleared by writing 1 to it.
Note2: This bit indicates bus master received error response or not, if bus master received error response, it means that target abort is happened
PDMA controller will stop transfer and respond this event to user then go to IDLE state
When target abort occurred, user must reset PDMA controller, and then transfer those data again.
[1]TDIF
Transfer Done Interrupt Status Flag
This bit indicates that PDMA has finished all transfer.
0 = Not finished yet.
1 = Done.
Note: This bit is cleared by writing 1 to it.
[6]TOUTIF
Time-out Interrupt Status Flag
This flag indicated that PDMA has waited peripheral request for a period defined by PDMA_TOC.
0 = No time-out flag.
1 = Time-out flag.
Note: This bit is cleared by writing 1 to it.
[8]PCNTIF
Periodic Count Interrupt Status Flag
This flag indicates PCNTITH (PDMA_CNTn[30:16], n=1~4) data has been transferred.
Note: This bit is cleared by writing 1 to it.

Definition at line 12883 of file Nano103.h.

◆ SAn

PDMA_CH_T::SAn

[0x0004] PDMA channel n Source Address Register

SAn

Offset: 0x04 PDMA channel n Source Address Register

BitsFieldDescriptions
[31:0]SA
PDMA Transfer Source Address Bits
This field indicates a 32-bit source address of PDMA.
Note: The source address must be word alignment.

Definition at line 12873 of file Nano103.h.

◆ TOCn

PDMA_CH_T::TOCn

[0x0028] PDMA channel n Time-out Counter Register

TOCn

Offset: 0x28 PDMA channel n Time-out Counter Register

BitsFieldDescriptions
[15:0]TOC
PDMA Time-out Period Counter
Each PDMA channel contains an internal counter
This internal counter will reload and start counting when completing each peripheral request service
The internal counter loads the value of TOC (PDAM_TOCn[15:0], n=1~4) and starts counting down when setting TOUTEN (PDMA_CTLn[12], n=1~4)
PDMA will request interrupt when this internal counter reaches 0 and TOUTIEN (PDMA_INTENn[6], n=1~4) is 1
[18:16]TPSC
PDMA Time-out Counter Clock Source Prescaler
000 = PDMA time-out clock source is HCLK/28.
001 = PDMA time-out clock source is HCLK/29.
010 = PDMA time-out clock source is HCLK/210.
011 = PDMA time-out clock source is HCLK/211.
100 = PDMA time-out clock source is HCLK/212.
101 = PDMA time-out clock source is HCLK/213.
110 = PDMA time-out clock source is HCLK/214.
111 = PDMA time-out clock source is HCLK/215.

Definition at line 12884 of file Nano103.h.


The documentation for this struct was generated from the following file: