| Nano103 BSP V3.01.002 The Board Support Package for Nano103 Series

spi.c
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1 /****************************************************************************/
13 #include "Nano103.h"
14
47 uint32_t SPI_Open(SPI_T *spi,
48 uint32_t u32MasterSlave,
49 uint32_t u32SPIMode,
50 uint32_t u32DataWidth,
51 uint32_t u32BusClock)
52 {
53 if(u32DataWidth == 32)
54 u32DataWidth = 0;
55
56 spi->CTL = u32MasterSlave | (u32DataWidth << SPI_CTL_DWIDTH_Pos) | (u32SPIMode);
57
58 return ( SPI_SetBusClock(spi, u32BusClock) );
59 }
60
66 void SPI_Close(SPI_T *spi)
67 {
68 /* Reset SPI */
69 if((uint32_t)spi == SPI0_BASE && (CLK->APBCLK & CLK_APBCLK_SPI0CKEN_Msk))
70 {
71 CLK->APBCLK &= ~CLK_APBCLK_SPI0CKEN_Msk;
72 SYS->IPRST2 |= SYS_IPRST2_SPI0RST_Msk;
73 SYS->IPRST2 &= ~SYS_IPRST2_SPI0RST_Msk;
74 CLK->APBCLK |= CLK_APBCLK_SPI0CKEN_Msk;
75 }
76 else if((uint32_t)spi == SPI1_BASE && (CLK->APBCLK & CLK_APBCLK_SPI1CKEN_Msk))
77 {
78 CLK->APBCLK &= ~CLK_APBCLK_SPI1CKEN_Msk;
79 SYS->IPRST2 |= SYS_IPRST2_SPI1RST_Msk;
80 SYS->IPRST2 &= ~SYS_IPRST2_SPI1RST_Msk;
81 CLK->APBCLK |= CLK_APBCLK_SPI1CKEN_Msk;
82 }
83 else if((uint32_t)spi == SPI2_BASE && (CLK->APBCLK & CLK_APBCLK_SPI2CKEN_Msk))
84 {
85 CLK->APBCLK &= ~CLK_APBCLK_SPI2CKEN_Msk;
86 SYS->IPRST2 |= SYS_IPRST2_SPI2RST_Msk;
87 SYS->IPRST2 &= ~SYS_IPRST2_SPI2RST_Msk;
88 CLK->APBCLK |= CLK_APBCLK_SPI2CKEN_Msk;
89 }
90 else if((uint32_t)spi == SPI3_BASE && (CLK->APBCLK & CLK_APBCLK_SPI3CKEN_Msk))
91 {
92 CLK->APBCLK &= ~CLK_APBCLK_SPI3CKEN_Msk;
93 SYS->IPRST2 |= SYS_IPRST2_SPI3RST_Msk;
94 SYS->IPRST2 &= ~SYS_IPRST2_SPI3RST_Msk;
95 CLK->APBCLK |= CLK_APBCLK_SPI3CKEN_Msk;
96 }
97 }
98
104 void SPI_ClearRxFIFO(SPI_T *spi)
105 {
106 spi->FIFOCTL |= SPI_FIFOCTL_RXFBCLR_Msk;
107 }
108
114 void SPI_ClearTxFIFO(SPI_T *spi)
115 {
116 spi->FIFOCTL |= SPI_FIFOCTL_TXFBCLR_Msk;
117 }
118
124 void SPI_DisableAutoSS(SPI_T *spi)
125 {
126 spi->SSCTL &= ~SPI_SSCTL_AUTOSS_Msk;
127 }
128
140 void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel)
141 {
142 spi->SSCTL = (spi->SSCTL & ~(SPI_SSCTL_SSACTPOL_Msk | SPI_SSCTL_SS_Msk)) | (u32SSPinMask | u32ActiveLevel) | SPI_SSCTL_AUTOSS_Msk;
143 }
144
151 uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock)
152 {
153 uint32_t u32ClkSrc, u32Div = 0;
154
155 if(spi == SPI0)
156 {
157 if((CLK->CLKSEL1 & CLK_CLKSEL1_SPI0SEL_Msk) == CLK_CLKSEL1_SPI0SEL_HCLK)
158 u32ClkSrc = CLK_GetHCLKFreq();
159 else if((CLK->CLKSEL1 & CLK_CLKSEL1_SPI0SEL_Msk) == CLK_CLKSEL1_SPI0SEL_PLL)
160 u32ClkSrc = CLK_GetPLLClockFreq();
161 else if((CLK->CLKSEL1 & CLK_CLKSEL1_SPI0SEL_Msk) == CLK_CLKSEL1_SPI0SEL_HXT)
162 u32ClkSrc = __HXT;
163 else //CLK_CLKSEL1_SPI0SEL_HIRC
164 {
165 if((CLK->CLKSEL0 & CLK_CLKSEL0_HIRCSEL_Msk)==CLK_CLKSEL0_HIRCSEL_Msk)
166 u32ClkSrc = __HIRC36M;
167 else
168 {
169 if((CLK->PWRCTL & CLK_PWRCTL_HIRC0EN_Msk)==CLK_PWRCTL_HIRC0EN_Msk)
170 u32ClkSrc = __HIRC16M;
171 else
172 u32ClkSrc = __HIRC12M;
173 }
174 }
175 }
176 else if(spi == SPI1)
177 {
178 if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_HCLK)
179 u32ClkSrc = CLK_GetHCLKFreq();
180 else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PLL)
181 u32ClkSrc = CLK_GetPLLClockFreq();
182 else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_HXT)
183 u32ClkSrc = __HXT;
184 else //CLK_CLKSEL2_SPI1SEL_HIRC
185 {
186 if((CLK->CLKSEL0 & CLK_CLKSEL0_HIRCSEL_Msk)==CLK_CLKSEL0_HIRCSEL_Msk)
187 u32ClkSrc = __HIRC36M;
188 else
189 {
190 if((CLK->PWRCTL & CLK_PWRCTL_HIRC0EN_Msk)==CLK_PWRCTL_HIRC0EN_Msk)
191 u32ClkSrc = __HIRC16M;
192 else
193 u32ClkSrc = __HIRC12M;
194 }
195 }
196 }
197 else if(spi == SPI2)
198 {
199 if((CLK->CLKSEL1 & CLK_CLKSEL1_SPI2SEL_Msk) == CLK_CLKSEL1_SPI2SEL_HCLK)
200 u32ClkSrc = CLK_GetHCLKFreq();
201 else if((CLK->CLKSEL1 & CLK_CLKSEL1_SPI2SEL_Msk) == CLK_CLKSEL1_SPI2SEL_PLL)
202 u32ClkSrc = CLK_GetPLLClockFreq();
203 else if((CLK->CLKSEL1 & CLK_CLKSEL1_SPI2SEL_Msk) == CLK_CLKSEL1_SPI2SEL_HXT)
204 u32ClkSrc = __HXT;
205 else //CLK_CLKSEL1_SPI2SEL_HIRC
206 {
207 if((CLK->CLKSEL0 & CLK_CLKSEL0_HIRCSEL_Msk)== CLK_CLKSEL0_HIRCSEL_Msk)
208 u32ClkSrc = __HIRC36M;
209 else
210 {
211 if((CLK->PWRCTL & CLK_PWRCTL_HIRC0EN_Msk)==CLK_PWRCTL_HIRC0EN_Msk)
212 u32ClkSrc = __HIRC16M;
213 else
214 u32ClkSrc = __HIRC12M;
215 }
216 }
217 }
218 else
219 {
220 if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI3SEL_Msk) == CLK_CLKSEL2_SPI3SEL_HCLK)
221 u32ClkSrc = CLK_GetHCLKFreq();
222 else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI3SEL_Msk) == CLK_CLKSEL2_SPI3SEL_PLL)
223 u32ClkSrc = CLK_GetPLLClockFreq();
224 else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI3SEL_Msk) == CLK_CLKSEL2_SPI3SEL_HXT)
225 u32ClkSrc = __HXT;
226 else //CLK_CLKSEL2_SPI3SEL_HIRC
227 {
228 if((CLK->CLKSEL0 & CLK_CLKSEL0_HIRCSEL_Msk)== CLK_CLKSEL0_HIRCSEL_Msk)
229 u32ClkSrc = __HIRC36M;
230 else
231 {
232 if((CLK->PWRCTL & CLK_PWRCTL_HIRC0EN_Msk)==CLK_PWRCTL_HIRC0EN_Msk)
233 u32ClkSrc = __HIRC16M;
234 else
235 u32ClkSrc = __HIRC12M;
236 }
237 }
238 }
239 if(u32BusClock > u32ClkSrc)
240 u32BusClock = u32ClkSrc;
241
242 if(u32BusClock != 0 )
243 {
244 u32Div = (u32ClkSrc / u32BusClock) - 1;
245 if(u32Div > SPI_CLKDIV_DIVIDER_Msk)
246 u32Div = SPI_CLKDIV_DIVIDER_Msk;
247 }
248 else
249 return 0;
250
251 spi->CLKDIV = (spi->CLKDIV & ~SPI_CLKDIV_DIVIDER_Msk) | u32Div;
252
253 return ( u32ClkSrc / (u32Div+1) );
254 }
255
263 void SPI_EnableFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold)
264 {
265 spi->FIFOCTL = ((spi->FIFOCTL & ~(SPI_FIFOCTL_TXTH_Msk) | SPI_FIFOCTL_RXTH_Msk) |
266 (u32TxThreshold << SPI_FIFOCTL_TXTH_Pos) |
267 (u32RxThreshold << SPI_FIFOCTL_RXTH_Pos));
268
269 spi->CTL |= SPI_CTL_FIFOM_Msk;
270 }
271
277 void SPI_DisableFIFO(SPI_T *spi)
278 {
279 spi->CTL &= ~SPI_CTL_FIFOM_Msk;
280 }
281
287 uint32_t SPI_GetBusClock(SPI_T *spi)
288 {
289 uint32_t u32Div;
290 uint32_t u32ClkSrc;
291
292 if(spi == SPI0)
293 {
294 if((CLK->CLKSEL1 & CLK_CLKSEL1_SPI0SEL_Msk) == CLK_CLKSEL1_SPI0SEL_HCLK)
295 u32ClkSrc = CLK_GetHCLKFreq();
296 else
297 u32ClkSrc = CLK_GetPLLClockFreq();
298 }
299 if(spi == SPI1)
300 {
301 if((CLK->CLKSEL1 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_HCLK)
302 u32ClkSrc = CLK_GetHCLKFreq();
303 else
304 u32ClkSrc = CLK_GetPLLClockFreq();
305 }
306 if(spi == SPI2)
307 {
308 if((CLK->CLKSEL2 & CLK_CLKSEL1_SPI2SEL_Msk) == CLK_CLKSEL1_SPI2SEL_HCLK)
309 u32ClkSrc = CLK_GetHCLKFreq();
310 else
311 u32ClkSrc = CLK_GetPLLClockFreq();
312 }
313 else
314 {
315 if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI3SEL_Msk) == CLK_CLKSEL2_SPI3SEL_HCLK)
316 u32ClkSrc = CLK_GetHCLKFreq();
317 else
318 u32ClkSrc = CLK_GetPLLClockFreq();
319 }
320
321 u32Div = spi->CLKDIV & SPI_CLKDIV_DIVIDER_Msk;
322 return (u32ClkSrc / (u32Div + 1));
323 }
324
339 void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask)
340 {
341 if((u32Mask & SPI_IE_MASK) == SPI_IE_MASK)
342 spi->CTL |= SPI_CTL_UNITIEN_Msk;
343
344 if((u32Mask & SPI_SSTAIEN_MASK) == SPI_SSTAIEN_MASK)
345 spi->SSCTL |= SPI_SSCTL_SSTAIEN_Msk;
346
347 if((u32Mask & SPI_FIFO_TXTHIEN_MASK) == SPI_FIFO_TXTHIEN_MASK)
348 spi->FIFOCTL |= SPI_FIFOCTL_TXTHIEN_Msk;
349
350 if((u32Mask & SPI_FIFO_RXTHIEN_MASK) == SPI_FIFO_RXTHIEN_MASK)
351 spi->FIFOCTL |= SPI_FIFOCTL_RXTHIEN_Msk;
352
353 if((u32Mask & SPI_FIFO_RXOVIEN_MASK) == SPI_FIFO_RXOVIEN_MASK)
354 spi->FIFOCTL |= SPI_FIFOCTL_RXOVIEN_Msk;
355
356 if((u32Mask & SPI_FIFO_TIMEOUIEN_MASK) == SPI_FIFO_TIMEOUIEN_MASK)
357 spi->FIFOCTL |= SPI_FIFOCTL_RXTOIEN_Msk;
358 }
359
374 void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask)
375 {
376 if((u32Mask & SPI_IE_MASK) == SPI_IE_MASK)
377 spi->CTL &= ~SPI_CTL_UNITIEN_Msk;
378
379 if((u32Mask & SPI_SSTAIEN_MASK) == SPI_SSTAIEN_MASK)
380 spi->SSCTL &= ~SPI_SSCTL_SSTAIEN_Msk;
381
382 if((u32Mask & SPI_FIFO_TXTHIEN_MASK) == SPI_FIFO_TXTHIEN_MASK)
383 spi->FIFOCTL &= ~SPI_FIFOCTL_TXTHIEN_Msk;
384
385 if((u32Mask & SPI_FIFO_RXTHIEN_MASK) == SPI_FIFO_RXTHIEN_MASK)
386 spi->FIFOCTL &= ~SPI_FIFOCTL_RXTHIEN_Msk;
387
388 if((u32Mask & SPI_FIFO_RXOVIEN_MASK) == SPI_FIFO_RXOVIEN_MASK)
389 spi->FIFOCTL &= ~SPI_FIFOCTL_RXOVIEN_Msk;
390
391 if((u32Mask & SPI_FIFO_TIMEOUIEN_MASK) == SPI_FIFO_TIMEOUIEN_MASK)
392 spi->FIFOCTL &= ~SPI_FIFOCTL_RXTOIEN_Msk;
393 }
394
400 void SPI_EnableWakeup(SPI_T *spi)
401 {
402 spi->CTL |= SPI_CTL_WKCLKEN_Msk;
403 }
404
410 void SPI_DisableWakeup(SPI_T *spi)
411 {
412 spi->CTL &= ~SPI_CTL_WKCLKEN_Msk;
413 }
414 /* end of group NANO103_SPI_EXPORTED_FUNCTIONS */
416 /* end of group NANO103_SPI_Driver */
418 /* end of group NANO103_Device_Driver */
420
421 /*** (C) COPYRIGHT 2015 Nuvoton Technology Corp. ***/
SPI_SSCTL_SS_Msk
#define SPI_SSCTL_SS_Msk
Definition: Nano103.h:23519
CLK_CLKSEL2_SPI1SEL_HCLK
#define CLK_CLKSEL2_SPI1SEL_HCLK
Definition: clk.h:227
SPI_EnableWakeup
void SPI_EnableWakeup(SPI_T *spi)
Enable wake-up function.
Definition: spi.c:400
__HXT
#define __HXT
Definition: system_Nano103.h:26
SPI_CLKDIV_DIVIDER_Msk
#define SPI_CLKDIV_DIVIDER_Msk
Definition: Nano103.h:23516
SPI_FIFO_RXTHIEN_MASK
#define SPI_FIFO_RXTHIEN_MASK
Definition: spi.h:53
CLK_APBCLK_SPI0CKEN_Msk
#define CLK_APBCLK_SPI0CKEN_Msk
Definition: Nano103.h:5014
SPI_CTL_WKCLKEN_Msk
#define SPI_CTL_WKCLKEN_Msk
Definition: Nano103.h:23462
SPI_FIFOCTL_RXTH_Msk
#define SPI_FIFOCTL_RXTH_Msk
Definition: Nano103.h:23588
SPI_T::SSCTL
__IO uint32_t SSCTL
Definition: Nano103.h:23396
SPI_ClearRxFIFO
void SPI_ClearRxFIFO(SPI_T *spi)
Clear Rx FIFO buffer.
Definition: spi.c:104
CLK_CLKSEL2_SPI1SEL_Msk
#define CLK_CLKSEL2_SPI1SEL_Msk
Definition: Nano103.h:5122
SYS_IPRST2_SPI0RST_Msk
#define SYS_IPRST2_SPI0RST_Msk
Definition: Nano103.h:3305
SPI_Open
uint32_t SPI_Open(SPI_T *spi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock)
This function make SPI module be ready to transfer. By default, the SPI transfer sequence is MSB firs...
Definition: spi.c:47
CLK_CLKSEL2_SPI1SEL_HXT
#define CLK_CLKSEL2_SPI1SEL_HXT
Definition: clk.h:224
CLK_CLKSEL1_SPI0SEL_Msk
#define CLK_CLKSEL1_SPI0SEL_Msk
Definition: Nano103.h:5092
CLK_APBCLK_SPI3CKEN_Msk
#define CLK_APBCLK_SPI3CKEN_Msk
Definition: Nano103.h:5023
__HIRC16M
#define __HIRC16M
Definition: system_Nano103.h:29
SPI_SSCTL_SSACTPOL_Msk
#define SPI_SSCTL_SSACTPOL_Msk
Definition: Nano103.h:23522
SPI_SSTAIEN_MASK
#define SPI_SSTAIEN_MASK
Definition: spi.h:51
SPI_DisableFIFO
void SPI_DisableFIFO(SPI_T *spi)
Disable FIFO mode.
Definition: spi.c:277
SPI_FIFO_RXOVIEN_MASK
#define SPI_FIFO_RXOVIEN_MASK
Definition: spi.h:54
SYS_IPRST2_SPI3RST_Msk
#define SYS_IPRST2_SPI3RST_Msk
Definition: Nano103.h:3314
CLK_CLKSEL1_SPI0SEL_PLL
#define CLK_CLKSEL1_SPI0SEL_PLL
Definition: clk.h:177
SPI_SetBusClock
uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock)
Set the SPI bus clock. Only available in Master mode.
Definition: spi.c:151
SPI_FIFO_TXTHIEN_MASK
#define SPI_FIFO_TXTHIEN_MASK
Definition: spi.h:52
SPI_T
Definition: Nano103.h:22569
SPI_T::FIFOCTL
__IO uint32_t FIFOCTL
Definition: Nano103.h:23408
SPI_FIFOCTL_TXTHIEN_Msk
#define SPI_FIFOCTL_TXTHIEN_Msk
Definition: Nano103.h:23579
SPI_EnableAutoSS
void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel)
Enable the automatic slave select function. Only available in Master mode.
Definition: spi.c:140
CLK_CLKSEL2_SPI3SEL_HCLK
#define CLK_CLKSEL2_SPI3SEL_HCLK
Definition: clk.h:231
SPI1_BASE
#define SPI1_BASE
SPI1 register base address.
Definition: Nano103.h:24826
SYS_IPRST2_SPI2RST_Msk
#define SYS_IPRST2_SPI2RST_Msk
Definition: Nano103.h:3311
CLK_CLKSEL2_SPI3SEL_Msk
#define CLK_CLKSEL2_SPI3SEL_Msk
Definition: Nano103.h:5125
CLK_CLKSEL1_SPI2SEL_HCLK
#define CLK_CLKSEL1_SPI2SEL_HCLK
Definition: clk.h:183
CLK_APBCLK_SPI1CKEN_Msk
#define CLK_APBCLK_SPI1CKEN_Msk
Definition: Nano103.h:5017
CLK_CLKSEL2_SPI3SEL_PLL
#define CLK_CLKSEL2_SPI3SEL_PLL
Definition: clk.h:229
SPI_ClearTxFIFO
void SPI_ClearTxFIFO(SPI_T *spi)
Clear Tx FIFO buffer.
Definition: spi.c:114
SPI_DisableAutoSS
void SPI_DisableAutoSS(SPI_T *spi)
Disable the automatic slave select function.
Definition: spi.c:124
SPI_CTL_FIFOM_Msk
#define SPI_CTL_FIFOM_Msk
Definition: Nano103.h:23447
SPI_CTL_DWIDTH_Pos
#define SPI_CTL_DWIDTH_Pos
Definition: Nano103.h:23425
SPI_EnableInt
void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask)
Enable FIFO related interrupts specified by u32Mask parameter.
Definition: spi.c:339
SPI_DisableWakeup
void SPI_DisableWakeup(SPI_T *spi)
Disable wake-up function.
Definition: spi.c:410
CLK_GetPLLClockFreq
uint32_t CLK_GetPLLClockFreq(void)
This function get PLL frequency. The frequency unit is Hz.
Definition: clk.c:176
SPI_FIFOCTL_RXTH_Pos
#define SPI_FIFOCTL_RXTH_Pos
Definition: Nano103.h:23587
SPI_IE_MASK
#define SPI_IE_MASK
Definition: spi.h:50
CLK_CLKSEL1_SPI0SEL_HXT
#define CLK_CLKSEL1_SPI0SEL_HXT
Definition: clk.h:176
SPI_FIFOCTL_RXTHIEN_Msk
#define SPI_FIFOCTL_RXTHIEN_Msk
Definition: Nano103.h:23576
SPI_EnableFIFO
void SPI_EnableFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold)
Enable FIFO mode with user-specified Tx FIFO threshold and Rx FIFO threshold configurations.
Definition: spi.c:263
SPI_FIFOCTL_RXFBCLR_Msk
#define SPI_FIFOCTL_RXFBCLR_Msk
Definition: Nano103.h:23570
CLK_GetHCLKFreq
uint32_t CLK_GetHCLKFreq(void)
This function get HCLK frequency. The frequency unit is Hz.
Definition: clk.c:126
SPI3_BASE
#define SPI3_BASE
SPI3 register base address.
Definition: Nano103.h:24827
SPI0_BASE
#define SPI0_BASE
SPI0 register base address.
Definition: Nano103.h:24816
SPI_SSCTL_AUTOSS_Msk
#define SPI_SSCTL_AUTOSS_Msk
Definition: Nano103.h:23525
SPI_FIFOCTL_TXFBCLR_Msk
#define SPI_FIFOCTL_TXFBCLR_Msk
Definition: Nano103.h:23573
CLK_CLKSEL1_SPI0SEL_HCLK
#define CLK_CLKSEL1_SPI0SEL_HCLK
Definition: clk.h:179
CLK_PWRCTL_HIRC0EN_Msk
#define CLK_PWRCTL_HIRC0EN_Msk
Definition: Nano103.h:4936
CLK_CLKSEL2_SPI3SEL_HXT
#define CLK_CLKSEL2_SPI3SEL_HXT
Definition: clk.h:228
Nano103.h
NANO103 peripheral access layer header file. This file contains all the peripheral register's definit...
__HIRC36M
#define __HIRC36M
Definition: system_Nano103.h:31
CLK_CLKSEL0_HIRCSEL_Msk
#define CLK_CLKSEL0_HIRCSEL_Msk
Definition: Nano103.h:5071
SPI2_BASE
#define SPI2_BASE
SPI2 register base address.
Definition: Nano103.h:24817
SPI_T::CLKDIV
__IO uint32_t CLKDIV
Definition: Nano103.h:23395
SYS_IPRST2_SPI1RST_Msk
#define SYS_IPRST2_SPI1RST_Msk
Definition: Nano103.h:3308
SPI_FIFO_TIMEOUIEN_MASK
#define SPI_FIFO_TIMEOUIEN_MASK
Definition: spi.h:55
SPI_FIFOCTL_TXTH_Msk
#define SPI_FIFOCTL_TXTH_Msk
Definition: Nano103.h:23591
CLK_CLKSEL1_SPI2SEL_HXT
#define CLK_CLKSEL1_SPI2SEL_HXT
Definition: clk.h:180
SPI_FIFOCTL_RXOVIEN_Msk
#define SPI_FIFOCTL_RXOVIEN_Msk
Definition: Nano103.h:23582
SPI2
#define SPI2
Pointer to SPI2 register structure.
Definition: Nano103.h:24872
SPI_GetBusClock
uint32_t SPI_GetBusClock(SPI_T *spi)
Get the actual frequency of SPI bus clock. Only available in Master mode.
Definition: spi.c:287
SPI_Close
void SPI_Close(SPI_T *spi)
Reset SPI module and disable SPI peripheral clock.
Definition: spi.c:66
SPI_SSCTL_SSTAIEN_Msk
#define SPI_SSCTL_SSTAIEN_Msk
Definition: Nano103.h:23540
__HIRC12M
#define __HIRC12M
Definition: system_Nano103.h:28
CLK_CLKSEL1_SPI2SEL_PLL
#define CLK_CLKSEL1_SPI2SEL_PLL
Definition: clk.h:181
SPI_CTL_UNITIEN_Msk
#define SPI_CTL_UNITIEN_Msk
Definition: Nano103.h:23438
SPI_FIFOCTL_RXTOIEN_Msk
#define SPI_FIFOCTL_RXTOIEN_Msk
Definition: Nano103.h:23585
CLK_APBCLK_SPI2CKEN_Msk
#define CLK_APBCLK_SPI2CKEN_Msk
Definition: Nano103.h:5020
CLK_CLKSEL1_SPI2SEL_Msk
#define CLK_CLKSEL1_SPI2SEL_Msk
Definition: Nano103.h:5095
CLK
#define CLK
Pointer to CLK register structure.
Definition: Nano103.h:24884
SPI0
#define SPI0
Pointer to SPI0 register structure.
Definition: Nano103.h:24870
SYS
#define SYS
Pointer to SYS register structure.
Definition: Nano103.h:24883
SPI_T::CTL
__IO uint32_t CTL
Definition: Nano103.h:23393
SPI1
#define SPI1
Pointer to SPI1 register structure.
Definition: Nano103.h:24871
SPI_FIFOCTL_TXTH_Pos
#define SPI_FIFOCTL_TXTH_Pos
Definition: Nano103.h:23590
SPI_DisableInt
void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask)
Disable FIFO related interrupts specified by u32Mask parameter.
Definition: spi.c:374
CLK_CLKSEL2_SPI1SEL_PLL
#define CLK_CLKSEL2_SPI1SEL_PLL
Definition: clk.h:225