| Nano103 BSP V3.01.002 The Board Support Package for Nano103 Series

Data Fields
UART_T Struct Reference

`#include <Nano103.h>`

## Data Fields
__IO uint32_t | DAT
__IO uint32_t | CTRL
__IO uint32_t | LINE
__IO uint32_t | INTEN
__IO uint32_t | INTSTS
__IO uint32_t | TRSR
__IO uint32_t | FIFOSTS
__IO uint32_t | MODEM
__IO uint32_t | TOUT
__IO uint32_t | BAUD
__IO uint32_t | IRDA
__IO uint32_t | ALTCTL
__IO uint32_t | FUNCSEL
__IO uint32_t | BRCOMPAT
__IO uint32_t | WKUPEN
__IO uint32_t | WKUPSTS

## Detailed Description

    @addtogroup UART Universal Asynchronous Receiver/Transmitter Controller(UART)
    Memory Mapped Structure for UART Controller

Definition at line 18880 of file Nano103.h.

## Field Documentation

## ◆ ALTCTL

UART_T::ALTCTL

[0x0034] UART Alternate Control State Register.

ALTCTL

Offset: 0x34 UART Alternate Control State Register.

Bits | Field | Descriptions
[2:0] | BRKFL | LIN TX Break Field Count The field contains 3-bit LIN TX break field count. Note: The break field length is BRKFL + 8.
[5:4] | LINHSEL | LIN Header Selection 00 = The LIN header includes break field. 01 = The LIN header includes break field + sync field. 10 = The LIN header includes break field + sync field + PID field. 11 = Reserved.
[6] | LINRXEN | LIN RX Enable Control When LIN RX mode enabled and received a break field or sync field or PID field (Select by LIN_Header_SEL), the controller will generator a interrupt to CPU (LININT) 0 = LIN RX mode Disabled. 1 = LIN RX mode Enabled.
[7] | LINTXEN | LIN TX Header Trigger Enable Bit The LIN TX header can be break field or break and sync field or break, sync and frame ID field, it is depend on setting LINHSEL (UART_ALT_CSR[5:4]). 0 = Send LIN TX header Disabled. 1 = Send LIN TX header Enabled. Note1: This bit will be cleared automatically and generate a interrupt to CPU (LININT). Note2: When transmitter header field (it may be break or break + sync or break + sync + frame ID selected by LINHSEL (UART_ALT_CSR[5:4]) field) transfer operation finished, this bit will be cleared automatically. Note3: If user wants to receive transmit data, it recommended to enable LINRXEN bit.
[8] | BITERREN | Bit Error Detect Enable Bit 0 = Bit error detection Disabled. 1 = Bit error detection Enabled. Note: In LIN function mode, when bit error occurs, the BITEF (UART_TRSR[5]) flag will be asserted If the LINIEN (UART_IER[8]) = 1, an interrupt will be generated .
[16] | RS485NMM | RS-485 Normal Multi-drop Operation Mode (NMM) 0 = RS-485 Normal Multi-drop Operation mode (NMM) Disabled. 1 = RS-485 Normal Multi-drop Operation mode (NMM) Enabled. Note: It cannot be active with RS-485_AAD operation mode.
[17] | RS485AAD | RS-485 Auto Address Detection Operation Mode (AAD) 0 = RS-485 Auto Address Detection Operation mode (AAD) Disabled. 1 = RS-485 Auto Address Detection Operation mode (AAD) Enabled. Note: It cannot be active with RS485NMM operation mode.
[18] | RS485AUD | RS-485 Auto Direction Function (AUD) 0 = RS-485 Auto Direction Operation function (AUD) Disabled. 1 = RS-485 Auto Direction Operation function (AUD) Enabled. Note: It can be active with RS485AAD or RS485NMM operation mode.
[19] | ADDRDEN | RS-485 Address Detection Enable Bit This bit is used to enable RS-485 Address Detection mode. 0 = Address detection mode Disabled. 1 = Address detection mode Enabled. Note: This bit is used for RS-485 any operation mode.
[31:24] | ADRMPID | Address / PID Match Value Register When in the RS-485 Function Mode, this field contains the RS-485 address match values. When in the LIN Function mode, this field contains the LIN protected identifier field, software fills ID0~ID5 (PID [5:0]), hardware will calculate P0 and P1. Note: This field is used for RS-485 auto address detection mode or used for LIN protected identifier field (PID).

Definition at line 20117 of file Nano103.h.

## ◆ BAUD

UART_T::BAUD

[0x0024] UART Baud Rate Divisor Register.

BAUD

Offset: 0x24 UART Baud Rate Divisor Register.

Bits | Field | Descriptions
[15:0] | BRD | Baud Rate Divider The field indicates the baud rate divider This filed is used in baud rate calculation The detail description is shown in UART Controller Baud Rate Generation.
[31] | DIV16EN | Divider 16 Enable Control The BRD = Baud Rate Divider, and the baud rate equation is Baud Rate = UART_CLK/ [M * (BRD + 1)]; The default value of M is 16. 0 = The equation of baud rate is UART_CLK / [ (BRD+1)]. 1 = The equation of baud rate is UART_CLK / [16 * (BRD+1)]. Note: In IrDA mode, this bit must clear to 0.

Definition at line 20112 of file Nano103.h.

## ◆ BRCOMPAT

UART_T::BRCOMPAT

[0x003c] UART Baud Rate Compensation Register.

BRCOMPAT

Offset: 0x3C UART Baud Rate Compensation Register.

Bits | Field | Descriptions
[8:0] | BRCOMPAT | Baud Rate Compensation Patten These 9 bits are used to define the relative bit is compensated or not BRCOMPAT[7:0] is used to define the compensation of D[7:0] and BRCOMPAT{[8] is used to define the parity bit.
[31] | BRCOMPDEC | Baud Rate Compensation Decrease 0 = Positive (increase one module clock) compensation for each compensated bit. 1 = Negative (decrease one module clock) compensation for each compensated bit.

Definition at line 20119 of file Nano103.h.

## ◆ CTRL

UART_T::CTRL

[0x0004] UART Control Register.

CTRL

Offset: 0x04 UART Control Register.

Bits | Field | Descriptions
[0] | RXRST | RX Field Software Reset When RXRST (UART_CTL[0]) is set, all the byte in the receiver FIFO and RX internal state machine are cleared. 0 = No effect. 1 = Reset the RX internal state machine and pointers. Note: This bit will automatically clear at least 3 UART peripheral clock cycles.
[1] | TXRST | TX Field Software Reset When TXRST (UART_CTL[1]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared. 0 = No effect. 1 = Reset the TX internal state machine and pointers. Note: This bit will automatically clear at least 3 UART peripheral clock cycles
[2] | RXOFF | Receiver Disable Bit 0 = Receiver Enabled. 1 = Receiver Disabled. Note1: In RS-485 NMM mode, user can set this bit to receive data before detecting address byte. Note2: In RS-485 AAD mode, this bit will be setting to 1 automatically. Note3: In RS-485 AUD mode and LIN break + sync +PID header mode, hardware will control data automatically, so don't fill any value to this bit.
[3] | TXOFF | Transfer Disable Bit 0 = Transfer Enabled. 1 = Transfer Disabled.
[4] | ATORTSEN | nRTS Auto-flow Control Enable Bit 0 = nRTS auto-flow control Disabled. 1 = nRTS auto-flow control Enabled. Note: When nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_TLCTL[13:12]), the UART will de-assert nRTS signal.
[5] | ATOCTSEN | nCTS Auto-flow Control Enable Bit 0 = nCTS auto-flow control Disabled. 1 = nCTS auto-flow control Enabled. Note: When nCTS auto-flow is enabled, the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted).
[6] | RXDMAEN | RX DMA Enable Bit This bit can enable or disable RX DMA service. 0 = RX DMA Disabled. 1 = RX DMA Enabled.
[7] | TXDMAEN | TX DMA Enable Bit This bit can enable or disable TX DMA service. 0 = TX DMA Disabled. 1 = TX DMA Enabled.
[8] | FTOEN | Frame Time Out Enable Bit This bit is used to enable the timer counter even the FIFO is still empty. 0 = Frame time out Disabled. 1 = Frame time out Enabled.
[12] | ABRDEN | Auto-baud Rate Detect Enable Bit 0 = Auto-baud rate detect function Disabled. 1 = Auto-baud rate detect function Enabled. Note: When the auto-baud rate detect operation finishes, hardware will clear this bit and the associated interrupt (ABRIF) will be generated (If ABRIEN (UART_IER [7]) be enabled).
[14:13] | ABRDBITS | Auto-baud Rate Detect Bit Length 00 = 1-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x01. 01 = 2-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x02. 10 = 4-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x08. 11 = 8-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x80. Note: The calculation of bit number includes the START bit.

Definition at line 20104 of file Nano103.h.

## ◆ DAT

UART_T::DAT

[0x0000] UART Receive/Transmit Buffer Register

DAT

Offset: 0x00 UART Receive/Transmit Buffer Register.

Bits | Field | Descriptions
[7:0] | DAT | Receive /Transmit Buffer Write Operation: By writing one byte to this register, the data byte will be stored in transmitter FIFO. The UART Controller will send out the data stored in transmitter FIFO top location through the UART_DAT. Read Operation: By reading this register, the UART will return an 8-bit data received from receiving FIFO.

Definition at line 20103 of file Nano103.h.

## ◆ FIFOSTS

UART_T::FIFOSTS

[0x0018] UART FIFO Status Register.

FIFOSTS

Offset: 0x18 UART FIFO Status Register.

Bits | Field | Descriptions
[0] | RXOVIF | RX Overflow Error Status Flag (Read Only) This bit is set when RX FIFO overflow If the number of bytes of received data is greater than RX_FIFO (UART_RBR) size, this bit will be set. 0 = RX FIFO is not overflow. 1 = RX FIFO is overflow. Note: This bit is read only, but can be cleared by writing 1 to it.
[1] | RXEMPTY | Receiver FIFO Empty (Read Only) This bit initiate RX FIFO empty or not. 0 = RX FIFO is not empty. 1 = RX FIFO is empty. Note: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high It will be cleared when UART receives any new data.
[2] | RXFULL | Receiver FIFO Full (Read Only) This bit initiates RX FIFO full or not. 0 = RX FIFO is not full. 1 = RX FIFO is full. Note: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise is cleared by hardware.
[4] | PEF | Parity Error State Status Flag (Read Only) This bit is set to logic 1 whenever the received character does not have a valid parity bit. 0 = No parity error is generated. 1 = Parity error is generated. Note: This bit is read only, but can be cleared by writing '1' to it.
[5] | FEF | Framing Error Flag (Read Only) This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as logic 0). 0 = No framing error is generated. 1 = Framing error is generated. Note: This bit is read only, but can be cleared by writing '1' to it.
[6] | BIF | Break Interrupt Flag( Read Only) This bit is set to logic 1 whenever the received data input (RX) is held in the spacing state (logic 0) for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits). 0 = No Break interrupt is generated. 1 = Break interrupt is generated. Note: This bit is read only, but can be cleared by writing '1' to it.
[8] | TXOVIF | TX Overflow Error Interrupt Status Flag (Read Only) If TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1. 0 = TX FIFO did not overflow. 1 = TX FIFO overflowed. Note: This bit is read only, but can be cleared by writing 1 to it.
[9] | TXEMPTY | Transmitter FIFO Empty (Read Only) This bit indicates TX FIFO empty or not. 0 = TX FIFO is not empty. 1 = TX FIFO is empty. Note: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high It will be cleared when writing data into DAT (TX FIFO not empty).
[10] | TXFULL | Transmitter FIFO Full (Read Only) This bit indicates TX FIFO full or not. 0 = TX FIFO is not full. 1 = TX FIFO is full. Note: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise is cleared by hardware.
[11] | TXENDF | Transmitter Empty Flag (Read Only) This bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted. 0 = TX FIFO is not empty or the STOP bit of the last byte has been not transmitted. 1 = TX FIFO is empty and the STOP bit of the last byte has been transmitted. Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
[20:16] | RXPTR | RX FIFO Pointer (Read Only) This field indicates the RX FIFO Buffer Pointer When UART receives one byte from external device, RXPTR increases one When one byte of RX FIFO is read by CPU, RXPTR decreases one. The Maximum value shown in RXPTR is 15 When the using level of RX FIFO Buffer equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0 As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15
[28:24] | TXPTR | TX-fIFO Pointer (Read Only) This field indicates the TX FIFO Buffer Pointer When CPU writes one byte into UART_DAT, TXPTR increases one When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one. The Maximum value shown in TXPTR is 15 When the using level of TX FIFO Buffer equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0 As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15

Definition at line 20109 of file Nano103.h.

## ◆ FUNCSEL

UART_T::FUNCSEL

[0x0038] UART Function Select Register.

FUNCSEL

Offset: 0x38 UART Function Select Register.

Bits | Field | Descriptions
[1:0] | FUNCSEL | Function Selection 00 = UART function mode. 01 = LIN function mode. 10 = IrDA function mode. 11 = RS-485 function mode.

Definition at line 20118 of file Nano103.h.

## ◆ INTEN

UART_T::INTEN

[0x000c] UART Interrupt Enable Register.

INTEN

Offset: 0x0C UART Interrupt Enable Register.

Bits | Field | Descriptions
[0] | RDAIEN | Receive Data Available Interrupt Enable Bit 0 = Receive data available interrupt Disabled. 1 = Receive data available interrupt Enabled.
[1] | THREIEN | Transmit Holding Register Empty Interrupt Enable Bit 0 = Transmit holding register empty interrupt Disabled. 1 = Transmit holding register empty interrupt Enabled.
[2] | RLSIEN | Receive Line Status Interrupt Enable Bit 0 = Receive Line Status interrupt Disabled. 1 = Receive Line Status interrupt Enabled.
[3] | MODEMIEN | Modem Status Interrupt Enable Bit 0 = Modem status interrupt Disabled. 1 = Modem status interrupt Enabled.
[4] | RXTOIEN | RX Time-out Interrupt Enable Bit 0 = RX time-out interrupt Disabled. 1 = RX time-out interrupt Enabled.
[5] | BUFERRIEN | Buffer Error Interrupt Enable Bit 0 = Buffer error interrupt Disabled. 1 = Buffer error interrupt Enabled.
[6] | WKUPIEN | Wake-up Interrupt Enable Bit 0 = Wake-up system function Disabled. 1 = Wake-up system function Enabled, when the system is in Power-down mode, one of the wake-up event will wake-up system from Power-down mode. Note: Hardware will clear one of the wake-up status bits in UART_WKUPSTS when the wake-up operation finishes and system clock work stable
[7] | ABRIEN | Auto-baud Rate Interrupt Enable Bit 0 = Auto-baud rate interrupt Disabled. 1 = Auto-baud rate interrupt Enabled.
[8] | LINIEN | LIN Bus Interrupt Enable Bit 0 = LIN bus interrupt Disabled. 1 = LIN bus interrupt Enabled. Note: This bit is used for LIN function mode.
[9] | TXENDIEN | Transmitter Empty Interrupt Enable Bit 0 = Transmit Empty interrupt Disabled. 1 = Transmit Empty interrupt Enabled. Note: If the bit is enabled, there is interrupt event when the TXENDF (UART_FSR[11]) is activated.

Definition at line 20106 of file Nano103.h.

## ◆ INTSTS

UART_T::INTSTS

[0x0010] UART Interrupt Status Register.

INTSTS

Offset: 0x10 UART Interrupt Status Register.

Bits | Field | Descriptions
[0] | RDAIF | Receive Data Available Interrupt Flag (Read Only) When the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_ISR[0]) will be set If RDAIEN (UART_IER [0]) is enabled, the RDA interrupt will be generated. 0 = No RDA interrupt flag is generated. 1 = RDA interrupt flag is generated. Note: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UART_TLCTL[9:8])
[1] | THREIF | Transmit Holding Register Empty Interrupt Flag (Read Only) This bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register If THREIEN (UART_IER[1]) is enabled, the THRE interrupt will be generated. 0 = No THRE interrupt flag is generated. 1 = THRE interrupt flag is generated. Note: This bit is read only and it will be cleared when writing data into UART_DAT (TX FIFO not empty)
[2] | RLSIF | Receive Line Interrupt Flag (Read Only) This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(UART_FSR[6]), FEF(UART_FSR[5]) and PEF(UART_FSR[4]), is set) If RLSIEN (UART_IER [2]) is enabled, the RLS interrupt will be generated. 0 = No RLS interrupt flag is generated. 1 = RLS interrupt flag is generated. Note1: In RS-485 function mode, this field is set include receiver detect and received address byte character (bit9 = '1') bit" At the same time, the bit of ADDRDETF (UART_TRSR[0]) is also set. Note2: This bit is read only and reset to 0 when all bits of BIF (UART_FSR[6]), FEF(UART_FSR[5]) and PEF(UART_FSR[4]) are cleared. Note3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FSR[6]) , FEF(UART_FSR[5]) and PEF(UART_FSR[4]) and ADDRDETF (UART_TRSR[0]) are cleared.
[3] | MODEMIF | MODEM Interrupt Flag (Read Only) Channel This bit is set when the nCTS pin has state change (CTSDETF (UART_MCSR[18]) = 1) If MODEMIEN (UART_IER [3]) is enabled, the Modem interrupt will be generated. 0 = No Modem interrupt flag is generated. 1 = Modem interrupt flag is generated. Note: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MCSR[18]).
[4] | RXTOIF | Rime-out Interrupt Flag (Read Only) This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC If RXTOIEN (UART_IER [4]) is enabled, the Tout interrupt will be generated. 0 = No Time-out interrupt flag is generated. 1 = Time-out interrupt flag is generated. Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it
[5] | BUFERRIF | Buffer Error Interrupt Flag (Read Only) This bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FSR[8]) or RXOVIF (UART_FSR[0]) is set) When BUFERRIF (UART_ISR[5])is set, the transfer is not correct If BFERRIEN (UART_IER [5]) is enabled, the buffer error interrupt will be generated. 0 = No buffer error interrupt flag is generated. 1 = Buffer error interrupt flag is generated. Note: This bit is read only This bit is cleared if both of RXOVIF(UART_FSR[0]) and TXOVIF(UART_FSR[8]) are cleared to 0 by writing 1 to RXOVIF(UART_FSR[0]) and TXOVIF(UART_FSR[8]).
[6] | WKUPIF | Wake-up Interrupt Flag (Read Only) This bit is set if chip wake-up from power-down state by one of UART controller wake-up event. 0 = Chip stays in power-down state. 1 = Chip wake-up from power-down state by one of UART controller wake-up event. Note1: If WKDATEN (UART_IER[6]) is enabled, the wake-up interrupt is generated. Note2: This bit is read only, but can be cleared by writing '1' to one of UART_WKUPSTS[4:0] (THRTOWKSTS or THRWKSTS or CTSWKSTS or DATWKSTS or ADRWKSTS).
[7] | ABRIF | Auto-baud Rate Interrupt Status Flag (Read Only) This bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN (UART_IER[7]) is set then the auto-baud rate interrupt will be generated. 0 = No Auto-Baud Rate interrupt is generated. 1 = Auto-Baud Rate interrupt is generated. Note1: This bit is read only, but can be cleared by writing 1 to ABRDTOIF (UART_TRSR[2]) or ABRDIF (UART_TRSR[1]). Note2: This bit is cleared when both the ABRDTOIF and ABRDIF are cleared.
[8] | LINIF | LIN Interrupt Status Flag (Read Only) This bit is set when the LIN TX header transmitted, RX header received or the SIN does not equal SOUT and if LINIEN(UART_IER[8]) is set then the LIN interrupt will be generated. 0 = No LIN interrupt is generated. 1 = LIN interrupt is generated. Note1: This bit is read only, but can be cleared by it by writing 1 to BITEF (UART_TRSR[5]), LINTXIF (UART_TRSR[3]) or LINRXIF (UART_TRSR[4]). Note2: This bit is cleared when both the BITEF, LINTXIF and LINRXIF are cleared.

Definition at line 20107 of file Nano103.h.

## ◆ IRDA

UART_T::IRDA

[0x0030] UART IrDA Control Register.

IRDA

Offset: 0x30 UART IrDA Control Register.

Bits | Field | Descriptions
[1] | TXEN | IrDA Receiver/Transmitter Selection Enable Bit 0 = IrDA Transmitter Disabled and Receiver Enabled. (Default) 1 = IrDA Transmitter Enabled and Receiver Disabled.
[5] | TXINV | IrDA Inverse Transmitting Output Signal 0 = None inverse transmitting signal. (Default) 1 = Inverse transmitting output signal.
[6] | RXINV | IrDA Inverse Receive Input Signal 0 = None inverse receiving input signal. 1 = Inverse receiving input signal. (Default)

Definition at line 20116 of file Nano103.h.

## ◆ LINE

UART_T::LINE

[0x0008] UART Transfer Line Control Register.

LINE

Offset: 0x08 UART Transfer Line Control Register.

Bits | Field | Descriptions
[1:0] | WLS | Word Length Selection This field sets UART word length. 00 = 5 bits. 01 = 6 bits. 10 = 7 bits. 11 = 8 bits.
[2] | NSB | Number of STOP Bit 0 = One STOP bit is generated in the transmitted data. 1 = When select 5-bit word length, 1.5 STOP bit is generated in the transmitted data When select 6-, 7- and 8-bit word length, 2 STOP bit is generated in the transmitted data.
[3] | PBE | Parity Bit Enable Bit 0 = No parity bit generated Disabled. 1 = Parity bit generated Enabled. Note: Parity bit is generated on each outgoing character and is checked on each incoming data.
[4] | EPE | Even Parity Enable Bit 0 = Odd number of logic 1's is transmitted and checked in each word. 1 = Even number of logic 1's is transmitted and checked in each word. Note: This bit has effect only when PBE (UART_TLCTL[3]) is set.
[5] | SPE | Stick Parity Enable Bit 0 = Stick parity Disabled. 1 = Stick parity Enabled. Note: If PBE (UART_TLCTL[3]) and EPE (UART_TLCTL[4]) are logic 1, the parity bit is transmitted and checked as logic 0 If PBE (UART_TLCTL[3]) is 1 and EPE (UART_TLCTL[4]) is 0 then the parity bit is transmitted and checked as 1.
[6] | BCB | Break Control Bit 0 = Break Control Disabled. 1 = Break Control Enabled. Note: When this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0) This bit acts only on TX line and has no effect on the transmitter logic.
[9:8] | RFITL | RX FIFO Interrupt Trigger Level When the number of bytes in the receive FIFO equals the RFITL, the RDAIF will be set (if RDAIEN (UART_IER [0]) enabled, and an interrupt will be generated). 0000 = RX FIFO Interrupt Trigger Level is 1 byte. 0001 = RX FIFO Interrupt Trigger Level is 4 bytes. 0010 = RX FIFO Interrupt Trigger Level is 8 bytes. 0011 = RX FIFO Interrupt Trigger Level is 14 bytes. Note: When operating in IrDA mode or RS-485 mode, the RFITL must be set to 0.
[13:12] | RTSTRGLV | nRTS Trigger Level for Auto-flow Control Use 00 = nRTS Trigger Level is 1 byte. 01 = nRTS Trigger Level is 4 bytes. 10 = nRTS Trigger Level is 8 bytes. 11 = nRTS Trigger Level is 14 bytes. Note: This field is used for auto nRTS flow control.

Definition at line 20105 of file Nano103.h.

## ◆ MODEM

UART_T::MODEM

[0x001c] UART Modem Control Status Register.

MODEM

Offset: 0x1C UART Modem Control Status Register.

Bits | Field | Descriptions
[0] | RTSACTLV | nRTS Pin Active Level This bit defines the active level state of nRTS pin output. 0 =n RTS pin output is high level active. 1 = nRTS pin output is low level active. (Default)
[1] | RTSSTS | nRTS Pin State (Read Only) This bit mirror from nRTS pin output of voltage logic status. 0 = nRTS pin output is low level voltage logic state. 1 = nRTS pin output is high level voltage logic state.
[16] | CTSACTLV | nCTS Trigger Level This bit defines the active level state of nCTS pin input. 0 = nCTS pin input is high level active. 1 = nCTS pin input is low level active. (Default)
[17] | CTSSTS | nCTS Pin Status (Read Only) This bit mirror from nCTS pin input of voltage logic status. 0 = nCTS pin input is low level voltage logic state. 1 = nCTS pin input is high level voltage logic state. Note: This bit echoes when UART Controller peripheral clock is enabled, and nCTS multi-function port is selected.
[18] | CTSDETF | Detect nCTS State Change Flag (Read Only) This bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_IER[3]). 0 = nCTS input has not change state. 1 = nCTS input has change state. Note: This bit is read only, but it can be cleared by writing 1 to it.

Definition at line 20110 of file Nano103.h.

## ◆ TOUT

UART_T::TOUT

[0x0020] UART Time-Out Control Register.

TOUT

Offset: 0x20 UART Time-Out Control Register.

Bits | Field | Descriptions
[8:0] | TOIC | Time-out Comparator The time-out counter resets and starts counting (the counting clock = baud rate) whenever the RX FIFO receives a new data word Once the content of time-out counter is equal to that of time-out interrupt comparator (TOIC (UART_TMCTL[8:0])), a receiver time-out interrupt (RXTOIF(UART_ISR[4])) is generated if RXTOIEN (UART_IER [4]) enabled A new incoming data word or RX FIFO empty will clear RXTOIF(UART_ISR[4]) In order to avoid receiver time-out interrupt generation immediately during one character is being received, TOIC value should be set between 40 and 255 So, for example, if TOIC is set with 40, the time-out interrupt is generated after four characters are not received when 1 stop bit and no parity check is set for UART transfer. Note1: Fill all 0 to this field indicates to disable this function. Note2: The real time-out value is TOIC + 1. Note3: The counting clock is baud rate clock. Note4: The UART data format is start bit + 8 data bits + parity bit + stop bit, although software can configure this field by any value but it is recommend to fill this field great than 0xA.
[23:16] | DLY | TX Delay Time Value This field is used to programming the transfer delay time between the last stop bit and next start bit The unit is bit time. Note1: Fill all 0 to this field indicates to disable this function. Note2: The real delay value is DLY. Note3: The counting clock is baud rate clock.

Definition at line 20111 of file Nano103.h.

## ◆ TRSR

UART_T::TRSR

[0x0014] UART Transfer Status Register.

TRSR

Offset: 0x14 UART Transfer Status Register.

Bits | Field | Descriptions
[0] | ADDRDETF | RS-485 Address Byte Detection Status Flag (Read Only) 0 = Receiver detects a data that is not an address bit (bit 9 ='0'). 1 = Receiver detects a data that is an address bit (bit 9 ='1'). Note1: This field is used for RS-485 function mode and ADDRDEN (UART_ALT_CSR[19]) is set to 1 to enable Address detection mode . Note2: This bit is read only, but can be cleared by writing '1' to it.
[1] | ABRDIF | Auto-baud Rate Interrupt (Read Only) This bit is set to logic 1 when auto-baud rate detect function finished. 0 = No Auto- Baud Rate interrupt is generated. 1= Auto-Baud Rate interrupt is generated. Note: This bit is read only, but can be cleared by writing 1 to it.
[2] | ABRDTOIF | Auto-baud Rate Time-out Interrupt (Read Only) 0 = Auto-baud rate counter is underflow. 1 = Auto-baud rate counter is overflow. Note1: This bit is set to logic 1 in Auto-baud Rate Detect mode and the baud rate counter is overflow. Note2: This bit is read only, but can be cleared by writing 1 to it.
[3] | LINTXIF | LIN TX Interrupt Flag (Read Only) This bit is set to logic 1 when LIN transmitted header field The header may be break field or break field + sync field or break field + sync field + PID field, it can be choose by setting LINHSEL (UART_ALT_CSR[5:4]) register. 0 = No LIN Transmit interrupt is generated. 1 = LIN Transmit interrupt is generated. Note: This bit is read only, but can be cleared by writing 1 to it.
[4] | LINRXIF | LIN RX Interrupt Flag (Read Only) This bit is set to logic 1 when received LIN header field The header may be break field or break field + sync field or break field + sync field + PID field, and it can be choose by setting LINHSEL (UART_ALT_CSR[5:4]) register. 0 = No LIN Rx interrupt is generated. 1 = LIN Rx interrupt is generated. Note: This bit is read only, but can be cleared by writing 1 to it.
[5] | BITEF | Bit Error Detect Status Flag (Read Only) At TX transfer state, hardware will monitoring the bus state, if the input pin (SIN) state is not equal to the output pin (SOUT) state, BITEF will be set. When occur bit error, hardware will generate an interrupt to CPU (LININT). 0 = No Bit error interrupt is generated. 1 = Bit error interrupt is generated. Note1: This bit is read only, but it can be cleared by writing 1 to it. Note2: This bit is only valid when enabling the bit error detection function (BITERREN (UART_ALT_CSR[8]) = 1).
[7] | RXBUSY | Receive Busy Status (Read Only) 0 = The receiver machine stays in idle state. 1 = The receiver machine stays in no Idle state. Note: The user can use this to check the busy status in receiver mode If the user want to enter the power down, this bit shall be confirm in Idle state and there is 2 UART clock latency for receiver pin.
[8] | SLVSYNCF | LIN RX SYNC Error Flag (Read Only) This bit is set to logic 1 when LIN received incorrect SYNC field. User can choose the header by setting LINHSEL (UART_ALT_CSR[5:4]) register. 0 = No LIN Rx sync error is generated. 1 = LIN Rx sync error is generated. Note: This bit is read only, but can be cleared by writing 1 to LINRXIF.

Definition at line 20108 of file Nano103.h.

## ◆ WKUPEN

UART_T::WKUPEN

[0x0040] UART Wake-up Enable Register.

WKUPEN

Offset: 0x40 UART Wake-up Enable Register.

Bits | Field | Descriptions
[0] | WKCTSEN | nCTS Wake-up Enable Bit When the system is in power-down mode, an external nCTS change will wake-up system from power-down mode. 0 = nCTS wake-up function Disabled. 1 = nCTS wake-up function Enabled.
[1] | WKDATEN | Incoming Data Wake-up Enable Bit 0 = Incoming data wake-up function Disabled. 1 = Incoming data wake-up function Enabled when the system is in power-down mode, incoming data will wake-up system from power-down mode. Note: Hardware will clear this bit when the incoming data wake-up operation finishes and system clock work stable
[2] | WKTHREN | FIFO Threshold Reach Wake-up Enable Bit 0 = Received FIFO threshold reach wake-up function Disabled. 1 = Received FIFO threshold reach wake-up function Enabled when the system is in power-down mode. Note: It is suggest the function is enabled in UART mode and the UART clock is selected in 32K.
[3] | WKTHRTOEN | FIFO Threshold Reach Time Out Wake-up Enable Bit 0 = Received FIFO threshold no reach and time out wake-up function Disabled. 1 = Received FIFO threshold no reach and time out wake-up function Enabled when the system is in power-down mode. Note: It is suggest the function is enabled when the WKTHREN (UART_WKUPEN[2]) is set to 1.
[4] | WKADRMEN | RS-485 Address Match Wake-up Enable Bit 0 = RS-485 ADD mode address match wake-up function Disabled. 1 = RS-485 AAD mode address match wake-up function Enabled when the system is in power-down mode.

Definition at line 20120 of file Nano103.h.

## ◆ WKUPSTS

UART_T::WKUPSTS

[0x0044] UART Wake-up Status Register.

WKUPSTS

Offset: 0x44 UART Wake-up Status Register.

Bits | Field | Descriptions
[0] | CTSWKSTS | nCTS Wake-up Flag (Read Only) 0 = Chip stays in power-down state. 1 = Chip wake-up from power-down state by nCTS wake-up. Note1: If WKCTSEN (UART_ WKUPEN [0])is enabled, the wake-up function is generated. Note2: This bit is read only, but can be cleared by writing '1' to it.
[1] | DATWKSTS | Data Wake-up Flag (Read Only) This bit is set if chip wake-up from power-down state by data wake-up. 0 = Chip stays in power-down state. 1 = Chip wake-up from power-down state by data wake-up. Note1: If WKDATEN (UART_ WKUPEN [1]) is enabled, the wake-up function is generated. Note2: This bit is read only, but can be cleared by writing '1' to it
[2] | THRWKSTS | Threshold Wake-up Flag (Read Only) 0 = Chip stays in power-down state. 1 = Chip wake-up from power-down state by FIFO threshold wake-up. Note1: If WKTHREN (UART_ WKUPEN [2])is enabled, the wake-up function is generated. Note2: This bit is read only, but can be cleared by writing '1' to it.
[3] | THRTOWKSTS | Threshold Wake-up Time Out Flag (Read Only) 0 = Chip stays in power-down state. 1 = Chip wake-up from power-down state by FIFO threshold time out wake-up. Note1: If WKTHRTOEN (UART_ WKUPEN [3])is enabled, the wake-up function is generated. Note2: This bit is read only, but can be cleared by writing '1' to it.
[4] | ADRWKSTS | RS-485 Address Byte Detection Wake-up Flag (Read Only) 0 = Chip stays in power-down state. 1 = Chip wake-up from power-down state by Receiver detects a data that is an address bit (bit 9 ='1'). Note1: If WKADRMEN (UART_WKUPEN[4])is enabled, the wake-up function is generated. Note2: This field is used for RS-485 function mode and ADDRDEN (UART_ALT_CSR[19]) is set to 1 to enable Address detection mode . Note2: This bit is read only, but can be cleared by writing '1' to it.

Definition at line 20121 of file Nano103.h.

The documentation for this struct was generated from the following file:

- C:/Users/yachen/workzone/bsp/nano103bsp/Library/Device/Nuvoton/Nano103/Include/Nano103.h