Nano103 BSP  V3.01.002
The Board Support Package for Nano103 Series
Data Fields
GP_DB_T Struct Reference

#include <Nano103.h>

Data Fields

__IO uint32_t DBCTL
 

Detailed Description

Definition at line 11778 of file Nano103.h.

Field Documentation

◆ DBCTL

GP_DB_T::DBCTL

[0x0180] Interrupt De-bounce Control Register

DBCTL

Offset: 0x180 Interrupt De-bounce Control Register

BitsFieldDescriptions
[3:0]DBCLKSEL
De-bounce Sampling Cycle Selection
0000 = Sample interrupt input once per 1 clocks.
0001 = Sample interrupt input once per 2 clocks.
0010 = Sample interrupt input once per 4 clocks.
0011 = Sample interrupt input once per 8 clocks.
0100 = Sample interrupt input once per 16 clocks.
0101 = Sample interrupt input once per 32 clocks.
0110 = Sample interrupt input once per 64 clocks.
0111 = Sample interrupt input once per 128 clocks.
1000 = Sample interrupt input once per 256 clocks.
1001 = Sample interrupt input once per 2*256 clocks.
1010 = Sample interrupt input once per 4*256 clocks.
1011 = Sample interrupt input once per 8*256 clocks.
1100 = Sample interrupt input once per 16*256 clocks.
1101 = Sample interrupt input once per 32*256 clocks.
1110 = Sample interrupt input once per 64*256 clocks.
1111 = Sample interrupt input once per 128*256 clocks.
[4]DBCLKSRC
De-bounce Counter Clock Source Selection
0 = De-bounce counter clock source is the HCLK.
1 = De-bounce counter clock source is the 10 kHz internal low speed RC oscillator (LIRC).
[5]ICLKON
Interrupt Clock on Mode
0 = Edge detection circuit is active only if I/O pin corresponding RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) bit is set to 1.
1 = All I/O pins edge detection circuit is always active after reset.
Note: It is recommended to disable this bit to save system power if no special application concern.

Definition at line 11848 of file Nano103.h.


The documentation for this struct was generated from the following file: