| Nano103 BSP V3.01.002 The Board Support Package for Nano103 Series

Data Fields
I2C_T Struct Reference

`#include <Nano103.h>`

## Data Fields
__IO uint32_t | CTL
__IO uint32_t | INTSTS
__I uint32_t | STATUS
__IO uint32_t | CLKDIV
__IO uint32_t | TOCTL
__IO uint32_t | DAT
__IO uint32_t | ADDR0
__IO uint32_t | ADDR1
__IO uint32_t | ADDRMSK0
__IO uint32_t | ADDRMSK1
__IO uint32_t | CTL2
__IO uint32_t | STATUS2

## Detailed Description

    @addtogroup I2C Inter-IC Bus Controller(I2C)
    Memory Mapped Structure for I2C Controller

Definition at line 21966 of file Nano103.h.

## Field Documentation

## ◆ ADDR0

I2C_T::ADDR0

[0x0018] I2C Slave Address Register0

ADDR0

Offset: 0x18 I2C Slave Address Register0

Bits | Field | Descriptions
[0] | GC | General Call Function Control 0 = General Call Function Disabled. 1 = General Call Function Enabled. Note: Refer to Address Register section for more detailed information.
[7:1] | ADDR | I2C Salve Address Bits The content of this register is irrelevant when the device is in Master mode In the Slave mode, the seven most significant bits must be loaded with the device's own address The device will react if either of the address is matched.

Definition at line 22437 of file Nano103.h.

## ◆ ADDR1

I2C_T::ADDR1

[0x001c] I2C Slave Address Register1

ADDR1

Offset: 0x1C I2C Slave Address Register1

Bits | Field | Descriptions
[0] | GC | General Call Function Control 0 = General Call Function Disabled. 1 = General Call Function Enabled. Note: Refer to Address Register section for more detailed information.
[7:1] | ADDR | I2C Salve Address Bits The content of this register is irrelevant when the device is in Master mode In the Slave mode, the seven most significant bits must be loaded with the device's own address The device will react if either of the address is matched.

Definition at line 22438 of file Nano103.h.

## ◆ ADDRMSK0

I2C_T::ADDRMSK0

[0x0028] I2C Slave Address Mask Register0

ADDRMSK0

Offset: 0x28 I2C Slave Address Mask Register0

Bits | Field | Descriptions
[7:1] | ADDRMSK | I2C Slave Address Mask Bits 0 = Mask disable (the received corresponding register bit should be exact the same as address register). 1 = Mask enable (the received corresponding address bit is don't care). I2C bus controllers support multiple address recognition with two address mask register When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.

Definition at line 22442 of file Nano103.h.

## ◆ ADDRMSK1

I2C_T::ADDRMSK1

[0x002c] I2C Slave Address Mask Register1

ADDRMSK1

Offset: 0x2C I2C Slave Address Mask Register1

Bits | Field | Descriptions
[7:1] | ADDRMSK | I2C Slave Address Mask Bits 0 = Mask disable (the received corresponding register bit should be exact the same as address register). 1 = Mask enable (the received corresponding address bit is don't care). I2C bus controllers support multiple address recognition with two address mask register When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.

Definition at line 22443 of file Nano103.h.

## ◆ CLKDIV

I2C_T::CLKDIV

[0x000c] I2C Clock Divided Register

CLKDIV

Offset: 0x0C I2C Clock Divided Register

Bits | Field | Descriptions
[7:0] | DIVIDER | I2C Clock Divided Bits Indicates the I2C clock rate bits: Data Baud Rate of I2C = PCLK /( 4 x ( I2C_CLKDIV + 1)). Note: The minimum value of I2C_CLKDIV is 4.

Definition at line 22434 of file Nano103.h.

## ◆ CTL

I2C_T::CTL

[0x0000] I2C Control Register

CTL

Offset: 0x00 I2C Control Register

Bits | Field | Descriptions
[0] | I2CEN | I2C Function Enable Bit 0 = I2C function Disabled. 1 = I2C function Enabled.
[1] | AA | Assert Acknowledge Control Bit When AA =1 prior to address or data is received, an acknowledged (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line when 1.)A slave is acknowledging the address sent from master, 2.) The receiver devices are acknowledging the data sent by transmitter When AA=0 prior to address or data received, a Not acknowledged (high level to SDA) will be returned during the acknowledge clock pulse on the SCL line.
[2] | STO | I2C STOP Control Bit In Master mode, setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected This bit will be cleared by hardware automatically.
[3] | STA | I2C START Command Setting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.
[4] | SI | I2C Status When a new state is present in the I2C_STATUS register, if the INTEN bit is set, the I2C interrupt is requested It must write one by software to this bit after the INTSTS (I2C_INTSTS[0]) is set to 1 and the I2C protocol function will go ahead until the STOP is active or the I2CEN is disabled. 0 = I2C's Status disabled and the I2C protocol function will go ahead. 1 = I2C's Status active. Note: If software wants to skip clearing INTSTS (I2C_INTSTS[0]), it also can write 1 to SI bit and must set INTEN bit That INTSTS (I2C_INTSTS[0]) will be cleared when SI is cleared.
[7] | INTEN | Interrupt Enable Bit 0 = I2C interrupt Disabled. 1 = I2C interrupt Enabled.

Definition at line 22431 of file Nano103.h.

## ◆ CTL2

I2C_T::CTL2

[0x0040] I2C Control Register 2

CTL2

Offset: 0x40 I2C Control Register 2

Bits | Field | Descriptions
[0] | WKUPEN | I2C Wake-up Function Enable Bit 0 = I2C wake-up function Disabled. 1 = I2C wake-up function Enabled.
[1] | OVIEN | I2C Overrun Interrupt Control Bit 0 = Overrun event interrupt Disabled. 1 = Send a interrupt to system when the TWOLVBUF bit is enabled and there is overrun event in received buffer.
[2] | URIEN | I2C Under run Interrupt Control Bit 0 = Under run event interrupt Disabled. 1 = Send a interrupt to system when the TWOLVBUF bit is enabled and there is under-run event happened in transmitted buffer.
[4] | TWOLVBUF | Two Level Buffer Enable Bit 0 = Two level buffer Disabled. 1 = Two level buffer Enabled.
[5] | NOSTRETCH | I2C BuS Stretch 0 = The I2C SCL bus is stretched by hardware if the SI (I2C_CTL[4]) is not cleared. 1 = The I2C SCL bus is not stretched by hardware if the SI is not cleared.
[6] | DATMODE | Data Mode Enable Bit 0 = Data mode Disabled. 1 = Data mode Enabled.
[7] | MSDAT | Master or Slave in Data Mode Enable Control 0 = Master writes data to device. 1 = Slave reads data from device.

Definition at line 22447 of file Nano103.h.

## ◆ DAT

I2C_T::DAT

[0x0014] I2C Data Register

DAT

Offset: 0x14 I2C Data Register

Bits | Field | Descriptions
[7:0] | DAT | I2C Data Bit [7:0] is located with the 8-bit transferred/received data of I2C serial port.

Definition at line 22436 of file Nano103.h.

## ◆ INTSTS

I2C_T::INTSTS

[0x0004] I2C Interrupt Status Register

INTSTS

Offset: 0x04 I2C Interrupt Status Register

Bits | Field | Descriptions
[0] | INTSTS | I2C STATUS's Interrupt Status When a new I2C state is present in the I2C_STATUS register, the INTSTS flag is set by hardware If bit INTEN (I2C_CTL [7]) is set, the I2C interrupt is requested.This bit must be cleared by software writing 1 . Note: If software wants to skip clearing INTSTS, it can also write 1 to SI (I2C_CTL [4]) bit and must set INTEN (I2C_CTL [7]) bit INISTS will be cleared when SI is cleared.
[1] | TOIF | Time-out Status 0 = No Time-out flag. 1 = Time-out flag active and it is set by hardware. It can interrupt CPU when INTEN bit is set. Note: This bit can be cleared by writing 1 to it.
[7] | WKAKDONE | Wake-up Address Frame Acknowledge Bit Done 0 = The ACK bit cycle of address match frame is not done. 1 = The ACK bit cycle of address match frame is done in power-down. Note: This bit can be cleared by writing 1 to it.

Definition at line 22432 of file Nano103.h.

## ◆ STATUS

I2C_T::STATUS

[0x0008] I2C Status Register

STATUS

Offset: 0x08 I2C Status Register

Bits | Field | Descriptions
[7:0] | STATUS | I2C Status Bits (Read Only) The three least significant bits are always 0 The five most significant bits contain the status code There are 28 possible status codes When the content of I2C_STATUS is F8H, no serial interrupt is requested Other I2C_STATUS values correspond to defined I2C states When each of these states is entered, a status interrupt is requested (INTSTS = 1) A valid status code is present in I2C_STATUS one cycle after INTSTS is set by hardware and is still present one cycle after INTSTS has been reset by software In addition, states 00H stands for a Bus Error A Bus Error occurs when a START or STOP condition is present at an illegal position in the formation frame Example of illegal position are during the serial transfer of an address byte, a data byte or an acknowledge bit.

Definition at line 22433 of file Nano103.h.

## ◆ STATUS2

I2C_T::STATUS2

[0x0044] I2C Status Register 2

STATUS2

Offset: 0x44 I2C Status Register 2

Bits | Field | Descriptions
[0] | WKIF | Wake-up Interrupt Flag 0 = Wake-up flag is inactive. 1 = Wake-up flag is active. Note: This bit can be cleared by writing 1 to it.
[1] | OVIF | I2C Overrun Status Bit 0 = The received buffer is not overrun when the TWOLVBUF = 1. 1 = The received buffer is overrun when the TWOLVBUF = 1. Note: This bit can be cleared by writing 1 to it.
[2] | URIF | I2C Under run Status Bit 0 = The transmitted buffer is not Under run when the TWOLVBUF = 1. 1 = The transmitted buffer is Under run when the TWOLVBUF = 1. Note: This bit can be cleared by writing 1 to it.
[3] | WRSTSWK | I2C Read/Write Status Bit in Address Wake-up Frame 0 = Write command is recorded on the address match wake-up frame. 1 = Read command is recorded on the address match wake-up frame.
[4] | FULL | I2C Two Level Buffer Full 0 = TX buffer no full when the TWOLVBUF = 1. 1 = TX buffer full when the TWOLVBUF = 1.
[5] | EMPTY | I2C Two Level Buffer Empty 0 = RX buffer is not empty when the TWOLVBUF = 1. 1 = RX buffer is empty when the TWOLVBUF = 1.
[6] | BUSFREE | Bus Free Status The bus status in the controller. 0 = I2C's 'Start' condition is detected on the bus. 1 = Bus is free and released by 'STOP' condition or the controller is disabled.

Definition at line 22448 of file Nano103.h.

## ◆ TOCTL

I2C_T::TOCTL

[0x0010] I2C Time-out Control Register

TOCTL

Offset: 0x10 I2C Time-out Control Register

Bits | Field | Descriptions
[0] | TOCEN | Time-out Counter Enable Bit When this bit is set to enabled and clock be stretched, the 14 bits time-out counter will start counting. 0 = Time-out counter Disabled. 1 = Time-out counter Enabled.
[1] | TOCDIV4 | Time-out Counter Input Clock Divider by 4 When enabled, the time-out period is extended 4 times. 0 = Time-out counter input clock divider by 4 Disabled. 1 = Time-out counter input clock divider by 4 Enabled.

Definition at line 22435 of file Nano103.h.

The documentation for this struct was generated from the following file:

- C:/Users/yachen/workzone/bsp/nano103bsp/Library/Device/Nuvoton/Nano103/Include/Nano103.h