| Nano103 BSP V3.01.002 The Board Support Package for Nano103 Series

Data Fields
FMC_T Struct Reference

`#include <Nano103.h>`

## Data Fields
__IO uint32_t | ISPCTL
__IO uint32_t | ISPADDR
__IO uint32_t | ISPDAT
__IO uint32_t | ISPCMD
__IO uint32_t | ISPTRG
__I uint32_t | DFBA
__IO uint32_t | FTCTL
__IO uint32_t | ISPSTS
__O uint32_t | KEY0
__O uint32_t | KEY1
__O uint32_t | KEY2
__IO uint32_t | KEYTRG
__IO uint32_t | KEYSTS
__I uint32_t | KECNT
__I uint32_t | KPCNT

## Detailed Description

    @addtogroup FMC Flash Memory Controller(FMC)
    Memory Mapped Structure for FMC Controller

Definition at line 5233 of file Nano103.h.

## Field Documentation

## ◆ DFBA

FMC_T::DFBA

[0x0014] Data Flash Base Address

DFBA

Offset: 0x14 Data Flash Base Address

Bits | Field | Descriptions
[31:0] | DFBA | Data Flash Base Address This register indicates Data Flash start address. It is a read only register. The Data Flash is shared with APROM. the content of this register is loaded from CONFIG1. This register is valid when DFEN (CONFIG0[0]) =0 .

Definition at line 5862 of file Nano103.h.

## ◆ FTCTL

FMC_T::FTCTL

[0x0018] Flash Access Time Control Register

FTCTL

Offset: 0x18 Flash Access Time Control Register

Bits | Field | Descriptions
[6:4] | FOM | Frequency Optimization Mode (Write Protect) The Nano103 series supports adjustable flash access timing to optimize the flash access cycles in different working frequency. 001 = Frequency <= 20MHz. 100 = Frequency <= 36MHz. (default power-on setting) Others = Reserved Note:This bit is write protected. Refer to the SYS_REGLCTL register.
[7] | CACHEOFF | Flash Cache Disable Control (Write Protect) 0 = Flash Cache function Enabled (default). 1 = Flash Cache function Disabled. Note:This bit is write protected. Refer to the SYS_REGLCTL register.

Definition at line 5863 of file Nano103.h.

## ◆ ISPADDR

FMC_T::ISPADDR

[0x0004] ISP Address Register

ISPADDR

Offset: 0x04 ISP Address Register

Bits | Field | Descriptions
[31:0] | ISPADDR | ISP Address The Nano103 series is equipped with embedded flash ISPADDR [1:0] must be kept 00 for ISP 32-bit operation. For both CRC-32 Checksum Calculation and Flash All-One Verification commands, this field is the flash starting address for checksum calculation and 512 bytes address alignment is necessary.

Definition at line 5858 of file Nano103.h.

## ◆ ISPCMD

FMC_T::ISPCMD

[0x000c] ISP CMD Register

ISPCMD

Offset: 0x0C ISP CMD Register

Bits | Field | Descriptions
[5:0] | CMD | ISP CMD ISP command table is shown below: 0x00 = FLASH 32-bit Read. 0x04 = Read Unique ID. 0x08 = Read All-One Verification Result. 0x0B = Read Company ID. 0x0C = Read Device ID. 0x0D = Read CRC-32 Checksum. 0x21 = FLASH 32-bit Program. 0x22 = FLASH Page Erase. 0x26 = FLASH Mass Erase. 0x28 = Run All-One Verification. 0x2D = Run CRC-32 Checksum Calculation. 0x2E = Vector Remap. The other commands are invalid.

Definition at line 5860 of file Nano103.h.

## ◆ ISPCTL

FMC_T::ISPCTL

[0x0000] ISP Control Register

ISPCTL

Offset: 0x00 ISP Control Register

Bits | Field | Descriptions
[0] | ISPEN | ISP Enable Bit (Write Protect) ISP function enable bit. Set this bit to enable ISP function. 0 = ISP function Disabled. 1 = ISP function Enabled. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[1] | BS | Boot Select (Write Protect) Set/clear this bit to select next booting from LDROM/APROM, respectively This bit also functions as chip booting status flag, which can be used to check where chip booted from. This bit is initiated with the inversed value of CBS[1] (CONFIG0[7]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened. 0 = Booting from APROM. 1 = Booting from LDROM. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[3] | APUEN | APROM Update Enable Bit (Write Protect) 0 = APROM cannot be updated when the chip runs in APROM booting without IAP mode. 1 = APROM can be updated when the chip runs in APROM booting without IAP mode Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[4] | CFGUEN | CONFIG Update Enable Bit (Write Protect) 0 = CONFIG cannot be updated. 1 = CONFIG can be updated. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[5] | LDUEN | LDROM Update Enable Bit (Write Protect) LDROM update enable bit. 0 = LDROM cannot be updated. 1 = LDROM can be updated. Note: This bit is write protected. Refer to the SYS_REGLCTL register. In LDROM booting without IAP mode, LDROM cannot be updated even if LDUEN=1.
[6] | ISPFF | ISP Fail Flag (Write Protect) This bit is set by hardware when a triggered ISP meets any of the following conditions: This bit needs to be cleared by writing 1 to it. (1) APROM writes to itself if APUEN is set to 0. (2) LDROM writes to itself if LDUEN is set to 0. (3) CONFIG is erased/programmed if CFGUEN is set to 0. (6) Page Erase command at LOCK mode with ICE connection (7) Erase or Program command at brown-out detected (8) Destination address is illegal, such as over an available range. (9) Invalid ISP commands (10) KPROM is erased/programmed if KEYLOCK is set to 1 (11) APROM(not include Data Flash) is erased/programmed if KEYLOCK is set to 1 Note: This bit is write protected. Refer to the SYS_REGLCTL register.

Definition at line 5857 of file Nano103.h.

## ◆ ISPDAT

FMC_T::ISPDAT

[0x0008] ISP Data Register

ISPDAT

Offset: 0x08 ISP Data Register

Bits | Field | Descriptions
[31:0] | ISPDAT | ISP Data Write data to this register before ISP program operation. Read data from this register after ISP read operation. For Run CRC-32 Checksum Calculation command, ISPDAT is the memory size (byte) and 512 bytes alignment For ISP Read CRC-32 Checksum command, ISPDAT is the checksum result If ISPDAT = 0x0000_0000, it means that (1) the checksum calculation is in progress, (2) the memory range for checksum calculation is incorrect.

Definition at line 5859 of file Nano103.h.

## ◆ ISPSTS

FMC_T::ISPSTS

[0x0040] ISP Status Register

ISPSTS

Offset: 0x40 ISP Status Register

Bits | Field | Descriptions
[0] | ISPBUSY | ISP Busy Flag (Read Only) Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished. This bit is the mirror of ISPGO(FMC_ISPTRG[0]). 0 = ISP operation is finished. 1 = ISP is progressed.
[2:1] | CBS | Boot Selection of CONFIG (Read Only) This bit is initiated with the CBS (CONFIG0 [7:6]) after any reset is happened except CPU reset (CPURF(SYS_RSTSTS[7]) is 1) or system reset (SYSRF(SYS_RSTSTS[5]) is happened. 00 = LDROM with IAP mode. 01 = LDROM without IAP mode. 10 = APROM with IAP mode. 11 = APROM without IAP mode.
[5] | PGFF | Flash Program with Fast Verification Flag(Read Only) This bit is set if data is mismatched at ISP programming verification This bit is clear by performing ISP flash erase or ISP read CID operation 0 = Flash Program is success. 1 = Flash Program is fail. Program data is different with data in the flash memory.
[6] | ISPFF | ISP Fail Flag (Write Protect) This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6] This bit is set by hardware when a triggered ISP meets any of the following conditions: (1) APROM writes to itself if APUEN is set to 0. (2) LDROM writes to itself if LDUEN is set to 0. (3) CONFIG is erased/programmed if CFGUEN is set to 0. (4) Page Erase command at LOCK mode with ICE connection (5) Erase or Program command at brown-out detected (6) Destination address is illegal, such as over an available range. (7) Invalid ISP commands (8) KPROM is erased/programmed if KEYLOCK is set to 1 (9) APROM(not include Data Flash) is erased/programmed if KEYLOCK is set to 1 Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
[7] | ALLONE | Flash All-one Verification Flag This bit is set by hardware if all of flash bits are 1, and clear if flash bits are not all 1 after "Run Flash All-One Verification" complete; this bit also can be clear by writing 1. 0 = All of flash bits are 1 after "Run Flash All-One Verification" complete. 1 = Flash bits are not all 1 after "Run Flash All-One Verification" complete.
[29:9] | VECMAP | Vector Page Mapping Address (Read Only) All access to 0x0000_0000~0x0000_01FF is remapped to the flash memory or SRAM address {VECMAP[20:0], 9'h000} ~ {VECMAP[20:0], 9'h1FF} VECMAP [20:19] = 00 system vector address is mapped to flash memory. VECMAP [20:19] = 10 system vector address is mapped to SRAM memory. VECMAP [18:12] should be 0.

Definition at line 5867 of file Nano103.h.

## ◆ ISPTRG

FMC_T::ISPTRG

[0x0010] ISP Trigger Control Register

ISPTRG

Offset: 0x10 ISP Trigger Control Register

Bits | Field | Descriptions
[0] | ISPGO | ISP Start Trigger (Write Protect) Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished. 0 = ISP operation is finished. 1 = ISP is progressed. Note:This bit is write protected. Refer to the SYS_REGLCTL register.

Definition at line 5861 of file Nano103.h.

## ◆ KECNT

FMC_T::KECNT

[0x0064] KEY-Unmatched Counting Register

KECNT

Offset: 0x64 KEY-Unmatched Counting Register

Bits | Field | Descriptions
[5:0] | KECNT | Error Key Entry Counter at Each Power-on (Read Only) KECNT is increased when entry keys is wrong in Security Key protection. KECNT is cleared to 0 if key comparison is matched or system power-on.
[13:8] | KEMAX | Maximum Number for Error Key Entry at Each Power-on (Read Only). KEMAX is the maximum error key entry number at each power-on. When KEMAXROM of KPROM is erased or programmed, KEMAX will also be updated. KEMAX is used to limit KECNT(FMC_KECNT[5:0]) maximum counting. The FORBID (FMC_KEYSTS [3]) will be set to 1 when KECNT is more than KEMAX.

Definition at line 5876 of file Nano103.h.

## ◆ KEY0

FMC_T::KEY0

[0x0050] KEY0 Data Register

KEY0

Offset: 0x50 KEY0 Data Register

Bits | Field | Descriptions
[31:0] | KEY0 | KEY0 Data (Write Only) Write KEY0 data to this register before KEY Comparison operation.

Definition at line 5871 of file Nano103.h.

## ◆ KEY1

FMC_T::KEY1

[0x0054] KEY1 Data Register

KEY1

Offset: 0x54 KEY1 Data Register

Bits | Field | Descriptions
[31:0] | KEY1 | KEY1 Data (Write Only) Write KEY1 data to this register before KEY Comparison operation.

Definition at line 5872 of file Nano103.h.

## ◆ KEY2

FMC_T::KEY2

[0x0058] KEY2 Data Register

KEY2

Offset: 0x58 KEY2 Data Register

Bits | Field | Descriptions
[31:0] | KEY2 | KEY2 Data (Write Only) Write KEY2 data to this register before KEY Comparison operation.

Definition at line 5873 of file Nano103.h.

## ◆ KEYSTS

FMC_T::KEYSTS

[0x0060] KEY Comparison Status Register

KEYSTS

Offset: 0x60 KEY Comparison Status Register

Bits | Field | Descriptions
[0] | KEYBUSY | KEY Comparison Busy (Read Only) 0 = KEY comparison is finished. 1 = KEY comparison is busy.
[1] | KEYLOCK | KEY LOCK Flag This bit is set to 1 if KEYMATCH (FMC_KEYSTS [2]) is 0 and cleared to 0 if KEYMATCH is 1 in Security Key protection This bit also can be set to 1 while l CPU write 1 to KEYLOCK(FMC_KEYSTS[1]) or l KEYFLAG(FMC_KEYSTS[4]) is 1 at power-on or reset or l KEYENROM is programmed a non-0xFF value or l Time-out event or l FORBID(FMC_KEYSTS[3]) is 1 0 = KPROM and APROM (not include Data Flash) is not in write protection. 1 = KPROM and APROM (not include Data Flash) is in write protection. CONFIG write protect is depended on CFGFLAG
[2] | KEYMATCH | KEY Match Flag(Read Only) This bit is set to 1 after KEY comparison complete if the KEY0, KEY1 and KEY2 are matched with the 96-bit security keys in KPROM; and cleared to 0 if KEYs are unmatched This bit is also cleared to 0 while l CPU writing 1 to KEYLOCK(FMC_KEYSTS[1]) or l Time-out event or l KPROM is erased or l KEYENROM is programmed to a non-0xFF value. l Chip is in Power-down mode. 0 = KEY0, KEY1, and KEY2 are unmatched with the KPROM setting. 1 = KEY0, KEY1, and KEY2 are matched with the KPROM setting.
[3] | FORBID | KEY Comparison Forbidden Flag(Read Only) This bit is set to 1 whenKECNT(FMC_KECNT[4:0])is more than KEMAX (FMC_KECNT[12:8]) orKPCNT (FMC_KPCNT [2:0])is more than KPMAX (FMC_KPCNT [10:8]). 0 = KEY comparison is not forbidden. 1 = KEY comparison is forbidden, KEYGO (FMC_KEYTRG [0]) cannot trigger.
[4] | KEYFLAG | KEY Protection Enable Flag(Read Only) This bit is set while the KEYENROM [7:0] is not 0xFF at power-on or reset This bit is cleared to 0 by hardware while KPROM is erased This bit is set to 1 by hardware while KEYENROM is programmed to a non-0xFF value. 0 = Security Key protection Disabled. 1 = Security KeyprotectionEnabled.
[5] | CFGFLAG | CONFIG Write-protection Enable Flag(Read Only) This bit is set while the KEYENROM [0] is 0 at power-on or reset This bit is cleared to 0 by hardware while KPROM is erased This bit is set to 1 by hardware while KEYENROM[0] is programmed to 0. 0 = CONFIG write-protection Disabled. 1 = CONFIG write-protection Enabled.

Definition at line 5875 of file Nano103.h.

## ◆ KEYTRG

FMC_T::KEYTRG

[0x005c] KEY Comparison Trigger Control Register

KEYTRG

Offset: 0x5C KEY Comparison Trigger Control Register

Bits | Field | Descriptions
[0] | KEYGO | KEY Comparison Start Trigger (Write Protection) Write 1 to start KEY comparison operation and this bit will be cleared to 0 by hardware automatically when KEY comparison operation is finished. This trigger operation is valid while FORBID (FMC_KEYSTS [3]) is 0. 0 = KEY comparison operation is finished. 1 = KEY comparison is progressed. Note:This bit is write-protected. Refer to the SYS_REGLCTL register.
[1] | TCEN | Time-out Counting Enable Bit (Write Protection) 0 = Time-out counting Disabled. 1 = Time-out counting Enabled if key is matched after key comparison finish. 10 minutes is at least for time-out, and average is about 20 minutes. Note:This bit is write-protected. Refer to the SYS_REGLCTL register.

Definition at line 5874 of file Nano103.h.

## ◆ KPCNT

FMC_T::KPCNT

[0x0068] KEY-Unmatched Power-on Counting Register

KPCNT

Offset: 0x68 KEY-Unmatched Power-on Counting Register

Bits | Field | Descriptions
[3:0] | KPCNT | Power-on Counter for Error Key Entry(Read Only). KPCNT is the power-on counting for error key entry in Security Key protection. KPCNT is cleared to 0 if key comparison is matched.
[11:8] | KPMAX | Power-on Maximum Number for Error Key Entry (Read Only). KPMAX is the power-on maximum number for error key entry. When KPMAXROM of KPROM is erased or programmed, KPMAX will also be updated. KPMAX is used to limit KPCNT (FMC_KPCNT [3:0]) maximum counting. The FORBID(FMC_KEYSTS[3]) will be set to 1 when KPCNT is more than KPMAX.

Definition at line 5877 of file Nano103.h.

The documentation for this struct was generated from the following file:

- C:/Users/yachen/workzone/bsp/nano103bsp/Library/Device/Nuvoton/Nano103/Include/Nano103.h