| Nano103 BSP V3.01.002 The Board Support Package for Nano103 Series

Data Fields
SPI_T Struct Reference

`#include <Nano103.h>`

## Data Fields
__IO uint32_t | CTL
__IO uint32_t | STATUS
__IO uint32_t | CLKDIV
__IO uint32_t | SSCTL
__I uint32_t | RX0
__I uint32_t | RX1
__O uint32_t | TX0
__O uint32_t | TX1
__IO uint32_t | PDMACTL
__IO uint32_t | FIFOCTL

## Detailed Description

    @addtogroup SPI Serial Peripheral Interface Controller(SPI)
    Memory Mapped Structure for SPI Controller

Definition at line 22569 of file Nano103.h.

## Field Documentation

## ◆ CLKDIV

SPI_T::CLKDIV

[0x0008] SPI Clock Divider Register

CLKDIV

Offset: 0x08 SPI Clock Divider Register

Bits | Field | Descriptions
[7:0] | DIVIDER | Clock Divider The value is the 1th frequency divider of the PCLK to generate the serial clock of SPI_CLK The desired frequency is obtained according to the following equation: Where is the SPI peripheral clock source It is defined in the CLK_SEL2[21:20] in Clock control section (CLK_BA + 0x18).

Definition at line 23395 of file Nano103.h.

## ◆ CTL

SPI_T::CTL

[0x0000] SPI Control Register

CTL

Offset: 0x00 SPI Control Register

Bits | Field | Descriptions
[0] | GOBUSY | SPI Transfer Control Bit and Busy Status 0 = Writing this bit 0 will stop data transfer if SPI is transferring. 1 = In Master mode, writing 1 to this bit will start the SPI data transfer; In Slave mode, writing '1' to this bit indicates that the slave is ready to communicate with a master. If the FIFO mode is disabled, during the data transfer, this bit keeps the value of '1' As the transfer is finished, this bit will be cleared automatically Software can read this bit to check if the SPI is in busy status. In FIFO mode, this bit will be controlled by hardware Software should not modify this bit In slave mode, this bit always returns 1 when software reads this register In master mode, this bit reflects the busy or idle status of SPI. Note: 1.When FIFO mode is disabled, all configurations should be set before writing 1 to the GOBUSY bit in the SPI_CTL register. 2 When FIFO bit is disabled and the software uses TX or RX PDMA function to transfer data, this bit will be cleared after the PDMA controller finishes the data transfer.
[1] | RXNEG | Receive on Negative Edge 0 = The received data is latched on the rising edge of SPI_CLK. 1 = The received data is latched on the falling edge of SPI_CLK. Note: Refer to Edge section.
[2] | TXNEG | Transmit on Negative Edge 0 = The transmitted data output is changed on the rising edge of SPI_CLK. 1 = The transmitted data output is changed on the falling edge of SPI_CLK. Note: Refer to Edge section.
[7:3] | DWIDTH | Data Width This field specifies how many bits can be transmitted / received in one transaction The minimum bit length is 8 bits and can be up to 32 bits. 01000 = 8 bits are transmitted in one transaction. 01001 = 9 bits are transmitted in one transaction. 01010 = 10 bits are transmitted in one transaction. ----- 11111 = 31 bits are transmitted in one transaction. 00000 = 32 bits are transmitted in one transaction.
[10] | LSB | Send LSB First 0 = The MSB, which bit of transmit/receive register depends on the setting of DWIDTH (SPI_CTL[7:3]), is transmitted/received first. 1 = The LSB, bit 0 of the SPI_TX0/1, is sent first to the the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (SPI_RX0/1). Note: Refer to LSB first section.
[11] | CLKPOL | Clock Polarity 0 = The default level of SPI_CLK is low. 1 = The default level of SPI_CLK is high. Note: Refer to Clock Parity section.
[15:12] | SUSPITV | Suspend Interval (Master Only) These four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer The suspend interval is from the last falling clock edge of the current transaction to the first rising clock edge of the successive transaction if CLKPOL = 0 If CLKPOL = 1, the interval is from the rising clock edge to the falling clock edge. The default value is 0x3 The desired suspend interval is obtained according to the following equation: )(SP_]YCLE[3]0) + 0.5) * period of SPI_CLK For example, SUSPITV = 0x0 .... 0.5 SPI_CLK clock cycle. SUSPITV = 0x1 .... 1.5 SPI_CLK clock cycle. ...... SUSPITV = 0xE .... 14.5 SPI_CLK clock cycle. SUSPITV = 0xF .... 15.5 SPI_CLK clock cycle.
[17] | UNITIEN | Unit Transfer Interrupt Enable Bit 0 = SPI unit transfer interrupt Disabled. 1 = SPI unit transfer interrupt Enabled.
[18] | SLAVE | Slave Mode Selection 0 = SPI controller set as Master mode. 1 = SPI controller set as Slave mode. Note: Refer to Slave Selection section
[19] | REORDER | Byte Reorder Function Enable Bit 0 = Byte reorder function Disabled. 1 = Enable byte reorder function and insert a byte suspend interval among each byte The setting of DWIDTH must be configured as 00b ( 32 bits/ word) Note: The suspend interval is defined in SUSPITV. Refer to Byte Reorder section. Note: Byte Suspend is only used in SPI Byte Reorder mode.
[21] | FIFOM | FIFO Mode Enable Bit 0 = FIFO mode Disabled (in Normal mode). 1 = FIFO mode Enabled. Note: Refer to FIFO Mode section.
[22] | TWOBIT | 2-bit Transfer Mode Enable Bit 0 = 2-bit transfer mode Disabled. 1 = 2-bit transfer mode Enabled. Refer to Two Bit Transfer Mode section Note: automatically
[28] | DUALDIR | Dual I/O Mode Direction Control 0 = Date read in the Dual I/O Mode function. 1 = Data write in the Dual I/O Mode function. Refer to Dual I/O Mode section.
[29] | DUALIOEN | Dual I/O Mode Enable Bit 0 = Dual I/O Mode function Disabled. 1 = Dual I/O Mode function Enabled. Refer to Dual I/O Mode section.
[30] | WKSSEN | Wake-up by Slave Select Enable Bit 0 = Wake-up function Disabled. 1 = Wake-up function Enabled. Note: The Slave select wake-up function is only available in SPI Slave mode When the system enters Power-down mode, the system can be wake-up from the SPI controller if this bit is enabled and there is any toggle on the SPI_SS port After the system wake-up, this bit must be cleared by user to disable the wake-up requirement.
[31] | WKCLKEN | Wake-up by SPI Clock Enable Bit 0 = Wake-up function Disabled. 1 = Wake-up function Enabled. Note: When the system enters Power-down mode, the system can be wake-up from the SPI controller if this bit is enabled and there is any toggle on the SPI_CLK port After the system wake-up, this bit must be cleared by user to disable the wake-up requirement.

Definition at line 23393 of file Nano103.h.

## ◆ FIFOCTL

SPI_T::FIFOCTL

[0x003c] SPI FIFO Control Register

FIFOCTL

Offset: 0x3C SPI FIFO Control Register

Bits | Field | Descriptions
[0] | RXFBCLR | Receive FIFO Buffer Clear 0 = No clear the received FIFO. 1 = Clear the received FIFO. Note: This bit is used to clear the receiver counter in FIFO Mode This bit can be written 1 to clear the receiver counter and this bit will be cleared to 0 automatically after clearing receiving counter After the clear operation, the flag of RXEMPTY in SPI_STATUS[0] will be set to 1.
[1] | TXFBCLR | Transmit FIFO Buffer Clear 0 = Not clear the transmitted FIFO. 1 = Clear the transmitted FIFO. Note: This bit is used to clear the transmit counter in FIFO Mode This bit can be written 1 to clear the transmitting counter and this bit will be cleared to 0 automatically after clearing transmitting counter After the clear operation, the flag of TXEMPTY in SPI_STATUS[2] will be set to 1.
[2] | RXTHIEN | Receive Threshold Interrupt Enable Bit 0 = RX threshold interrupt Disabled. 1 = RX threshold interrupt Enabled.
[3] | TXTHIEN | Transmit Threshold Interrupt Enable Bit 0 = TX threshold interrupt Disabled. 1 = TX threshold interrupt Enabled.
[4] | RXOVIEN | Receive FIFO over Run Interrupt Enable Bit 0 = RX FIFO over run interrupt Disabled. 1 = RX FIFO over run interrupt Enabled.
[7] | RXTOIEN | RX Read Time Out Interrupt Enable Bit 0 = RX read Timeout Interrupt Disabled. 1 = RX read Timeout Interrupt Enabled.
[26:24] | RXTH | Received FIFO Threshold If RX valid data counts are greater than RXTH, RXTHIF (SPI_STATUS[8]) will be set to 1.
[30:28] | TXTH | Transmit FIFO Threshold If TX valid data counts are smaller than or equal to TXTH, TXTHIF (SPI_STATUS[10]) will be set to 1.

Definition at line 23408 of file Nano103.h.

## ◆ PDMACTL

SPI_T::PDMACTL

[0x0038] SPI PDMA Control Register

PDMACTL

Offset: 0x38 SPI PDMA Control Register

Bits | Field | Descriptions
[0] | TXPDMAEN | Transmit PDMA Enable Bit 0 = Transmit PDMA function Disabled. 1 = Transmit PDMA function Enabled. Refer to PDMA section for more detail information. SPI_CTL Note: 1 Two transaction need minimal 18 APB clock + 8 SPI peripheral clocks suspend interval in master mode for edge mode and 18 APB clock + 9.5 SPI peripheral clocks for level mode. 2 If the 2-bit function is enabled, the requirement timing shall append 18 APB clock based on the above clock period. Hardware will clear this bit to 0 automatically after PDMA transfer done.
[1] | RXPDMAEN | Receiving PDMA Enable Bit 0 = Receiver PDMA function Disabled. 1 = Receiver PDMA function Enabled. Refer to PDMA section for more detail information. Note: Hardware will clear this bit to 0 automatically after PDMA transfer done. In Slave mode and the FIFO bit is disabled, if the receive PDMA is enabled but the transmit PDMA is disabled, the minimal suspend interval between two successive transactions input is need to be larger than 9 SPI peripheral clock + 4 APB clock for edge mode and 9.5 SPI peripheral clock + 4 APB clock
[2] | PDMARST | PDMA Reset It is used to reset the SPI PDMA function into default state. 0 = After reset PDMA function or in normal operation. 1 = Reset PDMA function. Note: it is auto cleared to 0 after the reset function has done.

Definition at line 23407 of file Nano103.h.

## ◆ RX0

SPI_T::RX0

[0x0010] SPI Receive Data FIFO Register 0

RX0

Offset: 0x10 SPI Receive Data FIFO Register 0

Bits | Field | Descriptions
[31:0] | RX | Receive Data Register (Read Only) The received data can be read on it If the FIFO bit is set as 1, the user also checks the RXEMPTY, SPI_STATUS[0], to check if there is any more received data or not. Note: The SPI_RX1 is used only in TWOBIT bit (SPI_CTL[22]) is set 1 The first channel's received data shall be read from SPI_RX0 and the second channel's received data shall be read from SPI_RX1 in two-bit mode SPI_RX0 shall be read first in TWOBIT mode. In FIFO and two-bit mode, the first read back data in SPI_RX0 is the first channel data and the second read back data in SPI_RX0 is the second channel data.

Definition at line 23397 of file Nano103.h.

## ◆ RX1

SPI_T::RX1

[0x0014] SPI Receive Data FIFO Register 1

RX1

Offset: 0x14 SPI Receive Data FIFO Register 1

Bits | Field | Descriptions
[31:0] | RX | Receive Data Register (Read Only) The received data can be read on it If the FIFO bit is set as 1, the user also checks the RXEMPTY, SPI_STATUS[0], to check if there is any more received data or not. Note: The SPI_RX1 is used only in TWOBIT bit (SPI_CTL[22]) is set 1 The first channel's received data shall be read from SPI_RX0 and the second channel's received data shall be read from SPI_RX1 in two-bit mode SPI_RX0 shall be read first in TWOBIT mode. In FIFO and two-bit mode, the first read back data in SPI_RX0 is the first channel data and the second read back data in SPI_RX0 is the second channel data.

Definition at line 23398 of file Nano103.h.

## ◆ SSCTL

SPI_T::SSCTL

[0x000c] SPI Slave Select Control Register

SSCTL

Offset: 0x0C SPI Slave Select Control Register

Bits | Field | Descriptions
[1:0] | SS | Slave Selection Control (Master Only) If AUTOSS bit (SPI_SSCTL[3]) is cleared, writing 1 to SS[0] (SPI_CTL[0]) bit sets the SPI_SS0 line to an active state and writing 0 sets the line back to inactive state (the same as SPI_CTL[1] for SPI_SS1). If AUTOSS = 0,. 00 = Both SPI_SS1 and SPI_SS0 are inactive. 01 = SPI_SS1 is inactive, SPI_SS0 is active. 10 = SPI_SS1 is active, SPI_SS0 is inactive. 11 = Both SPI_SS1 and SPI_SS0 are active. If AUTOSS bit is set, writing 1 to any bit location of this field will select appropriate SPI_SS0/SPI_SS1 line to be automatically driven to active state for the duration of the transaction, and will be driven to inactive state for the rest of the time (The active level of SPI_SS1/SPI_SS0 is specified in SSACTPOL). If AUTOSS =1,. 00 = Both SPI_SS1 and SPI_SS0 are inactive. 01 = SPI_SS1 is inactive, SPI_SS0 is active on the duration of transaction. 10 = SPI_SS1 is active on the duration of transaction, SPI_SS0 is inactive. 11 = Both SPI_SS1 and SPI_SS0 are active on the duration of transaction. Note: 1. This interface can only drive one device/slave at a given time. Therefore, the slaves select of the selected device must be set to its active level before starting any read or write transfer. 2. SPI_SS0 is also defined as device/slave select input in Slave mode And that the slave select input must be driven by edge active trigger which level depend on the SSACTPOL setting, otherwise the SPI slave core will go into dead path until the edge active triggers again or reset the SPI core by software
[2] | SSACTPOL | Slave Selection Active Polarity It defines the active polarity of slave selection signal (SPI_SS[1:0]). 0 = The SPI_SS slave select signal is active Low. 1 = The SPI_SS slave select signal is active High.
[3] | AUTOSS | Automatic Slave Selection Function Enable Bit (Master Only) 0 = If this bit is set as 0, slave select signals are asserted and de-asserted by setting and clearing related bits in SS[1:0] (SPI_CTL[1:0]). 1 = If this bit is set as 1, SPI_SS0 and SPI_SS1 signals are generated automatically It means that device/slave select signal, which is set in SS[1:0] (SPI_CTL[1:0]) is asserted by the SPI controller when transmit/receive is started, and is de-asserted after each transaction is done.
[4] | SSLTRIG | Slave Select Level Trigger Control 0 = The input slave select signal is edge-trigger. 1 = The slave select signal will be level-trigger It depends on SSACTPOL to decide the signal is active low or active high.
[5] | SLV3WIRE | Slave 3-wire Mode Enable Bit This bit is used to ignore the slave select signal in Slave mode The SPI controller can work with 3-wire interface including SPI_CLK, SPI_MISO, and SPI_MOSI when it is set as a slave device. 0 = The controller is 4-wire bi-direction interface. 1 = The controller is 3-wire bi-direction interface in Slave mode When this bit is set as 1, the controller start to transmit/receive data after the GOBUSY bit active and the SPI clock input. Note 1: Refer to No Slave Select Mode. Note 2: In no slave select signal mode, hardware will set the SSLTRIG (SPI_SSCTL[4]) as 1 automatically.
[6] | SLVTOIEN | Slave Time-out Interrupt Enable Bit This bit is used to enable the slave time-out function in slave mode and there will be an interrupt if slave time-out event occur 0 = Slave time-out function and interrupt both Disabled. 1 = Slave time-out function and interrupt both Enabled.
[8] | SLVABORT | Abort in Slave Mode with No Slave Selected 0 = No force the slave abort. 1 = Force the current transfer done in no slave select mode. Refer to No Slave Select Mode. Note: It is auto cleared to 0 by hardware when the abort event is active.
[9] | SSTAIEN | Slave Start Interrupt Enable Bit 0 = Transfer start interrupt Disabled in no slave select mode. 1 = Transaction start interrupt Enabled in no slave select mode It is cleared when the current transfer done or the SLVSTAIF bit cleared (write 1 clear). Refer to No Slave Select Mode.
[16] | SSINAIEN | Slave Select Inactive Interrupt Enable Bit It is used to enable the interrupt when the transfer has done in slave mode. 0 = No any interrupt, even there is slave select inactive event. 1 = There is interrupt event when the slave select becomes inactive from active condition It is used to inform the user to know that the transaction has finished and the slave select into the inactive state.
[29:20] | SLVTOCNT | Slave Mode Time-out Period In Slave mode, these bits indicate the time-out period when there is bus clock input during slave select active The clock source of the time-out counter is Slave peripheral clock If the value is 0, it indicates the slave mode time-out function is disabled.

Definition at line 23396 of file Nano103.h.

## ◆ STATUS

SPI_T::STATUS

[0x0004] SPI Status Register

STATUS

Offset: 0x04 SPI Status Register

Bits | Field | Descriptions
[0] | RXEMPTY | Receive FIFO Buffer Empty Indicator (Read Only) 0 = Received data FIFO is not empty in the FIFO mode. 1 = Received data FIFO is empty in the FIFO mode.
[1] | RXFULL | Receive FIFO Buffer Full Indicator (Read Only) 0 = Received data FIFO is not full in FIFO mode. 1 = Received data FIFO is full in the FIFO mode.
[2] | TXEMPTY | Transmit FIFO Buffer Empty Indicator (Read Only) 0 = Transmitted data FIFO is not empty in the FIFO mode. 1 =Transmitted data FIFO is empty in the FIFO mode.
[3] | TXFULL | Transmit FIFO Buffer Full Indicator (Read Only) 0 = Transmitted data FIFO is not full in the FIFO mode. 1 = Transmitted data FIFO is full in the FIFO mode.
[4] | LTRIGF | Level Trigger Accomplish Flag (Read Only) In Slave mode, this bit indicates whether the received bit number meets the requirement or not after the current transaction done. 0 = The transferred bit length of one transaction does not meet the specified requirement. 1 = The transferred bit length meets the specified requirement which defined in DWIDTH. Note: This bit is READ only As the software sets the GOBUSY bit to 1, the LTRIGF will be cleared to 0 after 4 SPI peripheral clock periods plus 1 system clock period In FIFO mode, this bit is unmeaning.
[6] | SLVSTAIF | Slave Start Interrupt Flag It is used to dedicate that the transfer has started in Slave mode with no slave select. 0 = Slave started transfer no active. 1 = Transfer has started in Slave mode with no slave select It is automatically cleared by transfer done or writing '1'.
[7] | UNITIF | Unit Transfer Interrupt Flag 0 = No transaction has been finished since this bit was cleared to 0. 1 = SPI controller has finished one unit transfer. Note 1: This bit will be cleared by writing 1 to it. 0 = Transfer is not finished yet. 1 = Transfer is done. The interrupt is requested when the UNITIEN (SPI_CTL[17]) bit is enabled. Note 2: This bit can be cleared by writing 1 to it.
[8] | RXTHIF | RX FIFO Threshold Interrupt Flag (Read Only) 0 = RX valid data counts small or equal than RXTH (SPI_FIFOCTL[27:24]). 1 = RX valid data counts bigger than RXTH. Note: If RXTHIEN(SPI_FIFOCTL[2]) = 1 and RXTHIF = 1, SPI will generate interrupt.
[9] | RXOVIF | Receive FIFO over Run Interrupt Flag 0 = No FIFO over run. 1 = Receive FIFO over run. Note 1: If SPI receives data when RX FIFO is full, this bit will set to 1, and the received data will be dropped. Note 2: This bit will be cleared by writing 1 to it.
[10] | TXTHIF | Transmit FIFO Threshold Interrupt Flag (Read Only) 0 = TX valid data counts bigger than TXTH (SPI_FIFOCTL[31:28]). 1 = TX valid data counts small or equal than TXTH.
[12] | RXTOIF | Receive Time-out Interrupt Flag 0 = There is not timeout event on the received buffer. 1 = Time out event active in RX FIFO is not empty. Refer to Time Out section. Note: This bit will be cleared by writing 1 to it.
[13] | SLVTOIF | Slave Time-out Interrupt Flag If SLVTOIEN (SPI_SSCTL[6]) is set to 1, this bit will be asserted when slave time-out event occur Software can clear this bit by setting RXFBCLR (SPI_FIFOCTL[0]) or writing 1 to clear this bit. 0 = Slave time-out does not occur yet. 1 = Slave time-out has occurred.
[15] | SLVTXSKE | Slave Mode Transmit Skew Buffer Empty Status This bit indicates the empty status of transmit skew buffer which is used in Slave mode.
[19:16] | RXCNT | Receive FIFO Data Counts (Read Only) This bit field indicates the valid data count of receive FIFO buffer.
[23:20] | TXCNT | Transmit FIFO Data Counts (Read Only) This bit field indicates the valid data count of transmit FIFO buffer.
[30] | WKSSIF | Wake-up by Slave Select Interrupt Flag When chip is woken up from Power-down mode by the toggle event on SPI_SS port, this bit is set to 1 This bit can be cleared by writing '1' to it.
[31] | WKCLKIF | Wake-up by SPI Clock Interrupt Flag When chip is woken up from Power-down mode by the toggle event on SPI_CLK port, this bit is set to 1 This bit can be cleared by writing '1' to it.

Definition at line 23394 of file Nano103.h.

## ◆ TX0

SPI_T::TX0

[0x0020] SPI Transmit Data FIFO Register 0

TX0

Offset: 0x20 SPI Transmit Data FIFO Register 0

Bits | Field | Descriptions
[31:0] | TX | Transmit Data Register (Write Only) The Data Transmit Registers hold the data to be transmitted in the next transfer The number of valid bits depends on the setting of transmit bit length field of the SPI_CTL register. For example, if DWIDTH is set to 0x8, the bit SPI_TX[7:0] will be transmitted in next transfer If DWIDTH is set to 0x0, the SPI controller will perform a 32-bit transfer. Note: 1. The SPI_TX1 is used only when TWOBIT bit (SPI_CTL[22]) is set 1 The first channel's transmitted data shall be written into SPI_TX0 and the second channel's transmitted data shall be written into SPI_TX1 in two-bit mode SPI_TX0 shall be written first in TWOBIT mode. In FIFO and two-bit mode, the first written into data in SPI_TX0 is the first channel's transmitted data and the second written data in SPI_TX1 is the second channel's transmitted data. 2. If the SPI controller operates as slave device and FIFO mode is disabled, software must update the transmit data register before setting the GOBUSY bit to 1

Definition at line 23402 of file Nano103.h.

## ◆ TX1

SPI_T::TX1

[0x0024] SPI Transmit Data FIFO Register 1

TX1

Offset: 0x24 SPI Transmit Data FIFO Register 1

Bits | Field | Descriptions
[31:0] | TX | Transmit Data Register (Write Only) The Data Transmit Registers hold the data to be transmitted in the next transfer The number of valid bits depends on the setting of transmit bit length field of the SPI_CTL register. For example, if DWIDTH is set to 0x8, the bit SPI_TX[7:0] will be transmitted in next transfer If DWIDTH is set to 0x0, the SPI controller will perform a 32-bit transfer. Note: 1 The SPI_TX1 is used only when TWOBIT bit (SPI_CTL[22]) is set 1 The first channel's transmitted data shall be written into SPI_TX0 and the second channel's transmitted data shall be written into SPI_TX1 in two-bit mode SPI_TX0 shall be written first in TWOBIT mode. In FIFO and two-bit mode, the first written into data in SPI_TX0 is the first channel's transmitted data and the second written data in SPI_TX1 is the second channel's transmitted data. 2 If the SPI controller operates as slave device and FIFO mode is disabled, software must update the transmit data register before setting the GOBUSY bit to 1

Definition at line 23403 of file Nano103.h.

The documentation for this struct was generated from the following file:

- C:/Users/yachen/workzone/bsp/nano103bsp/Library/Device/Nuvoton/Nano103/Include/Nano103.h