| Nano103 BSP V3.01.002 The Board Support Package for Nano103 Series

Data Fields
RTC_T Struct Reference

`#include <Nano103.h>`

## Data Fields
__IO uint32_t | INIT
__IO uint32_t | RWEN
__IO uint32_t | FREQADJ
__IO uint32_t | TIME
__IO uint32_t | CAL
__IO uint32_t | CLKFMT
__IO uint32_t | WEEKDAY
__IO uint32_t | TALM
__IO uint32_t | CALM
__I uint32_t | LEAPYEAR
__IO uint32_t | INTEN
__IO uint32_t | INTSTS
__IO uint32_t | TICK
__IO uint32_t | TAMSK
__IO uint32_t | CAMSK
__IO uint32_t | SPRCTL
__IO uint32_t | SPR [5]
__IO uint32_t | LXTCTL
__IO uint32_t | LXTOCTL
__IO uint32_t | LXTICTL
__IO uint32_t | TAMPCTL
__IO uint32_t | MISCCTL

## Detailed Description

    @addtogroup RTC Real Time Clock Controller(RTC)
    Memory Mapped Structure for RTC Controller

Definition at line 17868 of file Nano103.h.

## Field Documentation

## ◆ CAL

RTC_T::CAL

[0x0010] RTC Calendar Loading Register

CAL

Offset: 0x10 RTC Calendar Loading Register

Bits | Field | Descriptions
[3:0] | DAY | 1-Day Calendar Digit (0~9)
[5:4] | TENDAY | 10-Day Calendar Digit (0~3)
[11:8] | MON | 1-Month Calendar Digit (0~9)
[12] | TENMON | 10-Month Calendar Digit (0~1)
[19:16] | YEAR | 1-Year Calendar Digit (0~9)
[23:20] | TENYEAR | 10-Year Calendar Digit (0~9)

Definition at line 18623 of file Nano103.h.

## ◆ CALM

RTC_T::CALM

[0x0020] RTC Calendar Alarm Register

CALM

Offset: 0x20 RTC Calendar Alarm Register

Bits | Field | Descriptions
[3:0] | DAY | 1-Day Calendar Digit of Alarm Setting (0~9)
[5:4] | TENDAY | 10-Day Calendar Digit of Alarm Setting (0~3)
[11:8] | MON | 1-Month Calendar Digit of Alarm Setting (0~9)
[12] | TENMON | 10-Month Calendar Digit of Alarm Setting (0~1)
[19:16] | YEAR | 1-Year Calendar Digit of Alarm Setting (0~9)
[23:20] | TENYEAR | 10-Year Calendar Digit of Alarm Setting (0~9)

Definition at line 18627 of file Nano103.h.

## ◆ CAMSK

RTC_T::CAMSK

[0x0038] RTC Calendar Alarm Mask Register

CAMSK

Offset: 0x38 RTC Calendar Alarm Mask Register

Bits | Field | Descriptions
[0] | MDAY | Mask 1-Day Calendar Digit of Alarm Setting (0~9)
[1] | MTENDAY | Mask 10-Day Calendar Digit of Alarm Setting (0~3)
[2] | MMON | Mask 1-Month Calendar Digit of Alarm Setting (0~9)
[3] | MTENMON | Mask 10-Month Calendar Digit of Alarm Setting (0~1)
[4] | MYEAR | Mask 1-Year Calendar Digit of Alarm Setting (0~9)
[5] | MTENYEAR | Mask 10-Year Calendar Digit of Alarm Setting (0~9)

Definition at line 18633 of file Nano103.h.

## ◆ CLKFMT

RTC_T::CLKFMT

[0x0014] RTC Time Scale Selection Register

CLKFMT

Offset: 0x14 RTC Time Scale Selection Register

Bits | Field | Descriptions
[0] | 24HEN | 24-hour / 12-hour Time Scale Selection Indicates that RTC_TIME and RTC_TALM are in 24-hour time scale or 12-hour time scale 0 = 12-hour time scale with AM and PM indication selected. 1 = 24-hour time scale selected.

Definition at line 18624 of file Nano103.h.

## ◆ FREQADJ

RTC_T::FREQADJ

[0x0008] RTC Frequency Compensation Register

FREQADJ

Offset: 0x08 RTC Frequency Compensation Register

Bits | Field | Descriptions
[21:0] | FREQADJ | Frequency Compensation Register FREQADJ = 32768 * 0x200000 / (LXT period). LXT period: the clock period (Hz) of LXT.

Definition at line 18621 of file Nano103.h.

## ◆ INIT

RTC_T::INIT

[0x0000] RTC Initiation Register

INIT

Offset: 0x00 RTC Initiation Register

Bits | Field | Descriptions
[0] | INIT_ACTIVE | RTC Active Status (Read Only) 0 = RTC is at reset state. 1 = RTC is at normal active state.
[31:1] | INIT | RTC Initiation When RTC block is powered on, RTC is at reset state User has to write a number (0x a5eb1357) to INIT to make RTC leaving reset state Once the INIT is written as 0xa5eb1357, the RTC will be in un-reset state permanently. The INIT is a write-only field and read value will be always 0.

Definition at line 18619 of file Nano103.h.

## ◆ INTEN

RTC_T::INTEN

[0x0028] RTC Interrupt Enable Register

INTEN

Offset: 0x28 RTC Interrupt Enable Register

Bits | Field | Descriptions
[0] | ALMIEN | Alarm Interrupt Enable Bit 0 = RTC Alarm interrupt Disabled. 1 = RTC Alarm interrupt Enabled.
[1] | TICKIEN | Time Tick Interrupt Enable Bit 0 = RTC Time Tick interrupt Disabled. 1 = RTC Time Tick interrupt Enabled.
[2] | SNPDIEN | Snoop Detection Interrupt Enable Bit 0 = Snoop detected interrupt Disabled. 1 = Snoop detected interrupt Enabled.

Definition at line 18629 of file Nano103.h.

## ◆ INTSTS

RTC_T::INTSTS

[0x002c] RTC Interrupt Indicator Register

INTSTS

Offset: 0x2C RTC Interrupt Indicator Register

Bits | Field | Descriptions
[0] | ALMIF | RTC Alarm Interrupt Flag When RTC time counters RTC_TIME and RTC_CAL match the alarm setting time registers RTC_TALM and RTC_CALM, this bit will be set to 1 and an interrupt will be generated if RTC Alarm Interrupt enabled ALMIEN (RTC_INTEN[0]) is set to 1 Chip will be waken up if RTC Alarm Interrupt is enabled when chip is at Power-down mode. 0 = Alarm condition is not matched. 1 = Alarm condition is matched. Note: Write 1 to clear this bit.
[1] | TICKIF | RTC Time Tick Interrupt Flag When RTC time tick happened, this bit will be set to 1 and an interrupt will be generated if RTC Tick Interrupt enabled TICKIEN (RTC_INTEN[1]) is set to 1 Chip will also be waken up if RTC Tick Interrupt is enabled and this bit is set to 1 when chip is running at Power-down mode. 0 = Tick condition does not occur. 1 = Tick condition occur. Note: Write 1 to clear to clear this bit.
[2] | SNPDIF | Snoop Detect Interrupt Flag When tamper pin transition event is detected, this bit is set to 1 and an interrupt is generated if Snoop Detection Interrupt enabled SNPDIEN (RTC_INTEN[2]) is set to1 Chip will be waken up from Power-down mode if spare register snooper detect interrupt is enabled. 0 = No snoop event is detected. 1 = Snoop event is detected. Note: Write 1 to clear this bit.

Definition at line 18630 of file Nano103.h.

## ◆ LEAPYEAR

RTC_T::LEAPYEAR

[0x0024] RTC Leap Year Indicator Register

LEAPYEAR

Offset: 0x24 RTC Leap Year Indicator Register

Bits | Field | Descriptions
[0] | LEAPYEAR | Leap Year Indication Register (Read Only) 0 = This year is not a leap year. 1 = This year is leap year.

Definition at line 18628 of file Nano103.h.

## ◆ LXTCTL

RTC_T::LXTCTL

[0x0100] RTC 32.768 kHz Oscillator Control Register

LXTCTL

Offset: 0x100 RTC 32.768 kHz Oscillator Control Register

Bits | Field | Descriptions
[0] | LXT_TYPE | LXT TYPE Selection 0 = Crystal type ( Crystal connect to X32KI with X32KO). 1 = Oscillator type ( LXT source from X32KI PIN , X32KO as GPIO).

Definition at line 18639 of file Nano103.h.

## ◆ LXTICTL

RTC_T::LXTICTL

[0x0108] X32KI Pin Control Register

LXTICTL

Offset: 0x108 X32KI Pin Control Register

Bits | Field | Descriptions
[1:0] | OPMODE | IO Operation Mode 00 = X32KI (PF.7) is input only mode, without pull-up resistor. 01 = X32KI (PF.7) is output push pull mode. 10 = X32KI (PF.7) is open drain mode. 11 = X32KI (PF.7) is input only mode with internal pull up.
[2] | DOUT | IO Output Data 0 = X32KI (PF.7) output low. 1 = X32KI (PF.7) output high.
[3] | CTLSEL | IO Pin State Backup Selection When low speed 32 kHz oscillator is disabled, X32KI (PF.7) pin can be used as GPIO function User can program CTLSEL bit to decide X32KI (PF.7) I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_LXTICTL control register. 0 = X32KI (PF.7) pin I/O function is controlled by GPIO module It becomes floating state when system power is turned off. 1 = X32KI (PF.7) pin I/O function is controlled by VBAT power domain, X32KI (PF.7) pin function and I/O status are controlled by OPMODE[1:0] and DOUT after CTLSEL it set to 1 I/O pin keeps the previous state after system power is turned off. Note:CTLSEL (this bit) will automatically be set by hardware to 1 when system power is off and RTC Active Status = 1.

Definition at line 18641 of file Nano103.h.

## ◆ LXTOCTL

RTC_T::LXTOCTL

[0x0104] X32KO Pin Control Register

LXTOCTL

Offset: 0x104 X32KO Pin Control Register

Bits | Field | Descriptions
[1:0] | OPMODE | GPF0 Operation Mode 00 = X32KO (PF.6) is input only mode, without pull-up resistor. 01 = X32KO (PF.6) is output push pull mode. 10 = X32KO (PF.6) is open drain mode. 11 = X32KO (PF.6) is input only mode with internal pull up.
[2] | DOUT | IO Output Data 0 = X32KO (PF.6) output low. 1 = X32KO (PF.6) output high.
[3] | CTLSEL | IO Pin State Backup Selection When low speed 32 kHz oscillator is disabled, X32KO (PF.6) pin can be used as GPIO function User can program CTLSEL bit to decide X32KO (PF.6) I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_LXTOCTL control register. 0 = X32KO (PF.6) pin I/O function is controlled by GPIO module It becomes floating when system power is turned off. 1 = X32KO (PF.6) pin I/O function is controlled by VBAT power domain, X32KO (PF.6) pin function and I/O status are controlled by OPMODE[1:0] and DOUT after CTLSEL it set to 1 I/O pin keeps the previous state after system power is turned off. Note:CTLSEL (this bit) will automatically be set by hardware to 1 when system power is off and RTC Active Status = 1.

Definition at line 18640 of file Nano103.h.

## ◆ MISCCTL

RTC_T::MISCCTL

[0x01F0] Miscellaneous Control Register

MISCCTL

Offset: 0x1F0 Miscellaneous Control Register

Bits | Field | Descriptions
[13:12] | GAINSEL | LXT Gain Selection 00 = Gain 0. 01 = Gain 1. 10 = Gain 2. 11 = Gain 3.

Definition at line 18646 of file Nano103.h.

## ◆ RWEN

RTC_T::RWEN

[0x0004] RTC Access Enable Register

RWEN

Offset: 0x04 RTC Access Enable Register

Bits | Field | Descriptions
[15:0] | RWEN | RTC Register Access Enable Password (Write Only) Writing 0xA965 to this register will enable RTC access and keep 1024 RTC clock. Writing other value will clear RWENF.
[16] | RWENF | RTC Register Access Enable Flag (Read Only) 0 = RTC register read/write Disabled. 1 = RTC register read/write Enabled. This bit will be set after RTC_RWEN[15:0] register is load a 0xA965, and be cleared automatically after 1024 RTC clock . Note: RWENF will be mask to 0 during RTCBUSY = 1, and first turn on RTCCKEN (CLK_APBCLK[1]) also.
[24] | RTCBUSY | RTC Write Busy Flag 0: RTC write access enable 1: RTC write access disable , RTC under Busy Status. Note: BUSY By Exceed RTC IP Processing Write Counter Capacity ( 6 counts Per 1120 PCLK cycles) .

Definition at line 18620 of file Nano103.h.

## ◆ SPR

RTC_T::SPR

[0x0040] ~ [0x0050] RTC Spare Register 0 ~ 4

SPR

Offset: 0x40 ~ 0x50 RTC Spare Register 0 ~ 4

Bits | Field | Descriptions
[31:0] | SPARE | Spare Register This field is used to store back-up information defined by user. This field will be cleared by hardware automatically once a snooper pin event is detected. Before storing back-up information in to RTC_SPRx register, user should write 0xA965 to RTC_RWEN[15:0] to make sure register read/write enable bit REWNF (RTC_RWEN[16]) is enabled.

Definition at line 18635 of file Nano103.h.

## ◆ SPRCTL

RTC_T::SPRCTL

[0x003c] RTC Spare Functional Control Register

SPRCTL

Offset: 0x3C RTC Spare Functional Control Register

Bits | Field | Descriptions
[0] | SNPDEN | Snoop Detection Enable Bit 0 = TAMPER pin detection is Disabled. 1 = TAMPER pin detection is Enabled.
[1] | SNPTYPE0 | Snoop Detection Level This bit controls TAMPER detect event is rising edge or falling edge. 0 = Rising edge detection. 1 = Falling edge detection.
[2] | SPRRWEN | Spare Register Enable Bit 0 = Spare register is Disabled. 1 = Spare register is Enabled. Note: When spare register is disabled, RTC_SPR0 ~ RTC_SPR4 cannot be accessed Did not change the content of the spare register, but read data all 0.
[5] | SPRCSTS | SPR Clear Flag This bit indicates if the RTC_SPR0 ~RTC_SPR4 content is cleared when specify snoop event is detected. 0 = Spare register content is not cleared. 1 = Spare register content is cleared. Writes 1 to clear this bit.

Definition at line 18634 of file Nano103.h.

## ◆ TALM

RTC_T::TALM

[0x001c] RTC Time Alarm Register

TALM

Offset: 0x1C RTC Time Alarm Register

Bits | Field | Descriptions
[3:0] | SEC | 1-Sec Time Digit of Alarm Setting (0~9)
[6:4] | TENSEC | 10-Sec Time Digit of Alarm Setting (0~5)
[11:8] | MIN | 1-Min Time Digit of Alarm Setting (0~9)
[14:12] | TENMIN | 10-Min Time Digit of Alarm Setting (0~5)
[19:16] | HR | 1-Hour Time Digit of Alarm Setting (0~9)
[21:20] | TENHR | 10-hour Time Digit of Alarm Setting (0~2) When RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication (If RTC_TIME[21] is 1, it indicates PM time message.)the high bit of TENHR (RTC_TIME[21]) means AM/PM indication.

Definition at line 18626 of file Nano103.h.

## ◆ TAMPCTL

RTC_T::TAMPCTL

[0x010c] TAMPER Pin Control Register

TAMPCTL

Offset: 0x10C TAMPER Pin Control Register

Bits | Field | Descriptions
[1:0] | OPMODE | IO Operation Mode 00 = TAMPER (LQFP64:PB.13/LQFP48:PA.9/QFN32:PB.8) is input only mode, without pull-up resistor. 01 = TAMPER (LQFP64:PB.13/LQFP48:PA.9/QFN32:PB.8) is output push pull mode. 10 = TAMPER (LQFP64:PB.13/LQFP48:PA.9/QFN32:PB.8) is open drain mode. 11 = TAMPER (LQFP64:PB.13/LQFP48:PA.9/QFN32:PB.8) is input only mode with internal pull up.
[2] | DOUT | IO Output Data 0 = TAMPER (LQFP64:PB.13/LQFP48:PA.9/QFN32:PB.8) output low. 1 = TAMPER (LQFP64:PB.13/LQFP48:PA.9/QFN32:PB.8) output high.
[3] | CTLSEL | IO Pin State Backup Selection When tamper function is disabled, TAMPER pin can be used as GPIO function User can program CTLSEL bit to decide (LQFP64:PB.13/LQFP48:PA.9/QFN32:PB.8) I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_TAMPCTL control register. 0 =TAMPER (LQFP64:PB.13/LQFP48:PA.9/QFN32:PB.8) I/O function is controlled by GPIO module It becomes floating state when system power is turned off. 1 =TAMPER (LQFP64:PB.13/LQFP48:PA.9/QFN32:PB.8) I/O function is controlled by VBAT power domain LQFP64:PB.13/LQFP48:PA.9/QFN32:PB.8 function and I/O status are controlled by OPMODE[1:0] and DOUT after CTLSEL it set to 1 I/O pin state keeps previous state after system power is turned off. Note:CTLSEL (this bit) will automatically be set by hardware to 1 when system power is off and RTC Active Status = 1.

Definition at line 18642 of file Nano103.h.

## ◆ TAMSK

RTC_T::TAMSK

[0x0034] RTC Time Alarm Mask Register

TAMSK

Offset: 0x34 RTC Time Alarm Mask Register

Bits | Field | Descriptions
[0] | MSEC | Mask 1-Sec Time Digit of Alarm Setting (0~9)
[1] | MTENSEC | Mask 10-Sec Time Digit of Alarm Setting (0~5)
[2] | MMIN | Mask 1-Min Time Digit of Alarm Setting (0~9)
[3] | MTENMIN | Mask 10-Min Time Digit of Alarm Setting (0~5)
[4] | MHR | Mask 1-Hour Time Digit of Alarm Setting (0~9)
[5] | MTENHR | Mask 10-Hour Time Digit of Alarm Setting (0~2)

Definition at line 18632 of file Nano103.h.

## ◆ TICK

RTC_T::TICK

[0x0030] RTC Time Tick Register

TICK

Offset: 0x30 RTC Time Tick Register

Bits | Field | Descriptions
[2:0] | TICK | Time Tick Register These bits are used to select RTC time tick period for Periodic Time Tick Interrupt request. 000 = Time tick is 1 second. 001 = Time tick is 1/2 second. 010 = Time tick is 1/4 second. 011 = Time tick is 1/8 second. 100 = Time tick is 1/16 second. 101 = Time tick is 1/32 second. 110 = Time tick is 1/64 second. 111 = Time tick is 1/128 second. Note: This register can be read back after the RTC register access enable bit RWENF (RTC_RWEN[16]) is active.

Definition at line 18631 of file Nano103.h.

## ◆ TIME

RTC_T::TIME

[0x000c] RTC Time Loading Register

TIME

Offset: 0x0C RTC Time Loading Register

Bits | Field | Descriptions
[3:0] | SEC | 1-Sec Time Digit (0~9)
[6:4] | TENSEC | 10-Sec Time Digit (0~5)
[11:8] | MIN | 1-Min Time Digit (0~9)
[14:12] | TENMIN | 10-Min Time Digit (0~5)
[19:16] | HR | 1-Hour Time Digit (0~9)
[21:20] | TENHR | 10-hour Time Digit (0~2) When RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication (If RTC_TIME[21] is 1, it indicates PM time message.) the high bit of TENHR (RTC_TIME[21]) means AM/PM indication.

Definition at line 18622 of file Nano103.h.

## ◆ WEEKDAY

RTC_T::WEEKDAY

[0x0018] RTC Day of the Week Register

WEEKDAY

Offset: 0x18 RTC Day of the Week Register

Bits | Field | Descriptions
[2:0] | WEEKDAY | Day of the Week Register 000 = Sunday. 001 = Monday. 010 = Tuesday. 011 = Wednesday. 100 = Thursday. 101 = Friday. 110 = Saturday. 111 = Reserved.

Definition at line 18625 of file Nano103.h.

The documentation for this struct was generated from the following file:

- C:/Users/yachen/workzone/bsp/nano103bsp/Library/Device/Nuvoton/Nano103/Include/Nano103.h