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Nano103 BSP
V3.01.002
The Board Support Package for Nano103 Series
|
Modules | |
| Device CMSIS Definitions | |
| NANO103 Peripherals | |
Data Structures | |
| struct | SYS_T |
| #define | SYS_PDID_PDID_Pos (0) |
| #define | SYS_PDID_PDID_Msk (0xfffffffful << SYS_PDID_PDID_Pos) |
| #define | SYS_RSTSTS_PORF_Pos (0) |
| #define | SYS_RSTSTS_PORF_Msk (0x1ul << SYS_RSTSTS_PORF_Pos) |
| #define | SYS_RSTSTS_PINRF_Pos (1) |
| #define | SYS_RSTSTS_PINRF_Msk (0x1ul << SYS_RSTSTS_PINRF_Pos) |
| #define | SYS_RSTSTS_WDTRF_Pos (2) |
| #define | SYS_RSTSTS_WDTRF_Msk (0x1ul << SYS_RSTSTS_WDTRF_Pos) |
| #define | SYS_RSTSTS_LVRF_Pos (3) |
| #define | SYS_RSTSTS_LVRF_Msk (0x1ul << SYS_RSTSTS_LVRF_Pos) |
| #define | SYS_RSTSTS_BODRF_Pos (4) |
| #define | SYS_RSTSTS_BODRF_Msk (0x1ul << SYS_RSTSTS_BODRF_Pos) |
| #define | SYS_RSTSTS_SYSRF_Pos (5) |
| #define | SYS_RSTSTS_SYSRF_Msk (0x1ul << SYS_RSTSTS_SYSRF_Pos) |
| #define | SYS_RSTSTS_CPURF_Pos (7) |
| #define | SYS_RSTSTS_CPURF_Msk (0x1ul << SYS_RSTSTS_CPURF_Pos) |
| #define | SYS_RSTSTS_LOCKRF_Pos (8) |
| #define | SYS_RSTSTS_LOCKRF_Msk (0x1ul << SYS_RSTSTS_LOCKRF_Pos) |
| #define | SYS_IPRST1_CHIPRST_Pos (0) |
| #define | SYS_IPRST1_CHIPRST_Msk (0x1ul << SYS_IPRST1_CHIPRST_Pos) |
| #define | SYS_IPRST1_CPURST_Pos (1) |
| #define | SYS_IPRST1_CPURST_Msk (0x1ul << SYS_IPRST1_CPURST_Pos) |
| #define | SYS_IPRST1_PDMARST_Pos (2) |
| #define | SYS_IPRST1_PDMARST_Msk (0x1ul << SYS_IPRST1_PDMARST_Pos) |
| #define | SYS_IPRST2_GPIORST_Pos (1) |
| #define | SYS_IPRST2_GPIORST_Msk (0x1ul << SYS_IPRST2_GPIORST_Pos) |
| #define | SYS_IPRST2_TMR0RST_Pos (2) |
| #define | SYS_IPRST2_TMR0RST_Msk (0x1ul << SYS_IPRST2_TMR0RST_Pos) |
| #define | SYS_IPRST2_TMR1RST_Pos (3) |
| #define | SYS_IPRST2_TMR1RST_Msk (0x1ul << SYS_IPRST2_TMR1RST_Pos) |
| #define | SYS_IPRST2_TMR2RST_Pos (4) |
| #define | SYS_IPRST2_TMR2RST_Msk (0x1ul << SYS_IPRST2_TMR2RST_Pos) |
| #define | SYS_IPRST2_TMR3RST_Pos (5) |
| #define | SYS_IPRST2_TMR3RST_Msk (0x1ul << SYS_IPRST2_TMR3RST_Pos) |
| #define | SYS_IPRST2_I2C0RST_Pos (8) |
| #define | SYS_IPRST2_I2C0RST_Msk (0x1ul << SYS_IPRST2_I2C0RST_Pos) |
| #define | SYS_IPRST2_I2C1RST_Pos (9) |
| #define | SYS_IPRST2_I2C1RST_Msk (0x1ul << SYS_IPRST2_I2C1RST_Pos) |
| #define | SYS_IPRST2_SPI0RST_Pos (12) |
| #define | SYS_IPRST2_SPI0RST_Msk (0x1ul << SYS_IPRST2_SPI0RST_Pos) |
| #define | SYS_IPRST2_SPI1RST_Pos (13) |
| #define | SYS_IPRST2_SPI1RST_Msk (0x1ul << SYS_IPRST2_SPI1RST_Pos) |
| #define | SYS_IPRST2_SPI2RST_Pos (14) |
| #define | SYS_IPRST2_SPI2RST_Msk (0x1ul << SYS_IPRST2_SPI2RST_Pos) |
| #define | SYS_IPRST2_SPI3RST_Pos (15) |
| #define | SYS_IPRST2_SPI3RST_Msk (0x1ul << SYS_IPRST2_SPI3RST_Pos) |
| #define | SYS_IPRST2_UART0RST_Pos (16) |
| #define | SYS_IPRST2_UART0RST_Msk (0x1ul << SYS_IPRST2_UART0RST_Pos) |
| #define | SYS_IPRST2_UART1RST_Pos (17) |
| #define | SYS_IPRST2_UART1RST_Msk (0x1ul << SYS_IPRST2_UART1RST_Pos) |
| #define | SYS_IPRST2_PWM0RST_Pos (20) |
| #define | SYS_IPRST2_PWM0RST_Msk (0x1ul << SYS_IPRST2_PWM0RST_Pos) |
| #define | SYS_IPRST2_ACMP0RST_Pos (22) |
| #define | SYS_IPRST2_ACMP0RST_Msk (0x1ul << SYS_IPRST2_ACMP0RST_Pos) |
| #define | SYS_IPRST2_ADCRST_Pos (28) |
| #define | SYS_IPRST2_ADCRST_Msk (0x1ul << SYS_IPRST2_ADCRST_Pos) |
| #define | SYS_IPRST2_SC0RST_Pos (30) |
| #define | SYS_IPRST2_SC0RST_Msk (0x1ul << SYS_IPRST2_SC0RST_Pos) |
| #define | SYS_IPRST2_SC1RST_Pos (31) |
| #define | SYS_IPRST2_SC1RST_Msk (0x1ul << SYS_IPRST2_SC1RST_Pos) |
| #define | SYS_MISCCTL_POR33DIS_Pos (6) |
| #define | SYS_MISCCTL_POR33DIS_Msk (0x1ul << SYS_MISCCTL_POR33DIS_Pos) |
| #define | SYS_MISCCTL_POR18DIS_Pos (7) |
| #define | SYS_MISCCTL_POR18DIS_Msk (0x1ul << SYS_MISCCTL_POR18DIS_Pos) |
| #define | SYS_TEMPCTL_VTEMPEN_Pos (0) |
| #define | SYS_TEMPCTL_VTEMPEN_Msk (0x1ul << SYS_TEMPCTL_VTEMPEN_Pos) |
| #define | SYS_RCCFCTL_HIRC0FEN_Pos (0) |
| #define | SYS_RCCFCTL_HIRC0FEN_Msk (0x1ul << SYS_RCCFCTL_HIRC0FEN_Pos) |
| #define | SYS_RCCFCTL_HIRC1FEN_Pos (1) |
| #define | SYS_RCCFCTL_HIRC1FEN_Msk (0x1ul << SYS_RCCFCTL_HIRC1FEN_Pos) |
| #define | SYS_RCCFCTL_MRCFEN_Pos (2) |
| #define | SYS_RCCFCTL_MRCFEN_Msk (0x1ul << SYS_RCCFCTL_MRCFEN_Pos) |
| #define | SYS_GPA_MFPL_PA0MFP_Pos (0) |
| #define | SYS_GPA_MFPL_PA0MFP_Msk (0xful << SYS_GPA_MFPL_PA0MFP_Pos) |
| #define | SYS_GPA_MFPL_PA1MFP_Pos (4) |
| #define | SYS_GPA_MFPL_PA1MFP_Msk (0xful << SYS_GPA_MFPL_PA1MFP_Pos) |
| #define | SYS_GPA_MFPL_PA2MFP_Pos (8) |
| #define | SYS_GPA_MFPL_PA2MFP_Msk (0xful << SYS_GPA_MFPL_PA2MFP_Pos) |
| #define | SYS_GPA_MFPL_PA3MFP_Pos (12) |
| #define | SYS_GPA_MFPL_PA3MFP_Msk (0xful << SYS_GPA_MFPL_PA3MFP_Pos) |
| #define | SYS_GPA_MFPL_PA4MFP_Pos (16) |
| #define | SYS_GPA_MFPL_PA4MFP_Msk (0xful << SYS_GPA_MFPL_PA4MFP_Pos) |
| #define | SYS_GPA_MFPL_PA5MFP_Pos (20) |
| #define | SYS_GPA_MFPL_PA5MFP_Msk (0xful << SYS_GPA_MFPL_PA5MFP_Pos) |
| #define | SYS_GPA_MFPL_PA6MFP_Pos (24) |
| #define | SYS_GPA_MFPL_PA6MFP_Msk (0xful << SYS_GPA_MFPL_PA6MFP_Pos) |
| #define | SYS_GPA_MFPH_PA8MFP_Pos (0) |
| #define | SYS_GPA_MFPH_PA8MFP_Msk (0xful << SYS_GPA_MFPH_PA8MFP_Pos) |
| #define | SYS_GPA_MFPH_PA9MFP_Pos (4) |
| #define | SYS_GPA_MFPH_PA9MFP_Msk (0xful << SYS_GPA_MFPH_PA9MFP_Pos) |
| #define | SYS_GPA_MFPH_PA10MFP_Pos (8) |
| #define | SYS_GPA_MFPH_PA10MFP_Msk (0xful << SYS_GPA_MFPH_PA10MFP_Pos) |
| #define | SYS_GPA_MFPH_PA11MFP_Pos (12) |
| #define | SYS_GPA_MFPH_PA11MFP_Msk (0xful << SYS_GPA_MFPH_PA11MFP_Pos) |
| #define | SYS_GPA_MFPH_PA12MFP_Pos (16) |
| #define | SYS_GPA_MFPH_PA12MFP_Msk (0xful << SYS_GPA_MFPH_PA12MFP_Pos) |
| #define | SYS_GPA_MFPH_PA13MFP_Pos (20) |
| #define | SYS_GPA_MFPH_PA13MFP_Msk (0xful << SYS_GPA_MFPH_PA13MFP_Pos) |
| #define | SYS_GPA_MFPH_PA14MFP_Pos (24) |
| #define | SYS_GPA_MFPH_PA14MFP_Msk (0xful << SYS_GPA_MFPH_PA14MFP_Pos) |
| #define | SYS_GPA_MFPH_PA15MFP_Pos (28) |
| #define | SYS_GPA_MFPH_PA15MFP_Msk (0xful << SYS_GPA_MFPH_PA15MFP_Pos) |
| #define | SYS_GPB_MFPL_PB0MFP_Pos (0) |
| #define | SYS_GPB_MFPL_PB0MFP_Msk (0xful << SYS_GPB_MFPL_PB0MFP_Pos) |
| #define | SYS_GPB_MFPL_PB1MFP_Pos (4) |
| #define | SYS_GPB_MFPL_PB1MFP_Msk (0xful << SYS_GPB_MFPL_PB1MFP_Pos) |
| #define | SYS_GPB_MFPL_PB2MFP_Pos (8) |
| #define | SYS_GPB_MFPL_PB2MFP_Msk (0xful << SYS_GPB_MFPL_PB2MFP_Pos) |
| #define | SYS_GPB_MFPL_PB3MFP_Pos (12) |
| #define | SYS_GPB_MFPL_PB3MFP_Msk (0xful << SYS_GPB_MFPL_PB3MFP_Pos) |
| #define | SYS_GPB_MFPL_PB4MFP_Pos (16) |
| #define | SYS_GPB_MFPL_PB4MFP_Msk (0xful << SYS_GPB_MFPL_PB4MFP_Pos) |
| #define | SYS_GPB_MFPL_PB5MFP_Pos (20) |
| #define | SYS_GPB_MFPL_PB5MFP_Msk (0xful << SYS_GPB_MFPL_PB5MFP_Pos) |
| #define | SYS_GPB_MFPL_PB6MFP_Pos (24) |
| #define | SYS_GPB_MFPL_PB6MFP_Msk (0xful << SYS_GPB_MFPL_PB6MFP_Pos) |
| #define | SYS_GPB_MFPL_PB7MFP_Pos (28) |
| #define | SYS_GPB_MFPL_PB7MFP_Msk (0xful << SYS_GPB_MFPL_PB7MFP_Pos) |
| #define | SYS_GPB_MFPH_PB8MFP_Pos (0) |
| #define | SYS_GPB_MFPH_PB8MFP_Msk (0xful << SYS_GPB_MFPH_PB8MFP_Pos) |
| #define | SYS_GPB_MFPH_PB9MFP_Pos (4) |
| #define | SYS_GPB_MFPH_PB9MFP_Msk (0xful << SYS_GPB_MFPH_PB9MFP_Pos) |
| #define | SYS_GPB_MFPH_PB10MFP_Pos (8) |
| #define | SYS_GPB_MFPH_PB10MFP_Msk (0xful << SYS_GPB_MFPH_PB10MFP_Pos) |
| #define | SYS_GPB_MFPH_PB11MFP_Pos (12) |
| #define | SYS_GPB_MFPH_PB11MFP_Msk (0xful << SYS_GPB_MFPH_PB11MFP_Pos) |
| #define | SYS_GPB_MFPH_PB13MFP_Pos (20) |
| #define | SYS_GPB_MFPH_PB13MFP_Msk (0xful << SYS_GPB_MFPH_PB13MFP_Pos) |
| #define | SYS_GPB_MFPH_PB14MFP_Pos (24) |
| #define | SYS_GPB_MFPH_PB14MFP_Msk (0xful << SYS_GPB_MFPH_PB14MFP_Pos) |
| #define | SYS_GPB_MFPH_PB15MFP_Pos (28) |
| #define | SYS_GPB_MFPH_PB15MFP_Msk (0xful << SYS_GPB_MFPH_PB15MFP_Pos) |
| #define | SYS_GPC_MFPL_PC0MFP_Pos (0) |
| #define | SYS_GPC_MFPL_PC0MFP_Msk (0xful << SYS_GPC_MFPL_PC0MFP_Pos) |
| #define | SYS_GPC_MFPL_PC1MFP_Pos (4) |
| #define | SYS_GPC_MFPL_PC1MFP_Msk (0xful << SYS_GPC_MFPL_PC1MFP_Pos) |
| #define | SYS_GPC_MFPL_PC2MFP_Pos (8) |
| #define | SYS_GPC_MFPL_PC2MFP_Msk (0xful << SYS_GPC_MFPL_PC2MFP_Pos) |
| #define | SYS_GPC_MFPL_PC3MFP_Pos (12) |
| #define | SYS_GPC_MFPL_PC3MFP_Msk (0xful << SYS_GPC_MFPL_PC3MFP_Pos) |
| #define | SYS_GPC_MFPL_PC6MFP_Pos (24) |
| #define | SYS_GPC_MFPL_PC6MFP_Msk (0xful << SYS_GPC_MFPL_PC6MFP_Pos) |
| #define | SYS_GPC_MFPL_PC7MFP_Pos (28) |
| #define | SYS_GPC_MFPL_PC7MFP_Msk (0xful << SYS_GPC_MFPL_PC7MFP_Pos) |
| #define | SYS_GPC_MFPH_PC8MFP_Pos (0) |
| #define | SYS_GPC_MFPH_PC8MFP_Msk (0xful << SYS_GPC_MFPH_PC8MFP_Pos) |
| #define | SYS_GPC_MFPH_PC9MFP_Pos (4) |
| #define | SYS_GPC_MFPH_PC9MFP_Msk (0xful << SYS_GPC_MFPH_PC9MFP_Pos) |
| #define | SYS_GPC_MFPH_PC10MFP_Pos (8) |
| #define | SYS_GPC_MFPH_PC10MFP_Msk (0xful << SYS_GPC_MFPH_PC10MFP_Pos) |
| #define | SYS_GPC_MFPH_PC11MFP_Pos (12) |
| #define | SYS_GPC_MFPH_PC11MFP_Msk (0xful << SYS_GPC_MFPH_PC11MFP_Pos) |
| #define | SYS_GPC_MFPH_PC14MFP_Pos (24) |
| #define | SYS_GPC_MFPH_PC14MFP_Msk (0xful << SYS_GPC_MFPH_PC14MFP_Pos) |
| #define | SYS_GPC_MFPH_PC15MFP_Pos (28) |
| #define | SYS_GPC_MFPH_PC15MFP_Msk (0xful << SYS_GPC_MFPH_PC15MFP_Pos) |
| #define | SYS_GPD_MFPL_PD6MFP_Pos (24) |
| #define | SYS_GPD_MFPL_PD6MFP_Msk (0xful << SYS_GPD_MFPL_PD6MFP_Pos) |
| #define | SYS_GPD_MFPL_PD7MFP_Pos (28) |
| #define | SYS_GPD_MFPL_PD7MFP_Msk (0xful << SYS_GPD_MFPL_PD7MFP_Pos) |
| #define | SYS_GPD_MFPH_PD14MFP_Pos (24) |
| #define | SYS_GPD_MFPH_PD14MFP_Msk (0xful << SYS_GPD_MFPH_PD14MFP_Pos) |
| #define | SYS_GPD_MFPH_PD15MFP_Pos (28) |
| #define | SYS_GPD_MFPH_PD15MFP_Msk (0x7ul << SYS_GPD_MFPH_PD15MFP_Pos) |
| #define | SYS_GPE_MFPL_PE5MFP_Pos (20) |
| #define | SYS_GPE_MFPL_PE5MFP_Msk (0xful << SYS_GPE_MFPL_PE5MFP_Pos) |
| #define | SYS_GPF_MFPL_PF0MFP_Pos (0) |
| #define | SYS_GPF_MFPL_PF0MFP_Msk (0xful << SYS_GPF_MFPL_PF0MFP_Pos) |
| #define | SYS_GPF_MFPL_PF1MFP_Pos (4) |
| #define | SYS_GPF_MFPL_PF1MFP_Msk (0xful << SYS_GPF_MFPL_PF1MFP_Pos) |
| #define | SYS_GPF_MFPL_PF2MFP_Pos (8) |
| #define | SYS_GPF_MFPL_PF2MFP_Msk (0xful << SYS_GPF_MFPL_PF2MFP_Pos) |
| #define | SYS_GPF_MFPL_PF3MFP_Pos (12) |
| #define | SYS_GPF_MFPL_PF3MFP_Msk (0xful << SYS_GPF_MFPL_PF3MFP_Pos) |
| #define | SYS_GPF_MFPL_PF6MFP_Pos (24) |
| #define | SYS_GPF_MFPL_PF6MFP_Msk (0xful << SYS_GPF_MFPL_PF6MFP_Pos) |
| #define | SYS_GPF_MFPL_PF7MFP_Pos (28) |
| #define | SYS_GPF_MFPL_PF7MFP_Msk (0xful << SYS_GPF_MFPL_PF7MFP_Pos) |
| #define | SYS_PORCTL_POROFF_Pos (0) |
| #define | SYS_PORCTL_POROFF_Msk (0xfffful << SYS_PORCTL_POROFF_Pos) |
| #define | SYS_BODCTL_BODEN_Pos (0) |
| #define | SYS_BODCTL_BODEN_Msk (0x1ul << SYS_BODCTL_BODEN_Pos) |
| #define | SYS_BODCTL_BODIE_Pos (2) |
| #define | SYS_BODCTL_BODIE_Msk (0x1ul << SYS_BODCTL_BODIE_Pos) |
| #define | SYS_BODCTL_BODREN_Pos (3) |
| #define | SYS_BODCTL_BODREN_Msk (0x1ul << SYS_BODCTL_BODREN_Pos) |
| #define | SYS_BODCTL_BODIF_Pos (4) |
| #define | SYS_BODCTL_BODIF_Msk (0x1ul << SYS_BODCTL_BODIF_Pos) |
| #define | SYS_BODCTL_BODOUT_Pos (6) |
| #define | SYS_BODCTL_BODOUT_Msk (0x1ul << SYS_BODCTL_BODOUT_Pos) |
| #define | SYS_BODCTL_LVREN_Pos (7) |
| #define | SYS_BODCTL_LVREN_Msk (0x1ul << SYS_BODCTL_LVREN_Pos) |
| #define | SYS_BODCTL_LPBODEN_Pos (8) |
| #define | SYS_BODCTL_LPBODEN_Msk (0x1ul << SYS_BODCTL_LPBODEN_Pos) |
| #define | SYS_BODCTL_LPBODVL_Pos (9) |
| #define | SYS_BODCTL_LPBODVL_Msk (0x1ul << SYS_BODCTL_LPBODVL_Pos) |
| #define | SYS_BODCTL_LPBODIE_Pos (10) |
| #define | SYS_BODCTL_LPBODIE_Msk (0x1ul << SYS_BODCTL_LPBODIE_Pos) |
| #define | SYS_BODCTL_LPBODREN_Pos (11) |
| #define | SYS_BODCTL_LPBODREN_Msk (0x1ul << SYS_BODCTL_LPBODREN_Pos) |
| #define | SYS_BODCTL_BODVL_Pos (12) |
| #define | SYS_BODCTL_BODVL_Msk (0xful << SYS_BODCTL_BODVL_Pos) |
| #define | SYS_BODCTL_LPBOD20TRIM_Pos (16) |
| #define | SYS_BODCTL_LPBOD20TRIM_Msk (0xful << SYS_BODCTL_LPBOD20TRIM_Pos) |
| #define | SYS_BODCTL_LPBOD25TRIM_Pos (20) |
| #define | SYS_BODCTL_LPBOD25TRIM_Msk (0xful << SYS_BODCTL_LPBOD25TRIM_Pos) |
| #define | SYS_BODCTL_BODDGSEL_Pos (24) |
| #define | SYS_BODCTL_BODDGSEL_Msk (0x7ul << SYS_BODCTL_BODDGSEL_Pos) |
| #define | SYS_BODCTL_LVRDGSEL_Pos (28) |
| #define | SYS_BODCTL_LVRDGSEL_Msk (0x7ul << SYS_BODCTL_LVRDGSEL_Pos) |
| #define | SYS_IVREFCTL_BGPEN_Pos (0) |
| #define | SYS_IVREFCTL_BGPEN_Msk (0x1ul << SYS_IVREFCTL_BGPEN_Pos) |
| #define | SYS_IVREFCTL_REGEN_Pos (1) |
| #define | SYS_IVREFCTL_REGEN_Msk (0x1ul << SYS_IVREFCTL_REGEN_Pos) |
| #define | SYS_IVREFCTL_SEL25_Pos (2) |
| #define | SYS_IVREFCTL_SEL25_Msk (0x3ul << SYS_IVREFCTL_SEL25_Pos) |
| #define | SYS_IVREFCTL_EXTMODE_Pos (4) |
| #define | SYS_IVREFCTL_EXTMODE_Msk (0x1ul << SYS_IVREFCTL_EXTMODE_Pos) |
| #define | SYS_IVREFCTL_VREFTRIM_Pos (8) |
| #define | SYS_IVREFCTL_VREFTRIM_Msk (0xful << SYS_IVREFCTL_VREFTRIM_Pos) |
| #define | SYS_LDOCTL_FASTWK_Pos (1) |
| #define | SYS_LDOCTL_FASTWK_Msk (0x1ul << SYS_LDOCTL_FASTWK_Pos) |
| #define | SYS_LDOCTL_LDOLVL_Pos (2) |
| #define | SYS_LDOCTL_LDOLVL_Msk (0x3ul << SYS_LDOCTL_LDOLVL_Pos) |
| #define | SYS_LDOCTL_LPRMEN_Pos (4) |
| #define | SYS_LDOCTL_LPRMEN_Msk (0x1ul << SYS_LDOCTL_LPRMEN_Pos) |
| #define | SYS_LDOCTL_FMCLVEN_Pos (5) |
| #define | SYS_LDOCTL_FMCLVEN_Msk (0x1ul << SYS_LDOCTL_FMCLVEN_Pos) |
| #define | SYS_BATDIVCTL_BATDIV2EN_Pos (0) |
| #define | SYS_BATDIVCTL_BATDIV2EN_Msk (0x1ul << SYS_BATDIVCTL_BATDIV2EN_Pos) |
| #define | SYS_WKSTS_ACMPWK_Pos (0) |
| #define | SYS_WKSTS_ACMPWK_Msk (0x1ul << SYS_WKSTS_ACMPWK_Pos) |
| #define | SYS_WKSTS_I2C1WK_Pos (1) |
| #define | SYS_WKSTS_I2C1WK_Msk (0x1ul << SYS_WKSTS_I2C1WK_Pos) |
| #define | SYS_WKSTS_I2C0WK_Pos (2) |
| #define | SYS_WKSTS_I2C0WK_Msk (0x1ul << SYS_WKSTS_I2C0WK_Pos) |
| #define | SYS_WKSTS_TMR3WK_Pos (3) |
| #define | SYS_WKSTS_TMR3WK_Msk (0x1ul << SYS_WKSTS_TMR3WK_Pos) |
| #define | SYS_WKSTS_TMR2WK_Pos (4) |
| #define | SYS_WKSTS_TMR2WK_Msk (0x1ul << SYS_WKSTS_TMR2WK_Pos) |
| #define | SYS_WKSTS_TMR1WK_Pos (5) |
| #define | SYS_WKSTS_TMR1WK_Msk (0x1ul << SYS_WKSTS_TMR1WK_Pos) |
| #define | SYS_WKSTS_TMR0WK_Pos (6) |
| #define | SYS_WKSTS_TMR0WK_Msk (0x1ul << SYS_WKSTS_TMR0WK_Pos) |
| #define | SYS_WKSTS_WDTWK_Pos (7) |
| #define | SYS_WKSTS_WDTWK_Msk (0x1ul << SYS_WKSTS_WDTWK_Pos) |
| #define | SYS_WKSTS_BODWK_Pos (8) |
| #define | SYS_WKSTS_BODWK_Msk (0x1ul << SYS_WKSTS_BODWK_Pos) |
| #define | SYS_WKSTS_SPI3WK_Pos (9) |
| #define | SYS_WKSTS_SPI3WK_Msk (0x1ul << SYS_WKSTS_SPI3WK_Pos) |
| #define | SYS_WKSTS_SPI2WK_Pos (10) |
| #define | SYS_WKSTS_SPI2WK_Msk (0x1ul << SYS_WKSTS_SPI2WK_Pos) |
| #define | SYS_WKSTS_SPI1WK_Pos (11) |
| #define | SYS_WKSTS_SPI1WK_Msk (0x1ul << SYS_WKSTS_SPI1WK_Pos) |
| #define | SYS_WKSTS_SPI0WK_Pos (12) |
| #define | SYS_WKSTS_SPI0WK_Msk (0x1ul << SYS_WKSTS_SPI0WK_Pos) |
| #define | SYS_WKSTS_UART1WK_Pos (13) |
| #define | SYS_WKSTS_UART1WK_Msk (0x1ul << SYS_WKSTS_UART1WK_Pos) |
| #define | SYS_WKSTS_UART0WK_Pos (14) |
| #define | SYS_WKSTS_UART0WK_Msk (0x1ul << SYS_WKSTS_UART0WK_Pos) |
| #define | SYS_WKSTS_RTCWK_Pos (15) |
| #define | SYS_WKSTS_RTCWK_Msk (0x1ul << SYS_WKSTS_RTCWK_Pos) |
| #define | SYS_WKSTS_GPIOWK_Pos (16) |
| #define | SYS_WKSTS_GPIOWK_Msk (0x1ul << SYS_WKSTS_GPIOWK_Pos) |
| #define | SYS_IRC0TCTL_FREQSEL_Pos (0) |
| #define | SYS_IRC0TCTL_FREQSEL_Msk (0x7ul << SYS_IRC0TCTL_FREQSEL_Pos) |
| #define | SYS_IRC0TCTL_LOOPSEL_Pos (4) |
| #define | SYS_IRC0TCTL_LOOPSEL_Msk (0x3ul << SYS_IRC0TCTL_LOOPSEL_Pos) |
| #define | SYS_IRC0TCTL_RETRYCNT_Pos (6) |
| #define | SYS_IRC0TCTL_RETRYCNT_Msk (0x3ul << SYS_IRC0TCTL_RETRYCNT_Pos) |
| #define | SYS_IRC0TCTL_CESTOPEN_Pos (8) |
| #define | SYS_IRC0TCTL_CESTOPEN_Msk (0x1ul << SYS_IRC0TCTL_CESTOPEN_Pos) |
| #define | SYS_IRC0TIEN_TFAILIEN_Pos (1) |
| #define | SYS_IRC0TIEN_TFAILIEN_Msk (0x1ul << SYS_IRC0TIEN_TFAILIEN_Pos) |
| #define | SYS_IRC0TIEN_CLKEIEN_Pos (2) |
| #define | SYS_IRC0TIEN_CLKEIEN_Msk (0x1ul << SYS_IRC0TIEN_CLKEIEN_Pos) |
| #define | SYS_IRC0TISTS_FREQLOCK_Pos (0) |
| #define | SYS_IRC0TISTS_FREQLOCK_Msk (0x1ul << SYS_IRC0TISTS_FREQLOCK_Pos) |
| #define | SYS_IRC0TISTS_TFAILIF_Pos (1) |
| #define | SYS_IRC0TISTS_TFAILIF_Msk (0x1ul << SYS_IRC0TISTS_TFAILIF_Pos) |
| #define | SYS_IRC0TISTS_CLKERRIF_Pos (2) |
| #define | SYS_IRC0TISTS_CLKERRIF_Msk (0x1ul << SYS_IRC0TISTS_CLKERRIF_Pos) |
| #define | SYS_IRC1TCTL_FREQSEL_Pos (0) |
| #define | SYS_IRC1TCTL_FREQSEL_Msk (0x3ul << SYS_IRC1TCTL_FREQSEL_Pos) |
| #define | SYS_IRC1TCTL_LOOPSEL_Pos (4) |
| #define | SYS_IRC1TCTL_LOOPSEL_Msk (0x3ul << SYS_IRC1TCTL_LOOPSEL_Pos) |
| #define | SYS_IRC1TCTL_RETRYCNT_Pos (6) |
| #define | SYS_IRC1TCTL_RETRYCNT_Msk (0x3ul << SYS_IRC1TCTL_RETRYCNT_Pos) |
| #define | SYS_IRC1TCTL_CESTOPEN_Pos (8) |
| #define | SYS_IRC1TCTL_CESTOPEN_Msk (0x1ul << SYS_IRC1TCTL_CESTOPEN_Pos) |
| #define | SYS_IRC1TIEN_TFAILIEN_Pos (1) |
| #define | SYS_IRC1TIEN_TFAILIEN_Msk (0x1ul << SYS_IRC1TIEN_TFAILIEN_Pos) |
| #define | SYS_IRC1TIEN_CLKEIEN_Pos (2) |
| #define | SYS_IRC1TIEN_CLKEIEN_Msk (0x1ul << SYS_IRC1TIEN_CLKEIEN_Pos) |
| #define | SYS_IRC1TISTS_FREQLOCK_Pos (0) |
| #define | SYS_IRC1TISTS_FREQLOCK_Msk (0x1ul << SYS_IRC1TISTS_FREQLOCK_Pos) |
| #define | SYS_IRC1TISTS_TFAILIF_Pos (1) |
| #define | SYS_IRC1TISTS_TFAILIF_Msk (0x1ul << SYS_IRC1TISTS_TFAILIF_Pos) |
| #define | SYS_IRC1TISTS_CLKERRIF_Pos (2) |
| #define | SYS_IRC1TISTS_CLKERRIF_Msk (0x1ul << SYS_IRC1TISTS_CLKERRIF_Pos) |
| #define | SYS_MIRCTCTL_FREQSEL_Pos (0) |
| #define | SYS_MIRCTCTL_FREQSEL_Msk (0x3ul << SYS_MIRCTCTL_FREQSEL_Pos) |
| #define | SYS_MIRCTCTL_LOOPSEL_Pos (4) |
| #define | SYS_MIRCTCTL_LOOPSEL_Msk (0x3ul << SYS_MIRCTCTL_LOOPSEL_Pos) |
| #define | SYS_MIRCTCTL_RETRYCNT_Pos (6) |
| #define | SYS_MIRCTCTL_RETRYCNT_Msk (0x3ul << SYS_MIRCTCTL_RETRYCNT_Pos) |
| #define | SYS_MIRCTCTL_CESTOPEN_Pos (8) |
| #define | SYS_MIRCTCTL_CESTOPEN_Msk (0x1ul << SYS_MIRCTCTL_CESTOPEN_Pos) |
| #define | SYS_MIRCTIEN_TFAILIEN_Pos (1) |
| #define | SYS_MIRCTIEN_TFAILIEN_Msk (0x1ul << SYS_MIRCTIEN_TFAILIEN_Pos) |
| #define | SYS_MIRCTIEN_CLKEIEN_Pos (2) |
| #define | SYS_MIRCTIEN_CLKEIEN_Msk (0x1ul << SYS_MIRCTIEN_CLKEIEN_Pos) |
| #define | SYS_MIRCTISTS_FREQLOCK_Pos (0) |
| #define | SYS_MIRCTISTS_FREQLOCK_Msk (0x1ul << SYS_MIRCTISTS_FREQLOCK_Pos) |
| #define | SYS_MIRCTISTS_TFAILIF_Pos (1) |
| #define | SYS_MIRCTISTS_TFAILIF_Msk (0x1ul << SYS_MIRCTISTS_TFAILIF_Pos) |
| #define | SYS_MIRCTISTS_CLKERRIF_Pos (2) |
| #define | SYS_MIRCTISTS_CLKERRIF_Msk (0x1ul << SYS_MIRCTISTS_CLKERRIF_Pos) |
| #define | SYS_REGLCTL_REGLCTL_Pos (0) |
| #define | SYS_REGLCTL_REGLCTL_Msk (0x1ul << SYS_REGLCTL_REGLCTL_Pos) |
| #define | SYS_RPDBCLK_RSTPDBCLK_Pos (6) |
| #define | SYS_RPDBCLK_RSTPDBCLK_Msk (0x1ul << SYS_RPDBCLK_RSTPDBCLK_Pos) |
This file defines all structures and symbols for NANO103:
| #define SYS_BATDIVCTL_BATDIV2EN_Msk (0x1ul << SYS_BATDIVCTL_BATDIV2EN_Pos) |
SYS_T::BATDIVCTL: BATDIV2EN Mask
| #define SYS_BATDIVCTL_BATDIV2EN_Pos (0) |
SYS_T::BATDIVCTL: BATDIV2EN Position
| #define SYS_BODCTL_BODDGSEL_Msk (0x7ul << SYS_BODCTL_BODDGSEL_Pos) |
SYS_T::BODCTL: BODDGSEL Mask
| #define SYS_BODCTL_BODDGSEL_Pos (24) |
SYS_T::BODCTL: BODDGSEL Position
| #define SYS_BODCTL_BODEN_Msk (0x1ul << SYS_BODCTL_BODEN_Pos) |
SYS_T::BODCTL: BODEN Mask
| #define SYS_BODCTL_BODEN_Pos (0) |
SYS_T::BODCTL: BODEN Position
| #define SYS_BODCTL_BODIE_Msk (0x1ul << SYS_BODCTL_BODIE_Pos) |
SYS_T::BODCTL: BODIE Mask
| #define SYS_BODCTL_BODIE_Pos (2) |
SYS_T::BODCTL: BODIE Position
| #define SYS_BODCTL_BODIF_Msk (0x1ul << SYS_BODCTL_BODIF_Pos) |
SYS_T::BODCTL: BODIF Mask
| #define SYS_BODCTL_BODIF_Pos (4) |
SYS_T::BODCTL: BODIF Position
| #define SYS_BODCTL_BODOUT_Msk (0x1ul << SYS_BODCTL_BODOUT_Pos) |
SYS_T::BODCTL: BODOUT Mask
| #define SYS_BODCTL_BODOUT_Pos (6) |
SYS_T::BODCTL: BODOUT Position
| #define SYS_BODCTL_BODREN_Msk (0x1ul << SYS_BODCTL_BODREN_Pos) |
SYS_T::BODCTL: BODREN Mask
| #define SYS_BODCTL_BODREN_Pos (3) |
SYS_T::BODCTL: BODREN Position
| #define SYS_BODCTL_BODVL_Msk (0xful << SYS_BODCTL_BODVL_Pos) |
SYS_T::BODCTL: BODVL Mask
| #define SYS_BODCTL_BODVL_Pos (12) |
SYS_T::BODCTL: BODVL Position
| #define SYS_BODCTL_LPBOD20TRIM_Msk (0xful << SYS_BODCTL_LPBOD20TRIM_Pos) |
SYS_T::BODCTL: LPBOD20TRIM Mask
| #define SYS_BODCTL_LPBOD20TRIM_Pos (16) |
SYS_T::BODCTL: LPBOD20TRIM Position
| #define SYS_BODCTL_LPBOD25TRIM_Msk (0xful << SYS_BODCTL_LPBOD25TRIM_Pos) |
SYS_T::BODCTL: LPBOD25TRIM Mask
| #define SYS_BODCTL_LPBOD25TRIM_Pos (20) |
SYS_T::BODCTL: LPBOD25TRIM Position
| #define SYS_BODCTL_LPBODEN_Msk (0x1ul << SYS_BODCTL_LPBODEN_Pos) |
SYS_T::BODCTL: LPBODEN Mask
| #define SYS_BODCTL_LPBODEN_Pos (8) |
SYS_T::BODCTL: LPBODEN Position
| #define SYS_BODCTL_LPBODIE_Msk (0x1ul << SYS_BODCTL_LPBODIE_Pos) |
SYS_T::BODCTL: LPBODIE Mask
| #define SYS_BODCTL_LPBODIE_Pos (10) |
SYS_T::BODCTL: LPBODIE Position
| #define SYS_BODCTL_LPBODREN_Msk (0x1ul << SYS_BODCTL_LPBODREN_Pos) |
SYS_T::BODCTL: LPBODREN Mask
| #define SYS_BODCTL_LPBODREN_Pos (11) |
SYS_T::BODCTL: LPBODREN Position
| #define SYS_BODCTL_LPBODVL_Msk (0x1ul << SYS_BODCTL_LPBODVL_Pos) |
SYS_T::BODCTL: LPBODVL Mask
| #define SYS_BODCTL_LPBODVL_Pos (9) |
SYS_T::BODCTL: LPBODVL Position
| #define SYS_BODCTL_LVRDGSEL_Msk (0x7ul << SYS_BODCTL_LVRDGSEL_Pos) |
SYS_T::BODCTL: LVRDGSEL Mask
| #define SYS_BODCTL_LVRDGSEL_Pos (28) |
SYS_T::BODCTL: LVRDGSEL Position
| #define SYS_BODCTL_LVREN_Msk (0x1ul << SYS_BODCTL_LVREN_Pos) |
SYS_T::BODCTL: LVREN Mask
| #define SYS_BODCTL_LVREN_Pos (7) |
SYS_T::BODCTL: LVREN Position
| #define SYS_GPA_MFPH_PA10MFP_Msk (0xful << SYS_GPA_MFPH_PA10MFP_Pos) |
SYS_T::GPA_MFPH: PA10MFP Mask
| #define SYS_GPA_MFPH_PA10MFP_Pos (8) |
SYS_T::GPA_MFPH: PA10MFP Position
| #define SYS_GPA_MFPH_PA11MFP_Msk (0xful << SYS_GPA_MFPH_PA11MFP_Pos) |
SYS_T::GPA_MFPH: PA11MFP Mask
| #define SYS_GPA_MFPH_PA11MFP_Pos (12) |
SYS_T::GPA_MFPH: PA11MFP Position
| #define SYS_GPA_MFPH_PA12MFP_Msk (0xful << SYS_GPA_MFPH_PA12MFP_Pos) |
SYS_T::GPA_MFPH: PA12MFP Mask
| #define SYS_GPA_MFPH_PA12MFP_Pos (16) |
SYS_T::GPA_MFPH: PA12MFP Position
| #define SYS_GPA_MFPH_PA13MFP_Msk (0xful << SYS_GPA_MFPH_PA13MFP_Pos) |
SYS_T::GPA_MFPH: PA13MFP Mask
| #define SYS_GPA_MFPH_PA13MFP_Pos (20) |
SYS_T::GPA_MFPH: PA13MFP Position
| #define SYS_GPA_MFPH_PA14MFP_Msk (0xful << SYS_GPA_MFPH_PA14MFP_Pos) |
SYS_T::GPA_MFPH: PA14MFP Mask
| #define SYS_GPA_MFPH_PA14MFP_Pos (24) |
SYS_T::GPA_MFPH: PA14MFP Position
| #define SYS_GPA_MFPH_PA15MFP_Msk (0xful << SYS_GPA_MFPH_PA15MFP_Pos) |
SYS_T::GPA_MFPH: PA15MFP Mask
| #define SYS_GPA_MFPH_PA15MFP_Pos (28) |
SYS_T::GPA_MFPH: PA15MFP Position
| #define SYS_GPA_MFPH_PA8MFP_Msk (0xful << SYS_GPA_MFPH_PA8MFP_Pos) |
SYS_T::GPA_MFPH: PA8MFP Mask
| #define SYS_GPA_MFPH_PA8MFP_Pos (0) |
SYS_T::GPA_MFPH: PA8MFP Position
| #define SYS_GPA_MFPH_PA9MFP_Msk (0xful << SYS_GPA_MFPH_PA9MFP_Pos) |
SYS_T::GPA_MFPH: PA9MFP Mask
| #define SYS_GPA_MFPH_PA9MFP_Pos (4) |
SYS_T::GPA_MFPH: PA9MFP Position
| #define SYS_GPA_MFPL_PA0MFP_Msk (0xful << SYS_GPA_MFPL_PA0MFP_Pos) |
SYS_T::GPA_MFPL: PA0MFP Mask
| #define SYS_GPA_MFPL_PA0MFP_Pos (0) |
SYS_T::GPA_MFPL: PA0MFP Position
| #define SYS_GPA_MFPL_PA1MFP_Msk (0xful << SYS_GPA_MFPL_PA1MFP_Pos) |
SYS_T::GPA_MFPL: PA1MFP Mask
| #define SYS_GPA_MFPL_PA1MFP_Pos (4) |
SYS_T::GPA_MFPL: PA1MFP Position
| #define SYS_GPA_MFPL_PA2MFP_Msk (0xful << SYS_GPA_MFPL_PA2MFP_Pos) |
SYS_T::GPA_MFPL: PA2MFP Mask
| #define SYS_GPA_MFPL_PA2MFP_Pos (8) |
SYS_T::GPA_MFPL: PA2MFP Position
| #define SYS_GPA_MFPL_PA3MFP_Msk (0xful << SYS_GPA_MFPL_PA3MFP_Pos) |
SYS_T::GPA_MFPL: PA3MFP Mask
| #define SYS_GPA_MFPL_PA3MFP_Pos (12) |
SYS_T::GPA_MFPL: PA3MFP Position
| #define SYS_GPA_MFPL_PA4MFP_Msk (0xful << SYS_GPA_MFPL_PA4MFP_Pos) |
SYS_T::GPA_MFPL: PA4MFP Mask
| #define SYS_GPA_MFPL_PA4MFP_Pos (16) |
SYS_T::GPA_MFPL: PA4MFP Position
| #define SYS_GPA_MFPL_PA5MFP_Msk (0xful << SYS_GPA_MFPL_PA5MFP_Pos) |
SYS_T::GPA_MFPL: PA5MFP Mask
| #define SYS_GPA_MFPL_PA5MFP_Pos (20) |
SYS_T::GPA_MFPL: PA5MFP Position
| #define SYS_GPA_MFPL_PA6MFP_Msk (0xful << SYS_GPA_MFPL_PA6MFP_Pos) |
SYS_T::GPA_MFPL: PA6MFP Mask
| #define SYS_GPA_MFPL_PA6MFP_Pos (24) |
SYS_T::GPA_MFPL: PA6MFP Position
| #define SYS_GPB_MFPH_PB10MFP_Msk (0xful << SYS_GPB_MFPH_PB10MFP_Pos) |
SYS_T::GPB_MFPH: PB10MFP Mask
| #define SYS_GPB_MFPH_PB10MFP_Pos (8) |
SYS_T::GPB_MFPH: PB10MFP Position
| #define SYS_GPB_MFPH_PB11MFP_Msk (0xful << SYS_GPB_MFPH_PB11MFP_Pos) |
SYS_T::GPB_MFPH: PB11MFP Mask
| #define SYS_GPB_MFPH_PB11MFP_Pos (12) |
SYS_T::GPB_MFPH: PB11MFP Position
| #define SYS_GPB_MFPH_PB13MFP_Msk (0xful << SYS_GPB_MFPH_PB13MFP_Pos) |
SYS_T::GPB_MFPH: PB13MFP Mask
| #define SYS_GPB_MFPH_PB13MFP_Pos (20) |
SYS_T::GPB_MFPH: PB13MFP Position
| #define SYS_GPB_MFPH_PB14MFP_Msk (0xful << SYS_GPB_MFPH_PB14MFP_Pos) |
SYS_T::GPB_MFPH: PB14MFP Mask
| #define SYS_GPB_MFPH_PB14MFP_Pos (24) |
SYS_T::GPB_MFPH: PB14MFP Position
| #define SYS_GPB_MFPH_PB15MFP_Msk (0xful << SYS_GPB_MFPH_PB15MFP_Pos) |
SYS_T::GPB_MFPH: PB15MFP Mask
| #define SYS_GPB_MFPH_PB15MFP_Pos (28) |
SYS_T::GPB_MFPH: PB15MFP Position
| #define SYS_GPB_MFPH_PB8MFP_Msk (0xful << SYS_GPB_MFPH_PB8MFP_Pos) |
SYS_T::GPB_MFPH: PB8MFP Mask
| #define SYS_GPB_MFPH_PB8MFP_Pos (0) |
SYS_T::GPB_MFPH: PB8MFP Position
| #define SYS_GPB_MFPH_PB9MFP_Msk (0xful << SYS_GPB_MFPH_PB9MFP_Pos) |
SYS_T::GPB_MFPH: PB9MFP Mask
| #define SYS_GPB_MFPH_PB9MFP_Pos (4) |
SYS_T::GPB_MFPH: PB9MFP Position
| #define SYS_GPB_MFPL_PB0MFP_Msk (0xful << SYS_GPB_MFPL_PB0MFP_Pos) |
SYS_T::GPB_MFPL: PB0MFP Mask
| #define SYS_GPB_MFPL_PB0MFP_Pos (0) |
SYS_T::GPB_MFPL: PB0MFP Position
| #define SYS_GPB_MFPL_PB1MFP_Msk (0xful << SYS_GPB_MFPL_PB1MFP_Pos) |
SYS_T::GPB_MFPL: PB1MFP Mask
| #define SYS_GPB_MFPL_PB1MFP_Pos (4) |
SYS_T::GPB_MFPL: PB1MFP Position
| #define SYS_GPB_MFPL_PB2MFP_Msk (0xful << SYS_GPB_MFPL_PB2MFP_Pos) |
SYS_T::GPB_MFPL: PB2MFP Mask
| #define SYS_GPB_MFPL_PB2MFP_Pos (8) |
SYS_T::GPB_MFPL: PB2MFP Position
| #define SYS_GPB_MFPL_PB3MFP_Msk (0xful << SYS_GPB_MFPL_PB3MFP_Pos) |
SYS_T::GPB_MFPL: PB3MFP Mask
| #define SYS_GPB_MFPL_PB3MFP_Pos (12) |
SYS_T::GPB_MFPL: PB3MFP Position
| #define SYS_GPB_MFPL_PB4MFP_Msk (0xful << SYS_GPB_MFPL_PB4MFP_Pos) |
SYS_T::GPB_MFPL: PB4MFP Mask
| #define SYS_GPB_MFPL_PB4MFP_Pos (16) |
SYS_T::GPB_MFPL: PB4MFP Position
| #define SYS_GPB_MFPL_PB5MFP_Msk (0xful << SYS_GPB_MFPL_PB5MFP_Pos) |
SYS_T::GPB_MFPL: PB5MFP Mask
| #define SYS_GPB_MFPL_PB5MFP_Pos (20) |
SYS_T::GPB_MFPL: PB5MFP Position
| #define SYS_GPB_MFPL_PB6MFP_Msk (0xful << SYS_GPB_MFPL_PB6MFP_Pos) |
SYS_T::GPB_MFPL: PB6MFP Mask
| #define SYS_GPB_MFPL_PB6MFP_Pos (24) |
SYS_T::GPB_MFPL: PB6MFP Position
| #define SYS_GPB_MFPL_PB7MFP_Msk (0xful << SYS_GPB_MFPL_PB7MFP_Pos) |
SYS_T::GPB_MFPL: PB7MFP Mask
| #define SYS_GPB_MFPL_PB7MFP_Pos (28) |
SYS_T::GPB_MFPL: PB7MFP Position
| #define SYS_GPC_MFPH_PC10MFP_Msk (0xful << SYS_GPC_MFPH_PC10MFP_Pos) |
SYS_T::GPC_MFPH: PC10MFP Mask
| #define SYS_GPC_MFPH_PC10MFP_Pos (8) |
SYS_T::GPC_MFPH: PC10MFP Position
| #define SYS_GPC_MFPH_PC11MFP_Msk (0xful << SYS_GPC_MFPH_PC11MFP_Pos) |
SYS_T::GPC_MFPH: PC11MFP Mask
| #define SYS_GPC_MFPH_PC11MFP_Pos (12) |
SYS_T::GPC_MFPH: PC11MFP Position
| #define SYS_GPC_MFPH_PC14MFP_Msk (0xful << SYS_GPC_MFPH_PC14MFP_Pos) |
SYS_T::GPC_MFPH: PC14MFP Mask
| #define SYS_GPC_MFPH_PC14MFP_Pos (24) |
SYS_T::GPC_MFPH: PC14MFP Position
| #define SYS_GPC_MFPH_PC15MFP_Msk (0xful << SYS_GPC_MFPH_PC15MFP_Pos) |
SYS_T::GPC_MFPH: PC15MFP Mask
| #define SYS_GPC_MFPH_PC15MFP_Pos (28) |
SYS_T::GPC_MFPH: PC15MFP Position
| #define SYS_GPC_MFPH_PC8MFP_Msk (0xful << SYS_GPC_MFPH_PC8MFP_Pos) |
SYS_T::GPC_MFPH: PC8MFP Mask
| #define SYS_GPC_MFPH_PC8MFP_Pos (0) |
SYS_T::GPC_MFPH: PC8MFP Position
| #define SYS_GPC_MFPH_PC9MFP_Msk (0xful << SYS_GPC_MFPH_PC9MFP_Pos) |
SYS_T::GPC_MFPH: PC9MFP Mask
| #define SYS_GPC_MFPH_PC9MFP_Pos (4) |
SYS_T::GPC_MFPH: PC9MFP Position
| #define SYS_GPC_MFPL_PC0MFP_Msk (0xful << SYS_GPC_MFPL_PC0MFP_Pos) |
SYS_T::GPC_MFPL: PC0MFP Mask
| #define SYS_GPC_MFPL_PC0MFP_Pos (0) |
SYS_T::GPC_MFPL: PC0MFP Position
| #define SYS_GPC_MFPL_PC1MFP_Msk (0xful << SYS_GPC_MFPL_PC1MFP_Pos) |
SYS_T::GPC_MFPL: PC1MFP Mask
| #define SYS_GPC_MFPL_PC1MFP_Pos (4) |
SYS_T::GPC_MFPL: PC1MFP Position
| #define SYS_GPC_MFPL_PC2MFP_Msk (0xful << SYS_GPC_MFPL_PC2MFP_Pos) |
SYS_T::GPC_MFPL: PC2MFP Mask
| #define SYS_GPC_MFPL_PC2MFP_Pos (8) |
SYS_T::GPC_MFPL: PC2MFP Position
| #define SYS_GPC_MFPL_PC3MFP_Msk (0xful << SYS_GPC_MFPL_PC3MFP_Pos) |
SYS_T::GPC_MFPL: PC3MFP Mask
| #define SYS_GPC_MFPL_PC3MFP_Pos (12) |
SYS_T::GPC_MFPL: PC3MFP Position
| #define SYS_GPC_MFPL_PC6MFP_Msk (0xful << SYS_GPC_MFPL_PC6MFP_Pos) |
SYS_T::GPC_MFPL: PC6MFP Mask
| #define SYS_GPC_MFPL_PC6MFP_Pos (24) |
SYS_T::GPC_MFPL: PC6MFP Position
| #define SYS_GPC_MFPL_PC7MFP_Msk (0xful << SYS_GPC_MFPL_PC7MFP_Pos) |
SYS_T::GPC_MFPL: PC7MFP Mask
| #define SYS_GPC_MFPL_PC7MFP_Pos (28) |
SYS_T::GPC_MFPL: PC7MFP Position
| #define SYS_GPD_MFPH_PD14MFP_Msk (0xful << SYS_GPD_MFPH_PD14MFP_Pos) |
SYS_T::GPD_MFPH: PD14MFP Mask
| #define SYS_GPD_MFPH_PD14MFP_Pos (24) |
SYS_T::GPD_MFPH: PD14MFP Position
| #define SYS_GPD_MFPH_PD15MFP_Msk (0x7ul << SYS_GPD_MFPH_PD15MFP_Pos) |
SYS_T::GPD_MFPH: PD15MFP Mask
| #define SYS_GPD_MFPH_PD15MFP_Pos (28) |
SYS_T::GPD_MFPH: PD15MFP Position
| #define SYS_GPD_MFPL_PD6MFP_Msk (0xful << SYS_GPD_MFPL_PD6MFP_Pos) |
SYS_T::GPD_MFPL: PD6MFP Mask
| #define SYS_GPD_MFPL_PD6MFP_Pos (24) |
SYS_T::GPD_MFPL: PD6MFP Position
| #define SYS_GPD_MFPL_PD7MFP_Msk (0xful << SYS_GPD_MFPL_PD7MFP_Pos) |
SYS_T::GPD_MFPL: PD7MFP Mask
| #define SYS_GPD_MFPL_PD7MFP_Pos (28) |
SYS_T::GPD_MFPL: PD7MFP Position
| #define SYS_GPE_MFPL_PE5MFP_Msk (0xful << SYS_GPE_MFPL_PE5MFP_Pos) |
SYS_T::GPE_MFPL: PE5MFP Mask
| #define SYS_GPE_MFPL_PE5MFP_Pos (20) |
SYS_T::GPE_MFPL: PE5MFP Position
| #define SYS_GPF_MFPL_PF0MFP_Msk (0xful << SYS_GPF_MFPL_PF0MFP_Pos) |
SYS_T::GPF_MFPL: PF0MFP Mask
| #define SYS_GPF_MFPL_PF0MFP_Pos (0) |
SYS_T::GPF_MFPL: PF0MFP Position
| #define SYS_GPF_MFPL_PF1MFP_Msk (0xful << SYS_GPF_MFPL_PF1MFP_Pos) |
SYS_T::GPF_MFPL: PF1MFP Mask
| #define SYS_GPF_MFPL_PF1MFP_Pos (4) |
SYS_T::GPF_MFPL: PF1MFP Position
| #define SYS_GPF_MFPL_PF2MFP_Msk (0xful << SYS_GPF_MFPL_PF2MFP_Pos) |
SYS_T::GPF_MFPL: PF2MFP Mask
| #define SYS_GPF_MFPL_PF2MFP_Pos (8) |
SYS_T::GPF_MFPL: PF2MFP Position
| #define SYS_GPF_MFPL_PF3MFP_Msk (0xful << SYS_GPF_MFPL_PF3MFP_Pos) |
SYS_T::GPF_MFPL: PF3MFP Mask
| #define SYS_GPF_MFPL_PF3MFP_Pos (12) |
SYS_T::GPF_MFPL: PF3MFP Position
| #define SYS_GPF_MFPL_PF6MFP_Msk (0xful << SYS_GPF_MFPL_PF6MFP_Pos) |
SYS_T::GPF_MFPL: PF6MFP Mask
| #define SYS_GPF_MFPL_PF6MFP_Pos (24) |
SYS_T::GPF_MFPL: PF6MFP Position
| #define SYS_GPF_MFPL_PF7MFP_Msk (0xful << SYS_GPF_MFPL_PF7MFP_Pos) |
SYS_T::GPF_MFPL: PF7MFP Mask
| #define SYS_GPF_MFPL_PF7MFP_Pos (28) |
SYS_T::GPF_MFPL: PF7MFP Position
| #define SYS_IPRST1_CHIPRST_Msk (0x1ul << SYS_IPRST1_CHIPRST_Pos) |
SYS_T::IPRST1: CHIPRST Mask
| #define SYS_IPRST1_CHIPRST_Pos (0) |
SYS_T::IPRST1: CHIPRST Position
| #define SYS_IPRST1_CPURST_Msk (0x1ul << SYS_IPRST1_CPURST_Pos) |
SYS_T::IPRST1: CPURST Mask
| #define SYS_IPRST1_CPURST_Pos (1) |
SYS_T::IPRST1: CPURST Position
| #define SYS_IPRST1_PDMARST_Msk (0x1ul << SYS_IPRST1_PDMARST_Pos) |
SYS_T::IPRST1: PDMARST Mask
| #define SYS_IPRST1_PDMARST_Pos (2) |
SYS_T::IPRST1: PDMARST Position
| #define SYS_IPRST2_ACMP0RST_Msk (0x1ul << SYS_IPRST2_ACMP0RST_Pos) |
SYS_T::IPRST2: ACMP0RST Mask
| #define SYS_IPRST2_ACMP0RST_Pos (22) |
SYS_T::IPRST2: ACMP0RST Position
| #define SYS_IPRST2_ADCRST_Msk (0x1ul << SYS_IPRST2_ADCRST_Pos) |
SYS_T::IPRST2: ADCRST Mask
| #define SYS_IPRST2_ADCRST_Pos (28) |
SYS_T::IPRST2: ADCRST Position
| #define SYS_IPRST2_GPIORST_Msk (0x1ul << SYS_IPRST2_GPIORST_Pos) |
SYS_T::IPRST2: GPIORST Mask
| #define SYS_IPRST2_GPIORST_Pos (1) |
SYS_T::IPRST2: GPIORST Position
| #define SYS_IPRST2_I2C0RST_Msk (0x1ul << SYS_IPRST2_I2C0RST_Pos) |
SYS_T::IPRST2: I2C0RST Mask
| #define SYS_IPRST2_I2C0RST_Pos (8) |
SYS_T::IPRST2: I2C0RST Position
| #define SYS_IPRST2_I2C1RST_Msk (0x1ul << SYS_IPRST2_I2C1RST_Pos) |
SYS_T::IPRST2: I2C1RST Mask
| #define SYS_IPRST2_I2C1RST_Pos (9) |
SYS_T::IPRST2: I2C1RST Position
| #define SYS_IPRST2_PWM0RST_Msk (0x1ul << SYS_IPRST2_PWM0RST_Pos) |
SYS_T::IPRST2: PWM0RST Mask
| #define SYS_IPRST2_PWM0RST_Pos (20) |
SYS_T::IPRST2: PWM0RST Position
| #define SYS_IPRST2_SC0RST_Msk (0x1ul << SYS_IPRST2_SC0RST_Pos) |
SYS_T::IPRST2: SC0RST Mask
| #define SYS_IPRST2_SC0RST_Pos (30) |
SYS_T::IPRST2: SC0RST Position
| #define SYS_IPRST2_SC1RST_Msk (0x1ul << SYS_IPRST2_SC1RST_Pos) |
SYS_T::IPRST2: SC1RST Mask
| #define SYS_IPRST2_SC1RST_Pos (31) |
SYS_T::IPRST2: SC1RST Position
| #define SYS_IPRST2_SPI0RST_Msk (0x1ul << SYS_IPRST2_SPI0RST_Pos) |
SYS_T::IPRST2: SPI0RST Mask
| #define SYS_IPRST2_SPI0RST_Pos (12) |
SYS_T::IPRST2: SPI0RST Position
| #define SYS_IPRST2_SPI1RST_Msk (0x1ul << SYS_IPRST2_SPI1RST_Pos) |
SYS_T::IPRST2: SPI1RST Mask
| #define SYS_IPRST2_SPI1RST_Pos (13) |
SYS_T::IPRST2: SPI1RST Position
| #define SYS_IPRST2_SPI2RST_Msk (0x1ul << SYS_IPRST2_SPI2RST_Pos) |
SYS_T::IPRST2: SPI2RST Mask
| #define SYS_IPRST2_SPI2RST_Pos (14) |
SYS_T::IPRST2: SPI2RST Position
| #define SYS_IPRST2_SPI3RST_Msk (0x1ul << SYS_IPRST2_SPI3RST_Pos) |
SYS_T::IPRST2: SPI3RST Mask
| #define SYS_IPRST2_SPI3RST_Pos (15) |
SYS_T::IPRST2: SPI3RST Position
| #define SYS_IPRST2_TMR0RST_Msk (0x1ul << SYS_IPRST2_TMR0RST_Pos) |
SYS_T::IPRST2: TMR0RST Mask
| #define SYS_IPRST2_TMR0RST_Pos (2) |
SYS_T::IPRST2: TMR0RST Position
| #define SYS_IPRST2_TMR1RST_Msk (0x1ul << SYS_IPRST2_TMR1RST_Pos) |
SYS_T::IPRST2: TMR1RST Mask
| #define SYS_IPRST2_TMR1RST_Pos (3) |
SYS_T::IPRST2: TMR1RST Position
| #define SYS_IPRST2_TMR2RST_Msk (0x1ul << SYS_IPRST2_TMR2RST_Pos) |
SYS_T::IPRST2: TMR2RST Mask
| #define SYS_IPRST2_TMR2RST_Pos (4) |
SYS_T::IPRST2: TMR2RST Position
| #define SYS_IPRST2_TMR3RST_Msk (0x1ul << SYS_IPRST2_TMR3RST_Pos) |
SYS_T::IPRST2: TMR3RST Mask
| #define SYS_IPRST2_TMR3RST_Pos (5) |
SYS_T::IPRST2: TMR3RST Position
| #define SYS_IPRST2_UART0RST_Msk (0x1ul << SYS_IPRST2_UART0RST_Pos) |
SYS_T::IPRST2: UART0RST Mask
| #define SYS_IPRST2_UART0RST_Pos (16) |
SYS_T::IPRST2: UART0RST Position
| #define SYS_IPRST2_UART1RST_Msk (0x1ul << SYS_IPRST2_UART1RST_Pos) |
SYS_T::IPRST2: UART1RST Mask
| #define SYS_IPRST2_UART1RST_Pos (17) |
SYS_T::IPRST2: UART1RST Position
| #define SYS_IRC0TCTL_CESTOPEN_Msk (0x1ul << SYS_IRC0TCTL_CESTOPEN_Pos) |
SYS_T::IRC0TCTL: CESTOPEN Mask
| #define SYS_IRC0TCTL_CESTOPEN_Pos (8) |
SYS_T::IRC0TCTL: CESTOPEN Position
| #define SYS_IRC0TCTL_FREQSEL_Msk (0x7ul << SYS_IRC0TCTL_FREQSEL_Pos) |
SYS_T::IRC0TCTL: FREQSEL Mask
| #define SYS_IRC0TCTL_FREQSEL_Pos (0) |
SYS_T::IRC0TCTL: FREQSEL Position
| #define SYS_IRC0TCTL_LOOPSEL_Msk (0x3ul << SYS_IRC0TCTL_LOOPSEL_Pos) |
SYS_T::IRC0TCTL: LOOPSEL Mask
| #define SYS_IRC0TCTL_LOOPSEL_Pos (4) |
SYS_T::IRC0TCTL: LOOPSEL Position
| #define SYS_IRC0TCTL_RETRYCNT_Msk (0x3ul << SYS_IRC0TCTL_RETRYCNT_Pos) |
SYS_T::IRC0TCTL: RETRYCNT Mask
| #define SYS_IRC0TCTL_RETRYCNT_Pos (6) |
SYS_T::IRC0TCTL: RETRYCNT Position
| #define SYS_IRC0TIEN_CLKEIEN_Msk (0x1ul << SYS_IRC0TIEN_CLKEIEN_Pos) |
SYS_T::IRC0TIEN: CLKEIEN Mask
| #define SYS_IRC0TIEN_CLKEIEN_Pos (2) |
SYS_T::IRC0TIEN: CLKEIEN Position
| #define SYS_IRC0TIEN_TFAILIEN_Msk (0x1ul << SYS_IRC0TIEN_TFAILIEN_Pos) |
SYS_T::IRC0TIEN: TFAILIEN Mask
| #define SYS_IRC0TIEN_TFAILIEN_Pos (1) |
SYS_T::IRC0TIEN: TFAILIEN Position
| #define SYS_IRC0TISTS_CLKERRIF_Msk (0x1ul << SYS_IRC0TISTS_CLKERRIF_Pos) |
SYS_T::IRC0TISTS: CLKERRIF Mask
| #define SYS_IRC0TISTS_CLKERRIF_Pos (2) |
SYS_T::IRC0TISTS: CLKERRIF Position
| #define SYS_IRC0TISTS_FREQLOCK_Msk (0x1ul << SYS_IRC0TISTS_FREQLOCK_Pos) |
SYS_T::IRC0TISTS: FREQLOCK Mask
| #define SYS_IRC0TISTS_FREQLOCK_Pos (0) |
SYS_T::IRC0TISTS: FREQLOCK Position
| #define SYS_IRC0TISTS_TFAILIF_Msk (0x1ul << SYS_IRC0TISTS_TFAILIF_Pos) |
SYS_T::IRC0TISTS: TFAILIF Mask
| #define SYS_IRC0TISTS_TFAILIF_Pos (1) |
SYS_T::IRC0TISTS: TFAILIF Position
| #define SYS_IRC1TCTL_CESTOPEN_Msk (0x1ul << SYS_IRC1TCTL_CESTOPEN_Pos) |
SYS_T::IRC1TCTL: CESTOPEN Mask
| #define SYS_IRC1TCTL_CESTOPEN_Pos (8) |
SYS_T::IRC1TCTL: CESTOPEN Position
| #define SYS_IRC1TCTL_FREQSEL_Msk (0x3ul << SYS_IRC1TCTL_FREQSEL_Pos) |
SYS_T::IRC1TCTL: FREQSEL Mask
| #define SYS_IRC1TCTL_FREQSEL_Pos (0) |
SYS_T::IRC1TCTL: FREQSEL Position
| #define SYS_IRC1TCTL_LOOPSEL_Msk (0x3ul << SYS_IRC1TCTL_LOOPSEL_Pos) |
SYS_T::IRC1TCTL: LOOPSEL Mask
| #define SYS_IRC1TCTL_LOOPSEL_Pos (4) |
SYS_T::IRC1TCTL: LOOPSEL Position
| #define SYS_IRC1TCTL_RETRYCNT_Msk (0x3ul << SYS_IRC1TCTL_RETRYCNT_Pos) |
SYS_T::IRC1TCTL: RETRYCNT Mask
| #define SYS_IRC1TCTL_RETRYCNT_Pos (6) |
SYS_T::IRC1TCTL: RETRYCNT Position
| #define SYS_IRC1TIEN_CLKEIEN_Msk (0x1ul << SYS_IRC1TIEN_CLKEIEN_Pos) |
SYS_T::IRC1TIEN: CLKEIEN Mask
| #define SYS_IRC1TIEN_CLKEIEN_Pos (2) |
SYS_T::IRC1TIEN: CLKEIEN Position
| #define SYS_IRC1TIEN_TFAILIEN_Msk (0x1ul << SYS_IRC1TIEN_TFAILIEN_Pos) |
SYS_T::IRC1TIEN: TFAILIEN Mask
| #define SYS_IRC1TIEN_TFAILIEN_Pos (1) |
SYS_T::IRC1TIEN: TFAILIEN Position
| #define SYS_IRC1TISTS_CLKERRIF_Msk (0x1ul << SYS_IRC1TISTS_CLKERRIF_Pos) |
SYS_T::IRC1TISTS: CLKERRIF Mask
| #define SYS_IRC1TISTS_CLKERRIF_Pos (2) |
SYS_T::IRC1TISTS: CLKERRIF Position
| #define SYS_IRC1TISTS_FREQLOCK_Msk (0x1ul << SYS_IRC1TISTS_FREQLOCK_Pos) |
SYS_T::IRC1TISTS: FREQLOCK Mask
| #define SYS_IRC1TISTS_FREQLOCK_Pos (0) |
SYS_T::IRC1TISTS: FREQLOCK Position
| #define SYS_IRC1TISTS_TFAILIF_Msk (0x1ul << SYS_IRC1TISTS_TFAILIF_Pos) |
SYS_T::IRC1TISTS: TFAILIF Mask
| #define SYS_IRC1TISTS_TFAILIF_Pos (1) |
SYS_T::IRC1TISTS: TFAILIF Position
| #define SYS_IVREFCTL_BGPEN_Msk (0x1ul << SYS_IVREFCTL_BGPEN_Pos) |
SYS_T::IVREFCTL: BGPEN Mask
| #define SYS_IVREFCTL_BGPEN_Pos (0) |
SYS_T::IVREFCTL: BGPEN Position
| #define SYS_IVREFCTL_EXTMODE_Msk (0x1ul << SYS_IVREFCTL_EXTMODE_Pos) |
SYS_T::IVREFCTL: EXTMODE Mask
| #define SYS_IVREFCTL_EXTMODE_Pos (4) |
SYS_T::IVREFCTL: EXTMODE Position
| #define SYS_IVREFCTL_REGEN_Msk (0x1ul << SYS_IVREFCTL_REGEN_Pos) |
SYS_T::IVREFCTL: REGEN Mask
| #define SYS_IVREFCTL_REGEN_Pos (1) |
SYS_T::IVREFCTL: REGEN Position
| #define SYS_IVREFCTL_SEL25_Msk (0x3ul << SYS_IVREFCTL_SEL25_Pos) |
SYS_T::IVREFCTL: SEL25 Mask
| #define SYS_IVREFCTL_SEL25_Pos (2) |
SYS_T::IVREFCTL: SEL25 Position
| #define SYS_IVREFCTL_VREFTRIM_Msk (0xful << SYS_IVREFCTL_VREFTRIM_Pos) |
SYS_T::IVREFCTL: VREFTRIM Mask
| #define SYS_IVREFCTL_VREFTRIM_Pos (8) |
SYS_T::IVREFCTL: VREFTRIM Position
| #define SYS_LDOCTL_FASTWK_Msk (0x1ul << SYS_LDOCTL_FASTWK_Pos) |
SYS_T::LDOCTL: FASTWK Mask
| #define SYS_LDOCTL_FASTWK_Pos (1) |
SYS_T::LDOCTL: FASTWK Position
| #define SYS_LDOCTL_FMCLVEN_Msk (0x1ul << SYS_LDOCTL_FMCLVEN_Pos) |
SYS_T::LDOCTL: FMCLVEN Mask
| #define SYS_LDOCTL_FMCLVEN_Pos (5) |
SYS_T::LDOCTL: FMCLVEN Position
| #define SYS_LDOCTL_LDOLVL_Msk (0x3ul << SYS_LDOCTL_LDOLVL_Pos) |
SYS_T::LDOCTL: LDOLVL Mask
| #define SYS_LDOCTL_LDOLVL_Pos (2) |
SYS_T::LDOCTL: LDOLVL Position
| #define SYS_LDOCTL_LPRMEN_Msk (0x1ul << SYS_LDOCTL_LPRMEN_Pos) |
SYS_T::LDOCTL: LPRMEN Mask
| #define SYS_LDOCTL_LPRMEN_Pos (4) |
SYS_T::LDOCTL: LPRMEN Position
| #define SYS_MIRCTCTL_CESTOPEN_Msk (0x1ul << SYS_MIRCTCTL_CESTOPEN_Pos) |
SYS_T::MIRCTCTL: CESTOPEN Mask
| #define SYS_MIRCTCTL_CESTOPEN_Pos (8) |
SYS_T::MIRCTCTL: CESTOPEN Position
| #define SYS_MIRCTCTL_FREQSEL_Msk (0x3ul << SYS_MIRCTCTL_FREQSEL_Pos) |
SYS_T::MIRCTCTL: FREQSEL Mask
| #define SYS_MIRCTCTL_FREQSEL_Pos (0) |
SYS_T::MIRCTCTL: FREQSEL Position
| #define SYS_MIRCTCTL_LOOPSEL_Msk (0x3ul << SYS_MIRCTCTL_LOOPSEL_Pos) |
SYS_T::MIRCTCTL: LOOPSEL Mask
| #define SYS_MIRCTCTL_LOOPSEL_Pos (4) |
SYS_T::MIRCTCTL: LOOPSEL Position
| #define SYS_MIRCTCTL_RETRYCNT_Msk (0x3ul << SYS_MIRCTCTL_RETRYCNT_Pos) |
SYS_T::MIRCTCTL: RETRYCNT Mask
| #define SYS_MIRCTCTL_RETRYCNT_Pos (6) |
SYS_T::MIRCTCTL: RETRYCNT Position
| #define SYS_MIRCTIEN_CLKEIEN_Msk (0x1ul << SYS_MIRCTIEN_CLKEIEN_Pos) |
SYS_T::MIRCTIEN: CLKEIEN Mask
| #define SYS_MIRCTIEN_CLKEIEN_Pos (2) |
SYS_T::MIRCTIEN: CLKEIEN Position
| #define SYS_MIRCTIEN_TFAILIEN_Msk (0x1ul << SYS_MIRCTIEN_TFAILIEN_Pos) |
SYS_T::MIRCTIEN: TFAILIEN Mask
| #define SYS_MIRCTIEN_TFAILIEN_Pos (1) |
SYS_T::MIRCTIEN: TFAILIEN Position
| #define SYS_MIRCTISTS_CLKERRIF_Msk (0x1ul << SYS_MIRCTISTS_CLKERRIF_Pos) |
SYS_T::MIRCTISTS: CLKERRIF Mask
| #define SYS_MIRCTISTS_CLKERRIF_Pos (2) |
SYS_T::MIRCTISTS: CLKERRIF Position
| #define SYS_MIRCTISTS_FREQLOCK_Msk (0x1ul << SYS_MIRCTISTS_FREQLOCK_Pos) |
SYS_T::MIRCTISTS: FREQLOCK Mask
| #define SYS_MIRCTISTS_FREQLOCK_Pos (0) |
SYS_T::MIRCTISTS: FREQLOCK Position
| #define SYS_MIRCTISTS_TFAILIF_Msk (0x1ul << SYS_MIRCTISTS_TFAILIF_Pos) |
SYS_T::MIRCTISTS: TFAILIF Mask
| #define SYS_MIRCTISTS_TFAILIF_Pos (1) |
SYS_T::MIRCTISTS: TFAILIF Position
| #define SYS_MISCCTL_POR18DIS_Msk (0x1ul << SYS_MISCCTL_POR18DIS_Pos) |
SYS_T::MISCCTL: POR18DIS Mask
| #define SYS_MISCCTL_POR18DIS_Pos (7) |
SYS_T::MISCCTL: POR18DIS Position
| #define SYS_MISCCTL_POR33DIS_Msk (0x1ul << SYS_MISCCTL_POR33DIS_Pos) |
SYS_T::MISCCTL: POR33DIS Mask
| #define SYS_MISCCTL_POR33DIS_Pos (6) |
SYS_T::MISCCTL: POR33DIS Position
| #define SYS_PDID_PDID_Msk (0xfffffffful << SYS_PDID_PDID_Pos) |
SYS_T::PDID: PDID Mask
| #define SYS_PDID_PDID_Pos (0) |
@addtogroup SYS_CONST SYS Bit Field Definition Constant Definitions for SYS Controller
SYS_T::PDID: PDID Position
| #define SYS_PORCTL_POROFF_Msk (0xfffful << SYS_PORCTL_POROFF_Pos) |
SYS_T::PORCTL: POROFF Mask
| #define SYS_PORCTL_POROFF_Pos (0) |
SYS_T::PORCTL: POROFF Position
| #define SYS_RCCFCTL_HIRC0FEN_Msk (0x1ul << SYS_RCCFCTL_HIRC0FEN_Pos) |
SYS_T::RCCFCTL: HIRC0FEN Mask
| #define SYS_RCCFCTL_HIRC0FEN_Pos (0) |
SYS_T::RCCFCTL: HIRC0FEN Position
| #define SYS_RCCFCTL_HIRC1FEN_Msk (0x1ul << SYS_RCCFCTL_HIRC1FEN_Pos) |
SYS_T::RCCFCTL: HIRC1FEN Mask
| #define SYS_RCCFCTL_HIRC1FEN_Pos (1) |
SYS_T::RCCFCTL: HIRC1FEN Position
| #define SYS_RCCFCTL_MRCFEN_Msk (0x1ul << SYS_RCCFCTL_MRCFEN_Pos) |
SYS_T::RCCFCTL: MRCFEN Mask
| #define SYS_RCCFCTL_MRCFEN_Pos (2) |
SYS_T::RCCFCTL: MRCFEN Position
| #define SYS_REGLCTL_REGLCTL_Msk (0x1ul << SYS_REGLCTL_REGLCTL_Pos) |
SYS_T::REGLCTL: REGLCTL Mask
| #define SYS_REGLCTL_REGLCTL_Pos (0) |
SYS_T::REGLCTL: REGLCTL Position
| #define SYS_RPDBCLK_RSTPDBCLK_Msk (0x1ul << SYS_RPDBCLK_RSTPDBCLK_Pos) |
SYS_T::RPDBCLK: RSTPDBCLK Mask
| #define SYS_RPDBCLK_RSTPDBCLK_Pos (6) |
SYS_T::RPDBCLK: RSTPDBCLK Position
| #define SYS_RSTSTS_BODRF_Msk (0x1ul << SYS_RSTSTS_BODRF_Pos) |
SYS_T::RSTSTS: BODRF Mask
| #define SYS_RSTSTS_BODRF_Pos (4) |
SYS_T::RSTSTS: BODRF Position
| #define SYS_RSTSTS_CPURF_Msk (0x1ul << SYS_RSTSTS_CPURF_Pos) |
SYS_T::RSTSTS: CPURF Mask
| #define SYS_RSTSTS_CPURF_Pos (7) |
SYS_T::RSTSTS: CPURF Position
| #define SYS_RSTSTS_LOCKRF_Msk (0x1ul << SYS_RSTSTS_LOCKRF_Pos) |
SYS_T::RSTSTS: LOCKRF Mask
| #define SYS_RSTSTS_LOCKRF_Pos (8) |
SYS_T::RSTSTS: LOCKRF Position
| #define SYS_RSTSTS_LVRF_Msk (0x1ul << SYS_RSTSTS_LVRF_Pos) |
SYS_T::RSTSTS: LVRF Mask
| #define SYS_RSTSTS_LVRF_Pos (3) |
SYS_T::RSTSTS: LVRF Position
| #define SYS_RSTSTS_PINRF_Msk (0x1ul << SYS_RSTSTS_PINRF_Pos) |
SYS_T::RSTSTS: PINRF Mask
| #define SYS_RSTSTS_PINRF_Pos (1) |
SYS_T::RSTSTS: PINRF Position
| #define SYS_RSTSTS_PORF_Msk (0x1ul << SYS_RSTSTS_PORF_Pos) |
SYS_T::RSTSTS: PORF Mask
| #define SYS_RSTSTS_PORF_Pos (0) |
SYS_T::RSTSTS: PORF Position
| #define SYS_RSTSTS_SYSRF_Msk (0x1ul << SYS_RSTSTS_SYSRF_Pos) |
SYS_T::RSTSTS: SYSRF Mask
| #define SYS_RSTSTS_SYSRF_Pos (5) |
SYS_T::RSTSTS: SYSRF Position
| #define SYS_RSTSTS_WDTRF_Msk (0x1ul << SYS_RSTSTS_WDTRF_Pos) |
SYS_T::RSTSTS: WDTRF Mask
| #define SYS_RSTSTS_WDTRF_Pos (2) |
SYS_T::RSTSTS: WDTRF Position
| #define SYS_TEMPCTL_VTEMPEN_Msk (0x1ul << SYS_TEMPCTL_VTEMPEN_Pos) |
SYS_T::TEMPCTL: VTEMPEN Mask
| #define SYS_TEMPCTL_VTEMPEN_Pos (0) |
SYS_T::TEMPCTL: VTEMPEN Position
| #define SYS_WKSTS_ACMPWK_Msk (0x1ul << SYS_WKSTS_ACMPWK_Pos) |
SYS_T::WKSTS: ACMPWK Mask
| #define SYS_WKSTS_ACMPWK_Pos (0) |
SYS_T::WKSTS: ACMPWK Position
| #define SYS_WKSTS_BODWK_Msk (0x1ul << SYS_WKSTS_BODWK_Pos) |
SYS_T::WKSTS: BODWK Mask
| #define SYS_WKSTS_BODWK_Pos (8) |
SYS_T::WKSTS: BODWK Position
| #define SYS_WKSTS_GPIOWK_Msk (0x1ul << SYS_WKSTS_GPIOWK_Pos) |
SYS_T::WKSTS: GPIOWK Mask
| #define SYS_WKSTS_GPIOWK_Pos (16) |
SYS_T::WKSTS: GPIOWK Position
| #define SYS_WKSTS_I2C0WK_Msk (0x1ul << SYS_WKSTS_I2C0WK_Pos) |
SYS_T::WKSTS: I2C0WK Mask
| #define SYS_WKSTS_I2C0WK_Pos (2) |
SYS_T::WKSTS: I2C0WK Position
| #define SYS_WKSTS_I2C1WK_Msk (0x1ul << SYS_WKSTS_I2C1WK_Pos) |
SYS_T::WKSTS: I2C1WK Mask
| #define SYS_WKSTS_I2C1WK_Pos (1) |
SYS_T::WKSTS: I2C1WK Position
| #define SYS_WKSTS_RTCWK_Msk (0x1ul << SYS_WKSTS_RTCWK_Pos) |
SYS_T::WKSTS: RTCWK Mask
| #define SYS_WKSTS_RTCWK_Pos (15) |
SYS_T::WKSTS: RTCWK Position
| #define SYS_WKSTS_SPI0WK_Msk (0x1ul << SYS_WKSTS_SPI0WK_Pos) |
SYS_T::WKSTS: SPI0WK Mask
| #define SYS_WKSTS_SPI0WK_Pos (12) |
SYS_T::WKSTS: SPI0WK Position
| #define SYS_WKSTS_SPI1WK_Msk (0x1ul << SYS_WKSTS_SPI1WK_Pos) |
SYS_T::WKSTS: SPI1WK Mask
| #define SYS_WKSTS_SPI1WK_Pos (11) |
SYS_T::WKSTS: SPI1WK Position
| #define SYS_WKSTS_SPI2WK_Msk (0x1ul << SYS_WKSTS_SPI2WK_Pos) |
SYS_T::WKSTS: SPI2WK Mask
| #define SYS_WKSTS_SPI2WK_Pos (10) |
SYS_T::WKSTS: SPI2WK Position
| #define SYS_WKSTS_SPI3WK_Msk (0x1ul << SYS_WKSTS_SPI3WK_Pos) |
SYS_T::WKSTS: SPI3WK Mask
| #define SYS_WKSTS_SPI3WK_Pos (9) |
SYS_T::WKSTS: SPI3WK Position
| #define SYS_WKSTS_TMR0WK_Msk (0x1ul << SYS_WKSTS_TMR0WK_Pos) |
SYS_T::WKSTS: TMR0WK Mask
| #define SYS_WKSTS_TMR0WK_Pos (6) |
SYS_T::WKSTS: TMR0WK Position
| #define SYS_WKSTS_TMR1WK_Msk (0x1ul << SYS_WKSTS_TMR1WK_Pos) |
SYS_T::WKSTS: TMR1WK Mask
| #define SYS_WKSTS_TMR1WK_Pos (5) |
SYS_T::WKSTS: TMR1WK Position
| #define SYS_WKSTS_TMR2WK_Msk (0x1ul << SYS_WKSTS_TMR2WK_Pos) |
SYS_T::WKSTS: TMR2WK Mask
| #define SYS_WKSTS_TMR2WK_Pos (4) |
SYS_T::WKSTS: TMR2WK Position
| #define SYS_WKSTS_TMR3WK_Msk (0x1ul << SYS_WKSTS_TMR3WK_Pos) |
SYS_T::WKSTS: TMR3WK Mask
| #define SYS_WKSTS_TMR3WK_Pos (3) |
SYS_T::WKSTS: TMR3WK Position
| #define SYS_WKSTS_UART0WK_Msk (0x1ul << SYS_WKSTS_UART0WK_Pos) |
SYS_T::WKSTS: UART0WK Mask
| #define SYS_WKSTS_UART0WK_Pos (14) |
SYS_T::WKSTS: UART0WK Position
| #define SYS_WKSTS_UART1WK_Msk (0x1ul << SYS_WKSTS_UART1WK_Pos) |
SYS_T::WKSTS: UART1WK Mask
| #define SYS_WKSTS_UART1WK_Pos (13) |
SYS_T::WKSTS: UART1WK Position
| #define SYS_WKSTS_WDTWK_Msk (0x1ul << SYS_WKSTS_WDTWK_Pos) |
SYS_T::WKSTS: WDTWK Mask
| #define SYS_WKSTS_WDTWK_Pos (7) |
SYS_T::WKSTS: WDTWK Position
1.8.15