| Nano103 BSP V3.01.002 The Board Support Package for Nano103 Series

Data Fields
CLK_T Struct Reference

`#include <Nano103.h>`

## Data Fields
__IO uint32_t | PWRCTL
__IO uint32_t | AHBCLK
__IO uint32_t | APBCLK
__I uint32_t | STATUS
__IO uint32_t | CLKSEL0
__IO uint32_t | CLKSEL1
__IO uint32_t | CLKSEL2
__IO uint32_t | CLKDIV0
__IO uint32_t | CLKDIV1
__IO uint32_t | PLLCTL
__IO uint32_t | CLKOCTL
__IO uint32_t | WKINTSTS
__IO uint32_t | APBDIV
__IO uint32_t | CLKDCTL
__IO uint32_t | CLKDIE
__IO uint32_t | CLKDSTS
__IO uint32_t | CDUPB
__IO uint32_t | CDLOWB

## Detailed Description

    @addtogroup CLK System Clock Controller(CLK)
    Memory Mapped Structure for CLK Controller

Definition at line 3740 of file Nano103.h.

## Field Documentation

## ◆ AHBCLK

CLK_T::AHBCLK

[0x0004] AHB Devices Clock Enable Control Register

AHBCLK

Offset: 0x04 AHB Devices Clock Enable Control Register

Bits | Field | Descriptions
[0] | GPIOCKEN | GPIO Controller Clock Enable Control 0 = GPIO peripheral clock Disabled. 1 = GPIO peripheral clock Enabled.
[1] | PDMACKEN | PDMA Controller Clock Enable Bit 0 = PDMA peripheral clock Disabled. 1 = PDMA peripheral clock Enabled.
[2] | ISPCKEN | Flash ISP Controller Clock Enable Bit 0 = Flash ISP peripheral clock Disabled. 1 = Flash ISP peripheral clock Enabled.
[4] | SRAMCKEN | SRAM Controller Clock Enable Control Bit 0 = SRAM peripheral clock Disabled. 1 = SRAM peripheral clock Enabled.
[5] | STCKEN | System Tick Clock Enable Control Bit 0 = System Tick Clock Disabled. 1 = System Tick Clock Enabled.

Definition at line 4902 of file Nano103.h.

## ◆ APBCLK

CLK_T::APBCLK

[0x0008] APB Devices Clock Enable Control Register

APBCLK

Offset: 0x08 APB Devices Clock Enable Control Register

Bits | Field | Descriptions
[0] | WDTCKEN | Watchdog Timer Clock Enable Control This is a protected register. Please refer to open lock sequence to program it. This bit is used to control the WDT APB clock only, The WDT engine Clock Source is from LIRC. 0 = Watchdog Timer Clock Disabled. 1 = Watchdog Timer Clock Enabled.
[1] | RTCCKEN | Real-time-clock Clock Enable Control This bit is used to control the RTC APB clock only, The RTC engine Clock Source is from LXT. 0 = Real-time-clock Clock Disabled. 1 = Real-time-clock Clock Enabled.
[2] | TMR0CKEN | Timer0 Clock Enable Control 0 = Timer0 Clock Disabled. 1 = Timer0 Clock Enabled.
[3] | TMR1CKEN | Timer1 Clock Enable Control 0 = Timer1 Clock Disabled. 1 = Timer1 Clock Enabled.
[4] | TMR2CKEN | Timer2 Clock Enable Control 0 = Timer2 Clock Disabled. 1 = Timer2 Clock Enabled.
[5] | TMR3CKEN | Timer3 Clock Enable Control 0 = Timer3 Clock Disabled. 1 = Timer3 Clock Enabled.
[6] | CLKOCKEN | ClocK Output Clock Enable Control 0 = Clock Output Clock Disabled. 1 = Clock Output Clock Enabled.
[8] | I2C0CKEN | I2C0 Clock Enable Control 0 = I2C0 Clock Disabled. 1 = I2C0 Clock Enabled.
[9] | I2C1CKEN | I2C1 Clock Enable Control 0 = I2C1 Clock Disabled. 1 = I2C1 Clock Enabled.
[11] | ACMP0CKEN | ACMP0 Clock Enable Control 0 = ACMP0 Clock Disabled. 1 = ACMP0 Clock Enabled.
[12] | SPI0CKEN | SPI0 Clock Enable Control 0 = SPI0 Clock Disabled. 1 = SPI0 Clock Enabled.
[13] | SPI1CKEN | SPI1 Clock Enable Control 0 = SPI1 Clock Disabled. 1 = SPI1 Clock Enabled.
[14] | SPI2CKEN | SPI2 Clock Enable Control 0 = SPI2 Clock Disabled. 1 = SPI2 Clock Enabled.
[15] | SPI3CKEN | SPI3 Clock Enable Control 0 = SPI3 Clock Disabled. 1 = SPI3 Clock Enabled.
[16] | UART0CKEN | UART0 Clock Enable Control 0 = UART0 Clock Disabled. 1 = UART0 Clock Enabled.
[17] | UART1CKEN | UART1 Clock Enable Control 0 = UART1 Clock Disabled. 1 = UART1 Clock Enabled.
[20] | PWM0CKEN | PWM0 Clock Enable Control 0 = PWM0 Clock Disabled. 1 = PWM0 Clock Enabled.
[28] | ADCCKEN | Analog-digital-converter (ADC) Clock Enable Control 0 = ADC Clock Disabled. 1 = ADC Clock Enabled.
[30] | SC0CKEN | SmartCard 0 Clock Enable Control 0 = SmartCard 0 Clock Disabled. 1 = SmartCard 0 Clock Enabled.
[31] | SC1CKEN | SmartCard 1 Clock Enable Control 0 = SmartCard 1 Clock Disabled. 1 = SmartCard 1 Clock Enabled.

Definition at line 4903 of file Nano103.h.

## ◆ APBDIV

CLK_T::APBDIV

[0x0034] APB Clock Divider

APBDIV

Offset: 0x34 APB Clock Divider

Bits | Field | Descriptions
[2:0] | APB0DIV | APB0 Clock Divider APB0 PCLK0 can be divided from HCLK. 000: PCLK0 = HCLK. 001: PCLK0 = 1/2 HCLK. 010: PCLK0 = 1/4 HCLK. 011: PCLK0 = 1/8 HCLK. 100: PCLK0 = 1/16 HCLK. Others: PCLK0 = HCLK.
[6:4] | APB1DIV | APB1 Clock Divider APB1 PCLK1 can be divided from HCLK. 000: PCLK1 = HCLK. 001: PCLK1 = 1/2 HCLK. 010: PCLK1 = 1/4 HCLK. 011: PCLK1 = 1/8 HCLK. 100: PCLK1 = 1/16 HCLK. Others: PCLK1 = HCLK.

Definition at line 4916 of file Nano103.h.

## ◆ CDLOWB

CLK_T::CDLOWB

[0x0048] Clock Frequency Detector Lower Boundary Register

CDLOWB

Offset: 0x48 Clock Frequency Detector Lower Boundary Register

Bits | Field | Descriptions
[10:0] | LOWERBD | HXT Clock Frequency Detector Lower Boundary The bits define the low value of frequency monitor window. When HXT frequency monitor value lower than this register, the HXT frequency detect fail interrupt flag will set to 1.

Definition at line 4921 of file Nano103.h.

## ◆ CDUPB

CLK_T::CDUPB

[0x0044] Clock Frequency Detector Upper Boundary Register

CDUPB

Offset: 0x44 Clock Frequency Detector Upper Boundary Register

Bits | Field | Descriptions
[10:0] | UPERBD | HXT Clock Frequency Detector Upper Boundary The bits define the high value of frequency monitor window. When HXT frequency monitor value higher than this register, the HXT frequency detect fail interrupt flag will set to 1.

Definition at line 4920 of file Nano103.h.

## ◆ CLKDCTL

CLK_T::CLKDCTL

[0x0038] Clock Fail Detector Control Register

CLKDCTL

Offset: 0x38 Clock Fail Detector Control Register

Bits | Field | Descriptions
[0] | HXTFDEN | HXT Clock Fail Detector Enable Bit 0 = 4~32 MHz external high speed crystal oscillator (HXT) clock fail Detector Disabled. 1 = 4~32 MHz external high speed crystal oscillator (HXT) clock fail Detector Enabled.
[1] | LXTFDEN | LXT Clock Fail Detector Enable Bit 0 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail Detector Disabled. 1 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail Detector Enabled.
[2] | HXTFQDEN | HXT Clock Frequency Monitor Enable Bit 0 = 4~32 MHz external high speed crystal oscillator (HXT) clock frequency monitor Disabled. 1 = 4~32 MHz external high speed crystal oscillator (HXT) clock frequency monitor Enabled.

Definition at line 4917 of file Nano103.h.

## ◆ CLKDIE

CLK_T::CLKDIE

[0x003c] Clock Fail Detector Interrupt Enable Register

CLKDIE

Offset: 0x3C Clock Fail Detector Interrupt Enable Register

Bits | Field | Descriptions
[0] | HXTFIEN | HXT Clock Fail Interrupt Enable Bit 0 = 4~32 MHz external high speed crystal oscillator (HXT) clock fail interrupt Disabled. 1 = 4~32 MHz external high speed crystal oscillator (HXT) clock fail interrupt Enabled.
[1] | LXTFIEN | LXT Clock Fail Interrupt Enable Bit 0 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail interrupt Disabled. 1 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail interrupt Enabled.
[2] | HXTFQIEN | HXT Clock Frequency Monitor Interrupt Enable Bit 0 = 4~32 MHz external high speed crystal oscillator (HXT) clock frequency monitor fail interrupt Disabled. 1 = 4~32 MHz external high speed crystal oscillator (HXT) clock frequency monitor fail interrupt Enabled.

Definition at line 4918 of file Nano103.h.

## ◆ CLKDIV0

CLK_T::CLKDIV0

[0x001c] Clock Divider Number Register 0

CLKDIV0

Offset: 0x1C Clock Divider Number Register 0

Bits | Field | Descriptions
[3:0] | HCLKDIV | HCLK Clock Divide Number From HCLK Clock Source HCLK clock frequency = (HCLK clock source frequency) / (HCLKDIV + 1).
[11:8] | UART0DIV | UART0 Clock Divide Number From UART Clock Source The UART0 clock frequency = (UART0 Clock Source frequency) / (UART0DIV + 1).
[15:12] | UART1DIV | UART1 Clock Divide Number From UART Clock Source The UART1 clock frequency = (UART1 Clock Source frequency) / (UART1DIV + 1).
[23:16] | ADCDIV | ADC Clock Divide Number From ADC Clock Source ADC clock frequency = (ADC clock source frequency) / (ADCDIV + 1).
[31:28] | SC0DIV | SC0 Clock Divide Number From SC0 Clock Source SC0 clock frequency = (SC0 clock source frequency) / (SC0DIV + 1).

Definition at line 4908 of file Nano103.h.

## ◆ CLKDIV1

CLK_T::CLKDIV1

[0x0020] Clock Divider Number Register 1

CLKDIV1

Offset: 0x20 Clock Divider Number Register 1

Bits | Field | Descriptions
[3:0] | SC1DIV | SC 1 Clock Divide Number From SC 1 Clock Source The SC 1 clock frequency = (SC 1 Clock Source frequency) / (SC1DIV + 1).
[11:8] | TMR0DIV | Timer0 Clock Divide Number From Timer0 Clock Source The Timer0 clock frequency = (Timer0 Clock Source frequency) / (TMR0DIV + 1).
[15:12] | TMR1DIV | Timer1 Clock Divide Number From Timer1 Clock Source The Timer1 clock frequency = (Timer1 Clock Source frequency) / (TMR1DIV + 1).
[19:16] | TMR2DIV | Timer2 Clock Divide Number From Timer2 Clock Source The Timer2 clock frequency = (Timer2 Clock Source frequency) / (TMR2DIV + 1).
[23:20] | TMR3DIV | Timer3 Clock Divide Number From Timer3 Clock Source The Timer3 clock frequency = (Timer3 Clock Source frequency) / (TMR3DIV + 1).

Definition at line 4909 of file Nano103.h.

## ◆ CLKDSTS

CLK_T::CLKDSTS

[0x0040] Clock Fail Detector Status Register

CLKDSTS

Offset: 0x40 Clock Fail Detector Status Register

Bits | Field | Descriptions
[0] | HXTFIF | HXT Clock Fail Interrupt Flag 0 = 4~32 MHz external high speed crystal oscillator (HXT) clock is normal. 1 = 4~32 MHz external high speed crystal oscillator (HXT) clock stops. Note: Write 1 to clear the bit to 0.
[1] | LXTFIF | LXT Clock Fail Interrupt Flag 0 = 32.768 kHz external low speed crystal oscillator (LXT) clock is normal. 1 = 32.768 kHz external low speed crystal oscillator (LXT) stops. Note: Write 1 to clear the bit to 0.
[2] | HXTFQIF | HXT Clock Frequency Monitor Interrupt Flag 0 = 4~32 MHz external high speed crystal oscillator (HXT) clock is normal. 1 = 4~32 MHz external high speed crystal oscillator (HXT) clock frequency is abnormal. Note: Write 1 to clear the bit to 0.

Definition at line 4919 of file Nano103.h.

## ◆ CLKOCTL

CLK_T::CLKOCTL

[0x0028] Clock Output Control Register

CLKOCTL

Offset: 0x28 Clock Output Control Register

Bits | Field | Descriptions
[3:0] | FREQSEL | Clock Output Frequency Selection The formula of output frequency is Fout = Fin/2(N+1). Fin is the input clock frequency. Fout is the frequency of divider output clock. N is the 4-bit value of FREQSEL[3:0].
[4] | CLKOEN | Clock Output Enable Bit 0 = Clock Output function Disabled. 1 = Clock Output function Enabled.
[5] | DIV1EN | Clock Output Divide One Enable Bit 0 = Clock Output will output clock with source frequency divided by FREQSEL. 1 = Clock Output will output clock with source frequency.

Definition at line 4911 of file Nano103.h.

## ◆ CLKSEL0

CLK_T::CLKSEL0

[0x0010] Clock Source Select Control Register 0

CLKSEL0

Offset: 0x10 Clock Source Select Control Register 0

Bits | Field | Descriptions
[2:0] | HCLKSEL | HCLK Clock Source Selection (Write Protect) Before clock switching, the related clock sources (both pre-select and new-select) must be turned on. 000 = Clock source from HXT. 001 = Clock source from LXT. 010 = Clock source from PLL. 011 = Clock source from LIRC. 100= Clock source from HIRC1 or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting. Others = Clock source from MIRC. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[3] | HIRCSEL | HIRC Source Selection 0 = Clock source from HIRC0 (12~16MHz). 1 = Clock source from HIRC1 (36MHz).
[4] | ISPSEL | ISP Clock Source Selection 0 = Clock source from HIRC1 or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting. 1 = Clock source from MIRC.

Definition at line 4905 of file Nano103.h.

## ◆ CLKSEL1

CLK_T::CLKSEL1

[0x0014] Clock Source Select Control Register 1

CLKSEL1

Offset: 0x14 Clock Source Select Control Register 1

Bits | Field | Descriptions
[2:0] | UART0SEL | UART0 Clock Source Selection 000 = Clock source from 4~32 MHz external high speed crystal oscillator (HXT). 001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 010 = Clock source from PLL. 011 = Clock source from 36 MHz internal high speed RC oscillator (HIRC1) or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting. Others = Clock source from 4 MHz internal medium speed RC oscillator (MIRC).
[4] | PWM0SEL | PWM0 Clock Source Selection 0 = Clock source from PLL. 1 = Clock source from PCLK0.
[10:8] | TMR0SEL | Timer0 Clock Source Selection 000 = Clock source from 4~32 MHz external high speed crystal oscillator (HXT). 001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 010 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). 011 = Clock source from external clock pin. 100 = Clock source from 36 MHz internal high speed RC oscillator (HIRC1) or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting. 101 = Clock source from 4 MHz internal medium speed RC oscillator (MIRC). Others = Clock source from HCLK.
[14:12] | TMR1SEL | Timer1 Clock Source Selection 000 = Clock source from 4~32 MHz external high speed crystal oscillator (HXT). 001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 010 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). 011 = Clock source from external clock pin. 100 = Clock source from 36 MHz internal high speed RC oscillator (HIRC1) or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting. 101 = Clock source from 4 MHz internal medium speed RC oscillator (MIRC). Others = Clock source from HCLK.
[21:19] | ADCSEL | ADC Clock Source Selection 000 = Clock source from 4~32 MHz external high speed crystal oscillator (HXT). 001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 010 = Clock source from PLL. 011 = Clock source from 36 MHz internal high speed RC oscillator (HIRC1) or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting. 100 = Clock source from 4 MHz internal medium speed RC oscillator (MIRC). Others = Clock source from HCLK.
[25:24] | SPI0SEL | SPI0 Clock Source Selection 00 = Clock source from PLL. 01 = Clock source from HCLK. 10 = Clock source from 4~32 MHz external high speed crystal oscillator (HXT). 11 = Clock source from 36 MHz internal high speed RC oscillator (HIRC1) or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting.
[27:26] | SPI2SEL | SPI2 Clock Source Selection 00 = Clock source from PLL. 01 = Clock source from HCLK. 10 = Clock source from 4~32 MHz external high speed crystal oscillator (HXT). 11 = Clock source from 36 MHz internal high speed RC oscillator (HIRC1) or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting.
[29:28] | WDTSEL | WDT Clock Source Selection 00 = reserved. 01 = Clock source from LXT. 10 = Clock source from HCLK/2048. 11 = Clock source from LIRC
[31:30] | WWDTSEL | WDT Clock Source Selection 00 = reserved. 01 = reserved. 10 = Clock source from HCLK/2048. 11 = Clock source from LIRC

Definition at line 4906 of file Nano103.h.

## ◆ CLKSEL2

CLK_T::CLKSEL2

[0x0018] Clock Source Select Control Register 2

CLKSEL2

Offset: 0x18 Clock Source Select Control Register 2

Bits | Field | Descriptions
[2:0] | UART1SEL | UART1 Clock Source Selection 000 = Clock source from 4~32 MHz external high speed crystal oscillator (HXT). 001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 010 = Clock source from PLL. 011 = Clock source from 36 MHz internal high speed RC oscillator (HIRC1) or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting. Others = Clock source from 4 MHz internal medium speed RC oscillator (MIRC).
[6:4] | CLKOSEL | Clock Divider Clock Source Selection 000 = Clock source from 4~32 MHz external high speed crystal oscillator (HXT). 001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 010 = Clock source from HCLK. 011 = Clock source from 36 MHz internal high speed RC oscillator (HIRC1) or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting. Others = Clock source from 4 MHz internal medium speed RC oscillator (MIRC).
[10:8] | TMR2SEL | Timer2 Clock Source Selection 000 = Clock source from 4~32 MHz external high speed crystal oscillator (HXT). 001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 010 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). 011 = Clock source from external clock pin. 100 = Clock source from 36 MHz internal high speed RC oscillator (HIRC1) or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting. 101 = Clock source from 4 MHz internal medium speed RC oscillator (MIRC) Others = Clock source from HCLK.
[14:12] | TMR3SEL | Timer3 Clock Source Selection 000 = Clock source from 4~32 MHz external high speed crystal oscillator (HXT). 001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 010 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). 011 = Clock source from external clock pin. 100 = Clock source from 36 MHz internal high speed RC oscillator (HIRC1) or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting. 101 = Clock source from 4 MHz internal medium speed RC oscillator (MIRC). Others = Clock source from HCLK.
[18:16] | SC0SEL | SC0 Clock Source Selection 000 = Clock source from 4~32 MHz external high speed crystal oscillator (HXT). 001 = Clock source from PLL. 010 = Clock source from 36 MHz internal high speed RC oscillator (HIRC1) or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting. 011 = Clock source from 4 MHz internal medium speed RC oscillator (MIRC). Others = Clock source from HCLK.
[22:20] | SC1SEL | SC1 Clock Source Selection 000 = Clock source from 4~32 MHz external high speed crystal oscillator (HXT). 001 = Clock source from PLL. 010 = Clock source from 36 MHz internal high speed RC oscillator (HIRC1) or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting. 011 = Clock source from 4 MHz internal medium speed RC oscillator (MIRC). Others = Clock source from HCLK.
[25:24] | SPI1SEL | SPI1 Clock Source Selection 00 = Clock source from PLL. 01 = Clock source from HCLK. 10 = Clock source from 4~32 MHz external high speed crystal oscillator (HXT). 11 = Clock source from 36 MHz internal high speed RC oscillator (HIRC1) or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting.
[27:26] | SPI3SEL | SPI3 Clock Source Selection 00 = Clock source from PLL. 01 = Clock source from HCLK. 10 = Clock source from 4~32 MHz external high speed crystal oscillator (HXT). 11 = Clock source from 36 MHz internal high speed RC oscillator (HIRC1) or HIRC0 depend on HIRCSEL(CLK_CLKSEL0[3]) setting.

Definition at line 4907 of file Nano103.h.

## ◆ PLLCTL

CLK_T::PLLCTL

[0x0024] PLL Control Register

PLLCTL

Offset: 0x24 PLL Control Register

Bits | Field | Descriptions
[5:0] | PLLMLP | PLL Multiple 000000: Reserved 000001: X1 000010: X2 000011: X3 000100: X4 ... 010000:X16 ... 100000: X32 100100: X36 0thers: Reserved PLL output frequency: PLL input frequency * PLLMLP. PLL output frequency range: 16MHz ~ 36MHz
[13:8] | INDIV | PLL Input Source Divider The PLL input clock frequency = (PLL Clock Source frequency) / (INDIV + 1). PLL input clock frequency range: 0.8MHz ~ 2MHz
[15:14] | STBTSEL | PLL Stable Time Selection 00 = 100 cycle time of input clock source. 01 = 120 cycle time of input clock source. 10 = 180 cycle time of input clock source. 11 = 240 cycle time of input clock source.
[16] | PD | Power-down Mode If set the PDEN bit 1 in CLK_PWRCTL register, the PLL will enter Power-down mode too 0 = PLL is in normal mode. 1 = PLL is in power-down mode (default).
[18:17] | PLLSRC | PLL Source Clock Select 00 = PLL source clock from HXT. 01 = PLL source clock from HIRC0 or HIRC1. 10 = PLL source clock from MIRC 11 = reserved.

Definition at line 4910 of file Nano103.h.

## ◆ PWRCTL

CLK_T::PWRCTL

[0x0000] System Power-down Control Register

PWRCTL

Offset: 0x00 System Power-down Control Register

Bits | Field | Descriptions
[0] | HXTEN | HXT Enable Bit (Write Protect) 0 = 4~32 MHz external high speed crystal (HXT) Disabled. 1 = 4~32 MHz external high speed crystal (HXT) Enabled. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[1] | LXTEN | LXT Enable Bit (Write Protect) 0 = 32.768 kHz external low speed crystal (LXT) Disabled. 1 = 32.768 kHz external low speed crystal (LXT) Enabled. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[2] | HIRC0EN | HIRC0 Enable Bit (Write Protect) 0 = 12~16 MHz internal high speed RC oscillator (HIRC0) Disabled. 1 = 12~16 MHz internal high speed RC oscillator (HIRC0) Enabled. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[3] | LIRCEN | LIRC Enable Bit (Write Protect) 0 = 10 kHz internal low speed RC oscillator (LIRC) Disabled. 1 = 10 kHz internal low speed RC oscillator (LIRC) Enabled. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[4] | PDWKDLY | Enable the Wake-up Delay Counter (Write Protect) When the chip wakes up from Power-down mode, the clock control will delay 4096 clock cycles to wait system clock stable when chip works at 4~32 MHz external high speed crystal oscillator (HXT). 0 = Clock cycles delay Disabled. 1 = Clock cycles delay Enabled. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[5] | PDWKIEN | Power-Down Mode Wake-Up Interrupt Enable Bit (Write Protect) 0 = Power-down mode wake-up interrupt Disabled. 1 = Power-down mode wake-up interrupt Enabled. Note1: The interrupt (EINT0~1, GPIO,, UART0~1, WDT, ACMP01, BOD, RTC, TMR0~3, I2C0~1 or SPI0 ~3 )will occur when PDWKIEN are high. Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
[6] | PDEN | System Power-Down Enable (Write Protect) When this bit is set to 1, Power-down mode is enabled and chip Power-down behavior will depend on the PDWTCPU bit. (a) If the PDWTCPU is 0, then the chip enters Power-down mode immediately after the PDEN bit set (default) (b) if the PDWTCPU is 1, then the chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode. When chip wakes up from Power-down mode, this bit is auto cleared Users need to set this bit again for next Power-down. In Power-down mode, HXT and the HIRC will be disabled in this mode, but LXT and LIRC are not controlled by Power-down mode. In Power-down mode, the PLL and system clock are disabled, and ignored the clock source selection The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from LXT or LIRC. 0 = Chip operating normally or chip in idle mode because of WFI command. 1 = Chip enters Power-down mode instant or wait CPU sleep command WFI. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[8] | HXTSLTYP | HXT Mode Selection (Write Protect) 0 = High frequency crystal loop back path Disabled. It is used for external oscillator. 1 = High frequency crystal loop back path Enabled. It is used for external crystal. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[12:10] | HXTGAIN | HXT Gain Control Bit (Write Protect) Gain control is used to enlarge the gain of crystal to make sure crystal wok normally If gain control is enabled, crystal will consume more power than gain control off. 000= HXT frequency is lower than from 4 MHz. 001 = HXT frequency is from 4 MHz to 8 MHz. 010 = HXT frequency is from 8 MHz to 12 MHz. 011= HXT frequency is from 12 MHz to 16 MHz. 100 = HXT frequency is from 16 MHz to 24 MHz. 101 = HXT frequency is from 24 MHz to 32 MHz. 110 = HXT frequency is from 32 MHz to 36 MHz. 111 = HXT frequency is higher than 36 MHz. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[13] | HIRC0FSEL | HIRC0 Output Frequency Select Bit 0 = HIRC0 will output 12MHz clock. 1 = HIRC0 will output 16MHz Clock.
[14] | HIRC0FSTOP | HIRC0 Stop Output When Frequency Changes (Write Protect) 0 = HIRC0 will continue to output when HIRC frequency changes. 1 = HIRC0 will suppress to output during first 16 clocks when HIRC frequency change. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[24] | HIRC1EN | HIRC1 Enable Bit (Write Protect) 0 = 36 MHz internal high speed RC oscillator (HIRC1) Disabled. 1 = 36 MHz internal high speed RC oscillator (HIRC1) Enabled. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[25] | MIRCEN | MIRC Enable Bit (Write Protect) 0 = 4 MHz internal medium speed RC oscillator (MIRC) Disabled. 1 = 4 MHz internal medium speed RC oscillator (MIRC) Enabled. Note: This bit is write protected. Refer to the SYS_REGLCTL register.

Definition at line 4901 of file Nano103.h.

## ◆ STATUS

CLK_T::STATUS

[0x000c] Clock status monitor Register

STATUS

Offset: 0x0C Clock status monitor Register

Bits | Field | Descriptions
[0] | HXTSTB | HXT Clock Source Stable Flag (Read Only) 0 = 4~36 MHz external high speed crystal oscillator (HXT) clock is not stable or disabled. 1 = 4~36 MHz external high speed crystal oscillator (HXT) clock is stable and enabled.
[1] | LXTSTB | LXT Clock Source Stable Flag (Read Only) 0 = 32.768 kHz external low speed crystal oscillator (LXT) clock is not stable or disabled. 1 = 32.768 kHz external low speed crystal oscillator (LXT) clock is stabled and enabled.
[2] | PLLSTB | Internal PLL Clock Source Stable Flag (Read Only) 0 = Internal PLL clock is not stable or disabled. 1 = Internal PLL clock is stable and enabled.
[3] | LIRCSTB | LIRC Clock Source Stable Flag (Read Only) 0 = 10 kHz internal low speed RC oscillator (LIRC) clock is not stable or disabled. 1 = 10 kHz internal low speed RC oscillator (LIRC) clock is stable and enabled.
[4] | HIRC0STB | HIRC0 Clock Source Stable Flag (Read Only) 0 = 12~16 MHz internal high speed RC oscillator (HIRC0) clock is not stable or disabled. 1 = 12~16 MHz internal high speed RC oscillator (HIRC0) clock is stable and enabled.
[5] | HIRC1STB | HIRC Clock Source Stable Flag (Read Only) 0 = 36 MHz internal high speed RC oscillator (HIRC1) clock is not stable or disabled. 1 = 36 MHz internal high speed RC oscillator (HIRC1) clock is stable and enabled.
[6] | MIRCSTB | MIRC Clock Source Stable Flag (Read Only) 0 = 4 MHz internal medium speed RC oscillator (MIRC) clock is not stable or disabled. 1 = 4 MHz internal medium speed RC oscillator (MIRC) clock is stable and enabled.
[7] | CLKSFAIL | Clock Switching Fail Flag (Read Only) This bit is updated when software switches system clock source If switch target clock is stable, this bit will be set to 0 If switch target clock is not stable, this bit will be set to 1. 0 = Clock switching success. 1 = Clock switching failure.

Definition at line 4904 of file Nano103.h.

## ◆ WKINTSTS

CLK_T::WKINTSTS

[0x0030] Wake-up Interrupt Status

WKINTSTS

Offset: 0x30 Wake-up Interrupt Status

Bits | Field | Descriptions
[0] | PDWKIF | Wake-up Interrupt Status in Chip Power-down Mode This bit indicates that some event resumes chip from Power-down mode The status is set if external interrupts, UART, GPIO, RTC, USB, SPI, Timer, WDT, and BOD wake-up occurred. Write 1 to clear this bit.

Definition at line 4915 of file Nano103.h.

The documentation for this struct was generated from the following file:

- C:/Users/yachen/workzone/bsp/nano103bsp/Library/Device/Nuvoton/Nano103/Include/Nano103.h