| Nano103 BSP V3.01.002 The Board Support Package for Nano103 Series

Data Fields
SC_T Struct Reference

`#include <Nano103.h>`

## Data Fields
__IO uint32_t | DAT
__IO uint32_t | CTL
__IO uint32_t | ALTCTL
__IO uint32_t | EGT
__IO uint32_t | RXTOUT
__IO uint32_t | ETUCTL
__IO uint32_t | INTEN
__IO uint32_t | INTSTS
__IO uint32_t | STATUS
__IO uint32_t | PINCTL
__IO uint32_t | TMRCTL0
__IO uint32_t | TMRCTL1
__IO uint32_t | TMRCTL2
__IO uint32_t | UARTCTL
__IO uint32_t | ACTCTL

## Detailed Description

    @addtogroup SC Smart Card Host Interface Controller(SC)
    Memory Mapped Structure for SC Controller

Definition at line 20422 of file Nano103.h.

## Field Documentation

## ◆ ACTCTL

SC_T::ACTCTL

[0x0040] SC Activation Control Register.

ACTCTL

Offset: 0x40 SC Activation Control Register.

Bits | Field | Descriptions
[4:0] | T1EXT | Configurable Cycles T1EXT in Hardware Activation This field provide the configurable cycles to extend the Activation time T1 The cycle scaling factor is 2048. Extend cycles = (filled value * 2048) cycles. Refer to SC Activation Sequence in Figure 6.15-4 SC Activation Sequence. For example, SCLK = 4Mhz, each cycle = 0.25us,. Filled 20 to this field Extend time = 20*2048*0.25us = 10.24 ms. Note: setting 0 to this field conforms to the protocol ISO/IEC 7816-3

Definition at line 21653 of file Nano103.h.

## ◆ ALTCTL

SC_T::ALTCTL

[0x0008] SC Alternate Control Register.

ALTCTL

Offset: 0x08 SC Alternate Control Register.

Bits | Field | Descriptions
[0] | TXRST | TX Software Reset When TXRST is set, all the bytes in the transmit buffer and TX internal state machine will be cleared. 0 = No effect. 1 = Reset the TX internal state machine and pointers. Note: This bit will be auto cleared after reset is complete.
[1] | RXRST | Rx Software Reset When RXRST is set, all the bytes in the receiver buffer and Rx internal state machine will be cleared. 0 = No effect. 1 = Reset the Rx internal state machine and pointers. Note: This bit will be auto cleared after reset is complete.
[2] | DACTEN | Deactivation Sequence Generator Enable Bit This bit enables SC controller to initiate the card by deactivation sequence 0 = No effect. 1 = Deactivation sequence generator Enabled. Note1: When the deactivation sequence completed, this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to 1. Note2: This field will be cleared by TXRST (SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]).Thus,do not fill in this bit, TXRST, and RXRST at the same time. Note3: If SCEN (SC_CTL[0]) is not enabled, this filed cannot be programmed.
[3] | ACTEN | Activation Sequence Generator Enable Bit This bit enables SC controller to initiate the card by activation sequence 0 = No effect. 1 = Activation sequence generator Enabled. Note1: When the activation sequence completed, this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to 1, RXOFF(SC_CTL[2]) will be clear to 0. Note2: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]).Thus,do not fill in this bit, TXRST(SC_ALTCTL[0]), and RXRST(SC_ALTCTL[1]) at the same time. Note3: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
[4] | WARSTEN | Warm Reset Sequence Generator Enable Bit This bit enables SC controller to initiate the card by warm reset sequence 0 = No effect. 1 = Warm reset sequence generator Enabled. Note1: When the warm reset sequence completed, this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to 1, RXOFF(SC_CTL[2]) will be clear to 0. Note2: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]).Thus,do not fill in this bit, TXRST, and RXRST at the same time. Note3: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
[5] | CNTEN0 | Internal Timer0 Start Enable Bit This bit enables Timer 0 to start counting Software can fill 0 to stop it and set 1 to reload and count. 0 = Stops counting. 1 = Start counting. Note1: This field is used for internal 24 bit timer when TMRSEL (SC_CTL[14:13]) = 11,01,10. Note2: If the operation mode is not in auto-reload mode (SC_TMRCTL0[26] = 0), this bit will be auto-cleared by hardware. Note3: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
[6] | CNTEN1 | Internal Timer1 Start Enable Bit This bit enables Timer 1 to start counting Software can fill 0 to stop it and set 1 to reload and count. 0 = Stops counting. 1 = Start counting. Note1: This field is used for internal 8 bit timer when TMRSEL(SC_CTL[14:13]) = 11 Do not fill in CNTEN1 when TMRSEL(SC_CTL[14:13]) = 00 or TMRSEL(SC_CTL[14:13]) = 01. Note2: If the operation mode is not in auto-reload mode (SC_TMRCTL1[26] = 0), this bit will be auto-cleared by hardware. Note3: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
[7] | CNTEN2 | Internal Timer2 Start Enable Bit This bit enables Timer 2 to start counting Software can fill 0 to stop it and set 1 to reload and count. 0 = Stops counting. 1 = Start counting. Note1: This field is used for internal 8 bit timer when TMRSEL(SC_CTL[14:13]) = 11 Do not fill in CNTEN2 when TMRSEL(SC_CTL[14:13])= 00 or TMRSEL(SC_CTL[14:13]) = 01 or TMRSEL(SC_CTL[14:13]) = 10. Note2: If the operation mode is not in auto-reload mode (SC_TMRCTL2[26] = 0), this bit will be auto-cleared by hardware. Note3: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
[9:8] | INITSEL | Initial Timing Selection This fields indicates the timing of hardware initial state (activation or warm-reset or deactivation). Unit: SC clock Activation: Refer to SC Activation Sequence in Figure 6.15-4 SC Activation Sequence. Warm-reset: Refer to Warm-Reset Sequence in Figure 6.15-5 SC Warm Reset Sequence Deactivation: Refer to Deactivation Sequence in Figure 6.15-6 SC Deactivation Sequence Note: When set Activation and Warm reset in mode 11, it may have deviation at most 128 cycles.
[12] | RXBGTEN | Receiver Block Guard Time Function Enable Bit 0 = Receiver block guard time function Disabled. 1 = Receiver block guard time function Enabled.
[13] | ACTSTS0 | Internal Timer0 Active State (Read Only) This bit indicates the timer counter status of timer0. 0 = Timer0 is not active. 1 = Timer0 is active. Note: Timer0 is active does not always mean timer0 is counting the CNT(SC_TMRCTL0[23:0]).
[14] | ACTSTS1 | Internal Timer1 Active State (Read Only) This bit indicates the timer counter status of timer1. 0 = Timer1 is not active. 1 = Timer1 is active. Note: Timer1 is active does not always mean timer1 is counting the CNT(SC_TMRCTL1[7:0]).
[15] | ACTSTS2 | Internal Timer2 Active State (Read Only) This bit indicates the timer counter status of timer2. 0 = Timer2 is not active. 1 = Timer2 is active. Note: Timer2 is active does not always mean timer2 is counting the CNT(SC_TMRCTL2[7:0]).
[16] | OUTSEL | Smartcard Data Pin Output Mode Selection Use this bit to select smartcard data pin output mode. 0 = Quasi mode. 1 = Open-drain mode.

Definition at line 21638 of file Nano103.h.

## ◆ CTL

SC_T::CTL

[0x0004] SC Control Register.

CTL

Offset: 0x04 SC Control Register.

Bits | Field | Descriptions
[0] | SCEN | SC Engine Enable Bit Set this bit to 1 to enable SC operation If this bit is cleared, SC will force all transition to IDLE state Note1: SCEN must be set to 1 before filling in other registers, or smart card will not work properly. Note2: If SCEN is activated, all function can work correctly If SCEN is not activated, when CPU write data to SMC, only Flip-flop which works in PCLK domain will turn on for two PCLK cycle, Flip-flop working in SCLK domain will not be turn on.
[1] | RXOFF | RX Transition Disable Bit 0 = The receiver Enabled. 1 = The receiver Disabled. Note1: If AUTOCEN (SC_CTL[3])is enabled, these fields must be ignored. Note2: After hardware activation and hardware warm reset are done, RXOFF is set to 0 automatically.
[2] | TXOFF | TX Transition Disable Bit 0 = The transceiver Enabled. 1 = The transceiver Disabled.
[3] | AUTOCEN | Auto Convention Enable Bit 0 = Auto-convention Disabled. 1 = Auto-convention Enabled When hardware receives TS in answer to reset state and the TS is direct convention, CONSEL(SC_CTL[5:4]) will be set to 00 automatically, otherwise if the TS is inverse convention, and CONSEL (SC_CTL[5:4]) will be set to 11. If software enables auto convention function, the setting step must be done before Answer to Reset state and the first data must be 0x3B or 0x3F After hardware received first data and stored it at buffer, hardware will decided the convention and change the CONSEL (SC_CTL[5:4]) bits automatically If the first data is not 0x3B or 0x3F, hardware will generate an interrupt INT_ACON_ERR (if ACERRIEN (SC_INTEN[10]) = 1 to CPU.
[5:4] | CONSEL | Convention Selection 00 = Direct convention. 01 = Reserved. 10 = Reserved. 11 = Inverse convention. Note: If AUTOCEN(SC_CTL[3]) is enabled, this field is ignored.
[7:6] | RXTRGLV | Rx Buffer Trigger Level When the number of bytes in the receiving buffer equals the RXTRGLV, the RDAIF will be set (if [RDAIEN](SC_INTEN[0]) is enabled, an interrupt will be generated). 00 = INTR_RDA Trigger Level with 01 Bytes. 01 = INTR_RDA Trigger Level with 02 Bytes. 10 = INTR_RDA Trigger Level with 03 Bytes. 11 = Reserved.
[12:8] | BGT | Block Guard Time (BGT) Block guard time means the minimum bit length between the leading edges of two consecutive characters between different transfer directions This field indicates the counter for the bit length of block guard time According to ISO7816-3, in T = 0 mode, software must fill 15 (real block guard time = 16.5) to this field; in T = 1 mode, software must fill 21 (real block guard time = 22.5) to it. Note: The real block guard time is BGT + 1.
[14:13] | TMRSEL | Timer Selection 00 = All internal timer function Disabled. 11 = Internal 24 bit timer and two 8 bit timers Enabled Software can configure them by setting SC_TMRCTL0 [23:0], SC_TMRCTL1 [7:0] and SC_TMRCTL2 [7:0]. Other configurations are reserved
[15] | NSB | Stop Bit Length This field indicates the length of stop bit. 0 = The stop bit length is 2 ETU. 1= The stop bit length is 1 ETU. Note: The default stop bit length is 2. SMC and UART adopt NSB to program the stop bit length.
[18:16] | RXRTY | RX Error Retry Count Number This field indicates the maximum number of receiver retries that are allowed when parity error has occurred Note1: The real retry number is RX_ERETRY + 1, so 8 is the maximum retry number. Note2: This field cannot be changed when RX_ERETRY_EN enabled The change flow is to disable RX_ETRTRY_EN first and then fill in new retry value.
[19] | RXRTYEN | RX Error Retry Enable Bit This bit enables receiver retry function when parity error has occurred. 0 = RX error retry function Disabled. 1 = RX error retry function Enabled. Note: Software must fill in the RXRTY value before enabling this bit.
[22:20] | TXRTY | TX Error Retry Count Number This field indicates the maximum number of transmitter retries that are allowed when parity error has occurred. Note1: The real retry number is TXRTY + 1, so 8 is the maximum retry number. Note2: This field cannot be changed when TXRTYEN enabled The change flow is to disable TXRTYEN first and then fill in new retry value.
[23] | TXRTYEN | TX Error Retry Enable Bit This bit enables transmitter retry function when parity error has occurred. 0 = TX error retry function Disabled. 1 = TX error retry function Enabled.
[25:24] | CDDBSEL | Card Detect De-bounce Selection This field indicates the card detect de-bounce selection. 00 = De-bounce sample card insert once per 384 (128 * 3) engine clocks and de-bounce sample card removal once per 128 engine clocks. Other configurations are reserved.
[30] | SYNC | SYNC Flag Indicator(Read Only) Due to synchronization, software should check this bit before writing a new value to RXRTY and TXRTY.SYNC flag is 0 = synchronizing is completion, user can write new data to RXRTY and TXRTY. 1 = Last value is synchronizing.

Definition at line 21637 of file Nano103.h.

## ◆ DAT

SC_T::DAT

[0x0000] SC Receive/Transmit Holding Buffer Register.

DAT

Offset: 0x00 SC Receive/Transmit Holding Buffer Register.

Bits | Field | Descriptions
[7:0] | DAT | Receive/Transmit Holding Buffer Write Operation: By writing data to DAT, the SC will send out an 8-bit data. Note: If SCEN(SC_CTL[0]) is not enabled, DAT cannot be programmed. Read Operation: By reading DAT, the SC will return an 8-bit received data.

Definition at line 21636 of file Nano103.h.

## ◆ EGT

SC_T::EGT

[0x000c] SC Extra Guard Time Register.

EGT

Offset: 0x0C SC Extra Guard Time Register.

Bits | Field | Descriptions
[7:0] | EGT | Extra Guard Time This field indicates the extra guard timer value. Note: The counter is ETU base .

Definition at line 21639 of file Nano103.h.

## ◆ ETUCTL

SC_T::ETUCTL

[0x0014] SC Element Time Unit Control Register.

ETUCTL

Offset: 0x14 SC Element Time Unit Control Register.

Bits | Field | Descriptions
[11:0] | ETURDIV | ETU Rate Divider The field indicates the clock rate divider. The real ETU is ETURDIV + 1. Note: Software can configure this field, but this field must be greater than 0x004.

Definition at line 21641 of file Nano103.h.

## ◆ INTEN

SC_T::INTEN

[0x0018] SC Interrupt Enable Control Register.

INTEN

Offset: 0x18 SC Interrupt Enable Control Register.

Bits | Field | Descriptions
[0] | RDAIEN | Receive Data Reach Interrupt Enable Bit This field is used to enable received data reaching trigger level RXTRGLV (SC_CTL[7:6]) interrupt. 0 = Receive data reach trigger level interrupt Disabled. 1 = Receive data reach trigger level interrupt Enabled.
[1] | TBEIEN | Transmit Buffer Empty Interrupt Enable Bit This field is used to enable transmit buffer empty interrupt. 0 = Transmit buffer empty interrupt Disabled. 1 = Transmit buffer empty interrupt Enabled.
[2] | TERRIEN | Transfer Error Interrupt Enable Bit This field is used to enable transfer error interrupt The transfer error states is at SC_STATUS register which includes receiver break error BEF(SC_STATUS[6]), frame error FEF(SC_STATUS[5]), parity error PEF(SC_STATUS[4]), receiver buffer overflow error RXOV(SC_STATUS[0]), transmit buffer overflow error TXOV(SC_STATUS[8]), receiver retry over limit error RXOVERR(SC_STATUS[22]) and transmitter retry over limit error TXOVERR (SC_STATUS[30]). 0 = Transfer error interrupt Disabled. 1 = Transfer error interrupt Enabled.
[3] | TMR0IEN | Timer0 Interrupt Enable Bit This field is used to enable TMR0 interrupt. 0 = Timer0 interrupt Disabled. 1 = Timer0 interrupt Enabled.
[4] | TMR1IEN | Timer1 Interrupt Enable Bit This field is used to enable the TMR1 interrupt. 0 = Timer1 interrupt Disabled. 1 = Timer1 interrupt Enabled.
[5] | TMR2IEN | Timer2 Interrupt Enable Bit This field is used to enable TMR2 interrupt. 0 = Timer2 interrupt Disabled. 1 = Timer2 interrupt Enabled.
[6] | BGTIEN | Block Guard Time Interrupt Enable Bit This field is used to enable block guard time interrupt. 0 = Block guard time Disabled. 1 = Block guard time Enabled.
[7] | CDIEN | Card Detect Interrupt Enable Bit This field is used to enable card detect interrupt. The card detect status is CINSERT(SC_STATUS[12]) 0 = Card detect interrupt Disabled. 1 = Card detect interrupt Enabled.
[8] | INITIEN | Initial End Interrupt Enable Bit This field is used to enable activation (ACTEN(SC_ALTCTL[3] = 1)), deactivation ((DACTEN SC_ALTCTL[2]) = 1) and warm reset (WARSTEN (SC_ALTCTL [4])) sequence interrupt. 0 = Initial end interrupt Disabled. 1 = Initial end interrupt Enabled.
[9] | RXTOIEN | Receiver Buffer Time-out Interrupt Enable Bit This field is used to enable receiver buffer time-out interrupt. 0 = Receiver buffer time-out interrupt Disabled. 1 = Receiver buffer time-out interrupt Enabled.
[10] | ACERRIEN | Auto Convention Error Interrupt Enable Bit This field is used to enable auto-convention error interrupt. 0 = Auto-convention error interrupt Disabled. 1 = Auto-convention error interrupt Enabled.

Definition at line 21642 of file Nano103.h.

## ◆ INTSTS

SC_T::INTSTS

[0x001c] SC Interrupt Status Register.

INTSTS

Offset: 0x1C SC Interrupt Status Register.

Bits | Field | Descriptions
[0] | RDAIF | Receive Data Reach Interrupt Status Flag (Read Only) This field is used for received data reaching trigger level RXTRGLV (SC_CTL[7:6]) interrupt status flag. Note: This field is the status flag of received data reaching RXTRGLV (SC_CTL[7:6]) If software reads data from SC_DAT and receiver buffer data byte number is less than RXTRGLV (SC_CTL[7:6]), this bit will be cleared automatically.
[1] | TBEIF | Transmit Buffer Empty Interrupt Status Flag (Read Only) This field is used for transmit buffer empty interrupt status flag. Note: This field is the status flag of transmit buffer empty state If software wants to clear this bit, software must write data to DAT(SC_DAT[7:0]) buffer and then this bit will be cleared automatically.
[2] | TERRIF | Transfer Error Interrupt Status Flag (Read Only) This field is used for transfer error interrupt status flag The transfer error states is at SC_STATUS register which includes receiver break error BEF(SC_STATUS[6]), frame error FEF(SC_STATUS[5], parity error PEF(SC_STATUS[4] and receiver buffer overflow error RXOV(SC_STATUS[0]), transmit buffer overflow error TXOV(SC_STATUS[8]), receiver retry over limit error RXOVERR(SC_STATUS[22] and transmitter retry over limit error TXOVERR(SC_STATUS[30]). Note: This field is the status flag of BEF(SC_STATUS[6]), FEF(SC_STATUS[5]), PEF(SC_STATUS[4]), RXOV(SC_STATUS[0]), TXOV(SC_STATUS[8]), RXOVERR(SC_STATUS[22]) or TXOVERR(SC_STATUS[30]) So, if software wants to clear this bit, software must write 1 to each field.
[3] | TMR0IF | Timer0 Interrupt Status Flag (Read Only) This field is used for TMR0 interrupt status flag. Note: This bit is read only, but it can be cleared by writing 1 to it.
[4] | TMR1IF | Timer1 Interrupt Status Flag (Read Only) This field is used for TMR1 interrupt status flag. Note: This bit is read only, but it can be cleared by writing 1 to it.
[5] | TMR2IF | Timer2 Interrupt Status Flag (Read Only) This field is used for TMR2 interrupt status flag. Note: This bit is read only, but it can be cleared by writing 1 to it.
[6] | BGTIF | Block Guard Time Interrupt Status Flag (Read Only) This field is used for block guard time interrupt status flag. Note1: This bit is valid when RXBGTEN (SC_ALTCTL[12]) is enabled. Note2: This bit is read only, but it can be cleared by writing u201C1u201D to it.
[7] | CDIF | Card Detect Interrupt Status Flag (Read Only) This field is used for card detect interrupt status flag The card detect status is CINSERT (SC_STATUS[12]) and CREMOVE(SC_STATUS[11]). Note: This field is the status flag of CINSERT(SC_STATUS[12]) or CREMOVE(SC_STATUS[11])] So if software wants to clear these bits, software must write 1 to these field.
[8] | INITIF | Initial End Interrupt Status Flag (Read Only) This field is used for activation (ACTEN(SC_ALTCTL[3])), deactivation (DACTEN (SC_ALTCTL[2])) and warm reset (WARSTEN (SC_ALTCTL[4])) sequence interrupt status flag. Note: This bit is read only, but it can be cleared by writing 1 to it.
[9] | RXTOIF | Receiver Buffer Time-out Interrupt Status Flag (Read Only) This field is used for receiver buffer time-out interrupt status flag. Note: This field is the status flag of receiver buffer time-out state If software wants to clear this bit, software must read all receiver buffer remaining data by reading SC_DAT buffer,
[10] | ACERRIF | Auto Convention Error Interrupt Status Flag (Read Only) This field indicates auto convention sequence error If the received TS at ATR state is neither 0x3B nor 0x3F, this bit will be set. Note: This bit is read only, but it can be cleared by writing 1 to it.

Definition at line 21643 of file Nano103.h.

## ◆ PINCTL

SC_T::PINCTL

[0x0024] SC Pin Control State Register.

PINCTL

Offset: 0x24 SC Pin Control State Register.

Bits | Field | Descriptions
[0] | PWREN | SC_PWREN Pin Signal Software can set PWREN (SC_PINCTL[0]) and PWRINV (SC_PINCTL[11])to decide SC_PWR pin is in high or low level. Write this field to drive SC_PWR pin Refer PWRINV (SC_PINCTL[11]) description for programming SC_PWR pin voltage level. Read this field to get SC_PWR pin status. 0 = SC_PWR pin status is low. 1 = SC_PWR pin status is high. Note: When operating at hardware activation, warm reset or deactivation mode, this bit will be changed automatically Thus,do not fill in this field when operating in these modes.
[1] | SCRST | SC_RST Pin Signal This bit is the pin status of SC_RST but user can drive SC_RST pin to high or low by setting this bit. Write this field to drive SC_RST pin. 0 = Drive SC_RST pin to low. 1 = Drive SC_RST pin to high. Read this field to get SC_RST pin status. 0 = SC_RST pin status is low. 1 = SC_RST pin status is high. Note: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically Thus,do not fill in this field when operating in these modes.
[2] | CREMOVE | Card Detect Removal Status of SC_CD Pin (Read Only) This bit is set whenever card has been removal. 0 = No effect. 1 = Card removed. Note1: This bit is read only, but it can be cleared by writing u201C1u201D to it. Note2: Card detect engine will start after SCEN (SC_CTL[0])set.
[3] | CINSERT | Card Detect Insert Status of SC_CD Pin (Read Only) This bit is set whenever card has been inserted. 0 = No effect. 1 = Card insert. Note1: This bit is read only, but it can be cleared by writing u201C1u201D to it. Note2: The card detect engine will start after SCEN (SC_CTL[0]) set.
[4] | CDPINSTS | Card Detect Status of SC_CD Pin Status (Read Only) This bit is the pin status flag of SC_CD 0 = The SC_CD pin state at low. 1 = The SC_CD pin state at high.
[6] | CLKKEEP | SC Clock Enable Bit 0 = SC clock generation Disabled. 1 = SC clock always keeps free running. Note: When operating in activation, warm reset or deactivation mode, this bit will be changed automatically Thus,do not fill in this field when operating in these modes.
[7] | ADACEN | Auto Deactivation When Card Removal 0 = Auto deactivation Disabled when hardware detected the card removal. 1 = Auto deactivation Enabled when hardware detected the card removal. Note: When the card is removed, hardware will stop any process and then do deactivation sequence (if this bit is set) If this process completes, hardware will generate an interrupt INITIF to CPU.
[9] | SCDOUT | SC Data Output Pin This bit is the pin status of SCDATOUT but user can drive SCDATOUT pin to high or low by setting this bit. 0 = Drive SCDATOUT pin to low. 1 = Drive SCDATOUT pin to high. Note: When SC is at activation, warm reset or deactivation mode, this bit will be changed automatically Thus,do not fill in this field when SC is in these modes.
[10] | CDLV | Card Detect Level 0 = When hardware detects the card detect pin (SC_CD) from high to low, it indicates a card is detected. 1 = When hardware detects the card detect pin from low to high, it indicates a card is detected. Note: Software must select card detect level before activate Smart Card.
[11] | PWRINV | SC_POW Pin Inverse This bit is used for inverse the SC_POW pin. There are four kinds of combination for SC_POW pin setting by PWRINV(SC_PINCTL[11]) and PWREN(SC_PINCTL[0]) PWRINV (SC_PINCTL[11]) is bit 1 and PWREN(SC_PINCTL[0]) is bit 0 for SC_POW_Pin as high or low voltage selection. 00 = SC_POW_ Pin is 0. 01 = SC_POW _Pin is 1. 10 = SC_POW _Pin is 1. 11 = SC_POW_ Pin is 0. Note:Software must select PWRINV (SC_PINCTL[11]) before Smart Card is enabled by SCEN (SC_CTL[0]).
[16] | DATSTS | SC Data Input Pin Status (Read Only) This bit is the pin status of SC_DAT 0 = The SC_DAT pin is low. 1 = The SC_DAT pin is high.
[30] | SYNC | SYNC Flag Indicator(Read Only) Due to synchronization, software should check this bit when writing a new value to SC_PINCTL register. 0 = Synchronizing is completion, user can write new data to SC_PINCTL register. 1 = Last value is synchronizing.

Definition at line 21645 of file Nano103.h.

## ◆ RXTOUT

SC_T::RXTOUT

[0x0010] SC Receive buffer Time-out Register.

RXTOUT

Offset: 0x10 SC Receive buffer Time-out Register.

Bits | Field | Descriptions
[8:0] | RFTM | SC Receiver FIFO Time-out The time-out counter resets and starts counting whenever the RX buffer received a new data word Once the counter decrease to 1 and no new data is received or CPU does not read data by reading SC_DAT buffer, a receiver time-out interrupt INT_RTMR will be generated(if RXTOIF(SC_INTEN[9]) = 1 ). Note1:The counter unit is ETU based and the interval of time-out is RFTM + 0.5. Note2: Filling in all 0 to this field indicates to disable this function.

Definition at line 21640 of file Nano103.h.

## ◆ STATUS

SC_T::STATUS

[0x0020] SC Transfer Status Register.

STATUS

Offset: 0x20 SC Transfer Status Register.

Bits | Field | Descriptions
[0] | RXOV | RX Overflow Error Status Flag (Read Only) This bit is set when RX buffer overflow. If the number of received bytes is greater than Rx Buffer size (4 bytes), this bit will be set. Note: This bit is read only, but it can be cleared by writing 1 to it.
[1] | RXEMPTY | Receiver Buffer Empty Status Flag(Read Only) This bit indicates RX buffer empty or not. When the last byte of Rx buffer has been read by CPU, hardware sets this bit high It will be cleared when SC receives any new data.
[2] | RXFULL | Receiver Buffer Full Status Flag (Read Only) This bit indicates RX buffer full or not. This bit is set when RX pointer is equal to 4, otherwise it is cleared by hardware.
[4] | PEF | Receiver Parity Error Status Flag (Read Only) This bit is set to logic 1 whenever the received character does not have a valid parity bit. Note1: This bit is read only, but it can be cleared by writing 1 to it. Note2: If CPU sets receiver retries function by setting RXRTYEN(SC_CTL[19]) , hardware will not set this flag.
[5] | FEF | Receiver Frame Error Status Flag (Read Only) This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as logic 0). Note1: This bit is read only, but it can be cleared by writing 1 to it. Note2: If CPU sets receiver retries function by setting RXRTYEN(SC_CTL[19]) , hardware will not set this flag.
[6] | BEF | Receiver Break Error Status Flag (Read Only) This bit is set to logic 1 whenever the received data input (RX) held in the spacing state (logic 0) is longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits). Note1: This bit is read only, but it can be cleared by writing 1 to it. Note2: If CPU sets receiver retries function by setting RXRTYEN(SC_CTL[19]) , hardware will not set this flag.
[8] | TXOV | TX Overflow Error Interrupt Status Flag (Read Only) If TX buffer is full, an additional write to DAT(SC_DAT[7:0]) will cause this bit be set to 1 by hardware. Note: This bit is read only, but it can be cleared by writing 1 to it.
[9] | TXEMPTY | Transmit Buffer Empty Status Flag (Read Only) This bit indicates TX buffer empty or not. When the last byte of TX buffer has been transferred to Transmitter Shift Register, hardware sets this bit high It will be cleared when writing data into DAT(SC_DAT[7:0]) (TX buffer not empty).
[10] | TXFULL | Transmit Buffer Full Status Flag (Read Only) This bit indicates TX buffer full or not.This bit is set when TX pointer is equal to 4, otherwise is cleared by hardware.
[17:16] | RXPOINT | Receiver Buffer Pointer Status Flag (Read Only) This field indicates the RX buffer pointer status flag When SC receives one byte from external device, RXPOINT(SC_STATUS[17:16]) increases one When one byte of RX buffer is read by CPU, RXPOINT(SC_STATUS[17:16]) decreases one.
[21] | RXRERR | Receiver Retry Error (Read Only) This bit is set by hardware when RX has any error and retries transfer. Note1: This bit is read only, but it can be cleared by writing 1 to it. Note2 This bit is a flag and cannot generate any interrupt to CPU. Note3: If CPU enables receiver retry function by setting RXRTYEN (SC_CTL[19]) , the PEF(SC_STATUS[4]) flag will be ignored (hardware will not set PEF(SC_STATUS[4])).
[22] | RXOVERR | Receiver over Retry Error (Read Only) This bit is set by hardware when RX transfer error retry over retry number limit. Note1: This bit is read only, but it can be cleared by writing 1 to it. Note2: If CPU enables receiver retries function by setting RXRTYEN (SC_CTL[19]), the PEF(SC_STATUS[4]) flag will be ignored (hardware will not set PEF(SC_STATUS[4])).
[23] | RXACT | Receiver in Active Status Flag (Read Only) This bit is set by hardware when RX transfer is in active. This bit is cleared automatically when RX transfer is finished.
[25:24] | TXPOINT | Transmit Buffer Pointer Status Flag (Read Only) This field indicates the TX buffer pointer status flag When CPU writes data into SC_DAT, TXPOINT increases one When one byte of TX Buffer is transferred to transmitter shift register, TXPOINT decreases one.
[29] | TXRERR | Transmitter Retry Error (Read Only) This bit is set by hardware when transmitter re-transmits. Note1: This bit is read only, but it can be cleared by writing 1 to it. Note2 This bit is a flag and cannot generate any interrupt to CPU.
[30] | TXOVERR | Transmitter over Retry Error (Read Only) This bit is set by hardware when transmitter re-transmits over retry number limitation. Note: This bit is read only, but it can be cleared by writing 1 to it.
[31] | TXACT | Transmit in Active Status Flag (Read Only) 0 = This bit is cleared automatically when TX transfer is finished or the last byte transmission has completed. 1 = This bit is set by hardware when TX transfer is in active and the STOP bit of the last byte has been transmitted.

Definition at line 21644 of file Nano103.h.

## ◆ TMRCTL0

SC_T::TMRCTL0

[0x0028] SC Internal Timer 0 Control Register.

TMRCTL0

Offset: 0x28 SC Internal Timer 0 Control Register.

Bits | Field | Descriptions
[23:0] | CNT | Timer 0 Counter Value (ETU Based) This field indicates the internal timer operation values.
[27:24] | OPMODE | Timer 0 Operation Mode Selection This field indicates the internal 24-bit timer operation selection. Refer toTable 6.15-3 Timer Operation Mode for programming Timer0.
[31] | SYNC | SYNC Flag Indicator(Read Only) Due to synchronization, software should check this bit when writing a new value to the SC_TMRCTL0 register. 0 = Synchronizing is completion, user can write new data to SC_TMRCTL0 register. 1 = Last value is synchronizing.

Definition at line 21646 of file Nano103.h.

## ◆ TMRCTL1

SC_T::TMRCTL1

[0x002c] SC Internal Timer 1 Control Register.

TMRCTL1

Offset: 0x2C SC Internal Timer 1 Control Register.

Bits | Field | Descriptions
[7:0] | CNT | Timer 1 Counter Value (ETU Based) This field indicates the internal timer operation values.
[27:24] | OPMODE | Timer 1 Operation Mode Selection This field indicates the internal 8-bit timer operation selection. Refer toTable 6.15-3 Timer Operation Mode for programming Timer1.
[31] | SYNC | SYNC Flag Indicator(Read Only) Due to synchronization, software should check this bit when writing a new value to the SC_TMRCTL1 register. 0 = Synchronizing is completion, user can write new data to SC_TMRCTL1 register. 1 = Last value is synchronizing.

Definition at line 21647 of file Nano103.h.

## ◆ TMRCTL2

SC_T::TMRCTL2

[0x0030] SC Internal Timer 2 Control Register.

TMRCTL2

Offset: 0x30 SC Internal Timer 2 Control Register.

Bits | Field | Descriptions
[7:0] | CNT | Timer 2 Counter Value (ETU Based) This field indicates the internal timer operation values.
[27:24] | OPMODE | Timer 2 Operation Mode Selection This field indicates the internal 8-bit timer operation selection Refer to Table 6.15-3 Timer Operation Mode for programming Timer2.
[31] | SYNC | SYNC Flag Indicator(Read Only) Due to synchronization, software should check this bit when writing a new value to SC_TMRCTL2 register. 0 = Synchronizing is completion, user can write new data to SC_TMRCTL2 register. 1 = Last value is synchronizing.

Definition at line 21648 of file Nano103.h.

## ◆ UARTCTL

SC_T::UARTCTL

[0x0034] SC UART Mode Control Register.

UARTCTL

Offset: 0x34 SC UART Mode Control Register.

Bits | Field | Descriptions
[0] | UARTEN | UART Mode Enable Bit 0 = Smart Card mode. 1 = UART mode. Note1: When operating in UART mode, user must set CONSEL (SC_CTL[5:4]) = 00 and AUTOCEN(SC_CTL[3]) = 0. Note2: When operating in Smart Card mode, user must set UARTEN(SC_UARTCTL [0]) = 00. Note3: When UART is enabled, hardware will generate a reset to reset FIFO and internal state machine.
[5:4] | WLS | Word Length Selection 00 = Word length is 8 bits. 01 = Word length is 7 bits. 10 = Word length is 6 bits. 11 = Word length is 5 bits. Note: In smart card mode, this WLS must be '00'
[6] | PBOFF | Parity Bit Disable Control 0 = Parity bit is generated or checked between the last data word bit and stop bit of the serial data. 1 = Parity bit is not generated (transmitting data) or checked (receiving data) during transfer. Note: In smart card mode, this field must be '0' (default setting is with parity bit)
[7] | OPE | Odd Parity Enable Bit 0 = Even number of logic 1's are transmitted or check the data word and parity bits in receiving mode. 1 = Odd number of logic 1's are transmitted or check the data word and parity bits in receiving mode. Note: This bit has effect only when PBOFF bit is '0'.

Definition at line 21649 of file Nano103.h.

The documentation for this struct was generated from the following file:

- C:/Users/yachen/workzone/bsp/nano103bsp/Library/Device/Nuvoton/Nano103/Include/Nano103.h