Nano103 BSP  V3.01.002
The Board Support Package for Nano103 Series
Data Fields
GPIO_T Struct Reference

#include <Nano103.h>

Data Fields

__IO uint32_t MODE
 
__IO uint32_t DINOFF
 
__IO uint32_t DOUT
 
__IO uint32_t DATMSK
 
__I uint32_t PIN
 
__IO uint32_t DBEN
 
__IO uint32_t INTTYPE
 
__IO uint32_t INTEN
 
__IO uint32_t INTSRC
 
__IO uint32_t PUEN
 
__I uint32_t INTSTS
 

Detailed Description

@addtogroup GPIO General Purpose Input/Output Controller(GPIO)
Memory Mapped Structure for GPIO Controller

Definition at line 5998 of file Nano103.h.

Field Documentation

◆ DATMSK

GPIO_T::DATMSK

[0x000c] Pn Data Output Write Mask

DATMSK

Offset: 0x0C Pn Data Output Write Mask

BitsFieldDescriptions
[0]DMASK0
Port A-f Pin[N] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit
When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected
If the write signal is masked, writing data to the protect bit is ignored.
0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated.
1 = Corresponding DOUT (Px_DOUT[n]) bit protected.
Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note2:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note3:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[1]DMASK1
Port A-f Pin[N] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit
When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected
If the write signal is masked, writing data to the protect bit is ignored.
0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated.
1 = Corresponding DOUT (Px_DOUT[n]) bit protected.
Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note2:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note3:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[2]DMASK2
Port A-f Pin[N] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit
When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected
If the write signal is masked, writing data to the protect bit is ignored.
0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated.
1 = Corresponding DOUT (Px_DOUT[n]) bit protected.
Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note2:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note3:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[3]DMASK3
Port A-f Pin[N] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit
When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected
If the write signal is masked, writing data to the protect bit is ignored.
0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated.
1 = Corresponding DOUT (Px_DOUT[n]) bit protected.
Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note2:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note3:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[4]DMASK4
Port A-f Pin[N] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit
When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected
If the write signal is masked, writing data to the protect bit is ignored.
0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated.
1 = Corresponding DOUT (Px_DOUT[n]) bit protected.
Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note2:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note3:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[5]DMASK5
Port A-f Pin[N] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit
When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected
If the write signal is masked, writing data to the protect bit is ignored.
0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated.
1 = Corresponding DOUT (Px_DOUT[n]) bit protected.
Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note2:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note3:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[6]DMASK6
Port A-f Pin[N] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit
When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected
If the write signal is masked, writing data to the protect bit is ignored.
0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated.
1 = Corresponding DOUT (Px_DOUT[n]) bit protected.
Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note2:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note3:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[7]DMASK7
Port A-f Pin[N] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit
When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected
If the write signal is masked, writing data to the protect bit is ignored.
0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated.
1 = Corresponding DOUT (Px_DOUT[n]) bit protected.
Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note2:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note3:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[8]DMASK8
Port A-f Pin[N] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit
When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected
If the write signal is masked, writing data to the protect bit is ignored.
0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated.
1 = Corresponding DOUT (Px_DOUT[n]) bit protected.
Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note2:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note3:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[9]DMASK9
Port A-f Pin[N] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit
When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected
If the write signal is masked, writing data to the protect bit is ignored.
0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated.
1 = Corresponding DOUT (Px_DOUT[n]) bit protected.
Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note2:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note3:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[10]DMASK10
Port A-f Pin[N] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit
When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected
If the write signal is masked, writing data to the protect bit is ignored.
0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated.
1 = Corresponding DOUT (Px_DOUT[n]) bit protected.
Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note2:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note3:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[11]DMASK11
Port A-f Pin[N] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit
When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected
If the write signal is masked, writing data to the protect bit is ignored.
0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated.
1 = Corresponding DOUT (Px_DOUT[n]) bit protected.
Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note2:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note3:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[12]DMASK12
Port A-f Pin[N] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit
When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected
If the write signal is masked, writing data to the protect bit is ignored.
0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated.
1 = Corresponding DOUT (Px_DOUT[n]) bit protected.
Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note2:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note3:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[13]DMASK13
Port A-f Pin[N] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit
When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected
If the write signal is masked, writing data to the protect bit is ignored.
0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated.
1 = Corresponding DOUT (Px_DOUT[n]) bit protected.
Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note2:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note3:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[14]DMASK14
Port A-f Pin[N] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit
When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected
If the write signal is masked, writing data to the protect bit is ignored.
0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated.
1 = Corresponding DOUT (Px_DOUT[n]) bit protected.
Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note2:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note3:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[15]DMASK15
Port A-f Pin[N] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit
When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected
If the write signal is masked, writing data to the protect bit is ignored.
0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated.
1 = Corresponding DOUT (Px_DOUT[n]) bit protected.
Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note2:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note3:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.

Definition at line 11767 of file Nano103.h.

◆ DBEN

GPIO_T::DBEN

[0x0014] Pn De-Bounce Enable Control Register

DBEN

Offset: 0x14 Pn De-Bounce Enable Control Register

BitsFieldDescriptions
[0]DBEN0
Port A-f Pin[N] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit
If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt
The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
0 = Px.n de-bounce function Disabled.
1 = Px.n de-bounce function Enabled.
The de-bounce function is valid only for edge triggered interrupt
If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[1]DBEN1
Port A-f Pin[N] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit
If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt
The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
0 = Px.n de-bounce function Disabled.
1 = Px.n de-bounce function Enabled.
The de-bounce function is valid only for edge triggered interrupt
If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[2]DBEN2
Port A-f Pin[N] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit
If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt
The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
0 = Px.n de-bounce function Disabled.
1 = Px.n de-bounce function Enabled.
The de-bounce function is valid only for edge triggered interrupt
If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[3]DBEN3
Port A-f Pin[N] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit
If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt
The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
0 = Px.n de-bounce function Disabled.
1 = Px.n de-bounce function Enabled.
The de-bounce function is valid only for edge triggered interrupt
If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[4]DBEN4
Port A-f Pin[N] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit
If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt
The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
0 = Px.n de-bounce function Disabled.
1 = Px.n de-bounce function Enabled.
The de-bounce function is valid only for edge triggered interrupt
If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[5]DBEN5
Port A-f Pin[N] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit
If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt
The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
0 = Px.n de-bounce function Disabled.
1 = Px.n de-bounce function Enabled.
The de-bounce function is valid only for edge triggered interrupt
If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[6]DBEN6
Port A-f Pin[N] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit
If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt
The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
0 = Px.n de-bounce function Disabled.
1 = Px.n de-bounce function Enabled.
The de-bounce function is valid only for edge triggered interrupt
If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[7]DBEN7
Port A-f Pin[N] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit
If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt
The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
0 = Px.n de-bounce function Disabled.
1 = Px.n de-bounce function Enabled.
The de-bounce function is valid only for edge triggered interrupt
If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[8]DBEN8
Port A-f Pin[N] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit
If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt
The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
0 = Px.n de-bounce function Disabled.
1 = Px.n de-bounce function Enabled.
The de-bounce function is valid only for edge triggered interrupt
If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[9]DBEN9
Port A-f Pin[N] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit
If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt
The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
0 = Px.n de-bounce function Disabled.
1 = Px.n de-bounce function Enabled.
The de-bounce function is valid only for edge triggered interrupt
If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[10]DBEN10
Port A-f Pin[N] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit
If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt
The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
0 = Px.n de-bounce function Disabled.
1 = Px.n de-bounce function Enabled.
The de-bounce function is valid only for edge triggered interrupt
If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[11]DBEN11
Port A-f Pin[N] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit
If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt
The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
0 = Px.n de-bounce function Disabled.
1 = Px.n de-bounce function Enabled.
The de-bounce function is valid only for edge triggered interrupt
If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[12]DBEN12
Port A-f Pin[N] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit
If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt
The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
0 = Px.n de-bounce function Disabled.
1 = Px.n de-bounce function Enabled.
The de-bounce function is valid only for edge triggered interrupt
If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[13]DBEN13
Port A-f Pin[N] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit
If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt
The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
0 = Px.n de-bounce function Disabled.
1 = Px.n de-bounce function Enabled.
The de-bounce function is valid only for edge triggered interrupt
If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[14]DBEN14
Port A-f Pin[N] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit
If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt
The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
0 = Px.n de-bounce function Disabled.
1 = Px.n de-bounce function Enabled.
The de-bounce function is valid only for edge triggered interrupt
If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[15]DBEN15
Port A-f Pin[N] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit
If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt
The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
0 = Px.n de-bounce function Disabled.
1 = Px.n de-bounce function Enabled.
The de-bounce function is valid only for edge triggered interrupt
If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.

Definition at line 11769 of file Nano103.h.

◆ DINOFF

GPIO_T::DINOFF

[0x0004] Pn Digital Input Path Disable Control

DINOFF

Offset: 0x04 Pn Digital Input Path Disable Control

BitsFieldDescriptions
[16]DINOFF0
Port A-f Pin[N] Digital Input Path Disable Bit
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled
If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
0 = Px.n digital input path Enabled.
1 = Px.n digital input path Disabled (digital input tied to low).
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[17]DINOFF1
Port A-f Pin[N] Digital Input Path Disable Bit
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled
If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
0 = Px.n digital input path Enabled.
1 = Px.n digital input path Disabled (digital input tied to low).
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[18]DINOFF2
Port A-f Pin[N] Digital Input Path Disable Bit
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled
If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
0 = Px.n digital input path Enabled.
1 = Px.n digital input path Disabled (digital input tied to low).
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[19]DINOFF3
Port A-f Pin[N] Digital Input Path Disable Bit
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled
If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
0 = Px.n digital input path Enabled.
1 = Px.n digital input path Disabled (digital input tied to low).
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[20]DINOFF4
Port A-f Pin[N] Digital Input Path Disable Bit
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled
If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
0 = Px.n digital input path Enabled.
1 = Px.n digital input path Disabled (digital input tied to low).
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[21]DINOFF5
Port A-f Pin[N] Digital Input Path Disable Bit
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled
If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
0 = Px.n digital input path Enabled.
1 = Px.n digital input path Disabled (digital input tied to low).
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[22]DINOFF6
Port A-f Pin[N] Digital Input Path Disable Bit
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled
If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
0 = Px.n digital input path Enabled.
1 = Px.n digital input path Disabled (digital input tied to low).
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[23]DINOFF7
Port A-f Pin[N] Digital Input Path Disable Bit
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled
If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
0 = Px.n digital input path Enabled.
1 = Px.n digital input path Disabled (digital input tied to low).
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[24]DINOFF8
Port A-f Pin[N] Digital Input Path Disable Bit
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled
If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
0 = Px.n digital input path Enabled.
1 = Px.n digital input path Disabled (digital input tied to low).
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[25]DINOFF9
Port A-f Pin[N] Digital Input Path Disable Bit
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled
If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
0 = Px.n digital input path Enabled.
1 = Px.n digital input path Disabled (digital input tied to low).
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[26]DINOFF10
Port A-f Pin[N] Digital Input Path Disable Bit
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled
If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
0 = Px.n digital input path Enabled.
1 = Px.n digital input path Disabled (digital input tied to low).
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[27]DINOFF11
Port A-f Pin[N] Digital Input Path Disable Bit
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled
If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
0 = Px.n digital input path Enabled.
1 = Px.n digital input path Disabled (digital input tied to low).
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[28]DINOFF12
Port A-f Pin[N] Digital Input Path Disable Bit
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled
If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
0 = Px.n digital input path Enabled.
1 = Px.n digital input path Disabled (digital input tied to low).
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[29]DINOFF13
Port A-f Pin[N] Digital Input Path Disable Bit
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled
If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
0 = Px.n digital input path Enabled.
1 = Px.n digital input path Disabled (digital input tied to low).
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[30]DINOFF14
Port A-f Pin[N] Digital Input Path Disable Bit
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled
If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
0 = Px.n digital input path Enabled.
1 = Px.n digital input path Disabled (digital input tied to low).
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[31]DINOFF15
Port A-f Pin[N] Digital Input Path Disable Bit
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled
If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
0 = Px.n digital input path Enabled.
1 = Px.n digital input path Disabled (digital input tied to low).
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.

Definition at line 11765 of file Nano103.h.

◆ DOUT

GPIO_T::DOUT

[0x0008] Pn Data Output Value

DOUT

Offset: 0x08 Pn Data Output Value

BitsFieldDescriptions
[0]DOUT0
Port A-f Pin[N] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output.
0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output.
1 = Px.n will drive High if the Px.n pin is configured as Push-pull output.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[1]DOUT1
Port A-f Pin[N] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output.
0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output.
1 = Px.n will drive High if the Px.n pin is configured as Push-pull output.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[2]DOUT2
Port A-f Pin[N] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output.
0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output.
1 = Px.n will drive High if the Px.n pin is configured as Push-pull output.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[3]DOUT3
Port A-f Pin[N] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output.
0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output.
1 = Px.n will drive High if the Px.n pin is configured as Push-pull output.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[4]DOUT4
Port A-f Pin[N] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output.
0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output.
1 = Px.n will drive High if the Px.n pin is configured as Push-pull output.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[5]DOUT5
Port A-f Pin[N] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output.
0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output.
1 = Px.n will drive High if the Px.n pin is configured as Push-pull output.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[6]DOUT6
Port A-f Pin[N] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output.
0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output.
1 = Px.n will drive High if the Px.n pin is configured as Push-pull output.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[7]DOUT7
Port A-f Pin[N] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output.
0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output.
1 = Px.n will drive High if the Px.n pin is configured as Push-pull output.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[8]DOUT8
Port A-f Pin[N] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output.
0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output.
1 = Px.n will drive High if the Px.n pin is configured as Push-pull output.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[9]DOUT9
Port A-f Pin[N] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output.
0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output.
1 = Px.n will drive High if the Px.n pin is configured as Push-pull output.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[10]DOUT10
Port A-f Pin[N] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output.
0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output.
1 = Px.n will drive High if the Px.n pin is configured as Push-pull output.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[11]DOUT11
Port A-f Pin[N] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output.
0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output.
1 = Px.n will drive High if the Px.n pin is configured as Push-pull output.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[12]DOUT12
Port A-f Pin[N] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output.
0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output.
1 = Px.n will drive High if the Px.n pin is configured as Push-pull output.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[13]DOUT13
Port A-f Pin[N] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output.
0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output.
1 = Px.n will drive High if the Px.n pin is configured as Push-pull output.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[14]DOUT14
Port A-f Pin[N] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output.
0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output.
1 = Px.n will drive High if the Px.n pin is configured as Push-pull output.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[15]DOUT15
Port A-f Pin[N] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output.
0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output.
1 = Px.n will drive High if the Px.n pin is configured as Push-pull output.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.

Definition at line 11766 of file Nano103.h.

◆ INTEN

GPIO_T::INTEN

[0x001c] Pn Interrupt Enable Control Register

INTEN

Offset: 0x1C Pn Interrupt Enable Control Register

BitsFieldDescriptions
[0]FLIEN0
Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin
Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
0 = Px.n level low or high to low interrupt Disabled.
1 = Px.n level low or high to low interrupt Enabled.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[1]FLIEN1
Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin
Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
0 = Px.n level low or high to low interrupt Disabled.
1 = Px.n level low or high to low interrupt Enabled.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[2]FLIEN2
Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin
Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
0 = Px.n level low or high to low interrupt Disabled.
1 = Px.n level low or high to low interrupt Enabled.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[3]FLIEN3
Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin
Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
0 = Px.n level low or high to low interrupt Disabled.
1 = Px.n level low or high to low interrupt Enabled.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[4]FLIEN4
Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin
Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
0 = Px.n level low or high to low interrupt Disabled.
1 = Px.n level low or high to low interrupt Enabled.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[5]FLIEN5
Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin
Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
0 = Px.n level low or high to low interrupt Disabled.
1 = Px.n level low or high to low interrupt Enabled.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[6]FLIEN6
Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin
Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
0 = Px.n level low or high to low interrupt Disabled.
1 = Px.n level low or high to low interrupt Enabled.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[7]FLIEN7
Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin
Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
0 = Px.n level low or high to low interrupt Disabled.
1 = Px.n level low or high to low interrupt Enabled.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[8]FLIEN8
Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin
Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
0 = Px.n level low or high to low interrupt Disabled.
1 = Px.n level low or high to low interrupt Enabled.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[9]FLIEN9
Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin
Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
0 = Px.n level low or high to low interrupt Disabled.
1 = Px.n level low or high to low interrupt Enabled.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[10]FLIEN10
Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin
Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
0 = Px.n level low or high to low interrupt Disabled.
1 = Px.n level low or high to low interrupt Enabled.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[11]FLIEN11
Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin
Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
0 = Px.n level low or high to low interrupt Disabled.
1 = Px.n level low or high to low interrupt Enabled.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[12]FLIEN12
Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin
Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
0 = Px.n level low or high to low interrupt Disabled.
1 = Px.n level low or high to low interrupt Enabled.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[13]FLIEN13
Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin
Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
0 = Px.n level low or high to low interrupt Disabled.
1 = Px.n level low or high to low interrupt Enabled.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[14]FLIEN14
Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin
Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
0 = Px.n level low or high to low interrupt Disabled.
1 = Px.n level low or high to low interrupt Enabled.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[15]FLIEN15
Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin
Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
0 = Px.n level low or high to low interrupt Disabled.
1 = Px.n level low or high to low interrupt Enabled.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[16]RHIEN0
Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin
Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
0 = Px.n level high or low to high interrupt Disabled.
1 = Px.n level high or low to high interrupt Enabled.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[17]RHIEN1
Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin
Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
0 = Px.n level high or low to high interrupt Disabled.
1 = Px.n level high or low to high interrupt Enabled.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[18]RHIEN2
Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin
Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
0 = Px.n level high or low to high interrupt Disabled.
1 = Px.n level high or low to high interrupt Enabled.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[19]RHIEN3
Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin
Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
0 = Px.n level high or low to high interrupt Disabled.
1 = Px.n level high or low to high interrupt Enabled.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[20]RHIEN4
Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin
Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
0 = Px.n level high or low to high interrupt Disabled.
1 = Px.n level high or low to high interrupt Enabled.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[21]RHIEN5
Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin
Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
0 = Px.n level high or low to high interrupt Disabled.
1 = Px.n level high or low to high interrupt Enabled.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[22]RHIEN6
Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin
Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
0 = Px.n level high or low to high interrupt Disabled.
1 = Px.n level high or low to high interrupt Enabled.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[23]RHIEN7
Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin
Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
0 = Px.n level high or low to high interrupt Disabled.
1 = Px.n level high or low to high interrupt Enabled.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[24]RHIEN8
Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin
Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
0 = Px.n level high or low to high interrupt Disabled.
1 = Px.n level high or low to high interrupt Enabled.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[25]RHIEN9
Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin
Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
0 = Px.n level high or low to high interrupt Disabled.
1 = Px.n level high or low to high interrupt Enabled.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[26]RHIEN10
Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin
Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
0 = Px.n level high or low to high interrupt Disabled.
1 = Px.n level high or low to high interrupt Enabled.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[27]RHIEN11
Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin
Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
0 = Px.n level high or low to high interrupt Disabled.
1 = Px.n level high or low to high interrupt Enabled.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[28]RHIEN12
Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin
Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
0 = Px.n level high or low to high interrupt Disabled.
1 = Px.n level high or low to high interrupt Enabled.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[29]RHIEN13
Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin
Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
0 = Px.n level high or low to high interrupt Disabled.
1 = Px.n level high or low to high interrupt Enabled.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[30]RHIEN14
Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin
Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
0 = Px.n level high or low to high interrupt Disabled.
1 = Px.n level high or low to high interrupt Enabled.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[31]RHIEN15
Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin
Set bit to 1 also enable the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
0 = Px.n level high or low to high interrupt Disabled.
1 = Px.n level high or low to high interrupt Enabled.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.

Definition at line 11771 of file Nano103.h.

◆ INTSRC

GPIO_T::INTSRC

[0x0020] Pn Interrupt Source Flag

INTSRC

Offset: 0x20 Pn Interrupt Source Flag

BitsFieldDescriptions
[0]INTSRC0
Port A-f Pin[N] Interrupt Source Flag
Write Operation :
0 = No action.
1 = Clear the corresponding pending interrupt.
Read Operation :
0 = No interrupt at Px.n.
1 = Px.n generates an interrupt.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[1]INTSRC1
Port A-f Pin[N] Interrupt Source Flag
Write Operation :
0 = No action.
1 = Clear the corresponding pending interrupt.
Read Operation :
0 = No interrupt at Px.n.
1 = Px.n generates an interrupt.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[2]INTSRC2
Port A-f Pin[N] Interrupt Source Flag
Write Operation :
0 = No action.
1 = Clear the corresponding pending interrupt.
Read Operation :
0 = No interrupt at Px.n.
1 = Px.n generates an interrupt.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[3]INTSRC3
Port A-f Pin[N] Interrupt Source Flag
Write Operation :
0 = No action.
1 = Clear the corresponding pending interrupt.
Read Operation :
0 = No interrupt at Px.n.
1 = Px.n generates an interrupt.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[4]INTSRC4
Port A-f Pin[N] Interrupt Source Flag
Write Operation :
0 = No action.
1 = Clear the corresponding pending interrupt.
Read Operation :
0 = No interrupt at Px.n.
1 = Px.n generates an interrupt.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[5]INTSRC5
Port A-f Pin[N] Interrupt Source Flag
Write Operation :
0 = No action.
1 = Clear the corresponding pending interrupt.
Read Operation :
0 = No interrupt at Px.n.
1 = Px.n generates an interrupt.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[6]INTSRC6
Port A-f Pin[N] Interrupt Source Flag
Write Operation :
0 = No action.
1 = Clear the corresponding pending interrupt.
Read Operation :
0 = No interrupt at Px.n.
1 = Px.n generates an interrupt.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[7]INTSRC7
Port A-f Pin[N] Interrupt Source Flag
Write Operation :
0 = No action.
1 = Clear the corresponding pending interrupt.
Read Operation :
0 = No interrupt at Px.n.
1 = Px.n generates an interrupt.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[8]INTSRC8
Port A-f Pin[N] Interrupt Source Flag
Write Operation :
0 = No action.
1 = Clear the corresponding pending interrupt.
Read Operation :
0 = No interrupt at Px.n.
1 = Px.n generates an interrupt.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[9]INTSRC9
Port A-f Pin[N] Interrupt Source Flag
Write Operation :
0 = No action.
1 = Clear the corresponding pending interrupt.
Read Operation :
0 = No interrupt at Px.n.
1 = Px.n generates an interrupt.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[10]INTSRC10
Port A-f Pin[N] Interrupt Source Flag
Write Operation :
0 = No action.
1 = Clear the corresponding pending interrupt.
Read Operation :
0 = No interrupt at Px.n.
1 = Px.n generates an interrupt.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[11]INTSRC11
Port A-f Pin[N] Interrupt Source Flag
Write Operation :
0 = No action.
1 = Clear the corresponding pending interrupt.
Read Operation :
0 = No interrupt at Px.n.
1 = Px.n generates an interrupt.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[12]INTSRC12
Port A-f Pin[N] Interrupt Source Flag
Write Operation :
0 = No action.
1 = Clear the corresponding pending interrupt.
Read Operation :
0 = No interrupt at Px.n.
1 = Px.n generates an interrupt.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[13]INTSRC13
Port A-f Pin[N] Interrupt Source Flag
Write Operation :
0 = No action.
1 = Clear the corresponding pending interrupt.
Read Operation :
0 = No interrupt at Px.n.
1 = Px.n generates an interrupt.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[14]INTSRC14
Port A-f Pin[N] Interrupt Source Flag
Write Operation :
0 = No action.
1 = Clear the corresponding pending interrupt.
Read Operation :
0 = No interrupt at Px.n.
1 = Px.n generates an interrupt.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[15]INTSRC15
Port A-f Pin[N] Interrupt Source Flag
Write Operation :
0 = No action.
1 = Clear the corresponding pending interrupt.
Read Operation :
0 = No interrupt at Px.n.
1 = Px.n generates an interrupt.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.

Definition at line 11772 of file Nano103.h.

◆ INTSTS

GPIO_T::INTSTS

[0x0028] Pn Interrupt Status Register

INTSTS

Offset: 0x28 Pn Interrupt Status

BitsFieldDescriptions
[0]FLISTS0
Port A-f Pin[N] Falling Edge Interrupt Status
If the interrupt is falling edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])).
0 = No falling edge interrupt at Px.n.
1 = Px.n generates an falling edge interrupt.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[1]FLISTS1
Port A-f Pin[N] Falling Edge Interrupt Status
If the interrupt is falling edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])).
0 = No falling edge interrupt at Px.n.
1 = Px.n generates an falling edge interrupt.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[2]FLISTS2
Port A-f Pin[N] Falling Edge Interrupt Status
If the interrupt is falling edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])).
0 = No falling edge interrupt at Px.n.
1 = Px.n generates an falling edge interrupt.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[3]FLISTS3
Port A-f Pin[N] Falling Edge Interrupt Status
If the interrupt is falling edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])).
0 = No falling edge interrupt at Px.n.
1 = Px.n generates an falling edge interrupt.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[4]FLISTS4
Port A-f Pin[N] Falling Edge Interrupt Status
If the interrupt is falling edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])).
0 = No falling edge interrupt at Px.n.
1 = Px.n generates an falling edge interrupt.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[5]FLISTS5
Port A-f Pin[N] Falling Edge Interrupt Status
If the interrupt is falling edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])).
0 = No falling edge interrupt at Px.n.
1 = Px.n generates an falling edge interrupt.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[6]FLISTS6
Port A-f Pin[N] Falling Edge Interrupt Status
If the interrupt is falling edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])).
0 = No falling edge interrupt at Px.n.
1 = Px.n generates an falling edge interrupt.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[7]FLISTS7
Port A-f Pin[N] Falling Edge Interrupt Status
If the interrupt is falling edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])).
0 = No falling edge interrupt at Px.n.
1 = Px.n generates an falling edge interrupt.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[8]FLISTS8
Port A-f Pin[N] Falling Edge Interrupt Status
If the interrupt is falling edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])).
0 = No falling edge interrupt at Px.n.
1 = Px.n generates an falling edge interrupt.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[9]FLISTS9
Port A-f Pin[N] Falling Edge Interrupt Status
If the interrupt is falling edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])).
0 = No falling edge interrupt at Px.n.
1 = Px.n generates an falling edge interrupt.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[10]FLISTS10
Port A-f Pin[N] Falling Edge Interrupt Status
If the interrupt is falling edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])).
0 = No falling edge interrupt at Px.n.
1 = Px.n generates an falling edge interrupt.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[11]FLISTS11
Port A-f Pin[N] Falling Edge Interrupt Status
If the interrupt is falling edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])).
0 = No falling edge interrupt at Px.n.
1 = Px.n generates an falling edge interrupt.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[12]FLISTS12
Port A-f Pin[N] Falling Edge Interrupt Status
If the interrupt is falling edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])).
0 = No falling edge interrupt at Px.n.
1 = Px.n generates an falling edge interrupt.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[13]FLISTS13
Port A-f Pin[N] Falling Edge Interrupt Status
If the interrupt is falling edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])).
0 = No falling edge interrupt at Px.n.
1 = Px.n generates an falling edge interrupt.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[14]FLISTS14
Port A-f Pin[N] Falling Edge Interrupt Status
If the interrupt is falling edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])).
0 = No falling edge interrupt at Px.n.
1 = Px.n generates an falling edge interrupt.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[15]FLISTS15
Port A-f Pin[N] Falling Edge Interrupt Status
If the interrupt is falling edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])).
0 = No falling edge interrupt at Px.n.
1 = Px.n generates an falling edge interrupt.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[16]RHISTS0
Port A-f Pin[N] Rising Edge Interrupt Status
If the interrupt is rising edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])).
0 = No rising edge interrupt at Px.n.
1 = Px.n generates an rising edge interrupt.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[17]RHISTS1
Port A-f Pin[N] Rising Edge Interrupt Status
If the interrupt is rising edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])).
0 = No rising edge interrupt at Px.n.
1 = Px.n generates an rising edge interrupt.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[18]RHISTS2
Port A-f Pin[N] Rising Edge Interrupt Status
If the interrupt is rising edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])).
0 = No rising edge interrupt at Px.n.
1 = Px.n generates an rising edge interrupt.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[19]RHISTS3
Port A-f Pin[N] Rising Edge Interrupt Status
If the interrupt is rising edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])).
0 = No rising edge interrupt at Px.n.
1 = Px.n generates an rising edge interrupt.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[20]RHISTS4
Port A-f Pin[N] Rising Edge Interrupt Status
If the interrupt is rising edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])).
0 = No rising edge interrupt at Px.n.
1 = Px.n generates an rising edge interrupt.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[21]RHISTS5
Port A-f Pin[N] Rising Edge Interrupt Status
If the interrupt is rising edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])).
0 = No rising edge interrupt at Px.n.
1 = Px.n generates an rising edge interrupt.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[22]RHISTS6
Port A-f Pin[N] Rising Edge Interrupt Status
If the interrupt is rising edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])).
0 = No rising edge interrupt at Px.n.
1 = Px.n generates an rising edge interrupt.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[23]RHISTS7
Port A-f Pin[N] Rising Edge Interrupt Status
If the interrupt is rising edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])).
0 = No rising edge interrupt at Px.n.
1 = Px.n generates an rising edge interrupt.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[24]RHISTS8
Port A-f Pin[N] Rising Edge Interrupt Status
If the interrupt is rising edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])).
0 = No rising edge interrupt at Px.n.
1 = Px.n generates an rising edge interrupt.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[25]RHISTS9
Port A-f Pin[N] Rising Edge Interrupt Status
If the interrupt is rising edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])).
0 = No rising edge interrupt at Px.n.
1 = Px.n generates an rising edge interrupt.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[26]RHISTS10
Port A-f Pin[N] Rising Edge Interrupt Status
If the interrupt is rising edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])).
0 = No rising edge interrupt at Px.n.
1 = Px.n generates an rising edge interrupt.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[27]RHISTS11
Port A-f Pin[N] Rising Edge Interrupt Status
If the interrupt is rising edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])).
0 = No rising edge interrupt at Px.n.
1 = Px.n generates an rising edge interrupt.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[28]RHISTS12
Port A-f Pin[N] Rising Edge Interrupt Status
If the interrupt is rising edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])).
0 = No rising edge interrupt at Px.n.
1 = Px.n generates an rising edge interrupt.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[29]RHISTS13
Port A-f Pin[N] Rising Edge Interrupt Status
If the interrupt is rising edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])).
0 = No rising edge interrupt at Px.n.
1 = Px.n generates an rising edge interrupt.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[30]RHISTS14
Port A-f Pin[N] Rising Edge Interrupt Status
If the interrupt is rising edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])).
0 = No rising edge interrupt at Px.n.
1 = Px.n generates an rising edge interrupt.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[31]RHISTS15
Port A-f Pin[N] Rising Edge Interrupt Status
If the interrupt is rising edge trigger for each of the corresponding input Px.n pin, this bit will be set after interrupt occurred and automatically cleared by interrupt source flag (INTSRC (Px_INTSRC[n])).
0 = No rising edge interrupt at Px.n.
1 = Px.n generates an rising edge interrupt.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.

Definition at line 11774 of file Nano103.h.

◆ INTTYPE

GPIO_T::INTTYPE

[0x0018] Pn Interrupt Trigger Type Control

INTTYPE

Offset: 0x18 Pn Interrupt Trigger Type Control

BitsFieldDescriptions
[0]TYPE0
Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger
If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce
If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
0 = Edge trigger interrupt.
1 = Level trigger interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n])
If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt
If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[1]TYPE1
Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger
If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce
If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
0 = Edge trigger interrupt.
1 = Level trigger interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n])
If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt
If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[2]TYPE2
Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger
If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce
If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
0 = Edge trigger interrupt.
1 = Level trigger interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n])
If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt
If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[3]TYPE3
Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger
If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce
If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
0 = Edge trigger interrupt.
1 = Level trigger interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n])
If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt
If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[4]TYPE4
Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger
If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce
If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
0 = Edge trigger interrupt.
1 = Level trigger interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n])
If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt
If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[5]TYPE5
Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger
If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce
If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
0 = Edge trigger interrupt.
1 = Level trigger interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n])
If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt
If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[6]TYPE6
Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger
If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce
If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
0 = Edge trigger interrupt.
1 = Level trigger interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n])
If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt
If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[7]TYPE7
Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger
If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce
If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
0 = Edge trigger interrupt.
1 = Level trigger interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n])
If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt
If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[8]TYPE8
Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger
If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce
If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
0 = Edge trigger interrupt.
1 = Level trigger interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n])
If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt
If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[9]TYPE9
Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger
If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce
If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
0 = Edge trigger interrupt.
1 = Level trigger interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n])
If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt
If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[10]TYPE10
Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger
If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce
If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
0 = Edge trigger interrupt.
1 = Level trigger interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n])
If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt
If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[11]TYPE11
Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger
If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce
If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
0 = Edge trigger interrupt.
1 = Level trigger interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n])
If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt
If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[12]TYPE12
Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger
If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce
If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
0 = Edge trigger interrupt.
1 = Level trigger interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n])
If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt
If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[13]TYPE13
Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger
If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce
If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
0 = Edge trigger interrupt.
1 = Level trigger interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n])
If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt
If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[14]TYPE14
Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger
If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce
If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
0 = Edge trigger interrupt.
1 = Level trigger interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n])
If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt
If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[15]TYPE15
Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger
If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce
If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
0 = Edge trigger interrupt.
1 = Level trigger interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n])
If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt
If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.

Definition at line 11770 of file Nano103.h.

◆ MODE

GPIO_T::MODE

[0x0000] Pn I/O Mode Control

MODE

Offset: 0x00 Pn I/O Mode Control

BitsFieldDescriptions
[1:0]MODE0
Port A-f I/O Pin[N] Mode Control
Determine each I/O mode of Px.n pins.
00 = Px.n is in Input mode.
01 = Px.n is in Push-pull Output mode.
10 = Px.n is in Open-drain Output mode.
11 = Reserved.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[3:2]MODE1
Port A-f I/O Pin[N] Mode Control
Determine each I/O mode of Px.n pins.
00 = Px.n is in Input mode.
01 = Px.n is in Push-pull Output mode.
10 = Px.n is in Open-drain Output mode.
11 = Reserved.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[5:4]MODE2
Port A-f I/O Pin[N] Mode Control
Determine each I/O mode of Px.n pins.
00 = Px.n is in Input mode.
01 = Px.n is in Push-pull Output mode.
10 = Px.n is in Open-drain Output mode.
11 = Reserved.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[7:6]MODE3
Port A-f I/O Pin[N] Mode Control
Determine each I/O mode of Px.n pins.
00 = Px.n is in Input mode.
01 = Px.n is in Push-pull Output mode.
10 = Px.n is in Open-drain Output mode.
11 = Reserved.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[9:8]MODE4
Port A-f I/O Pin[N] Mode Control
Determine each I/O mode of Px.n pins.
00 = Px.n is in Input mode.
01 = Px.n is in Push-pull Output mode.
10 = Px.n is in Open-drain Output mode.
11 = Reserved.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[11:10]MODE5
Port A-f I/O Pin[N] Mode Control
Determine each I/O mode of Px.n pins.
00 = Px.n is in Input mode.
01 = Px.n is in Push-pull Output mode.
10 = Px.n is in Open-drain Output mode.
11 = Reserved.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[13:12]MODE6
Port A-f I/O Pin[N] Mode Control
Determine each I/O mode of Px.n pins.
00 = Px.n is in Input mode.
01 = Px.n is in Push-pull Output mode.
10 = Px.n is in Open-drain Output mode.
11 = Reserved.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[15:14]MODE7
Port A-f I/O Pin[N] Mode Control
Determine each I/O mode of Px.n pins.
00 = Px.n is in Input mode.
01 = Px.n is in Push-pull Output mode.
10 = Px.n is in Open-drain Output mode.
11 = Reserved.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[17:16]MODE8
Port A-f I/O Pin[N] Mode Control
Determine each I/O mode of Px.n pins.
00 = Px.n is in Input mode.
01 = Px.n is in Push-pull Output mode.
10 = Px.n is in Open-drain Output mode.
11 = Reserved.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[19:18]MODE9
Port A-f I/O Pin[N] Mode Control
Determine each I/O mode of Px.n pins.
00 = Px.n is in Input mode.
01 = Px.n is in Push-pull Output mode.
10 = Px.n is in Open-drain Output mode.
11 = Reserved.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[21:20]MODE10
Port A-f I/O Pin[N] Mode Control
Determine each I/O mode of Px.n pins.
00 = Px.n is in Input mode.
01 = Px.n is in Push-pull Output mode.
10 = Px.n is in Open-drain Output mode.
11 = Reserved.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[23:22]MODE11
Port A-f I/O Pin[N] Mode Control
Determine each I/O mode of Px.n pins.
00 = Px.n is in Input mode.
01 = Px.n is in Push-pull Output mode.
10 = Px.n is in Open-drain Output mode.
11 = Reserved.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[25:24]MODE12
Port A-f I/O Pin[N] Mode Control
Determine each I/O mode of Px.n pins.
00 = Px.n is in Input mode.
01 = Px.n is in Push-pull Output mode.
10 = Px.n is in Open-drain Output mode.
11 = Reserved.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[27:26]MODE13
Port A-f I/O Pin[N] Mode Control
Determine each I/O mode of Px.n pins.
00 = Px.n is in Input mode.
01 = Px.n is in Push-pull Output mode.
10 = Px.n is in Open-drain Output mode.
11 = Reserved.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[29:28]MODE14
Port A-f I/O Pin[N] Mode Control
Determine each I/O mode of Px.n pins.
00 = Px.n is in Input mode.
01 = Px.n is in Push-pull Output mode.
10 = Px.n is in Open-drain Output mode.
11 = Reserved.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[31:30]MODE15
Port A-f I/O Pin[N] Mode Control
Determine each I/O mode of Px.n pins.
00 = Px.n is in Input mode.
01 = Px.n is in Push-pull Output mode.
10 = Px.n is in Open-drain Output mode.
11 = Reserved.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.

Definition at line 11764 of file Nano103.h.

◆ PIN

GPIO_T::PIN

[0x0010] Pn Pin Value

PIN

Offset: 0x10 Pn Pin Value

BitsFieldDescriptions
[0]PIN0
Port A-f Pin[N] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin
If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[1]PIN1
Port A-f Pin[N] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin
If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[2]PIN2
Port A-f Pin[N] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin
If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[3]PIN3
Port A-f Pin[N] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin
If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[4]PIN4
Port A-f Pin[N] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin
If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[5]PIN5
Port A-f Pin[N] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin
If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[6]PIN6
Port A-f Pin[N] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin
If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[7]PIN7
Port A-f Pin[N] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin
If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[8]PIN8
Port A-f Pin[N] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin
If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[9]PIN9
Port A-f Pin[N] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin
If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[10]PIN10
Port A-f Pin[N] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin
If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[11]PIN11
Port A-f Pin[N] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin
If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[12]PIN12
Port A-f Pin[N] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin
If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[13]PIN13
Port A-f Pin[N] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin
If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[14]PIN14
Port A-f Pin[N] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin
If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[15]PIN15
Port A-f Pin[N] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin
If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.

Definition at line 11768 of file Nano103.h.

◆ PUEN

GPIO_T::PUEN

[0x0024] Pn Pull-Up Enable Control Register

PUEN

Offset: 0x24 Pn Pull-Up Enable Control Register

BitsFieldDescriptions
[0]PUEN0
Port A-f Pin[N] Pull-up Enable Bit
Read :
0 = Px.n internal pull-up resistor Disabled.
1 = Px.n internal pull-up resistor Enabled.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[1]PUEN1
Port A-f Pin[N] Pull-up Enable Bit
Read :
0 = Px.n internal pull-up resistor Disabled.
1 = Px.n internal pull-up resistor Enabled.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[2]PUEN2
Port A-f Pin[N] Pull-up Enable Bit
Read :
0 = Px.n internal pull-up resistor Disabled.
1 = Px.n internal pull-up resistor Enabled.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[3]PUEN3
Port A-f Pin[N] Pull-up Enable Bit
Read :
0 = Px.n internal pull-up resistor Disabled.
1 = Px.n internal pull-up resistor Enabled.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[4]PUEN4
Port A-f Pin[N] Pull-up Enable Bit
Read :
0 = Px.n internal pull-up resistor Disabled.
1 = Px.n internal pull-up resistor Enabled.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[5]PUEN5
Port A-f Pin[N] Pull-up Enable Bit
Read :
0 = Px.n internal pull-up resistor Disabled.
1 = Px.n internal pull-up resistor Enabled.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[6]PUEN6
Port A-f Pin[N] Pull-up Enable Bit
Read :
0 = Px.n internal pull-up resistor Disabled.
1 = Px.n internal pull-up resistor Enabled.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[7]PUEN7
Port A-f Pin[N] Pull-up Enable Bit
Read :
0 = Px.n internal pull-up resistor Disabled.
1 = Px.n internal pull-up resistor Enabled.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[8]PUEN8
Port A-f Pin[N] Pull-up Enable Bit
Read :
0 = Px.n internal pull-up resistor Disabled.
1 = Px.n internal pull-up resistor Enabled.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[9]PUEN9
Port A-f Pin[N] Pull-up Enable Bit
Read :
0 = Px.n internal pull-up resistor Disabled.
1 = Px.n internal pull-up resistor Enabled.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[10]PUEN10
Port A-f Pin[N] Pull-up Enable Bit
Read :
0 = Px.n internal pull-up resistor Disabled.
1 = Px.n internal pull-up resistor Enabled.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[11]PUEN11
Port A-f Pin[N] Pull-up Enable Bit
Read :
0 = Px.n internal pull-up resistor Disabled.
1 = Px.n internal pull-up resistor Enabled.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[12]PUEN12
Port A-f Pin[N] Pull-up Enable Bit
Read :
0 = Px.n internal pull-up resistor Disabled.
1 = Px.n internal pull-up resistor Enabled.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[13]PUEN13
Port A-f Pin[N] Pull-up Enable Bit
Read :
0 = Px.n internal pull-up resistor Disabled.
1 = Px.n internal pull-up resistor Enabled.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[14]PUEN14
Port A-f Pin[N] Pull-up Enable Bit
Read :
0 = Px.n internal pull-up resistor Disabled.
1 = Px.n internal pull-up resistor Enabled.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.
[15]PUEN15
Port A-f Pin[N] Pull-up Enable Bit
Read :
0 = Px.n internal pull-up resistor Disabled.
1 = Px.n internal pull-up resistor Enabled.
Note1:
Max. n=15 for port A/B/C/D/E.
Max. n=7 for port F.
Note2:
The PA.7/PB.12/PC.4/PC.5/PC.12/PC.13/PD.0/PD.1/PD.2/PD.3/PD.4/PD.5/PD.8/PD.9/
PD.10/PD.11/PD.12/PD.13/PE.0/PE.1/PE.2/PE.3/PE.4/PE.6/PE.7/PE.8/PE.9/PE.10/PE.11/
PE.12/PE.13/PE.14/PE.15/PF.4/PF.5 pin is ignored.

Definition at line 11773 of file Nano103.h.


The documentation for this struct was generated from the following file: