| Nano103 BSP V3.01.002 The Board Support Package for Nano103 Series

adc.h
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1 /**************************************************************************/
12 #ifndef __ADC_H__
13 #define __ADC_H__
14
15 #ifdef __cplusplus
16 extern "C"
17 {
18 #endif
19
20
33 #define ADC_CH_0_MASK (1UL << 0)
34 #define ADC_CH_1_MASK (1UL << 1)
35 #define ADC_CH_2_MASK (1UL << 2)
36 #define ADC_CH_3_MASK (1UL << 3)
37 #define ADC_CH_4_MASK (1UL << 4)
38 #define ADC_CH_5_MASK (1UL << 5)
39 #define ADC_CH_6_MASK (1UL << 6)
40 #define ADC_CH_7_MASK (1UL << 7)
41 #define ADC_CH_12_MASK (1UL << 12)
42 #define ADC_CH_13_MASK (1UL << 13)
43 #define ADC_CH_14_MASK (1UL << 14)
44 #define ADC_CH_15_MASK (1UL << 15)
45 #define ADC_CH_16_MASK (1UL << 16)
46 #define ADC_CH_17_MASK (1UL << 17)
47 #define ADC_ADCHER_CHEN_Msk (0x3FFFF)
48 #define ADC_PDMADATA_AD_PDMA_Msk (0xFFF)
49 #define ADC_CMP_LESS_THAN (0UL)
50 #define ADC_CMP_GREATER_OR_EQUAL_TO (ADC_CMP0_CMPCOND_Msk)
51 #define ADC_TRIGGER_BY_EXT_PIN (0UL)
52 #define ADC_TRIGGER_BY_PWM (ADC_CTL_HWTRGSEL_Msk)
53 #define ADC_LOW_LEVEL_TRIGGER (0UL << ADC_CTL_HWTRGCOND_Pos)
54 #define ADC_HIGH_LEVEL_TRIGGER (1UL << ADC_CTL_HWTRGCOND_Pos)
55 #define ADC_FALLING_EDGE_TRIGGER (2UL << ADC_CTL_HWTRGCOND_Pos)
56 #define ADC_RISING_EDGE_TRIGGER (3UL << ADC_CTL_HWTRGCOND_Pos)
57 #define ADC_ADF_INT (ADC_STATUS_ADIF_Msk)
58 #define ADC_CMP0_INT (ADC_STATUS_ADCMPF0_Msk)
59 #define ADC_CMP1_INT (ADC_STATUS_ADCMPF1_Msk)
60 #define ADC_INPUT_MODE_SINGLE_END (0UL << ADC_CTL_DIFF_Pos)
61 #define ADC_INPUT_MODE_DIFFERENTIAL (1UL << ADC_CTL_DIFF_Pos)
62 #define ADC_OPERATION_MODE_SINGLE (0UL << ADC_CTL_ADMD_Pos)
63 #define ADC_OPERATION_MODE_SINGLE_CYCLE (2UL << ADC_CTL_ADMD_Pos)
64 #define ADC_OPERATION_MODE_CONTINUOUS (3UL << ADC_CTL_ADMD_Pos)
65 #define ADC_RESSEL_6_BIT (0UL << ADC_CTL_RESSEL_Pos)
66 #define ADC_RESSEL_8_BIT (1UL << ADC_CTL_RESSEL_Pos)
67 #define ADC_RESSEL_10_BIT (2UL << ADC_CTL_RESSEL_Pos)
68 #define ADC_RESSEL_12_BIT (3UL << ADC_CTL_RESSEL_Pos)
69 #define ADC_REFSEL_POWER (0UL << ADC_CTL_REFSEL_Pos)
70 #define ADC_REFSEL_INT_VREF (1UL << ADC_CTL_REFSEL_Pos)
71 #define ADC_REFSEL_VREF (2UL << ADC_CTL_REFSEL_Pos)
73 /* end of group NANO103_ADC_EXPORTED_CONSTANTS */
74
75
87 #define ADC_GET_CONVERSION_DATA(adc, u32ChNum) ((ADC->DAT[u32ChNum]) & ADC_DAT0_RESULT_Msk)
88
99 #define ADC_GET_INT_FLAG(adc, u32Mask) (ADC->STATUS & (u32Mask))
100
111 #define ADC_CLR_INT_FLAG(adc, u32Mask) (ADC->STATUS = (ADC->STATUS & ~(ADC_STATUS_ADIF_Msk | \
112 ADC_STATUS_ADCMPF0_Msk | \
113 ADC_STATUS_ADCMPF1_Msk)) | (u32Mask))
114
123 #define ADC_IS_BUSY(adc) (ADC->STATUS & ADC_STATUS_BUSY_Msk ? 1 : 0)
124
134 #define ADC_IS_DATA_OVERRUN(adc, u32ChNum) (ADC->DAT[u32ChNum] & ADC_DAT0_OV_Msk ? 1 : 0)
135
145 #define ADC_IS_DATA_VALID(adc, u32ChNum) (ADC->DAT[u32ChNum] & ADC_DAT0_VALID_Msk ? 1 : 0)
146
153 #define ADC_POWER_DOWN(adc) (ADC->CTL &= ~ADC_CTL_ADCEN_Msk)
154
161 #define ADC_POWER_ON(adc) \
162 do { \
163 ADC->CTL |= ADC_CTL_ADCEN_Msk; \
164 while ((!(ADC->STATUS & ADC_STATUS_INITRDY_Msk)) || (!(ADC->PWD & ADC_PWD_PWUPRDY_Msk))); \
165 } while(0)
166
182 #define ADC_ENABLE_CMP0(adc, \
183 u32ChNum, \
184 u32Condition, \
185 u32Data, \
186 u32MatchCount) (ADC->CMP0 = ((u32ChNum) << ADC_CMP0_CMPCH_Pos) | \
187 (u32Condition) | \
188 ((u32Data) << ADC_CMP0_CMPDAT_Pos) | \
189 (((u32MatchCount) - 1) << ADC_CMP0_CMPMCNT_Pos) |\
190 ADC_CMP0_ADCMPEN_Msk)
191
197 #define ADC_DISABLE_CMP0(adc) (ADC->CMP0 = 0)
198
214 #define ADC_ENABLE_CMP1(adc, \
215 u32ChNum, \
216 u32Condition, \
217 u32Data, \
218 u32MatchCount) (ADC->CMP1 = ((u32ChNum) << ADC_CMP1_CMPCH_Pos) | \
219 (u32Condition) | \
220 ((u32Data) << ADC_CMP1_CMPDAT_Pos) | \
221 ((u32MatchCount - 1) << ADC_CMP1_CMPMCNT_Pos) |\
222 ADC_CMP1_ADCMPEN_Msk)
223
229 #define ADC_DISABLE_CMP1(adc) (ADC->CMP1 = 0)
230
238 #define ADC_SET_INPUT_CHANNEL(adc, u32Mask) (ADC->CHEN = (ADC->CHEN & ~ADC_ADCHER_CHEN_Msk) | (u32Mask))
239
246 #define ADC_START_CONV(adc) (ADC->CTL |= ADC_CTL_SWTRG_Msk)
247
254 #define ADC_STOP_CONV(adc) (ADC->CTL &= ~ADC_CTL_SWTRG_Msk)
255
267 #define ADC_SET_RESOLUTION(adc, u32Resolution) (ADC->CTL = (ADC->CTL & ~ADC_CTL_RESSEL_Msk) | u32Resolution)
268
279 #define ADC_SET_REF_VOLTAGE(adc, u32Ref) (ADC->CTL = (ADC->CTL & ~ADC_CTL_REFSEL_Msk) | u32Ref)
280
289 #define ADC_SET_POWERDOWN_MODE(adc, u32Mode, u32CalEn) \
290 ADC->PWD = (ADC->PWD & ~(ADC_PWD_PWDMOD_Msk | ADC_PWD_PWDCALEN_Msk)) \
291 | (u32Mode << ADC_PWD_PWDMOD_Pos) | (u32CalEn << ADC_PWD_PWDCALEN_Pos)
292
299 #define ADC_ENABLE_PDMA(adc) (ADC->CTL |= ADC_CTL_PTEN_Msk)
300
307 #define ADC_DISABLE_PDMA(adc) (ADC->CTL &= ~ADC_CTL_PTEN_Msk)
308
315 #define ADC_GET_PDMA_DATA(adc) (ADC->PDMA & ADC_PDMA_AD_PDMA_Msk)
316
317 void ADC_Open(ADC_T *adc,
318 uint32_t u32InputMode,
319 uint32_t u32OpMode,
320 uint32_t u32ChMask);
321 void ADC_Close(ADC_T *adc);
322 void ADC_EnableHWTrigger(ADC_T *adc,
323 uint32_t u32Source,
324 uint32_t u32Param);
325 void ADC_DisableHWTrigger(ADC_T *adc);
326 void ADC_EnableTimerTrigger(ADC_T *adc,
327 uint32_t u32Source,
328 uint32_t u32PDMACnt);
329 void ADC_DisableTimerTrigger(ADC_T *adc);
330 void ADC_SetExtraSampleTime(ADC_T *adc,
331 uint32_t u32ChNum,
332 uint32_t u32SampleTime);
333 void ADC_EnableInt(ADC_T *adc, uint32_t u32Mask);
334 void ADC_DisableInt(ADC_T *adc, uint32_t u32Mask);
335
336
337 /* end of group NANO103_ADC_EXPORTED_FUNCTIONS */
339 /* end of group NANO103_ADC_Driver */
341 /* end of group NANO103_Device_Driver */
343
344 #ifdef __cplusplus
345 }
346 #endif
347
348 #endif //__ADC_H__
349
350 /*** (C) COPYRIGHT 2015 Nuvoton Technology Corp. ***/
ADC_DisableInt
void ADC_DisableInt(ADC_T *adc, uint32_t u32Mask)
Disable the interrupt(s) selected by u32Mask parameter.
Definition: adc.c:190
ADC_EnableTimerTrigger
void ADC_EnableTimerTrigger(ADC_T *adc, uint32_t u32Source, uint32_t u32PDMACnt)
Config and enable timer trigger.
Definition: adc.c:116
ADC_Close
void ADC_Close(ADC_T *adc)
Disable ADC module.
Definition: adc.c:59
ADC_DisableHWTrigger
void ADC_DisableHWTrigger(ADC_T *adc)
Disable hardware trigger ADC function.
Definition: adc.c:103
ADC_SetExtraSampleTime
void ADC_SetExtraSampleTime(ADC_T *adc, uint32_t u32ChNum, uint32_t u32SampleTime)
Configure the hardware trigger condition and enable hardware trigger.
Definition: adc.c:145
ADC_EnableInt
void ADC_EnableInt(ADC_T *adc, uint32_t u32Mask)
Enable the interrupt(s) selected by u32Mask parameter.
Definition: adc.c:167
ADC_EnableHWTrigger
void ADC_EnableHWTrigger(ADC_T *adc, uint32_t u32Source, uint32_t u32Param)
Configure the hardware trigger condition and enable hardware trigger.
Definition: adc.c:81
ADC_Open
void ADC_Open(ADC_T *adc, uint32_t u32InputMode, uint32_t u32OpMode, uint32_t u32ChMask)
This API configures ADC module to be ready for convert the input from selected channel.
Definition: adc.c:41
ADC_DisableTimerTrigger
void ADC_DisableTimerTrigger(ADC_T *adc)
Disable timer trigger ADC function.
Definition: adc.c:131
ADC_T
Definition: Nano103.h:23603