|
| enum | IRQn {
NonMaskableInt_IRQn = -14,
HardFault_IRQn = -13,
SVCall_IRQn = -5,
PendSV_IRQn = -2,
SysTick_IRQn = -1,
BOD_IRQn = 0,
WDT_IRQn = 1,
EINT0_IRQn = 2,
EINT1_IRQn = 3,
GPABC_IRQn = 4,
GPDEF_IRQn = 5,
PWM0_IRQn = 6,
TMR0_IRQn = 8,
TMR1_IRQn = 9,
TMR2_IRQn = 10,
TMR3_IRQn = 11,
UART0_IRQn = 12,
UART1_IRQn = 13,
SPI0_IRQn = 14,
SPI1_IRQn = 15,
SPI2_IRQn = 16,
HIRC_IRQn = 17,
I2C0_IRQn = 18,
I2C1_IRQn = 19,
SC0_IRQn = 21,
SC1_IRQn = 22,
CKSD_IRQn = 24,
PDMA_IRQn = 26,
SPI3_IRQn = 27,
PDWU_IRQn = 28,
ADC_IRQn = 29,
ACMP_IRQn = 30,
RTC_IRQn = 31
} |
| |
Configuration of the Cortex-M0 Processor and Core Peripherals
◆ __CM0_REV
Core Revision r2p1
Definition at line 129 of file Nano103.h.
◆ __FPU_PRESENT
FPU present or not
Definition at line 133 of file Nano103.h.
◆ __MPU_PRESENT
MPU present or not
Definition at line 132 of file Nano103.h.
◆ __NVIC_PRIO_BITS
| #define __NVIC_PRIO_BITS 2 |
Number of Bits used for Priority Levels
Definition at line 130 of file Nano103.h.
◆ __Vendor_SysTickConfig
| #define __Vendor_SysTickConfig 0 |
Set to 1 if different SysTick Config is used
Definition at line 131 of file Nano103.h.
◆ IRQn_Type
Interrupt Number Definition. The maximum of 32 Specific Interrupts are possible.
◆ IRQn
Interrupt Number Definition. The maximum of 32 Specific Interrupts are possible.
| Enumerator |
|---|
| NonMaskableInt_IRQn | 2 Non Maskable Interrupt
|
| HardFault_IRQn | 3 Cortex-M0 Hard Fault Interrupt
|
| SVCall_IRQn | 11 Cortex-M0 SV Call Interrupt
|
| PendSV_IRQn | 14 Cortex-M0 Pend SV Interrupt
|
| SysTick_IRQn | 15 Cortex-M0 System Tick Interrupt
|
| BOD_IRQn | Brownout low voltage detected interrupt
|
| WDT_IRQn | Watch Dog Timer interrupt
|
| EINT0_IRQn | External signal interrupt from PB.14 pin
|
| EINT1_IRQn | External signal interrupt from PB.15 pin
|
| GPABC_IRQn | External signal interrupt from PA[15:0]/PB[13:0]/PC[15:0]
|
| GPDEF_IRQn | External interrupt from PD[15:0]/PE[15:0]/PF[15:0]
|
| PWM0_IRQn | PWM 0 interrupt
|
| TMR0_IRQn | Timer 0 interrupt
|
| TMR1_IRQn | Timer 1 interrupt
|
| TMR2_IRQn | Timer 2 interrupt
|
| TMR3_IRQn | Timer 3 interrupt
|
| UART0_IRQn | UART0 interrupt
|
| UART1_IRQn | UART1 interrupt
|
| SPI0_IRQn | SPI0 interrupt
|
| SPI1_IRQn | SPI1 interrupt
|
| SPI2_IRQn | SPI2 interrupt
|
| HIRC_IRQn | HIRC interrupt
|
| I2C0_IRQn | I2C0 interrupt
|
| I2C1_IRQn | I2C1 interrupt
|
| SC0_IRQn | Smart Card 0 interrupt
|
| SC1_IRQn | Smart Card 1 interrupt
|
| CKSD_IRQn | Clock stop detect interrupt
|
| PDMA_IRQn | PDMA interrupt
|
| SPI3_IRQn | SPI3 interrupt
|
| PDWU_IRQn | Power Down Wake up interrupt
|
| ADC_IRQn | ADC interrupt
|
| ACMP_IRQn | Analog Comparator interrupt
|
| RTC_IRQn | Real time clock interrupt
|
Definition at line 80 of file Nano103.h.