| Nano103 BSP V3.01.002 The Board Support Package for Nano103 Series

Functions
CLK Exported Functions
NANO103 Device Driver » CLK Driver

## Functions
void | CLK_DisableCKO (void)
| This function disable frequency output function. More...
void | CLK_EnableCKO (uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En)
| This function enable frequency divider module clock, enable frequency divider clock function and configure frequency divider. More...
void | CLK_PowerDown (void)
| This function let system enter to fractal fx-2-down mode. More...
void | CLK_Idle (void)
| This function let system enter to Idle mode. More...
uint32_t | CLK_GetHXTFreq (void)
| This function get external high frequency crystal frequency. The frequency unit is Hz. More...
uint32_t | CLK_GetLXTFreq (void)
| This function get external low frequency crystal frequency. The frequency unit is Hz. More...
uint32_t | CLK_GetHCLKFreq (void)
| This function get HCLK frequency. The frequency unit is Hz. More...
uint32_t | CLK_GetPCLK0Freq (void)
| This function get PCLK0 frequency. The frequency unit is Hz. More...
uint32_t | CLK_GetPCLK1Freq (void)
| This function get PCLK1 frequency. The frequency unit is Hz. More...
uint32_t | CLK_GetCPUFreq (void)
| This function get CPU frequency. The frequency unit is Hz. More...
uint32_t | CLK_GetPLLClockFreq (void)
| This function get PLL frequency. The frequency unit is Hz. More...
uint32_t | CLK_SetCoreClock (uint32_t u32Hclk)
| This function set HCLK frequency. The frequency unit is Hz. The range of u32Hclk is 16 ~ 48 MHz. More...
void | CLK_SetHCLK (uint32_t u32ClkSrc, uint32_t u32ClkDiv)
| This function set HCLK clock source and HCLK clock divider. More...
void | CLK_SetPCLK0 (uint32_t u32ClkDiv)
| This function set APB PCLK0 clock divider. More...
void | CLK_SetPCLK1 (uint32_t u32ClkDiv)
| This function set APB PCLK1 clock divider. More...
void | CLK_SetModuleClock (uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv)
| This function set selected module clock source and module clock divider. More...
void | CLK_SetSysTickClockSrc (uint32_t u32ClkSrc)
void | CLK_EnableXtalRC (uint32_t u32ClkMask)
| This function enable clock source. More...
void | CLK_DisableXtalRC (uint32_t u32ClkMask)
| This function disable clock source. More...
void | CLK_EnableModuleClock (uint32_t u32ModuleIdx)
| This function enable module clock. More...
void | CLK_DisableModuleClock (uint32_t u32ModuleIdx)
| This function disable module clock. More...
uint32_t | CLK_EnablePLL (uint32_t u32PllClkSrc, uint32_t u32PllFreq)
| This function set PLL frequency. More...
void | CLK_DisablePLL (void)
| This function disable PLL. More...
void | CLK_SysTickDelay (uint32_t us)
| This function execute delay function. More...
void | CLK_EnableSysTick (uint32_t u32ClkSrc, uint32_t u32Count)
| Enable System Tick counter. More...
void | CLK_DisableSysTick (void)
| Disable System Tick counter. More...
uint32_t | CLK_WaitClockReady (uint32_t u32ClkMask)
| This function check selected clock source status. More...

## Detailed Description

## Function Documentation

## ◆ CLK_DisableCKO()

void CLK_DisableCKO | ( | void |  | ) |

This function disable frequency output function.

Parameters

  None |

Returns
  None

Definition at line 32 of file clk.c.

## ◆ CLK_DisableModuleClock()

void CLK_DisableModuleClock | ( | uint32_t | u32ModuleIdx | ) |

This function disable module clock.

Parameters

  [in] | u32ModuleIdx | is module index. Including : GPIO_MODULE PDMA_MODULE ISP_MODULE SRAM_MODULE STC_MODULE WDT_MODULE WWDT_MODULE RTC_MODULE TMR0_MODULE TMR1_MODULE TMR2_MODULE TMR3_MODULE CLKO_MODULE I2C0_MODULE I2C1_MODULE ACMP0_MODULE SPI0_MODULE SPI1_MODULE SPI2_MODULE SPI3_MODULE UART0_MODULE UART1_MODULE PWM0_MODULE ADC_MODULE SC0_MODULE SC1_MODULE

Returns
  None

Definition at line 500 of file clk.c.

## ◆ CLK_DisablePLL()

void CLK_DisablePLL | ( | void |  | ) |

This function disable PLL.

Parameters

  None |

Returns
  None

Definition at line 582 of file clk.c.

## ◆ CLK_DisableSysTick()

void CLK_DisableSysTick | ( | void |  | ) |

Disable System Tick counter.

Returns
  None

This function disable System Tick counter.

Definition at line 635 of file clk.c.

## ◆ CLK_DisableXtalRC()

void CLK_DisableXtalRC | ( | uint32_t | u32ClkMask | ) |

This function disable clock source.

Parameters

  u32ClkMask | is clock source mask. Including: CLK_PWRCTL_HXTEN_Msk CLK_PWRCTL_LXTEN_Msk CLK_PWRCTL_HIRC0EN_Msk CLK_PWRCTL_LIRCEN_Msk CLK_PWRCTL_HIRC1EN_Msk CLK_PWRCTL_MIRCEN_Msk

Returns
  None

Definition at line 428 of file clk.c.

## ◆ CLK_EnableCKO()

void CLK_EnableCKO | ( | uint32_t | u32ClkSrc,
|  | uint32_t | u32ClkDiv,
|  | uint32_t | u32ClkDivBy1En
| ) |  |

This function enable frequency divider module clock, enable frequency divider clock function and configure frequency divider.

Parameters

  u32ClkSrc | is frequency divider function clock source CLK_CLKSEL2_CLKOSEL_HXT CLK_CLKSEL2_CLKOSEL_LXT CLK_CLKSEL2_CLKOSEL_HCLK CLK_CLKSEL2_CLKOSEL_HIRC CLK_CLKSEL2_CLKOSEL_MIRC
  u32ClkDiv | is divider output frequency selection.
  u32ClkDivBy1En | is frequency divided by one enable.

Returns
  None

Output selected clock to CKO. The output clock frequency is divided by u32ClkDiv. The formula is: CKO frequency = (Clock source frequency) / 2^(u32ClkDiv + 1) This function is just used to set CKO clock. User must enable I/O for CKO clock output pin by themselves.

Definition at line 57 of file clk.c.

## ◆ CLK_EnableModuleClock()

void CLK_EnableModuleClock | ( | uint32_t | u32ModuleIdx | ) |

This function enable module clock.

Parameters

  [in] | u32ModuleIdx | is module index. Including : GPIO_MODULE PDMA_MODULE ISP_MODULE SRAM_MODULE STC_MODULE WDT_MODULE WWDT_MODULE RTC_MODULE TMR0_MODULE TMR1_MODULE TMR2_MODULE TMR3_MODULE CLKO_MODULE I2C0_MODULE I2C1_MODULE ACMP0_MODULE SPI0_MODULE SPI1_MODULE SPI2_MODULE SPI3_MODULE UART0_MODULE UART1_MODULE PWM0_MODULE ADC_MODULE SC0_MODULE SC1_MODULE

Returns
  None

Definition at line 464 of file clk.c.

## ◆ CLK_EnablePLL()

uint32_t CLK_EnablePLL | ( | uint32_t | u32PllClkSrc,
|  | uint32_t | u32PllFreq
| ) |  |

This function set PLL frequency.

Parameters

  [in] | u32PllClkSrc | is PLL clock source. Including : CLK_PLLCTL_PLL_SRC_MIRC CLK_PLLCTL_PLL_SRC_HIRC CLK_PLLCTL_PLL_SRC_HXT
  [in] | u32PllFreq | is PLL frequency

Returns
  None

Definition at line 514 of file clk.c.

## ◆ CLK_EnableSysTick()

void CLK_EnableSysTick | ( | uint32_t | u32ClkSrc,
|  | uint32_t | u32Count
| ) |  |

Enable System Tick counter.

Parameters

  [in] | u32ClkSrc | is System Tick clock source. Including: CLK_CLKSEL0_STCLKSEL_HCLK_DIV8 CLK_CLKSEL0_STCLKSEL_HCLK
  [in] | u32Count | is System Tick reload value. It should be 0x1~0xFFFFFF.

Returns
  None

This function set System Tick clock source, reload value, enable System Tick counter and interrupt. The register write-protection function should be disabled before using this function.

Definition at line 616 of file clk.c.

## ◆ CLK_EnableXtalRC()

void CLK_EnableXtalRC | ( | uint32_t | u32ClkMask | ) |

This function enable clock source.

Parameters

  [in] | u32ClkMask | is clock source mask. Including: CLK_PWRCTL_HXTEN_Msk CLK_PWRCTL_LXTEN_Msk CLK_PWRCTL_HIRC0EN_Msk CLK_PWRCTL_LIRCEN_Msk CLK_PWRCTL_HIRC1EN_Msk CLK_PWRCTL_MIRCEN_Msk

Returns
  None

Definition at line 412 of file clk.c.

## ◆ CLK_GetCPUFreq()

uint32_t CLK_GetCPUFreq | ( | void |  | ) |

This function get CPU frequency. The frequency unit is Hz.

Parameters

  None |

Returns
  CPU frequency

Definition at line 165 of file clk.c.

## ◆ CLK_GetHCLKFreq()

uint32_t CLK_GetHCLKFreq | ( | void |  | ) |

This function get HCLK frequency. The frequency unit is Hz.

Parameters

  None |

Returns
  HCLK frequency

Definition at line 126 of file clk.c.

## ◆ CLK_GetHXTFreq()

uint32_t CLK_GetHXTFreq | ( | void |  | ) |

This function get external high frequency crystal frequency. The frequency unit is Hz.

Parameters

  None |

Returns
  None

Definition at line 100 of file clk.c.

## ◆ CLK_GetLXTFreq()

uint32_t CLK_GetLXTFreq | ( | void |  | ) |

This function get external low frequency crystal frequency. The frequency unit is Hz.

Parameters

  None |

Returns
  LXT frequency

Definition at line 113 of file clk.c.

## ◆ CLK_GetPCLK0Freq()

uint32_t CLK_GetPCLK0Freq | ( | void |  | ) |

This function get PCLK0 frequency. The frequency unit is Hz.

Parameters

  None |

Returns
  PCLK0 frequency

Definition at line 137 of file clk.c.

## ◆ CLK_GetPCLK1Freq()

uint32_t CLK_GetPCLK1Freq | ( | void |  | ) |

This function get PCLK1 frequency. The frequency unit is Hz.

Parameters

  None |

Returns
  PCLK1 frequency

Definition at line 151 of file clk.c.

## ◆ CLK_GetPLLClockFreq()

uint32_t CLK_GetPLLClockFreq | ( | void |  | ) |

This function get PLL frequency. The frequency unit is Hz.

Parameters

  None |

Returns
  PLL frequency

Definition at line 176 of file clk.c.

## ◆ CLK_Idle()

void CLK_Idle | ( | void |  | ) |

This function let system enter to Idle mode.

Parameters

  None |

Returns
  None

Definition at line 89 of file clk.c.

## ◆ CLK_PowerDown()

void CLK_PowerDown | ( | void |  | ) |

This function let system enter to fractal fx-2-down mode.

Parameters

  None |

Returns
  None

Definition at line 75 of file clk.c.

## ◆ CLK_SetCoreClock()

uint32_t CLK_SetCoreClock | ( | uint32_t | u32Hclk | ) |

This function set HCLK frequency. The frequency unit is Hz. The range of u32Hclk is 16 ~ 48 MHz.

Parameters

  [in] | u32Hclk | is HCLK frequency

Returns
  None

Definition at line 227 of file clk.c.

## ◆ CLK_SetHCLK()

void CLK_SetHCLK | ( | uint32_t | u32ClkSrc,
|  | uint32_t | u32ClkDiv
| ) |  |

This function set HCLK clock source and HCLK clock divider.

Parameters

  [in] | u32ClkSrc | is HCLK clock source. Including : CLK_CLKSEL0_HCLKSEL_HXT CLK_CLKSEL0_HCLKSEL_LXT CLK_CLKSEL0_HCLKSEL_PLL CLK_CLKSEL0_HCLKSEL_LIRC CLK_CLKSEL0_HCLKSEL_HIRC CLK_CLKSEL0_HCLKSEL_HIRC0 CLK_CLKSEL0_HCLKSEL_HIRC1 CLK_CLKSEL0_HCLKSEL_MIRC
  [in] | u32ClkDiv | is HCLK clock divider. Including : CLK_HCLK_CLK_DIVIDER(x)

Returns
  None

Definition at line 256 of file clk.c.

## ◆ CLK_SetModuleClock()

void CLK_SetModuleClock | ( | uint32_t | u32ModuleIdx,
|  | uint32_t | u32ClkSrc,
|  | uint32_t | u32ClkDiv
| ) |  |

This function set selected module clock source and module clock divider.

Parameters

  [in] | u32ModuleIdx | is module index.
  [in] | u32ClkSrc | is module clock source.
  [in] | u32ClkDiv | is module clock divider.

Returns
  None

Valid parameter combinations listed in following table:

- Module index | Clock source | Divider
  --- | --- | ---
  ISP_MODULE | CLK_CLKSEL0_ISPSEL_HIRC | x
  ISP_MODULE | CLK_CLKSEL0_ISPSEL_MIRC | x
  UART0_MODULE | CLK_CLKSEL1_UART0SEL_HXT | CLK_UART0_CLK_DIVIDER(x)
  UART0_MODULE | CLK_CLKSEL1_UART0SEL_LXT | CLK_UART0_CLK_DIVIDER(x)
  UART0_MODULE | CLK_CLKSEL1_UART0SEL_PLL | CLK_UART0_CLK_DIVIDER(x)
  UART0_MODULE | CLK_CLKSEL1_UART0SEL_HIRC | CLK_UART0_CLK_DIVIDER(x)
  UART0_MODULE | CLK_CLKSEL1_UART0SEL_MIRC | CLK_UART0_CLK_DIVIDER(x)
  PWM0_MODULE | CLK_CLKSEL1_PWM0SEL_PLL | x
  PWM0_MODULE | CLK_CLKSEL1_PWM0SEL_PCLK0 | x
  TMR0_MODULE | CLK_CLKSEL1_TMR0SEL_HXT | CLK_TMR0_CLK_DIVIDER(x)
  TMR0_MODULE | CLK_CLKSEL1_TMR0SEL_LXT | CLK_TMR0_CLK_DIVIDER(x)
  TMR0_MODULE | CLK_CLKSEL1_TMR0SEL_LIRC | CLK_TMR0_CLK_DIVIDER(x)
  TMR0_MODULE | CLK_CLKSEL1_TMR0SEL_HIRC | CLK_TMR0_CLK_DIVIDER(x)
  TMR0_MODULE | CLK_CLKSEL1_TMR0SEL_MIRC | CLK_TMR0_CLK_DIVIDER(x)
  TMR0_MODULE | CLK_CLKSEL1_TMR0SEL_EXT | CLK_TMR0_CLK_DIVIDER(x)
  TMR1_MODULE | CLK_CLKSEL1_TMR1SEL_HXT | CLK_TMR1_CLK_DIVIDER(x)
  TMR1_MODULE | CLK_CLKSEL1_TMR1SEL_LXT | CLK_TMR1_CLK_DIVIDER(x)
  TMR1_MODULE | CLK_CLKSEL1_TMR1SEL_LIRC | CLK_TMR1_CLK_DIVIDER(x)
  TMR1_MODULE | CLK_CLKSEL1_TMR1SEL_HIRC | CLK_TMR1_CLK_DIVIDER(x)
  TMR1_MODULE | CLK_CLKSEL1_TMR1SEL_MIRC | CLK_TMR1_CLK_DIVIDER(x)
  TMR1_MODULE | CLK_CLKSEL1_TMR1SEL_EXT | CLK_TMR1_CLK_DIVIDER(x)
  ADC_MODULE | CLK_CLKSEL1_ADCSEL_HXT | CLK_ADC_CLK_DIVIDER(x)
  ADC_MODULE | CLK_CLKSEL1_ADCSEL_LXT | CLK_ADC_CLK_DIVIDER(x)
  ADC_MODULE | CLK_CLKSEL1_ADCSEL_PLL | CLK_ADC_CLK_DIVIDER(x)
  ADC_MODULE | CLK_CLKSEL1_ADCSEL_HIRC | CLK_ADC_CLK_DIVIDER(x)
  ADC_MODULE | CLK_CLKSEL1_ADCSEL_MIRC | CLK_ADC_CLK_DIVIDER(x)
  ADC_MODULE | CLK_CLKSEL1_ADCSEL_HCLK | CLK_ADC_CLK_DIVIDER(x)
  SPI0_MODULE | CLK_CLKSEL1_SPI0SEL_HXT | x
  SPI0_MODULE | CLK_CLKSEL1_SPI0SEL_PLL | x
  SPI0_MODULE | CLK_CLKSEL1_SPI0SEL_HIRC | x
  SPI0_MODULE | CLK_CLKSEL1_SPI0SEL_HCLK | x
  SPI2_MODULE | CLK_CLKSEL1_SPI2SEL_HXT | x
  SPI2_MODULE | CLK_CLKSEL1_SPI2SEL_PLL | x
  SPI2_MODULE | CLK_CLKSEL1_SPI2SEL_HIRC | x
  SPI2_MODULE | CLK_CLKSEL1_SPI2SEL_HCLK | x
  WDT_MODULE | CLK_CLKSEL1_WDTSEL_LXT | x
  WDT_MODULE | CLK_CLKSEL1_WDTSEL_LIRC | x
  WDT_MODULE | CLK_CLKSEL1_WDTSEL_HCLKDIV2048 | x
  WWDT_MODULE | CLK_CLKSEL1_WWDTSEL_LIRC | x
  WWDT_MODULE | CLK_CLKSEL1_WWDTSEL_HCLKDIV2048 | x
  UART1_MODULE | CLK_CLKSEL2_UART1SEL_HXT | CLK_UART1_CLK_DIVIDER(x)
  UART1_MODULE | CLK_CLKSEL2_UART1SEL_LXT | CLK_UART1_CLK_DIVIDER(x)
  UART1_MODULE | CLK_CLKSEL2_UART1SEL_PLL | CLK_UART1_CLK_DIVIDER(x)
  UART1_MODULE | CLK_CLKSEL2_UART1SEL_HIRC | CLK_UART1_CLK_DIVIDER(x)
  UART1_MODULE | CLK_CLKSEL2_UART1SEL_MIRC | CLK_UART1_CLK_DIVIDER(x)
  CLKO_MODULE | CLK_CLKSEL2_CLKOSEL_HXT | x
  CLKO_MODULE | CLK_CLKSEL2_CLKOSEL_LXT | x
  CLKO_MODULE | CLK_CLKSEL2_CLKOSEL_HIRC | x
  CLKO_MODULE | CLK_CLKSEL2_CLKOSEL_HIRC | x
  CLKO_MODULE | CLK_CLKSEL2_CLKOSEL_HCLK | x
  TMR2_MODULE | CLK_CLKSEL2_TMR2SEL_HXT | CLK_TMR2_CLK_DIVIDER(x)
  TMR2_MODULE | CLK_CLKSEL2_TMR2SEL_LXT | CLK_TMR2_CLK_DIVIDER(x)
  TMR2_MODULE | CLK_CLKSEL2_TMR2SEL_LIRC | CLK_TMR2_CLK_DIVIDER(x)
  TMR2_MODULE | CLK_CLKSEL2_TMR2SEL_HIRC | CLK_TMR2_CLK_DIVIDER(x)
  TMR2_MODULE | CLK_CLKSEL2_TMR2SEL_MIRC | CLK_TMR2_CLK_DIVIDER(x)
  TMR2_MODULE | CLK_CLKSEL2_TMR2SEL_EXT | CLK_TMR2_CLK_DIVIDER(x)
  TMR3_MODULE | CLK_CLKSEL2_TMR3SEL_HXT | CLK_TMR3_CLK_DIVIDER(x)
  TMR3_MODULE | CLK_CLKSEL2_TMR3SEL_LXT | CLK_TMR3_CLK_DIVIDER(x)
  TMR3_MODULE | CLK_CLKSEL2_TMR3SEL_LIRC | CLK_TMR3_CLK_DIVIDER(x)
  TMR3_MODULE | CLK_CLKSEL2_TMR3SEL_HIRC | CLK_TMR3_CLK_DIVIDER(x)
  TMR3_MODULE | CLK_CLKSEL2_TMR3SEL_MIRC | CLK_TMR3_CLK_DIVIDER(x)
  TMR3_MODULE | CLK_CLKSEL2_TMR3SEL_EXT | CLK_TMR3_CLK_DIVIDER(x)
  SC0_MODULE | CLK_CLKSEL2_SC0SEL_HXT | CLK_SC0_CLK_DIVIDER(x)
  SC0_MODULE | CLK_CLKSEL2_SC0SEL_PLL | CLK_SC0_CLK_DIVIDER(x)
  SC0_MODULE | CLK_CLKSEL2_SC0SEL_HIRC | CLK_SC0_CLK_DIVIDER(x)
  SC0_MODULE | CLK_CLKSEL2_SC0SEL_MIRC | CLK_SC0_CLK_DIVIDER(x)
  SC0_MODULE | CLK_CLKSEL2_SC0SEL_HCLK | CLK_SC0_CLK_DIVIDER(x)
  SPI1_MODULE | CLK_CLKSEL2_SPI1SEL_HXT | x
  SPI1_MODULE | CLK_CLKSEL2_SPI1SEL_PLL | x
  SPI1_MODULE | CLK_CLKSEL2_SPI1SEL_HIRC | x
  SPI1_MODULE | CLK_CLKSEL2_SPI1SEL_HCLK | x
  SPI3_MODULE | CLK_CLKSEL2_SPI3SEL_HXT | x
  SPI3_MODULE | CLK_CLKSEL2_SPI3SEL_PLL | x
  SPI3_MODULE | CLK_CLKSEL2_SPI3SEL_HIRC | x
  SPI3_MODULE | CLK_CLKSEL2_SPI3SEL_HCLK | x

Definition at line 380 of file clk.c.

## ◆ CLK_SetPCLK0()

void CLK_SetPCLK0 | ( | uint32_t | u32ClkDiv | ) |

This function set APB PCLK0 clock divider.

Parameters

  [in] | u32ClkDiv | is PCLK0 clock divider. Including : CLK_APB0DIV_HCLK CLK_APB0DIV_1_2HCLK CLK_APB0DIV_1_4HCLK CLK_APB0DIV_1_8HCLK CLK_APB0DIV_1_16HCLK

Returns
  None

Definition at line 273 of file clk.c.

## ◆ CLK_SetPCLK1()

void CLK_SetPCLK1 | ( | uint32_t | u32ClkDiv | ) |

This function set APB PCLK1 clock divider.

Parameters

  [in] | u32ClkDiv | is PCLK1 clock divider. Including : CLK_APB1DIV_HCLK CLK_APB1DIV_1_2HCLK CLK_APB1DIV_1_4HCLK CLK_APB1DIV_1_8HCLK CLK_APB1DIV_1_16HCLK

Returns
  None

Definition at line 288 of file clk.c.

## ◆ CLK_SetSysTickClockSrc()

void CLK_SetSysTickClockSrc | ( | uint32_t | u32ClkSrc | ) |

## ◆ CLK_SysTickDelay()

void CLK_SysTickDelay | ( | uint32_t | us | ) |

This function execute delay function.

Parameters

  [in] | us | Delay time. The Max value is 2^24 / CPU Clock(MHz). Ex: 50MHz => 335544us, 48MHz => 349525us, 28MHz => 699050us ...

Returns
  None

Use the SysTick to generate the delay time and the UNIT is in us. The SysTick clock source is from HCLK, i.e the same as system core clock.

Definition at line 595 of file clk.c.

## ◆ CLK_WaitClockReady()

uint32_t CLK_WaitClockReady | ( | uint32_t | u32ClkMask | ) |

This function check selected clock source status.

Parameters

  [in] | u32ClkMask | is selected clock source. Including CLK_STATUS_CLKSFAIL_Msk CLK_STATUS_MIRCSTB_Msk CLK_STATUS_HIRC1STB_Msk CLK_STATUS_HIRC0STB_Msk CLK_STATUS_LIRCSTB_Msk CLK_STATUS_PLLSTB_Msk CLK_STATUS_LXTSTB_Msk CLK_STATUS_HXTSTB_Msk

Returns
  0 clock is not stable 1 clock is stable

To wait for clock ready by specified CLKSTATUS bit or timeout (~5ms)

Definition at line 656 of file clk.c.