| Nano103 BSP V3.01.002 The Board Support Package for Nano103 Series

Data Fields
ADC_T Struct Reference

`#include <Nano103.h>`

## Data Fields
__I uint32_t | DAT [18]
__IO uint32_t | CTL
__IO uint32_t | CHEN
__IO uint32_t | CMP0
__IO uint32_t | CMP1
__IO uint32_t | STATUS
__I uint32_t | PDMA
__IO uint32_t | PWD
__IO uint32_t | CALCTL
__IO uint32_t | CALWORD
__IO uint32_t | EXTSMPT0
__IO uint32_t | EXTSMPT1

## Detailed Description

    @addtogroup ADC Analog to Digital Converter(ADC)
    Memory Mapped Structure for ADC Controller

Definition at line 23603 of file Nano103.h.

## Field Documentation

## ◆ CALCTL

ADC_T::CALCTL

[0x0068] A/D Calibration Control Register

CALCTL

Offset: 0x68 A/D Calibration Control Register

Bits | Field | Descriptions
[0] | CALEN | Calibration Function Enable Bit Enable this bit to turn on the calibration function block. 0 = Bypass calibration functional block. 1 = Enabled calibration functional block.
[1] | CALSTART | Calibration Functional Block Start 0 = Stops calibration functional block. 1 = Starts calibration functional block. Note: This bit is set by software and cleared by hardware; don't write 1 to this bit while CALEN (ADC_CALCTL[0]) = 0.
[2] | CALDONE | Calibrate Functional Block Done 0 = Not yet. 1 = Selected calibration functional block complete. Note: This bit is set by hardware and auto cleared by hardware, This bit can also be cleared by software writing 1.
[3] | CALSEL | Calibration Functional Block Selection 0 = Load calibration functional block. 1 = Calibration functional block.

Definition at line 24398 of file Nano103.h.

## ◆ CALWORD

ADC_T::CALWORD

[0x006c] A/D Calibration Load word Register

CALWORD

Offset: 0x6C A/D Calibration Load word Register

Bits | Field | Descriptions
[6:0] | CALWORD | Calibration Word Bits Write to this register with the previous calibration word before load calibration action, read this register after calibration done. Note: The calibration block contains two parts CALIBRATION and LOAD CALIBRATION; if the calibration block configure as CALIBRATION; then this register represent the result of calibration when calibration is completed; if configure as LOAD CALIBRATION ; configure this register before loading calibration action, after loading calibration complete, the loaded calibration word will apply to the ADC; while in loading calibration function the loaded value will not be equal to the original CALWORD until calibration is done.

Definition at line 24399 of file Nano103.h.

## ◆ CHEN

ADC_T::CHEN

[0x004c] A/D Channel Enable Register

CHEN

Offset: 0x4C A/D Channel Enable Register

Bits | Field | Descriptions
[0] | CHEN0 | Analog Input Channel 0 Enable Bit (Convert Input Voltage From PA.0 ) 0 = Channel 0 Disabled. 1 = Channel 0 Enabled. Note: If software enables more than one channel, the channel with the smallest number will be selected and the other enabled channels will be ignored.
[1] | CHEN1 | Analog Input Channel 1 Enable Bit (Convert Input Voltage From PA.1 ) 0 = Channel 1 Disabled. 1 = Channel 1 Enabled.
[2] | CHEN2 | Analog Input Channel 2 Enable Bit (Convert Input Voltage From PA.2 ) 0 = Channel 2 Disabled. 1 = Channel 2 Enabled.
[3] | CHEN3 | Analog Input Channel 3 Enable Bit (Convert Input Voltage From PA.3 ) 0 = Channel 3 Disabled. 1 = Channel 3 Enabled.
[4] | CHEN4 | Analog Input Channel 4 Enable Bit (Convert Input Voltage From PA.4 ) 0 = Channel 4 Disabled. 1 = Channel 4 Enabled.
[5] | CHEN5 | Analog Input Channel 5 Enable Bit (Convert Input Voltage From PA.5 ) 0 = Channel 5 Disabled. 1 = Channel 5 Enabled.
[6] | CHEN6 | Analog Input Channel 6 Enable Bit (Convert Input Voltage From PA.6 ) 0 = Channel 6 Disabled. 1 = Channel 6 Enabled.
[7] | CHEN7 | Analog Input Channel 7 Enable Bit (Convert Input Voltage From PA.7 ) 0 = Channel 7 Disabled. 1 = Channel 7 Enabled.
[12] | CHEN12 | Analog Input Channel 12 Enable Bit (Convert VBG) 0 = Channel 12 Disabled. 1 = Channel 12 Enabled.
[13] | CHEN13 | Analog Input Channel 13 Enable Bit (Convert VBAT) 0 = Channel 13 Disabled. 1 = Channel 13 Enabled.
[14] | CHEN14 | Analog Input Channel 14 Enable Bit (Convert VTEMP) 0 = Channel 14 Disabled. 1 = Channel 14 Enabled.
[15] | CHEN15 | Analog Input Channel 15 Enable Bit (Convert Int_VREF) 0 = Channel 15 Disabled. 1 = Channel 15 Enabled.
[16] | CHEN16 | Analog Input Channel 16 Enable Bit (Convert AVDD) 0 = Channel 16 Disabled. 1 = Channel 16 Enabled.
[17] | CHEN17 | Analog Input Channel 17 Enable Bit (Convert AVSS) 0 = Channel 17 Disabled. 1 = Channel 17 Enabled.

Definition at line 24389 of file Nano103.h.

## ◆ CMP0

ADC_T::CMP0

[0x0050] A/D Compare Register 0

CMP0

Offset: 0x50 A/D Compare Register 0

Bits | Field | Descriptions
[0] | ADCMPEN | A/D Compare Enable Bit Set 1 to this bit to enable comparing CMPDAT (ADC_CMPx[27:16]) with specified channel conversion results when converted data is loaded into the ADC_DATx register. 0 = Compare function Disabled. 1 = Compare function Enabled. Note: When this bit is set to 1 and CMPMCNT (ADC_CMPx[11:8]) is 0, the ADCMPFx (ADC_STATUS[2:1]) will be set once the match is hit.
[1] | ADCMPIE | A/D Compare Interrupt Enable Bit If the compare function is enabled and the compare condition matches the setting of CMPCOND (ADC_CMPx[2]) and CMPMCNT (ADC_CMPx[11:8]), ADCMPFx (ADC_STATUS[2:1]) bit will be asserted, in the meanwhile, if ADCMPIE(ADC_CMPx[1]) is set to 1, a compare interrupt request will generate. 0 = Compare function interrupt Disabled. 1 = Compare function interrupt Enabled.
[2] | CMPCOND | Compare Condition 0 = Set the compare condition as that when a A/D conversion result is less than the CMPDAT (ADC_CMPx[27:16]), the internal match counter will increase one. 1 = Set the compare condition as that when a A/D conversion result is more than or equal to the CMPDAT (ADC_CMPx[27:16]), the internal match counter will increase one. Note: When the internal counter reaches the value to (CMPMATCNT +1), the ADCMPFx (ADC_STATUS[2:1]) bit will be set.
[7:3] | CMPCH | Compare Channel Selection Set this field to select which channel's result to be compared. Note: Valid setting of this field is channel 0~17, but channel 8~12 are reserved.
[11:8] | CMPMCNT | Compare Match Count When the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND (ADC_CMPx[2]), the internal match counter will increase 1. Note: When the internal counter reaches the value to (CMPMCNT+1), the ADCMPFx (ADC_STATUS[2:1]) bit will be set.
[27:16] | CMPDAT | Comparison Data The 12 bits data is used to compare with conversion result of specified channel Software can use it to monitor the external analog input pin voltage variation in scan mode without imposing a load on software.

Definition at line 24390 of file Nano103.h.

## ◆ CMP1

ADC_T::CMP1

[0x0054] A/D Compare Register 1

CMP1

Offset: 0x54 A/D Compare Register 1

Bits | Field | Descriptions
[0] | ADCMPEN | A/D Compare Enable Bit Set 1 to this bit to enable comparing CMPDAT (ADC_CMPx[27:16]) with specified channel conversion results when converted data is loaded into the ADC_DATx register. 0 = Compare function Disabled. 1 = Compare function Enabled. Note: When this bit is set to 1 and CMPMCNT (ADC_CMPx[11:8]) is 0, the ADCMPFx (ADC_STATUS[2:1]) will be set once the match is hit.
[1] | ADCMPIE | A/D Compare Interrupt Enable Bit If the compare function is enabled and the compare condition matches the setting of CMPCOND (ADC_CMPx[2]) and CMPMCNT (ADC_CMPx[11:8]), ADCMPFx (ADC_STATUS[2:1]) bit will be asserted, in the meanwhile, if ADCMPIE(ADC_CMPx[1]) is set to 1, a compare interrupt request will generate. 0 = Compare function interrupt Disabled. 1 = Compare function interrupt Enabled.
[2] | CMPCOND | Compare Condition 0 = Set the compare condition as that when a A/D conversion result is less than the CMPDAT (ADC_CMPx[27:16]), the internal match counter will increase one. 1 = Set the compare condition as that when a A/D conversion result is more than or equal to the CMPDAT (ADC_CMPx[27:16]), the internal match counter will increase one. Note: When the internal counter reaches the value to (CMPMATCNT +1), the ADCMPFx (ADC_STATUS[2:1]) bit will be set.
[7:3] | CMPCH | Compare Channel Selection Set this field to select which channel's result to be compared. Note: Valid setting of this field is channel 0~17, but channel 8~12 are reserved.
[11:8] | CMPMCNT | Compare Match Count When the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND (ADC_CMPx[2]), the internal match counter will increase 1. Note: When the internal counter reaches the value to (CMPMCNT+1), the ADCMPFx (ADC_STATUS[2:1]) bit will be set.
[27:16] | CMPDAT | Comparison Data The 12 bits data is used to compare with conversion result of specified channel Software can use it to monitor the external analog input pin voltage variation in scan mode without imposing a load on software.

Definition at line 24391 of file Nano103.h.

## ◆ CTL

ADC_T::CTL

[0x0048] A/D Control Register

CTL

Offset: 0x48 A/D Control Register

Bits | Field | Descriptions
[0] | ADCEN | A/D Converter Enable Bit 0 = A/D Converter Disabled. 1 = A/D Converter Enabled. Note: Before starting A/D conversion function, this bit should be set to 1 Clear it to 0 to disable A/D converter analog circuit to save power consumption.
[1] | ADCIEN | A/D Interrupt Enable Bit A/D conversion end interrupt request is generated if ADCIEN (ADC_CTL[1]) bit is set to 1. 0 = A/D interrupt function Disabled. 1 = A/D interrupt function Enabled.
[3:2] | ADMD | A/D Converter Operation Mode 00 = Single conversion. 01 = Reserved. 10 = Single-cycle scan. 11 = Continuous scan.
[5:4] | HWTRGSEL | Hardware Trigger Source Select Bit In hardware trigger mode, ADC starts to convert by the external trigger from STADC pin or PWM trigger. 00= A/D conversion is started by external STADC pin. 01= Reserved. 10= Reserved. 11= A/D conversion is started by PWM0 trigger. Note: Software should disable HWTRGEN (ADC_CTL[8]) and clear SWTRG (ADC_CTL[11]) before change HWTRGSEL (ADC_CTL[5:4]).
[7:6] | HWTRGCOND | Hardware External Trigger Condition These two bits decide external pin STADC trigger event is level or edge The signal must be kept at stable state at least 8 PCLKs for level trigger and 4 PCLKs at high and low state. 00 = Low level. 01 = High level. 10 = Falling edge. 11 = Rising edge.
[8] | HWTRGEN | Hardware External Trigger Enable Bit Enable or disable triggering of A/D conversion by external STADC pin If external trigger is enabled, ADC starts to convert by the selected hardware trigger source. 0= External trigger Disabled. 1= External trigger Enabled.
[9] | PTEN | PDMA Transfer Enable Bit When A/D conversion is completed, the converted data is loaded into ADC_DATx, software can enable this bit to generate a PDMA data transfer request. 0 = PDMA data transfer Disabled. 1 = PDMA data transfer in ADC_DATx Enabled. Note: When PDMA transfer enable, software must set ADCIEN (ADC_CTL[1]) = 0 to disable interrupt PDMA can access ADC_DATx registers by block or single transfer mode.
[10] | DIFF | Differential Mode Selection 0 = ADC is operated in single-ended mode. 1 = ADC is operated in differential mode. Note: Calibration should calibrated each time when switching between single-ended and differential mode.
[11] | SWTRG | Software Trigger A/D Conversion Start 0 = Conversion stopped and A/D converter enter idle state. 1 = Conversion starts. ADC can be start to convert from three sources: software write, external pin STADC and PWM trigger SWTRG (ADC_CTL[11]) is cleared to 0 by hardware automatically at the end of single mode and single-cycle scan mode on specified channels In continuous scan mode, A/D conversion is continuously performed sequentially unless software writes 0 to this bit or chip reset. Note: After ADC conversion is done, SW needs to wait at least one ADC clock before to set this bit high again.
[13:12] | TMSEL | Select A/D Enable Time-out Source Selects one of four timer events source to trigger ADC starts to convert. 00 = TMR0. 01 = TMR1. 10 = TMR2. 11 = TMR3.
[15] | TMTRGMOD | Timer Event Trigger ADC Conversion Mode 0 = Timer event trigger ADC conversion disabled. 1 = ADC can be start to conversion by timer out event. Note1: setting TMSEL (ADC_CTL[13:12]) to select timer event from timer0~3. Note2: If timer event is used as ADC trigger source, ADCEN (ADC_CTL[0]) needs to be disabled.
[17:16] | REFSEL | Reference Voltage Source Selection 00 = Select as reference voltage. 01 = Select as reference voltage. 10 = Select as reference voltage. 11 = Reserved.
[19:18] | RESSEL | Resolution Selection 00 = 6-bit. ADC result will put at RESULT (ADC_DATx[5:0]). 01 = 8-bit. ADC result will put at RESULT (ADC_DATx[7:0]). 10 = 10-bit. ADC result will put at RESULT (ADC_DATx[9:0]). 11 = 12-bit. ADC result will put at RESULT (ADC_DATx[11:0]).
[31:24] | TMPDMACNT | Timer Event PDMA Count When each timer event occur PDMA will transfer TMPDMACNT +1 ADC result in the amount of this register setting. Note: The total amount of PDMA transferring data should be set in PDMA byte count register When PDMA finish is set, ADC will not be enabled and will start transfer even though the timer event occurred.

Definition at line 24388 of file Nano103.h.

## ◆ DAT

ADC_T::DAT

[0x0000] A/D Data Register 0 ~ 17

DAT

Offset: 0x00 A/D Data Register

Bits | Field | Descriptions
[11:0] | RESULT | A/D Conversion Result This field contains conversion result of ADC.
[16] | VALID | Valid Flag This bit is set to 1 when ADC conversion is completed and cleared by hardware after the ADC_DATx register is read. 0 = Data in RESULT (ADC_DAT[11:0]) bits is not valid. 1 = Data in RESULT (ADC_DAT[11:0]) bits is valid.
[17] | OV | over Run Flag If converted data in RESULT (ADC_DAT[11:0]) has not been read before the new conversion result is loaded to this register, OV is set to 1 It is cleared by hardware after the ADC_DATx register is read. 0 = Data in RESULT (ADC_DAT[11:0]) is recent conversion result. 1 = Data in RESULT (ADC_DAT[11:0]) overwrote.

Definition at line 24387 of file Nano103.h.

## ◆ EXTSMPT0

ADC_T::EXTSMPT0

[0x0070] A/D Sampling Time Counter Register 0

EXTSMPT0

Offset: 0x70 A/D Sampling Time Counter Register 0

Bits | Field | Descriptions
[3:0] | EXTSMPT_CH0 | Additional ADC Sample Clock for Channel 0 If the ADC input is unstable, user can set this register to increase the sampling time to get a stable ADC input signal The default sampling time is 1 ADC clocks The additional clock number will be inserted to lengthen the sampling clock. 0 = Number of additional clock cycles is 0. 1 = Number of additional clock cycles is 1. 2 = Number of additional clock cycles is 2. 3 = Number of additional clock cycles is 4. 4 = Number of additional clock cycles is 8. 5 = Number of additional clock cycles is 16. 6 = Number of additional clock cycles is 32. 7 = Number of additional clock cycles is 64. 8 = Number of additional clock cycles is 128. 9 = Number of additional clock cycles is 256. 10 = Number of additional clock cycles is 512. 11 = Number of additional clock cycles is 1024. 12 = Number of additional clock cycles is 1024. 13 = Number of additional clock cycles is 1024. 14 = Number of additional clock cycles is 1024. 15 = Number of additional clock cycles is 1024.
[7:4] | EXTSMPT_CH1 | Additional ADC Sample Clock for Channel 1 The same as channel 0 description.
[11:8] | EXTSMPT_CH2 | Additional ADC Sample Clock for Channel 2 The same as channel 0 description.
[15:12] | EXTSMPT_CH3 | Additional ADC Sample Clock for Channel 3 The same as channel 0 description.
[19:16] | EXTSMPT_CH4 | Additional ADC Sample Clock for Channel 4 The same as channel 0 description.
[23:20] | EXTSMPT_CH5 | Additional ADC Sample Clock for Channel 5 The same as channel 0 description.
[27:24] | EXTSMPT_CH6 | Additional ADC Sample Clock for Channel 6 The same as channel 0 description.
[31:28] | EXTSMPT_CH7 | Additional ADC Sample Clock for Channel 7 The same as channel 0 description.

Definition at line 24400 of file Nano103.h.

## ◆ EXTSMPT1

ADC_T::EXTSMPT1

[0x0074] A/D Sampling Time Counter Register 1

EXTSMPT1

Offset: 0x74 A/D Sampling Time Counter Register 1

Bits | Field | Descriptions
[19:16] | EXTSMPT_INTCH | Additional ADC Sample Clock for Internal Channel (VTEMP, AVDD, AVSS, Int_VREF, VBAT, VBG) The same as channel 0 description.

Definition at line 24401 of file Nano103.h.

## ◆ PDMA

ADC_T::PDMA

[0x0060] A/D PDMA Current Transfer Data Register

PDMA

Offset: 0x60 A/D PDMA Current Transfer Data Register

Bits | Field | Descriptions
[11:0] | AD_PDMA | ADC PDMA Current Transfer Data (Read Only) During PDMA transfer, reading these bits can monitor the current PDMA transfer data.

Definition at line 24396 of file Nano103.h.

## ◆ PWD

ADC_T::PWD

[0x0064] A/D Power Management Register

PWD

Offset: 0x64 A/D Power Management Register

Bits | Field | Descriptions
[0] | PWUPRDY | ADC Power-up Sequence Completed and Ready for Conversion 0 = ADC is not ready for conversion, it may be in power saving state or in the progress of power up. 1 = ADC is ready for conversion.
[1] | PWDCALEN | Power Up Calibration Function Enable Bit 0 = Power up without calibration. 1 = Power up with calibration. Note: This bit works together with CALSEL (ADC_CALCTL[3]), see the following {PWDCALEN,CALFBSEL} Description: PWDCALEN is 0 and CALFBSEL is 0: No need to calibrate. PWDCALEN is 0 and CALFBSEL is 1: No need to calibrate. PWDCALEN is 1 and CALFBSEL is 0: Load calibration word when power up. PWDCALEN is 1 and CALFBSEL is 1: Calibrate when power up.
[3:2] | PWDMOD | ADC Power Saving Mode Set this bit fields to select ADC power saving mode. 00 = Reserved. 01 = ADC Power-down mode. 10 = ADC Standby mode. 11 = Reserved. Note1: Different power saving mode has different power down/up sequence To avoid ADC powering up with wrong sequence, user must keep PWMOD (ADC_PWD[3:2]) consistent each time in power down and power up. Note2: While the ADC is powered up from power saving mode (set to 00b/01b/11b) without calibration, the PWDCALEN(ADC_PWD[1]) is set to 0, and the calibration value will be reset.

Definition at line 24397 of file Nano103.h.

## ◆ STATUS

ADC_T::STATUS

[0x0058] A/D Status Register

STATUS

Offset: 0x58 A/D Status Register

Bits | Field | Descriptions
[0] | ADIF | A/D Conversion End Flag A status flag that indicates the end of A/D conversion, ADIF (ADC_STATUS[0]) is set to 1 at these two conditions: When A/D conversion ends in single mode When A/D conversion ends on all specified channels in scan mode. Note: This bit can be cleared to 0 by software writing 1.
[1] | ADCMPF0 | A/D Compare Flag 0 When the selected channel A/D conversion result meets the setting condition in ADC_CMP0, this bit is set to 1. 0 = Conversion result in ADC_DATx does not meet the CMPDAT (ADC_CMP0[27:16]) setting. 1 = Conversion result in ADC_DATx meets the CMPDAT (ADC_CMP0[27:16]) setting. This flag can be cleared by writing 1 to it. Note: This flag can be cleared by software writing 1 to it, when this flag is set, the matching counter will be reset to 0,and continue to count when user writes 1 to clear ADCMPF0 (ADC_STATUS[1]).
[2] | ADCMPF1 | A/D Compare Flag 1 When the selected channel A/D conversion result meets the setting condition in ADC_CMP1, this bit is set to 1. 0 = Conversion result in ADC_DATx does not meet the CMPDAT (ADC_CMP1[27:16]) setting. 1 = Conversion result in ADC_DATx meets the CMPDAT (ADC_CMP1[27:16]) setting. Note: This flag can be cleared by software writing 1 to it, when this flag is set, the matching counter will be reset to 0,and continue to count when user writes 1 to clear ADCMPF1 (ADC_STATUS[2]).
[3] | BUSY | BUSY/IDLE (Read Only) 0 = A/D converter is in idle state. 1 = A/D converter is busy at conversion. Note: This bit is mirror of SWTRG (ADC_CTL [11]) bit.
[8:4] | CHANNEL | Current Conversion Channel (Read Only) This filed reflects the current conversion channel when BUSY (ADC_STATUS[3]) = 1 When BUSY (ADC_STATUS[3]) = 0, it shows the number of the next converted channel.
[16] | INITRDY | ADC Initial Ready by Power-up Sequence Completed 0 = ADC not powered up after system reset. 1 = ADC has been powered up since the last system reset. Note: This bit will be set after system reset occurred and automatically cleared by power-up event.

Definition at line 24392 of file Nano103.h.

The documentation for this struct was generated from the following file:

- C:/Users/yachen/workzone/bsp/nano103bsp/Library/Device/Nuvoton/Nano103/Include/Nano103.h