| NUC472_NUC442_BSP V3.03.003 The Board Support Package for NUC472/NUC442

ebi.c
Go to the documentation of this file.
1/****************************************************************************/
12#include "NUC472_442.h"
13#include "ebi.h"
14
54 void EBI_Open(uint32_t u32Bank, uint32_t u32DataWidth, uint32_t u32TimingClass, uint32_t u32BusMode, uint32_t u32CSActiveLevel)
55{
56 /* Enable EBI channel */
57 EBI->TCTL[u32Bank] |= EBI_TCTL_CSEN_Msk;
58
59 /* Configure data bus to 8 or 16bit */
60 if(u32DataWidth == EBI_BUSWIDTH_8BIT)
61 EBI->TCTL[u32Bank] &= ~EBI_TCTL_DW16_Msk;
62 else
63 EBI->TCTL[u32Bank] |= EBI_TCTL_DW16_Msk;
64
65 /* Enable separate mode */
66 if(u32BusMode)
67 EBI->TCTL[u32Bank] |= EBI_TCTL_SEPEN_Msk;
68 else
69 EBI->TCTL[u32Bank] &= ~EBI_TCTL_SEPEN_Msk;
70
71 /* Setup active level of chip select */
72 switch(u32Bank)
73 {
74 case EBI_BANK0:
75 if(u32CSActiveLevel)
76 EBI->CTL |= (0x1ul << EBI_CTL_CSPOLINV_Pos);
77 else
78 EBI->CTL &= ~(0x1ul << EBI_CTL_CSPOLINV_Pos);
79 break;
80
81 case EBI_BANK1:
82 if(u32CSActiveLevel)
83 EBI->CTL |= (0x2ul << EBI_CTL_CSPOLINV_Pos);
84 else
85 EBI->CTL &= ~(0x2ul << EBI_CTL_CSPOLINV_Pos);
86 break;
87
88 case EBI_BANK2:
89 if(u32CSActiveLevel)
90 EBI->CTL |= (0x4ul << EBI_CTL_CSPOLINV_Pos);
91 else
92 EBI->CTL &= ~(0x4ul << EBI_CTL_CSPOLINV_Pos);
93 break;
94
95 case EBI_BANK3:
96 if(u32CSActiveLevel)
97 EBI->CTL |= (0x8ul << EBI_CTL_CSPOLINV_Pos);
98 else
99 EBI->CTL &= ~(0x8ul << EBI_CTL_CSPOLINV_Pos);
100 break;
101 }
102
103 /* Clear R2R/R2W/R2X/TAHD/TACC/TALE entries for safety */
104 EBI->TCTL[u32Bank] &= ~0x0F0FF7FF;
105
106 /* Setup EBI timing */
107 switch(u32TimingClass)
108 {
109 case EBI_TIMING_FASTEST:
110 EBI->CTL = (EBI->CTL & ~EBI_CTL_MCLKDIV_Msk) | ( EBI_MCLKDIV_1 << 8);
111 break;
112
113 case EBI_TIMING_VERYFAST:
114 EBI->CTL = (EBI->CTL & ~EBI_CTL_MCLKDIV_Msk) | ( EBI_MCLKDIV_1 << 8);
115 EBI->TCTL[u32Bank] |= 0x0303331B;
116 break;
117
118 case EBI_TIMING_FAST:
119 EBI->CTL = (EBI->CTL & ~EBI_CTL_MCLKDIV_Msk) | ( EBI_MCLKDIV_2 << 8);
120 break;
121
122 case EBI_TIMING_NORMAL:
123 EBI->CTL = (EBI->CTL & ~EBI_CTL_MCLKDIV_Msk) | ( EBI_MCLKDIV_2 << 8);
124 EBI->TCTL[u32Bank] |= 0x0303331B;
125 break;
126
127 case EBI_TIMING_SLOW:
128 EBI->CTL = (EBI->CTL & ~EBI_CTL_MCLKDIV_Msk) | ( EBI_MCLKDIV_2 << 8);
129 EBI->TCTL[u32Bank] |= 0x0707773F;
130 break;
131
132 case EBI_TIMING_VERYSLOW:
133 EBI->CTL = (EBI->CTL & ~EBI_CTL_MCLKDIV_Msk) | ( EBI_MCLKDIV_4 << 8);
134 EBI->TCTL[u32Bank] |= 0x0707773F;
135 break;
136
137 case EBI_TIMING_SLOWEST:
138 EBI->CTL = (EBI->CTL & ~EBI_CTL_MCLKDIV_Msk) | ( EBI_MCLKDIV_8 << 8);
139 EBI->TCTL[u32Bank] |= 0x0707773F;
140 break;
141 }
142}
143
153 void EBI_Close(uint32_t u32Bank)
154{
155 EBI->TCTL[u32Bank] &= ~EBI_TCTL_CSEN_Msk;
156}
157
175 void EBI_SetBusTiming(uint32_t u32Bank, uint32_t u32TimingConfig, uint32_t u32MclkDiv)
176{
177 EBI->CTL = (EBI->CTL & ~EBI_CTL_MCLKDIV_Msk) | (u32MclkDiv << EBI_CTL_MCLKDIV_Pos);
178 EBI->TCTL[u32Bank] |= (u32TimingConfig & 0x0F0FF7FF);
179}
180
191 void EBI_EnableCrypto(uint32_t u32Bank, uint32_t *u32Key)
192{
193 switch(u32Bank)
194 {
195 case EBI_BANK0:
196 EBI->CTL |= (0x1ul << EBI_CTL_CRYPTOEN_Pos);
197 break;
198 case EBI_BANK1:
199 EBI->CTL |= (0x2ul << EBI_CTL_CRYPTOEN_Pos);
200 break;
201 case EBI_BANK2:
202 EBI->CTL |= (0x4ul << EBI_CTL_CRYPTOEN_Pos);
203 break;
204 case EBI_BANK3:
205 EBI->CTL |= (0x8ul << EBI_CTL_CRYPTOEN_Pos);
206 break;
207 }
208
209 /* Setup 128-bits key */
210 EBI->KEY0 = u32Key[0];
211 EBI->KEY1 = u32Key[1];
212 EBI->KEY2 = u32Key[2];
213 EBI->KEY3 = u32Key[3];
214}
215
225 void EBI_DisbleCrypto(uint32_t u32Bank)
226{
227 switch(u32Bank)
228 {
229 case EBI_BANK0:
230 EBI->CTL &= ~(0x1ul << EBI_CTL_CRYPTOEN_Pos);
231 break;
232 case EBI_BANK1:
233 EBI->CTL &= ~(0x2ul << EBI_CTL_CRYPTOEN_Pos);
234 break;
235 case EBI_BANK2:
236 EBI->CTL &= ~(0x4ul << EBI_CTL_CRYPTOEN_Pos);
237 break;
238 case EBI_BANK3:
239 EBI->CTL &= ~(0x8ul << EBI_CTL_CRYPTOEN_Pos);
240 break;
241 }
242}
243 /* end of group NUC472_442_EBI_EXPORTED_FUNCTIONS */
245 /* end of group NUC472_442_EBI_Driver */
247 /* end of group NUC472_442_Device_Driver */
249
250/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
NUC472_442.h
NUC472/NUC442 peripheral access layer header file. This file contains all the peripheral register's d...
EBI_CTL_MCLKDIV_Pos
#define EBI_CTL_MCLKDIV_Pos
Definition: NUC472_442.h:11693
EBI_CTL_CRYPTOEN_Pos
#define EBI_CTL_CRYPTOEN_Pos
Definition: NUC472_442.h:11696
EBI_TCTL_SEPEN_Msk
#define EBI_TCTL_SEPEN_Msk
Definition: NUC472_442.h:11727
EBI_TCTL_DW16_Msk
#define EBI_TCTL_DW16_Msk
Definition: NUC472_442.h:11724
EBI_TCTL_CSEN_Msk
#define EBI_TCTL_CSEN_Msk
Definition: NUC472_442.h:11721
EBI_CTL_CSPOLINV_Pos
#define EBI_CTL_CSPOLINV_Pos
Definition: NUC472_442.h:11699
ebi.h
NUC472/NUC442 EBI driver header file.
EBI_TIMING_VERYFAST
#define EBI_TIMING_VERYFAST
EBI timing is very fast
Definition: ebi.h:105
EBI_MCLKDIV_4
#define EBI_MCLKDIV_4
EBI clock is MCLK div 4.
Definition: ebi.h:99
EBI_BANK0
#define EBI_BANK0
EBI bank 0.
Definition: ebi.h:79
EBI_MCLKDIV_1
#define EBI_MCLKDIV_1
EBI clock is MCLK div 1.
Definition: ebi.h:97
EBI_MCLKDIV_8
#define EBI_MCLKDIV_8
EBI clock is MCLK div 8.
Definition: ebi.h:100
EBI_BANK1
#define EBI_BANK1
EBI bank 1.
Definition: ebi.h:80
EBI_BANK2
#define EBI_BANK2
EBI bank 2.
Definition: ebi.h:81
EBI_MCLKDIV_2
#define EBI_MCLKDIV_2
EBI clock is MCLK div 2.
Definition: ebi.h:98
EBI_TIMING_FASTEST
#define EBI_TIMING_FASTEST
EBI timing is the fastest.
Definition: ebi.h:104
EBI_TIMING_FAST
#define EBI_TIMING_FAST
EBI timing is fast.
Definition: ebi.h:106
EBI_BUSWIDTH_8BIT
#define EBI_BUSWIDTH_8BIT
EBI bus width is 8-bit.
Definition: ebi.h:89
EBI_TIMING_VERYSLOW
#define EBI_TIMING_VERYSLOW
EBI timing is very slow.
Definition: ebi.h:109
EBI_TIMING_NORMAL
#define EBI_TIMING_NORMAL
EBI timing is normal.
Definition: ebi.h:107
EBI_TIMING_SLOW
#define EBI_TIMING_SLOW
EBI timing is slow.
Definition: ebi.h:108
EBI_TIMING_SLOWEST
#define EBI_TIMING_SLOWEST
EBI timing is the slowest.
Definition: ebi.h:110
EBI_BANK3
#define EBI_BANK3
EBI bank 3.
Definition: ebi.h:82
EBI_EnableCrypto
void EBI_EnableCrypto(uint32_t u32Bank, uint32_t *u32Key)
Enable encrypt/decrypt function and set key for EBI bank 0~3.
Definition: ebi.c:191
EBI_Close
void EBI_Close(uint32_t u32Bank)
Disable EBI for bank 0~3.
Definition: ebi.c:153
EBI_Open
void EBI_Open(uint32_t u32Bank, uint32_t u32DataWidth, uint32_t u32TimingClass, uint32_t u32BusMode, uint32_t u32CSActiveLevel)
Initialize EBI for Bank 0~3.
Definition: ebi.c:54
EBI_SetBusTiming
void EBI_SetBusTiming(uint32_t u32Bank, uint32_t u32TimingConfig, uint32_t u32MclkDiv)
Set EBI bus timings.
Definition: ebi.c:175
EBI_DisbleCrypto
void EBI_DisbleCrypto(uint32_t u32Bank)
Disable encrypt/decrypt function for EBI bank 0~3.
Definition: ebi.c:225
EBI
#define EBI
Definition: NUC472_442.h:28822