| NUC472_NUC442_BSP V3.03.003 The Board Support Package for NUC472/NUC442

usbh_ohci.h
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1/*
2 * URB OHCI HCD (Host Controller Driver) for USB.
3 *
4 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
5 * (C) Copyright 2000 David Brownell <david-b@pacbell.net>
6 *
7 * usb-ohci.h
8 */
9
10#ifndef _USB_OHCI_H_
11#define _USB_OHCI_H_
12
14
15/*------------------------------------------------------------------------------------
16 *
17 * USB Host Controller
18 *
19 *------------------------------------------------------------------------------------*/
20#define OHCI_BASE OHCI_BASE_ADDR
21#define HC_REVISION (OHCI_BASE+0x00) // HcRevision - Revision Register
22#define HC_CONTROL (OHCI_BASE+0x04) // CTL - Control Register
23#define HC_CMD_STATUS (OHCI_BASE+0x08) // HcCommandStatus - Command Status Register
24#define HC_INT_STATUS (OHCI_BASE+0x0C) // HcInterruptStatus - Interrupt Status Register
25#define HC_INT_ENABLE (OHCI_BASE+0x10) // HcInterruptEnable - Interrupt Enable Register
26#define HC_INT_DISABLE (OHCI_BASE+0x14) // HcInterruptDisable - Interrupt Disable Register
27#define HC_HCCA (OHCI_BASE+0x18) // HcHCCA - Communication Area Register
28#define HC_PERIOD_CURED (OHCI_BASE+0x1C) // HcPeriodCurrentED - Period Current ED Register
29#define HC_CTRL_HEADED (OHCI_BASE+0x20) // HcControlHeadED - Control Head ED Register
30#define HC_CTRL_CURED (OHCI_BASE+0x24) // HcControlCurrentED - Control Current ED Register
31#define HC_BULK_HEADED (OHCI_BASE+0x28) // HcBulkHeadED - Bulk Head ED Register
32#define HC_BULK_CURED (OHCI_BASE+0x2C) // HcBulkCurrentED - Bulk Current ED Register
33#define HC_DONE_HEAD (OHCI_BASE+0x30) // HcBulkCurrentED - Done Head Register
34#define HC_FM_INTERVAL (OHCI_BASE+0x34) // HcFmInterval - Frame Interval Register
35#define HC_FM_REMAINING (OHCI_BASE+0x38) // HcFrameRemaining - Frame Remaining Register
36#define HC_FM_NUMBER (OHCI_BASE+0x3C) // HcFmNumber - Frame Number Register
37#define HC_PERIOD_START (OHCI_BASE+0x40) // HcPeriodicStart - Periodic Start Register
38#define HC_LS_THRESHOLD (OHCI_BASE+0x44) // HcLSThreshold - Low Speed Threshold Register
39#define HC_RH_DESCRIPTORA (OHCI_BASE+0x48) // HcRhDescriptorA - Root Hub Descriptor A Register
40#define HC_RH_DESCRIPTORB (OHCI_BASE+0x4C) // HcRevision - Root Hub Descriptor B Register
41#define HC_RH_STATUS (OHCI_BASE+0x50) // HcRhStatus - Root Hub Status Register
42#define HC_RH_PORT_STATUS1 (OHCI_BASE+0x54) // HcRevision - Root Hub Port Status [1]
43#define HC_RH_PORT_STATUS2 (OHCI_BASE+0x58) // HcRevision - Root Hub Port Status [2]
44#define HC_RH_OP_MODE (OHCI_BASE+0x204)
45
46
47/* ED States */
48
49#define ED_NEW 0x00
50#define ED_UNLINK 0x01
51#define ED_OPER 0x02
52#define ED_DEL 0x04
53#define ED_URB_DEL 0x08
54
55/* usb_ohci_ed */
56 typedef struct ohci_ed_t
57{
58 uint32_t hwINFO;
59 uint32_t hwTailP;
60 uint32_t hwHeadP;
61 uint32_t hwNextED;
62
63 struct ohci_ed_t *ed_prev;
64 uint8_t int_period;
65 uint8_t int_branch;
66 uint8_t int_load;
67 uint8_t int_interval;
68 uint8_t state;
69 uint8_t type;
70 uint16_t last_iso;
71 struct ohci_ed_t *ed_rm_list;
72} ED_T, *EDP_T;
73
74
75
76/* TD info field */
77#define TD_CC 0xF0000000
78#define TD_CC_GET(td_p) ((td_p >>28) & 0x0F)
79#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0FFFFFFF) | (((cc) & 0x0F) << 28)
80#define TD_EC 0x0C000000
81//#define TD_T 0x03000000
82#define TD_T_DATA0 0x02000000
83#define TD_T_DATA1 0x03000000
84#define TD_T_TOGGLE 0x00000000
85#define TD_R 0x00040000
86#define TD_DI 0x00E00000
87#define TD_DI_SET(X) (((X) & 0x07)<< 21)
88#define TD_DP 0x00180000
89#define TD_DP_SETUP 0x00000000
90#define TD_DP_IN 0x00100000
91#define TD_DP_OUT 0x00080000
92
93#define TD_ISO 0x00010000
94#define TD_DEL 0x00020000
95
96/* CC Codes */
97#define TD_CC_NOERROR 0x00
98#define TD_CC_CRC 0x01
99#define TD_CC_BITSTUFFING 0x02
100#define TD_CC_DATATOGGLEM 0x03
101#define TD_CC_STALL 0x04
102#define TD_DEVNOTRESP 0x05
103#define TD_PIDCHECKFAIL 0x06
104#define TD_UNEXPECTEDPID 0x07
105#define TD_DATAOVERRUN 0x08
106#define TD_DATAUNDERRUN 0x09
107#define TD_BUFFEROVERRUN 0x0C
108#define TD_BUFFERUNDERRUN 0x0D
109#define TD_NOTACCESSED 0x0E
110
111
112#define MAXPSW 8
113
114 typedef struct ohci_td_t
115{
116 uint32_t hwINFO;
117 uint32_t hwCBP; /* Current Buffer Pointer */
118 uint32_t hwNextTD; /* Next TD Pointer */
119 uint32_t hwBE; /* Memory Buffer End Pointer */
120 uint32_t hwPSW[4];
121 int is_iso_packet;
122 int index;
123 ED_T *ed;
124 struct ohci_td_t *next_dl_td;
125 URB_T *urb;
126 uint32_t dummy[3]; /* let TD_T to be 64 bytes for 32 bytes memory alignment */
127} TD_T;
128
129
130#define OHCI_ED_SKIP (1 << 14)
131
132/*
133 * The HCCA (Host Controller Communications Area) is a 256 byte
134 * structure defined in the OHCI spec. that the host controller is
135 * told the base address of. It must be 256-byte aligned.
136 */
137
138#define NUM_INTS 32 /* part of the OHCI standard */
139
140 typedef struct ohci_hcca
141{
142 uint32_t int_table[NUM_INTS]; /* Interrupt ED table */
143 uint16_t frame_no; /* current frame number */
144 uint16_t pad1; /* set to 0 on each frame_no change */
145 uint32_t done_head; /* info returned for an interrupt */
146 //uint8_t reserved_for_hc[116];
147} OHCI_HCCA_T;
148
149
150/*
151 * Maximum number of root hub ports.
152 */
153#define MAX_ROOT_PORTS 2
154
155/*
156 * This is the structure of the OHCI controller's memory mapped I/O
157 * region. This is Memory Mapped I/O. You must use the readl() and
158 * writel() macros defined in asm/io.h to access these!!
159 */
160 struct ohci_regs
161{
162 /* control and status registers */
163 uint32_t HcRevision;
164 uint32_t CTL;
165 uint32_t HcCommandStatus;
166 uint32_t HcInterruptStatus;
167 uint32_t HcInterruptEnable;
168 uint32_t HcInterruptDisable;
169 /* memory pointers */
170 uint32_t HcHCCA;
171 uint32_t HcPeriodCurrentED;
172 uint32_t HcControlHeadED;
173 uint32_t HcControlCurrentED;
174 uint32_t HcBulkHeadED;
175 uint32_t HcBulkCurrentED;
176 uint32_t HcDoneHead;
177 /* frame counters */
178 uint32_t HcFmInterval;
179 uint32_t HcFrameRemaining;
180 uint32_t HcFmNumber;
181 uint32_t HcPeriodicStart;
182 uint32_t HcLSThreshold;
183 /* Root hub ports */
184 struct ohci_roothub_regs
185 {
186 uint32_t a;
187 uint32_t b;
188 uint32_t status;
189 uint32_t portstatus[MAX_ROOT_PORTS];
190 } roothub;
191};
192 typedef struct ohci_regs OHCI_REGS_T;
193
194
195/* OHCI CONTROL AND STATUS REGISTER MASKS */
196
197/*
198 * CTL (control) register masks
199 */
200#define OHCI_CTRL_CBSR (3 << 0) /* control/bulk service ratio */
201#define OHCI_CTRL_PLE (1 << 2) /* periodic list enable */
202#define OHCI_CTRL_IE (1 << 3) /* isochronous enable */
203#define OHCI_CTRL_CLE (1 << 4) /* control list enable */
204#define OHCI_CTRL_BLE (1 << 5) /* bulk list enable */
205#define OHCI_CTRL_HCFS (3 << 6) /* host controller functional state */
206#define OHCI_CTRL_IR (1 << 8) /* interrupt routing */
207#define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */
208#define OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */
209
210/* pre-shifted values for HCFS */
211#define OHCI_USB_RESET (0 << 6)
212#define OHCI_USB_RESUME (1 << 6)
213#define OHCI_USB_OPER (2 << 6)
214#define OHCI_USB_SUSPEND (3 << 6)
215
216/*
217 * HcCommandStatus (cmdstatus) register masks
218 */
219#define OHCI_HCR (1 << 0) /* host controller reset */
220#define OHCI_CLF (1 << 1) /* control list filled */
221#define OHCI_BLF (1 << 2) /* bulk list filled */
222#define OHCI_OCR (1 << 3) /* ownership change request */
223#define OHCI_SOC (3 << 16) /* scheduling overrun count */
224
225/*
226 * masks used with interrupt registers:
227 * HcInterruptStatus (intrstatus)
228 * HcInterruptEnable (intrenable)
229 * HcInterruptDisable (intrdisable)
230 */
231#define OHCI_INTR_SO (1 << 0) /* scheduling overrun */
232#define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */
233#define OHCI_INTR_SF (1 << 2) /* start frame */
234#define OHCI_INTR_RD (1 << 3) /* resume detect */
235#define OHCI_INTR_UE (1 << 4) /* unrecoverable error */
236#define OHCI_INTR_FNO (1 << 5) /* frame number overflow */
237#define OHCI_INTR_RHSC (1 << 6) /* root hub status change */
238#define OHCI_INTR_OC (1 << 30) /* ownership change */
239#define OHCI_INTR_MIE 0x80000000 /* master interrupt enable */
240
241
242/* Virtual Root HUB */
243 typedef struct virt_root_hub
244{
245 int devnum; /* Address of Root Hub endpoint */
246 void *urb;
247 void *int_addr;
248 int send;
249 int interval;
250} VIRT_ROOT_HUB_T;
251
252
253
254/* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */
255
256/* destination of request */
257#define RH_INTERFACE 0x0100
258#define RH_ENDPOINT 0x0200
259#define RH_OTHER 0x0300
260#define RH_CLASS 0x2000
261#define RH_VENDOR 0x4000
262
263/* Requests: bRequest << 8 | bmRequestType */
264#define RH_GET_STATUS 0x8000
265#define RH_CLEAR_FEATURE 0x0001
266#define RH_SET_FEATURE 0x0003
267#define RH_SET_ADDRESS 0x0005
268#define RH_GET_DESCRIPTOR 0x8006
269#define RH_SET_DESCRIPTOR 0x0007
270#define RH_GET_CONFIGURATION 0x8008
271#define RH_SET_CONFIGURATION 0x0009
272#define RH_GET_STATE 0x8002
273#define RH_GET_INTERFACE 0x800A
274#define RH_SET_INTERFACE 0x000B
275#define RH_SYNC_FRAME 0x800C
276/* Our Vendor Specific Request */
277#define RH_SET_EP 0x0020
278
279
280/* Hub port features */
281#define RH_PORT_CONNECTION 0x00
282#define RH_PORT_ENABLE 0x01
283#define RH_PORT_SUSPEND 0x02
284#define RH_PORT_OVER_CURRENT 0x03
285#define RH_PORT_RESET 0x04
286#define RH_PORT_POWER 0x08
287#define RH_PORT_LOW_SPEED 0x09
288
289#define RH_C_PORT_CONNECTION 0x10
290#define RH_C_PORT_ENABLE 0x11
291#define RH_C_PORT_SUSPEND 0x12
292#define RH_C_PORT_OVER_CURRENT 0x13
293#define RH_C_PORT_RESET 0x14
294
295/* Hub features */
296#define RH_C_HUB_LOCAL_POWER 0x00
297#define RH_C_HUB_OVER_CURRENT 0x01
298
299#define RH_DEVICE_REMOTE_WAKEUP 0x00
300#define RH_ENDPOINT_STALL 0x01
301
302#define RH_ACK 0x01
303#define RH_REQ_ERR -1
304#define RH_NACK 0x00
305
306
307/* OHCI ROOT HUB REGISTER MASKS */
308
309/* roothub.portstatus [i] bits */
310#define RH_PS_CCS 0x00000001 /* current connect status */
311#define RH_PS_PES 0x00000002 /* port enable status*/
312#define RH_PS_PSS 0x00000004 /* port suspend status */
313#define RH_PS_POCI 0x00000008 /* port over current indicator */
314#define RH_PS_PRS 0x00000010 /* port reset status */
315#define RH_PS_PPS 0x00000100 /* port power status */
316#define RH_PS_LSDA 0x00000200 /* low speed device attached */
317#define RH_PS_CSC 0x00010000 /* connect status change */
318#define RH_PS_PESC 0x00020000 /* port enable status change */
319#define RH_PS_PSSC 0x00040000 /* port suspend status change */
320#define RH_PS_OCIC 0x00080000 /* over current indicator change */
321#define RH_PS_PRSC 0x00100000 /* port reset status change */
322
323/* roothub.status bits */
324#define RH_HS_LPS 0x00000001 /* local power status */
325#define RH_HS_OCI 0x00000002 /* over current indicator */
326#define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */
327#define RH_HS_LPSC 0x00010000 /* local power status change */
328#define RH_HS_OCIC 0x00020000 /* over current indicator change */
329#define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */
330
331/* roothub.b masks */
332#define RH_B_DR 0x0000FFFF /* device removable flags */
333#define RH_B_PPCM 0xFFFF0000 /* port power control mask */
334
335/* roothub.a masks */
336#define RH_A_NDP (0xFF) /* number of downstream ports */
337#define RH_A_PSM (1 << 8) /* power switching mode */
338#define RH_A_NPS (1 << 9) /* no power switching */
339#define RH_A_DT (1 << 10) /* device type (mbz) */
340#define RH_A_OCPM (1 << 11) /* over current protection mode */
341#define RH_A_NOCP (1 << 12) /* no over current protection */
342#define RH_A_POTPGT (0xFF000000) /* power on to power good time */
343
344#undef min
345#define min(a,b) (((a)<(b))?(a):(b))
346
347
348/* urb */
349
350#define URB_DEL 1
351
352/*
353 * This is the full ohci controller description
354 *
355 * Note how the "proper" USB information is just
356 * a subset of what the full implementation needs. (Linus)
357 */
358
359 typedef struct ohci
360{
361 OHCI_HCCA_T *hcca; /* hcca */
362 /* Modified by YCHuang, from hcca to *hcca */
363 /* We must guarantee the HCCA is located on 256 */
364 /* bytes boundary. */
365 int disabled; /* e.g. got a UE, we're hung */
366 int resume_count; /* atomic_t, defending against multiple resumes */
367
368 //OHCI_REGS_T *regs; /* OHCI controller's memory */
369
370 int ohci_int_load[32]; /* load of the 32 Interrupt Chains (for load balancing)*/
371 ED_T *ed_rm_list[2]; /* lists of all endpoints to be removed */
372 ED_T *ed_bulktail; /* last endpoint of bulk list */
373 ED_T *ed_controltail; /* last endpoint of control list */
374 ED_T *ed_isotail; /* last endpoint of iso list */
375 int intrstatus;
376 uint32_t hc_control; /* copy of the hc control reg */
377 USB_BUS_T *bus;
378 USB_DEV_T *dev[DEV_MAX_NUM];
379 VIRT_ROOT_HUB_T rh;
380} OHCI_T;
381
382
383#define NUM_TDS 0 /* num of preallocated transfer descriptors */
384#define NUM_EDS 32 /* num of preallocated endpoint descriptors */
385
386 typedef struct ohci_device
387{
388 //ED_T ed[NUM_EDS];
389 EDP_T edp[NUM_EDS];
390 int ed_cnt;
391} OHCI_DEVICE_T;
392
393
394/* #define ohci_to_usb(ohci) ((ohci)->usb) */
395#define usb_to_ohci(usb) ((OHCI_DEVICE_T *)(usb)->hcpriv)
396
398
399#endif /* _USB_OHCI_H_ */
400
DEV_MAX_NUM
#define DEV_MAX_NUM
Definition: usbh_config.h:48
USB_DEV_T
HIDDEN_SYMBOLS struct usb_device USB_DEV_T
urb_t
Definition: usbh_core.h:537