; generated by ARM C/C++ Compiler, 5.03 [Build 24]
; commandline ArmCC [--list --split_sections --debug -c --asm --interleave -o.\obj\clk.o --asm_dir=.\lst\ --list_dir=.\lst\ --depend=.\obj\clk.d --cpu=Cortex-M0 --apcs=interwork -I.\ -I..\..\..\..\Library\CMSIS\Include -I..\..\..\..\Library\Device\Nuvoton\NUC200Series\Include -I..\..\..\..\Library\StdDriver\inc -IC:\Keil\ARM\RV31\INC -IC:\Keil\ARM\CMSIS\Include -IC:\Keil\ARM\Inc\?ST\STM32F10x -D__MICROLIB --omf_browse=.\obj\clk.crf ..\..\..\..\Library\StdDriver\src\clk.c]
                          THUMB

                          AREA ||i.CLK_DisableCKO||, CODE, READONLY, ALIGN=2

                  CLK_DisableCKO PROC
;;;30       */
;;;31     void CLK_DisableCKO(void)
000000  b500              PUSH     {lr}
;;;32     { 
;;;33         /* Disable CKO clock source */
;;;34         CLK_DisableModuleClock(FDIV_MODULE);
000002  4802              LDR      r0,|L1.12|
000004  f7fffffe          BL       CLK_DisableModuleClock
;;;35     }
000008  bd00              POP      {pc}
;;;36     
                          ENDP

00000a  0000              DCW      0x0000
                  |L1.12|
                          DCD      0x66200006

                          AREA ||i.CLK_DisableModuleClock||, CODE, READONLY, ALIGN=2

                  CLK_DisableModuleClock PROC
;;;481      */
;;;482    void CLK_DisableModuleClock(uint32_t u32ModuleIdx)
000000  b51f              PUSH     {r0-r4,lr}
;;;483    {
;;;484        uint32_t u32OffsetTbl[4] = {0x0, 0x4, 0x2C, 0x0};     
000002  4c0a              LDR      r4,|L2.44|
000004  3428              ADDS     r4,r4,#0x28
000006  cc1e              LDM      r4,{r1-r4}
;;;485        
;;;486        *(volatile uint32_t *)((uint32_t)&CLK->AHBCLK+u32OffsetTbl[MODULE_APBCLK(u32ModuleIdx)])  &= ~(1<<MODULE_IP_EN_Pos(u32ModuleIdx));
000008  9403              STR      r4,[sp,#0xc]
00000a  466c              MOV      r4,sp
00000c  c40e              STM      r4!,{r1-r3}
00000e  0f81              LSRS     r1,r0,#30
000010  008a              LSLS     r2,r1,#2
000012  4669              MOV      r1,sp
000014  588a              LDR      r2,[r1,r2]
000016  4906              LDR      r1,|L2.48|
000018  1851              ADDS     r1,r2,r1
00001a  684a              LDR      r2,[r1,#4]
00001c  06c3              LSLS     r3,r0,#27
00001e  0edb              LSRS     r3,r3,#27
000020  2001              MOVS     r0,#1
000022  4098              LSLS     r0,r0,r3
000024  4382              BICS     r2,r2,r0
000026  604a              STR      r2,[r1,#4]
;;;487    }
000028  bd1f              POP      {r0-r4,pc}
;;;488    
                          ENDP

00002a  0000              DCW      0x0000
                  |L2.44|
                          DCD      ||.constdata||
                  |L2.48|
                          DCD      0x50000200

                          AREA ||i.CLK_DisablePLL||, CODE, READONLY, ALIGN=2

                  CLK_DisablePLL PROC
;;;597      */
;;;598    void CLK_DisablePLL(void)
000000  4802              LDR      r0,|L3.12|
;;;599    {
;;;600        CLK->PLLCON |= CLK_PLLCON_PD_Msk;
000002  6a01              LDR      r1,[r0,#0x20]
000004  01c2              LSLS     r2,r0,#7
000006  4311              ORRS     r1,r1,r2
000008  6201              STR      r1,[r0,#0x20]
;;;601    }
00000a  4770              BX       lr
;;;602    
                          ENDP

                  |L3.12|
                          DCD      0x50000200

                          AREA ||i.CLK_DisableXtalRC||, CODE, READONLY, ALIGN=2

                  CLK_DisableXtalRC PROC
;;;399      */
;;;400    void CLK_DisableXtalRC(uint32_t u32ClkMask)
000000  4902              LDR      r1,|L4.12|
;;;401    {
;;;402      CLK->PWRCON &= ~u32ClkMask;
000002  680a              LDR      r2,[r1,#0]
000004  4382              BICS     r2,r2,r0
000006  600a              STR      r2,[r1,#0]
;;;403    }
000008  4770              BX       lr
;;;404    
                          ENDP

00000a  0000              DCW      0x0000
                  |L4.12|
                          DCD      0x50000200

                          AREA ||i.CLK_EnableCKO||, CODE, READONLY, ALIGN=2

                  CLK_EnableCKO PROC
;;;54       */
;;;55     void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En)
000000  b530              PUSH     {r4,r5,lr}
;;;56     {
000002  4604              MOV      r4,r0
;;;57         /* CKO = clock source / 2^(u32ClkDiv + 1) */
;;;58         CLK->FRQDIV = CLK_FRQDIV_DIVIDER_EN_Msk | u32ClkDiv;
000004  2210              MOVS     r2,#0x10
000006  4806              LDR      r0,|L5.32|
000008  4311              ORRS     r1,r1,r2
00000a  6241              STR      r1,[r0,#0x24]
;;;59     
;;;60         /* Enable CKO clock source */
;;;61         CLK_EnableModuleClock(FDIV_MODULE);
00000c  4d05              LDR      r5,|L5.36|
00000e  4628              MOV      r0,r5
000010  f7fffffe          BL       CLK_EnableModuleClock
;;;62         
;;;63         /* Select CKO clock source */    
;;;64         CLK_SetModuleClock(FDIV_MODULE, u32ClkSrc, 0);    
000014  2200              MOVS     r2,#0
000016  4621              MOV      r1,r4
000018  4628              MOV      r0,r5
00001a  f7fffffe          BL       CLK_SetModuleClock
;;;65     }
00001e  bd30              POP      {r4,r5,pc}
;;;66     
                          ENDP

                  |L5.32|
                          DCD      0x50000200
                  |L5.36|
                          DCD      0x66200006

                          AREA ||i.CLK_EnableModuleClock||, CODE, READONLY, ALIGN=2

                  CLK_EnableModuleClock PROC
;;;439      */
;;;440    void CLK_EnableModuleClock(uint32_t u32ModuleIdx)
000000  b51f              PUSH     {r0-r4,lr}
;;;441    {
;;;442        uint32_t u32OffsetTbl[4] = {0x0, 0x4, 0x2C, 0x0}; 
000002  4c0a              LDR      r4,|L6.44|
000004  3418              ADDS     r4,r4,#0x18
000006  cc1e              LDM      r4,{r1-r4}
;;;443        
;;;444        *(volatile uint32_t *)((uint32_t)&CLK->AHBCLK+u32OffsetTbl[MODULE_APBCLK(u32ModuleIdx)])  |= 1<<MODULE_IP_EN_Pos(u32ModuleIdx);
000008  9403              STR      r4,[sp,#0xc]
00000a  466c              MOV      r4,sp
00000c  c40e              STM      r4!,{r1-r3}
00000e  0f81              LSRS     r1,r0,#30
000010  008a              LSLS     r2,r1,#2
000012  4669              MOV      r1,sp
000014  588a              LDR      r2,[r1,r2]
000016  4906              LDR      r1,|L6.48|
000018  1851              ADDS     r1,r2,r1
00001a  684a              LDR      r2,[r1,#4]
00001c  06c3              LSLS     r3,r0,#27
00001e  0edb              LSRS     r3,r3,#27
000020  2001              MOVS     r0,#1
000022  4098              LSLS     r0,r0,r3
000024  4302              ORRS     r2,r2,r0
000026  604a              STR      r2,[r1,#4]
;;;445    }
000028  bd1f              POP      {r0-r4,pc}
;;;446    
                          ENDP

00002a  0000              DCW      0x0000
                  |L6.44|
                          DCD      ||.constdata||
                  |L6.48|
                          DCD      0x50000200

                          AREA ||i.CLK_EnablePLL||, CODE, READONLY, ALIGN=2

                  CLK_EnablePLL PROC
;;;497      */
;;;498    uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq)
000000  b5f0              PUSH     {r4-r7,lr}
;;;499    {
000002  460c              MOV      r4,r1
;;;500        uint32_t u32PllSrcClk, u32NR, u32NF, u32NO, u32CLK_SRC;
;;;501        uint32_t u32Tmp, u32Tmp2, u32Tmp3, u32Min, u32MinNF, u32MinNR;
;;;502    
;;;503        /* Disable PLL first to avoid unstable when setting PLL. */
;;;504        CLK->PLLCON = CLK_PLLCON_PD_Msk;
000004  2201              MOVS     r2,#1
000006  494e              LDR      r1,|L7.320|
000008  b085              SUB      sp,sp,#0x14           ;499
00000a  0412              LSLS     r2,r2,#16
00000c  620a              STR      r2,[r1,#0x20]
;;;505        
;;;506        if (u32PllClkSrc==CLK_PLLCON_PLL_SRC_HXT){
;;;507            /* PLL source clock from HXT */
;;;508            u32CLK_SRC = 0;
;;;509            u32PllSrcClk = __HXT;
00000e  4e4d              LDR      r6,|L7.324|
;;;510            u32NR = 2;
;;;511        }
;;;512        else {
;;;513            /* PLL source clock from HIRC */
;;;514            u32CLK_SRC = CLK_PLLCON_PLL_SRC_Msk;
;;;515            u32PllSrcClk = __HIRC;
000010  4f4d              LDR      r7,|L7.328|
000012  2800              CMP      r0,#0                 ;506
000014  d00b              BEQ      |L7.46|
000016  0289              LSLS     r1,r1,#10             ;514
;;;516            u32NR = 4; /* u32NR start from 4 when FIN = 22.1184MHz to avoid calculation overflow */
000018  2504              MOVS     r5,#4
00001a  9703              STR      r7,[sp,#0xc]
00001c  9102              STR      r1,[sp,#8]
                  |L7.30|
;;;517        }
;;;518    
;;;519        /* Select "NO" according to request frequency */
;;;520        if ( (u32PllFreq <= FREQ_200MHZ) && (u32PllFreq > FREQ_100MHZ) )
00001e  494b              LDR      r1,|L7.332|
000020  4a4b              LDR      r2,|L7.336|
000022  1861              ADDS     r1,r4,r1
000024  4291              CMP      r1,r2
000026  d807              BHI      |L7.56|
;;;521        {
;;;522            u32NO = 0;
000028  2000              MOVS     r0,#0
00002a  9004              STR      r0,[sp,#0x10]
00002c  e016              B        |L7.92|
                  |L7.46|
00002e  2100              MOVS     r1,#0                 ;508
000030  2502              MOVS     r5,#2                 ;510
000032  9603              STR      r6,[sp,#0xc]          ;510
000034  9102              STR      r1,[sp,#8]            ;510
000036  e7f2              B        |L7.30|
                  |L7.56|
;;;523        }
;;;524        else if ( (u32PllFreq <= FREQ_100MHZ) && (u32PllFreq > FREQ_50MHZ) )
000038  4946              LDR      r1,|L7.340|
00003a  4a47              LDR      r2,|L7.344|
00003c  1861              ADDS     r1,r4,r1
00003e  4291              CMP      r1,r2
000040  d803              BHI      |L7.74|
;;;525        {
;;;526            u32NO = 1;
000042  2001              MOVS     r0,#1
;;;527            u32PllFreq = u32PllFreq << 1;
000044  0064              LSLS     r4,r4,#1
000046  9004              STR      r0,[sp,#0x10]
000048  e008              B        |L7.92|
                  |L7.74|
;;;528        }
;;;529        else if ( (u32PllFreq <= FREQ_50MHZ) && (u32PllFreq >= FREQ_25MHZ) )
00004a  4944              LDR      r1,|L7.348|
00004c  4a43              LDR      r2,|L7.348|
00004e  1861              ADDS     r1,r4,r1
000050  4252              RSBS     r2,r2,#0
000052  4291              CMP      r1,r2
000054  d848              BHI      |L7.232|
;;;530        {
;;;531            u32NO = 3;
000056  2003              MOVS     r0,#3
;;;532            u32PllFreq = u32PllFreq << 2;
000058  00a4              LSLS     r4,r4,#2
00005a  9004              STR      r0,[sp,#0x10]
                  |L7.92|
;;;533        }
;;;534        else
;;;535        {
;;;536            /* Wrong frequency request. Just return default setting. */
;;;537            goto lexit;
;;;538        } 
;;;539        
;;;540        /* Find best solution */
;;;541        u32Min = (uint32_t)-1;
00005c  2600              MOVS     r6,#0
00005e  43f6              MVNS     r6,r6
;;;542        u32MinNR = 0;
000060  2000              MOVS     r0,#0
;;;543        u32MinNF = 0;
000062  9000              STR      r0,[sp,#0]
;;;544        for(;u32NR<=33;u32NR++)
000064  9001              STR      r0,[sp,#4]
000066  e020              B        |L7.170|
                  |L7.104|
;;;545        {
;;;546            u32Tmp = u32PllSrcClk / u32NR;
000068  4629              MOV      r1,r5
00006a  9803              LDR      r0,[sp,#0xc]
00006c  f7fffffe          BL       __aeabi_uidivmod
;;;547            if((u32Tmp > 1600000) && (u32Tmp < 15000000))
000070  493b              LDR      r1,|L7.352|
000072  4a3c              LDR      r2,|L7.356|
000074  1841              ADDS     r1,r0,r1
000076  4291              CMP      r1,r2
000078  d216              BCS      |L7.168|
;;;548            {
;;;549                for(u32NF=2;u32NF<=513;u32NF++)
00007a  2202              MOVS     r2,#2
                  |L7.124|
00007c  4601              MOV      r1,r0
;;;550                {
;;;551                    u32Tmp2 = u32Tmp * u32NF;
;;;552                    if((u32Tmp2 > 120000000) && (u32Tmp2 < 200000000))
00007e  4b3a              LDR      r3,|L7.360|
000080  4351              MULS     r1,r2,r1              ;551
000082  18cf              ADDS     r7,r1,r3
000084  4b39              LDR      r3,|L7.364|
000086  429f              CMP      r7,r3
000088  d20a              BCS      |L7.160|
;;;553                    {
;;;554                        u32Tmp3 = (u32Tmp2 > u32PllFreq)?u32Tmp2-u32PllFreq:u32PllFreq-u32Tmp2;
00008a  42a1              CMP      r1,r4
00008c  d901              BLS      |L7.146|
00008e  1b0b              SUBS     r3,r1,r4
000090  e000              B        |L7.148|
                  |L7.146|
000092  1a63              SUBS     r3,r4,r1
                  |L7.148|
;;;555                        if(u32Tmp3 < u32Min)
000094  42b3              CMP      r3,r6
000096  d203              BCS      |L7.160|
;;;556                        {
;;;557                            u32Min = u32Tmp3;
000098  001e              MOVS     r6,r3
;;;558                            u32MinNR = u32NR;
;;;559                            u32MinNF = u32NF;
;;;560                            
;;;561                            /* Break when get good results */
;;;562                            if(u32Min == 0)
00009a  9500              STR      r5,[sp,#0]
00009c  9201              STR      r2,[sp,#4]
00009e  d003              BEQ      |L7.168|
                  |L7.160|
0000a0  4933              LDR      r1,|L7.368|
0000a2  1c52              ADDS     r2,r2,#1              ;549
0000a4  428a              CMP      r2,r1                 ;549
0000a6  d9e9              BLS      |L7.124|
                  |L7.168|
0000a8  1c6d              ADDS     r5,r5,#1              ;544
                  |L7.170|
0000aa  2d21              CMP      r5,#0x21              ;544
0000ac  d9dc              BLS      |L7.104|
;;;563                                break;
;;;564                        }
;;;565                    }
;;;566                }
;;;567            }
;;;568        }
;;;569            
;;;570        /* Enable and apply new PLL setting. */
;;;571        CLK->PLLCON = u32CLK_SRC | (u32NO<<14) | ((u32MinNR - 2)<<9) | (u32MinNF - 2);
0000ae  9804              LDR      r0,[sp,#0x10]
0000b0  9902              LDR      r1,[sp,#8]
0000b2  0380              LSLS     r0,r0,#14
0000b4  4308              ORRS     r0,r0,r1
0000b6  9900              LDR      r1,[sp,#0]
0000b8  024a              LSLS     r2,r1,#9
0000ba  2101              MOVS     r1,#1
0000bc  0289              LSLS     r1,r1,#10
0000be  1a51              SUBS     r1,r2,r1
0000c0  4308              ORRS     r0,r0,r1
0000c2  9901              LDR      r1,[sp,#4]
0000c4  1e89              SUBS     r1,r1,#2
0000c6  4308              ORRS     r0,r0,r1
0000c8  491d              LDR      r1,|L7.320|
0000ca  6208              STR      r0,[r1,#0x20]
;;;572        
;;;573        /* Waiting for PLL clock stable */
;;;574        CLK_WaitClockReady(CLK_CLKSTATUS_PLL_STB_Msk);
0000cc  2004              MOVS     r0,#4
0000ce  f7fffffe          BL       CLK_WaitClockReady
;;;575        
;;;576        /* Return acture PLL output clock frequency */
;;;577        return u32PllSrcClk/((u32NO+1)*u32MinNR)*u32MinNF;    
0000d2  9904              LDR      r1,[sp,#0x10]
0000d4  9800              LDR      r0,[sp,#0]
0000d6  1c49              ADDS     r1,r1,#1
0000d8  4341              MULS     r1,r0,r1
0000da  9803              LDR      r0,[sp,#0xc]
0000dc  f7fffffe          BL       __aeabi_uidivmod
0000e0  9901              LDR      r1,[sp,#4]
0000e2  4348              MULS     r0,r1,r0
                  |L7.228|
;;;578        
;;;579    lexit:    
;;;580        
;;;581        /* Apply default PLL setting and return */
;;;582        if (u32PllClkSrc==CLK_PLLCON_PLL_SRC_HXT)
;;;583            CLK->PLLCON = 0xC22E; /* 48MHz */
;;;584        else
;;;585            CLK->PLLCON = 0xD66F; /* 48.06498462MHz */
;;;586    
;;;587        CLK_WaitClockReady(CLK_CLKSTATUS_PLL_STB_Msk);
;;;588        return CLK_GetPLLClockFreq();  
;;;589        
;;;590        
;;;591    }
0000e4  b005              ADD      sp,sp,#0x14
0000e6  bdf0              POP      {r4-r7,pc}
                  |L7.232|
0000e8  2800              CMP      r0,#0                 ;582
0000ea  d00f              BEQ      |L7.268|
0000ec  4921              LDR      r1,|L7.372|
                  |L7.238|
0000ee  4814              LDR      r0,|L7.320|
0000f0  6201              STR      r1,[r0,#0x20]         ;585
0000f2  2004              MOVS     r0,#4                 ;587
0000f4  f7fffffe          BL       CLK_WaitClockReady
0000f8  a01f              ADR      r0,|L7.376|
0000fa  6800              LDR      r0,[r0,#0]            ;587
0000fc  9000              STR      r0,[sp,#0]            ;587
0000fe  4810              LDR      r0,|L7.320|
000100  6a01              LDR      r1,[r0,#0x20]         ;587
000102  1300              ASRS     r0,r0,#12             ;587
000104  4201              TST      r1,r0                 ;587
000106  d003              BEQ      |L7.272|
000108  2000              MOVS     r0,#0                 ;587
00010a  e7eb              B        |L7.228|
                  |L7.268|
00010c  491b              LDR      r1,|L7.380|
00010e  e7ee              B        |L7.238|
                  |L7.272|
000110  0308              LSLS     r0,r1,#12             ;583
000112  d501              BPL      |L7.280|
000114  4638              MOV      r0,r7                 ;583
000116  e000              B        |L7.282|
                  |L7.280|
000118  4630              MOV      r0,r6                 ;583
                  |L7.282|
00011a  038a              LSLS     r2,r1,#14             ;583
00011c  d4e2              BMI      |L7.228|
00011e  040a              LSLS     r2,r1,#16             ;583
000120  0f92              LSRS     r2,r2,#30             ;583
000122  466b              MOV      r3,sp                 ;583
000124  5c9b              LDRB     r3,[r3,r2]            ;583
000126  05ca              LSLS     r2,r1,#23             ;583
000128  0489              LSLS     r1,r1,#18             ;583
00012a  0dd2              LSRS     r2,r2,#23             ;583
00012c  0ec9              LSRS     r1,r1,#27             ;583
00012e  1c92              ADDS     r2,r2,#2              ;583
000130  1c89              ADDS     r1,r1,#2              ;583
000132  0880              LSRS     r0,r0,#2              ;583
000134  4359              MULS     r1,r3,r1              ;583
000136  4350              MULS     r0,r2,r0              ;583
000138  f7fffffe          BL       __aeabi_uidivmod
00013c  0080              LSLS     r0,r0,#2              ;583
00013e  e7d1              B        |L7.228|
;;;592    
                          ENDP

                  |L7.320|
                          DCD      0x50000200
                  |L7.324|
                          DCD      0x00b71b00
                  |L7.328|
                          DCD      0x01518000
                  |L7.332|
                          DCD      0xfa0a1eff
                  |L7.336|
                          DCD      0x05f5e0ff
                  |L7.340|
                          DCD      0xfd050f7f
                  |L7.344|
                          DCD      0x02faf07f
                  |L7.348|
                          DCD      0xfe8287c0
                  |L7.352|
                          DCD      0xffe795ff
                  |L7.356|
                          DCD      0x00cc77bf
                  |L7.360|
                          DCD      0xf8d8f1ff
                  |L7.364|
                          DCD      0x04c4b3ff
                  |L7.368|
                          DCD      0x00000201
                  |L7.372|
                          DCD      0x0000d66f
                  |L7.376|
000178  01020204          DCB      1,2,2,4
                  |L7.380|
                          DCD      0x0000c22e

                          AREA ||i.CLK_EnableXtalRC||, CODE, READONLY, ALIGN=2

                  CLK_EnableXtalRC PROC
;;;385      */
;;;386    void CLK_EnableXtalRC(uint32_t u32ClkMask)
000000  4902              LDR      r1,|L8.12|
;;;387    {
;;;388        CLK->PWRCON |= u32ClkMask; 
000002  680a              LDR      r2,[r1,#0]
000004  4302              ORRS     r2,r2,r0
000006  600a              STR      r2,[r1,#0]
;;;389    }
000008  4770              BX       lr
;;;390    
                          ENDP

00000a  0000              DCW      0x0000
                  |L8.12|
                          DCD      0x50000200

                          AREA ||i.CLK_GetCPUFreq||, CODE, READONLY, ALIGN=2

                  CLK_GetCPUFreq PROC
;;;129      */
;;;130    uint32_t CLK_GetCPUFreq(void)
000000  b510              PUSH     {r4,lr}
;;;131    {
;;;132        SystemCoreClockUpdate();
000002  f7fffffe          BL       SystemCoreClockUpdate
;;;133        return SystemCoreClock;
000006  4801              LDR      r0,|L9.12|
000008  6800              LDR      r0,[r0,#0]  ; SystemCoreClock
;;;134    }
00000a  bd10              POP      {r4,pc}
;;;135    
                          ENDP

                  |L9.12|
                          DCD      SystemCoreClock

                          AREA ||i.CLK_GetHCLKFreq||, CODE, READONLY, ALIGN=2

                  CLK_GetHCLKFreq PROC
;;;118      */
;;;119    uint32_t CLK_GetHCLKFreq(void)
000000  b510              PUSH     {r4,lr}
;;;120    {
;;;121        SystemCoreClockUpdate();
000002  f7fffffe          BL       SystemCoreClockUpdate
;;;122        return SystemCoreClock;
000006  4801              LDR      r0,|L10.12|
000008  6800              LDR      r0,[r0,#0]  ; SystemCoreClock
;;;123    }
00000a  bd10              POP      {r4,pc}
;;;124    
                          ENDP

                  |L10.12|
                          DCD      SystemCoreClock

                          AREA ||i.CLK_GetHXTFreq||, CODE, READONLY, ALIGN=2

                  CLK_GetHXTFreq PROC
;;;92       */
;;;93     uint32_t CLK_GetHXTFreq(void)
000000  4802              LDR      r0,|L11.12|
;;;94     {  
;;;95       if(CLK->PWRCON & CLK_PWRCON_XTL12M_EN_Msk )
000002  6800              LDR      r0,[r0,#0]
000004  07c0              LSLS     r0,r0,#31
000006  d000              BEQ      |L11.10|
;;;96         return __HXT;
000008  4801              LDR      r0,|L11.16|
                  |L11.10|
;;;97       else 
;;;98         return 0;
;;;99     }
00000a  4770              BX       lr
;;;100    
                          ENDP

                  |L11.12|
                          DCD      0x50000200
                  |L11.16|
                          DCD      0x00b71b00

                          AREA ||i.CLK_GetLXTFreq||, CODE, READONLY, ALIGN=2

                  CLK_GetLXTFreq PROC
;;;105      */
;;;106    uint32_t CLK_GetLXTFreq(void)
000000  4803              LDR      r0,|L12.16|
;;;107    {
;;;108      if(CLK->PWRCON & CLK_PWRCON_XTL32K_EN_Msk )
000002  6800              LDR      r0,[r0,#0]
000004  0780              LSLS     r0,r0,#30
000006  d501              BPL      |L12.12|
;;;109        return __HIRC;
000008  4802              LDR      r0,|L12.20|
;;;110      else 
;;;111        return 0;
;;;112    }
00000a  4770              BX       lr
                  |L12.12|
00000c  2000              MOVS     r0,#0                 ;111
00000e  4770              BX       lr
;;;113    
                          ENDP

                  |L12.16|
                          DCD      0x50000200
                  |L12.20|
                          DCD      0x01518000

                          AREA ||i.CLK_Idle||, CODE, READONLY, ALIGN=2

                  CLK_Idle PROC
;;;81       */
;;;82     void CLK_Idle(void)
000000  4805              LDR      r0,|L13.24|
;;;83     {
;;;84         SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
000002  6901              LDR      r1,[r0,#0x10]
000004  2204              MOVS     r2,#4
000006  4391              BICS     r1,r1,r2
000008  6101              STR      r1,[r0,#0x10]
;;;85         CLK->PWRCON &= ~CLK_PWRCON_PWR_DOWN_EN_Msk;
00000a  4804              LDR      r0,|L13.28|
00000c  6801              LDR      r1,[r0,#0]
00000e  2280              MOVS     r2,#0x80
000010  4391              BICS     r1,r1,r2
000012  6001              STR      r1,[r0,#0]
;;;86         __WFI();
000014  bf30              WFI      
;;;87     }
000016  4770              BX       lr
;;;88     
                          ENDP

                  |L13.24|
                          DCD      0xe000ed00
                  |L13.28|
                          DCD      0x50000200

                          AREA ||i.CLK_PowerDown||, CODE, READONLY, ALIGN=2

                  CLK_PowerDown PROC
;;;70       */
;;;71     void CLK_PowerDown(void)
000000  4806              LDR      r0,|L14.28|
;;;72     {
;;;73         SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
000002  6901              LDR      r1,[r0,#0x10]
000004  2204              MOVS     r2,#4
000006  4311              ORRS     r1,r1,r2
000008  6101              STR      r1,[r0,#0x10]
;;;74         CLK->PWRCON |= (CLK_PWRCON_PWR_DOWN_EN_Msk | CLK_PWRCON_PD_WAIT_CPU_Msk);
00000a  4805              LDR      r0,|L14.32|
00000c  6801              LDR      r1,[r0,#0]
00000e  22ff              MOVS     r2,#0xff
000010  3281              ADDS     r2,r2,#0x81
000012  4311              ORRS     r1,r1,r2
000014  6001              STR      r1,[r0,#0]
;;;75         __WFI();
000016  bf30              WFI      
;;;76     }
000018  4770              BX       lr
;;;77     
                          ENDP

00001a  0000              DCW      0x0000
                  |L14.28|
                          DCD      0xe000ed00
                  |L14.32|
                          DCD      0x50000200

                          AREA ||i.CLK_SetCoreClock||, CODE, READONLY, ALIGN=2

                  CLK_SetCoreClock PROC
;;;141      */
;;;142    uint32_t CLK_SetCoreClock(uint32_t u32Hclk)
000000  b5f8              PUSH     {r3-r7,lr}
;;;143    {    
;;;144        uint8_t u32FomSel; /* u32FomSel[1:0] => 72MHz, [3:2] => 50MHz, [5:4] => 25MHz */
;;;145        uint32_t u32Div;
;;;146        
;;;147        /* Boundary Check */
;;;148        if(u32Hclk > FREQ_72MHZ)
000002  4b24              LDR      r3,|L15.148|
000004  4298              CMP      r0,r3
000006  d901              BLS      |L15.12|
;;;149            u32Hclk = FREQ_72MHZ;
000008  4618              MOV      r0,r3
00000a  e003              B        |L15.20|
                  |L15.12|
;;;150        if(u32Hclk < FREQ_25MHZ)
00000c  4922              LDR      r1,|L15.152|
00000e  4288              CMP      r0,r1
000010  d200              BCS      |L15.20|
;;;151            u32Hclk = FREQ_25MHZ;
000012  4608              MOV      r0,r1
                  |L15.20|
;;;152        
;;;153        /* HCLK divider */
;;;154        u32Div = 1;
;;;155        
;;;156        /* Flash Access Delay */
;;;157        if(u32Hclk > FREQ_50MHZ)
000014  4921              LDR      r1,|L15.156|
000016  2401              MOVS     r4,#1                 ;154
000018  4288              CMP      r0,r1
00001a  d901              BLS      |L15.32|
;;;158          u32FomSel = 5;  
00001c  2505              MOVS     r5,#5
00001e  e000              B        |L15.34|
                  |L15.32|
;;;159        else
;;;160          u32FomSel = 0;
000020  2500              MOVS     r5,#0
                  |L15.34|
;;;161    
;;;162        /* Maximum Flash Access Delay for Safe */
;;;163        FMC->FATCON = (FMC->FATCON & (~(5 << 4))) | 5;
000022  4e1f              LDR      r6,|L15.160|
000024  69b1              LDR      r1,[r6,#0x18]
000026  2250              MOVS     r2,#0x50
000028  4391              BICS     r1,r1,r2
00002a  2205              MOVS     r2,#5
00002c  4311              ORRS     r1,r1,r2
00002e  61b1              STR      r1,[r6,#0x18]
;;;164        
;;;165        /* Switch to HIRC for Safe. Avoid HCLK too high when applying new divider. */
;;;166        CLK->PWRCON |= CLK_PWRCON_OSC22M_EN_Msk;
000030  491c              LDR      r1,|L15.164|
000032  680a              LDR      r2,[r1,#0]
000034  2704              MOVS     r7,#4
000036  433a              ORRS     r2,r2,r7
000038  600a              STR      r2,[r1,#0]
                  |L15.58|
;;;167        while((CLK->CLKSTATUS & CLK_CLKSTATUS_OSC22M_STB_Msk) == 0);
00003a  68ca              LDR      r2,[r1,#0xc]
00003c  06d2              LSLS     r2,r2,#27
00003e  d5fc              BPL      |L15.58|
;;;168        CLK->CLKSEL0 = (CLK->CLKSEL0 & (~CLK_CLKSEL0_HCLK_S_Msk)) | CLK_CLKSEL0_HCLK_S_HIRC;
000040  690a              LDR      r2,[r1,#0x10]
000042  2707              MOVS     r7,#7
000044  433a              ORRS     r2,r2,r7
000046  610a              STR      r2,[r1,#0x10]
;;;169        
;;;170        /* Disable PLL to Avoid PLL Unstable while Setting */
;;;171        CLK->PLLCON |= CLK_PLLCON_PD_Msk;
000048  6a0a              LDR      r2,[r1,#0x20]
00004a  2701              MOVS     r7,#1
00004c  043f              LSLS     r7,r7,#16
00004e  433a              ORRS     r2,r2,r7
000050  620a              STR      r2,[r1,#0x20]
;;;172        
;;;173        if (CLK->PWRCON & CLK_PWRCON_XTL12M_EN_Msk)      
000052  6809              LDR      r1,[r1,#0]
000054  07c9              LSLS     r1,r1,#31
000056  d018              BEQ      |L15.138|
;;;174        {
;;;175            if(u32Hclk == FREQ_72MHZ)
000058  4298              CMP      r0,r3
00005a  d106              BNE      |L15.106|
;;;176            {
;;;177                /* PLL = 144MHz, HCLK = PLL / 2 (This is for using USB(48MHz) with HCLK=72MHz) */
;;;178                u32Hclk = CLK_EnablePLL(CLK_PLLCON_PLL_SRC_HXT, u32Hclk*2);
00005c  0041              LSLS     r1,r0,#1
00005e  2000              MOVS     r0,#0
000060  f7fffffe          BL       CLK_EnablePLL
000064  4607              MOV      r7,r0
;;;179                u32Div = 2;
000066  2402              MOVS     r4,#2
000068  e004              B        |L15.116|
                  |L15.106|
;;;180            }
;;;181            else
;;;182                u32Hclk = CLK_EnablePLL(CLK_PLLCON_PLL_SRC_HXT, u32Hclk);
00006a  4601              MOV      r1,r0
00006c  2000              MOVS     r0,#0
                  |L15.110|
00006e  f7fffffe          BL       CLK_EnablePLL
000072  4607              MOV      r7,r0
                  |L15.116|
;;;183        }
;;;184        else
;;;185            u32Hclk = CLK_EnablePLL(CLK_PLLCON_PLL_SRC_HIRC, u32Hclk); 
;;;186        
;;;187        CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_PLL,CLK_CLKDIV_HCLK(u32Div));
000074  1e61              SUBS     r1,r4,#1
000076  2002              MOVS     r0,#2
000078  f7fffffe          BL       CLK_SetHCLK
;;;188    
;;;189        /* Flash Access Delay */
;;;190        FMC->FATCON = (FMC->FATCON & (~(5 << 4))) | u32FomSel;
00007c  69b0              LDR      r0,[r6,#0x18]
00007e  2150              MOVS     r1,#0x50
000080  4388              BICS     r0,r0,r1
000082  4328              ORRS     r0,r0,r5
000084  61b0              STR      r0,[r6,#0x18]
;;;191        
;;;192        return u32Hclk;
000086  4638              MOV      r0,r7
;;;193    }
000088  bdf8              POP      {r3-r7,pc}
                  |L15.138|
00008a  4601              MOV      r1,r0                 ;185
00008c  2001              MOVS     r0,#1                 ;185
00008e  04c0              LSLS     r0,r0,#19             ;185
000090  e7ed              B        |L15.110|
;;;194    
                          ENDP

000092  0000              DCW      0x0000
                  |L15.148|
                          DCD      0x044aa200
                  |L15.152|
                          DCD      0x017d7840
                  |L15.156|
                          DCD      0x02faf080
                  |L15.160|
                          DCD      0x5000c000
                  |L15.164|
                          DCD      0x50000200

                          AREA ||i.CLK_SetHCLK||, CODE, READONLY, ALIGN=2

                  CLK_SetHCLK PROC
;;;206      */
;;;207    void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv)
000000  b510              PUSH     {r4,lr}
;;;208    {
;;;209        /* Switch to HIRC for Safe. Avoid HCLK too high when applying new divider. */
;;;210        CLK->PWRCON |= CLK_PWRCON_OSC22M_EN_Msk;
000002  4a0c              LDR      r2,|L16.52|
000004  6813              LDR      r3,[r2,#0]
000006  2404              MOVS     r4,#4
000008  4323              ORRS     r3,r3,r4
00000a  6013              STR      r3,[r2,#0]
                  |L16.12|
;;;211        while((CLK->CLKSTATUS & CLK_CLKSTATUS_OSC22M_STB_Msk) == 0);
00000c  68d3              LDR      r3,[r2,#0xc]
00000e  06db              LSLS     r3,r3,#27
000010  d5fc              BPL      |L16.12|
;;;212        CLK->CLKSEL0 = (CLK->CLKSEL0 & (~CLK_CLKSEL0_HCLK_S_Msk)) | CLK_CLKSEL0_HCLK_S_HIRC;
000012  6913              LDR      r3,[r2,#0x10]
000014  2407              MOVS     r4,#7
000016  4323              ORRS     r3,r3,r4
000018  6113              STR      r3,[r2,#0x10]
;;;213        
;;;214        /* Apply new Divider */
;;;215        CLK->CLKDIV = (CLK->CLKDIV & (~CLK_CLKDIV_HCLK_N_Msk)) | u32ClkDiv;
00001a  6993              LDR      r3,[r2,#0x18]
00001c  091b              LSRS     r3,r3,#4
00001e  011b              LSLS     r3,r3,#4
000020  430b              ORRS     r3,r3,r1
000022  6193              STR      r3,[r2,#0x18]
;;;216        
;;;217        /* Switch to new HCLK source */
;;;218        CLK->CLKSEL0 = (CLK->CLKSEL0 & (~CLK_CLKSEL0_HCLK_S_Msk)) | u32ClkSrc;
000024  6911              LDR      r1,[r2,#0x10]
000026  43a1              BICS     r1,r1,r4
000028  4301              ORRS     r1,r1,r0
00002a  6111              STR      r1,[r2,#0x10]
;;;219        
;;;220        /* Update System Core Clock */
;;;221        SystemCoreClockUpdate();
00002c  f7fffffe          BL       SystemCoreClockUpdate
;;;222    }
000030  bd10              POP      {r4,pc}
;;;223    
                          ENDP

000032  0000              DCW      0x0000
                  |L16.52|
                          DCD      0x50000200

                          AREA ||i.CLK_SetModuleClock||, CODE, READONLY, ALIGN=2

                  CLK_SetModuleClock PROC
;;;328      
;;;329    void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv)
000000  b5f0              PUSH     {r4-r7,lr}
;;;330    {
;;;331        uint32_t u32sel=0,u32div=0;
;;;332        uint32_t u32SelTbl[4] = {0x0, 0x4, 0xC, 0x24}; 
000002  4b2c              LDR      r3,|L17.180|
000004  b086              SUB      sp,sp,#0x18           ;330
000006  461c              MOV      r4,r3
000008  3408              ADDS     r4,r4,#8
00000a  ccf0              LDM      r4,{r4-r7}
;;;333        uint32_t u32DivTbl[2] = {0x0, 0x20}; 
00000c  9703              STR      r7,[sp,#0xc]
00000e  466f              MOV      r7,sp
000010  c770              STM      r7!,{r4-r6}
000012  cb18              LDM      r3,{r3,r4}
;;;334    
;;;335        if(MODULE_CLKSEL_Msk(u32ModuleIdx)!=MODULE_NoMsk)
000014  9304              STR      r3,[sp,#0x10]
000016  0e43              LSRS     r3,r0,#25
000018  9405              STR      r4,[sp,#0x14]
00001a  075b              LSLS     r3,r3,#29
00001c  d033              BEQ      |L17.134|
;;;336        {  
;;;337            /* Get clock select control register address */
;;;338            u32sel = (uint32_t)&CLK->CLKSEL0+(u32SelTbl[MODULE_CLKSEL(u32ModuleIdx)]);
00001e  0083              LSLS     r3,r0,#2
000020  0f9b              LSRS     r3,r3,#30
000022  009b              LSLS     r3,r3,#2
000024  466c              MOV      r4,sp
000026  58e3              LDR      r3,[r4,r3]
000028  4c23              LDR      r4,|L17.184|
00002a  191b              ADDS     r3,r3,r4
;;;339            /* Set new clock selection setting */
;;;340            M32(u32sel) = (M32(u32sel) & (~(MODULE_CLKSEL_Msk(u32ModuleIdx)<<MODULE_CLKSEL_Pos(u32ModuleIdx)))) | u32ClkSrc;
00002c  0104              LSLS     r4,r0,#4
00002e  0f65              LSRS     r5,r4,#29
000030  01c4              LSLS     r4,r0,#7
000032  0ee4              LSRS     r4,r4,#27
000034  40a5              LSLS     r5,r5,r4
000036  681c              LDR      r4,[r3,#0]
000038  43ac              BICS     r4,r4,r5
00003a  430c              ORRS     r4,r4,r1
00003c  601c              STR      r4,[r3,#0]
;;;341          
;;;342            /* We need to set CLKSEL2 ext control bit for PWM */
;;;343            if( u32ModuleIdx==PWM01_MODULE )
;;;344                CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_PWM01_S_E_Msk)) | (u32ClkSrc&CLK_CLKSEL2_PWM01_S_E_Msk);  
00003e  4b1e              LDR      r3,|L17.184|
000040  24ff              MOVS     r4,#0xff
000042  4d1e              LDR      r5,|L17.188|
000044  3401              ADDS     r4,#1
000046  3b10              SUBS     r3,r3,#0x10
000048  4021              ANDS     r1,r1,r4
00004a  42a8              CMP      r0,r5                 ;343
00004c  d104              BNE      |L17.88|
00004e  69dd              LDR      r5,[r3,#0x1c]
000050  43a5              BICS     r5,r5,r4
000052  430d              ORRS     r5,r5,r1
000054  61dd              STR      r5,[r3,#0x1c]
000056  e016              B        |L17.134|
                  |L17.88|
;;;345            else if( u32ModuleIdx==PWM23_MODULE )  
000058  4c19              LDR      r4,|L17.192|
00005a  42a0              CMP      r0,r4
00005c  d103              BNE      |L17.102|
;;;346                CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_PWM23_S_E_Msk)) | (u32ClkSrc&CLK_CLKSEL2_PWM01_S_E_Msk);
00005e  69dc              LDR      r4,[r3,#0x1c]
000060  2501              MOVS     r5,#1
000062  026d              LSLS     r5,r5,#9
000064  e00c              B        |L17.128|
                  |L17.102|
;;;347            else if( u32ModuleIdx==PWM45_MODULE )  
000066  4c17              LDR      r4,|L17.196|
000068  42a0              CMP      r0,r4
00006a  d103              BNE      |L17.116|
;;;348                CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_PWM45_S_E_Msk)) | (u32ClkSrc&CLK_CLKSEL2_PWM01_S_E_Msk);  
00006c  69dc              LDR      r4,[r3,#0x1c]
00006e  2501              MOVS     r5,#1
000070  02ad              LSLS     r5,r5,#10
000072  e005              B        |L17.128|
                  |L17.116|
;;;349            else if( u32ModuleIdx==PWM67_MODULE )  
000074  4c14              LDR      r4,|L17.200|
000076  42a0              CMP      r0,r4
000078  d105              BNE      |L17.134|
;;;350                CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_PWM67_S_E_Msk)) | (u32ClkSrc&CLK_CLKSEL2_PWM01_S_E_Msk);        
00007a  69dc              LDR      r4,[r3,#0x1c]
00007c  2501              MOVS     r5,#1
00007e  02ed              LSLS     r5,r5,#11
                  |L17.128|
000080  43ac              BICS     r4,r4,r5
000082  430c              ORRS     r4,r4,r1
000084  61dc              STR      r4,[r3,#0x1c]
                  |L17.134|
;;;351        }
;;;352    
;;;353        if(MODULE_CLKDIV_Msk(u32ModuleIdx)!=MODULE_NoMsk)
000086  0a83              LSRS     r3,r0,#10
000088  0619              LSLS     r1,r3,#24
00008a  0e09              LSRS     r1,r1,#24
00008c  d00f              BEQ      |L17.174|
;;;354        {
;;;355            /* Get clock divider control register address */
;;;356            u32div =(uint32_t)&CLK->CLKDIV+(u32DivTbl[MODULE_CLKDIV(u32ModuleIdx)]);
00008e  0301              LSLS     r1,r0,#12
000090  0f89              LSRS     r1,r1,#30
000092  0089              LSLS     r1,r1,#2
000094  ac04              ADD      r4,sp,#0x10
000096  5861              LDR      r1,[r4,r1]
000098  4c07              LDR      r4,|L17.184|
;;;357            /* Applie new divider */
;;;358            M32(u32div) = (M32(u32div) & (~(MODULE_CLKDIV_Msk(u32ModuleIdx)<<MODULE_CLKDIV_Pos(u32ModuleIdx)))) | u32ClkDiv;  
00009a  0580              LSLS     r0,r0,#22
00009c  3408              ADDS     r4,r4,#8              ;356
00009e  1909              ADDS     r1,r1,r4              ;356
0000a0  b2db              UXTB     r3,r3
0000a2  0ec0              LSRS     r0,r0,#27
0000a4  4083              LSLS     r3,r3,r0
0000a6  6808              LDR      r0,[r1,#0]
0000a8  4398              BICS     r0,r0,r3
0000aa  4310              ORRS     r0,r0,r2
0000ac  6008              STR      r0,[r1,#0]
                  |L17.174|
;;;359        }
;;;360    }
0000ae  b006              ADD      sp,sp,#0x18
0000b0  bdf0              POP      {r4-r7,pc}
;;;361    
                          ENDP

0000b2  0000              DCW      0x0000
                  |L17.180|
                          DCD      ||.constdata||
                  |L17.184|
                          DCD      0x50000210
                  |L17.188|
                          DCD      0x57c00014
                  |L17.192|
                          DCD      0x57e00015
                  |L17.196|
                          DCD      0x66400016
                  |L17.200|
                          DCD      0x66600017

                          AREA ||i.CLK_SetSysTickClockSrc||, CODE, READONLY, ALIGN=2

                  CLK_SetSysTickClockSrc PROC
;;;371      */
;;;372    void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc)
000000  4a03              LDR      r2,|L18.16|
;;;373    {
;;;374        CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_STCLK_S_Msk) | u32ClkSrc;
000002  6911              LDR      r1,[r2,#0x10]
000004  2338              MOVS     r3,#0x38
000006  4399              BICS     r1,r1,r3
000008  4301              ORRS     r1,r1,r0
00000a  6111              STR      r1,[r2,#0x10]
;;;375    }
00000c  4770              BX       lr
;;;376    
                          ENDP

00000e  0000              DCW      0x0000
                  |L18.16|
                          DCD      0x50000200

                          AREA ||i.CLK_WaitClockReady||, CODE, READONLY, ALIGN=2

                  CLK_WaitClockReady PROC
;;;617      */
;;;618    uint32_t CLK_WaitClockReady(uint32_t u32ClkMask)
000000  b510              PUSH     {r4,lr}
;;;619    {
000002  4604              MOV      r4,r0
;;;620        int32_t i32TimeOutCnt;
;;;621    
;;;622        i32TimeOutCnt = __HSI / 200; /* About 5ms */
000004  4907              LDR      r1,|L19.36|
;;;623        
;;;624        while((CLK->CLKSTATUS & u32ClkMask) != u32ClkMask)
000006  4b08              LDR      r3,|L19.40|
000008  e005              B        |L19.22|
                  |L19.10|
;;;625        {
;;;626            if(i32TimeOutCnt-- <= 0)
00000a  460a              MOV      r2,r1
00000c  1e49              SUBS     r1,r1,#1
00000e  2a00              CMP      r2,#0
000010  dc01              BGT      |L19.22|
;;;627                return 0;     
000012  2000              MOVS     r0,#0
;;;628        } 
;;;629        
;;;630        return 1;    
;;;631    }
000014  bd10              POP      {r4,pc}
                  |L19.22|
000016  68da              LDR      r2,[r3,#0xc]          ;624
000018  4620              MOV      r0,r4                 ;624
00001a  4390              BICS     r0,r0,r2              ;624
00001c  d1f5              BNE      |L19.10|
00001e  2001              MOVS     r0,#1                 ;630
000020  bd10              POP      {r4,pc}
;;;632    
                          ENDP

000022  0000              DCW      0x0000
                  |L19.36|
                          DCD      0x0003d090
                  |L19.40|
                          DCD      0x50000200

                          AREA ||.constdata||, DATA, READONLY, ALIGN=2

                          DCD      0x00000000
                          DCD      0x00000020
                          DCD      0x00000000
                          DCD      0x00000004
                          DCD      0x0000000c
                          DCD      0x00000024
                          DCD      0x00000000
                          DCD      0x00000004
                          DCD      0x0000002c
                          DCD      0x00000000
                          DCD      0x00000000
                          DCD      0x00000004
                          DCD      0x0000002c
                          DCD      0x00000000

;*** Start embedded assembler ***

#line 1 "..\\..\\..\\..\\Library\\StdDriver\\src\\clk.c"
	AREA ||.rev16_text||, CODE, READONLY
	THUMB
	EXPORT |__asm___5_clk_c_9b5832dc____REV16|
#line 118 "..\\..\\..\\..\\Library\\CMSIS\\Include\\core_cmInstr.h"
|__asm___5_clk_c_9b5832dc____REV16| PROC
#line 119

 rev16 r0, r0
 bx lr
	ENDP
	AREA ||.revsh_text||, CODE, READONLY
	THUMB
	EXPORT |__asm___5_clk_c_9b5832dc____REVSH|
#line 132
|__asm___5_clk_c_9b5832dc____REVSH| PROC
#line 133

 revsh r0, r0
 bx lr
	ENDP

;*** End   embedded assembler ***
