; generated by ARM C/C++ Compiler, 5.03 [Build 24]
; commandline ArmCC [--list --split_sections --debug -c --asm --interleave -o.\obj\fmc.o --asm_dir=.\lst\ --list_dir=.\lst\ --depend=.\obj\fmc.d --cpu=Cortex-M0 --apcs=interwork -I.\ -I..\..\..\..\Library\CMSIS\Include -I..\..\..\..\Library\Device\Nuvoton\NUC200Series\Include -I..\..\..\..\Library\StdDriver\inc -IC:\Keil\ARM\RV31\INC -IC:\Keil\ARM\CMSIS\Include -IC:\Keil\ARM\Inc\?ST\STM32F10x -D__MICROLIB --omf_browse=.\obj\fmc.crf ..\..\..\..\Library\StdDriver\src\fmc.c]
                          THUMB

                          AREA ||i.FMC_Close||, CODE, READONLY, ALIGN=2

                  FMC_Close PROC
;;;53       */
;;;54     void FMC_Close(void)
000000  4802              LDR      r0,|L1.12|
;;;55     {
;;;56         FMC->ISPCON &= ~FMC_ISPCON_ISPEN_Msk;
000002  6801              LDR      r1,[r0,#0]
000004  0849              LSRS     r1,r1,#1
000006  0049              LSLS     r1,r1,#1
000008  6001              STR      r1,[r0,#0]
;;;57     }
00000a  4770              BX       lr
;;;58     
                          ENDP

                  |L1.12|
                          DCD      0x5000c000

                          AREA ||i.FMC_DisableAPUpdate||, CODE, READONLY, ALIGN=2

                  FMC_DisableAPUpdate PROC
;;;66       */
;;;67     void FMC_DisableAPUpdate(void)
000000  4802              LDR      r0,|L2.12|
;;;68     {
;;;69         FMC->ISPCON &= ~FMC_ISPCON_APUEN_Msk;
000002  6801              LDR      r1,[r0,#0]
000004  2208              MOVS     r2,#8
000006  4391              BICS     r1,r1,r2
000008  6001              STR      r1,[r0,#0]
;;;70     }
00000a  4770              BX       lr
;;;71     
                          ENDP

                  |L2.12|
                          DCD      0x5000c000

                          AREA ||i.FMC_DisableConfigUpdate||, CODE, READONLY, ALIGN=2

                  FMC_DisableConfigUpdate PROC
;;;78       */
;;;79     void FMC_DisableConfigUpdate(void)
000000  4802              LDR      r0,|L3.12|
;;;80     {
;;;81         FMC->ISPCON &= ~FMC_ISPCON_CFGUEN_Msk;
000002  6801              LDR      r1,[r0,#0]
000004  2210              MOVS     r2,#0x10
000006  4391              BICS     r1,r1,r2
000008  6001              STR      r1,[r0,#0]
;;;82     }
00000a  4770              BX       lr
;;;83     
                          ENDP

                  |L3.12|
                          DCD      0x5000c000

                          AREA ||i.FMC_DisableLDUpdate||, CODE, READONLY, ALIGN=2

                  FMC_DisableLDUpdate PROC
;;;90       */
;;;91     void FMC_DisableLDUpdate(void)
000000  4802              LDR      r0,|L4.12|
;;;92     {
;;;93         FMC->ISPCON &= ~FMC_ISPCON_LDUEN_Msk;
000002  6801              LDR      r1,[r0,#0]
000004  2220              MOVS     r2,#0x20
000006  4391              BICS     r1,r1,r2
000008  6001              STR      r1,[r0,#0]
;;;94     }
00000a  4770              BX       lr
;;;95     
                          ENDP

                  |L4.12|
                          DCD      0x5000c000

                          AREA ||i.FMC_EnableAPUpdate||, CODE, READONLY, ALIGN=2

                  FMC_EnableAPUpdate PROC
;;;102      */
;;;103    void FMC_EnableAPUpdate(void)
000000  4802              LDR      r0,|L5.12|
;;;104    {
;;;105        FMC->ISPCON |= FMC_ISPCON_APUEN_Msk;
000002  6801              LDR      r1,[r0,#0]
000004  2208              MOVS     r2,#8
000006  4311              ORRS     r1,r1,r2
000008  6001              STR      r1,[r0,#0]
;;;106    }
00000a  4770              BX       lr
;;;107    
                          ENDP

                  |L5.12|
                          DCD      0x5000c000

                          AREA ||i.FMC_EnableConfigUpdate||, CODE, READONLY, ALIGN=2

                  FMC_EnableConfigUpdate PROC
;;;114      */
;;;115    void FMC_EnableConfigUpdate(void)
000000  4802              LDR      r0,|L6.12|
;;;116    {
;;;117        FMC->ISPCON |= FMC_ISPCON_CFGUEN_Msk;
000002  6801              LDR      r1,[r0,#0]
000004  2210              MOVS     r2,#0x10
000006  4311              ORRS     r1,r1,r2
000008  6001              STR      r1,[r0,#0]
;;;118    }
00000a  4770              BX       lr
;;;119    
                          ENDP

                  |L6.12|
                          DCD      0x5000c000

                          AREA ||i.FMC_EnableLDUpdate||, CODE, READONLY, ALIGN=2

                  FMC_EnableLDUpdate PROC
;;;126      */
;;;127    void FMC_EnableLDUpdate(void)
000000  4802              LDR      r0,|L7.12|
;;;128    {
;;;129        FMC->ISPCON |= FMC_ISPCON_LDUEN_Msk;
000002  6801              LDR      r1,[r0,#0]
000004  2220              MOVS     r2,#0x20
000006  4311              ORRS     r1,r1,r2
000008  6001              STR      r1,[r0,#0]
;;;130    }
00000a  4770              BX       lr
;;;131    
                          ENDP

                  |L7.12|
                          DCD      0x5000c000

                          AREA ||i.FMC_GetBootSource||, CODE, READONLY, ALIGN=2

                  FMC_GetBootSource PROC
;;;141      */
;;;142    int32_t FMC_GetBootSource(void)
000000  4803              LDR      r0,|L8.16|
;;;143    {
;;;144        if(FMC->ISPCON & FMC_ISPCON_BS_Msk)
000002  6800              LDR      r0,[r0,#0]
000004  0780              LSLS     r0,r0,#30
000006  d501              BPL      |L8.12|
;;;145            return 1;
000008  2001              MOVS     r0,#1
;;;146        else
;;;147            return 0;
;;;148    }
00000a  4770              BX       lr
                  |L8.12|
00000c  2000              MOVS     r0,#0                 ;147
00000e  4770              BX       lr
;;;149    
                          ENDP

                  |L8.16|
                          DCD      0x5000c000

                          AREA ||i.FMC_Open||, CODE, READONLY, ALIGN=2

                  FMC_Open PROC
;;;156      */
;;;157    void FMC_Open(void)
000000  4802              LDR      r0,|L9.12|
;;;158    {
;;;159        FMC->ISPCON |=  FMC_ISPCON_ISPEN_Msk;
000002  6801              LDR      r1,[r0,#0]
000004  2201              MOVS     r2,#1
000006  4311              ORRS     r1,r1,r2
000008  6001              STR      r1,[r0,#0]
;;;160    }
00000a  4770              BX       lr
;;;161    
                          ENDP

                  |L9.12|
                          DCD      0x5000c000

                          AREA ||i.FMC_Read||, CODE, READONLY, ALIGN=2

                  FMC_Read PROC
;;;124     */
;;;125    static __INLINE uint32_t FMC_Read(uint32_t u32addr)
000000  4906              LDR      r1,|L10.28|
;;;126    {
;;;127        FMC->ISPCMD = FMC_ISPCMD_READ; /* Set ISP Command Code */
000002  2200              MOVS     r2,#0
000004  60ca              STR      r2,[r1,#0xc]
;;;128        FMC->ISPADR = u32addr;         /* Set Target ROM Address. The address must be word alignment. */
000006  6048              STR      r0,[r1,#4]
;;;129        FMC->ISPTRG = 0x1;             /* Trigger to start ISP procedure */
000008  2001              MOVS     r0,#1
00000a  6108              STR      r0,[r1,#0x10]
;;;130        __ISB();                       /* To make sure ISP/CPU be Synchronized */
00000c  f3bf8f6f          ISB      
                  |L10.16|
;;;131        while(FMC->ISPTRG);            /* Waiting for ISP Done */
000010  6908              LDR      r0,[r1,#0x10]
000012  2800              CMP      r0,#0
000014  d1fc              BNE      |L10.16|
;;;132    
;;;133        return FMC->ISPDAT;
000016  6888              LDR      r0,[r1,#8]
;;;134    }
000018  4770              BX       lr
;;;135    
                          ENDP

00001a  0000              DCW      0x0000
                  |L10.28|
                          DCD      0x5000c000

                          AREA ||i.FMC_ReadConfig||, CODE, READONLY, ALIGN=1

                  FMC_ReadConfig PROC
;;;178      */
;;;179    int32_t FMC_ReadConfig(uint32_t *u32Config, uint32_t u32Count)
000000  b5f8              PUSH     {r3-r7,lr}
;;;180    {
000002  460e              MOV      r6,r1
000004  4607              MOV      r7,r0
;;;181        int32_t i;
;;;182    
;;;183        for(i = 0; i < u32Count; i++)
000006  2400              MOVS     r4,#0
000008  e007              B        |L11.26|
                  |L11.10|
;;;184            u32Config[i] = FMC_Read(FMC_CONFIG_BASE + i * 4);
00000a  2003              MOVS     r0,#3
00000c  00a5              LSLS     r5,r4,#2
00000e  0500              LSLS     r0,r0,#20
000010  1828              ADDS     r0,r5,r0
000012  f7fffffe          BL       FMC_Read
000016  5178              STR      r0,[r7,r5]
000018  1c64              ADDS     r4,r4,#1              ;183
                  |L11.26|
00001a  42b4              CMP      r4,r6                 ;183
00001c  d3f5              BCC      |L11.10|
;;;185    
;;;186        return 0;
00001e  2000              MOVS     r0,#0
;;;187    }
000020  bdf8              POP      {r3-r7,pc}
;;;188    
                          ENDP


                          AREA ||i.FMC_ReadDataFlashBaseAddr||, CODE, READONLY, ALIGN=2

                  FMC_ReadDataFlashBaseAddr PROC
;;;165      */
;;;166    uint32_t FMC_ReadDataFlashBaseAddr(void)
000000  4801              LDR      r0,|L12.8|
;;;167    {
;;;168        return FMC->DFBADR;
000002  6940              LDR      r0,[r0,#0x14]
;;;169    }
000004  4770              BX       lr
;;;170    
                          ENDP

000006  0000              DCW      0x0000
                  |L12.8|
                          DCD      0x5000c000

                          AREA ||i.FMC_SetBootSource||, CODE, READONLY, ALIGN=2

                  FMC_SetBootSource PROC
;;;41       */
;;;42     void FMC_SetBootSource(int32_t i32BootSrc)
000000  4904              LDR      r1,|L13.20|
;;;43     {
;;;44         if(i32BootSrc)
;;;45             FMC->ISPCON |= FMC_ISPCON_BS_Msk; /* Boot from LDROM */
000002  2202              MOVS     r2,#2
000004  2800              CMP      r0,#0                 ;44
;;;46         else
;;;47             FMC->ISPCON &= ~FMC_ISPCON_BS_Msk;/* Boot from APROM */
000006  6808              LDR      r0,[r1,#0]
000008  d001              BEQ      |L13.14|
00000a  4310              ORRS     r0,r0,r2              ;45
00000c  e000              B        |L13.16|
                  |L13.14|
00000e  4390              BICS     r0,r0,r2
                  |L13.16|
000010  6008              STR      r0,[r1,#0]            ;45
;;;48     }
000012  4770              BX       lr
;;;49     
                          ENDP

                  |L13.20|
                          DCD      0x5000c000

                          AREA ||i.FMC_WriteConfig||, CODE, READONLY, ALIGN=2

                  FMC_WriteConfig PROC
;;;203      */
;;;204    int32_t FMC_WriteConfig(uint32_t *u32Config, uint32_t u32Count)
000000  b5f3              PUSH     {r0,r1,r4-r7,lr}
;;;205    {
000002  b081              SUB      sp,sp,#4
000004  4607              MOV      r7,r0
;;;206        int32_t i;
;;;207    
;;;208        for(i = 0; i < u32Count; i++)
000006  2400              MOVS     r4,#0
000008  4d0f              LDR      r5,|L14.72|
00000a  e018              B        |L14.62|
                  |L14.12|
;;;209        {
;;;210            FMC_Write(FMC_CONFIG_BASE + i * 4, u32Config[i]);
00000c  00a6              LSLS     r6,r4,#2
00000e  2003              MOVS     r0,#3
000010  0500              LSLS     r0,r0,#20
000012  1830              ADDS     r0,r6,r0
000014  59b9              LDR      r1,[r7,r6]
000016  2221              MOVS     r2,#0x21
000018  60ea              STR      r2,[r5,#0xc]
00001a  6068              STR      r0,[r5,#4]
00001c  60a9              STR      r1,[r5,#8]
00001e  2101              MOVS     r1,#1
000020  6129              STR      r1,[r5,#0x10]
000022  f3bf8f6f          ISB      
                  |L14.38|
000026  6929              LDR      r1,[r5,#0x10]
000028  2900              CMP      r1,#0
00002a  d1fc              BNE      |L14.38|
;;;211            if(FMC_Read(FMC_CONFIG_BASE + i * 4) != u32Config[i])
00002c  f7fffffe          BL       FMC_Read
000030  59b9              LDR      r1,[r7,r6]
000032  4288              CMP      r0,r1
000034  d002              BEQ      |L14.60|
;;;212                return -1;
000036  2000              MOVS     r0,#0
000038  43c0              MVNS     r0,r0
;;;213        }
;;;214    
;;;215        return 0;
;;;216    }
00003a  bdfe              POP      {r1-r7,pc}
                  |L14.60|
00003c  1c64              ADDS     r4,r4,#1              ;208
                  |L14.62|
00003e  9802              LDR      r0,[sp,#8]            ;208
000040  4284              CMP      r4,r0                 ;208
000042  d3e3              BCC      |L14.12|
000044  2000              MOVS     r0,#0                 ;215
000046  bdfe              POP      {r1-r7,pc}
;;;217    
                          ENDP

                  |L14.72|
                          DCD      0x5000c000

;*** Start embedded assembler ***

#line 1 "..\\..\\..\\..\\Library\\StdDriver\\src\\fmc.c"
	AREA ||.rev16_text||, CODE, READONLY
	THUMB
	EXPORT |__asm___5_fmc_c_15679c7a____REV16|
#line 118 "..\\..\\..\\..\\Library\\CMSIS\\Include\\core_cmInstr.h"
|__asm___5_fmc_c_15679c7a____REV16| PROC
#line 119

 rev16 r0, r0
 bx lr
	ENDP
	AREA ||.revsh_text||, CODE, READONLY
	THUMB
	EXPORT |__asm___5_fmc_c_15679c7a____REVSH|
#line 132
|__asm___5_fmc_c_15679c7a____REVSH| PROC
#line 133

 revsh r0, r0
 bx lr
	ENDP

;*** End   embedded assembler ***
