; generated by ARM C/C++ Compiler, 5.03 [Build 24]
; commandline ArmCC [--list --split_sections --debug -c --asm --interleave -o.\obj\main.o --asm_dir=.\lst\ --list_dir=.\lst\ --depend=.\obj\main.d --cpu=Cortex-M0 --apcs=interwork -I.\ -I..\..\..\..\Library\CMSIS\Include -I..\..\..\..\Library\Device\Nuvoton\NUC200Series\Include -I..\..\..\..\Library\StdDriver\inc -IC:\Keil\ARM\RV31\INC -IC:\Keil\ARM\CMSIS\Include -IC:\Keil\ARM\Inc\?ST\STM32F10x -D__MICROLIB --omf_browse=.\obj\main.crf ..\main.c]
                          THUMB

                          AREA ||i.SYS_Init||, CODE, READONLY, ALIGN=2

                  SYS_Init PROC
;;;23     
;;;24     void SYS_Init(void)
000000  b570              PUSH     {r4-r6,lr}
;;;25     {
;;;26         
;;;27     /*---------------------------------------------------------------------------------------------------------*/
;;;28     /* Init System Clock                                                                                       */
;;;29     /*---------------------------------------------------------------------------------------------------------*/   
;;;30         
;;;31         /* Enable Internal RC 22.1184MHz clock */
;;;32         CLK_EnableXtalRC(CLK_PWRCON_OSC22M_EN_Msk);
000002  2004              MOVS     r0,#4
000004  f7fffffe          BL       CLK_EnableXtalRC
;;;33     
;;;34         /* Waiting for Internal RC clock ready */
;;;35         CLK_WaitClockReady(CLK_CLKSTATUS_OSC22M_STB_Msk);
000008  2010              MOVS     r0,#0x10
00000a  f7fffffe          BL       CLK_WaitClockReady
;;;36     
;;;37         /* Switch HCLK clock source to Internal RC and HCLK source divide 1 */
;;;38         CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HIRC, CLK_CLKDIV_HCLK(1));
00000e  2100              MOVS     r1,#0
000010  2007              MOVS     r0,#7
000012  f7fffffe          BL       CLK_SetHCLK
;;;39     
;;;40         /* Enable external XTAL 12MHz clock */
;;;41         CLK_EnableXtalRC(CLK_PWRCON_XTL12M_EN_Msk);
000016  2001              MOVS     r0,#1
000018  f7fffffe          BL       CLK_EnableXtalRC
;;;42         
;;;43         /* Waiting for external XTAL clock ready */
;;;44         CLK_WaitClockReady(CLK_CLKSTATUS_XTL12M_STB_Msk);
00001c  2001              MOVS     r0,#1
00001e  f7fffffe          BL       CLK_WaitClockReady
;;;45     
;;;46         /* Set Flash Access Delay */
;;;47         FMC->FATCON |= FMC_FATCON_FOMSEL1_Msk | FMC_FATCON_FOMSEL0_Msk;
000022  4813              LDR      r0,|L1.112|
000024  6981              LDR      r1,[r0,#0x18]
000026  2250              MOVS     r2,#0x50
000028  4311              ORRS     r1,r1,r2
00002a  6181              STR      r1,[r0,#0x18]
;;;48         
;;;49         /* Set core clock */
;;;50         CLK_SetCoreClock(72000000);
00002c  4811              LDR      r0,|L1.116|
00002e  f7fffffe          BL       CLK_SetCoreClock
;;;51         
;;;52         /* Enable UART, USBD module clock */
;;;53         CLK_EnableModuleClock(UART0_MODULE);
000032  4c11              LDR      r4,|L1.120|
000034  4620              MOV      r0,r4
000036  f7fffffe          BL       CLK_EnableModuleClock
;;;54         CLK_EnableModuleClock(USBD_MODULE);
00003a  4d10              LDR      r5,|L1.124|
00003c  4628              MOV      r0,r5
00003e  f7fffffe          BL       CLK_EnableModuleClock
;;;55         
;;;56         /* Select UART, USBD module clock source */
;;;57         CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UART_S_HXT, CLK_CLKDIV_UART(1));
000042  2200              MOVS     r2,#0
000044  4611              MOV      r1,r2
000046  4620              MOV      r0,r4
000048  f7fffffe          BL       CLK_SetModuleClock
;;;58         CLK_SetModuleClock(USBD_MODULE, 0, CLK_CLKDIV_USB(3));
00004c  2220              MOVS     r2,#0x20
00004e  2100              MOVS     r1,#0
000050  4628              MOV      r0,r5
000052  f7fffffe          BL       CLK_SetModuleClock
;;;59         
;;;60     /*---------------------------------------------------------------------------------------------------------*/
;;;61     /* Init I/O Multi-function                                                                                 */
;;;62     /*---------------------------------------------------------------------------------------------------------*/
;;;63     
;;;64         /* Set GPB multi-function pins for UART0 RXD and TXD, and Clock Output */
;;;65         SYS->GPB_MFP |=  (SYS_GPB_MFP_PB0_UART0_RXD | SYS_GPB_MFP_PB1_UART0_TXD | SYS_GPB_MFP_PB8_CLKO);
000056  2005              MOVS     r0,#5
000058  0700              LSLS     r0,r0,#28
00005a  6b41              LDR      r1,[r0,#0x34]
00005c  22ff              MOVS     r2,#0xff
00005e  3204              ADDS     r2,#4
000060  4311              ORRS     r1,r1,r2
000062  6341              STR      r1,[r0,#0x34]
;;;66         SYS->ALT_MFP |=  SYS_ALT_MFP_PB8_CLKO;
000064  4806              LDR      r0,|L1.128|
000066  6901              LDR      r1,[r0,#0x10]
000068  05c2              LSLS     r2,r0,#23
00006a  4311              ORRS     r1,r1,r2
00006c  6101              STR      r1,[r0,#0x10]
;;;67         
;;;68     }    
00006e  bd70              POP      {r4-r6,pc}
;;;69         
                          ENDP

                  |L1.112|
                          DCD      0x5000c000
                  |L1.116|
                          DCD      0x044aa200
                  |L1.120|
                          DCD      0x57803d10
                  |L1.124|
                          DCD      0x40003e1b
                  |L1.128|
                          DCD      0x50000040

                          AREA ||i.SYS_UnlockReg||, CODE, READONLY, ALIGN=2

                  SYS_UnlockReg PROC
;;;1402     */
;;;1403   static __INLINE void SYS_UnlockReg(void)
000000  b510              PUSH     {r4,lr}
;;;1404   {
;;;1405     while(SYS->REGWRPROT != SYS_REGWRPROT_REGPROTDIS_Msk) {
;;;1406       SYS->REGWRPROT = 0x59;
000002  2159              MOVS     r1,#0x59
;;;1407       SYS->REGWRPROT = 0x16;
000004  2316              MOVS     r3,#0x16
000006  4805              LDR      r0,|L2.28|
;;;1408       SYS->REGWRPROT = 0x88;  
000008  2288              MOVS     r2,#0x88
00000a  e002              B        |L2.18|
                  |L2.12|
00000c  6001              STR      r1,[r0,#0]            ;1406
00000e  6003              STR      r3,[r0,#0]            ;1407
000010  6002              STR      r2,[r0,#0]
                  |L2.18|
000012  6804              LDR      r4,[r0,#0]            ;1405
000014  2c01              CMP      r4,#1                 ;1405
000016  d1f9              BNE      |L2.12|
;;;1409     }
;;;1410   }
000018  bd10              POP      {r4,pc}
;;;1411   
                          ENDP

00001a  0000              DCW      0x0000
                  |L2.28|
                          DCD      0x50000100

                          AREA ||i.UART0_Init||, CODE, READONLY, ALIGN=2

                  UART0_Init PROC
;;;70     
;;;71     void UART0_Init(void)
000000  2005              MOVS     r0,#5
;;;72     {
;;;73         /*---------------------------------------------------------------------------------------------------------*/
;;;74         /* Init UART                                                                                               */
;;;75         /*---------------------------------------------------------------------------------------------------------*/
;;;76         /* Reset IP */
;;;77         SYS->IPRSTC2 |=  SYS_IPRSTC2_UART0_RST_Msk;
000002  0700              LSLS     r0,r0,#28
000004  68c2              LDR      r2,[r0,#0xc]
000006  2101              MOVS     r1,#1
000008  0409              LSLS     r1,r1,#16
00000a  430a              ORRS     r2,r2,r1
00000c  60c2              STR      r2,[r0,#0xc]
;;;78         SYS->IPRSTC2 &= ~SYS_IPRSTC2_UART0_RST_Msk;
00000e  68c2              LDR      r2,[r0,#0xc]
000010  438a              BICS     r2,r2,r1
000012  60c2              STR      r2,[r0,#0xc]
;;;79     
;;;80         /* Configure UART0 and set UART0 Baudrate */
;;;81         UART0->BAUD = UART_BAUD_MODE2 | UART_BAUD_MODE2_DIVIDER(__HXT, 115200);
000014  4803              LDR      r0,|L3.36|
000016  4902              LDR      r1,|L3.32|
000018  6241              STR      r1,[r0,#0x24]
;;;82         UART0->LCR = UART_WORD_LEN_8 | UART_PARITY_NONE | UART_STOP_BIT_1;
00001a  2103              MOVS     r1,#3
00001c  60c1              STR      r1,[r0,#0xc]
;;;83     }
00001e  4770              BX       lr
;;;84     
                          ENDP

                  |L3.32|
                          DCD      0x30000066
                  |L3.36|
                          DCD      0x40050000

                          AREA ||i.main||, CODE, READONLY, ALIGN=2

                  main PROC
;;;88     /*---------------------------------------------------------------------------------------------------------*/
;;;89     int32_t main (void)
000000  b57c              PUSH     {r2-r6,lr}
;;;90     {
;;;91         uint32_t au32Config[2];
;;;92     
;;;93         /* Unlock protected registers */
;;;94         SYS_UnlockReg();
000002  f7fffffe          BL       SYS_UnlockReg
;;;95         
;;;96         SYS_Init();
000006  f7fffffe          BL       SYS_Init
;;;97         UART0_Init();
00000a  f7fffffe          BL       UART0_Init
;;;98     
;;;99         printf("+-------------------------------------------------------+\n");
00000e  a02b              ADR      r0,|L4.188|
000010  f7fffffe          BL       __2printf
;;;100        printf("|          NnMicro USB MassStorage Sample Code          |\n");
000014  a038              ADR      r0,|L4.248|
000016  f7fffffe          BL       __2printf
;;;101        printf("+-------------------------------------------------------+\n");
00001a  a028              ADR      r0,|L4.188|
00001c  f7fffffe          BL       __2printf
;;;102    
;;;103        SYS_UnlockReg();
000020  f7fffffe          BL       SYS_UnlockReg
;;;104        /* Enable FMC ISP function */
;;;105        FMC_Open();
000024  f7fffffe          BL       FMC_Open
;;;106    
;;;107        /* Check if Data Flash Size is 64K. If not, to re-define Data Flash size and to enable Data Flash function */
;;;108        if (FMC_ReadConfig(au32Config, 2) < 0)
000028  2102              MOVS     r1,#2
00002a  4668              MOV      r0,sp
00002c  f7fffffe          BL       FMC_ReadConfig
;;;109            return -1;
000030  2500              MOVS     r5,#0
000032  43ed              MVNS     r5,r5
000034  2800              CMP      r0,#0                 ;108
000036  db16              BLT      |L4.102|
;;;110    
;;;111        if (((au32Config[0] & 0x01) == 1) || (au32Config[1] != DATA_FLASH_BASE) ) {
000038  9800              LDR      r0,[sp,#0]
00003a  2401              MOVS     r4,#1
00003c  07c0              LSLS     r0,r0,#31
00003e  0424              LSLS     r4,r4,#16
;;;112            FMC_EnableConfigUpdate();
;;;113            au32Config[0] &= ~0x1;
;;;114            au32Config[1] = DATA_FLASH_BASE;
;;;115            if (FMC_WriteConfig(au32Config, 2) < 0)
;;;116                return -1;
;;;117    
;;;118            FMC_ReadConfig(au32Config, 2);
;;;119            if (((au32Config[0] & 0x01) == 1) || (au32Config[1] != DATA_FLASH_BASE)) {
;;;120                printf("Error: Program Config Failed!\n");
;;;121                /* Disable FMC ISP function */
;;;122                FMC_Close();
;;;123                return -1;
;;;124            }
;;;125    
;;;126            /* Reset Chip to reload new CONFIG value */
;;;127            SYS->IPRSTC1 = SYS_IPRSTC1_CHIP_RST_Msk;
000040  2601              MOVS     r6,#1
000042  2800              CMP      r0,#0                 ;111
000044  d102              BNE      |L4.76|
000046  9801              LDR      r0,[sp,#4]            ;111
000048  42a0              CMP      r0,r4                 ;111
00004a  d021              BEQ      |L4.144|
                  |L4.76|
00004c  f7fffffe          BL       FMC_EnableConfigUpdate
000050  9800              LDR      r0,[sp,#0]            ;113
000052  2102              MOVS     r1,#2                 ;115
000054  0840              LSRS     r0,r0,#1              ;113
000056  0040              LSLS     r0,r0,#1              ;113
000058  9000              STR      r0,[sp,#0]            ;115
00005a  9401              STR      r4,[sp,#4]            ;115
00005c  4668              MOV      r0,sp                 ;115
00005e  f7fffffe          BL       FMC_WriteConfig
000062  2800              CMP      r0,#0                 ;115
000064  da01              BGE      |L4.106|
                  |L4.102|
000066  4628              MOV      r0,r5                 ;116
;;;128        }
;;;129    
;;;130        printf("NnMicro USB MassStorage Start!\n");
;;;131    
;;;132        USBD_Open(&gsInfo, MSC_ClassRequest, NULL);
;;;133        /* Endpoint configuration */
;;;134        MSC_Init();
;;;135        USBD_Start();
;;;136        NVIC_EnableIRQ(USBD_IRQn);
;;;137    
;;;138        while(1) {
;;;139            MSC_ProcessCmd();
;;;140            Flush();
;;;141        }
;;;142    }
000068  bd7c              POP      {r2-r6,pc}
                  |L4.106|
00006a  2102              MOVS     r1,#2                 ;118
00006c  4668              MOV      r0,sp                 ;118
00006e  f7fffffe          BL       FMC_ReadConfig
000072  9800              LDR      r0,[sp,#0]            ;119
000074  07c0              LSLS     r0,r0,#31             ;119
000076  d102              BNE      |L4.126|
000078  9801              LDR      r0,[sp,#4]            ;119
00007a  42a0              CMP      r0,r4                 ;119
00007c  d005              BEQ      |L4.138|
                  |L4.126|
00007e  a02d              ADR      r0,|L4.308|
000080  f7fffffe          BL       __2printf
000084  f7fffffe          BL       FMC_Close
000088  e7ed              B        |L4.102|
                  |L4.138|
00008a  2005              MOVS     r0,#5                 ;127
00008c  0700              LSLS     r0,r0,#28             ;127
00008e  6086              STR      r6,[r0,#8]            ;127
                  |L4.144|
000090  a030              ADR      r0,|L4.340|
000092  f7fffffe          BL       __2printf
000096  2200              MOVS     r2,#0                 ;132
000098  4936              LDR      r1,|L4.372|
00009a  4837              LDR      r0,|L4.376|
00009c  f7fffffe          BL       USBD_Open
0000a0  f7fffffe          BL       MSC_Init
0000a4  f7fffffe          BL       USBD_Start
0000a8  2001              MOVS     r0,#1                 ;135
0000aa  4934              LDR      r1,|L4.380|
0000ac  05c0              LSLS     r0,r0,#23             ;135
0000ae  6008              STR      r0,[r1,#0]            ;135
                  |L4.176|
0000b0  f7fffffe          BL       MSC_ProcessCmd
0000b4  f7fffffe          BL       Flush
0000b8  e7fa              B        |L4.176|
;;;143    
                          ENDP

0000ba  0000              DCW      0x0000
                  |L4.188|
0000bc  2b2d2d2d          DCB      "+------------------------------------------------------"
0000c0  2d2d2d2d
0000c4  2d2d2d2d
0000c8  2d2d2d2d
0000cc  2d2d2d2d
0000d0  2d2d2d2d
0000d4  2d2d2d2d
0000d8  2d2d2d2d
0000dc  2d2d2d2d
0000e0  2d2d2d2d
0000e4  2d2d2d2d
0000e8  2d2d2d2d
0000ec  2d2d2d2d
0000f0  2d2d2d  
0000f3  2d2b0a00          DCB      "-+\n",0
0000f7  00                DCB      0
                  |L4.248|
0000f8  7c202020          DCB      "|          NnMicro USB MassStorage Sample Code         "
0000fc  20202020
000100  2020204e
000104  6e4d6963
000108  726f2055
00010c  5342204d
000110  61737353
000114  746f7261
000118  67652053
00011c  616d706c
000120  6520436f
000124  64652020
000128  20202020
00012c  202020  
00012f  207c0a00          DCB      " |\n",0
000133  00                DCB      0
                  |L4.308|
000134  4572726f          DCB      "Error: Program Config Failed!\n",0
000138  723a2050
00013c  726f6772
000140  616d2043
000144  6f6e6669
000148  67204661
00014c  696c6564
000150  210a00  
000153  00                DCB      0
                  |L4.340|
000154  4e6e4d69          DCB      "NnMicro USB MassStorage Start!\n",0
000158  63726f20
00015c  55534220
000160  4d617373
000164  53746f72
000168  61676520
00016c  53746172
000170  74210a00
                  |L4.372|
                          DCD      MSC_ClassRequest
                  |L4.376|
                          DCD      gsInfo
                  |L4.380|
                          DCD      0xe000e100

;*** Start embedded assembler ***

#line 1 "..\\main.c"
	AREA ||.rev16_text||, CODE, READONLY
	THUMB
	EXPORT |__asm___6_main_c_SYS_Init____REV16|
#line 118 "..\\..\\..\\..\\Library\\CMSIS\\Include\\core_cmInstr.h"
|__asm___6_main_c_SYS_Init____REV16| PROC
#line 119

 rev16 r0, r0
 bx lr
	ENDP
	AREA ||.revsh_text||, CODE, READONLY
	THUMB
	EXPORT |__asm___6_main_c_SYS_Init____REVSH|
#line 132
|__asm___6_main_c_SYS_Init____REVSH| PROC
#line 133

 revsh r0, r0
 bx lr
	ENDP

;*** End   embedded assembler ***

                  __ARM_use_no_argv EQU 0
