; generated by ARM C/C++ Compiler, 5.03 [Build 24]
; commandline ArmCC [--list --split_sections --debug -c --asm --interleave -o.\obj\system_nuc200series.o --asm_dir=.\lst\ --list_dir=.\lst\ --depend=.\obj\system_nuc200series.d --cpu=Cortex-M0 --apcs=interwork -I.\ -I..\..\..\..\Library\CMSIS\Include -I..\..\..\..\Library\Device\Nuvoton\NUC200Series\Include -I..\..\..\..\Library\StdDriver\inc -IC:\Keil\ARM\RV31\INC -IC:\Keil\ARM\CMSIS\Include -IC:\Keil\ARM\Inc\?ST\STM32F10x -D__MICROLIB --omf_browse=.\obj\system_nuc200series.crf ..\..\..\..\Library\Device\Nuvoton\NUC200Series\Source\system_NUC200Series.c]
                          THUMB

                          AREA ||i.SystemCoreClockUpdate||, CODE, READONLY, ALIGN=2

                  SystemCoreClockUpdate PROC
;;;23      *----------------------------------------------------------------------------*/
;;;24     void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
000000  b538              PUSH     {r3-r5,lr}
000002  a01d              ADR      r0,|L1.120|
000004  6800              LDR      r0,[r0,#0]
000006  4c1d              LDR      r4,|L1.124|
000008  9000              STR      r0,[sp,#0]
00000a  6a21              LDR      r1,[r4,#0x20]
00000c  1320              ASRS     r0,r4,#12
00000e  4201              TST      r1,r0
;;;25     {
000010  d001              BEQ      |L1.22|
000012  2000              MOVS     r0,#0
000014  e016              B        |L1.68|
                  |L1.22|
000016  0308              LSLS     r0,r1,#12
000018  d501              BPL      |L1.30|
00001a  4819              LDR      r0,|L1.128|
00001c  e000              B        |L1.32|
                  |L1.30|
00001e  4819              LDR      r0,|L1.132|
                  |L1.32|
000020  038a              LSLS     r2,r1,#14
000022  d40f              BMI      |L1.68|
000024  040a              LSLS     r2,r1,#16
000026  0f92              LSRS     r2,r2,#30
000028  466b              MOV      r3,sp
00002a  5c9b              LDRB     r3,[r3,r2]
00002c  05ca              LSLS     r2,r1,#23
00002e  0489              LSLS     r1,r1,#18
000030  0dd2              LSRS     r2,r2,#23
000032  0ec9              LSRS     r1,r1,#27
000034  1c92              ADDS     r2,r2,#2
000036  1c89              ADDS     r1,r1,#2
000038  0880              LSRS     r0,r0,#2
00003a  4359              MULS     r1,r3,r1
00003c  4350              MULS     r0,r2,r0
00003e  f7fffffe          BL       __aeabi_uidivmod
000042  0080              LSLS     r0,r0,#2
                  |L1.68|
;;;26         uint32_t u32Freq, u32ClkSrc;
;;;27         uint32_t u32HclkDiv;
;;;28     
;;;29         /* Update PLL Clock */
;;;30         PllClock = CLK_GetPLLClockFreq();
000044  4d10              LDR      r5,|L1.136|
;;;31      
;;;32         u32ClkSrc = CLK->CLKSEL0 & CLK_CLKSEL0_HCLK_S_Msk;
000046  60a8              STR      r0,[r5,#8]  ; PllClock
000048  6921              LDR      r1,[r4,#0x10]
00004a  0749              LSLS     r1,r1,#29
00004c  0f49              LSRS     r1,r1,#29
;;;33     
;;;34         if(u32ClkSrc != CLK_CLKSEL0_HCLK_S_PLL)
00004e  2902              CMP      r1,#2
000050  d003              BEQ      |L1.90|
;;;35         {
;;;36             /* Use the clock sources directly */
;;;37             u32Freq = gau32ClkSrcTbl[u32ClkSrc];
000052  0088              LSLS     r0,r1,#2
000054  4629              MOV      r1,r5
000056  310c              ADDS     r1,r1,#0xc
000058  5808              LDR      r0,[r1,r0]
                  |L1.90|
;;;38         }
;;;39         else
;;;40         {
;;;41             /* Use PLL clock */
;;;42             u32Freq = PllClock;
;;;43         }
;;;44      
;;;45         u32HclkDiv = (CLK->CLKDIV & CLK_CLKDIV_HCLK_N_Msk) + 1; 
00005a  69a1              LDR      r1,[r4,#0x18]
00005c  0709              LSLS     r1,r1,#28
00005e  0f09              LSRS     r1,r1,#28
000060  1c49              ADDS     r1,r1,#1
;;;46         
;;;47         /* Update System Core Clock */
;;;48         SystemCoreClock = u32Freq/u32HclkDiv;
000062  f7fffffe          BL       __aeabi_uidivmod
;;;49     
;;;50         CyclesPerUs = (SystemCoreClock + 500000) / 1000000;
000066  4909              LDR      r1,|L1.140|
000068  6028              STR      r0,[r5,#0]  ; SystemCoreClock
00006a  104a              ASRS     r2,r1,#1
00006c  1880              ADDS     r0,r0,r2
00006e  f7fffffe          BL       __aeabi_uidivmod
000072  6068              STR      r0,[r5,#4]  ; CyclesPerUs
;;;51     }
000074  bd38              POP      {r3-r5,pc}
;;;52     
                          ENDP

000076  0000              DCW      0x0000
                  |L1.120|
000078  01020204          DCB      1,2,2,4
                  |L1.124|
                          DCD      0x50000200
                  |L1.128|
                          DCD      0x01518000
                  |L1.132|
                          DCD      0x00b71b00
                  |L1.136|
                          DCD      ||.data||
                  |L1.140|
                          DCD      0x000f4240

                          AREA ||i.SystemInit||, CODE, READONLY, ALIGN=1

                  SystemInit PROC
;;;65     /*---------------------------------------------------------------------------------------------------------*/
;;;66     void SystemInit (void)
000000  4770              BX       lr
;;;67     {
;;;68     }
                          ENDP


                          AREA ||.data||, DATA, ALIGN=2

                  SystemCoreClock
                          DCD      0x02faf080
                  CyclesPerUs
                          DCD      0x00000032
                  PllClock
                          DCD      0x02faf080
                  gau32ClkSrcTbl
                          DCD      0x00b71b00
                          DCD      0x00008000
                          DCD      0x02faf080
                          DCD      0x00002710
                          DCD      0x00000000
                          DCD      0x00000000
                          DCD      0x00000000
                          DCD      0x01518000

;*** Start embedded assembler ***

#line 1 "..\\..\\..\\..\\Library\\Device\\Nuvoton\\NUC200Series\\Source\\system_NUC200Series.c"
	AREA ||.rev16_text||, CODE, READONLY
	THUMB
	EXPORT |__asm___21_system_NUC200Series_c_5d646a67____REV16|
#line 118 "..\\..\\..\\..\\Library\\CMSIS\\Include\\core_cmInstr.h"
|__asm___21_system_NUC200Series_c_5d646a67____REV16| PROC
#line 119

 rev16 r0, r0
 bx lr
	ENDP
	AREA ||.revsh_text||, CODE, READONLY
	THUMB
	EXPORT |__asm___21_system_NUC200Series_c_5d646a67____REVSH|
#line 132
|__asm___21_system_NUC200Series_c_5d646a67____REVSH| PROC
#line 133

 revsh r0, r0
 bx lr
	ENDP

;*** End   embedded assembler ***
